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8523agi-03 www.icst.com/products/hiperclocks.html rev. a september 13, 2004 1 integrated circuit systems, inc. ics8523i-03 l ow s kew , 1- to -4 d ifferential - to -lvhstl f anout b uffer b lock d iagram p in a ssignment ics8523i-03 20-lead tssop 6.5mm x 4.4mm x 0.92mm body package g package top view gnd clk_en clk_sel clk0 nclk0 clk1 nclk1 nc nc v dd 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 q0 nq0 v ddo q1 nq1 q2 nq2 v ddo q3 nq3 g eneral d escription the ics8523i-03 is a low skew, high perfor- mance 1-to-4 differential-to-lvhstl fanout buffer and a member of the hipercloc ks? f amily of high performance clock solutions from ics. the ics8523i-03 has two selectable clock inputs. the input pairs can accept most standard differential input levels. the clock enable is internally synchronized to eliminate runt pulses on the outputs during asynchronous assertion/deassertion of the clock enable pin. guaranteed output and part-to-part skew characteristics make the ics8523i-03 ideal for those applications demand- ing well defined performance and repeatability. f eatures ? 4 differential lvhstl compatible outputs ? selectable differential clk0, nclk0 and clk1, nclk1 clock inputs ? clock input pairs can accept the following differential input levels: lvds, lvpecl, lvhstl, sstl, hcsl ? maximum output frequency: 650mhz ? translates any single-ended input signal to lvhstl levels with resistor bias on nclk input ? output skew: 50ps (maximum) ? part-to-part skew: 400ps (maximum) ? propagation delay: 1.2ns (typical) ? v oh = 1v (maximum) ? 3.3v core, 1.8v output operating supply ? lead-free package available ? -40c to 85c ambient operating temperature hiperclocks? ics clk0 nclk0 clk1 nclk1 q0 nq0 q1 nq1 q2 nq2 q3 nq3 0 1 clk_en clk_sel d q le
8523agi-03 www.icst.com/products/hiperclocks.html rev. a september 13, 2004 2 integrated circuit systems, inc. ics8523i-03 l ow s kew , 1- to -4 d ifferential - to -lvhstl f anout b uffer t able 1. p in d escriptions t able 2. p in c haracteristics l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u c n i e c n a t i c a p a c t u p n i 4f p r p u l l u p r o t s i s e r p u l l u p t u p n i 1 5k ? r n w o d l l u p r o t s i s e r n w o d l l u p t u p n i 1 5k ? r e b m u ne m a ne p y tn o i t p i r c s e d 1d n gr e w o p. d n u o r g y l p p u s r e w o p 2n e _ k l ct u p n ip u l l u p k c o l c w o l l o f s t u p t u o k c o l c , h g i h n e h w . e l b a n e k c o l c g n i z i n o r h c n y s d e c r o f e r a s t u p t u o q n , w o l d e c r o f e r a s t u p t u o q , w o l n e h w . t u p n i . s l e v e l e c a f r e t n i l t t v l / s o m c v l . h g i h 3l e s _ k l ct u p n in w o d l l u p 1 k l c n , 1 k l c l a i t n e r e f f i d s t c e l e s , h g i h n e h w . t u p n i t c e l e s k c o l c . s t u p n i 0 k l c n , 0 k l c s t c e l e s , w o l n e h w . s t u p n i . s l e v e l e c a f r e t n i l t t v l / s o m c v l 40 k l ct u p n in w o d l l u p. t u p n i k c o l c l a i t n e r e f f i d g n i t r e v n i - n o n 50 k l c nt u p n ip u l l u p. t u p n i k c o l c l a i t n e r e f f i d g n i t r e v n i 61 k l ct u p n in w o d l l u p. t u p n i k c o l c l a i t n e r e f f i d g n i t r e v n i - n o n 71 k l c nt u p n ip u l l u p. t u p n i k c o l c l a i t n e r e f f i d g n i t r e v n i 9 , 8c nd e s u n u. t c e n n o c o n 0 1v d d r e w o p. n i p y l p p u s e r o c 2 1 , 1 13 q , 3 q nt u p t u o. s l e v e l e c a f r e t n i l t s h v l . r i a p t u p t u o l a i t n e r e f f i d 8 1 , 3 1v o d d r e w o p. s n i p y l p p u s t u p t u o 5 1 , 4 12 q , 2 q nt u p t u o. s l e v e l e c a f r e t n i l t s h v l . r i a p t u p t u o l a i t n e r e f f i d 7 1 , 6 11 q , 1 q nt u p t u o. s l e v e l e c a f r e t n i l t s h v l . r i a p t u p t u o l a i t n e r e f f i d 0 2 , 9 10 q , 0 q nt u p t u o. s l e v e l e c a f r e t n i l t s h v l . r i a p t u p t u o l a i t n e r e f f i d : e t o n p u l l u p d n a n w o d l l u p . s e u l a v l a c i p y t r o f , s c i t s i r e t c a r a h c n i p , 2 e l b a t e e s . s r o t s i s e r t u p n i l a n r e t n i o t r e f e r
8523agi-03 www.icst.com/products/hiperclocks.html rev. a september 13, 2004 3 integrated circuit systems, inc. ics8523i-03 l ow s kew , 1- to -4 d ifferential - to -lvhstl f anout b uffer t able 3a. c ontrol i nput f unction t able t able 3b. c lock i nput f unction t able s t u p n is t u p t u o e d o m t u p t u o o t t u p n iy t i r a l o p 1 k l c r o 0 k l c1 k l c n r o 0 k l c n3 q : 0 q3 q n : 0 q n 00w o lh g i hl a i t n e r e f f i d o t l a i t n e r e f f i dg n i t r e v n i n o n 11 h g i hw o ll a i t n e r e f f i d o t l a i t n e r e f f i dg n i t r e v n i n o n 01 e t o n ; d e s a i bw o lh g i hl a i t n e r e f f i d o t d e d n e e l g n i sg n i t r e v n i n o n 11 e t o n ; d e s a i bh g i hw o ll a i t n e r e f f i d o t d e d n e e l g n i sg n i t r e v n i n o n 1 e t o n ; d e s a i b0h g i hw o ll a i t n e r e f f i d o t d e d n e e l g n i sg n i t r e v n i 1 e t o n ; d e s a i b1w o lh g i hl a i t n e r e f f i d o t d e d n e e l g n i sg n i t r e v n i . " s l e v e l d e d n e e l g n i s t p e c c a o t t u p n i l a i t n e r e f f i d e h t g n i r i w " , n o i t c e s n o i t a m r o f n i n o i t a c i l p p a e h t o t r e f e r e s a e l p : 1 e t o n f igure 1. clk_en t iming d iagram enabled disabled nclk0, nclk1 clk0, clk1 clk_en nq0:nq3 q0:q3 s t u p n is t u p t u o n e _ k l cl e s _ k l ce c r u o s d e t c e l e s3 q : 0 q3 q n : 0 q n 00 0 k l c n , 0 k l cw o l ; d e l b a s i dh g i h ; d e l b a s i d 01 1 k l c n , 1 k l cw o l ; d e l b a s i dh g i h ; d e l b a s i d 10 0 k l c n , 0 k l cd e l b a n ed e l b a n e 11 1 k l c n , 1 k l cd e l b a n ed e l b a n e e g d e k c o l c t u p n i g n i l l a f d n a g n i s i r a g n i w o l l o f d e l b a n e r o d e l b a s i d e r a s t u p t u o k c o l c e h t , s e h c t i w s n e _ k l c r e t f a . 1 e r u g i f n i n w o h s s a d e b i r c s e d s a s t u p n i 1 k l c n , 1 k l c d n a 0 k l c n , 0 k l c e h t f o n o i t c n u f a e r a s t u p t u o e h t f o e t a t s e h t , e d o m e v i t c a e h t n i . b 3 e l b a t n i
8523agi-03 www.icst.com/products/hiperclocks.html rev. a september 13, 2004 4 integrated circuit systems, inc. ics8523i-03 l ow s kew , 1- to -4 d ifferential - to -lvhstl f anout b uffer t able 4a. p ower s upply dc c haracteristics , v dd = 3.3v5%, v ddo = 1.8v0.2v, t a = -40c to 85c t able 4b. lvcmos / lvttl dc c haracteristics , v dd = 3.3v5%, v ddo = 1.8v0.2v, t a = -40c to 85c t able 4c. d ifferential dc c haracteristics , v dd = 3.3v5%, v ddo = 1.8v0.2v, t a = -40c to 85c l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u v d d e g a t l o v y l p p u s e r o c 5 3 1 . 33 . 35 6 4 . 3v v o d d e g a t l o v y l p p u s r e w o p t u p t u o6 . 18 . 10 . 2v i d d t n e r r u c y l p p u s r e w o p 5 5a m l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u v h i e g a t l o v h g i h t u p n il e s _ k l c , n e _ k l c2v d d 3 . 0 +v v l i e g a t l o v w o l t u p n il e s _ k l c , n e _ k l c3 . 0 -8 . 0v i h i t n e r r u c h g i h t u p n i n e _ k l cv d d v = n i v 5 6 4 . 3 =5a l e s _ k l cv d d v = n i v 5 6 4 . 3 =0 5 1a i l i t n e r r u c w o l t u p n i n e _ k l cv d d v , v 5 6 4 . 3 = n i v 0 =0 5 1 -a l e s _ k l cv d d v , v 5 6 4 . 3 = n i v 0 =5 -a l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u i h i t n e r r u c h g i h t u p n i 1 k l c n , 0 k l c nv d d v = n i v 5 6 4 . 3 =5a 1 k l c , 0 k l cv d d v = n i v 5 6 4 . 3 =0 5 1a i l i t n e r r u c w o l t u p n i 1 k l c n , 0 k l c nv d d v , v 5 6 4 . 3 = n i v 0 =0 5 1 -a 1 k l c , 0 k l cv d d v , v 5 6 4 . 3 = n i v 0 =5 -a v p p e g a t l o v t u p n i k a e p - o t - k a e p 5 1 . 03 . 1v v r m c ; e g a t l o v t u p n i e d o m n o m m o c 2 , 1 e t o n 5 . 0v d d 5 8 . 0 -v v s i 1 k l c n , 1 k l c d n a 0 k l c n , 0 k l c r o f e g a t l o v t u p n i m u m i x a m e h t s n o i t a c i l p p a d e d n e e l g n i s r o f : 1 e t o n d d . v 3 . 0 + v s a d e n i f e d s i e g a t l o v e d o m n o m m o c : 2 e t o n h i . a bsolute m aximum r atings supply voltage, v cc 4.6v inputs, v i -0.5v to v cc + 0.5v outputs, i o continuous current 50ma surge current 100ma package thermal impedance, ja 73.2c/w (0 lfpm) storage temperature, t stg -65c to 150c note: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these ratings are stress specifications only. functional operation of product at these conditions or any conditions be- yond those listed in the dc characteristics or ac character- istics is not implied. exposure to absolute maximum rating conditions for extended periods may affect product reliability.
8523agi-03 www.icst.com/products/hiperclocks.html rev. a september 13, 2004 5 integrated circuit systems, inc. ics8523i-03 l ow s kew , 1- to -4 d ifferential - to -lvhstl f anout b uffer t able 5. ac c haracteristics , v dd = 3.3v5%, v ddo = 1.8v0.2v, t a = -40c to 85c l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u f x a m y c n e u q e r f t u p t u o m u m i x a m 0 5 6z h m t d p 1 e t o n ; y a l e d n o i t a g a p o r p? z h m 0 5 69 . 02 . 15 . 1s n t ) o ( k s4 , 2 e t o n ; w e k s t u p t u o 0 5s p t ) p p ( k s4 , 3 e t o n ; w e k s t r a p - o t - t r a p 0 0 4s p t r /t f e m i t l l a f / e s i r t u p t u o% 0 8 o t % 0 20 5 10 0 5s p c d oe l c y c y t u d t u p t u o z h m 0 0 2 > ?5 40 55 5% ? z h m 0 0 28 42 5% . e s i w r e h t o d e t o n s s e l n u z h m 0 0 5 t a d e r u s a e m s r e t e m a r a p l l a . r e t t i j d d a t o n s e o d t r a p e h t . t u p t u o e h t n o r e t t i j e h t l a u q e l l i w t u p n i e h t n o r e t t i j e l c y c o t e l c y c e h t . t n i o p g n i s s o r c t u p t u o l a i t n e r e f f i d e h t o t t n i o p g n i s s o r c t u p n i l a i t n e r e f f i d e h t m o r f d e r u s a e m : 1 e t o n . s n o i t i d n o c d a o l l a u q e h t i w d n a e g a t l o v y l p p u s e m a s e h t t a s t u p t u o n e e w t e b w e k s s a d e n i f e d : 2 e t o n . s t n i o p s s o r c l a i t n e r e f f i d t u p t u o t a d e r u s a e m s e g a t l o v y l p p u s e m a s e h t t a g n i t a r e p o s e c i v e d t n e r e f f i d n o s t u p t u o n e e w t e b w e k s s a d e n i f e d : 3 e t o n d e r u s a e m e r a s t u p t u o e h t , e c i v e d h c a e n o s t u p n i f o e p y t e m a s e h t g n i s u . s n o i t i d n o c d a o l l a u q e h t i w d n a . s t n i o p s s o r c l a i t n e r e f f i d e h t t a . 5 6 d r a d n a t s c e d e j h t i w e c n a d r o c c a n i d e n i f e d s i r e t e m a r a p s i h t : 4 e t o n t able 4d. lvhstl dc c haracteristics , v dd = 3.3v5%, v ddo = 1.8v0.2v, t a = -40c to 85c l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u v h o 1 e t o n ; e g a t l o v h g i h t u p t u o 7 . 00 . 1v v l o 1 e t o n ; e g a t l o v w o l t u p t u o 04 . 0v v g n i w s g n i w s e g a t l o v t u p t u o k a e p - o t - k a e p 4 . 00 . 1v 0 5 h t i w d e t a n i m r e t s t u p t u o : 1 e t o n ? . d n u o r g o t
8523agi-03 www.icst.com/products/hiperclocks.html rev. a september 13, 2004 6 integrated circuit systems, inc. ics8523i-03 l ow s kew , 1- to -4 d ifferential - to -lvhstl f anout b uffer p arameter m easurement i nformation p art - to -p art s kew p ropagation d elay o utput r ise /f all t ime clock outputs 20% 80% 80% 20% t r t f v od t sk(o) nqx qx nqy qy d ifferential i nput l evel o utput s kew 3.3v c ore /1.8v o utput l oad ac t est c ircuit scope lvhstl qx nqx v cmr cross points v pp gnd clk0, clk1 nclk0, nclk1 v dd t sk(pp) nqx qx nqy qy part 1 part 2 nclk0, nclk1 clk0, clk1 nq0:nq3 q0:q3 t pd v dd gnd = 0v 3.3v 5% v ddo 1.8v 0.2v o utput d uty c ycle /p ulse w idth /p eriod pulse width t period t pw t period odc = nq0:nq3 q0:q3
8523agi-03 www.icst.com/products/hiperclocks.html rev. a september 13, 2004 7 integrated circuit systems, inc. ics8523i-03 l ow s kew , 1- to -4 d ifferential - to -lvhstl f anout b uffer a pplication i nformation figure 2 shows how the differential input can be wired to accept single ended levels. the reference voltage v_ref = v dd /2 is generated by the bias resistors r1, r2 and c1. this bias circuit should be located as close as possible to the input pin. the ratio f igure 2. s ingle e nded s ignal d riving d ifferential i nput w iring the d ifferential i nput to a ccept s ingle e nded l evels of r1 and r2 might need to be adjusted to position the v_ref in the center of the input voltage swing. for example, if the input clock swing is only 2.5v and v dd = 3.3v, v_ref should be 1.25v and r2/r1 = 0.609. v_ref r1 1k c1 0.1u r2 1k single ended clock input clkx nclkx vdd
8523agi-03 www.icst.com/products/hiperclocks.html rev. a september 13, 2004 8 integrated circuit systems, inc. ics8523i-03 l ow s kew , 1- to -4 d ifferential - to -lvhstl f anout b uffer f igure 3c. h i p er c lock s clk/nclk i nput d riven by 3.3v lvpecl d river f igure 3b. h i p er c lock s clk/nclk i nput d riven by 3.3v lvpecl d river f igure 3d. h i p er c lock s clk/nclk i nput d riven by 3.3v lvds d river 3.3v r1 50 r3 50 zo = 50 ohm lvpecl zo = 50 ohm hiperclocks clk nclk 3.3v input r2 50 zo = 50 ohm input hiperclocks clk nclk 3.3v r3 125 r2 84 zo = 50 ohm 3.3v r4 125 lvpecl r1 84 3.3v d ifferential c lock i nput i nterface the clk /nclk accepts lvds, lvpecl, lvhstl, sstl, hcsl and other differential signals. both v swing and v oh must meet the v pp and v cmr input requirements. figures 3a to 3e show inter- face examples for the hiperclocks clk/nclk input driven by the most common driver types. the input interfaces suggested f igure 3a. h i p er c lock s clk/nclk i nput d riven by ics h i p er c lock s lvhstl d river here are examples only. please consult with the vendor of the driver component to confirm the driver termination requirements. for example in figure 4a, the input termination applies for ics hiperclocks lvhstl drivers. if you are using an lvhstl driver from another vendor, use their termination recommendation. 1.8v r2 50 input lvhstl driver ics hiperclocks r1 50 lvhstl 3.3v zo = 50 ohm zo = 50 ohm hiperclocks clk nclk f igure 3e. h i p er c lock s clk/ n clk i nput d riven by 3.3v lvpecl d river with ac c ouple zo = 50 ohm r3 125 hiperclocks clk nclk 3.3v r5 100 - 200 3.3v r2 84 3.3v r6 100 - 200 input r5,r6 locate near the driver pin. zo = 50 ohm r1 84 r4 125 c2 lvpecl c1 zo = 50 ohm r1 100 3.3v lvds_driv er zo = 50 ohm receiv er clk nclk 3.3v
8523agi-03 www.icst.com/products/hiperclocks.html rev. a september 13, 2004 9 integrated circuit systems, inc. ics8523i-03 l ow s kew , 1- to -4 d ifferential - to -lvhstl f anout b uffer zo = 50 + - c2 0.1u zo = 50 c1 0.1u zo = 50 r5 50 r2 50 r8 50 + - r1 50 r3 50 r12 1k + - r4 50 r9 50 zo = 50 ohm 3.3v zo = 50 ohm r7 50 r10 50 zo = 50 r6 50 3.3v + - 1.8v zo = 50 lvhstl driver c3 0.1u 1.8v 1.8v zo = 50 zo = 50 u1 ics8523-03 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 20 19 18 17 gnd clk_en clk_sel clk0 nclk0 clk1 nclk1 nc nc vdd nq3 q3 vddo nq2 q2 nq1 q0 nq0 vddo q1 1.8v zo = 50 r11 1k s chematic e xample this application note provides general design guide using ics8523i-03 lvhstl buffer. figure 3 shows a schematic ex- ample of the ics8523i-03 lvhstl clock buffer. in this example, f igure 4. e xample ics8523i-03 lvhstl c lock o utput b uffer s chematic the input is driven by an lvhstl driver. clk_en is set at logic low to select clk0/nclk0 input.
8523agi-03 www.icst.com/products/hiperclocks.html rev. a september 13, 2004 10 integrated circuit systems, inc. ics8523i-03 l ow s kew , 1- to -4 d ifferential - to -lvhstl f anout b uffer p ower c onsiderations this section provides information on power dissipation and junction temperature for the ics8523i-03. equations and example calculations are also provided. 1. power dissipation. the total power dissipation for the ics8523i-03 is the sum of the core power plus the power dissipated in the load(s). the following is the power dissipation for v dd = 3.3v + 5% = 3.465v, which gives worst case results. note: please refer to section 3 for details on calculating power dissipated in the load. ? power (core) max = v dd_max * i dd_max = 3.465v * 55ma = 190mw ? power (outputs) max = 32.8mw/loaded output pair if all outputs are loaded, the total power is 4 * 32.8mw = 131mw total power _max (3.465v, with all outputs switching) = 190mw + 131mw = 321mw 2. junction temperature. junction temperature, tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. the maximum recommended junction temperature for hiperclocks tm devices is 125c. the equation for tj is as follows: tj = ja * pd_total + t a tj = junction temperature ja = junction-to-ambient thermal resistance pd_total = total device power dissipation (example calculation is in section 1 above) t a = ambient temperature in order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance ja must be used. assuming a moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 66.6c/w per table 6 below. therefore, tj for an ambient temperature of 85c with all outputs switching is: 85c + 0.321w * 66.6c/w = 106.4c. this is well below the limit of 125c. this calculation is only an example. tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow , and the type of board (single layer or multi-layer). ja by velocity (linear feet per minute) 0 200 500 single-layer pcb, jedec standard test boards 114.5c/w 98.0c/w 88.0c/w multi-layer pcb, jedec standard test boards 73.2c/w 66.6c/w 63.5c/w note: most modern pcb designs use multi-layered boards. the data in the second row pertains to most designs. t able 6. t hermal r esistance ja for 20- pin tssop, f orced c onvection
8523agi-03 www.icst.com/products/hiperclocks.html rev. a september 13, 2004 11 integrated circuit systems, inc. ics8523i-03 l ow s kew , 1- to -4 d ifferential - to -lvhstl f anout b uffer 3. calculations and equations. the purpose of this section is to derive the power dissipated into the load. lvhstl output driver circuit and termination are shown in figure 5. t o calculate worst case power dissipation into the load, use the following equations which assume a 50 ? load. pd_h is power dissipation when the output drives high. pd_l is the power dissipation when the output drives low. pd_h = (v oh_max /r l ) * (v ddo_max - v oh_max ) pd_l = (v ol_max /r l ) * (v ddo_max - v ol_max ) pd_h = (1v/50 ? ) * (2v - 1v) = 20mw pd_l = (0.4v/50 ? ) * (2v - 0.4v) = 12.8mw total power dissipation per output pair = pd_h + pd_l = 32.8mw f igure 5. lvhstl d river c ircuit and t ermination v ddo v out rl 50 ? q1
8523agi-03 www.icst.com/products/hiperclocks.html rev. a september 13, 2004 12 integrated circuit systems, inc. ics8523i-03 l ow s kew , 1- to -4 d ifferential - to -lvhstl f anout b uffer r eliability i nformation t ransistor c ount the transistor count for ics8523i-03 is: 472 t able 7. ja vs . a ir f low t able for 20 l ead tssop ja by velocity (linear feet per minute) 0 200 500 single-layer pcb, jedec standard test boards 114.5c/w 98.0c/w 88.0c/w multi-layer pcb, jedec standard test boards 73.2c/w 66.6c/w 63.5c/w note: most modern pcb designs use multi-layered boards. the data in the second row pertains to most designs.
8523agi-03 www.icst.com/products/hiperclocks.html rev. a september 13, 2004 13 integrated circuit systems, inc. ics8523i-03 l ow s kew , 1- to -4 d ifferential - to -lvhstl f anout b uffer p ackage o utline - g s uffix for 20 l ead tssop t able 8. p ackage d imensions reference document: jedec publication 95, ms-153 l o b m y s s r e t e m i l l i m m u m i n i mm u m i x a m n0 2 a- -0 2 . 1 1 a5 0 . 05 1 . 0 2 a0 8 . 05 0 . 1 b9 1 . 00 3 . 0 c9 0 . 00 2 . 0 d0 4 . 60 6 . 6 ec i s a b 0 4 . 6 1 e0 3 . 40 5 . 4 ec i s a b 5 6 . 0 l5 4 . 05 7 . 0 0 8 a a a- -0 1 . 0
8523agi-03 www.icst.com/products/hiperclocks.html rev. a september 13, 2004 14 integrated circuit systems, inc. ics8523i-03 l ow s kew , 1- to -4 d ifferential - to -lvhstl f anout b uffer t able 9. o rdering i nformation while the information presented herein has been checked for both accuracy and reliability, integrated circuit systems, incorpor ated (ics) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. no other circuits, patents, or licenses are i mplied. this product is intended for use in normal commercial and industrial applications. any other applications such as those requiring high reliability or other extraordinary environment al requirements are not recommended without additional processing by ics. ics reserves the right to change any circuitry or specifications without notice. ics does not authorize or w arrant any ics product for use in life support devices or critical medical instruments. r e b m u n r e d r o / t r a pg n i k r a me g a k c a pt n u o ce r u t a r e p m e t 3 0 - i g a 3 2 5 8 s c i3 0 i g a 3 2 5 8 s c ip o s s t d a e l 0 2e b u t r e p 2 7c 5 8 o t c 0 4 - t 3 0 - i g a 3 2 5 8 s c i3 0 i g a 3 2 5 8 s c il e e r d n a e p a t n o p o s s t d a e l 0 20 0 5 2c 5 8 o t c 0 4 - f l 3 0 - i g a 3 2 5 8 s c il 3 0 i a 3 2 5 8 s c ip o s s t " e e r f - d a e l " d a e l 0 2e b u t r e p 2 7c 5 8 o t c 0 4 - t f l 3 0 - i g a 3 2 5 8 s c il 3 0 i a 3 2 5 8 s c i n o p o s s t " e e r f - d a e l " d a e l 0 2 l e e r d n a e p a t 0 0 5 2c 5 8 o t c 0 4 - the aforementioned trademark, hiperclocks? is a trademark of integrated circuit systems, inc. or its subsidiaries in the unite d states and/or other countries.
8523agi-03 www.icst.com/products/hiperclocks.html rev. a september 13, 2004 15 integrated circuit systems, inc. ics8523i-03 l ow s kew , 1- to -4 d ifferential - to -lvhstl f anout b uffer t e e h s y r o t s i h n o i s i v e r v e re l b a te g a pe g n a h c f o n o i t p i r c s e de t a d a 9 t 1 8 4 1 . t e l l u b e e r f - d a e l d e d d a - n o i t c e s s e r u t a e f d e t e l e d d n a n o i t c e s e c a f r e t n i t u p n i k c o l c l a i t n e r e f f i d d e t a d p u . n o i t c e s e c a f r e t n i t u p n i k c o l c l c e p v l . e l b a t n o i t a m r o f n i g n i r e d r o o t g n i k r a m e e r f - d a e l d e d d a 4 0 / 3 1 / 9

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