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  ul tra-low phase-locked dielectric resona t or oscilla tors pldro series 6.7 ? 13.4 ghz fea tures ? l owest phase noise ? very fine frequency resolution ? reference from 5 to 100 mhz ? internal reference available ? small package ? low power consumption ? 100% burn-in & environmentally tested ? three year warranty * for better harmonics consult factory. ** reference frequency above 100 mhz is available, consult factory *** reverse logic available elect rical specif ica tio ns environmental conditions operating temperature ****..... ............................... -20 to +70c storage temperature ............................................ -50 to +100c humidity .......... .................... ................ ............. .... 95% at 40c, noncondensing shock (survival).................................................... 30 g?s, 10 ms pulse vibration (survival) ... .............. .............. ................ 20 to 2000 hz random to 4 g?s rms weight ............... ............. .............. .............. .......... 125 grams (typical) **** extended temperature ranges available, consult factory. wn-177697b 5/6/2008 parameters units fundamental output frequency range ghz 6.7 to 13.4 output power (minimum) dbm +13 harmonics (maximum)* dbc -20 fundamentals (maximum) dbc n/a spurious (maximum) dbc -75 phase noise dbc/hz see next page reference frequency** mhz 5 to 100 reference input power dbm 0 3 voltage vdc +5.6, +8, +12, or +15 voltage tolerance (maximum) vdc +/- 0.2 current (maximum) ma 370 load vswr (maximum) 2:1 alarm*** ttl "high" in-lock connectors rf in/out sma/sma voltage/alarm/phase voltage solder pin feedthru pldro series
ul tra-low phase-locked dielectric resona t or oscilla tors ordering informa t ion external reference option: pldro internal reference option: pldro - i - output frequency (mhz) d.c. supply (+volts) d.c. supply (+volts) external reference frequency (mhz) p - - - - alarm output frequency (mhz) - p - alarm alarm: 3. ttl; low in lock, high out of lock 4. ttl; high in lock, low out of lock wn-177697b 5/6/2008 maximum phase noise data pldro fundamental phase noise @ 6.7ghz ? 8.0ghz 8.0ghz ? 11.5ghz 11.5ghz ?13.4ghz 10hz -53dbc/hz -48dbc/hz -48dbc/hz 100hz -76dbc/hz -73dbc/hz -72dbc/hz 1khz -110dbc/hz -108dbc/hz -105dbc/hz 10khz -117dbc/hz -115dbc/hz -106dbc/hz 100khz -120dbc/hz -118dbc/hz -106dbc/hz 1mhz -143dbc/hz -141dbc/hz -130dbc/hz pldro typical phase n oise -1 7 0 -1 6 0 -1 5 0 -1 4 0 -1 3 0 -1 2 0 -1 1 0 -1 0 0 -9 0 -8 0 -7 0 -6 0 -5 0 -4 0 -3 0 -2 0 -1 0 0 10 100 1000 10000 100000 1000000 f re q u e n c y o ffs e t fro m c a rrie r (h z ) phase noise dbc/hz pld ro -010-06950-4-12p pldr o -010-12950-12p
1478748 pldro series (fundamental) outline drawing wn-177697b 5/6/2008


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