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preliminary data this is preliminary information on a new product now in deve lopment or undergoing evaluation. details are subject to change without notice. november 2010 doc id 18171 rev 1 1/30 30 lps001wp mems pressure sensor 300-1100 mbar absolute digital output barometer features piezoresistive pressure sensor 300-1100 mbar absolute pressure range 0.065 mbar resolution embedded offset and span temperature compensation embedded 16-bit adc spi and i 2 c interfaces supply voltage 2.2 v to 3.6 v high shock survivability (10000 g) small and thin package ecopack ? lead-free compliant applications altimeter and barometer for portable devices smartphones indoor navigation gps applications weather station equipment sports watches description the lps001wp is an ultra compact absolute piezoresistive pressure sensor. it includes a monolithic sensing element and an ic interface able to take information from the sensing element and to provide a digital signal to the external world. the sensing element cons ists of a suspended membrane realized insi de a single mono-silicon substrate. it is capable of detecting pressure and is manufactured using a dedicated process developed by st, called vensens . the vensens process allows the building of a mono-silicon membr ane above an air cavity with controlled gap and defined pressure. the membrane is very small compared to the traditionally built silicon micromachined membranes. membrane breakage is prevented by intrinsic mechanical stoppers. the ic interface is manufactured using a standard cmos process that allows a high level of integration to design a dedicated circuit which is trimmed to better match the sensing element characteristics. the lps001wp is available in a small plastic land grid array (hclga) package and is guaranteed to operate over a temperature range extending from -40 c to +85 c. the package is holed to allow external pressure to reach the sensing element. the lps001wp belongs to a family of products suitable for a variety of applications. hclga-8l (3x5x1 mm) table 1. device summary part number temperature range [c] package packing lps001wp -40 to +85 hclga-8l tr ay LPS001WPTR tape and reel www.st.com obsolete product(s) - obsolete product(s)
contents lps001wp 2/30 doc id 18171 rev 1 contents 1 block diagram and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 1.1 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 1.2 pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2 mechanical and electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . 8 2.1 mechanical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.2 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 3 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 4 functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 4.1 sensing element . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 4.2 ic interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 4.3 factory calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 5 application hints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 5.1 soldering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 5.2 procedure for single acquisition (low power consumption) . . . . . . . . . . . 11 5.2.1 reduced power consumption procedure . . . . . . . . . . . . . . . . . . . . . . . . 12 6 digital interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 6.1 i 2 c serial interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 6.1.1 i 2 c operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 6.2 spi bus interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 6.2.1 spi read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 6.2.2 spi write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 6.2.3 spi read in 3-wires mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 7 register mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 8 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 8.1 who_am_i (0fh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 8.2 ctrl_reg1 (20h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 obsolete product(s) - obsolete product(s)
lps001wp contents doc id 18171 rev 1 3/30 8.3 ctrl_reg2 (21h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 8.4 status_reg (27h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 8.5 press_out_l (28h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 8.6 press_out_h (29h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 8.7 temp_out_l (2ah) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 8.8 temp_out_h (2bh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 8.9 delta_p_l (2ch) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 8.10 delta_p_h (2dh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 8.11 ref_p_l (30h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 8.12 ref_p_h (31h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 8.13 ths_p_l (32h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 8.14 ths_p_h (33h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 9 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 10 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 obsolete product(s) - obsolete product(s)
list of tables lps001wp 4/30 doc id 18171 rev 1 list of tables table 1. device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 table 2. pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 table 3. mechanical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 table 4. electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 table 5. absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 table 6. power consumption @ 1 hz and @ 4 hz odr . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 table 7. serial interface pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 table 8. serial interface pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 table 9. sad+read/write patterns. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 table 10. transfer when master is writing one byte to slave . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 table 11. transfer when master is writing multiple bytes to slave . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 table 12. transfer when master is receiving (reading) one byte of data from slave . . . . . . . . . . . . . 15 table 13. transfer when master is receiving (reading) multiple bytes of data from slave . . . . . . . . . 15 table 14. registers address map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 table 15. who_am_i (0fh) register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 table 16. ctrl_reg1 (20h) register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 table 17. ctrl_reg1 (20h) register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 table 18. output data rate bit configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 table 19. ctrl_reg2 (21h) register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 table 20. ctrl_reg2 (21h) register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 table 21. press_out_l (28h) register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 table 22. ress_out_l (28h) register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 table 24. press_out_h (29h) regist er description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 table 25. temp_out_l (2ah) register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 table 26. temp_out_l (2ah) register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 table 27. temp_out_h (2bh) register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 table 28. temp_out_h (2bh) register description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 table 29. delta_p_l (2ch) register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 table 30. delta_p_l (2ch) register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 table 31. delta_p_h (2dh) register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 table 32. delta_p_h (2dh) register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 table 33. ref_p_l (30h) register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 table 34. ref_p_l (30h) register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 table 35. ref_p_h (31h) register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 table 36. ref_p_h (31h) register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 table 37. ths_p_l (32h) register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 table 38. ths_p_l (32h) register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 table 39. ths_p_h (33h) register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 table 40. ths_p_h (33h) register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 table 42. revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 obsolete product(s) - obsolete product(s)
lps001wp list of figures doc id 18171 rev 1 5/30 list of figures figure 1. block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 figure 2. pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 figure 3. lps001wp electrical connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 figure 4. read and write protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 figure 5. spi read protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 figure 6. multiple bytes spi read protocol (2 bytes example) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 figure 7. spi write protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 figure 8. multiple bytes spi write protocol (2 bytes example) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 figure 9. spi read protocol in 3-wires mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 figure 10. hclga-8l mechanical drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 obsolete product(s) - obsolete product(s)
block diagram and pin description lps001wp 6/30 doc id 18171 rev 1 1 block diagram and pin description 1.1 block diagram figure 1. block diagram 1.2 pin description figure 2. pin connection p -58 ")4 6' !$# $30&/2 ,/7./)3% $)')4!,&),4%2 4%-0%2!452% #/-0%.3!4)/. !.!,/' &2/.4%.$ ) # #3 3%.3/2")!3 4%-0%2 !452% 3%.3/2 6/,4!'% !.$#522%.4 ")!3 #,/#+ 4)-).' 30) 3#,30# 3$!3$/3$) 3!3$/ 6up 6down 6out 2s 2s 2s 2s 3%.3).' %,%-%.4 !.$ !-6 6$$ (6 '.$ 03 3#, 3$) 3$/ #3 4op vi ew 6$$ (6 3#, 3$) #3 (6 3#, 3$) !-6 obsolete product(s) - obsolete product(s)
lps001wp block diagram and pin description doc id 18171 rev 1 7/30 table 2. pin description pin n pin name function 1 vdd power supply 2ps protocol selection i 2 c/spi mode selection (logic 1: i 2 c mode; logic 0: spi enabled) 3 gnd 0 v supply 4 hv connect to vdd (logical ?1?) 5 cs spi enable (chip select) 6sa0/sdo i 2 c less significant bit of de vice slave address (sa0) spi serial data output 7 sda/ sdi/ sdo i 2 c serial data (sda) spi serial data input (sdi) 3-wire interface serial data output (sdo) 8 scl/spc i 2 c serial clock (scl) spi serial port clock (spc) obsolete product(s) - obsolete product(s)
mechanical and electrical specifications lps001wp 8/30 doc id 18171 rev 1 2 mechanical and electrical specifications conditions @ vdd = 2.5 v, t = 25 c, unless otherwise noted. 2.1 mechanical characteristics . 2.2 electrical characteristics table 3. mechanical characteristics symbol parameter test condition min. typ. (1) 1. typical specificat ions are not guaranteed. max. unit pop operating pressure range 300 1100 mbar res (2) 2. parameter given as standard deviation value. pressure resolution 16 lsb/mbar pn pressure noise density 0.028 mbar/sqrt (hz) acc accuracy p = 300 to 1100 mbar t = -10 to 85 c +/-25 mbar tso temperature resolution 64 lsb/c table 4. electrical characteristics symbol parameter test condition min. typ. (1) 1. typical specificat ions are not guaranteed. max. unit vdd supply voltage 2.2 3.6 v idd supply current continous mode odr p = 7 hz odr t = 1 hz 190 a during conversion 400 iddpdn supply current in power-down mode 1 a odr p pressure output data rate (2) 2. for pressure and temperature output data rate configurations refer to table 18 . 712.5hz odr t temperature output data rate (3) 3. datasheet specification guar anteed only between -10 to 85 c. 17 12.5hz to p (3) extended operating temperature range -40 +85 c obsolete product(s) - obsolete product(s)
lps001wp absolute maximum ratings doc id 18171 rev 1 9/30 3 absolute maximum ratings stress above those listed as ?absolute maximum ratings? may cause permanent damage to the device. this is a stress rating only and functional operation of the device under these conditions is not implied. exposure to maximum rating conditions for extended periods may affect device reliability. table 5. absolute maximum ratings symbol ratings maximum value unit vdd supply voltage -0.3 to 6 v vin input voltage on any control pin -0.3 to vdd +0.3 v p overpressure 20 bar t stg storage temperature range -40 to +125 c this is a mechanical shock sensitive device, improper handling can cause permanent damage to the part this is an esd sensitive device, improper handling can cause permanent damage to the part obsolete product(s) - obsolete product(s)
functionality lps001wp 10/30 doc id 18171 rev 1 4 functionality the lps001wp is a high-resolution, digital-output pressure sensor packaged in an lga holed package. the complete device includes a sensing element based on a piezoresistive whetstone bridge approach, and an ic interface capable of providing information from the sensing element to external applications as a digital signal. 4.1 sensing element an st proprietary process is used to obtain a mono-silic on -sized membrane for mems pressure sensors, without requiring substrate-to-substrate bonding. when pressure is applied, membrane deflection induces an imbalance in the wheatstone bridge piezoresistors, whose output signal is converted by the ic interface. intrinsic mechanical stoppers prevent breakage in case of pressure overstress, ensuring measurement repeatability. the pressure inside the buried cavity under the membrane is constant and controlled by process parameters. to be compatible with traditio nal packaging technologies, a s ilicon holed cap is placed on top of the sensing element. during the moulding phase, this opening is covered by dedicated protection to avoid membrane blocking. the package design leaves the holed cap exposed, allowing ambient pressure to reach the sensing element. 4.2 ic interface the complete measurement chain consists of a low-noise capacitive amplifier, which converts the resistive unbalance of the mems sensor into an analog voltage signal, and of an analog-to-digital converter, which translates the produced signal into a digital bitstream. the converter is coupled with a dedicated reco nstruction filter which removes the high frequency components of the quantization noise and provides low rate and high resolution digital words. the pressure data can be accessed through an i 2 c/spi interface, making the device particularly suitable for direct interfacing with a microcontroller. 4.3 factory calibration the ic interface is factory-calibrated at two temperatures and two pressure levels for sensitivity and accuracy. the trimming values are stored inside the device using a non-volatile structure. each time the device is turned on, the trimming parameters are downloaded into the registers to be employed during normal operation. this allo ws the user to employ the device without requiring further calibration. obsolete product(s) - obsolete product(s)
lps001wp application hints doc id 18171 rev 1 11/30 5 application hints figure 3. lps001wp electrical connection the device core is supplied through the vdd line. power supply decoupling capacitors (100 nf ceramic, 10 f aluminum) should be placed as near as possible to the supply pad of the device (common design practice). the functionality of the device and the measured data outputs are selectable and accessible through the i 2 c/spi interface. when using the i 2 c, cs must be tied high. it is possible to change, on the fly, the commun ication interface used to access the device registers. the ps (protocol selection) pin performs this change. 5.1 soldering information the hclga package is compliant with the ecopack ? standard. it is qualified for soldering heat resist ance according to jedec j-std-020c. 5.2 procedure for single acquisi tion (low power consumption) if the lps001wp output data rate requested is lower than 7 hz, a dedicated procedure to reduce the power consumption can be implemented. lps001wp is in power down, then it is woken up for the acquisition and again put in power down. this procedure reduces the power consumption. #3 3#,3#0 '.$ 3$!3$) 3$/ 3! 3$/ ;= ;= ;= ;= ;= ;= ;= ;= 6$$ ?& n& topview 6$$ #3 3#,3#0 3$!3$) 3$/ 3! 3$/ ;= ;= ;= ;= ;= ;= ;= ;= ?& n& 6$$ !-6 obsolete product(s) - obsolete product(s)
application hints lps001wp 12/30 doc id 18171 rev 1 5.2.1 reduced power consumption procedure 1. lps001wp power down and low resolution mode a) write ctrl_reg1 (20h) <= ?1000xxxx?b or b) write ctrl_reg1 (20h) <= ?0000xxxx?b (normal resolution) 2. lps001wp wake up a) write ctrl_reg1 (20h) <= ?1100xxxx?b or b) write ctrl_reg1 (20h) <= ?0100xxxx?b (normal resolution) 3. wait 80 ms - settling time 4. output read a) read press_out_h (29h) b) read press_out_l (28h) c) read temp_out_h (2bh) d) read temp_out_l (2ah) 5. lps001wp power down and low power mode a) write ctrl_reg1 (20h) <= ?1000xxxx?b or b) write ctrl_reg1 (20h) <= ?0000xxxx?b (normal resolution) note: power down and normal mode configuration: ctrl_reg1 (20h) <= ?0000xxxx?b table 6. power consumption @ 1 hz and @ 4 hz odr power consumption condition min. typ. (1) 1. typical specificat ions are not guaranteed. max. unit idd supply current low resolution odr = 1 hz 21 a normal resolution odr = 4 hz 75 normal resolution odr = 1 hz 40 normal resolution odr = 4 hz 150 obsolete product(s) - obsolete product(s)
lps001wp digital interfaces doc id 18171 rev 1 13/30 6 digital interfaces the registers embedded inside the lps001wp may be accessed through both the i 2 c and spi serial interfaces. the latter may be sw configured to operate either in 3-wire or 4-wire interface mode. the serial interfaces are mapped onto the same pads. to select/exploit the i 2 c interface, cs line must be tied high. ps pin select i 2 c or spi interface. if the i 2 c interface is disabled (ps pin connected to gnd or logical ?0?) and cs is kept high (logical ?1?), pin sdo and sdi are put in tri-state. 6.1 i 2 c serial interface the lps001wp i 2 c is a bus slave. the i 2 c is employed to write the data into the registers whose content can also be read back. the relevant i 2 c terminology is given in table 8 . there are two signals associated with the i 2 c bus: the serial clock line (scl) and the serial data line (sda). the latter is a bi-directional line used for sending and receiving the data to/from the interface. both the lines are connected to vdd through a pull-up resistor embedded inside the lps001wp. when the bus is free, both lines are high. table 7. serial interface pin description pin name pin description ps protocol selection i 2 c/spi mode selection (logic 1: i 2 c mode; logic 0: i 2 c disabled) cs spi enable (chip select) scl/spc i 2 c serial clock (scl) spi serial port clock (spc) sda/sdi/sdo i 2 c serial data (sda) spi serial data input (sdi) 3-wire interface serial data output (sdo) sa0/sdo i 2 c less significant bit of device slave address (sa0) spi serial data output (sdo) table 8. serial interface pin description term description transmitter the device which sends data to the bus receiver the device which receives data from the bus master the device which initiates a transfer, generates clock signals, and terminates a transfer slave the device addressed by the master obsolete product(s) - obsolete product(s)
digital interfaces lps001wp 14/30 doc id 18171 rev 1 the i 2 c interface is compliant wit h fast mode (400 khz) i 2 c standards as well as normal mode. 6.1.1 i 2 c operation the transaction on the bus is started through a start (st) signal. a start condition is defined as a high to low transition on the data line while the scl line is held high. after this has been transmitted by the master, the bus is considered busy. the next byte of data transmitted after the start condition contains the address of the slave in the first 7 bits and the eighth bit tells whether the master is receiving data from the slave or transmitting data to the slave. when an address is sent, each device in the system compares the first seven bits after a start condition with its address. if they match, the device considers itself addressed by the master. the slave address (sad) associated to the lps001wp is 101110xb. the sdo pad can be used to modify the less significant bit of the de vice address. if the sdo pad is connected to voltage supply, lsb is ?1? (address 1011101b), otherwise, if the sdo pad is connected to ground, the lsb value is ?0? (address 1011100b). this solution permits to connect and address two different lps001wps to the same i 2 c lines. data transfer with acknowledge is mandatory. the transmitter must release the sda line during the acknowledge pulse. the receiver must then pull the data line low so that it remains stable low during the high period of the acknowledge clock pulse. a receiver which has been addressed is obliged to generate an acknowledge after each byte of data has been received. the i 2 c embedded inside the lps001wp behaves like a slave device and the following protocol must be adhered to. after the start condition (st) a slave address is sent (sad + r/w), once a slave acknowledge (sak) has been returned, an 8- bit sub-address is transmitted (sub): the 7 lsb represent the actual register address while the msb enables address auto increment. if the msb of the sub field is 1, the sub (register address) is automatically incremented to a llow a multiple data read/write. the slave address is completed with a read/write bit. if the bit was ?1? (read), a repeated start (sr) condition must be issued after the two sub-address bytes; if the bit is ?0? (write), the master transmits to the slave with an unchanged direction. table 9 explains how the sad+read/write bit pattern is composed, listing all the possible configurations. table 9. sad+read/write patterns command sad[6:1] sad[0] = sdo r/w sad+r/w read 101110 0 1 10111001 (b9h) write 101110 0 0 10111000 (b8h) read 101110 1 1 10111011 (bbh) write 101110 1 0 10111010 (bah) table 10. transfer when master is writing one byte to slave master st sad + w sub data sp slave sak sak sak obsolete product(s) - obsolete product(s)
lps001wp digital interfaces doc id 18171 rev 1 15/30 data are transmitted in byte format (data). each data transfer contains 8 bits. the number of bytes transferred per transfer is unlimited. data is transferred with the most significant bit (msb) first. if a receiver can?t receive another complete byte of data until it has performed some other function, it can hold the clock line, scl low, to force the transmitter into a wait state. data transfer only continues when the receiver is ready for another byte and releases the data line. if a slave receiver doesn?t acknowledge the slave address (i.e. it is not able to receive because it is performing some real-time function) the data line must be left high by the slave. the master can then abort the transfer. a low to high transition on the sda line while the scl line is high is defined as a stop condition. each data transfer must be terminated by the generation of a stop (sp) condition. in order to read multiple bytes incrementing the register address, it is necessary to assert the most significant bit of the sub-address field. in other words, sub(7) must be equal to 1 while sub(6-0) represents the address of the first register to read. in the presented communication format mak is master acknowledge and nmak is no master acknowledge. 6.2 spi bus interface the lps001wp spi is a bus slave. the spi allows to write and read the registers of the device. the serial interface interacts with the outside world with 4 wires: cs, spc, sdi and sdo. table 11. transfer when master is writing multiple bytes to slave master st sad + w sub data data sp slave sak sak sak sak table 12. transfer when master is receiving (reading) one byte of data from slave master st sad + w sub sr sad + r nmak sp slave sak sak sak data table 13. transfer when master is receiving (reading) multiple bytes of data from slave master st sad+w sub sr sad+r mak mak nmak sp slave sak sak sak data data data obsolete product(s) - obsolete product(s)
digital interfaces lps001wp 16/30 doc id 18171 rev 1 figure 4. read and write protocol cs is the serial port enable and it is controlled by the spi master. it goes low at the start of the transmission and returns to high at the end. spc is the serial port clock and it is controlled by the spi master. it is stopped high when cs is high (no transmission). sdi and sdo are respectively the serial port data input and output. those lines are driven at the falling edge of spc and s hould be captured at the rising edge of spc. both the read register and write register commands are completed in 16 clock pulses or in multiples of 8 in the case of multiple byte read/write. bit duration is the time between two falling edges of spc. the first bit (bit 0) starts at the first falling edge of spc after the falling edge of cs while the last bit (bit 15, bit 23, ...) starts at the last falling edge of spc just before the rising edge of cs. bit 0 : rw bit. when 0, the data di(7:0) is written into the device. when 1, the data do(7:0) from the device is read. in the latter case, the chip drives sdo at the start of bit 8. bit 1 : ms bit. when 0, the address remains unchanged in multiple read/write commands. when 1, the address is auto incremented in multiple read/write commands. bit 2-7 : address ad(5:0). this is the address field of the indexed register. bit 8-15 : data di(7:0) (write mode). this is the data that is written into the device (msb first). bit 8-15 : data do(7:0) (read mode). this is the data that is read from the device (msb first). in multiple read/write commands further blocks of 8 clock periods are added. when the ms bit is 0, the address used to read/write data remains the same for every block. when ms bit is 1, the address used to read/write data is incremented at every block. the function and the behavior of sdi and sdo remain unchanged. cs spc sdi sdo rw ad5ad4ad3ad2ad1ad0 di7di6 di5di4 di3di2di1 di0 do7do6do5do4do3do2 do1do0 ms cs spc sdi sdo rw ad5ad4ad3ad2ad1ad0 di7di6 di5di4 di3di2di1 di0 do7do6do5do4do3do2 do1do0 ms obsolete product(s) - obsolete product(s)
lps001wp digital interfaces doc id 18171 rev 1 17/30 6.2.1 spi read figure 5. spi read protocol the spi read command is performed with 16 clock pulses. the multiple byte read command is performed adding blocks of 8 clock pulses at the previous one. bit 0 : read bit. the value is 1. bit 1 : ms bit. when 0, do not increment the address, when 1, increment the address in multiple readings. bit 2-7 : address ad(5:0). this is the address field of the indexed register. bit 8-15 : data do(7:0) (read mode). this is the data that is read from the device (msb first). bit 16-... : data do(...-8). further data in multiple byte readings. figure 6. multiple bytes spi read protocol (2 bytes example) 6.2.2 spi write figure 7. spi write protocol cs spc sdi sdo rw do7do6 d o5 do4do3 d o2 do1do0 ad5 ad4 a d3 a d2 ad1 ad0 ms cs spc sdi sdo rw do7do6 d o5 do4do3 d o2 do1do0 ad5 ad4 a d3 a d2 ad1 ad0 ms cs spc sdi sd o rw do7 do6do5 do4 d o3 do2 do1 do0 ad5 ad4 ad3 ad2 ad1 ad0 do15 do 14 do13 do12 do11 do 10 do 9 d o8 ms cs spc sdi sd o rw do7 do6do5 do4 d o3 do2 do1 do0 ad5 ad4 ad3 ad2 ad1 ad0 do15 do 14 do13 do12 do11 do 10 do 9 d o8 ms cs spc sdi rw di7di6di5di4di3di2di1di0 ad5 ad4 ad3 ad2 ad 1 ad0 ms cs spc sdi rw di7di6di5di4di3di2di1di0 ad5 ad4 ad3 ad2 ad 1 ad0 ms obsolete product(s) - obsolete product(s)
digital interfaces lps001wp 18/30 doc id 18171 rev 1 the spi write command is performed with 16 clock pulses. the multiple byte write command is performed adding blocks of 8 clock pulses at the previous one. bit 0 : write bit. the value is 0. bit 1 : ms bit. when 0, do not increment the address, when 1, increment the address in multiple writings. bit 2 -7 : address ad(5:0). this is the address field of the indexed register. bit 8-15 : data di(7:0) (write mode). this is the data that is written inside the device (msb first). bit 16-... : data di(...-8). further data in multiple byte writings. figure 8. multiple bytes spi write protocol (2 bytes example) 6.2.3 spi read in 3-wires mode 3-wires mode is entered by setting to 1 bit sim (spi serial interface mode selection) in the internal control register. figure 9. spi read protocol in 3-wires mode the spi read command is performed with 16 clock pulses: bit 0 : read bit. the value is 1. bit 1 : ms bit. when 0, do not increment the address, when 1, increment the address in multiple readings. bit 2-7 : address ad(5:0). this is the address field of the indexed register. bit 8-15 : data do(7:0) (read mode). this is the data that is read from the device (msb first). multiple read command is also available in 3-wires mode. cs spc sdi rw a d5 a d4 ad3 ad 2 ad 1 a d0 di7di6 di5di4 di3 di2di1 di0 di15 di 14 di 1 3 d i1 2 d i 11 d i 1 0 di9 di8 ms cs spc sdi rw a d5 a d4 ad3 ad 2 ad 1 a d0 di7di6 di5di4 di3 di2di1 di0 di15 di 14 di 1 3 d i1 2 d i 11 d i 1 0 di9 di8 ms cs spc sdi/o rw do7do6do5do4do3do2do1do0 ad5 ad4 ad3 ad2 ad1 ad0 ms cs spc sdi/o rw do7do6do5do4do3do2do1do0 ad5 ad4 ad3 ad2 ad1 ad0 ms obsolete product(s) - obsolete product(s)
lps001wp register mapping doc id 18171 rev 1 19/30 7 register mapping table 14 below provides a listing of the 8-bit registers embedded in the device and the related addresses. . registers marked as reserved must not be changed. writing to those registers may cause permanent damage to the device. the content of the registers that are loaded at boot should not be changed. they contain the factory calibration values. their content is automatically restored when the device is powered up. table 14. registers address map name type register address default comment hex binary reserved (do not modify) 00-0e reserved who_am_i r 0f 000 1111 10111010 dummy register reserved (do not modify) 10-1f reserved ctrl_reg1 rw 20 010 0000 00000000 ctrl_reg2 rw 21 010 0001 00000000 reserved (do not modify) 23-26 reserved status_reg r 27 010 0111 00000000 press_out_l r 28 010 1000 output press_out_h r 29 010 1001 output temp_out_l r 2a 010 1010 output temp_out_h r 2b 010 1011 output delta_p_l r 2c 010 1100 output delta_p_h r 2d 010 1101 output reserved (do not modify) 2e-2f reserved ref_p_l rw 30 011 0000 00000000 ref_p_h rw 31 011 0001 00000000 ths_p_l rw 32 011 0010 00000000 ths_p_h rw 33 011 0011 00000000 interrupt_cfg rw 34 011 0100 00000000 int_source r 35 011 0101 output int_ack r 36 011 0110 dummy register reserved (do not modify) 37-3f reserved obsolete product(s) - obsolete product(s)
register description lps001wp 20/30 doc id 18171 rev 1 8 register description the device contains a set of registers which are used to control its behavior and to retrieve pressure and temperature data. the registers address, made up of 7 bits, is used to identify them and to read/write the data through the serial interface. 8.1 who_am_i (0fh) device identification register. this read only register contains the device identifier which, for lps001wp, is set to bah. 8.2 ctrl_reg1 (20h) pd bit allows to turn on the device. the device is in power-down mode when pd = ?0? (default value after boot). the device is active w hen pd is set to ?1?. odr1 - odr0 bits allow to change the output data rates of pressure and temperature samples. the default value is ?00? which corresponds to a data rate of 7 hz for pressure table 15. who_am_i (0fh) register 10111010 table 16. ctrl_reg1 (20h) register x pd odr1 odr0 diff_en bdu ble sim table 17. ctrl_reg1 (20h) register description reserved low power functionality. default value: 0 (0: normal mode; 1: low-power activated) pd power down control. default value: 0 (0: power-down mode; 1: active mode) odr1 odr0 output data rate selection. default value: 00 (see table 18 ) diff_en interrupt circuit enable. default value: 0 (0: interrupt generation disabled; 1: interrupt circuit enabled) bdu block data update. default value: 0 (0: continuous update; 1: output registers not updated until msb and lsb reading) ble big/little endian selection. default value: 0 (0: little endian; 1: big endian) sim spi serial interface mode selection. default value: 0 (0: 4-wire interface; 1: 3-wire interface) obsolete product(s) - obsolete product(s)
lps001wp register description doc id 18171 rev 1 21/30 output and 1hz for temperature output. odr1 and odr2 bits can be configured as described in table 18 . diff_en bit is used to enable the circuitry for the computing of delta pressure output, delta_p. in default mode (diff_en = ?0?) this circuitry is turned off. it is suggested to turn on the circuitry only after the configuration of the ref_p_l, ref_p_h, ths_p_l and ths_p_h r egisters used by the circuitry. bdu bit is used to inhibit output registers update between the reading of upper and lower register parts. in default mode (bdu = ?0?) the lower and upper register parts are updated continuously. if it doesn?t read the output fast enough, the data update is blocked until the two registers have been read. in this way, after the reading of the lower (upper) register part, the content of that output register is not updated until the upper (lower) part is read too. this feature avoids reading lsb and msb related to different samples. ble bit is used to select big endian or little endian representation for output registers. in the big endian one, msb values are located in press_out_l (pressure), temp_out_l (temperature) and delta_p_l (delta pressure), while lsb values are located in press_out_h, temp_out_h and delta_p_h. in little endian representation the order is inverted (refer to data registers description for more details). sim bit selects the spi serial interface mode. when sim is ?0? (default value) the 4-wire interface mode is selected and data coming from the device are sent to pin #4 (sdo). in 3-wire interface mode, output data are sent to pin #5 (sdi/sdo). 8.3 ctrl_reg2 (21h) boot bit is used to refresh the content of internal registers stored in the flash memory block. at device power-up, the content of the flash memory block is transferred to the internal registers related to trimming functions to permit a good behavior of the device itself. if for any reason the content of trimming registers was changed, it is sufficient to use this bit table 18. output data rate bit configurations odr1 (1) 1. ?10? bit configuration is not allowed and may cause incorrec t device functionality. odr0 pressure output data rate temperature output data rate 0 0 7 hz 1 hz 0 1 7 hz 7 hz 1 1 12.5 hz 12.5 hz table 19. ctrl_reg2 (21h) register bootxxxxxx0 (1) 1. bit to be kept to ?0? for correct device functionality table 20. ctrl_reg2 (21h) register description boot reboot memory content. default value: 0 (0: normal mode; 1: reboot memory content) obsolete product(s) - obsolete product(s)
register description lps001wp 22/30 doc id 18171 rev 1 to restore the correct values. when the boot bit is set to ?1? the content of internal flash is copied inside the corresponding internal registers and is used to calibrate the device. these values are factory trimmed and they are different for every device. they permit a good behavior of the device and normally they do not have to be changed. at the end of the boot process the boot bit is set again to ?0?. the boot bit takes effect after one odr clock cycle. 8.4 status_reg (27h) the content of this register is updated every odr cycle, regardless of the bdu value in ctrl_reg1. p_da is set to '1' whenever a new pressure samp le is available. p_da is cleared anytime the press_out_h (29h) register is read. t_da is set to '1' whenever a new temperature sample is available. t_da is cleared anytime the temp_out_h (2bh) register is read. p_or bit is set to '1' whenever new pressure data is available and p_da was set in the previous odr cycle and not cleared. p_or is cleared anytime the press_out_h (29h) register is read. t_or is set to '1' whenever new temperature data is available and t_da was set in the previous odr cycle and not cleared. t_or is cleared anytime the temp_out_h (2bh) register is read. 8.5 press_out_l (28h) 0 0 p_or t_or 0 0 p_da t_da p_or pressure data overrun. default value: 0 (0: no overrun has occurred; 1: new data for pressure has overwritten the previous one) t_or temperature data overrun. default value: 0 (0: no overrun has occurred; 1: new data for temperature has overwritten the previous one) p_da pressure data available. default value: 0 (0: new data for pressure is not yet available; 1: new data for pressure is available) t_da temperature data available. default value: 0 (0: new data for temperature is not yet available; 1: new data for temperature is available) table 21. press_out_ l (28h) register pout7 pout6 pout5 pout4 pout3 pout2 pout1 pout0 obsolete product(s) - obsolete product(s)
lps001wp register description doc id 18171 rev 1 23/30 pressure data are expressed as absolute values. values exceeding the operating pressure range (see table 3 ) are clipped. in big endian mode (ble bit in ctrl_reg1 set to ?1?) the content of this register is the msb pressure data. 8.6 press_out_h (29h) in big endian mode (ble bit in ctrl_reg1 set to ?1?) the content of this register is the lsb pressure data. 8.7 temp_out_l (2ah) temperature data are expressed as 2s complement numbers. in big endian mode (ble bit in ctrl_reg1 set to ?1?) the content of this register is the msb temperature data. 8.8 temp_out_h (2bh) table 22. ress_out_l (28h ) register description pout7 - pout0 pressure data lsb (when ble bit in the ctrl_reg1 is set to ?0?, little endian) table 23. press_out_h (29h) register pout15 pout14 pout13 pout12 pout11 pout10 pout9 pout8 table 24. press_out_h (29h ) register description pout15 - pout8 pressure data msb (when ble bit in ctrl_reg1 is set to ?0?) table 25. temp_out_l (2ah) register tout7 tout6 tout5 tout4 tout3 tout2 tout1 tout0 table 26. temp_out_l (2ah) register description tout7 - tout0 temperature data lsb (when ble bit in ctrl_reg1 register is set to ?0?, little endian) table 27. temp_out_h (2bh) register tout15 tout14 tout13 tout12 tout11 tout10 tout9 tout8 obsolete product(s) - obsolete product(s)
register description lps001wp 24/30 doc id 18171 rev 1 temperature data are expressed as 2s complement numbers. in big endian mode (ble bit in ctrl_reg1 set to ?1?) the content of this register is the lsb temperature data. 8.9 delta_p_l (2ch) delta_p registers store a delta pressure representing the difference between a constant reference value, ref_p registers, and the actual pressure measured, press_out registers. in big endian mode (ble bit in ctrl_reg1 set to ?1?) the content of this register is the msb delta pressure data. 8.10 delta_p_h (2dh) in big endian mode (ble bit in ctrl_reg1 set to ?1?) the content of this register is the lsb delta pressure data. 8.11 ref_p_l (30h) table 28. temp_out_h (2bh) register description tout8 - tout15 temperature data msb (when ble bit in ctrl_reg1 register is set to ?0?) table 29. delta_p_l (2ch) register dp7 dp6 dp5 dp4 dp3 dp2 dp1 dp0 table 30. delta_p_l (2ch) register description dp7 - dp0 delta pressure data lsb (when ble bit in ctrl_reg1 register is set to ?0?) table 31. delta_p_h (2dh) register dp15 dp14 dp13 dp12 dp11 dp10 dp9 dp8 table 32. delta_p_h (2dh) register description dp15 - dp8 delta pressure data msb (when ble bit in ctrl_reg1 register is set to ?0?). table 33. ref_p_l (30h) register refl7 refl6 refl5 refl4 refl3 refl2 refl1 refl0 obsolete product(s) - obsolete product(s)
lps001wp register description doc id 18171 rev 1 25/30 this register contains the lower part of the reference pressure for computing of delta pressure. full value is ref_p_h & ref_p_l and it is represented as an unsigned number. 8.12 ref_p_h (31h) this register contains the higher part of the reference pressure for computing of delta pressure. full value is ref_p_h & ref_p_l and it is represented as an unsigned number. 8.13 ths_p_l (32h) this register contains the low part of threshold value for pressure interrupt generation. the complete threshold value is given by ths_p_h & ths_p_l and is expressed as an unsigned number. 8.14 ths_p_h (33h) table 34. ref_p_l (30h) register description refl7 - refl0 reference pressure lsb data. default value: 00h. table 35. ref_p_h (31h) register refl15 refl14 refl13 refl12 refl11 refl10 refl9 refl8 table 36. ref_p_h (31h) register description refl15 - refl8 reference pressure msb data. default value: 00h. table 37. ths_p_l (32h) register ths7 ths6 ths5 ths4 ths3 ths2 ths1 ths0 table 38. ths_p_l (32h) register description ths7 - ths0 threshold pressure lsb. default value: 00h. table 39. ths_p_h (33h) register ths15 ths14 ths13 ths12 ths11 ths10 ths9 ths8 table 40. ths_p_h (33h) register description ths15 - ths8 threshold pressure msb. default value: 00h. obsolete product(s) - obsolete product(s)
register description lps001wp 26/30 doc id 18171 rev 1 this register contains the high part of threshold value for pressure interrupt generation. the complete threshold value is given by ths_p_h & ths_p_l and is expressed as an unsigned number. obsolete product(s) - obsolete product(s)
lps001wp package information doc id 18171 rev 1 27/30 9 package information in order to meet environmental requirements, st offers these devices in different grades of ecopack ? packages, depending on their level of environmental compliance. ecopack specifications, grade definitions, and product status are available at: www.st.com . ecopack is an st trademark. table 41. hclga-8l mechanical data dimensions ref. mm min. typ. max. e1 2.850 3.0 3.150 e3 0 d1 4.850 5.0 5.150 d3 1.200 r1 1.0 a1 1.0 n1 1.0 n2 0.625 l1 2.0 l2 3.750 p1 1.300 p2 2.300 t1 0.800 d0.200 t2 0.500 k0.050 m1 0.100 obsolete product(s) - obsolete product(s)
package information lps001wp 28/30 doc id 18171 rev 1 figure 10. hclga-8l mechanical drawing e1 d 1 m1 d a1 d 3 n1 l1 p1 p 2 e3 r 1 ? k d e c ? k d ? k e ? k c ? k pin 1 indicator top view bottom view t 2 n 2 l 2 t1 obsolete product(s) - obsolete product(s)
lps001wp revision history doc id 18171 rev 1 29/30 10 revision history table 42. document revision history date revision changes 05-nov-2010 1 initial release. obsolete product(s) - obsolete product(s)
lps001wp 30/30 doc id 18171 rev 1 please read carefully: information in this document is provided solely in connection with st products. stmicroelectronics nv and its subsidiaries (?st ?) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described he rein at any time, without notice. all st products are sold pursuant to st?s terms and conditions of sale. purchasers are solely responsible for the choice, selection and use of the st products and services described herein, and st as sumes no liability whatsoever relating to the choice, selection or use of the st products and services described herein. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. i f any part of this document refers to any third party products or services it shall not be deemed a license grant by st for the use of such third party products or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoev er of such third party products or services or any intellectual property contained therein. unless otherwise set forth in st?s terms and conditions of sale st disclaims any express or implied warranty with respect to the use and/or sale of st products including without limitation implied warranties of merchantability, fitness for a parti cular purpose (and their equivalents under the laws of any jurisdiction), or infringement of any patent, copyright or other intellectual property right. unless expressly approved in writing by an authorized st representative, st products are not recommended, authorized or warranted for use in milita ry, air craft, space, life saving, or life sustaining applications, nor in products or systems where failure or malfunction may result in personal injury, death, or severe property or environmental damage. st products which are not specified as "automotive grade" may only be used in automotive applications at user?s own risk. resale of st products with provisions different from the statements and/or technical features set forth in this document shall immediately void any warranty granted by st for the st product or service described herein and shall not create or extend in any manner whatsoev er, any liability of st. st and the st logo are trademarks or registered trademarks of st in various countries. information in this document supersedes and replaces all information previously supplied. the st logo is a registered trademark of stmicroelectronics. all other names are the property of their respective owners. ? 2010 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - belgium - brazil - canada - china - czech republic - finland - france - germany - hong kong - india - israel - ital y - japan - malaysia - malta - morocco - philippines - singapore - spain - sweden - switzerland - united kingdom - united states of america www.st.com obsolete product(s) - obsolete product(s)

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