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cmos ic ordering number : enn*7157 ver:1.03 m2003. m2003 nothing (nothing) sk no.7157-1/26 8-bit single chip microcontrolle r lc877372a/64a56a/48 a lc877372a 8 bit single chip microcontroller incorporating 72kb rom and 2048 byte ram on chip LC877364A 8 bit single chip microcontroller incorporating 64kb rom and 2048 byte ram on chip lc877356a 8 bit single chip microcontroller incorporating 56kb rom and 2048 byte ram on chip lc877348a 8 bit single chip microcontroller incorporating 48kb rom and 2048 byte ram on chip overview the lc877372a, LC877364A lc877356a and lc877348a are 8-bit single chip microcontrollers with the following on-chip functional blocks : - cpu: operable at a minimum bus cycle time of 100 ns - on-chip rom maximum capacity : lc877372a 72k bytes LC877364A 64k bytes lc877356a 56k bytes lc877348a 48k bytes - on-chip ram capacity: 2048 bytes - lcd controller / driver - 16 bit timer / counter (can be divided into two 8 bit timers) - 16 bit timer / pwm (can be divided into two 8 bit timers) - four 8-bit timer with prescalers - timer for use as date / time clock - synchronous serial i/o port (with automatic block transmit / receive function) - asynchronous / synchronous serial i/o port - 15-channel 8-bit ad converter - small signal detector
lc877372a/64a/56a/48a 2/26 - high-speed clock counter - system clock divider - 18-source 10-vectored interrupt system features (1) read-only memory (rom) - 73728 8 bits (lc877372a) - 65536 8 bits (LC877364A) - 57344 8 bits (lc877356a) - 49152 8 bits (lc877348a) (2) random access memory (ram): 2048 9 bits (lc877372a, LC877364A, lc877356a, lc877348a) (3) minimum bus cycle time: 100 ns (10 mhz) note: the bus cycle time indicates rom read time. (4) minimum instruction cycle time (tcyc) : 300 ns (10mhz) (5) ports - input/output ports data direction programmable for each bit individually : 26 (p1n, p30-p35, p70-p73, p8n) data direction programmable in nibble units : 8 (p0n) (when n-channel open drain output is selected, data can be input in bit units.) - input ports : 2 (xt1,xt2) - lcd ports segment output : 48 (s00-s47) common output : 4 (com0-com3) bias terminals for lcd driver 3 (v1-v3) other functions input/output ports : 48(pan,pbn,pcn,pdn,pen,pfn) input ports : 7 (pln) - oscillator pins : 2 (cf1,cf2) - reset pin : 1 ( res ) - power supply : 6 (vss1-3,vdd1-3) (6) lcd controller - seven display modes are available (static, 1/2, 1/3, 1/4 duty 1/2, 1/3 bias) - segment output and common output can be switched to general purpose input/output ports. (7) small signal detection (mic signals etc) - counts pulses with the level which is greater than a preset value - 2 bit counter
lc877372a/64a/56a/48a 3/26 (8) timers - timer 0: 16 bit timer / counter with capture register mode 0: 2 channel 8-bit timer with programmable 8 bit prescaler and 8 bit capture register mode 1: 8 bit timer with 8 bit programmable prescaler and 8 bit capture register + 8 bit counter with 8-bit capture register mode 2: 16 bit timer with 8 bit programmable prescaler and 16 bit capture register mode 3: 16 bit counter with 16 bit capture register - timer 1: pwm / 16 bit timer with toggle output function mode 0: 2 channel 8 bit timer (with toggle output) mode 1: 2 channel 8 bit pwm mode 2: 16 bit timer (with toggle output) toggle output from lower 8 bits is also possible. mode 3: 16 bit timer (with toggle output) lower order 8 bits can be used as pwm. - timer 4: 8-bit timer with 6-bit prescaler - timer 5: 8-bit timer with 6-bit prescaler - timer 6: 8-bit timer with 6-bit prescaler - timer 7: 8-bit timer with 6-bit prescaler - base timer 1) the clock signal can be selected from any of the following : sub-clock (32.768khz crystal oscillator), system clock, and prescaler output from timer 0 2) interrupts of five different time intervals are possible. (9) high-speed clock counter - countable up to 20 mhz clock (when using 10mhz main clock) - real time output (10) serial-interface - sio 0: 8 bit synchronous serial interface 1) lsb first / msb first is selectable 2) internal 8 bit baud-rate generator (fastest clock period 4 / 3 tcyc) 3) consecutive automatic data communication (1-256 bits) - sio 1: 8 bit asynchronous / synchronous serial interface mode 0: synchronous 8 bit serial io (2-wire or 3-wire, transmit clock 2?512 tcyc) mode 1: asynchronous serial io (half duplex, 8 data bits, 1 stop bit, baud rate 8?2048tcyc) mode 2: bus mode 1 (start bit, 8 data bits, transmit clock 2?512 tcyc) mode 3: bus mode 2 (start detection, 8 data bits, stop detection) (11) ad converter -8 bits 15 channels (12) remote control receiver circuit (connected to p73 / int3 / t0in terminal) -noise rejection function (noise rejection filter?s time constant can be selected from 1 / 32 / 128 tcyc) (13) watchdog timer - the watching time period is determined by an external rc. - watchdog timer can produce interrupt or system reset
lc877372a/64a/56a/48a 4/26 (14) interrupts: 18 sources, 10 vectors 1) three priority (low, high and highest) multiple interrupts are supported. during interrupt handling, an equal or lower priority interrupt request is postponed. 2) if interrupt requests to two or more vector addre sses occur at once, the higher priority interrupt takes precedence. in the case of equal priority levels, the vector with the lowest address takes precedence. no. vector selectable level interrupt signal 1 00003h x or l int0 2 0000bh x or l int1 3 00013h h or l int2/t0l 4 0001bh h or l int3/base timer 5 00023h h or l t0h 6 0002bh h or l t1l/t1h 7 00033h h or l sio0 8 0003bh h or l sio1 9 00043h h or l adc/mic/t6/t7 10 0004bh h or l port 0/t4/t5 ? priority level : x > h > l ? for equal priority levels, vector with lowest address takes precedence. (15) subroutine stack levels: 1024 levels max. stack is located in ram. (16) multiplication and division - 16 bit 8 bit (executed in 5 cycles) - 24 bit 16 bit (12 cycles) - 16 bit 8 bit (8 cycles) - 24 bit 16 bit (12 cycles) (17) oscillation circuits - on-chip rc oscillation for system clock use. - cf oscillation for system clock use. (rf built in, rd external) - crystal oscillation low speed system clock use. (rf built in, rd external) - on-chip frequency variable rc oscillation circuit for system clock use. (18) system clock divider - low power consumption operation is available - minimum instruction cycle time (300ns, 600ns, 1.2s, 2.4s, 4.8s, 9.6s, 19.2s, 38.4s, 76.8s can be switched by program (when using 10mhz main clock) (19) standby function - halt mode halt mode is used to reduce power consumption. during the halt mode, program execution is stopped but peripheral circuits keep operating (some parts of serial transfer operation stop.) 1) oscillation circuits are not stopped automatically. 2) released by the system reset or interrupts.
lc877372a/64a/56a/48a 5/26 -hold mode hold mode is used to reduce power consumption. program execution and peripheral circuits are stopped. 1) cf, rc and crystal oscillation circuits stop automatically. 2) released by any of the following conditions. (1) low level input to the reset pin (2) specified level input to one of int0, int1, int2 (3) port 0 interrupt -x?tal hold made x?tal hold mode is used to reduce power consumption. program execution is stopped. all peripheral circuits except the base timer are stopped. 1) cf and rc oscillation circuits stop automatically. 2) crystal oscillator operation is kept in its state at hold mode inception. 3) released by any of the following conditions (1) low level input to the reset pin (2) specified level input to one of int0, int1, int2 (3) port 0 interrupt (4) base-timer interrupt (20) package - qip100e - tqfp100 (21) development tools - evaluation chip : lc876093 - emulator: eva62s + ecb876600 (evaluation chip board) + sub877300 + pod100qfp or pod100sqfp (type b): : ice-b877300 + sub877300 + pod100qfpor pod100sqfp (type b) - flash rom version: lc87f73c8a
lc877372a/64a/56a/48a 6/26 pin assignment sanyo: qip100e s20/pc4 s19/pc3 s18/pc2 s17/pc1 s16/pc0 s15/pb7 s14/pb6 s13/pb5 s12/pb4 s11/pb3 s10/pb2 s9/pb1 s8/pb0 s7/pa7 s6/pa6 s5/pa5 s4/pa4 s3/pa3 s2/pa2 s1pa1 v2/pl5/an13 v1/pl4/an12 com0/pl0 com1/pl1 com2/pl2 com3/pl3 p30 p31 vss3 vdd3 p32 p33 p34 p35 p00 p01 p02 p03 p04 p05 p06 p07 p10/so0 p11/si0/sb0 p12/sck0 p13/so1 p14/si1/sb1 p15/sck1 p16/t1pwml p17/t1pwmh/buz res xt1/an10 xt2/an11 vss1 cf1 cf2 vdd1 p80/an0 p81/an1 p82/an2 p83/an3 p84/an4 p85/an5 p86/an6 p87/an7/micin p70/int0/t0lcp/an8 p71/int1/t0hcp/an9 p72/int2/t0in p73/int3/t0in s0/pa0 v3/pl6/an14 s47/pf7 s46/pf6 s45/pf5 s44/pf4 s43/pf3 s42/pf2 s41/pf1 s40/pf0 s39/pe7 s38/pe6 s37/pe5 s36/pe4 s35/pe3 s34/pe2 s33/pe1 s32/pe0 s31/pd7 s30/pd6 s29/pd5 s28/pd4 s27/pd3 s26/pd2 s25/pd1 s24/pd0 vss2 vdd2 s23/pc7 s22/pc6 s21/pc5 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100
lc877372a/64a/56a/48a 7/26 sanyo: tqfp100 s23/pc7 s22/pc6 s21/pc5 s20/pc4 s19/pc3 s18/pc2 s17/pc1 s16/pc0 s15/pb7 s14/pb6 s13/pb5 s12/pb4 s11/pb3 s10/pb2 s9/pb1 s8/pb0 s7/pa7 s6/pa6 s5/pa5 s4/pa4 s3/pa3 s2/pa2 s1pa1 s0/pa0 p73/int3/t0in s47/pf7 v3/pl6/an14 v2/pl5/an13 v1/pl4/an12 com0/pl0 com1/pl1 com2/pl2 com3/pl3 p30 p31 vss3 vdd3 p32 p33 p34 p35 p00 p01 p02 p03 p04 p05 p06 p07 p10/so0 p11/si0/sb0 p12/sck0 p13/so1 p14/si1/sb1 p15/sck1 p16/t1pwml p17/t1pwmh/buz res xt1/an10 xt2/an11 vss1 cf1 cf2 vdd1 p80/an0 p81/an1 p82/an2 p83/an3 p84/an4 p85/an5 p86/an6 p87/an7/micin p70/int0/t0lcp/an8 p71/int1/t0hcp/an9 p72/int2/t0in s46/pf6 s45/pf5 s44/pf4 s43/pf3 s42/pf2 s41/pf1 s40/pf0 s39/pe7 s38/pe6 s37/pe5 s36/pe4 s35/pe3 s34/pe2 s33/pe1 s32/pe0 s31/pd7 s30/pd6 s29/pd5 s28/pd4 s27/pd3 s26/pd2 s25/pd1 s24/pd0 vss2 vdd2 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
lc877372a/64a/56a/48a 8/26 system block diagram interrupt control stand-by control ir pla rom pc bus interface port 0 port 1 sio0 sio1 base timer lcd controller int0 - 3 noise rejection filter port 3 port 7 port 8 adc weak signal detector acc b register c register psw rar ram stack pointer watch dog timer alu timer 4 timer 5 timer 6 timer 7 timer 0 (high-speed clock counter) timer 1 clock generator cf rc mrc x?tal
lc877372a/64a/56a/48a 9/26 pin assignment pin name i/o function option vss1 vss2 vss3 - ? power supply (-) no vdd1 vdd2 vdd3 - ? power supply (+) no port0 p00 to p07 i/o ? 8bit input/output port ? data direction programmable in nibble units ? use of pull-up resistor can be specified in nibble units ? input for hold release ? input for port 0 interrupt ye s port1 p10 to p17 i/o ? 8bit input/output port ? data direction programmable for each bit ? use of pull-up resistor can be specified for each bit individually ? other pin functions p10 sio0 data output p11 sio0 data input or bus input/output p12 sio0 clock input/output p13 sio1 data output p14 sio1 data input or bus input/output p15 sio1 clock input/output p16: timer 1 pwml output p17: timer 1 pwmh output/buzzer output ye s port3 p30 to p35 i/o ? 6bit input/output port ? data direction can be specified for each bit ? use of pull-up resistor can be specified for each bit individually ye s ? 4bit input/output port ? data direction can be specified for each bit ? use of pull-up resistor can be specified for each bit individually ? other functions p70: int0 input/hold release input/timer0l capture input/output for watchdog timer p71: int1 input/hold release input/timer0h capture input p72: int2 input/hold release input/timer 0 event input/timer0l capture input p73: int3 input(noise rejection filter attached)/timer 0 event input/timer0h capture input ad input port: an8(p70), an9(p71) ? interrupt detection selection rising falling rising and falling h level l level int0 int1 int2 int3 ye s ye s ye s ye s ye s ye s ye s ye s no no ye s ye s ye s ye s no no ye s ye s no no port7 p70 to p73 i/o no continued
lc877372a/64a/56a/48a 10/26 pin name i/o function description option port8 p80 to p87 i/o ? 8bit input/output port ? input/output can be specified for each bit individually ? other functions: ad input port: an0 to an7 small signal detector input port: micin(p87) no s0/pa0 to s7/pa7 i/o ? segment output for lcd ? can be used as general purpose input/output port (pa) no s8/pb0 to s15/pb7 i/o ? segment output for lcd ? can be used as general purpose input/output port (pb) no s16/pc0 to s23/pc7 i/o ? segment output for lcd ? can be used as general purpose input/output port (pc) no s24 /pd0to s31/pd7 i/o ? segment output for lcd ? can be used as general purpose input/output port (pd) no s32/pe0 to s39/pe7 i/o ? segment output for lcd ? can be used as general purpose input/output port (pe) no s40/pf0 to s47/pf7 i/o ? segment output for lcd ? can be used as general purpose input/output port (pf) no com0/pl0 to com3/pl3 i/o ? common output for lcd ? can be used as general purpose input port (pl) no v1/pl4 to v3/pl6 i/o ? lcd output bias power supply ? can be used as general purpose input port (pl) ? other functions: ad input ports: an12 to an14 no res i reset terminal no xt1 i ? input for 32.768khz crystal oscillation ? other functions: general purpose input port ad input port: an10 ? when not in use, connect to vdd1 no xt2 i/o ? output for 32.768khz crystal oscillation ? other functions: general purpose input port ad input port: an11 ? when not in use, set to oscillation mode and leave open no cf1 i input terminal for ceramic oscillator no cf2 o output terminal for ceramic oscillator no
lc877372a/64a/56a/48a 11/26 port configuration port form and pull-up resistor options are shown in the following table. port status can be read even when port is set to output mode. terminal option applies to: options output form pull-up resistor 1 cmos programmable (note 1) p00 to p07 each bit 2 nch-open drain none 1 cmos programmable p10 to p17 each bit 2 nch-open drain programmable 1 cmos programmable p30 to p35 each bit 2 nch-open drain none p70 ? none nch-open drain programmable p71 to p73 ? none cmos programmable p80 to p87 ? none nch-open drain none s0/pa0 to s47/pf7 ? none cmos programmable com0/pl0 to com3/pl3 ? none input only none v1/pl4 to v3/pl6 ? none input only none xt1 ? none input only none xt2 ? none output for 32.768khz crystal oscillation none note 1 attachment of port0 programmable pull-up resistors is controllable in nibble units (p00-03, p04-07). * note 1: connect as follows to reduce noise on vdd. vss1, vss2 and vss3 must be co nnected together and grounded. *note 2 : the power supply for the internal memory is vdd1 but it uses the vdd3 as the power supply for ports. when the vdd3 is not backed up, the port level does not become ?h? even if the port latch is in the ?h? level. therefore, when the vdd3 is not backed up and the port latch is ?h? level, the port level is unstable in the hold mode, and the back up time becomes shorter because the through current runs from vdd to gnd in the input buffer. if vdd3 is not backed up, output ?l? by the program or pull the port to ?l? by the external circuit in the hold mode so that the port level becomes ?l? level and unnecessary current consumption is prevented. lsi vdd1 back-up capacitors *2 vdd2 vdd3 vss2 vss1 p ower supply vss3
lc877372a/64a/56a/48a 12/26 1. absolute maximum ratings / ta=25c and vss1=vss2=vss3=0v limits parameter symbol pins conditions vdd [v] min. typ. max. unit supply voltage vddmax vdd1,vdd2,vdd3 vdd1=vdd2 =vdd3 -0.3 +7.0 supply voltage for lcd vlcd v1/pl4, v2/pl5, v3/pl6 vdd1=vdd2 =vdd3 -0.3 vdd input voltage vi port l xt1,xt2,cf1, res -0.3 vdd+0.3 input/output voltage vi0(1) ?port0, 1, 3, 7, 8 ?port a, b, c, d, e, f -0.3 vdd+0.3 v ioph(1) port 0, 1, 3 ?cmos output selected ?current at each pin -10 ioph(2) port 71,72,73 current at each pin -3 peak output current ioph(3) port a, b, c, d, e, f current at each pin -5 ioah(1) port 0, 1, 32, 33, 34, 35 total of all pins -40 ioah(2) port 30, 31 total of all pins -10 ioah(3) port 7 total of all pins -5 ioah(4) port a, b, c total of all pins -25 high level output current total output current ioah(5) port d, e, f total of all pins -25 iopl(1) port 0, 1, 32-35 current at each pin 20 iopl(2) port 30, 31 current at each pin 30 iopl(3) port 7,8 current at each pin 5 peak output current iopl(4) port a, b,c, d, e, f current at each pin 15 ioal(1) port 0, 1, 32, 33, 34, 35 total of all pins 60 ioal(2) port 30, 31 total of all pins 60 low level output current total output current ioal(3) port 7,8 total of all pins 20 ioal(4) port a,b,c total of all pins 40 ioal(5) port d, e, f total of all pins 40 ma qip100e 519 maximum power consumption pdmax tqfp100 ta = -30 to +70c 399 mw operating temperature range topg -30 70 storage temperature range tstg -55 125 c
lc877372a/64a/56a/48a 13/26 2. recommended operating range / ta=-30c to +70c, vss1=vss2=vss3=0v limits parameter symbol pins conditions vdd [v] min. typ. max. unit vdd(1) 0.294s t cyc 200s 4.5 6.0 operating supply voltage range vdd(2) vdd1=vdd2=vdd3 0.735s t cyc 200s 2.5 6.0 supply voltage range in hold mode vhd vdd1 keep ram and register data in hold mode. 2.0 6.0 vih(1) ?port 0, 3, 8 ?port a,b,c,d,e,f,l output disable 2.5?6.0 0.3vdd +0.7 vdd vih(2) ?port 1 ?port 71,72,73 ?p70 port input/interrupt output disable 2.5-6.0 0.3vdd +0.7 vdd vih(3) p87 small signal input output disable 2.5-6.0 0 .75vdd vdd vih(4) port 70 watchdog timer output disable 2.5-6.0 0.9vdd vdd input high voltage vih(5) xt1, xt2, cf1, res 2.5-6.0 0 .75vdd vdd vil(1) ?port 0, 3, 8 ?port a,b,c,d,e,f,l output disable 2.5-6.0 vss 0.15vdd +0.4 vil(2) ?port 1 ?port 71,72,73 ?p70 port input/interrupt output disable 2.5-6.0 vss 0.1vdd +0.4 vil(3) port 87 small signal input output disable 2.5-6.0 vss 0.25vdd vil(4) port 70 watchdog timer output disable 2.5-6.0 vss 0.8vdd -1.0 input low voltage vil(5) xt1,xt2,cf1, res 2.5-6.0 vss 0.25vdd v 4.5?6.0 0.294 200 operation cycle time t cyc 2.5-6.0 0.735 200 s 4.5?6.0 0.1 10 ?cf2 open ?system clock divider :1/1 ?external clock duty = 505% 2.5-6.0 0.1 4 4.5?6.0 0.2 20 external system clock frequency fexcf(1) cf1 ?cf2 open ?system clock divider :1/2 2.5-6.0 0.2 8 mhz continued
lc877372a/64a/56a/48a 14/26 limits parameter symbol pins conditions vdd[v] min. typ. max. unit fmcf(1) cf1, cf2 10mhz ceramic resonator oscillation refer to figure 1 4.5?6.0 10 fmcf(2) cf1, cf2 4mhz ceramic resonator oscillation refer to figure 1 2.5?6.0 4 fmrc rc oscillation 2.5-6.0 0.3 1.0 2.0 fmmrc frequency variable rc oscillation source oscillation 2.5-6.0 50 mhz oscillation frequency range (note 1) fsx?tal xt1, xt2 32.768khz crystal resonator oscillation refer to figure 2 2.5-6.0 32.768 khz (note 1) the port value of oscillation circuit is shown in table 1 and table 2.
lc877372a/64a/56a/48a 15/26 3. electrical characteristics / ta=-30 c to +70 c , vss1=vss2=vss3=0v limits parameter symbol pins conditions vdd[v] min. typ. max. unit iih(1) ?port 0,1,3,7,8 ?port a,b,c,d,e, f,l ?output disabled ?pull-up resister off. ?vin=vdd (including off state leak current of the output tr.) 2.5-6.0 1 iih(2) res vin=vdd 2.5-6.0 1 iih(3) xt1,xt2 when configured as an input port vin=vdd 2.5-6.0 1 iih(4) cf1 vin=vdd 2.5-6.0 15 high level input current iih(5) p87/an7/micin small signal input vin=v bis +0.5v (v bis : bias voltage) 2.5-6.0 4.2 8.5 15 iil(1) ?port 0,1,3,7,8 ?port a,b,c,d,e, f,l ?output disabled ?pull-up resister off. ?vin=vss (including off state leak current of the output tr.) 2.5-6.0 -1 iil(2) res vin=vss 2.5-6.0 -1 iil(3) xt1,xt2 when configured as an input port vin=vss 2.5-6.0 -1 iil(4) cf1 vin=vss 2.5-6.0 -15 low level input current iil(5) p87/an7/micin small signal input vin=v bis -0.5v (v bis : bias voltage) 2.5-6.0 -15 -8.5 -4.2 a voh(1) ioh=-1.0ma 4.5-6.0 vdd-1 voh(2) port 0,1,3: cmos output option ioh=-0.1ma 2.5?6.0 vdd-0.5 voh(3) port 7 ioh=-0.4ma 2.5-6.0 vdd-1 voh(4) ioh=-1.0ma 4.5?6.0 vdd-1 high level output voltage voh(5) port a,b,c,d,e,f ioh=-0.1ma 2.5?6.0 vdd-0.5 vol(1) iol=10ma 4.5?6.0 1.5 vol(2) port 0,1,3 iol=1.6ma 2.5?6.0 0.4 vol(3) port 30,31 iol=30ma 4.5?6.0 1.5 vol(4) iol=1ma 4.5?6.0 0.4 vol(5) port 7,8 iol=0.5ma 2.5?6.0 0.4 vol(6) iol=8ma 4.5?6.0 1.5 low level output voltage vol(7) port a,b,c,d,e,f iol=1.4ma 2.5-6.0 0.4 vodls s0?s47 i0=0ma vlcd, 2/3vlcd, 1/3vlcd level output refer to figure 8 2.5?6.0 0 0.2 lcd output voltage regulation vodlc com0?com3 i0=0ma vlcd, 2/3vlcd, 1/2vlcd 1/3vlcd level output refer to figure 8 2.5?6.0 0 0.2 v rlcd(1) resistance per one bias resistor refer to figure 8 2.5?6.0 60 lcd bias resistor rlcd(2) ?resistance per one bias resistor ?1/2r mode refer to figure 8 2.5?6.0 30 k ? continued
lc877372a/64a/56a/48a 16/26 limits parameter symbol pins conditions vdd[v] min. typ. max. unit 4.5?6.0 15 40 70 resistance of pull-up mos tr. rpu ?port 0,1,3,7 ?port a,b,c,d,e,f voh=0.9vdd 2.5-4.5 25 70 150 k ? vhis(1) ?port 1,7 ? res 2.5-6.0 0.1vdd hysterisis voltage vhis(2) port 87 small signal input 2.5-6.0 0.1vdd v pin capacitance cp all pins ?all other terminals connected to vss. ? f =1mhz ? t a =25c 2.5-6.0 10 pf input sensitivity vsen port 87 small signal input 2.5-6.0 0.12vdd vpp
lc877372a/64a/56a/48a 17/26 4. serial input/output characteristics / ta=-30c to +70c, vss1=vss2=vss3=0v limits parameter symbol pins conditions vdd[v] min. typ. max. unit cycle time tsck(1) 4/3 tsckl(1) 2/3 low level pulse width tsckla(1) 2/3 tsckh(1) 2/3 high level pulse width tsckha(1) sck0(p12) refer to figure 6 2.5-6.0 5 cycle time tsck(2) 2 low level pulse width tsckl(2) 1 input clock high level pulse width tsckh(2) sck1(p15) refer to figure 6 2.5-6.0 1 cycle time tsck(3) 4/3 t cyc tsckl(3) 1/2 low level pulse width tsckla(2) 3/4 tsckh(3) 1/2 high level pulse width tsckha(2) sck0(p12) ?cmos output ?refer to figure 6 2.5-6.0 2 tsck cycle time tsck(4) 2 tcyc low level pulse width tsckl(4) 1/2 serial clock output clock high level pulse width tsckh(4) sck1(p15) ?cmos output ?refer to figure 6 2.5-6.0 1/2 tsck 4.5?6.0 0.03 data set-up time t sdi 2.5-6.0 0.1 4.5?6.0 0.03 serial input data hold time t hdi si0(p11), si1(p14), sb0(p11), sb1(p14) ?measured with respect to si0clk leading edge. ?refer to figure 6 2.5-6.0 0.1 4.5?6.0 1/3 tcyc +0.05 serial output output delay time tddo so0(p10), so1(p13), sb0(011), sb1(p14) ?when port is open drain: time delay form sioclk trailing edge to the so data change ?refer to figure 6 2.5-6.0 1/3 tcyc +0.25 s
lc877372a/64a/56a/48a 18/26 5. pulse input conditions / ta=- 30c to +70c, vss1=vss2=vss3=0v limits parameter symbol pins conditions vdd[v] min. typ. max. unit tpih(1) tpil(1) int0(p70), int1(p71), int2(p72) ?condition that interrupt is accepted ?condition that event input to timer 0 is accepted 2.5-6.0 1 tpih(2) tpil(2) int3(p73) (noise rejection ratio is 1/1.) ?condition that interrupt is accepted ?condition that event input to timer 0 is accepted 2.5-6.0 2 tpih(3) tpil(3) int3(p73) (noise rejection ratio is 1/32.) ?condition that interrupt is accepted ?condition that event input to timer 0 is accepted 2.5-6.0 64 tpih(4) tpil(4) int3(p73) (noise rejection ratio is 1/128.) ?condition that interrupt is accepted ?condition that event input to timer 0 is accepted 2.5-6.0 256 tpil(5) tpil(5) micin(p87) ?condition that signal is accepted to small signal detection counter. 2.5-6.0 1 t cyc high/low level pulse width tpil(6) res ?condition that reset is accepted 2.5-6.0 200 s 6. ad converter characteristics / ta=-30c to + 70c, vss1=vss2=vss3=0v limits parameter symbol pins conditions vdd[v] min. typ. max. unit resolution n 3.0?6.0 8 bit absolute precision et (note2) 3.0-6.0 1.5 lsb 4.0-6.0 15.62 (tcyc= 0.488s) 97.92 (tcyc= 3.06s) ad conversion time = 32 tcyc (adcr2=0) (note 3) 3.0-6.0 23.52 (tcyc= 0.735s) 97.92 (tcyc= 3.06s) 4.5-6.0 18.82 (tcyc= 0.294s) 97.92 (tcyc= 1.53s) conversion time tcad ad conversion time = 64 tcyc (adcr2=1) (note 3) 3.0-6.0 47.04 (tcyc= 0.735s) 97.92 (tcyc= 1.53s) s analog input voltage range vain 3.0-6.0 vss vdd v iainh vain=vdd 3.0-6.0 1 analog port input current iainl an0(p80) ?an7(p87) an8(p70) an9(p71) an10(xt1) an11(xt2) an12(v1) an13(v2) an14(v3) vain=vss 3.0-6.0 -1 a (note 2) absolute precision does not include quantizing error (1/2 lsb). (note 3) conversion time means time from executing ad conversion instruction to loading complete digital value to register.
lc877372a/64a/56a/48a 19/26 7. current consumption characteristics / ta=-30c to +70c, vss1=vss2=vss3=0v limits parameter symbol pins conditions vdd[v] min. typ. max unit iddop(1) ?fmcf=10mhz ceramic resonator oscillation ?fsx?tal=32.768khz crystal oscillation ?system clock: cf 10mhz oscillation ?internal rc oscillation stopped. ?frequency variable rc oscillation stopped ?divider : 1/1 4.5?6.0 8.7 30 iddop(2) ?cf1=20mhz external clock ?fsx?tal=32.768khz crystal oscillation ?system clock: cf1 oscillation ?internal rc oscillation stopped. ?frequency variable rc oscillation stopped ?divider :1/2 4.5?6.0 9.5 31 iddop(3) 4.5?6.0 4.2 17 iddop(4) ?fmcf=4mhz ceramic resonator oscillation ?fsx?tal=32.768khz crystal oscillation ?system clock: cf 4mhz oscillation ?internal rc oscillation stopped. ?frequency variable rc oscillation stopped ?divider :1/1 2.5?4.5 2.1 11 iddop(5) 4.5?6.0 0.9 10 iddop(6) ?fmcf=0hz (no oscillation) ?fsx?tal=32.768khz crystal oscillation ?frequency variable rc oscillation stopped ?system clock: rc oscillation ?divider :1/2 2.5?4.5 0.4 6 iddop(7) 4.5-6.0 1.9 12 iddop(8) ?fmcf=0hz (no oscillation) ?fsx?tal=32.768khz crystal oscillation ?internal rc oscillation stopped. ?system clock: 1mhz with frequency variable rc oscillation ?divider :1/2 2.5-4.5 1.4 8 ma iddop(9) 4.5?6.0 40 140 current consumption during normal operation (note 4) iddop(10) vdd1= vdd2= vdd3 ?fmcf=0hz (no oscillation) ?fsx?tal=32.768khz crystal oscillation ?system clock: 32.768khz ?internal rc oscillation stopped. ?frequency variable rc oscillation stopped ?divider :1/2 2.5?4.5 16 60 a continued
lc877372a/64a/56a/48a 20/26 limits parameter symbol pins conditions vdd[v] min. typ. max. unit iddhalt(1) halt mode ?fmcf=10mhz ceramic resonator oscillation ?fsx?tal=32.768khz crystal oscillation ?system clock : cf 10mhz oscillation ?internal rc oscillation stopped ?frequency variable rc oscillation stopped ?divider: 1/1 4.5?6.0 3.8 12 iddhalt(2) halt mode ?cf1=20mhz for external clock ?fsx?tal=32.768khz crystal oscillation ?system clock : cf1 oscillation ?internal rc oscillation stopped ?frequency variable rc oscillation stopped ?divider :1/2 4.5?6.0 4.2 13 iddhalt(3) 4.5?6.0 1.8 6 iddhalt(4) halt mode ?fmcf=4mhz ceramic resonator oscillation ?fsx?tal=32.768khz crystal oscillation ?system clock : cf 4mhz oscillation ?internal rc oscillation stopped ?frequency variable rc oscillation stopped ?divider: 1/1 2.5?4.5 1.0 5 ma iddhalt(5) 4.5?6.0 500 1600 iddhalt(6) halt mode ?fmcf=0hz (oscillation stop) ?fsx?tal=32.768khz crystal oscillation ?internal rc oscillation stopped ?frequency variable rc oscillation stopped ?divider: 1/2 2.5?4.5 250 1300 iddhalt(7) 4.5-6.0 1500 3600 iddhalt(8) halt mode ?fmcf=0hz (no oscillation) ?fsx?tal=32.768khz crystal oscillation ?internal rc oscillation stopped. ?system clock: 1mhz with frequency variable rc oscillation ?divider :1/2 2.5-4.5 1250 3300 iddhalt(9) 4.5?6.0 25 100 current consumption during halt mode (note 4) iddhalt(10) vdd1= vdd2= vdd3 halt mode ?fmcf=0hz (oscillation stop) ?fsx?tal=32.768khz crystal oscillation ?system clock : 32.768khz ?internal rc oscillation stopped ?frequency variable rc oscillation stopped ?divider: 1/2 2.5?4.5 12 60 a continued
lc877372a/64a/56a/48a 21/26 limits parameter symbol pins conditions vdd[v] min. typ. max. unit iddhold(1) 4.5?6.0 0.05 25 current consumption during hold mode iddhold(2) vdd1 hold mode ?cf1=vdd or open (when using external clock) 2.5?4.5 0.015 20 iddhold(3) 4.5?6.0 20 90 current consumption during date/time clock hold mode iddhold(4) vdd1 date/time clock hold mode ?cf1=vdd or open (when using external clock) ?fmx?tal=32.768khz crystal oscillation 2.5?4.5 8 50 a (note 4) the currents through the output transistors and the pull-up mos transistors are ignored.
lc877372a/64a/56a/48a 22/26 main system clock oscillation circuit characteristics the characteristics in the table bellow is based on the following conditions: 1. use the standard evaluation board sanyo has provided. 2. use the peripheral parts with indicated value externally. 3. the peripheral parts value is a recommended value of oscillator manufacturer table 1. main system clock oscillation circuit characteristics using ceramic resonator circuit parameters oscillation stabilizing time frequency manufacturer oscillator c1 [pf] c2 [pf] rd1 [ ? ] operating supply voltage range [v] typ [ms] max [ms] notes cstls10m0g53-b0 (15) (15) 100 4.5-6.0 0.04 0.2 built-in c1, c2 murata cstce10m0g52-r0 (10) (10) 150 4.5-6.0 0.04 0.2 built-in c1, c2 10mhz kyocera ssr10.00cr-s24 (24) (24) 0 4.5-6.0 0.1 0.5 built-in c1, c2 cstls4m00g53-b0 (15) (15) 470 2.5-6.0 0.04 0.2 built-in c1, c2 murata cstcr4m00g53-r0 (15) (15) 150 2.5-6.0 0.07 0.35 built-in c1, c2 4mhz kyocera pbrc4.00hr (30) (30) 0 2.5-6.0 0.05 0.25 built-in c1, c2 the oscillation stabilizing time is a period until the oscillation becomes stable after vdd becomes higher than minimum operating voltage. (refer to figure4) subsystem clock oscillation circuit characteristics the characteristics in the table bellow is based on the following conditions: 1. use the standard evaluation board sanyo has provided. 2. use the peripheral parts with indicated value externally. 3. the peripheral parts value is a recommended value of oscillator manufacturer table 2. subsystem clock oscillation circuit characteristics using crystal oscillator circuit parameters oscillation stabilizing time frequency manufacturer oscillator c3 [pf] c4 [pf] rf [ ? ] rd2 [ ? ] operating supply voltage range [v] typ [s] max [s] notes 32.768khz seiko epson mc-306 18 18 open 390k 2.5-6.0 1.1 3.0 applicable cl value = 14.0pf the oscillation stabilizing time is a period until the oscillation becomes stable after executing the instruction which starts the sub-clock oscillation or after releasing the hold mode. (refer to figure4) (notes) ? since the circuit pattern affects the oscillation frequency, place the oscillation-related parts as close to the oscillation pins as possible with the shortest possible pattern length. figure 1 ceramic oscillation circuit figure 2 crystal oscillation circuit c3 rd2 c4 x?tal xt2 xt1 rf c1 c2 cf cf2 cf1 rd1
lc877372a/64a/56a/48a 23/26 figure 3 ac timing measurement point reset time and oscillation stable time hold release signal and oscillation stable time 0.5vdd power supply res internal rc oscillation cf1 , cf2 xt1 , xt2 operation mode reset time tmscf tmsxtal unfixed reset instruction execution mode vdd vdd limit 0v internal rc oscillation cf1,cf2 xt1,xt2 operation mode hold release signal without hold release signal hold release signal valid tmscf tmsxtal hold halt
lc877372a/64a/56a/48a 24/26 figure 4 oscillation stabilizing time figure 5 reset circuit figure 6 serial input / output wave form (note) select c res and r res value to assure that at least 200s reset time is generated after the vdd becomes higher than the minimum operating volta g e. c res vdd r res res sioclk datain dataout di0 di1 di2 di3 di4 di5 di6 di7 di8 do0 do1 do2 do3 do4 do5 do6 do7 do8 data ram transmission period (only sio0) sioclk datain dataout tsck tsckl tsckh tsdi thdi tddo sioclk datain dataout tddo tsdi thdi tsckla tsckha data ram transmission period (only sio0)
lc877372a/64a/56a/48a 25/26 figure 7 pulse input timing figure 8 lcd bias resistor tpil tpih vlcd sw : on ( vlcd=vdd ) 2/3vlcd 1/2vlcd 1/3vlcd sw : on/off(programmable) vdd gnd rlcd rlcd rlcd rlcd rlcd rlcd rlcd rlcd rlcd rlcd
lc877372a/64a/56a/48a ps no.7157-26 / 26 this catalog provies information as of nov,2001. specifications and information herein are subject to change without notice

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