View X24026T21-27_7060227.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

? xicor, inc. 1998 patents pending 7020-1.3 6/15/99 t2/c0/d3 sh 1 characteristics subject to change without notice 2k x24026 256 x 8 bit serial e2prom features 2.7v to 5.5v power supply low power cmos active current less than 1ma standby current less than 50? internally organized 256 x 8 self timed write cycle typical write cycle time of 5 ms 2 wire serial interface bidirectional data transfer protocol four byte page write operation minimizes total write time per byte high reliability endurance: 100,000 cycles data retention: 100 years esd protection > 2kv description the x24026 is a cmos 2048 bit serial e 2 prom, inter- nally organized 256 x 8. the x24026 features a serial interface and software protocol allowing operation on a simple two wire bus. xicor e 2 proms are designed and tested for applications requiring extended endurance. inherent data retention is greater than 100 years. available in dice form, smart card module with iso 7816 compatible pinout. iso 7816 compatible functional diagram start stop logic control logic slave address register +comparator h.v. generation timing & control word address counter xdec ydec d out ack e prom 2 64 x 32 data register start cycle v cc r/w pin v ss sda d out load inc ck 8 7020 frm 01 scl
x24026 2 pin descriptions serial clock (scl) the scl input is used to clock all data into and out of the device. serial data (sda) sda is a bidirectional pin used to transfer data into and out of the device. it is an open drain output and may be wire-ored with any number of open drain or open collector outputs. an open drain output requires the use of a pull-up resistor. for selecting typical values, refer to the guidelines for calculating typical values of bus pull-up resistors graph. die configuration pin descriptions 7020 frm t01 symbol description sda serial data scl serial clock v ss ground v cc +5v v cc v ss sda scl sda x24026 die revision a .055 x .079 7020 frm 02 v cc v ss nc nc sda scl 35mm tape smart card module pin configuration
x24026 3 device operation the x24026 supports a bidirectional bus oriented proto- col. the protocol de?es any device that sends data onto the bus as a transmitter and the receiving device as the receiver. the device controlling the transfer is a master and the device being controlled is the slave. the master will always initiate data transfers and provide the clock for both transmit and receive operations. therefore, the x24026 will be considered a slave in all applications. clock and data conventions data states on the sda line can change only during scl low. sda state changes during scl high are reserved for indicating start and stop conditions. refer to figures 1 and 2. start condition all commands are preceded by the start condition, which is a high to low transition of sda when scl is high. the x24026 continuously monitors the sda and scl lines for the start condition and will not respond to any command until this condition has been met. figure 1. data validity scl sda data stable data change 7020 frm 03
x24026 4 stop condition all communications must be terminated by a stop condi- tion, which is a low to high transition of sda when scl is high. the stop condition is also used by the x24026 to place the device in the standby power mode after a read sequence. a stop condition can only be issued after the transmitting device has released the bus. acknowledge acknowledge is a software convention used to indicate successful data transfer. the transmitting device, either master or slave, will release the bus after transmitting eight bits. during the ninth clock cycle the receiver will pull the sda line low to acknowledge that it received the eight bits of data. refer to figure 3. the x24026 will respond with an acknowledge after rec- ognition of a start condition and its slave address. if both the device and a write operation have been selected, the x24026 will respond with an acknowledge after the receipt of each subsequent eight bit word. in the read mode the x24026 will transmit eight bits of data, release the sda line and monitor the line for an acknowledge. if an acknowledge is detected and no stop condition is generated by the master, the x24026 will continue to transmit data. if an acknowledge is not detected, the x24026 will terminate further data trans- missions. the master must then issue a stop condition to return the x24026 to the standby power mode and place the device into a known state. figure 2. definition of start and stop figure 3. acknowledge response from receiver device addressing following a start condition the master must output the address of the slave it is accessing. the most signi?ant four bits of the slave are the device type identi?r (see figure 4). for the x24026 this is ?ed as 1010[b]. scl sda start bit stop bit 7020 frm 04 7020 frm 05 scl from master data output from transmitter 1 89 data output from receiver start acknowledge
x24026 5 figure 4. slave address the next three signi?ant bits are reserved address bits. the last bit of the slave address de?es the operation to be performed. when set to one a read operation is selected, when set to zero a write operations is selected. following the start condition, the x24026 monitors the sda bus comparing the slave address being transmitted with its slave address. upon a correct compare the x24026 outputs an acknowledge on the sda line. depending on the state of the r/w bit, the x24026 will execute a read or write operation. write operations byte write for a write operation, the x24026 requires a second address ?ld. this address ?ld is the word address, comprised of eight bits, providing access to any one of the 256 words of memory. upon receipt of the word address the x24026 responds with an acknowledge, and awaits the next eight bits of data, again responding with an acknowledge. the master then terminates the transfer by generating a stop condition, at which time the x24026 begins the internal write cycle to the nonvolatile memory. while the internal write cycle is in progress the x24026 inputs are disabled, and the device will not respond to any requests from the master. refer to figure 5 for the address, acknowledge and data transfer sequence. figure 5. byte write figure 6. page write 1 7020 frm 06 0 10000 r/w device type identifier reserve address bits bus activity: master sda line x24026 s t a r t slave address s s t o p p a c k a c k a c k word address data 7020 frm 07 bus activity: bus activity: master sda line x24026 s t a r t slave address s s t o p p a c k a c k a c k a c k a c k word address (n) data n data n+1 data n+3 note: in this example n = xxxx 000 (b); x = 1 or 0 7020 frm 08 bus activity:
x24026 6 page write the x24026 is capable of a four byte page write opera- tion. it is initiated in the same manner as the byte write operation, but instead of terminating the write cycle after the ?st data word is transferred, the master can transmit up to three more words. after the receipt of each word, the x24026 will respond with an acknowledge. after the receipt of each word, the two low order address bits are internally incremented by one. the high order six bits of the address remain constant. if the master should transmit more than four words prior to generating the stop condition, the address counter will ?oll over and the previously written data will be overwritten. as with the byte write operation, all inputs are disabled until comple- tion of the internal write cycle. refer to figure 6 for the address, acknowledge and data transfer sequence. acknowledge polling the disabling of the inputs, during the internal write oper- ation, can be used to take advantage of the typical 5 ms write cycle time. once the stop condition is issued to indi- cate the end of the hosts write operation the x24026 ini- tiates the internal write cycle. ack polling can be initiated immediately. this involves issuing the start condition fol- lowed by the slave address for a write operation. if the x24026 is still busy with the write operation no ack will be returned. if the x24026 has completed the write oper- ation an ack will be returned and the master can then proceed with the next read or write operation. read operations read operations are initiated in the same manner as write operations with the exception that the r/w bit of the slave address is set to a one. there are three basic read operations: current address read, random read and sequential read. it should be noted that the ninth clock cycle of the read operation is not a ?on? care. to terminate a read opera- tion, the master must either issue a stop condition during the ninth cycle or hold sda high during the ninth clock cycle and then issue a stop condition. flow 1. ack polling sequence 7020 frm 09 write operation completed enter ack polling issue start issue slave_ address and r/w = 0 ack returned? next operation a write? issue byte address proceed issue stop no yes yes proceed issue stop no
x24026 7 current address read internally the x24026 contains an address counter that maintains the address of the last word accessed, incre- mented by one. therefore, if the last access (either a read or write) was to address n, the next read operation would access data from address n + 1. upon receipt of the slave address with the r/w bit set to one, the x24026 issues an acknowledge and transmits the eight bit word during the next eight clock cycles. the master terminates this transmission by issuing a stop condition, omitting the ninth clock cycle acknowledge. refer to figure 7 for the sequence of address, acknowledge and data transfer. random read random read operations allow the master to access any memory location in a random manner. prior to issuing the slave address with the r/w bit set to one, the master must ?st perform a ?ummy write operation. the master issues the start condition, and the slave address followed by the word address it is to read. after the word address acknowledge, the master immediately reissues the start condition and the slave address with the r/w bit set to one. this will be followed by an acknowledge from the x24026 and then by the eight bit word. the master termi- nates this transmission by issuing a stop condition, omit- ting the ninth clock cycle acknowledge. refer to figure 8 for the address, acknowledge and data transfer sequence. figure 7. current address read figure 8. random read 7020 frm 10 s t a r t s s t o p p a c k bus activity: master sda line x24026 bus activity: slave address data 7020 frm 11 s t a r t s s t o p p a c k a c k a c k word address n slave address data n s t a r t s bus activity: master sda line x24026 bus activity: slave address
x24026 8 sequential read sequential read can be initiated as either a current address read or random access read. the ?st word is transmitted as with the other modes, however, the master now responds with an acknowledge, indicating it requires additional data. the x24026 continues to output data for each acknowledge received. the master terminates this transmission by issuing a stop condition, omitting the ninth clock cycle acknowledge. the data output is sequential, with the data from address n followed by the data from n + 1. the address counter for read operations increments all address bits, allowing the entire memory contents to be serially read during one operation. at the end of the address space (address 255), the counter ?olls over to address 0 and the x24026 continues to output data for each acknowledge received. refer to figure 9 for the address, acknowledge and data transfer sequence. figure 9. sequential read 7020 frm 12 a c k a c k s t o p p data n a c k data n+1 a c k bus activity: master sda line x24026 bus activity: slave address data n+2 data n+x
x24026 9 absolute maximum ratings* temperature under bias...................?5? to +135? storage temperature ........................?5? to +150? voltage on any pin with respect to v ss ............................. ?.0v to +7.0v d.c. output current .............................................5 ma lead temperature (soldering, 10 seconds) ...... 300? *comment stresses above those listed under ?bsolute maximum ratings may cause permanent damage to the device. this is a stress rating only and the functional operation of the device at these or any other conditions above those indicated in the operational sections of this speci?ation is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reli- ability. recommended operating conditions 7020 frm t09 7020 frm t10 temperature min. max. commercial 0? 70? supply voltage limits x24026 4.5v to 5.5v x24026-2.7 2.7v to 5.5v d.c. operating characteristics (over recommended operating conditions unless otherwise specified). 7020 frm t02 capacitance t a = 25?, f = 1 mhz, v cc = 5v 7020 frm t04 notes: (1) must perform a stop command prior to measurement. (2) v il min. and v ih max. are for reference only and are not tested. (3) this parameter is periodically sampled and not 100% tested. symbol parameter limits units test conditions min. max. l cc1 power supply current (read) 1 ma scl = v cc x 0.1/v cc x 0.9 levels @ 100 khz, sda = open l cc2 power supply current (write) 2 i sb (1) standby current 50 ? scl = sda = v cc ?0.3v, v cc = 5v ?0% i sb (2) standby current 30 ? scl = sda = v cc ?0.3v, v cc = 3v i li input leakage current 10 ? v in = gnd to v cc i lo output leakage current 10 ? v out = gnd to v cc v ll (2) input low voltage ?.0 v cc x 0.3 v v ih (2) input high voltage v cc x 0.7 v cc + 0.5 v v ol output low voltage 0.4 v i ol = 3 ma symbol parameter max. units test conditions c i/o (3) input/output capacitance (sda) 8 pf v i/o = 0v c in (3) input capacitance (scl) 6 pf v in = 0v
x24026 10 a.c. conditions of test 7020 pgm t05 equivalent a.c. load circuit input pulse levels v cc x 0.1 to v cc x 0.9 input rise and fall times 10 ns input and output timing levels v cc x 0.5 7020 frm 13 1533 ? output 100pf 5.0v a.c. characteristics (over recommended operating conditions) data input timing 7020 frm t06 bus timing power-up timing 7020 frm t07 notes: (4) t pur and t puw are the delays required from the time v cc is stable until the specified operation can be initiated. these parameters are periodically sampled and not 100% tested. symbol parameter min. max. units f scl scl clock frequency 0 100 khz t i noise suppression time constant at scl, sda inputs 100 ns t aa scl low to sda data out valid 0.3 3.5 ? t buf time the bus must be free before a new transmission can start 4.7 ? t hd:sta start condition hold time 4.0 ? t low clock low period 4.7 ? t high clock high period 4.0 ? t su:sta start condition setup time 4.7 ? t hd:dat data in hold time 0 s t su:dat data in setup time 250 ns t r sda and scl rise time 1 s t f sda and scl fall time 300 ns t su:sto stop condition setup time 4.7 ? t dh data out hold time 300 ns symbol parameter max. units t pur (4) power-up to read operation 1 ms t puw (4) power-up to write operation 5 ms 7020 frm 14 t su:sta t hd:sta t hd:dat t su:dat t low t su:sto t r t buf scl sda in sda out t dh t aa t f t high
x24026 11 write cycle limits 7020 frm t08 the write cycle time is the time from a valid stop condition of a write sequence to the end of the internal erase/program cycle. during the write cycle, the x24026 bus interface circuits are disabled, sda is allowed to remain high, and the device does not respond to its slave address. write cycle timing notes: (5) typical values are for t a = 25? and nominal supply voltage (5v) (6) t wr is the minimum cycle time from the system perspective when polling techniques are not used. it is the maximum time the device requires to perform the internal write operation. symbol parameter min. typ. (5) max. units t wr (6) write cycle time 5 10 ms 7020 frm 15 scl sda 8th bit word n ack t wr stop condition start condition x24026 address guidelines for calculating typical values of bus pull-up resistors 7020 frm 16 120 100 80 40 60 20 20 40 60 80 100 120 0 0 resistance (k ? ) bus capacitance (pf) min. resistance max. resistance r max = c bus t r r min = i ol min v cc max =1.8k ?
x24026 12 6 pad chip on board smart card module type x smartcard module generic 6 contact module 8 1.3 1.3 0.2 0.2 10.62 1.31 1.31 35mm tape 9.500 35 4.75 31.83 14.20
x24026 13 ordering information x24026: 256 x 8 cmos serial e 2 prom device x24026 x x temperature range blank = commercial = 0 c to +70 c package t20 = 35mm tape:m3, 6 pin module, 10k/reel limited warranty devices sold by xicor, inc. are covered by the warranty and patent indemni?ation provisions appearing in its terms of sale onl y. xicor, inc. makes no warranty, express, statutory, implied, or by description regarding the information set forth herein or regarding the f reedom of the described devices from patent infringement. xicor, inc. makes no warranty of merchantability or ?ness for any purpose. xicor, inc. reserves the right to discontinue production and change speci?ations and prices at any time and without notice. xicor, inc. assumes no responsibility for the use of any circuitry other than circuitry embodied in a xicor, inc. product. no o ther circuits, patents, licenses are implied. u.s. patents xicor products are covered by one or more of the following u.s. patents: 4,263,664; 4,274,012; 4,300,212; 4,314,265; 4,326,134; 4,393,481; 4,404,475; 4,450,402; 4,486,769; 4,488,060; 4,520,461; 4,533,846; 4,599,706; 4,617,652; 4,668,932; 4,752,912; 4,829, 482; 4,874 , 967; 4,883, 976. foreign patents and additional patents pending. life related policy in situations where semiconductor component failure may endanger life, system designers using this product should design the sy stem with appropriate error detection and correction, redundancy and back-up features to prevent such an occurence. xicor's products are not authorized for use in critical components in life support devices or systems. 1. life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) su pport or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a signi?ant injury to the user. 2. a critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. h = dice (waffle packs) ? v cc range 2.7 = 2.7v to 5.5v w = wafer form x = cob smartcard module blank = 4.5v to 5.5v t21 = 35mm tape:m3, 6 pin module, 5k/reel t22 = 35mm tape:m3, 6 pin module, 2k/reel

▲Up To Search▲

Price & Availability of X24026T21-27

	To Download X24026T21-27 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .