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lxt305a integrated t1/e1 short-haul transceiver with transmit ja datasheet the lxt305a is a fully integrated transceiver for both north american 1.544 mbps (t1) and international 2.048 mbps (e1) applications. transmit pulse shapes (t1 or e1) are selectable for various line lengths and cable types. the lxt305a provides transmit jitter attenuation starting at 3 hz, and is microprocessor controllable through a serial interface. it is especially well suited for applications in which the t1/e1 signals are demultiplexed from a higher rate service such as ds3 or sonet/sdh. this demultiplexing results in a gapped clock which the lxt305a smooths out. the lxt305a, an advanced double-poly, double-metal cmos device, requires only a single +5v power supply. applications product features sonet/sdh equipment m13 multiplexers digital microwave radio pcm/voice channel banks data channel bank/concentrator t1/e1 multiplexer digital access and cross-connect systems (dacs) computer to pbx interface (cpi & dmi) high-speed data transmission lines interfacing customer premises equipment to a csu digital loop carrier (dlc) terminals low power consumption (400 mw maximum) constant low output impedance transmitter, regardless of data pattern (3 ? typical) high transmit and receive return loss exceeds ets 300166 and g.703 compatible with most popular pcm framers line driver, data recovery and clock recovery functions minimum receive signal of 500 mv selectable slicer levels (t1/e1) improve snr programmable transmit equalizer shapes pulses to meet dsx-1 pulse template from 0 to 655 ft local and remote loopback functions transmit driver performance monitor (dpm) output receive monitor with analog/digital loss of signal (los) output per g.775 receiver jitter tolerance 0.4 ui from 40 khz to 100 khz transmit jitter attenuation starting at 3 hz meets ctr 12/13 serial control interface available in 28-pin dip and plcc as of january 15, 2001, this document replaces the level one document order number: 249068-001 lxt305a ? integrated t1/e1 short-haul transceiver with transmit ja . january 2001
datasheet information in this document is provided in connection with intel ? products. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. except as provided in intel?s terms and conditions of sale for such products, inte l assumes no liability whatsoever, and intel disclaims any express or implied warranty, relating to sale and/or use of intel products including liabil ity or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property righ t. intel products are not intended for use in medical, life saving, or life sustaining applications. intel may make changes to specifications and product descriptions at any time, without notice. designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." int el reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. the lxt305a may contain design defects or errors known as errata which may cause the product to deviate from published specific ations. current characterized errata are available on request. contact your local intel sales office or your distributor to obtain the latest specifications and before placing your product o rder. copies of documents which have an ordering number and are referenced in this document, or other intel literature may be obtaine d by calling 1-800- 548-4725 or by visiting intel?s website at http://www.intel.com. copyright ? intel corporation, 2001 *third-party brands and names are the property of their respective owners.
datasheet 3 integrated t1/e1 short-haul transceiver with transmit ja ? lxt305a contents 1.0 pin assignments and signal descriptions ...................................................... 6 2.0 functional description ............................................................................................. 9 2.1 power requirements............................................................................................. 9 2.2 reset operation .................................................................................................... 9 2.3 receiver ................................................................................................................ 9 2.4 transmitter ..........................................................................................................10 2.4.1 jitter attenuation ....................................................................................10 2.4.2 driver performance monitor ...................................................................11 2.4.3 line code ...............................................................................................11 2.5 operating modes.................................................................................................12 2.5.1 host mode operation .............................................................................12 2.5.2 hardware mode operation .....................................................................14 2.5.3 diagnostic mode operation....................................................................14 2.5.3.1 transmit all ones ......................................................................14 2.5.3.2 remote loopback .....................................................................14 2.5.3.3 local loopback .........................................................................14 3.0 application information .........................................................................................16 3.1 1.544 mbps t1 interface applications .................................................................16 3.2 2.048 mbps e1 interface applications.................................................................16 3.3 line protection ....................................................................................................17 4.0 test specifications ..................................................................................................20 5.0 mechanical specifications ....................................................................................27
lxt305a ? integrated t1/e1 short-haul transceiver with transmit ja 4 datasheet figures 1 lxt305a block diagram....................................................................................... 5 2 lxt305a pin assignments and package markings.............................................. 6 3 50% ami coding ................................................................................................. 11 4 lxt305a serial interface data structure............................................................ 13 5 typical lxt305a 1.544 mbps t1 host mode application................................... 18 6 typical lxt305a 120 w 2.048 mbps e1 hardware mode application ............... 19 7 typical receive jitter tolerance ......................................................................... 22 8 lxt305a transmit jitter transfer performance (typical)................................... 23 9 lxt305a receive clock timing diagram........................................................... 24 10 lxt305a transmit clock timing diagram.......................................................... 24 11 lxt305a serial data input timing diagram ....................................................... 25 12 lxt305a serial data output timing diagram .................................................... 26 13 package specifications ....................................................................................... 27 tables 1 lxt305a pin descriptions .................................................................................... 6 2 lxt305a serial data output bits (see figure 5 )................................................ 11 3 valid clke settings............................................................................................ 12 4 equalizer control inputs...................................................................................... 13 5 lxt305a crystal specifications (external) ......................................................... 14 6 t1/e1 input/output configurations...................................................................... 17 7 absolute maximum ratings ................................................................................ 20 8 recommended operating conditions and characteristics ................................. 20 9 electrical characteristics (under recommended operating conditions) ........... 20 10 analog characteristics (under recommended operating conditions) ............... 21 11 lxt305a receive timing characteristics (see figure 9 )................................... 23 12 lxt305a master clock and transmit timing characteristics (see figure 10 )...24 13 lxt305a serial i/o timing characteristics (see figure 11 and figure 12 )........ 25
integrated t1/e1 short-haul transceiver with transmit ja ? lxt305a datasheet 5 figure 1. lxt305a block diagram transmit driver control peak detector rtip rring mtip mring data slicers line driver ttip tring timing recovery internal clock generator data recovery receive monitor jitter attenuator mode tpos tneg tclk mclk rpos rneg xtalin xtalout rclk dpm los hardware host int sdi sdo cs sclk clke ec1 ec2 ec3 rloop lloop taos equalizer control
lxt305a ? integrated t1/e1 short-haul transceiver with transmit ja 6 datasheet 1.0 pin assignments and signal descriptions figure 2. lxt305a pin assignments and package markings package topside markings marking definition part # unique identifier for this product family. rev # identifies the particular silicon ? stepping ? ? refer to the specification update for additional stepping information. lot # identifies the batch. fpo # identifies the finish process order. table 1. lxt305a pin descriptions pin # sym i/o 1 description 1mclkdi master clock. a 1.544 or 2.048 mhz clock input used to generate internal clocks. upon loss of signal (los), rclk is derived from mclk. if mclk is not applied, this pin should be grounded. 2tclkdi transmit clock. transmit clock input. tpos and tneg are sampled on the falling edge of tclk. when tclk is inactive, the transmitter powers down. 3tposdi transmit positive data. input for positive pulse to be transmitted on the cable line. 4tnegdi transmit negative data. input for negative pulse to be transmitted on the cable line. 1. entries in i/o column are: di = digital input; do = digital output; ai = analog input; ao = analog output; s = supply. mclk tclk tpos tneg mode rneg rpos rclk xtalin xtalout dpm los ttip tgnd 28 27 26 25 24 23 22 21 20 19 18 17 16 15 1 2 3 4 5 6 7 8 9 10 11 12 13 14 clke / taos sclk / lloop cs / rloop sdo / ec3 sdi / ec2 int / ec1 rgnd rv+ rring rtip mring mtip tring tv+ LXT305ANE mode rneg rpos rclk xtalin xtalout dpm 25 24 23 22 21 20 19 5 6 7 8 9 10 11 12 13 14 15 16 17 18 4 3 2 1 28 27 26 sdo / ec3 sdi / ec2 int / ec1 rgnd rv+ rring rtip tneg tpos tclk mclk clke / taos sclk / lloop cs / rloop los ttip tgnd tv+ tring mtip mring lxt305xe xx xxxxxx xxxxxxxx
integrated t1/e1 short-haul transceiver with transmit ja ? lxt305a datasheet 7 5modedi mode select. setting mode high puts the lxt305a in the host mode. in the host mode, the serial interface is used to control the lxt305a and determine its status. setting mode low puts the lxt305a in the hardware (h/w) mode. in the hardware mode, the serial interface is disabled and hard-wired pins are used to control configuration and report status. 6 rneg do receive negative data; receive positive data. received data outputs. a signal on rneg corresponds to receipt of a negative pulse on rtip and rring. a signal on rpos corresponds to receipt of a positive pulse on rtip and rring. rneg and rpos outputs are non-return-to-zero (nrz). both outputs are stable and valid on the rising edge of rclk. in the host mode, clke determines the clock edge at which these outputs are stable and valid. in the hardware mode both outputs are stable and valid on the rising edge of rclk. 7rposdo 8rclkdo recovered clock. this is the clock recovered from the signal received at rtip and rring. 9xtalinai crystal input; crystal output. an external crystal operating at four times the bit rate (6.176 mhz for dsx-1, 8.192 mhz for e1 applications with an 18.7pf load) is required to enable the jitter attenuation function of the lxt305a. these pins may also be used to disable the jitter attenuator by connecting the xtalin pin to the positive supply through a resistor, and tying the xtalout pin to ground. 10 xtalout ao 11 dpm do driver performance monitor. dpm goes high when the transmit monitor loop (mtip and mring) does not detect a signal for 63 2 clock periods. dpm remains high until a signal is detected. 12 los do loss of signal. los goes high when 175 consecutive spaces have been detected on rtip and rring. los returns low when the received signal reaches 12.5% ones density (based on 4 ones in any 32-bit period) with no more than 15 consecutive zeros. 13 ttip ao transmit tip; transmit ring. differential driver outputs. these low impedance outputs achieve maximum power savings through a 1:1.15 transformer (t1), or a 1:1 (75 ? ) or 1:1.26 (120 ? ) transformer (e1) without additional components. to provide higher return loss, resistors may be used in series with a transformer as specified in application information. 16 tring ao 14 tgnd s transmit ground. ground return for the transmit drivers power supply tv+. 15 tv+ s transmit power supply. +5 vdc power supply input for the transmit drivers. tv+ must not vary from rv+ by more than 0.3 v. 17 mtip ai monitor tip; monitor ring. these pins are used to monitor the tip and ring transmit outputs. the transceiver can be connected to monitor its own output or the output of another lxt305a on the board. host mode only: to prevent false interrupts in the host mode if the monitor is not used, apply a clock signal to one of the monitor pins and tie the other monitor pin to approximately the clock ? s mid-level voltage. the monitor clock can range from 100 khz to the tclk frequency. 18 mring ai 19 rtip ai receive tip; receive ring. the ami signal received from the line is applied at these pins. a center-tapped, center-grounded, 2:1 step-up transformer is required on these pins. data and clock from the signal applied at these pins are recovered and output on the rpos, rneg and rclk pins. 20 rring ai 21 rv+ s receive power supply. +5 vdc power supply for all circuits except the transmit drivers (transmit drivers are supplied by tv+). 22 rgnd s receive ground. ground return for power supply rv+. 23 int do interrupt (host mode) . this lxt305a host mode output goes low to flag the host processor when los or dpm go active. int is an open-drain output and should be tied to power supply rv+ through a resistor. int is reset by clearing the respective register bit (los and/or dpm). ec1 di equalizer control 1 (h/w mode) . the signal applied at this pin in the lxt305a hardware mode is used in conjunction with ec2 and ec3 inputs to determine shape and amplitude of ami output transmit pulses. table 1. lxt305a pin descriptions (continued) pin # sym i/o 1 description 1. entries in i/o column are: di = digital input; do = digital output; ai = analog input; ao = analog output; s = supply.
lxt305a ? integrated t1/e1 short-haul transceiver with transmit ja 8 datasheet 24 sdi di serial data in (host mode) . the serial data input stream is applied to this pin when the lxt305a operates in the host mode. sdi is sampled on the rising edge of sclk. ec2 di equalizer control 2 (h/w mode) . the signal applied at this pin in the lxt305a hardware mode is used in conjunction with ec1 and ec3 inputs to determine shape and amplitude of ami output transmit pulses. 25 sdo do serial data out (host mode) . the serial data from the on-chip register is output on this pin in the lxt305a host mode. if clke is high, sdo is valid on the rising edge of sclk. if clke is low sdo is valid on the falling edge of sclk. this pin goes to a high-impedance state when the serial port is being written to and when cs is high. ec3 di equalizer control 3 (h/w mode) . the signal applied at this pin in the lxt305a hardware mode is used in conjunction with ec1 and ec2 inputs to determine shape and amplitude of ami output transmit pulses. 26 cs di chip select (host mode) . this input is used to access the serial interface in the lxt305a host mode. for each read or write operation, cs must transition from high to low, and remain low. rloop di remote loopback (h/w mode) . this input controls loopback functions in the lxt305a hardware mode. setting rloop high enables the remote loopback mode. setting both rloop and lloop high causes a reset. 27 sclk di serial clock (host mode) . this clock is used in the lxt305a host mode to write data to or read data from the serial interface registers. lloop di local loopback (h/w mode) . this input controls loopback functions in the lxt305a hardware mode. setting lloop high enables the local loopback mode. 28 clke di clock edge (host mode) . setting clke high causes rpos and rneg to be valid on the falling edge of rclk, and sdo to be valid on the rising edge of sclk. when clke is low, rpos and rneg are valid on the rising edge of rclk, and sdo is valid on the falling edge of sclk. taos di transmit all ones (h/w mode) . when set high, taos causes the lxt305a (hardware mode) to transmit a continuous stream of marks at the mclk frequency. activating taos causes tpos and tneg inputs to be ignored. taos is inhibited during remote loopback. table 1. lxt305a pin descriptions (continued) pin # sym i/o 1 description 1. entries in i/o column are: di = digital input; do = digital output; ai = analog input; ao = analog output; s = supply.
integrated t1/e1 short-haul transceiver with transmit ja ? lxt305a datasheet 9 2.0 functional description the lxt305a is a fully integrated pcm transceiver for both 1.544 mbps (dsx-1) and 2.048 mbps (e1) applications. it allows full-duplex transmission of digital data over existing twisted-pair installations. the first page of this data sheet shows a simplified block diagram of the lxt305a. the lxt305a transceiver interfaces with either two twisted-pair lines or two coax cables (one for transmit, one for receive) through standard pulse transformers and appropriate resistors. 2.1 power requirements the lxt305a is a low-power cmos device. it operates from a single +5 v power supply which can be connected externally to both the transmitter and receiver. however, the two inputs must be within .3v of each other, and decoupled to their respective grounds separately. refer to application information for typical decoupling circuitry. isolation between the transmit and receive circuits is provided internally. the transmitter powers down to conserve power when the required clock input is not supplied. the lxt305a enters the power down mode during normal operation and local loopback if tclk is not supplied, and during taos if mclk is not supplied. 2.2 reset operation upon power up, the transceiver is held static until the power supply reaches approximately 3 v. upon crossing this threshold, the device begins a 32 ms reset cycle to calibrate the transmit and receive delay lines and lock the phase lock loop (pll) to the receive line. a reference clock is required to calibrate the delay lines. mclk provides the receiver reference. the crystal oscillator provides the transmitter reference. if the crystal oscillator is grounded, mclk is used as the transmitter reference clock. the transceiver can also be reset from the host or hardware mode. in host mode, reset is commanded by simultaneously writing rloop and lloop to the register. in hardware mode, reset is commanded by holding the rloop and lloop pins high simultaneously for 200 ns. hardware mode reset is initiated on the falling edge of the reset request. in either mode, reset clears and sets all registers to 0 and then begins calibration. 2.3 receiver the lxt305a receives the signal input from one twisted-pair line (or coax cable) on each side of a center-grounded transformer. positive pulses are detected at rtip and negative pulses are detected at rring. recovered data is output at rpos and rneg, and the recovered clock is output at rclk. refer to test specifications for lxt305a receiver timing. the signal received at rtip and rring is processed through the peak detector and data slicers. the peak detector samples the inputs and determines the maximum value of the received signal. a percentage of the peak value is provided to the data slicers as a threshold level to ensure optimum signal-to-noise ratio. for t1 applications (determined by equalizer control inputs ec1 - ec3
lxt305a ? integrated t1/e1 short-haul transceiver with transmit ja 10 datasheet 000 or 001) the threshold is set to 70% of the peak value. this threshold is maintained above 65% for up to 15 successive zeros over the range of specified operating conditions. for e1 applications (ec inputs = 000 or 001) the threshold is 50%. the receiver is capable of accurately recovering signals with up to -13.6 db of attenuation (from 2.4 v), corresponding to a received signal level of approximately 500 mv. maximum line length is 1500 feet of abam cable (approximately 6 db of attenuation). regardless of received signal level, the peak detectors are held above a minimum level of.3 v to provide immunity from impulsive noise. after processing through the data slicers, the received signal is routed to the data and clock recovery sections, and to the receive monitor. the data and clock recovery circuits are highly tolerant with an input jitter tolerance significantly better than required by pub 62411. refer to test specifications for additional information. the receiver monitor loads a digital counter at the rclk frequency. the count is incremented each time a zero is received, and reset to zero each time a one (mark) is received. upon receipt of 175 consecutive zeros the los pin goes high, and a smooth transition replaces the rclk output with the mclk. received marks are output regardless of the los status, but the los pin will not reset until the ones density reaches 12.5%. this level is based on receipt of at least 4 ones in any 32-bit period with no more than 15 consecutive zeros. 2.4 transmitter data received for transmission onto the line is clocked serially into the device at tpos and tneg. input synchronization is supplied by the transmit clock (tclk). the transmitted pulse shape is determined by equalizer control signals ec1 through ec3 as shown in table 4 . refer to test specifications for master and transmit clock timing characteristics. shaped pulses are applied to the ami line driver for transmission onto the line at ttip and tring. equalizer control signals may be hardwired in the hardware mode, or input as part of the serial data stream (sdi) in the host mode pulses can be shaped for either 1.544 or 2.048 mbps applications. 1.544 mbps pulses for dsx-1 applications can be programmed to match line lengths from 0 to 655 feet of abam cable. the lxt305a also matches fcc and ecsa specifications for csu applications. 2.048 mbps pulses can drive coaxial or shielded twisted-pair lines. 2.4.1 jitter attenuation jitter attenuation of the lxt305a transmit outputs is provided by a jitter attenuation loop (jal) and an elastic store (es). an external crystal oscillating at 4 times the bit rate provides clock stabilization. refer to application information for crystal specifications. the es is a 32 x 2-bit register. transmit data is clocked into the es with the transmit clock (tclk) signal, and clocked out of the es with the dejittered clock from the jal. when the bit count in the es is within two bits of overflowing or underflowing, the es adjusts the output clock by 1/8 of a bit period. the es produces an average delay of 16 bits in the receive path.
integrated t1/e1 short-haul transceiver with transmit ja ? lxt305a datasheet 11 2.4.2 driver performance monitor the transceiver incorporates a driver performance monitor (dpm). mtip and mring connect in parallel with ttip and tring at the output transformer. the dpm output goes high upon detection of 63 consecutive zeros. it is reset when a one is detected on the transmit line, or when a reset command is received. 2.4.3 line code the lxt305a transmits data as a 50% ami line code as shown in figure 3 . the output driver maintains a constant low output impedance regardless of whether it is driving marks or spaces. this well controlled output impedance provides excellent return loss (> 18 db) when used with external 9.1 ? precision ( 1% accuracy) in series with a transmit transformer with a turns ratio of 1:2.3 ( 2% accuracy). series resistors also provide increased surge protection and reduced short circuit current flow. figure 3. 50% ami coding table 2. lxt305a serial data output bits (see figure 5 ) bit d5 bit d6 bit d7 status 0 0 0 reset has occurred, or no program input. 001taos is active. 0 1 0 local loopback is active. 0 1 1 taos and local loopback are active. 1 0 0 remote loopback is active. 101 dpm has changed state since last clear dpm occurred. 110 los has changed state since last clear los occurred. 111 los and dpm have both changed state since last clear dpm and clear los occurred. ttip bit cell 1 1 0 tring
lxt305a ? integrated t1/e1 short-haul transceiver with transmit ja 12 datasheet 2.5 operating modes the lxt305a can be controlled through hard-wired pins (hardware mode) or by a microprocessor through a serial interface (host mode). the mode of operation is set by the mode pin logic level. the lxt305a can also be commanded to operate in one of several diagnostic modes. 2.5.1 host mode operation to allow a host microprocessor to access and control the lxt305a through the serial interface, mode is set high. the serial interface (sdi/sdo) uses a 16-bit word consisting of an 8-bit command/address byte and an 8-bit data byte. figure 4 shows the serial interface data structure and relative timing. the host mode provides a latched interrupt output (int ) which is triggered by a change in the loss of signal (los) and/or driver performance monitor (dpm) bits. the interrupt is cleared when the interrupt condition no longer exists, and the host processor enables the respective bit in the serial input data byte. host mode also allows control of the serial data and receive data output timing. the clock edge (clke) signal determines when these outputs are valid, relative to the serial clock (sclk) or rclk as listed in table 3 . . table 3. valid clke settings clke output clock valid edge low rpos rneg sdo rclk rclk sclk rising rising falling high rpos rneg sdo rclk rclk sclk falling falling rising
integrated t1/e1 short-haul transceiver with transmit ja ? lxt305a datasheet 13 the lxt305a serial port is addressed by setting bit a4 in the address/command byte, corresponding to address 16. the lxt305a contains only a single output data register so no complex chip addressing scheme is required. the register is accessed by causing the chip select (cs ) pin to transition from high to low. bit 1 of the serial address/command byte provides read/ write control when the chip is accessed. a logic 1 indicates a read operation, and a logic 0 indicates a write operation. table 2 lists serial data output bit combinations for each status. serial data i/o timing characteristics are shown in the test specifications section. figure 4. lxt305a serial interface data structure table 4. equalizer control inputs ec3 ec2 ec1 line length 1 cable loss 2 application bit rate 0 1 1 1 1 1 0 0 1 1 1 0 1 0 1 0 ~ 133 ft abam 133 ~ 266 ft abam 266 ~ 399 ft abam 399 ~ 533 ft abam 533 ~ 655 ft abam 0.6 db 1.2 db 1.8 db 2.4 db 3.0 db dsx-1 1.544 mbps 0 0 0 0 0 1 itu recommendation g.703 e1 - coax (75 ? ) e1 - twisted-pair (120 ? ) 2.048 mbps 0 1 0 fcc part 68, option a csu (ds-1) 1.544 mbps cs sclk sdi/ sdo address / command byte input data byte r/w a0 a1 a2 a3 a4 a5 d0 d1 d2 d3 d4 d5 d6 d7 a6 address / command byte data input / output byte los dfm ec1 ec2 ec3 remote local taos r/w 00 0001 x a0 a6 clear interrupts set loopbacks or reset d0 (lsb) d7(msb) x=don ? t care r/w - = 1: read r/w - = 0: write a4 note: output data byte is the same as the input data byte except for bits d<5:7> shown in table 2 .
lxt305a ? integrated t1/e1 short-haul transceiver with transmit ja 14 datasheet 2.5.2 hardware mode operation in hardware mode the transceiver is accessed and controlled through individual pins. with the exception of the interrupt (int pin) and clock edge select (clke pin) functions, hardware mode provides all the functions provided in the host mode. in the hardware mode rpos and rneg outputs are valid on the rising edge of rclk. to operate in hardware mode, mode must be set low. the equalizer control signals (ec1 through ec3) are input on the int , sdi and sdo pins respectively. diagnostic control for remote loopback (rloop), local loopback (lloop), and transmit all ones (taos) modes is provided by individual pins. 2.5.3 diagnostic mode operation 2.5.3.1 transmit all ones in transmit all ones (taos) mode the tpos and tneg inputs to the transceiver are ignored. the transceiver transmits a continuous stream of ones when the taos mode is activated. taos can be commanded simultaneously with local loopback, but is inhibited during remote loopback. during taos, the transmitter is locked to mclk. if mclk is not supplied, the transmitter powers down. 2.5.3.2 remote loopback in remote loopback (rloop) mode, the transmit data and clock inputs (tpos, tneg and tclk) are ignored. the rpos and rneg outputs are looped back through the transmit circuits and output on ttip and tring at the rclk frequency. receiver circuits are unaffected by the rloop command and continue to output the rpos, rneg and rclk signals received from the twisted-pair or coaxial cable. 2.5.3.3 local loopback in local loopback (lloop) mode, the receiver circuits are inhibited. the transmit data and clock inputs (tpos, tneg and tclk) are looped back onto the receive data and clock outputs (rpos, rneg and rclk). the transmitter circuits are unaffected by the lloop command. the tpos and tneg inputs (or a stream of ones if the taos command is active) will be transmitted normally. during local loopback if tclk is not supplied, the transmitter powers down. if los and lloop are both active, lloop takes precedence, forcing rclk = tclk. table 5. lxt305a crystal specifications (external) parameter t1 e1 frequency 6.176 mhz 8.192 mhz frequency stability 20 ppm @ 25 c 25 ppm from -40 c to 85 c (ref 25 c reading) 20 ppm @ 25 c 25 ppm from -40 c to 85 c (ref 25 c reading) pullability cl = 11 pf to 18.7 pf, + ? f = 175 to 195 ppm cl = 18.7 pf to 34 pf, - ? f = 175 to 195 ppm cl = 11 pf to 18.7 pf, + ? f = 95 to 115 ppm cl = 18.7 pf to 34 pf, - ? f = 95 to 115 ppm effective series resistance 40 ? maximum 30 ? maximum crystal cut at at
integrated t1/e1 short-haul transceiver with transmit ja ? lxt305a datasheet 15 resonance parallel parallel maximum drive level 2.0 mw 2.0 mw mode of operation fundamental fundamental crystal holder hc49 (r3w), c o = 7 pf maximum c m = 17 ff typical hc49 (r3w), c o = 7 pf maximum c m = 17 ff typical table 5. lxt305a crystal specifications (external) parameter t1 e1
lxt305a ? integrated t1/e1 short-haul transceiver with transmit ja 16 datasheet 3.0 application information 3.1 1.544 mbps t1 interface applications figure 5 is a typical 1.544 mbps t1 interface application. use a 1:1.15 transmit transformer without in-line resistors for maximum power savings. the lxt305a is shown in the host mode with a t1/esf framer providing the digital interface with the host controller. an lxp600a clock adapter (clad) provides the 2.048 mhz system backplane clock, locked to the recovered 1.544 mhz clock signal. the power supply inputs are tied to a common bus with appropriate decoupling capacitors installed (68 f on the transmit side, 1.0 f and 0.1 f on the receive side). for dsx-1 applications, series resistors can be used in line with the transmit transformer to provide higher return loss. 3.2 2.048 mbps e1 interface applications figure 6 is a typical 2.048 mbps e1 application. the lxt305a is shown in hardware mode with an e1/crc4 framer. as in the dsx-1 application figure 5 , this configuration is illustrated with a crystal in place to enable the lxt305a jitter attenuation loop, and a single power supply bus. the hard-wired control lines for taos, lloop and rloop are individually controllable, and the lloop and rloop lines are also tied to a single control for the reset function. with the 1:1 transformer ratio and code 000 selected on the ec inputs, the lxt305a outputs the itu specified 2.37 v pulse onto 75 ? coaxial cable. simply changing the ec code to 001 allows the lxt305a to match the 3.0 v pulse specification for 120 ? shielded twisted-pair cable. no transformer change is required. for situations where a 1:1.26 transformer is desired, ec code 000 selects the correct output for 120 ? twisted-pair cable. to achieve higher return loss, increased surge protection and lower output short circuit current, series resistors can be used in line with the transmit transformer.
integrated t1/e1 short-haul transceiver with transmit ja ? lxt305a datasheet 17 3.3 line protection on the receive side, the 1 k ? series resistors protect the receiver against current surges coupled into the device. due to the high receiver impedance (typically 40k ? ) the resistors do not affect the receiver sensitivity. on the transmit side, schottky diodes d1-d4 protect the output driver. while not mandatory for normal operation, these protection elements are strongly recommended to improve the design?s robustness. table 6. t1/e1 input/output configurations bit rate (mbps) crystal xtal cable ( ? ) rr 2 ( ? ) ec3/2/1 transmit transformer 1 (tr) rt 2 ( ? ) typical tx return loss 3 (db) cc ( f) 1.544 (t1) lxc6176 100 200 0/1/1 - 1/1/1 1:1.15 1:2 1:2.3 0 9.1 9.1 0.5 18 18 0.47 0 0 2.048 (e1) lxc8192 120 240 0/0/0 0/0/0 0/0/1 0/0/1 1:1.26 1:2 1:1 1:2 0 9.1 0 15 0.5 12 0.5 18 0.47 0 0.47 0 75 150 0/0/0 0/0/0 0/0/1 0/0/1 1:1 1:2 1:1 1:2 0 9.1 10 14.3 0.5 18 5 10 0.47 0 0 0 1. transformer turns ratio accuracy is 2%. 2. rr and rt values are 1%. 3. typical return loss, 51 khz to 3.072 mhz band.
lxt305a ? integrated t1/e1 short-haul transceiver with transmit ja 18 datasheet figure 5. typical lxt305a 1.544 mbps t1 host mode application mode mclk clke los dpm tpos tneg tclk rpos rneg rclk control and monitor framer lxp600a +5v clki fsi clko 2.048 mhz xtalin xtalout rv+ rgnd tgnd tv+ +5v 68 f 0.1 f 1.0 f sclk cs int sdi sdo tring ttip mring mtip rtip rring p serial port rr receive line rr 2ct:1 lxt305a cc rt rt 470 1 pf transmit line tr d2 d1 d3 d4 1k 1k 1. typical value = 470 pf. adjust for actual board parasitics to obtain optimum return loss. 2. d1 - d4 = international rectifier: 11dq04 or 10bq060; motorola: mbr0540t1 +5v +5v
integrated t1/e1 short-haul transceiver with transmit ja ? lxt305a datasheet 19 figure 6. typical lxt305a 120 ? 2.048 mbps e1 hardware mode application mode mclk taos rloop lloop los dpm tpos tneg tclk rpos rneg rclk control and monitor framer lxp600a clki fsi clko 1.544 mhz xtalin xtalout rv+ rgnd tgnd tv+ +5v 68 f 0.1 f 1.0 f ec1 ec2 ec3 tring ttip mring mtip rtip rring line length setting lxt305a d3 rt 470 1 pf transmit line 1k receive line rr tr 2ct:1 rt 1k rr d2 d1 d4 cc 1. typical value = 470 pf. adjust for actual board parasitics to obtain optimum return loss. 2. d1 - d4 = international rectifier: 11dq04 or 10bq060; motorola: mbr0540t1 +5v +5v
lxt305a ? integrated t1/e1 short-haul transceiver with transmit ja 20 datasheet 4.0 test specifications note: the minimum and maximum values in table 7 through table 13 and figure 7 through figure 12 represent the performance specifications of the lxt305a and are guaranteed by test, except where noted by design. table 7. absolute maximum ratings parameter sym min max unit dc supply (referenced to gnd) rv+, tv+ -0.3 6.0 v input voltage, any pin 1 v in rgnd - 0.3 rv+ + 0.3 v input current, any pin 2 iin -10 10 ma storage temperature t stg -65 150 c caution: operations at or beyond these limits may result in permanent damage to the device. normal operation is not guaranteed at these extremes. 1. excluding rtip and rring which must stay between -6v and (rv+ + 0.3) v. 2. transient currents of up to 100 ma will not cause scr latch up. ttip, tring, tv+ and tgnd can withstand a continuous current of 100 ma. table 8. recommended operating conditions and characteristics parameter sym min typ max unit dc supply 1 rv+, tv+ 4.75 5.0 5.25 v ambient operating temperature t a -40 25 85 c 1. tv+ must not exceed rv+ by more than 0.3 v. table 9. electrical characteristics (under recommended operating conditions) parameter sym min max unit test conditions total power dissipation 1 p d ? 400 mw 100% ones density & maximum line length @ 5.25 v high level input voltage 2,3 (pins 1-5, 10, 23-28) v ih 2.0 ? v low level input voltage 2,3 (pins 1-5, 10, 23-28) vil ? 0.8 v high level output voltage 2,3 (pins 6-8, 11, 12, 23, 25) v oh 2.4 ? vi out = -400 a low level output voltage 2,3 (pins 6-8, 11, 12, 23, 25) v ol ? 0.4 v i out = 1.6 ma input leakage current 4 i ll 010 a three-state leakage current 2 (pin 25) i3 l 010 a 1. power dissipation while driving line load over operating temperature range. includes device and load. digital input levels ar e within 10% of the supply rails and digital outputs are driving a 50 pf capacitive load. 2. functionality of pins 23 and 25 depends on mode. see host/hardware mode descriptions. 3. output drivers will output cmos logic levels into cmos loads. 4. except mtip and mring ill = 50 a.
integrated t1/e1 short-haul transceiver with transmit ja ? lxt305a datasheet 21 table 10. analog characteristics (under recommended operating conditions) parameter min typ 1 max unit test conditions ami output pulse amplitudes dsx-1 2.4 3.0 3.6 v measured at the dsx e1 2.7 3.0 3.3 v measured at line side recommended output load at ttip and tring ? 75 ? ? jitter added by the transmitter 2 10 hz - 8 khz ?? 0.02 ui 8 khz - 40 khz ?? 0.025 ui 10 hz - 40 khz ?? 0.025 ui broad band ?? 0.05 ui sensitivity below dsx (0 db = 2.4 v) 13.6 ?? db 500 ?? mv loss of signal threshold ? 0.3 ? v data decision threshold dsx-1 63 70 77 % peak e1 43 50 57 % peak allowable consecutive zeros before los 160 175 190 ? input jitter tolerance 10 khz - 100 khz 0.4 ?? ui jitter attenuation curve corner frequency 3 ? 3 ? hz minimum return loss 4,5 transmit min typ receive min typ db 51 khz - 102 khz 18 ? 20 ? db 102 khz - 2.048 khz 18 ? 20 ? db 2.048 khz - 3.072 khz 18 ? 20 ? db 1. typical values are measured at 25 c and are for design aid only; not guaranteed and not subject to production testing. 2. input signal to tclk is jitter-free. 3. circuit attenuates jitter at 20 db/decade above the corner frequency. 4. in accordance with itu g.703/ets 300166 return loss specifications when wired per figure 6 (e1). 5. guaranteed by design.
lxt305a ? integrated t1/e1 short-haul transceiver with transmit ja 22 datasheet figure 7. typical receive jitter tolerance 300 jitter 400 1.2 ui pub 62411 dec 1990 lxt305a performance 10000 ui 1200 ui 1000 ui 138 ui 100 ui 28 ui 10 ui 1 ui 0.4 ui 0.1 ui 1 hz 10 hz 100 hz 1 khz 10 khz 100 khz 30 khz frequency
integrated t1/e1 short-haul transceiver with transmit ja ? lxt305a datasheet 23 figure 8. lxt305a transmit jitter transfer performance (typical) table 11. lxt305a receive timing characteristics (see figure 9 ) parameter sym min typ 1 max unit test conditions receive clock duty cycle 2 t1 rclkd 40 50 60 % e1 rclkd 40 50 60 % receive clock period 2 t1 t pw 594 648 702 ns e1 t pw 447 488 529 ns receive clock pulse width high t1 t pwh ? 324 ? ns e1 t pwh ? 244 ? ns receive clock pulse width low t1 t pwl 270 324 378 ns e1 t pwl 203 244 285 ns rpos/rneg to rclk rising setup time t1 t sur 50 270 ? ns e1 t sur 50 203 ? ns rclk rising to rpos/rneg hold time t1 t hr 50 270 ? ns e1 t hr 50 203 ? ns 1. typical values are at 25 c and are for design aid only; they are not guaranteed and not subject to production testing. 2. rclk duty cycle widths will vary depending on extent of received pulse jitter displacement. max and min rclk duty cycles are for worst case jitter conditions (0.4 ui clock displacement for 1.544 mhz, 0.2 ui clock displacement for 2.048 mhz). 20 db 1 hz typical lxt305a performance 0 db -10 db -20 db -30 db -40 db -60 db 10 hz 100 hz 1 khz 10 khz 100 khz 1450 hz 20 hz 0.5 db / 3 hz 0.5 db / 40 hz at&t 62411 template slope equivalent to 20 db per decade ccitt g.735 template slope equivalent to 20 db per decade at&t 62411 template slope equivalent to 40 db per decade frequency gain 19.5 db / 100 hz 19.5 db / 400 hz
lxt305a ? integrated t1/e1 short-haul transceiver with transmit ja 24 datasheet figure 9. lxt305a receive clock timing diagram table 12. lxt305a master clock and transmit timing characteristics (see figure 10 ) parameter sym min typ 1 max unit master clock frequency dsx-1 mclk ? 1.544 ? mhz e1 mclk ? 2.048 ? mhz master clock tolerance mclkt ? 100 ? ppm master clock duty cycle mclkd 40 ? 60 % crystal frequency dsx-1 fc ? 6.176 ? mhz e1 fc ? 8.192 ? mhz transmit clock frequency dsx-1 tclk ? 1.544 ? mhz e1 tclk ? 2.048 ? mhz transmit clock tolerance tclkt ? 50 ? ppm transmit clock duty cycle tclkd 10 ? 90 % tpos/tneg to tclk setup time t sut 25 ?? ns tclk to tpos/tneg hold time t ht 25 ?? ns 1. typical values are at 25 c and are for design aid only; they are not guaranteed and not subject to production testing. figure 10. lxt305a transmit clock timing diagram t pwh t pwl t pw t hr t sur rclk rpos rneg rpos rneg t sur t hr host mode clke = 1 host mode clke = 0, & h/w mode t ht t sut tclk tpos tneg
integrated t1/e1 short-haul transceiver with transmit ja ? lxt305a datasheet 25 table 13. lxt305a serial i/o timing characteristics (see figure 11 and figure 12 ) parameter sym min typ 1 max unit test conditions rise/fall time - any digital output t rf ?? 100 ns load 1.6 ma, 50 pf sdi to sclk setup time t dc 50 ?? ns sclk to sdi hold time t cdh 50 ?? ns sclk low time t cl 240 ?? ns sclk high time t ch 240 ?? ns sclk rise and fall time t r , t f ?? 50 ns cs to sclk setup time t cc 50 ?? ns sclk to cs hold time t cch 50 ?? ns cs inactive time t cwh 250 ?? ns sclk to sdo valid t cdv ?? 200 ns sclk falling edge or cs rising edge to sdo high z t cdz ? 100 ? ns 1. typical values are at 25 c and are for design aid only; they are not guaranteed and not subject to production testing. figure 11. lxt305a serial data input timing diagram t cwh t cch t cl t ch t cc sclk sdi t dc lsb t cdh lsb t cdh msb control byte data byte cs
lxt305a ? integrated t1/e1 short-haul transceiver with transmit ja 26 datasheet figure 12. lxt305a serial data output timing diagram sclk t cdz cs high-z high-z t cdv t cdv sdo sdo clke=1 clke=0 t cdz
integrated t1/e1 short-haul transceiver with transmit ja ? lxt305a datasheet 27 5.0 mechanical specifications figure 13. package specifications 1 b 2 e 1 a a 2 b l e d ea eb e d 1 d c b c l d f a 2 a 1 a 28-pin plastic dual in-line package p/n LXT305ANE temperature range -45 c to +85 c 28-pin plastic leaded chip carrier p/n lxt305ape temperature range -45 c to +85 c dim inches millimeters min max min max a ? 0.250 ? 6.350 a 2 0.125 0.195 3.175 4.953 b 0.014 0.022 0.356 0.559 b 2 0.030 0.070 0.762 1.778 d 1.380 1.565 35.052 39.751 e 0.600 0.625 15.240 15.875 e 1 0.485 0.580 12.319 14.732 e 0.100 bsc 1 (nominal) 2.540 bsc 1 (nominal) ea 0.600 bsc 1 (nominal) 15.240 bsc 1 (nominal) eb ? 0.700 ? 17.780 l 0.115 0.200 2.921 5.080 1. bsc ? basic spacing between centers. dim inches millimeters minmaxminmax a 0.165 0.180 4.191 4.572 a 1 0.090 0.120 2.286 3.048 a 2 0.062 0.083 1.575 2.108 b .050 bsc 1 (nominal) 1.27 bsc 1 (nominal) c 0.026 0.032 0.660 0.813 d 0.485 0.495 12.319 12.573 d 1 0.450 0.456 11.430 11.582 f 0.013 0.021 0.330 0.533 1. bsc ? basic spacing between centers.

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