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| idsh1g?02a1f1c idsh1g?03a1f1c idsh1g?04a1f1c 1-gbit double-data-rate-three sdram ddr3 sdram eu rohs compliant products advance internet data sheet rev. 0.63 june 2008
advance internet data sheet idsh1g?0[2/3/4]a1f1c 1-gbit double-data-rate-three sdram qag_techdoc_a4, 4.20, 2008-01-25 2 12192007-s9ar-zt6n we listen to your comments any information within this document that yo u feel is wrong, unclear or missing at all? your feedback will help us to continuous ly improve the quality of this document. please send your proposal (including a reference to this document) to: techdoc@qimonda.com revision history: rev. 0.63, 2008-06 added more products page 42 added new table table 35 ?ddr3-dll_off speed bins and operating conditions? on page 42 page 27 added values in table 16 ?dc and ac input levels for single-ended command, address and control signals? on page 27 page 33 changed cio for ddr3-1066 to 2.7 pf in chapter 3.13 previous revision: rev. 0.62, 2008-03 added errata data sheet added output drive impedance of 40 ohm updated output slew rates updated idd tables previous revision: rev. 0.61, 2008-02 editorial changes previous revision: rev. 0.60, 2007-12 added new product idsh1g-03a1f1c-16h, idsh1g-03a1f1c-16j, idsh1g-03a1f1c-16k, idsh1g- 03a1f1c-16g previous revision: rev. 0.51, 2007-12 page 9 added ?termination data strobe ? in table 3 page 7 corrected figure, ballout for 1gb 8 components editorial changes previous revision: rev. 0.50, 2007-11 inital document idsh1g?0[2/3/4]a1f1c 1-gbit double-data-rate-three sdram advance internet data sheet rev. 0.63, 2008-06 3 12192007-s9ar-zt6n 1overview this chapter gives an overview of the double-data-rate-thr ee (ddr3) sdram component product family and describes its main characteristics. 1.1 features the ddr3 sdram offers t he following key features: ? 1.5 v 0.075 v supply voltage for v dd and v ddq ? sdram configurations with 4, 8 and 16 data in/outputs ? eight internal banks for concurrent operation ? 8-bit prefetch architecture ? page size:1 kbyte page size for 4 and 8; 2 kbyte page size for 16 components ? asynchronous reset ? auto-precharge operation fo r read and write commands ? refresh, self-refresh and power saving power-down modes; auto self-refresh (asr) and partial array self refresh (pasr) ? average refresh period 7.8 s at a t oper up to 85 c, 3.9 s up to 95 c ? operating temperature range 0 - 85 c and 85 - 95 c ? data mask function for write operation ? commands can be entered on each positive clock edge ? data and data mask are referenced to both edges of a differential data strobe pair (double data rate) ? cas latency (cl): 5, 6, 7, 8, 9, 10 and 11 ? posted cas with programmable additive latency (al = 0, cl?1 and cl?2) for improved command, address and data bus efficiency ? read latency rl = al + cl ? programmable cas write latency (cwl) per operating frequency ? write latency wl = al + cwl ? burst length 8 (bl8) and burst chop 4(bc4) modes: fixed via mode register (mrs) or selectable on-the-fly (otf) ? programmable read burst orderin g: interleaved or nibble sequential ? multi-purpose register (mpr) for readout of non-memory related information ? system level timing calibration support via write leveling and mpr read pattern ? differential clock inputs (ck/ck ) ? bi-directional, differential data strobe pair (dqs/dqs ) is transmitted / received with data. edge aligned with read data and center-aligned with write data ? dll aligns transmitted read data and strobe pair transition with clock ? push-pull output driver with nominal r on of 34 and 40 at v out = v ddq /2 ? programmable on-die termination (odt) for data, data mask and differential strobe pairs ? dynamic odt mode for improved signal integrity and pre- selectable termination impedances during writes ? terminate dqs (tdqs) feature for mix of 4 and 8 based memory modules within a memory channel ? zq calibration for output driver and on-die termination using external reference resistor to ground ? two reference voltage inputs v refdq , v refca ? lead and halogen free packages: 78 ball (pg-tfbga-60) for 4 and 8 components ? lead and halogen free packages: 96 ball (pg-tfbga-84) for 16 components, 0.8 0.8 mm ball pitch idsh1g?0[2/3/4]a1f1c 1-gbit double-data-rate-three sdram advance internet data sheet rev. 0.63, 2008-06 4 12192007-s9ar-zt6n 1.2 product list the product list shows all possible products within the 1-gbit ddr3 sdram first component generation. availability depends on application needs. for qimonda part number nomenclature see chapter 6 . table 1 ordering information qag part number max. clock frequency cas-rcd-rp latencies speed sort name package ddr3 sdram components in 4 organization (256m 4) idsh1g-02a1f1c-10f 533 7-7-7 ddr3-1066f pg-tfbga-78 idsh1g-02a1f1c-13g 667 8-8-8 ddr3-1333g pg-tfbga-78 idsh1g-02a1f1c-13h 667 9-9-9 ddr3-1333h pg-tfbga-78 idsh1g-02a1f1cl10f 533 7-7-7 ddr3-1066f pg-tfbga-78 ddr3 sdram components in 8 organization (128m 8) idsh1g-03a1f1c-08d 400 5-5-5 ddr3-800d pg-tfbga-78 idsh1g-03a1f1c-08e 400 6-6-6 ddr3-800e pg-tfbga-78 idsh1g-03a1f1c-10f 533 7-7-7 ddr3-1066f pg-tfbga-78 idsh1g-03a1f1c-10g 533 8-8-8 ddr3-1066g pg-tfbga-78 idsh1g-03a1f1c-13g 667 8-8-8 ddr3-1333g pg-tfbga-78 idsh1g-03a1f1c-13h 667 9-9-9 ddr3-1333h pg-tfbga-78 idsh1g-03a1f1c-16g 800 8-8-8 ddr3-1600g pg-tfbga-78 idsh1g-03a1f1c-16h 800 9-9-9 ddr3-1600h pg-tfbga-78 idsh1g-03a1f1c-16j 800 10-10-10 ddr3-1600j pg-tfbga-78 idsh1g-03a1f1c-16k 800 11-11-11 ddr3-1600k pg-tfbga-78 idsh1g-03a1f1cl10f 533 7-7-7 ddr3-1066f pg-tfbga-78 ddr3 sdram components in 16 organization (64m 16) IDSH1G-04A1F1C-10E 533 6-6-6 ddr3-1066e pg-tfbga-96 idsh1g-04a1f1c-10f 533 7-7-7 ddr3-1066f pg-tfbga-96 idsh1g-04a1f1c-10g 533 8-8-8 ddr3-1066g pg-tfbga-96 idsh1g-04a1f1c-13g 667 8-8-8 ddr3-1333g pg-tfbga-96 idsh1g-04a1f1c-13h 667 9-9-9 ddr3-1333h pg-tfbga-96 idsh1g-04a1f1c-16g 800 8-8-8 ddr3-1600g pg-tfbga-96 idsh1g-04a1f1c-16h 800 9-9-9 ddr3-1600h pg-tfbga-96 idsh1g-04a1f1c-16j 800 10-10-10 ddr3-1600j pg-tfbga-96 idsh1g-04a1f1c-16k 800 11-11-11 ddr3-1600k pg-tfbga-96 idsh1g?0[2/3/4]a1f1c 1-gbit double-data-rate-three sdram advance internet data sheet rev. 0.63, 2008-06 5 12192007-s9ar-zt6n 1.3 ddr3 sdram addressing table 2 1-gbit ddr3 sdram addressing configuration 256mbit 4 128mbit 8 64mbit 16 note internal organization 8 banks 32 mbits 4 8 banks 16 mbits 8 8 banks 8 mbits 16 number of banks 8 8 8 bank address ba[2:0] ba[2:0] ba[2:0] row address a[13: 0] a[13:0] a[12:0] number of addressable rows 8k 8k 4k column address a[9: 0], a11 a[9:0] a[9:0] number of addressable columns (page length) 2048 1024 1024 1) 1) page length is the number of addre ssable columns and is defined as 2 colbits , where colbits is the number of column address bits, excluding a10/ap and a12/bc page size 1 kb 1 kb 2 kb 2) 2) page size is the number of bytes of data delivered from the a rray to the internal sense amplifiers when an active command is registered. page size is per memory bank and ca lculated as follows: page size = 2 colbits org/8, where colbits is the number of column address bits and org is the number of dq bits for a given sdram configuration ( 4, 8 or 16). auto-precharge a10 / ap a10 / ap a10 / ap burst length on-the-fly bit a12/bc a12/bc a12/bc idsh1g?0[2/3/4]a1f1c 1-gbit double-data-rate-three sdram advance internet data sheet rev. 0.63, 2008-06 6 12192007-s9ar-zt6n 1.4 package ballout figure 1 , figure 2 and figure 3 show the ballouts for ddr3 sdram components. see chapter 5 for package outlines. figure 1 ballout for 1gb 4 components (pg-tfbga-78) 0 3 3 + ' 5 $ 0 7 r s 9 l h z $ 9 6 6 9 ' ' 1 & 1 & 9 6 6 9 ' ' $ % 9 6 6 9 6 6 4 ' 4 ' 0 9 6 6 4 9 ' ' 4 % & 9 ' ' 4 ' 4 ' 4 6 ' 4 ' 4 9 6 6 4 & ' 9 6 6 4 1 & ' 4 6 9 ' ' 9 6 6 9 6 6 4 ' ( 9 5 ( ) ' 4 9 ' ' 4 1 & 1 & 1 & 9 ' ' 4 ( ) 1 & 9 6 6 5 $ 6 & . 9 6 6 1 & ) * 2 ' 7 9 ' ' & $ 6 & . 9 ' ' & . ( * + 1 & & 6 : ( $ $ 3 = 4 1 & + - 9 6 6 % $ % $ 1 & 9 5 ( ) & $ 9 6 6 - . 9 ' ' $ $ $ % & % $ 9 ' ' . / 9 6 6 $ $ $ $ 9 6 6 / 0 9 ' ' $ $ $ $ 9 ' ' 0 1 9 6 6 5 ( 6 ( 7 $ 1 & $ 9 6 6 1 idsh1g?0[2/3/4]a1f1c 1-gbit double-data-rate-three sdram advance internet data sheet rev. 0.63, 2008-06 7 12192007-s9ar-zt6n figure 2 ballout for 1gb 8 components (pg-tfbga-78) 0 3 3 + $ 9 6 6 9 ' ' 1 & 1 8 7 ' 4 6 9 6 6 9 ' ' $ % 9 6 6 9 6 6 4 ' 4 ' 0 7 ' 4 6 9 6 6 4 9 ' ' 4 % & 9 ' ' 4 ' 4 ' 4 6 ' 4 ' 4 9 6 6 4 & ' 9 6 6 4 ' 4 ' 4 6 9 ' ' 9 6 6 9 6 6 4 ' ( 9 5 ( ) ' 4 9 ' ' 4 ' 4 ' 4 ' 4 9 ' ' 4 ( ) 1 & 9 6 6 5 $ 6 & . 9 6 6 1 & ) * 2 ' 7 9 ' ' & $ 6 & . 9 ' ' & . ( * + 1 & & 6 : ( $ $ 3 = 4 1 & + - 9 6 6 % $ % $ 1 & 9 5 ( ) & $ 9 6 6 - . 9 ' ' $ $ $ % & % $ 9 ' ' . / 9 6 6 $ $ $ $ 9 6 6 / 0 9 ' ' $ $ $ $ 9 ' ' 0 1 9 6 6 5 ( 6 ( 7 $ 1 & $ 9 6 6 1 ' 5 $ 0 7 r s 9 l h z idsh1g?0[2/3/4]a1f1c 1-gbit double-data-rate-three sdram advance internet data sheet rev. 0.63, 2008-06 8 12192007-s9ar-zt6n figure 3 ballout for 1gb 16 components (pg-tfbga-96) 0 3 3 + ' 5 $ 0 7 r s 9 l h z $ 9 ' ' 4 ' 4 8 ' 4 8 ' 4 8 9 ' ' 4 9 6 6 $ % 9 6 6 4 9 ' ' 9 6 6 ' 4 6 8 ' 4 8 9 6 6 4 % & 9 ' ' 4 ' 4 8 ' 4 8 ' 4 6 8 ' 4 8 9 ' ' 4 & ' 9 6 6 4 9 ' ' 4 ' 0 8 ' 4 8 9 6 6 4 9 ' ' ' ( 9 6 6 9 6 6 4 ' 4 / ' 0 / 9 6 6 4 9 ' ' 4 ( ) 9 ' ' 4 ' 4 / ' 4 6 / ' 4 / ' 4 / 9 6 6 4 ) * 9 6 6 4 ' 4 / ' 4 6 / 9 ' ' 9 6 6 9 6 6 4 * + 9 5 ( ) ' 4 9 ' ' 4 ' 4 / ' 4 / ' 4 / 9 ' ' 4 + - 1 & 9 6 6 5 $ 6 & . 9 6 6 1 & - . 2 ' 7 9 ' ' & $ 6 & . 9 ' ' & . ( . / 1 & & 6 : ( $ $ 3 = 4 1 & / 0 9 6 6 % $ % $ 1 & 9 5 ( ) & $ 9 6 6 0 1 9 ' ' $ $ $ % & % $ 9 ' ' 1 3 9 6 6 $ $ $ $ 9 6 6 3 5 9 ' ' $ $ $ $ 9 ' ' 5 7 9 6 6 5 ( 6 ( 7 1 & 1 & $ 9 6 6 7 idsh1g?0[2/3/4]a1f1c 1-gbit double-data-rate-three sdram advance internet data sheet rev. 0.63, 2008-06 9 12192007-s9ar-zt6n 1.5 input / output signal functional description table 3 input / output signal functional description symbol eda signal name 1) type function ck, ck ck_t, ck_c input clock: ck and ck are differential clock inputs. all address and control input signals are sampled on the cro ssing of the positive edge of ck and negative edge of ck . cke cke input clock enable: cke high activates, and cke low deactivates internal clock signals and device input buffer s and output driver s. taking cke low provides precharge power-down and self-refresh operation (all banks idle), or active power-down ( active row in any bank). cke is asynchronous for self-refresh exit. after v refca and v refdq have become stable during the power on and initialization sequence, they must be maintained during all operati ons (including self-refresh). cke must be maintained high throughout read and write accesses. input buffers, excluding ck, ck , odt, cke and reset are disabled during power-down. input buffers, excluding cke and reset are disabled during self refresh. cs cs_n input chip select: all command are masked when cs is registered high. cs provides for external rank selectio n on systems with mu ltiple ranks. cs is considered part of the command code. ras , cas , we ras_n, cas_n, we_n input command inputs: ras , cas and we (along with cs ) define the command being entered. odt odt input on-die termination: odt (registered high) enables termination resistance internal to the ddr3 sdram. when enabled, odt is only applied to each dq, dqs, dqs and dm signal for 4/ 8 configurations. for 16 configuration odt is applied to each dq, dqsu, dqsu , dqsl, dqsl , dmu and dml signal. the odt signal will be ignored if the mode register mr1 is programmed to disable odt and during self refresh. dm ( 4, 8); dmu, dml ( 16) dm (4); dm_tdqs_t (8); dmu, dml (16) input input data mask: dm is an input mask signal for write data. input data is masked when dm is sampled high coincident with that input data during a write access. dm is sampled on both edges of dqs. dmu and dml are the input mask signals for 16 components and control the lower or upper bytes. tdqs/tdqs dm_tdqs_t, nu_tdqs_c termin ation termination data strobe: tdqs/tdqs is applicable for 8 drams only. when enabled via mode register a11 = 1 in mr1, the dram will enable the same termination resistance function on tdqs/tdqs that is applied to dqs/dqs . when disabled via mode register a11 = 0 in mr1, dm/tdqs will provide the data mask function and tdqs is not used. 4/16 drams must disable the tdqs function via mode register a11 = 0 in mr1. ba0 - ba2 ba0 - ba2 input bank address inputs: define to which bank an active, read, write or precharge command is being applied. bank address also determines which mode register is to be accessed during a mode register set cycle. idsh1g?0[2/3/4]a1f1c 1-gbit double-data-rate-three sdram advance internet data sheet rev. 0.63, 2008-06 10 12192007-s9ar-zt6n note: input only pins (ba0-ba2, a0-a15, ras , cas , we , cs , cke, odt, and reset ) do not supply termination. a0 - a13( 4, 8); a0-a12( 16) a0 - a13( 4, 8); a0- a12( 16) input address inputs: provides the row address for active commands and the column address for read/write commands to select one location out of the memory array in the respective bank. (a10/ap and a12/bc have additional functions, see below). the address inputs also provide the op-code during mode register set commands. for numbers of addresses used on this assembly see table 2 . a10 / ap a10 input auto-precharge: a10/ap is sampled during read/write commands to determine whether auto-precharge should be performed to the accessed bank after the read/write operation. (high: auto-precharge, low: no auto-precharge). a10/ ap is sampled during precharge command to determine whether the precharge applies to one bank (a10 low) or all banks (a10 high). if onl y one bank is to be precharged, the bank is selected by bank addresses. a12 / bc a12 input burst chop: a12/bc is sampled during read and write commands to determine if burst chop (on-the-fly) will be performed. (high: no burst chop, low: burst chopped). see ?command truth table? on page 11 for details. dq (4, 8); dql/dqu (16) dq (4, 8) dql/dqu (16) input/ output data input/output: bi-directional data bus. dqs / dqs ( 4, 8); dqsl, dqsl , dqsu, dqsu ( 16) dqs_t / dqs_c ( 4, 8); dqsl_t, dqsl_c, dqsu_t, dqsu_c ( 16) input/ output data strobe: output with read data, input with write data. edge-aligned with read data, centered in write data. for the 16, dqsl corresponds to the data on dql0 - dql7; dqsu corresponds to the data on dqu0- dqu7.the data strobes dqs, dqsl and dqsu are paired with differential signals dqs , dqsl and dqsu , respectively, to provide differential pair signaling to the system during both reads and writes. ddr3 sdram supports differential data strobe only and does not support single-ended. reset reset_n cmos input active low asynchronous reset: reset is active when reset is low, and inactive when reset is high. reset must be high during normal operation. reset is a cmos rail to rail signal with dc high and low are 80% and 20% of v dd , reset active is destructive to data contents. nc ? ? no connect: no internal electrical connection is present v ddq vddq supply dq power supply: 1.5 v 0.075 v v ssq vssq supply dq ground v dd vdd supply power supply: 1.5 v 0.075 v v ss vss supply ground v refdq vrefdq supply reference voltage for dq v refca vrefca supply reference voltage for command and address inputs zq zq supply reference ball for zq calibration 1) the eda signal name is used in qimonda's si mulation models such as ibis, verilog, etc. symbol eda signal name 1) type function idsh1g?0[2/3/4]a1f1c 1-gbit double-data-rate-three sdram advance internet data sheet rev. 0.63, 2008-06 11 12192007-s9ar-zt6n 2 functional description the ddr3 sdram is a high-speed dynamic random-access memory internally configured as an eight-bank sdram. 2.1 truth tables the truth tables list the input signal values at a given clock edge which represent a command or state transition expected to be executed by the ddr3 sdram . table 4 lists all valid commands to the ddr3 sdram. for a detailed description of the various power mode entries and exits please refer to table 5 . in addition, the dm functionality is described in table 6 . table 4 command truth table function abbr. cke cs ras cas we ba2 - ba0 a15 - a13 a12/ bc a10/ ap a11, a9-a0 note prev. cycle curr. cycle mode register set mrs h h l l l l ba op code 1)2)3)4)5) refresh ref h h l l l h v v v v v 1)2)3)4)5) self-refresh entry sre h l l l l h v v v v v 1)2)3)4)5)6)7)8) self-refresh exit srx l h h v v v v v v v v 1)2)3)4)5)6)7)8)9) lhhh single bank precharge pre h h l l h l ba v v l v 1)2)3)4)5) precharge all banks prea h h l l h l v v v h v 1)2)3)4)5) active act h h l l h h ba ra (row address) 1)2)3)4)5) write (bl8mrs or bc4mrs) wr h h l h l l ba rfu v l ca 1)2)3)4)5)10) write (bc4otf) wrs4 h h l h l l ba rfu l l ca 1)2)3)4)5)10) write (bl8otf) wrs8 h h l h l l ba rfu h l ca 1)2)3)4)5)10) write w/ap (bl8mrs or bc4mrs) wra h h l h l l ba rfu v h ca 1)2)3)4)5)10) write w/ap (bc4otf) wras4 h h l h l l ba rfu l h ca 1)2)3)4)5)10) write w/ap (bl8otf) wras8 h h l h l l ba rfu h h ca 1)2)3)4)5)10) read (bl8mrs or bc4mrs) rd h h l h l h ba rfu v l ca 1)2)3)4)5)10) read (bc4otf) rds4 h h l h l h ba rfu l l ca 1)2)3)4)5)10) read (bl8otf) rds8 h h l h l h ba rfu h l ca 1)2)3)4)5)10) read w/ap (bl8mrs or bc4mrs) rda h h l h l h ba rfu v h ca 1)2)3)4)5)10) read w/ap (bc4otf) rdas4 h h l h l h ba rfu l h ca 1)2)3)4)5)10) read w/ap (bl8otf) rdas8 h h l h l h ba rfu h h ca 1)2)3)4)5)10) no operation nop h h l h h h v v v v v 1)2)3)4)5)11) idsh1g?0[2/3/4]a1f1c 1-gbit double-data-rate-three sdram advance internet data sheet rev. 0.63, 2008-06 12 12192007-s9ar-zt6n device deselect des h h h x x x x x x x x 1)2)3)4)5)12) power down entry pde h l l h h h v v v v v 1)2)3)4)5)8)13) hvvv power down exit pdx l h l h h h v v v v v 1)2)3)4)5)8)13) hvvv zq calibration short zqcs h h l h h l x x x l x 1)2)3)4)5) zq calibration long zqcl h h l h h l x x x h x 1)2)3)4)5) 1) ba = bank address, ra = row address, ca = column address, bc = burst chop, ap = auto precha rge, x = don?t care, v = valid 2) all ddr3 sdram commands are defined by states of cs , ras , cas , we and cke at the rising edge of the clock. the higher order address bits of ba, ra and ca are device densit y and io configuration (4, 8, 16) dependent. 3) reset is a low active signal which will be used only for asynchronous reset. it mu st be maintained high during any function. 4) bank addresses (ba) determine which bank is to be operated upon. for mrs, ba selects a mode register. 5) v means h or l (but a defined logic level) and x means either ?defined or undefined ( like floating) logic level?. 6) the state of odt does not affect the states described in this table. the odt function is not available during self refresh 7) v ref (both v refca and v refdq ) must be maintained during self refresh operation. 8) refer to ?clock enable (cke) truth table for synchronous transitions? on page 13 for more detail with cke transition. 9) self refresh exit is asynchronous. 10) burst reads or writes cannot be terminated or inte rrupted and fixed/on-the-fly bl will be defined by mrs. 11) the no operation (nop) command should be used in cases when the ddr3 sdram is in an idle or a wait state. the purpose of the nop command is to prevent the ddr3 sdram from registering any unwanted commands between operations. a nop command will not terminate a previous operation that is still executing, such as a read or write burst. 12) the deselect command (des) performs the same function as a no operation command. 13) the power down mode does not perform any refresh operation. function abbr. cke cs ras cas we ba2 - ba0 a15 - a13 a12/ bc a10/ ap a11, a9-a0 note prev. cycle curr. cycle idsh1g?0[2/3/4]a1f1c 1-gbit double-data-rate-three sdram advance internet data sheet rev. 0.63, 2008-06 13 12192007-s9ar-zt6n table 5 clock enable (cke) truth table for synchronous transitions current state 1) 1) current state is defined as the state of t he ddr3 sdram immediately prior to clock edge n. cke(n-1) 2) 2) cke(n) is the logic state of cke at clock edge n; c ke (n-1) was the state of cke at the previous clock edge. cke(n) 2) command (n) 3) ras , cas , we , cs 3) command (n) is the command registered at clock edge n, and acti on (n) is a result of command (n),odt is not included here. action (n) 3) note previous cycle current cycle power down l l x maintain power down 4)5)6)7)8)9) 4) all states and sequences not shown ar e illegal or reserved unless explicitly described else where in this document. 5) the state of odt does not affect the states described in this table. the odt function is not available during self refresh. 6) cke must be registered with the same value on t cke.min consecutive positive clock edges. cke must remain at the valid input level the entire time it takes to achieve the t cke.min clocks of registeration. thus, after any cke trans ition, cke may not transition from its valid level during the time period of t is + t cke.min + t ih . 7) des and nop are defined in ?command truth table? on page 11 . 8) the power down does not perform any refresh operations 9) x means don?t care (i ncluding floating around v refca ) in self refresh and power down. it also applies to address pins. l h des or nop power down exit 4)5)6)7)8)10) 10) valid commands for power down entry and exit are nop and des only self refresh l l x maintain self refresh 4)5)6)7)9)11) 11) v ref (both v refca and v refdq ) must be maintained during self refresh operation. l h des or nop self refresh exit 4)5)6)7)11)12)13) 12) on self refresh exit des or nop commands must be issued on every clock edge occurring during the t xs period. read, or odt commands may be issued only after t xsdll is satisfied. 13) valid commands for self refresh exit are nop and des only. bank(s) active h l des or nop active power down entry 4)5)6)7)8)10)14) 14) self refresh can not be entered while read or write operations are in progress. reading h l des or nop power down entry 4)5)6)7)8)10)14)15) 15) if all banks are closed at the conclusion of a read, write or precharge command then precharge power-down is entered, otherw ise active power-down is entered. writing h l des or nop power down entry 4)5)6)7)8)10)14)15) precharging h l des or nop power down entry 4)5)6)7)8)10)14)15) refreshing h l des or nop precharge power down entry 4)5)6)7)10) all banks idle h l des or nop precharge power down entry 4)5)6)7)10)8)14)16) 16) ?idle state? is defined as all banks are closed ( t rp , t dal , etc. satisfied), no data bursts are in pr ogress, cke is high, and all timings from previous operations are satisfied ( t mrd , t mod , t rfc , t zq.init , t zq.oper , t zqcs , etc.) as well as all self-refresh exit and power-down exit parameters are satisfied ( t xs , t xp , t xpdll , etc.). h l ref self refresh entry 4)5)6)7)14)16)17) 17) self refresh mode can only be entered from the all banks idle state. any other state refer to ?command truth table? on page 11 for more detail with all command signals 4)5)6)7)18) 18) must be a legal command as defined in ?command truth table? on page 11 . idsh1g?0[2/3/4]a1f1c 1-gbit double-data-rate-three sdram advance internet data sheet rev. 0.63, 2008-06 14 12192007-s9ar-zt6n table 6 data mask (dm) truth table name (function) dm dqs write enable l valid write inhibit h x idsh1g?0[2/3/4]a1f1c 1-gbit double-data-rate-three sdram advance internet data sheet rev. 0.63, 2008-06 15 12192007-s9ar-zt6n 2.2 mode register 0 (mr0) the mode register mr0 stores the data for controlling various operating modes of ddr3 sdram. it controls burst length, read burst type, cas latency, test mode, dll reset, wr (write recovery time for auto-precharge) and dll control for precharge power-down, which includes various vendor specific options to make ddr3 sdram useful for various applications. the mode register is written by asserting low on cs , ras , cas , we , ba0, ba1, and ba2, while controlling the states of address pins according to table 7 . table 7 mr0 mode register definition (ba[2:0]=000 b ) field bits 1) description bl a[1:0] burst length (bl) and control method number of sequential bits per dq re lated to one read/write command. 00 b bl8mrs mode with fixed burst length of 8. a12/bc at read or write comma nd time is don?t care at read or write command time. 01 b blotf on-the-fly (otf) enabled using a12/bc at read or write comm and time. when a12/bc is high during read or write command time a burst length of 8 is selected (bl8otf mode). when a12/bc is low, a burst chop of 4 is selected (bc4 otf mode). auto-precharge can be enabled or disabled. 10 b bc4mrs mode with fixed burst chop of 4 with t ccd =4 n ck . a12/bc is don?t care at read or write command time. 11 b tbd reserved rbt a3 read burst type 0 b nibble sequential 1 b interleaved cl a[6:4,2] cas latency (cl) cas latency is the delay, in clock cycles, between the internal read command and the availability of the first bit of output data. note: all other bit combinations are reserved. 0000 b reserved 0010 b 5 0100 b 6 0110 b 7 1000 b 8 1010 b 9 1100 b 10 1110 b 11 0 3 % + % $ % $ % $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ 7 0 & / 5 % 7 % / : 5 3 3 ' ' / / u h v & / idsh1g?0[2/3/4]a1f1c 1-gbit double-data-rate-three sdram advance internet data sheet rev. 0.63, 2008-06 16 12192007-s9ar-zt6n tm a7 test mode the normal operating mode is selected by mr0(bit a7 = 0) and all other bits set to the desired values shown in this table. programming bit a7 to a 1 plac es the ddr3 sdram into a test mode that is only used by the sdram manufacturer and s hould not be used. no operations or functionality is guaranteed if a7 = 1. 0 b normal mode 1 b vendor specific test mode dllres a8 dll reset the internal dll reset bit is self-clearing, meaning it returns back to the value of 0 after the dll reset function has been issued. once the dll is enabled, a subsequent dll reset should be applied. any time the dll reset function is used, t dllk must be met before any function s that require the dll can be used (i.e. read commands or synchronous odt operations). 0 b no dll reset 1 b dll reset triggered wr a[11:9] write recovery fo r auto-precharge number of clock cycles for write recovery during auto-precharge. wr min in clock cycles is calculated by dividing t wr.min (in ns) by the actual t ck.avg (in ns) and rounding up to the next integer: wr.min [ n ck ] = roundup( t wr.min [ns] / t ck.avg [ns]). the wr value in the mode regi ster must be programmed to be equal or larger than wr.min. the resulting wr value is also used with t rp to determine t dal . since wr of 9 and 11 is not implemented in ddr3 and the above fo rmula results in these values, higher values have to be programmed. 000 b reserved 001 b 5 010 b 6 011 b 7 100 b 8 101 b 10 110 b 12 111 b reserved ppd a12 precharge power-down dll control active power-down will always be with dll-on. bit a1 2 will have no effect in this case. for precharge power-down, bit a12 in mr0 is used to select the dll usage as shown below. 0 b slow exit. dll is frozen during precharge power-down.read and synchronous odt commands are only allowed after t xpdll . 1 b fast exit. dll remains on during precharge power-down.any command can be applied after t xp , provided that other timing parameters are satisfied. 1) a13, a14 and a15 - even if not available on a specific device - must be programmed to 0 b . field bits 1) description idsh1g?0[2/3/4]a1f1c 1-gbit double-data-rate-three sdram advance internet data sheet rev. 0.63, 2008-06 17 12192007-s9ar-zt6n 2.3 mode register 1 (mr1) the mode register mr1 stores the data for enabling or disabling the dll, out put driver strength, r tt_nom impedance, additive latency (al), write leveling enable and qoff (output disable). the mode register mr1 is written by asserting low on cs , ras , cas , we , high on ba0 and low on ba1and ba2, while controlling the states of address pins according to table 8 . table 8 mr1 mode register definition (ba[2:0]=001 b ) field bits 1) description dlldis a0 dll disable the dll must be enabled for normal operation. d ll enable is required during power up initialization, after reset and upon returning to normal operation after having the dll disabled. during normal operation (dll-on) with mr1(a0 = 0), the dll is automatically disabled when entering self-refresh operation and is automatical ly re-enabled and reset upon exit of self-refresh operation. any time the dll is enabled, a dll reset must be issued afterwards. any time the dll is reset, t dllk clock cycles must occur before a read or synchronous odt command can be issued to allow time for the internal clock to be synchronized with the external clock. failing to wait for synchronization to occur may result in a violation of the t dqsck , t aon , t aof or t adc parameters. during t dllk , cke must continuously be registered high. ddr3 sdram does not require dll for any write operation. . 0 b dll is enabled 1 b dll is disabled dic a[5, 1] output driver impedance control note: all other bit combinations are reserved. 00 b nominal drive strength ro n40 = rzq/6 (nominal 40.0 , with nominal rzq = 240 ) 01 b nominal drive strength ro n34 = rzq/7 (nominal 34.3 , with nominal rzq = 240 ) r tt_nom a[9, 6, 2] nominal termination resistance of odt notes 1. if r tt_nom is used during writes, only the values r zq /2, r zq /4 and r zq /6 are allowed. 2. in write leveling mode (mr1[bit7 ] = 1) with mr1[bit12] = 1, all r tt _nom settings are allowed; in write leveling mode (mr1[bit7] = 1) with mr1[bit12] = 0, only r tt_nom settings of r zq /2, r zq /4 and r zq /6 are allowed. 3. all other bit combinations are reserved. 000 b odt disabled, r tt_nom = off, dynamic odt mode disabled 001 b rtt60 = rzq / 4 (nominal 60 with nominal rzq = 240 ) 010 b rtt120 = rzq / 2 (nominal 120 with nominal rzq = 240 011 b rtt40 = rzq / 6 (nominal 40 with nominal rzq = 240 ) 100 b rtt20 = rzq / 12 (nominal 20 with nominal rzq = 240 ) 101 b rtt30 = rzq / 8 (nominal 30 with nominal rzq = 240 ) 0 3 % + % $ % $ % $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ / h y h o ' , & $ / ' / / g l v 7 ' 4 6 4 r i i 5 7 7 b q r p 5 7 7 b q r p 5 7 7 b q r p ' , & idsh1g?0[2/3/4]a1f1c 1-gbit double-data-rate-three sdram advance internet data sheet rev. 0.63, 2008-06 18 12192007-s9ar-zt6n al a[4, 3] additive latency (al) any read or write command is held for the time of additive latency (al) before it is issued as internal read or write command. notes 1. al has a value of cl - 1 or cl - 2 as per the cl value programmed in the mr0 register. 00 b al = 0 (al disabled) 01 b al = cl - 1 10 b al = cl - 2 11 b reserved level a7 write leveling mode 0 b write leveling mode disabled, normal operation mode 1 b write leveling mode enabled tdqs a11 tdqs enable 0 b disable 1 b enable qoff a12 output disable under normal operation, the sdram outputs are e nabled during read operation and write leveling for driving data (qoff bit in the mr1 is set to 0 b ). when the qoff bit is set to 1 b , the sdram outputs (dq, dqs, dqs , also on upper byte lane in case of 16) will be disabled - also during write leveling. disabling the sdram outputs allows users to run write leveling on multiple ranks and to measure i dd currents during read operations , without including the output. 0 b output buffer enabled 1 b output buffer disabled 1) a13, a14, a15 - even if not available on a specific device - must be programmed to 0 b . field bits 1) description idsh1g?0[2/3/4]a1f1c 1-gbit double-data-rate-three sdram advance internet data sheet rev. 0.63, 2008-06 19 12192007-s9ar-zt6n 2.4 mode register 2 (mr2) the mode register mr2 stores the data for controlling refresh related features, r tt_wr impedance, and cas write latency. the mode register mr2 is written by asserting low on cs , ras , cas , we , high on ba1 and low on ba0 and ba2, while controlling the states of address signals according to table 9 . table 9 mr2 mode register definition (ba[2:0]=010 b ) field bits 1) description pasr a[2:0] partial array self refresh (pasr) if pasr (partial array self refresh) is enabled, data located in areas of the array beyond the specified self refresh loca tion may get lost if self refresh is entered. during non-self-refresh operation, data integrity will be maintained if t refi conditions are met. 000 b full array (banks 000 b - 111 b ) 001 b half array(banks 000 b - 011 b ) 010 b quarter array(banks 000 b - 001 b ) 011 b 1/8th array (banks 000 b ) 100 b 3/4 array(banks 010 b - 111 b ) 101 b half array(banks 100 b - 111 b ) 110 b quarter array(banks 110 b - 111 b ) 111 b 1/8th array(banks 111 b ) cwl a[5:3] cas write latency (cwl) number of clock cycles from internal write command to first write data in. 000 b 5 (3.3 ns t ck.avg 2.5 ns) 001 b 6 (2.5 ns > t ck.avg 1.875 ns) 010 b 7 (1.875 ns > t ck.avg 1.5 ns) 011 b 8 (1.5 ns > t ck.avg 1.25 ns) note: besides cwl limitations on t ck.avg , there are also t aa.min/max restrictions that need to be observed. for details, please refer to ?speed bins? on page 36 . asr a6 auto self refresh (asr) when enabled, ddr3 sdram will automatically provid e appropriate self refr esh entry all supported operating temperature values. if not enabled, the srt bit must be programmed to indicate t oper during subsequent self refresh operation. 0 b disabled, manual self-refresh reference (srt) 1 b auto self refresh enabled 0 3 % + % $ % $ % $ $ $ $ $ $ $ $ $ $ $ $ $ $ u h j d g g u 6 5 7 $ 6 5 & : / 3 $ 6 5 $ 5 7 7 b : 5 idsh1g?0[2/3/4]a1f1c 1-gbit double-data-rate-three sdram advance internet data sheet rev. 0.63, 2008-06 20 12192007-s9ar-zt6n srt a7 self-refresh temperature range (srt) if asr = 0, the srt bit must be programmed to indicate t oper during subsequent self refresh operation. if asr = 1, sr t bit must be set to 0 b . 0 b normal operating temperature range 1 b extended operating temperature range r tt_wr a[10:9] dynamic odt mode and r tt_wr pre-selection notes 1. the r tt_wr value can be applied during writes even when r tt_nom is disabled. during write leveling, dynamic odt is not available. 00 b dynamic odt mode disabled 01 b dynamic odt mode enabled with r tt_wr = rzq/4 = 60 10 b dynamic odt mode enabled with r tt_wr = rzq/2 = 120 1) a13, a14, a15 - even if not available on a specific device - must be programmed to 0 b . field bits 1) description idsh1g?0[2/3/4]a1f1c 1-gbit double-data-rate-three sdram advance internet data sheet rev. 0.63, 2008-06 21 12192007-s9ar-zt6n 2.5 mode register 3 (mr3) the mode register mr3 controls multi purpose registers and optional on-die thermal sensor (odts) feature. the mode register mr3 is written by asserting low on cs , ras , cas , we , high on ba1 and ba0, and low on ba2 while controlling the states of address signals according to table 10 . table 10 mr3 mode register definition (ba[2:0]=011 b ) field bits 1) 1) a13, a14 and a15 - even if not available on a specific device - must be programmed to 0 b . description mpr loc a[1:0] multi purpose register location 00 b pre-defined data pattern for read synchronization 01 b rfu 10 b rfu 11 b rfu mpr a2 multi purpose register enable 0 b mpr disabled, normal memory operation 1 b dataflow from the multi purpose register mpr 0 3 % + % $ % $ % $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ 0 3 5 0 3 5 o r f idsh1g?0[2/3/4]a1f1c 1-gbit double-data-rate-three sdram advance internet data sheet rev. 0.63, 2008-06 22 12192007-s9ar-zt6n 2.6 read / write operat ions and access modes after a bank has been activated, a read or write access can be executed. this is accomplished by setting ras high, cs and cas low at the clock?s rising edge. we must also be defined at this time to dete rmine whether the access cycle is a read operation (we high) or a write operation (we low). the ddr3 sdram provides a burst column access operation. a single read or write command will initiate a serial read or write operat ion on successive clock edges. 2.6.1 burst order accesses within a given burst may be interleaved or nibble sequential depending on the programmed bit a3 in the mode register mr0. regarding read commands, the lower 3 column address bits ca[2:0] at read command time determine the start address for the read burst. regarding write commands, the burst order is always fixed. for writes with a burst length of 8, the inputs on the lower 3 column address bits ca[2:0] are ignored during the write command. for writes with a burst being chopped to 4, the input on column address 2 (ca[2]) determines if the lower or upper four burst bits are selected. in this case, the inputs on the lower 2 column address bits ca[1:0] are ignored during the write command.the follo wing table shows burst order versus burst start address for r eads and writes of bursts of 8 as well as of bursts of 4 operation (burst chop). table 11 bit order during burst burst length command column address 2:0 interleaved burst sequence nibble sequential burst sequence note bit order within burst bit order within burst ca2 ca1 ca0 1. 2. 3. 4. 5. 6. 7. 8. 1. 2. 3. 4. 5. 6. 7. 8. 8 read 0 0 0 0 123 4 567 0 123 4 567 1) 001 1 032 5 476 1 230 5 674 1) 010 2 301 6 745 2 301 6 745 1) 011 3 210 7 654 3 012 7 456 1) 100 4 567 0 123 4 567 0 123 1) 101 5 476 1 032 5 674 1 230 1) 110 6 745 2 301 6 745 2 301 1) 111 7 654 3 210 7 456 3 012 1) write v v v 0 123 4 567 0 123 4 567 1)2) 4 (burst chop mode) read 0 0 0 0 123 t ttt 0 123 t ttt 1)3)4) 001 1 032 t ttt 1 230 t ttt 1)3)4) 010 2 301 t ttt 2 301 t ttt 1)3)4) 011 3 210 t ttt 3 012 t ttt 1)3)4) 100 4 567 t ttt 4 567 t ttt 1)3)4) 101 5 476 t ttt 5 674 t ttt 1)3)4) 110 6 745 t ttt 6 745 t ttt 1)3)4) 111 7 654 t ttt 7 456 t ttt 1)3)4) write 0 v v 0 123 x xxx 0 123 x xxx 1)2)4)5) 1vv 4 567 x xxx 4 567 x xxx 1)2)4)5) idsh1g?0[2/3/4]a1f1c 1-gbit double-data-rate-three sdram advance internet data sheet rev. 0.63, 2008-06 23 12192007-s9ar-zt6n 1) 0...7 bit number is value of ca[2:0] that caus es this bit to be the first read during a burst. 2) v: a valid logic level (0 or 1), but respec tive buffer input ignores level on input pins. 3) t: output drivers for data and strobe are in high impedance. 4) in case of bc4mrs (burst length being fixed to 4 by mr0 se tting), the internal write operation starts two cloc k cycles earlie r than for the bl8 modes. this means that the starting point for t wr and t wtr will be pulled in by two clocks. in ca se of bc4otf mode (burst length being selected on-the-fly via a12/bc ), the internal write operation starts at the same point in time as a burst of 8 write operation. this means that during on-the-fly control, the starting point for t wr and t wtr will not be pulled in by two clocks. 5) x: don?t care idsh1g?0[2/3/4]a1f1c 1-gbit double-data-rate-three sdram advance internet data sheet rev. 0.63, 2008-06 24 12192007-s9ar-zt6n 3 operating conditions and interface specification 3.1 absolute maximum ratings table 12 absolute maximum ratings parameter symbol rating unit note min. max. voltage on v dd ball relative to v ss v dd ?0.4 +1.975 v 1)2) 1) stresses greater than those listed under ?a bsolute maximum ratings? may cause permanent damage to the device. this is a stres s rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may a ffect reliability. 2) v dd and v ddq must be within 300mv of each other at all times. v refdq and v refca must not be greater than 0.6 v ddq . when v dd and v ddq are less than 500 mv, v refdq and v refca may be equal or less than 300 mv. voltage on v ddq ball relative to v ss v ddq ?0.4 +1.975 v 1)2) voltage on any ball relative to v ss v in , v out ?0.4 +1.975 v 1) storage temperature t stg ?55 +100 c 1)3) 3) storage temperature is the case surface temperature on the ce nter/top side of the sdram. for the measurement conditions, plea se refer to jesd51-2 standard. idsh1g?0[2/3/4]a1f1c 1-gbit double-data-rate-three sdram advance internet data sheet rev. 0.63, 2008-06 25 12192007-s9ar-zt6n 3.2 operating conditions table 13 sdram component operating temperature range table 14 dc operating conditions parameter symbol rating unit note min. max. normal operating temperature range t oper 085 c 1)2)3) 1) operating temperature t oper is the case surface temperature on the center / top side of the sdram. for meas urement conditions, please refer to the jedec document jesd51-2. 2) the normal temperature range specifies the temperatur es where all sdram specif ication will be supported. 3) during operation, the sdram operating temperature must be main tained above 0 c under all oper ating conditions. either the de vice operating temperature rating may be used to set an appropriate refr esh rate and/or to monitor the maximum operating temperature . extended temperature range 85 95 c 1)3)4) 4) some application require operation of the dram in the extended temperature range between 85 c and 95 c operating temperature. full specifications are provi ded in this range, but the follow ing additional conditions apply: a) refresh commands have to be doubled in frequenc y, therefore reducing the refresh interval t refi to 3.9 s. b) if self-refresh operation is required in the extended temperature range, than it is mandatory to either use the manual self-refresh mode with extended temperature range capability (mr2 a6 = 0 b and mr2 a7 = 1 b ) or enable the auto self-refresh mode (asr) (mr2 a6 = 1 b and mr2 a7= 0 b ). for sdram operations on dimm module refer to dimm module data sheets and spd bytes for extended temperature and auto self-refresh option availability. parameter symbol min. typ. max. unit note supply voltage v dd 1.425 1.5 1.575 v 1)2) 1) v ddq tracks with v dd . ac parameters are measured with v dd and v ddq tied together 2) under all conditions v ddq must be less than or equal to v dd . supply voltage for output v ddq 1.425 1.5 1.575 v 1)2) reference voltage for dq, dm inputs v refdq.dc 0.49 v dd 0.5 v dd 0.51 v dd v 3)4) 3) the ac peak noise on v ref may not allow v ref to deviate from v ref.dc by more than 1% v dd (for reference: approx. 15 mv). 4) for reference: approx. v dd /2 15 mv. reference voltage for add, cmd inputs v refca.dc 0.49 v dd 0.5 v dd 0.51 v dd v 3)4) external calibration resistor connected from zq ball to ground r zq 237.6 240.0 242.4 5) 5) the external calibration resistor r zq can be time-shared among drams in multi-rank dimms. idsh1g?0[2/3/4]a1f1c 1-gbit double-data-rate-three sdram advance internet data sheet rev. 0.63, 2008-06 26 12192007-s9ar-zt6n table 15 input and output leakage currents 3.3 interface test conditions figure 4 represents the effective reference load of 25 used in defining the relevant timing parameters of the device as well as for output slew rate measurements. it is not intended as either a precise representation of the typical system environment nor a depiction of the actual load presented by a production tester. system designers should use ibis or other simulation tools to correlate the timing reference load to a system environment. qimonda correlates to its production test conditions, generally one or more coaxial transmission lines terminated at the tester electronics. figure 4 reference load for ac timings and output slew rates the timing reference points are the idealized input and output nodes / terminals on the outside of the packaged sdram device as they would appear in a schematic or an ibis model. the output timing reference voltage level for single ended signals is the cross point with v tt. the output timing reference voltage level for differential signals is the cross point of the true (e.g. dqs) and the complement (e.g. dqs ) signal. parameter symbol condition rating unit note min. max. input leakage current i il any input 0 v < v in < v dd ?2 +2 a 1)2) 1) all other balls not under test = 0 v. 2) values are shown per ball. output leakage current i ol 0v < v out < v ddq ?5 +5 a 2)3) 3) dq?s, dqs, dqs and odt are disabled. 0 3 % + 9 ' ' 4 & . & . ' 8 7 r k p ' 4 ' 4 6 ' 4 6 9 7 7 9 ' ' 4 7 l p l q j 5 h i h u h q f h 3 r l q w v idsh1g?0[2/3/4]a1f1c 1-gbit double-data-rate-three sdram advance internet data sheet rev. 0.63, 2008-06 27 12192007-s9ar-zt6n 3.4 voltage levels 3.4.1 dc and ac logic input levels table 16 shows the input levels for single-ended input signals for address and control signals. table 17 shows the input levels for single-ended input signals for dq and dm signals. table 16 dc and ac input levels for single-ended command, address and control signals table 17 dc and ac input levels for single-ended dq and dm signals parameter symbol ddr3-800, ddr3-1066 ddr3-1333, ddr3-1600 unit note min. max. min. max. dc input logic high v ih.ca.dc v ref + 0.100 v dd v ref + 0.100 v dd v 1) 1) for input only pins except reset: v ref = v ref.ca dc input logic low v il.ca.dc v ss v ref - 0.100 v ss v ref - 0.100 v 1) ac input logic high v ih.ca.ac v ref + 0.175 see 2) 2) see chapter 3.9 , overshoot and undershoot specification . v ref + 0.175 see 2) v 1) ac input logic low v il.ca.ac see 2) v ref - 0.175 see 2) v ref - 0.175 v 1) reduced ac input logic high v ih.ca.ac150 v ref + 0.150 see 2) v ref + 0.150 see 2) v 1) reduced ac input logic low v il.ca.ac150 see 2) v ref - 0.150 see 2) v ref - 0.150 v 1) parameter symbol ddr3-800, ddr3-1066 ddr3-1333, ddr3-1600 unit note min. max. min. max. dc input logic high v ih.dq.dc v ref + 0.100 v dd v ref + 0.100 v dd v 1) 1) for dq and dm: v ref = v refdq , for input only signals except reset : v ref = v refca dc input logic low v il.dq.dc v ss v ref - 0.100 v ss v ref - 0.100 v 1) ac input logic high v ih.dq.ac v ref + 0.175 see 2) 2) see chapter 3.9 , overshoot and undershoot specification . v ref + 0.150 see 2) v 1) 3) 3) single ended swing requirement for dqs, dqs is 350 mv (peak to peak). differential swing requirement for dqs, dqs is 700 mv (peak to peak). ac input logic low v il.dq.ac see 2) v ref - 0.175 see 2) v ref - 0.150 v 1) 3) idsh1g?0[2/3/4]a1f1c 1-gbit double-data-rate-three sdram advance internet data sheet rev. 0.63, 2008-06 28 12192007-s9ar-zt6n differential swing requiremen t for differential signals table 18 shows the input levels for differential input signals. table 18 differential swing requirement for clock (ck - ck ) and strobe (dqs - dqs ) table 19 allowed time before ringback ( t dvac ) for clk - clk and dqs - dqs single-ended requirements for differential signals each individual component of a differential signal (for 4, 8: ck, dqs, ck , dqs , for 16: ck, dqsl, dqsu, ck , dqsl , dqsu ) has also to comply with certain requirements for single-ended signals. ck and ck have to approximately reach v seh.min / v sel.max (approximately equal to the ac- levels ( v ih.ca.ac / v il.ca.ac ) for add/cmd signals) in every half-cycle. dqs, dqs ( 4, 8) and dqsl, dqsl , dqsu, dqsu (16), respective ly, have to reach v seh.min / v sel.max (approximately the ac-levels ( v ih.dq.ac / v il.dq.ac ) for dq signals) in every half-cycle pr eceeding and following a valid transition. note that the applicable ac-levels for add/cmd and dqs might be different per speed-bin etc. e.g. if v ih.ca.ac150 / v il.ca.ac150 is used for add/cmd signals, then parameter symbol ddr3?800, ddr3?1066, ddr3?1333, ddr3?1600 unit note min. max. differential input high v ih.diff +0.200 see 1) 1) these values are not defined, however they single-ended signals ck, ck , dqs, dqs , dqsl, dqsl , dqsu, dqsu need to be within the respective limits ( v ih.dc.max , v il.dc.min ) for single-ended signals as we ll as the limitations for ov ershoot and undershoot. refer to chapter 3.9 . v 2) 2) used to define a differential signal slew-rate. differential input low v il.diff see 1) ?0.200 v 2) differential input high ac v ih.diff.ac 2 ( v ih.ac - v ref ) 3) 3) clock: use v ih.ca.ac for v ih.ac . strobe: use v ih.dq.ac for v ih.ac . see 1) v 4) 4) for ck - ck use v ih / v il.ca.ac of add/cmd and v refca ; for dqs - dqs ( 4, 8); or dqsl - dqsl , dqsu - dqsu ( 16) use v ih / v il.dq.ac of dqs and v refdq ; if a reduced ac-high or ac-low level is used for a signal group, then the reduced level applies also here. differential input low ac v il.diff.ac see 1) 2 ( v ref - v il.ac ) 5) 5) clock: use v il.ca.ac for v il.ac . strobe: use v il.dq.ac for v il.ac . v 4) slew rate [v/ns] t dvac [ps] @ | v ih/il.diff.ac | = 350mv t dvac [ps] @ | v ih/il.diff.ac | = 300mv min. max. min. max. > 4.0 75 ? 175 ? 4.0 57 ? 170 ? 3.0 50 ? 167 ? 2.0 38 ? 163 ? 1.8 34 ? 162 ? 1.6 29 ? 161 ? 1.4 22 ? 159 ? 1.2 13 ? 155 ? 1.0 0 ? 150 ? <1.0 0 ? 150 ? idsh1g?0[2/3/4]a1f1c 1-gbit double-data-rate-three sdram advance internet data sheet rev. 0.63, 2008-06 29 12192007-s9ar-zt6n these ac-levels apply also for the single-ended signals ck and ck . note that while add/cmd and dq signal requirements are with respect to v ref , the single-ended components of differential signals have a requirement with respect to v dd /2; this is nominally the same. the transition of single-ended signals through the ac-levels is used to measure setup time. for single-ended components of differential signals the requirement to reach v sel.max , v seh.min has no bearing on timing, but adds a restri ction on the common mode charateristics of these signals. table 20 each single-ended levels for ck, ck , dqs, dqs , dqsl, dqsl , dqsu or dqsu table 21 cross point voltage for differential input signals (ck, dqs) parameter symbol ddr3?800, ddr3?1066, ddr3?1333, ddr3?1600 unit note min. max. single-ended high-level for strobes v seh (v dd /2) + 0.175 see 1) 1) these values are not defined, however they single-ended signals ck, ck , dqs, dqs , dqsl, dqsl , dqsu, dqsu need to be within the respective limits ( v ih.dc.max , v il.dc.min ) for single-ended signals as well as the limitations for overshoot and undershoot. v 2)3) 2) for ck, ck use v ih.ca.ac / v il.ca.ac of add/cmd; for strobes (dqs, dqs , dqsl, dqsl , dqsu, dqsu ) use v ih.dq.ac / v il.dq.ac of dqs. 3) v ih.dq.ac / v il.dq.ac for dqs is based on v refdq ; v ih.ca.ac / v il.ca.ac for add/cmd is based on v refca ; if a reduced ac-high or ac-low level is used for a signal group, then the reduced level applies also here. single-ended high-level for ck, ck v seh (v dd /2) + 0.175 see 1) v single-ended low-level for strobes v sel see 1) (v dd /2) - 0.175 v single-ended low-level for ck, ck v sel see 1) (v dd /2) - 0.175 v symbol parameter ddr3?800, ddr3?1066, ddr3?1333, ddr3?1600 unit note min. max. v ix differential input cross point voltage relative to v dd /2 for ck - ck ?150 150 mv ?175 175 mv 1) 1) extended range for v ix is only allowed for clock and if single-ended clock input signals ck and ck are monotonic, have a single-ended swing v sel / v seh (see single-ended requirements for differential signals ) of at least v dd /2 +/-250 mv and if the differential slew rate of ck - ck is larger than 3 v/ns. v ix differential input cross point voltage relative to v dd /2 for dqs -dqs ?150 150 mv idsh1g?0[2/3/4]a1f1c 1-gbit double-data-rate-three sdram advance internet data sheet rev. 0.63, 2008-06 30 12192007-s9ar-zt6n 3.4.2 dc and ac output measurements levels table 22 dc and ac output levels for single-ended signals table 23 ac output levels for differential signals parameter symbol value unit note dc output high measurement level (for output impedance measurement) v oh.dc 0.8 v ddq v dc output mid measurement level (f or output impedance measurement) v om.dc 0.5 v ddq v dc output low measurement level (for output impedance measurement) v ol.dc 0.2 v ddq v ac output high measurement le vel (for output slew rate) v oh.ac v tt + 0.1 v ddq v 1) 1) background: the swing of 0.1 v ddq is based on approximately 50% of the static differential output high or low swing with a driver impedance of 40 and an effective test load of 25 to v tt = v ddq / 2. ac output low measurement level (for output slew rate) v ol.ac v tt - 0.1 v ddq v 1) parameter symbol value unit note min. max. ac differential output high measurement level (for output slew rate) v oh.diff.ac +0.2 v ddq v 1) 1) background: the swing of 0.2 v ddq is based on approximately 50% of the static differential output high or low swing with a driver impedance of 40 and an effective test load of 25 to v tt = v ddq / 2 at each of the differential outputs. ac differential output low measurem ent level (for output slew rate) v ol.diff.ac ?0.2 v ddq v 1) deviation of the output cross point voltage from the termination voltage v ox -100 100 mv 2) 2) with an effective test load of 25 to v tt = v ddq /2 at each of the differential outputs (see chapter chapter 3.3 , interface test conditions ). idsh1g?0[2/3/4]a1f1c 1-gbit double-data-rate-three sdram advance internet data sheet rev. 0.63, 2008-06 31 12192007-s9ar-zt6n 3.5 odt dc impedance and mid-level characteristics table 24 provides the odt dc impedance and mid-level characteristics. table 24 odt dc impedance and mid-level characteristics 3.6 odt dc impedance sensitivity on temperature and voltage drifts if temperature and/or volta ge change after calibration, the tolerance limits widen for r tt according to the fo llowing tables. the following definitions are used: t = t - t (at calibration) v = v ddq - v ddq (at calibration) v dd = v ddq table 25 odt dc impedance after proper io calibration and voltage/temperature drift symbol description v out condition min. nom. max. unit note r tt120 r tt effective = 120 v il.ac and v ih.ac 0.9 1.0 1.6 r zq /2 1)2)3)4) 1) with r zq = 240 . 2) measurement definition for r tt : apply v ih.ac and v il.ac to test ball separately, then measure current i ( v ih.ac ) and i ( v il.ac ) respectively. r tt = [ v ih.ac - v il.ac ] / [ i ( v ih.ac ) - i ( v il.ac )] 3) the tolerance limits are specified after calibration with st able voltage and temperature. for the behaviour of the tolerance limits if temperature or voltage changes after calibration, see the odt dc impedance sensitivity on temperature and voltage drifts . 4) the tolerance limits are specified under the condition that v ddq = v dd and that v ssq = v ss . r tt60 r tt effective = 60 0.9 1.0 1.6 r zq /4 1)2)3)4) r tt40 r tt effective = 40 0.9 1.0 1.6 r zq /6 1)2)3)4) r tt30 r tt effective = 30 0.9 1.0 1.6 r zq /8 1)2)3)4) r tt20 r tt effective = 20 0.9 1.0 1.6 r zq /12 1)2)3)4) v m deviation of v m with respect to v ddq / 2 floating ?5 ? +5 % 1)2)3)4)5) 5) measurement definition for v m : measure voltage ( v m ) at test ball (midpoint) with no load: v m = (2 v m / v ddq - 1) 100% symbol value unit note min. max. r tt 0.9 - d r tt dt | t| - d r tt dv | v| 1.6 + d r tt dt | t| + d r tt dv | v| r zq / tisf rtt 1) 1) tisf rtt : termination impedance scaling factor for r tt : tisf rtt = 12 for r tt020 tisf rtt = 8 for r tt030 tisf rtt = 6 for r tt040 tisf rtt = 4 for r tt060 tisf rtt = 2 for r tt120 idsh1g?0[2/3/4]a1f1c 1-gbit double-data-rate-three sdram advance internet data sheet rev. 0.63, 2008-06 32 12192007-s9ar-zt6n table 26 otd dc impedance sensitivity parameters 3.7 output slew rate definition and requirements the slew rate definition depends if the signal is single-ended or differential. for the relevant ac output reference levels see chapter 3.4.2 . 3.7.1 output slew rates table 27 output slew rates symbol value unit note min. max. d r tt dt 0 1.5 %/c 1) 1) these parameters may not be subject to production te st. they are verified by design and characterization. d r tt dv 0 0.15 %/mv parameter symbol ddr3?800, ddr3?1066, ddr3?1333, ddr3?1600 unit note min. max. single-ended output slew rate srqse 2.5 5 1) 1) in two cases, a maximum slew rate of 6 v/ns applies for a single dq signal within a byte lane. - case 1 is defined for a single dq signal within a byte lane which is switching into a certai n direction (either from high to low or l ow to high) while all remaining dq signals in the same byte l ane are static (i.e they stay at either high or low). - case 2 is defined for a single dq signal within a byte lane which is switching into a certai n direction (either from high to low or l ow to high) while all remaining dq signals in the same byte lane are switching into the oppos ite direction (i.e. from low to high or high to low respectively). for the remaining dq signal switching into the op posite direction, the regular ma ximum limit of 5 v/ns applies. v / ns 2)3) 2) for r on = r zq /7 settings only. 3) background for symbol nomenclature: sr: slew rate; q: query output; se: single-ended; diff: differential differential output slew rate srqdiff 5 12 v / ns idsh1g?0[2/3/4]a1f1c 1-gbit double-data-rate-three sdram advance internet data sheet rev. 0.63, 2008-06 33 12192007-s9ar-zt6n 3.8 interface capacitance definition and values for interface capacit ances are provided in the following table. table 28 interface capacitance values parameter signals symbol ddr3?800 ddr3?1066 ddr3?1333 ddr3?1600 unit note min. max. min. max. min. max. min. max. input/output capacitance dq, dm, dqs, dqs c io 1.5 3.0 1.5 2.7 1.5 2.5 1.5 2.3 pf 1)2)3) 1) although the dm signal has different f unction, the loading matches dq and dqs 2) this parameter is not subject to produc tion test. it is verified by design and char acterization. capacitance is measured acco rding to jep147 (procedure for measuring input capacitance us ing a vector network analyzer (vna) with v dd , v ddq , v ss , v ssq applied and all other balls floating (except the ball under test, cke, reset and odt as necessary). v dd = v ddq = 1.5 v, v bias = v dd /2 and on-die termination off 3) this parameter applies to monolithic devices onl y; stacked/dual-die devices are not covered here input capacitance ck, ck c ck 0.8 1.6 0.8 1.6 0.8 1.4 0.8 1.4 pf 2)3) delta of input capacitance ck, ck c dck 0 0.15 0 0.15 0 0.15 0 0.15 pf 2)3)4) 4) absolute value of c ck - c ck# delta of input/output capacitance of dqs balls dqs, dqs c ddqs 0 0.2 0 0.2 0 0.15 0 0.15 pf 2)3)5) 5) absolute value of c io.dqs - c io.dqs# input capacitance all other input-only pins c i 0.75 1.5 0.75 1.5 0.75 1.3 0.75 1.3 pf 2)3)6) 6) c i applies to odt, cs , cke, a[a13:0] ( 4, 8) or a[a12:0] ( 16), ba[2:0], ras , cas , we delta of input capacitance all ctrl input-only pins c di.ctrl ?0.5 0.3 ?0.5 0.3 ?0.4 0.2 ?0.4 0.2 pf 2)3)7)8) 7) c di_ctrl applies to odt, cs and cke 8) c di_ctrl = c i.ctrl - 0.5 ( c ck + c ck# ) delta of input capacitance all add and cmd input-only pins c di.add_cmd ?0.5 0.5 ?0.5 0.5 ?0.4 0.4 ?0.4 0.4 pf 2)3)9) 10) 9) c di_add_cmd applies to a[a13:0] ( 4, 8) or a[a12:0] ( 16), ba[2:0], ba[2:0], ras , cas and we 10) c di_add_cmd = c i.add,cmd - 0.5 ( c i.ck + c i.ck# ) delta of input/output capacitance dq, dm, dqs, dqs c dio ?0.5 0.3 ?0.5 0.3 ?0.5 0.3 ?0.5 0.3 pf 2)3)11) 11) c dio = c io.dq,dm - 0.5 ( c io.dqs + c io.dqs# ) zq capacitance zq c zq ?3?3 ?3 ?3 pf 12) 12) maximum external load capac itance on zq signal: 5 pf idsh1g?0[2/3/4]a1f1c 1-gbit double-data-rate-three sdram advance internet data sheet rev. 0.63, 2008-06 34 12192007-s9ar-zt6n 3.9 overshoot and undershoot specification table 29 ac overshoot / undershoot specification for address and control signals figure 5 ac overshoot / undershoot definitions for address and control signals table 30 ac overshoot / undershoot specification for clock, data, strobe and mask signals parameter ddr3?800 ddr3?1066 ddr3?1333 ddr3?1600 unit note maximum peak amplitude allowed for overshoot area 0.4 0.4 0.4 0.4 v 1) 1) applies for the following signals: a[15:0], ba[3:0], cs , ras , cas , we , cke and odt maximum peak amplitude allowed for undershoot area 0.4 0.4 0.4 0.4 v 1) maximum overshoot area above v dd 0.67 0.5 0.4 0.33 v ns 1) maximum undershoot area below v ss 0.67 0.5 0.4 0.33 v ns 1) parameter ddr3? 800 ddr3? 1066 ddr3? 1333 ddr3? 1600 unit note maximum peak amplitude allowed for overshoot area 0.4 0.4 0.4 0.4 v 1) 1) applies for ck, ck , dq, dqs, dqs & dm maximum peak amplitude allowed for undershoot area 0.4 0.4 0.4 0.4 v 1) maximum overshoot area above v ddq 0.25 0.19 0.15 0.13 v ns 1) maximum undershoot area below v ssq 0.25 0.19 0.15 0.13 v ns 1) 0 3 ( + 9 r o w v 9 9 ' ' 9 6 6 0 d [ l p x p $ p s o l w x g h 7 l p h q v 0 d [ l p x p $ p s o l w x g h 2 y h u v k r r w $ u h d 8 q g h u v k r r w $ u h d idsh1g?0[2/3/4]a1f1c 1-gbit double-data-rate-three sdram advance internet data sheet rev. 0.63, 2008-06 35 12192007-s9ar-zt6n figure 6 ac overshoot / undershoot definitions for clock, data, strobe and mask signals 0 3 ( + 9 r o w v 9 9 ' ' 4 9 6 6 4 0 d [ l p x p $ p s o l w x g h 7 l p h q v 0 d [ l p x p $ p s o l w x g h 2 y h u v k r r w $ u h d 8 q g h u v k r r w $ u h d idsh1g?0[2/3/4]a1f1c 1-gbit double-data-rate-three sdram advance internet data sheet rev. 0.63, 2008-06 36 12192007-s9ar-zt6n 4 speed bins and timing parameters ac timings are provided with ck/ck and dqs/dqs differential slew rate of 2.0 v/ns. timings are further provided for calibrated ocd driv e strength. the ck/ck input reference level (for timing referenced to ck / ck ) is the point at which ck and ck cross. the dqs/dqs reference leve l (for timing referenced to dqs/dqs ) is the point at which dqs and dqs cross. inputs are not re cognized as valid until v ref stabilizes. during the period before v ref.ca and v refdq stabilizes, cke = 0.2 x v ddq is recognized as low. the output timing reference voltage level is v tt . 4.1 speed bins the following tables show ddr3 speed bins and relevant timing parameters. other timi ng parameters are provided in the following chapter. the absolute specification for all speed bins is t oper and v dd = v ddq = 1.5 v +/-0.075 v. in addition the following general notes apply. general notes for speed bins: ? the cl setting and cwl setting result in t ck.avg.min and t ck.avg.max requirements. when making a selection of t ck.avg , both need to be fulfiled: requirements from cl setting as well as requirements from cwl setting ? t ck.avg.min limits: since cas latency is not purely analog - data and strobe output are syn chronized by the dll - all possible intermediate frequencies may not be provided. an application should use the next smaller standard t ck.avg value (2.5, 1.875, 1.5, or 1. 25 ns) when calculating cl [nck] = t aa [ns] / t ck.avg [ns], rounding up to the next ?supported cl? ? t ck.avg.max limits: calculate t ck.avg = t aa.max / clselected and round the resulting t ck.avg down to the next valid speed bin limit (i.e. 3.3 ns or 2.5 ns or 1.875 ns or 1.25 ns). this result is t ck.avg.max corresponding to clselected ? ?reserved? settings are not a llowed. user must program a different value ? any ddr3-1066 speed bin also supports functional operation at lower frequencies as shown in the tables which are not subject to production tests but verified by design/characterization ? any ddr3-1333 speed bin also supports functional operation at lower frequencies as shown in the tables which are not subject to production tests but verified by design/characterization ? any ddr3-1600 speed bin also supports functional operation at lower frequencies as shown in the tables which are not subject to production tests but verified by design/characterization idsh1g?0[2/3/4]a1f1c 1-gbit double-data-rate-three sdram advance internet data sheet rev. 0.63, 2008-06 37 12192007-s9ar-zt6n table 31 ddr3-800 speed bins an d operating conditions speed bin ddr3-800d ddr3-800e unit note cl- n rcd - n rp 5-5-5 6-6-6 qag partnumber extension -08d -08e parameter symbol min. max. min. max. internal read command to first data t aa 12.5 20.0 15.0 20.0 ns 1) 1) please refer to "general notes for speed bins" at beginning of this chapter. act to internal read or write delay time t rcd 12.5 ? 15.0 ? ns 1) pre command period t rp 12.5 ? 15.0 ? ns 1) act to act or ref command period t rc 50.0 ? 52.5 ? ns 1) supported cl settings sup_cl 5, 6 6 n ck 1) supported cwl settings sup_cwl 5 5 n ck 1) average clock period with cl = 5; cwl = 5 t ck.avg.cl05.cwl05 2.5 3.3 reserved ns 1)2) 2) max. limits are exclusive. e.g. if t ck.avg.max value is 2.5 ns, t ck.avg needs to be < 2.5 ns. average clock period with cl = 6; cwl = 5 t ck.avg.cl06.cwl05 2.5 3.3 2.5 3.3 ns 1)2) idsh1g?0[2/3/4]a1f1c 1-gbit double-data-rate-three sdram advance internet data sheet rev. 0.63, 2008-06 38 12192007-s9ar-zt6n table 32 ddr3-1066 speed bins and operating conditions speed bin ddr3-1066e ddr3-1066f ddr3-1066g unit note cl- n rcd - n rp 6-6-6 7-7-7 8-8-8 qag partnumber extension -10e -10f -10g parameter symbol min. max. min. max. min. max. internal read command to first data t aa 11.25 20.0 13.125 20.0 15.0 20.0 ns 1) 1) please refer to "general notes for speed bins" at beginning of this chapter. act to internal read or write delay time t rcd 11.25 ? 13.125 ? 15.0 ? ns 1) pre command period t rp 11.25 ? 13.125 ? 15.0 ? ns 1) act to act or ref command period t rc 48.75 ? 50.625 ? 52.5 ? ns 1) supported cl settings sup_cl 5, 6, 7, 8 6, 7, 8 6, 8 n ck 1) supported cwl settings sup_cwl 5, 6 5, 6 5, 6 n ck 1) average clock period with cl = 5; cwl = 5 t ck.avg.cl05.cwl05 2.5 3.3 reserved reserved ns 1)2) 2) max. limits are exclusive. e.g. if t ck.avg.max value is 2.5 ns, t ck.avg needs to be < 2.5 ns. average clock period with cl = 5; cwl = 6 t ck.avg.cl05.cwl06 reserved reserved reserved ns 1)2) average clock period with cl = 6; cwl = 5 t ck.avg.cl06.cwl05 2.5 3.3 2.5 3.3 2.5 3.3 ns 1)2) average clock period with cl = 6; cwl = 6 t ck.avg.cl06.cwl06 1.875 2.5 reserved reserved ns 1)2) average clock period with cl = 7; cwl = 5 t ck.avg.cl07.cwl05 reserved reserved reserved ns 1)2) average clock period with cl = 7; cwl = 6 t ck.avg.cl07.cwl06 1.875 2.5 1.875 2.5 reserved ns 1)2) average clock period with cl = 8; cwl = 5 t ck.avg.cl08.cwl05 reserved reserved reserved ns 1)2) average clock period with cl = 8; cwl = 6 t ck.avg.cl08.cwl06 1.875 2.5 1.875 2.5 1.875 2.5 ns 1)2) idsh1g?0[2/3/4]a1f1c 1-gbit double-data-rate-three sdram advance internet data sheet rev. 0.63, 2008-06 39 12192007-s9ar-zt6n table 33 ddr3-1333 speed bins and operating conditions speed bin ddr3-1333g ddr3-1333h unit note cl-nrcd-nrp 8-8-8 9-9-9 qag partnumber extension -13g -13h parameter symbol min. max. min. max. internal read command to first data t aa 12.0 20.0 13.5 20.0 ns 1) 1) please refer to "general notes for speed bins" at beginning of this chapter. act to internal read or write delay time t rcd 12.0 ? 13.5 ? ns 1) pre command period t rp 12.0 ? 13.5 ? ns 1) act to act or ref command period t rc 48.0 ? 49.5 ? ns 1) supported cl settings sup_cl 5, 6, 7, 8, 9, 10 6, 8, 9, 10 n ck 1) supported cwl settings sup_cwl 5, 6, 7 5, 6, 7 n ck 1) average clock period with cl = 5; cwl = 5 t ck.avg.cl05.cwl05 2.5 3.3 reserved ns 1)2) 2) max. limits are exclusive. e.g. if t ck.avg.max value is 2.5 ns, t ck.avg needs to be < 2.5 ns. average clock period with cl = 5; cwl = 6 t ck.avg.cl05.cwl06 reserved reserved ns 1)2) average clock period with cl = 5; cwl = 7 t ck.avg.cl05.cwl07 reserved reserved ns 1)2) average clock period with cl = 6; cwl = 5 t ck.avg.cl06.cwl05 2.5 3.3 2.5 3.3 ns 1)2) average clock period with cl = 6; cwl = 6 t ck.avg.cl06.cwl06 reserved reserved ns 1)2) average clock period with cl = 6; cwl = 7 t ck.avg.cl06.cwl07 reserved reserved ns 1)2) average clock period with cl = 7; cwl = 5 t ck.avg.cl07.cwl05 reserved reserved ns 1)2) average clock period with cl = 7; cwl = 6 t ck.avg.cl07.cwl06 1.875 2.5 reserved ns 1)2) average clock period with cl = 7; cwl = 7 t ck.avg.cl07.cwl07 reserved reserved ns 1)2) average clock period with cl = 8; cwl = 5 t ck.avg.cl08.cwl05 reserved reserved ns 1)2) average clock period with cl = 8; cwl = 6 t ck.avg.cl08.cwl06 1.875 2.5 1.875 2.5 ns 1)2) average clock period with cl = 8; cwl = 7 t ck.avg.cl08.cwl07 1.5 1.875 reserved ns 1)2) average clock period with cl = 9; cwl = 5 t ck.avg.cl09.cwl05 reserved reserved ns 1)2) average clock period with cl = 9; cwl = 6 t ck.avg.cl09.cwl06 reserved reserved ns 1)2) average clock period with cl = 9; cwl = 7 t ck.avg.cl09.cwl07 1.5 1.875 1.5 1.875 ns 1)2) average clock period with cl = 10; cwl = 5 t ck.avg.cl10.cwl05 reserved reserved ns 1)2) average clock period with cl = 10; cwl = 6 t ck.avg.cl10.cwl06 reserved reserved ns 1)2) average clock period with cl = 10; cwl = 7 t ck.avg.cl10.cwl07 1.5 1.875 1.5 1.875 ns 1)2) idsh1g?0[2/3/4]a1f1c 1-gbit double-data-rate-three sdram advance internet data sheet rev. 0.63, 2008-06 40 12192007-s9ar-zt6n table 34 ddr3-1600 speed bins and operating conditions speed bin ddr3-1600g ddr3-160 0h ddr3-1600j ddr3-1600k unit note cl-nrcd-nrp 8-8-8 9-9-9 10-10-10 11-11-11 qag partnumber extension -16g -16h -16j -16k parameter symbol min. max. min. max. min. max. min. max. internal read command to first data t aa 10.0 20.0 11.25 20.0 12.5 20.0 13.75 20.0 ns 1) act to internal read or write delay time t rcd 10.0 ? 11.25 ? 12.5 ? 13.75 ? ns 1) pre command period t rp 10.0 ? 11.25 ? 12.5 ? 13.75 ? ns 1) act to act or ref command period t rc 45.0 ? 46.25 ? 47.5 ? 48.75 ? ns 1) supported cl settings sup_cl 5, 6, 7, 8, 9, 10, 11 5, 6, 7, 8, 9, 10, 11 5, 6, 7, 8, 9, 10, 11 6, 8, 10, 11 n ck 1) supported cwl settings sup_cwl 5, 6, 7, 8 5, 6, 7, 8 5, 6, 7, 8 5, 6, 7, 8 n ck 1) average clock period with cl = 5; cwl = 5 t ck.avg.cl05.cwl05 2.5 3.3 2.5 3.3 2.5 3.3 reserved ns 1)2) average clock period with cl = 5; cwl = 6 t ck.avg.cl05.cwl06 reserved reserved reserved reserved ns 1)2) average clock period with cl = 5; cwl = 7 t ck.avg.cl05.cwl07 reserved reserved reserved reserved ns 1)2) average clock period with cl = 5; cwl = 8 t ck.avg.cl05.cwl08 reserved reserved reserved reserved ns 1)2) average clock period with cl = 6; cwl = 5 t ck.avg.cl06.cwl05 2.5 3.3 2.5 3.3 2.5 3.3 2.5 3.3 ns 1)2) average clock period with cl = 6; cwl = 6 t ck.avg.cl06.cwl06 1.875 2.5 1.875 2.5 reserved reserved ns 1)2) average clock period with cl = 6; cwl = 7 t ck.avg.cl06.cwl07 reserved reserved reserved reserved ns 1)2) average clock period with cl = 6; cwl = 8 t ck.avg.cl06.cwl08 reserved reserved reserved reserved ns 1)2) average clock period with cl = 7; cwl = 5 t ck.avg.cl07.cwl05 reserved reserved reserved reserved ns 1)2) average clock period with cl = 7; cwl = 6 t ck.avg.cl07.cwl06 1.875 2.5 1.875 2.5 1.875 2.5 reserved ns 1)2) average clock period with cl = 7; cwl = 7 t ck.avg.cl07.cwl07 1.5 1.875 reserved reserved reserved ns 1)2) average clock period with cl = 7; cwl = 8 t ck.avg.cl07.cwl08 reserved reserved reserved reserved ns 1)2) average clock period with cl = 8; cwl = 5 t ck.avg.cl08.cwl05 reserved reserved reserved reserved ns 1)2) idsh1g?0[2/3/4]a1f1c 1-gbit double-data-rate-three sdram advance internet data sheet rev. 0.63, 2008-06 41 12192007-s9ar-zt6n average clock period with cl = 8; cwl = 6 t ck.avg.cl08.cwl06 1.875 2.5 1.875 2.5 1.875 2.5 1.875 2.5 ns 1)2) average clock period with cl = 8; cwl = 7 t ck.avg.cl08.cwl07 1.5 1.875 1.5 1.875 reserved reserved ns 1)2) average clock period with cl = 8; cwl = 8 t ck.avg.cl08.cwl08 1.25 1.5 reserved reserved reserved ns 1)2) average clock period with cl = 9; cwl = 5 t ck.avg.cl09.cwl05 reserved reserved reserved reserved ns 1)2) average clock period with cl = 9; cwl = 6 t ck.avg.cl09.cwl06 reserved reserved reserved reserved ns 1)2) average clock period with cl = 9; cwl = 7 t ck.avg.cl09.cwl07 1.5 1.875 1.5 1.875 1.5 1.875 reserved ns 1)2) average clock period with cl = 9; cwl = 8 t ck.avg.cl09.cwl08 1.25 1.5 1.25 1.5 reserved reserved ns 1)2) average clock period with cl = 10; cwl = 5 t ck.avg.cl10.cwl05 reserved reserved reserved reserved ns 1)2) average clock period with cl = 10; cwl = 6 t ck.avg.cl10.cwl06 reserved reserved reserved reserved ns 1)2) average clock period with cl = 10; cwl = 7 t ck.avg.cl10.cwl07 1.5 1.875 1.5 1.875 1.5 1.875 1.5 1.875 ns 1)2) average clock period with cl = 10; cwl = 8 t ck.avg.cl10.cwl08 1.25 1.5 1.25 1.5 1.25 1.5 reserved ns 1)2) average clock period with cl = 11; cwl = 5 t ck.avg.cl11.cwl05 reserved reserved reserved reserved ns 1)2) average clock period with cl = 11; cwl = 6 t ck.avg.cl11.cwl06 reserved reserved reserved reserved ns 1)2) average clock period with cl = 11; cwl = 7 t ck.avg.cl11.cwl07 reserved reserved reserved reserved ns 1)2) average clock period with cl = 11; cwl = 8 t ck.avg.cl11.cwl08 1.25 1.5 1.25 1.5 1.25 1.5 1.25 1.5 ns 1)2) 1) please refer to "general notes for speed bins" at beginning of this chapter. 2) max. limits are exclusive. e.g. if t ck.avg.max value is 2.5 ns, t ck.avg needs to be < 2.5 ns. speed bin ddr3-1600g ddr3-160 0h ddr3-1600j ddr3-1600k unit note cl-nrcd-nrp 8-8-8 9-9-9 10-10-10 11-11-11 qag partnumber extension -16g -16h -16j -16k parameter symbol min. max. min. max. min. max. min. max. idsh1g?0[2/3/4]a1f1c 1-gbit double-data-rate-three sdram advance internet data sheet rev. 0.63, 2008-06 42 12192007-s9ar-zt6n table 35 ddr3-dll_off speed bins and operating conditions speed bin ddr3-d ll_off unit note cl-nrcd-nrp 6-x-x qag partnumber extension dll_off parameter symbol min. max. internal read command to first data t aa 48.0 ?ns 1) 1) please refer to "general notes for speed bins" at beginning of this chapter. act to internal read or write delay time t rcd 15.0 ? ns 1) pre command period t rp 15.0 ? ns 1) act to act or ref command period t rc 52.5 ? ns 1) supported cl settings sup_cl 6 n ck 1) supported cwl settings sup_cwl 6 n ck 1) average clock period with cl = 6; cwl = 6 t ck.avg.cl06.cwl06 8.0 ? ns 1)2) 2) max. limits are exclusive. e.g. if t ck.avg.max value is 2.5 ns, t ck.avg needs to be < 2.5 ns. idsh1g?0[2/3/4]a1f1c 1-gbit double-data-rate-three sdram advance internet data sheet rev. 0.63, 2008-06 43 12192007-s9ar-zt6n 5 package outline this chapter contains the package dimension figures. figure 7 package outlines. left: pg-tfbga-78 (x4/x8). right: pg-tfbga-96 (x16) idsh1g?0[2/3/4]a1f1c 1-gbit double-data-rate-three sdram advance internet data sheet rev. 0.63, 2008-06 44 12192007-s9ar-zt6n 6 product type nomenclature for reference the applicable qimonda ddr3 com ponent nomenclature is lis ted in this chapter. table 36 example for nomenclature fields table 37 ddr3 sdram nomenclature example for field number 1 2 3 4567 8 9 10 11 12 ddr3 sdram component id sh 1g ? 0 2 a1 f1 c ? 08 e field description value coding 1 qimonda sdram component prefix id qimonda sdram 2 sdram technology sh standard ddr3 3 component density 512 512 mbit 1g 1 gbit 2g 2 gbit 4g 4 gbit 4 module type / ecc support ? no ecc support on sdram level 5 number of chip select 0 1 chip select (2 0 ) 1 2 chip select (2 1 ) 6 number of dqs 2 4 dq lines (2 2 ) 3 8 dq lines (2 3 ) 4 16 dq lines (2 4 ) 5 32 dq lines (2 5 ) 7 die revision a1 first die 8 package f1 planar fbga, lead- and halogen-free f2 dual die fbga, lead- and halogen-free 9 temperature range c commercial (0 c - 95 c) 10 reserved for future use ? rfu 11 band width per dq 08 ddr3?800 = 800 mbit per ball per second, t ck = 2.5 ns 10 ddr3?1066 = 1066 mbit per ball per second, t ck = 1.875 ns 13 ddr3?1333 = 1333 mbit per ball per second, t ck = 1.5 ns 16 ddr3?1600 = 1600 mbit per ball per second, t ck = 1.25 ns idsh1g?0[2/3/4]a1f1c 1-gbit double-data-rate-three sdram advance internet data sheet rev. 0.63, 2008-06 45 12192007-s9ar-zt6n 12 latencies d cl?rcd?rp = 5?5?5 e cl?rcd?rp = 6?6?6 f cl?rcd?rp = 7?7?7 g cl?rcd?rp = 8?8?8 h cl?rcd?rp = 9?9?9 j cl?rcd?rp = 10?10?10 k cl?rcd?rp = 11?11?11 field description value coding idsh1g?0[2/3/4]a1f1c 1-gbit double-data-rate-three sdram advance internet data sheet rev. 0.63, 2008-06 46 12192007-s9ar-zt6n list of illustrations figure 1 ballout for 1gb 4 components (pg-tfbga-78). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 figure 2 ballout for 1gb 8 components (pg-tfbga-78) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 figure 3 ballout for 1gb 16 components (pg-tfbga-96) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 figure 4 reference load for ac timings and output slew rates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 figure 5 ac overshoot / undershoot definitions for address and control signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 figure 6 ac overshoot / undershoot definitions for clock, data, st robe and mask signals . . . . . . . . . . . . . . . . . . . . . 35 figure 7 package outlines. left: pg-tfbga-78 (x4/x8). right: pg-tfb ga-96 (x16) . . . . . . . . . . . . . . . . . . . . . . . . . . 43 idsh1g?0[2/3/4]a1f1c 1-gbit double-data-rate-three sdram advance internet data sheet rev. 0.63, 2008-06 47 12192007-s9ar-zt6n list of tables table 1 ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 table 2 1-gbit ddr3 sdram addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 table 3 input / output signal functional descripti on. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 table 4 command truth table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 table 5 clock enable (cke) truth table for synchronous transitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 table 6 data mask (dm) truth table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 table 7 mr0 mode register definition (ba[2:0]=000 b ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 table 8 mr1 mode register definition (ba[2:0]=001 b ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 table 9 mr2 mode register definition (ba[2:0]=010 b ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 table 10 mr3 mode register definition (ba[2:0]=011 b ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 table 11 bit order during burst . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 table 12 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 table 13 sdram component operating temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 table 14 dc operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 table 15 input and output leakage currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 table 16 dc and ac input levels for single-ended command, address and control signals . . . . . . . . . . . . . . . . . . . 27 table 17 dc and ac input levels for single-ended dq and dm signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 table 18 differential swing requirement for clo ck (ck - ck) and strobe (dqs - dqs) . . . . . . . . . . . . . . . . . . . . . . . . 28 table 19 allowed time before ringback ( t dvac ) for clk - clk and dqs - dqs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 table 20 each single-ended levels for ck, ck, dqs, dqs, dqsl, dqsl, dqsu or dqsu . . . . . . . . . . . . . . . . . . . 29 table 21 cross point voltage for differential input signals (ck, dqs). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 table 22 dc and ac output levels for single-ended signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 table 23 ac output levels for differential signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 table 24 odt dc impedance and mid-level characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 table 25 odt dc impedance after proper io calibration and voltage/temperature drift . . . . . . . . . . . . . . . . . . . . . . . 31 table 26 otd dc impedance sensitivity paramete rs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 table 27 output slew rates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 table 28 interface capacitance values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 table 29 ac overshoot / undershoot specification for address and control signals. . . . . . . . . . . . . . . . . . . . . . . . . . . 34 table 30 ac overshoot / undershoot specification for clock, data, strobe and mask signals . . . . . . . . . . . . . . . . . . . 3 4 table 31 ddr3-800 speed bins and operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 table 32 ddr3-1066 speed bins and operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 table 33 ddr3-1333 speed bins and operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 table 34 ddr3-1600 speed bins and operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 table 35 ddr3-dll_off speed bins and operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 table 36 example for nomenclature fields. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 table 37 ddr3 sdram nomenclature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 idsh1g?0[2/3/4]a1f1c 1-gbit double-data-rate-three sdram advance internet data sheet rev. 0.63, 2008-06 48 12192007-s9ar-zt6n contents 1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1.2 product list. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 1.3 ddr3 sdram addressing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 1.4 package ballout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 1.5 input / output signal functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.1 truth tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.2 mode register 0 (mr0). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.3 mode register 1 (mr1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 2.4 mode register 2 (mr2). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 2.5 mode register 3 (mr3). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 2.6 read / write operations and access modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 2.6.1 burst order . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 3 operating conditions an d interface specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 3.1 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 3.2 operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 3.3 interface test conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 3.4 voltage levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 3.4.1 dc and ac logic input levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 3.4.2 dc and ac output measurements levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 3.5 odt dc impedance and mid-level characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 3.6 odt dc impedance sensitivity on temperature and voltage drifts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 3.7 output slew rate definition and requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 3.7.1 output slew rates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 3.8 interface capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 3.9 overshoot and undershoot specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 4 speed bins and timing parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 4.1 speed bins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 5 package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 6 product type nomenclature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 edition 2008-06 published by qimonda ag gustav-heinemann-ring 212 d-81739 mnchen, germany ? qimonda ag 2008. all rights reserved. legal disclaimer the information given in this internet data sh eet shall in no event be regarded as a guarantee of conditions or characteristics. with respect to any examples or hints given herein, any typical values stated herein an d/or any information regarding the application of the device, qimonda hereby disclaims any and all warranties and liabilities of any ki nd, including without limitation warranties of non-infringement of in tellectual property righ ts of any third party. information for further information on technology, delivery terms and conditio ns and prices please contact your nearest qimonda office. warnings due to technical requirements components may contain dangerous substances. for information on the types in question please contact your nearest qimonda office. qimonda components may only be used in life-support devices or systems with the express writte n approval of qimonda, if a failure of such components can reasonably be expected to cause the failure of that life-support devi ce or system, or to affect the safety or effectiveness of that device or system. life support devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain and/or protect human life. if they fail, it is re asonable to assume that the he alth of the user or other persons may be endangered. www.qimonda.com advance internet data sheet |
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