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hd66712 (lcd-ii/f12) (dot-matrix liquid crystal display controller/driver) description the hd66712 dot-matrix liquid crystal display controller and driver lsi displays alphanumerics, numbers, and symbols. it can be configured to drive a dot-matrix liquid crystal display under the control of a serial or a 4- or 8-bit microprocessor. since all the functions such as display ram, character generator, and liquid crystal driver, required for driving a dot-matrix liquid crystal display are internally provided on one chip, a minimum system can be interfaced with this con- troller/driver. a single hd66712 is capable of displaying a single 24-character line, two 24-character lines, or four 12-character lines. the hd66712 software is upwardly compatible with the lcdii (hd44780) which allows the user to easily replace an lcd-ii with an hd66712. in addition, the hd66712 is equipped with functions such as segment displays for icon marks, a 4-line display mode, and a horizontal smooth scroll, and thus supports various display forms. this achieves various display forms. the hd66712 character generator rom is extended to generate 240 5 8 dot characters. the low-voltage operation (2.7 v) of the hd66712, combined with a low-power mode, is suitable for any portable battery-driven product requiring low power consumption. features ? 8 dot matrix possible clock-synchronized serial interface capability; can interface with 4- or 8-bit mpu low-power operation support: 2.7 to 5.5 v (low voltage) wide liquid-crystal voltage range: 3.0 to 13.0 v max. booster for liquid crystal voltage two/three times (13 v max.) high-speed mpu bus interface (2mhz at 5-v operation) extension driver interface character display and independent 60-icon mark display possible horizontal smooth scroll by 6-dot font width display possible 80 8-bit display ram (80 characters max.) 9,600-bit character generator rom 240 characters (5 8 dot) 64 8-bit character generator ram 8 characters (5 8 dot) 16 8-bit segment icon mark ?96-segment icon mark 34-common 60-segment liquid crystal display driver programmable duty cycle (see list 1) software upwardly compatible with hd44780 wide range of instruction functions: functions compatible with lcd-ii: display clear, cursor home, display on/off, cursor on/off, display character blink, cursor shift, display shift additional functions: icon mark control, 4- line display, horizontal smooth scroll, 6-dot character width control, white-black invert- ing blinking cursor automatic reset circuit that initializes the con- troller/driver after power on (standard version only)
internal oscillator with an external resistor low power consumption qfp 1420-128 pin, tcp-128 pin, bare-chip list 1 programmable duty cycles 5-dot font width number single-chip operation with extension driver of lines duty ratio displayed characters icons displayed characters icons 1 1/17 one 24-character 60 one 52-character 80 line line 2 1/33 two 24-character 60 two 32-character 80 lines lines 4 1/33 four 24-character 60 four 20-character 80 lines lines 6-dot font width number single-chip operation with extension driver of lines duty ratio displayed characters icons displayed characters icons 1 1/17 one 20-character 60 one 50-character 96 line line 2 1/33 two 20-character 60 two 30-character 96 lines lines 4 1/33 four 10-character 60 four 20-character 96 lines lines ordering information type no. package cgrom hd66712a00fs qfp1420-128 (fp-128) japanese standard hd66712a00ta0 standard tcp-128 hd66712a00tb0 * folding tcp-128 hcd66712a00 chip hcd66712a01 chip communication hd66712a02fs qfp1420-128 (fp-128) european font HCD66712A02 chip hcd66712a03 chip japanese + european font hd66712bxxfs qfp1420-128 (fp-128) custom font hcd66712bxx chip note: bxx = rom code no. * under development hd66712 417
lcd-ii family comparison lcd-ii lcd-ii/e20 lcd-ii/f8 lcd-ii/f12 item (hd44780u) (hd66702) (hd66710) hd66712 power supply voltage 2.7 v to 5.5 v 5 v 10 % 2.7 v to 5.5 v 2.7 v to 5.5 v (standard) 2.7 v to 5.5 v (low voltage) liquid crystal drive 3.0 v to 11 v 3.0 v to 8.3 v 3.0 v to 13.0 v 3.0 v to 13.0 v voltage maximum display 8 characters 20 characters 16 characters 24 characters digits per chip 2 lines 2 lines 2 lines/ 2 lines/ 8 characters 12 characters 4 lines 4 lines segment display none none 40 segments 60 segments display duty cycle 1/8, 1/11, and 1/8, 1/11, and 1/17 and 1/33 1/17 and 1/33 1/16 1/16 cgrom 9,920 bits 7,200 bits 9,600 bits 9,600 bits (208 5 8 dot (160 5 7 dot (240 5 8 dot (240 5 8 dot characters and characters and characters) characters) 32 5 10 dot 32 5 10 dot characters) characters) cgram 64 bytes 64 bytes 64 bytes 64 bytes ddram 80 bytes 80 bytes 80 bytes 80 bytes segram none none 8 bytes 16 bytes segment signals 40 100 40 60 common signals 16 16 33 34 liquid crystal drive abbb waveform bleeder resistor for external external external external lcd power supply (adjustable) (adjustable) (adjustable) (adjustable) clock source external resistor external resistor external resistor external resistor or external clock or external clock or external clock or external clock r f oscillation frequency 270 khz 30% 320 khz 30% 270 khz 30% 270 khz 30% (frame frequency) (59 to 110 hz for (70 to 130 hz for (56 to 103 hz for (56 to 103 hz for 1/8 and 1/16 duty 1/8 and 1/16 duty 1/17 duty cycle; 1/17 duty cycle; cycle; 43 to 80 cycle; 51 to 95 57 to 106 hz for 57 to 106 hz for hz for 1/11 duty hz for 1/11 duty 1/33 duty cycle) 1/33 duty cycle) cycle) cycle) r f resistance 91 k w : 5-v 68 k w : 5-v 91 k w : 5-v 91 k w : 5-v operation; operation; operation; operation; 75 k w : 3-v 56 k w : (3-v 75 k w : 3-v 75 k w : 3-v operation operation) operation operation 418 hd66712
lcd-ii lcd-ii/e20 lcd-ii/f8 lcd-ii/f12 item (hd44780u) (hd66702) (hd66710) hd66712 liquid crystal voltage none none 2? times step- 2? times step- booster circuit up circuit up circuit extension driver control independent independent used in common independent signal control signal control signal with a driver control signal output pin reset function power on power on power on power on automatic automatic automatic automatic reset reset reset reset or reset input instructions lcd-ii fully compatible upper upper compatible (hd44780) with the lcd-ii compatible with with the lcd-ii the lcd-ii number of displayed 1 or 2 1 or 2 1, 2, or 4 1, 2, or 4 lines low power mode none none available available horizontal scroll character unit character unit dot unit dot unit bus interface 4 bits/8 bits 4 bits/8 bits 4 bits/8 bits serial; 4 bits/8 bits cpu bus timing 2 mhz: 5-v 1 mhz 2 mhz: 5-v 2 mhz: 5-v operation; operation; operation; 1 mhz: 3-v 1 mhz: 3-v 1 mhz: 3-v operation operation operation package qfp-1420-80 lqfp-2020?44 qfp-1420-100 qfp-1420-128 80-pin bare chip 144-pin bare chip tqfp-1414-100 tcp-128 100-pin bare chip 128-pin bare chip hd66712 419
hd66712 block diagram 420 hd66712 com0? com33 v1 v2 v3 v4 v5 rs/cs * r/sclk rw/sid db4?b7 db3?b0 v cc gnd seg1? seg60 osc1 osc2 8 7 8 8 7 7 8 7 7 8 8 5/6 5 vci c1 c2 v5out2 8 3 v5out3 ext 34-bit shift register common signal driver timing generator display data ram (dd ram) 80 8 bits address counter instruction decoder cpg instruction register (i r) reset circuit acl 60-bit shift register 60-bit latch circuit segment signal driver lcd drive voltage selector cursor and bling controller character generator rom (cgrom) 9,600 bytes character generator ram (cgram) 64 bytes segment ram (sgram) 16 bytes parallel/serial converter and smooth scroll circuit booster busy flag data register (dr) input/ output buffer system interface serial 4 bits 8 bits cl1 cl2 m reset * db0esod d
hd66712 pin arrangement hd66712 421 seg17 seg16 seg15 seg14 seg13 seg12 seg11 seg10 seg9 seg8 seg7 seg6 seg5 seg4 seg3 seg2 seg1 com0 com1 com2 com3 com4 com5 com6 com7 com8 com17 com18 com19 com20 com21 com22 com23 com24 v1 v2 v3 v4 seg43 seg42 seg41 seg40 seg39 seg38 seg37 seg36 seg35 seg34 seg33 seg32 seg31 seg30 seg29 seg28 seg27 seg26 seg25 seg24 seg23 seg22 seg21 seg20 seg19 seg18 cl2 d m reset * im ext test gnd rs/cs * rw/sid e/sclk db0/sod db1 db2 db3 db4 db5 db6 db7 vci c2 c1 gnd v5out2 v5out3 v5 seg44 seg45 seg46 seg47 seg48 seg49 seg50 seg51 seg52 seg53 seg54 seg55 seg56 seg57 seg58 seg59 seg60 com9 com10 com11 com12 com13 com14 com15 com16 com25 com26 com27 com28 com29 com30 com31 com32 com33 v cc osc2 osc1 cl1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 lcd-ii/f12 (top view) 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103
tcp dimensions 422 hd66712 0.24-mm pitch com33 com32 com25 com16 com9 seg60 seg1 com0 com1 com8 com17 com24 lcd driver output side i/o/power supply side 0.65-mm pitch nc v cc osc2 osc1 cl1 cl2 d m reset * im ext test gnd rs/cs * rw/sid e/sclk db0/sod db1 db2 db3 db4 db5 db6 db7 vci c2 c1 gnd v5out2 v5out3 v5 v4 v3 v2 v1 nc
hd66712 pad arrangement hd66712 423 seg17 seg16 seg15 seg14 seg13 seg12 seg11 seg10 seg9 seg8 seg7 seg6 seg5 seg4 seg3 seg2 seg1 com0 com1 com2 com3 com4 com5 com6 com7 com8 com17 com18 com19 com20 com21 com22 com23 com24 v1 v2 v3 v4 seg43 seg42 seg41 seg40 seg39 seg38 seg37 seg36 seg35 seg34 seg33 seg32 seg31 seg30 seg29 seg28 seg27 seg26 seg25 seg24 seg23 seg22 seg21 seg20 seg19 seg18 cl2 d m reset * im ext test gnd rs/cs * rw/sid e/sclk db0/sod db1 db2 db3 db4 db5 db6 db7 vci c2 c1 gnd v5out2 v5out3 v5 seg44 seg45 seg46 seg47 seg48 seg49 seg50 seg51 seg52 seg53 seg54 seg55 seg56 seg57 seg58 seg59 seg60 com9 com10 com11 com12 com13 com14 com15 com16 com25 com26 com27 com28 com29 com30 com31 com32 com33 v cc osc2 osc1 cl1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 lcd-ii/f12 (top view) 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103
pin functions table 1 pin functional description number device signal of pins i/o interfaced with function im 1 i selects interface mode with the mpu; low: serial mode high: 4-bit/8-bit bus mode (bus width is specified by instruction.) rs/cs * 1 i mpu selects registers during bus mode: low: instruction register (write); busy flag, address counter (read) high: data register (write/read) acts as chip-select during serial mode: low: select (access enable) high: not selected (access disable) rw/sid 1 i mpu selects read/write during bus mode; low: write high: read inputs serial data during serial mode. e/sclk 1 i mpu starts data read/write during bus mode; inputs (receives) serial clock during serial mode. db 4 to 4 i/o mpu four high-order bidirectional tristate data bus pins. used db 7 for data transfer between the mpu and the hd66712. db 7 can be used as a busy flag. open these pins during serial mode since these signals are not used. db 1 to 3 i/o mpu three low order bidirectional tristate data bus pins. db 3 used for data transfer between the mpu and the hd66712. open these pins during 4-bit operation or serial mode since they are not used. db0/ 1 i/o mpu the lowest bidirectional data bit (db0) during 8-bit bus sod /o mode. open these pins during 4-bit mode since they are not used. outputs (transfers) serial data during serial mode. open this pin if reading (transfer) is not performed. com 0 to 34 o lcd common signals; those that are not used become non- com 33 selected waveforms. at 1/17 duty rate, com 1 to com 16 are used for character display, com 0 and com 17 for icon display, and com 18 to com 33 become non-selected waveforms. at 1/33 duty rate, com 1 to com 32 are used for character display, and com 0 and com 33 for icon display. because two com signals output the same level simultaneously, apply them according to the wiring pattern of the display device. seg 1 to 60 o lcd segment output signals seg 60 424 hd66712
table 1 pin functional description (cont) number device signal of pins i/o interfaced with function cl1 1 o extension driver when ext = high, outputs the extension driver latch pulse. cl2 1 o extension driver when ext = high, outputs the extension driver shift clock. d 1 o extension driver when ext = high, outputs extension driver data; data from the 61st dot on is output. m 1 o extension driver when ext = high, outputs the extension driver ac signal. ext 1 i when ext = high, outputs the extension driver control signal. when ext = low, the signal becomes tristate and can suppress consumption current. v 1 to v 5 5 power supply power supply for lcd drive v cc ? 5 = 13 v (max) v cc /gnd 2 power supply v cc : +2.7 v to +5.5 v, gnd: 0 v osc 1 /osc 2 2 oscillation when crystal oscillation is performed, an external resistor resistor must be connected. when the pin input is an clock external clock, it must be input to osc 1. vci 1 i inputs voltage to the booster to generate the liquid crystal display drive voltage. vci is reference voltage and power supply for the booster. vci = 2.0 v to 5.0 v vci v 5 out 2 1ov 5 pin/ voltage input to the vci pin is boosted twice and output. booster when the voltage is boosted three times, the same capacitance capacitance as that of c1?2 should be connected here. v 5 out 3 1ov 5 pin voltage input to the vci pin is boosted three times and output. c1/c2 2 booster external capacitance should be connected here when capacitance using the booster. reset * 1 i reset pin. initialized to ?ow. test 1 i test pin. should be wired to ground. hd66712 425
426 hd66712 function description system interface the hd66712 has three types of system interfaces: synchronized serial, 4-bit bus, and 8-bit bus. the serial interface is selected by the im-pin, and the 4/8-bit bus interface is selected by the dl bit in the instruction register. the hd66712 has two 8-bit registers: an instruc- tion register (ir) and a data register (dr). the ir stores instruction codes, such as display clear and cursor shift, and address information for the display data ram (dd ram), the character generator ram (cg ram), and the segment ram (segram). the mpu can only write to ir, and cannot be read from. the dr temporarily stores data to be written into dd ram, cg ram, or segram. data written into the dr from the mpu is automatically written into dd ram, cg ram, or segram by an internal operation. the dr is also used for data storage when reading data from dd ram, cg ram, or segram. when address information is written into the ir, data is read and then stored into the dr from dd ram or cg ram by an internal operation. data transfer between the mpu is then completed when the mpu reads the dr. after the read, data in dd ram, cg ram, or segram at the next address is sent to the dr for the next read from the mpu. these two registers can be selected by the registor selector (rs) signal in the 4/8 bit bus interface, and by the rs bit in start byte data in synchronized serial interface (table 2). busy flag (bf) when the busy flag is 1, the hd66712 is in the internal operation mode, and the next instruction will not be accepted. when rs = 0 and r/w = 1 (table 2), the busy flag is output from db 7 . the next instruction must be written after ensuring that the busy flag is 0. address counter (ac) the address counter (ac) assigns addresses to dd ram, cg ram, or segram. when an address of an instruction is written into the ir, the address information is sent from the ir to the ac. selec- tion of dd ram, cg ram, and segram is also determined concurrently by the instruction. after writing into (reading from) dd ram, cg ram, or segram, the ac is automatically incre- mented by 1 (decremented by 1). the ac contents are then output to db 0 to db 6 when rs = 0 and r/ w = 1 (table 2). table 2 resistor selection rs r/ w operation 0 0 ir write as an internal operation (display clear, etc.) 0 1 read busy flag (db 7 ) and address counter (db 0 to db 6 ) 1 0 dr write as an internal operation (dr to dd ram, cg ram, or segram) 1 1 dr read as an internal operation (dd ram, cg ram, or segram to dr)
hd66712 427 display data ram (dd ram) display data ram (dd ram) stores display data represented in 8-bit character codes. its capacity is 80 8 bits, or 80 characters. the area in display data ram (dd ram) that is not used for display can be used as general data ram. the dd ram address (a dd ) is set in the address counter (ac) as a hexadecimal number, as shown in figure 1. the relationship between dd ram addresses and positions on the liquid crystal display is described and shown on the following pages for a variety of cases. figure 1 dd ram address ac6 ac5 ac4 ac3 ac2 ac1 ac0 ac msb lsb 1001110 example: dd ram address 4e
428 hd66712 1-line display (n = 0, and nw = 0) case 1: when there are fewer than 80 dis- play characters, the display begins at the beginning of dd ram. for example, when 24 5-dot font-width characters are displayed using one hd66712, the display is generated as shown in figure 2. when a display shift is performed, the dd ram addresses shift as well as shown in the figure. when 20 6-dot font-width characters are displayed using one hd66712, the display is generated as shown in figure 3. note that com9 to com16 begins at address (0a)h in this case 20 characters are displayed. when a display shift is performed, the dd ram addresses shift as well as shown in the figure. case 2: figure 4 shows the case where the ext pin is fixed high and the hd66712 and the 40-output extension driver are used to display 24 6-dot font-width characters. in this case, com9 to com16 begins at (0a)h. when a display shift is performed, the dd ram addresses shift as well as shown in the figure. figure 2 1-line by 24-character display (5-dot font width) figure 3 1-line by 20-character display (6-dot font width) com1 to 8 com9 to 16 com1 to 8 com9 to 16 (left shift display) com1 to 8 com9 to 16 (right shift display) display position ddram address 00 01 02 03 04 06 05 12345678 07 com1 to 8 0c 0d 0e 0f 10 12 11 13 14 15 16 17 18 19 20 13 01 02 03 04 05 07 06 12345678 08 0d 0e 0f 10 11 13 12 13 14 15 16 17 18 19 20 14 4f 00 01 02 03 05 04 06 0b 0c 0d 0e 0f 11 10 12 9 08 9 09 07 10 09 10 0a 08 11 0a 11 0b 09 0b 0c 0a 12 12 21 14 21 15 13 22 15 22 16 14 23 16 23 17 15 24 17 24 18 16 com1 to 8 com9 to 16 com1 to 8 com9 to 16 (left shift display) com1 to 8 com9 to 16 (right shift display) display position ddram address 00 01 02 03 04 06 05 12345678 07 com1 to 8 0a 0b 0c 0d 0e 10 0f 11 12 13 14 15 16 17 18 11 01 02 03 04 05 07 06 12345678 08 0b 0c 0d 0e 0f 11 10 11 12 13 14 15 16 17 18 12 4f 00 01 02 03 05 04 06 09 0a 0b 0c 0d 0f 0e 10 9 08 9 09 07 10 09 10 0a 08 19 12 19 13 11 20 20 14 12 13
figure 4 1-line by 24-character display (6-dot font width) hd66712 429 01 02 03 04 06 05 07 0b 0c 0d 0e 0f 15 16 com1 to 8 com9 to 16 (left shift display) 1 2 3 4 5 6 7 11 12 13 14 15 21 22 23 00 01 02 03 04 05 09 0a 0b 0c 0d 13 14 15 com1 to 8 com9 to 16 (right shift display) 4f 17 00 01 02 03 04 06 05 0a 0b 0c 0d 0e 14 15 16 com1 to 8 com9 to 16 1 2 3 4 5 6 7 11 12 13 14 15 21 22 23 lcd-ii/f12 seg1 to seg60 lcd-ii/f12 seg1 to seg60 extension driver seg1 to seg24 display position ddram address 08 8 06 07 8 09 9 07 08 9 0a 10 08 09 10 10 16 0e 0f 16 11 17 0f 10 17 12 18 10 11 18 13 19 11 12 19 14 20 12 13 20 24 18 17 24 16
430 hd66712 2-line display (n = 1, and nw = 0) case 1: the first line is displayed from com1 to com16, and the second line is displayed from com17 to com32. note that the last address of the first line and the first address of the second line are not consecutive. figure 5 shows an example where a 5-dot font-width 24 2-line display is performed using one hd66712. here, com9 to com16 begins at (0c)h, and com25 to com32 at (4c)h. when a display shift is performed, the dd ram addresses shift as shown. figure 6 shows an example where a 6-dot font-width 20 2-line display is performed using one hd66712. com9 to com16 begins at (0a)h, and com25 to com32 at (4a)h. figure 5 2-line by 24-character display (5-dot font width) figure 6 2-line by 20-character display (6-dot font width) com1 to com8 com9 to com16 display position 00 01 02 03 04 06 05 12345678 07 0c 0d 0e 0f 10 12 11 13 14 15 16 17 18 19 20 13 9 08 10 09 11 0a 0b 12 21 14 22 15 23 16 24 17 com1 to com8 com9 to com16 com1 to com8 com9 to com16 com1 01 02 03 04 05 07 06 12345678 08 0d 0e 0f 10 11 13 12 13 14 15 16 17 18 19 20 14 27 00 01 02 03 05 04 06 0b 0c 0d 0e 0f 11 10 12 9 09 07 10 0a 08 11 0b 09 0c 0a 12 21 15 13 22 16 14 23 17 15 24 18 16 com17 to com24 com25 to com32 ddram address 40 41 42 43 44 46 45 47 4c 4d 4e 4f 50 52 51 53 48 49 4a 4b 54 55 56 57 com17 to com24 com25 to com32 com1 41 42 43 44 45 47 46 48 4d 4e 4f 50 51 53 52 54 49 4a 4b 4c 55 56 57 58 com17 to com24 com25 to com32 67 40 41 42 43 45 44 46 4b 4c 4d 4e 4f 51 50 52 47 48 49 4a 53 54 55 56 (left shift display) (right shift display) com1 to com8 com9 to com16 display position 00 01 02 03 04 06 05 12345678 07 0a 0b 0c 0d 0e 11 10 11 12 13 14 15 16 17 18 12 9 08 10 09 19 13 20 com17 to com24 com25 to com32 ddram address 40 41 42 43 44 46 45 47 4a 4b 4c 4d 4e 50 4f 51 48 49 52 53 0f
hd66712 431 case 2: figure 7 shows the case where the ext pin is fixed high and the hd66712 and the 40-output extension driver are used to extend the number of display characters to 32 5-dot font-width characters. in this case, com9 to com16 begins at (0c)h, and com25 to com32 at (4c)h. when a display shift is performed, the dd ram addresses shift as shown. figure 7 2-line by 32 character display (5-dot font width) com1 to com8 00 01 02 03 04 06 05 12345678 07 0c 0d 0e 0f 10 12 11 13 14 15 16 17 18 19 20 13 9 08 10 09 11 0a 0b 12 21 14 22 15 23 16 24 17 com1 to com8 com1 to com8 com1 01 02 03 04 05 07 06 12345678 08 0d 0e 0f 10 11 13 12 13 14 15 16 17 18 19 20 14 27 00 01 02 03 05 04 06 0b 0c 0d 0e 0f 11 10 12 9 09 07 10 0a 08 11 0b 09 0c 0a 12 21 15 13 22 16 14 23 17 15 24 18 16 com17 to com24 40 41 42 43 44 46 45 47 4c 4d 4e 4f 50 52 51 53 48 49 4a 4b 54 55 56 57 com17 to com24 com1 41 42 43 44 45 47 46 48 4d 4e 4f 50 51 53 52 54 49 4a 4b 4c 55 56 57 58 com17 to com24 67 40 41 42 43 45 44 46 4b 4c 4d 4e 4f 51 50 52 47 48 49 4a 53 54 55 56 com9 to com16 display position 18 19 1a 1b 1c 1e 1d 25 26 27 28 29 30 31 32 1f com9 to com16 com9 to com16 25 26 27 28 29 30 31 32 17 18 19 1a 1b 1d 1c 1e com25 to com32 ddram address 58 59 5a 5b 5c 5e 5d 5f com25 to com32 59 5a 5b 5c 5d 5f 5e 60 com25 to com32 57 58 59 5a 5b 5d 5c 5e (left shift display) (right shift display) 19 1a 1b 1c 1d 1f 1e 20 lcd-ii/f12 seg1?eg60 lcd-ii/f12 seg1?eg60 extension driver seg1?eg40
432 hd66712 4-line display (nw = 1) case 1: the first line is displayed from com1 to com8, the second line is dis- played from com9 to com16, the third line is displayed from com17 to com24, and the fourth line is displayed from com25 to com32. note that the dd ram addresses of each line are not consecutive. figure 8 shows an example where a 12 4-line display is per- formed using one hd66712. when a display shift is performed, the dd ram addresses shift as shown. figure 8 4-line display (left shift display) 01 02 03 04 05 06 21 22 23 24 25 26 com1 to 8 com17 to 24 com9 to 16 com25 to 32 1234567 41 42 43 44 45 46 61 62 63 64 65 66 07 27 67 8 28 48 47 08 68 (right shift display) 1234567 13 33 53 00 01 02 03 04 05 06 20 21 22 23 24 25 26 40 41 42 43 44 45 46 60 61 62 63 64 65 66 73 8 00 01 02 03 04 05 06 20 21 22 23 24 25 26 com1 to 8 com17 to 24 com9 to 16 com25 to 32 1234567 40 41 42 43 44 45 46 60 61 62 63 64 65 66 display position ddram address 07 27 8 47 67 08 28 9 48 68 09 29 10 49 69 0a 2a 11 4a 6a 0b 2b 12 4b 6b 9 29 49 09 69 10 2a 4a 0a 6a 11 2b 4b 0b 6b 12 2c 4c 0c 6c 07 27 47 67 9 08 28 48 68 10 09 29 49 69 11 0a 2a 4a 6a 12
hd66712 433 case 2: figure 9 shows the case where the ext pin is fixed high and the hd66712 and the 40-output extension driver are used to extend the number of display characters. when a display shift is performed, the dd ram addresses shift as shown. figure 9 4-line by 20-character display 1 2 3 4 5 6 7 8 9 101112 1314151617181920 4e 1 2 3 4 5 6 7 8 9 101112 1314151617181920 01 02 03 04 05 06 11 12 13 0a 0b 0c 0d 0e 0f 10 07 08 09 00 21 22 23 24 25 26 31 32 33 2a 2b 2c 2d 2e 2f 30 27 28 29 20 41 42 43 44 45 46 51 52 53 4a 4b 4c 4d 4f 50 47 48 49 40 61 62 63 64 65 66 71 72 73 6a 6b 6c 6d 6e 6f 70 67 68 69 60 00 01 02 03 04 05 06 11 12 0a 0b 0c 0d 0e 0f 10 07 08 09 13 20 21 22 23 24 25 26 31 32 2a 2b 2c 2d 2e 2f 30 27 28 29 33 40 41 42 43 44 45 46 51 52 4a 4b 4c 4d 4e 4f 50 47 48 49 53 60 61 62 63 64 65 66 71 72 6a 6b 6c 6d 6e 6f 70 67 68 69 73 (right shift display) (left shift display) 00 01 02 03 04 05 06 20 21 22 23 24 25 26 com1 to 8 com17 to 24 com9 to 16 com25 to 32 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 41 42 43 44 45 46 60 61 62 63 64 65 66 11 12 13 0a 0b 0c 0d 0e 0f 10 07 08 09 31 32 33 2a 2b 2c 2d 2e 2f 30 27 28 29 51 52 53 4a 4b 4c 4d 4e 4f 50 47 48 49 71 72 73 6a 6b 6c 6d 6e 6f 70 67 68 69 lcd-ii/f12 extension driver display position ddram address
434 hd66712 character generator rom (cg rom) the character generator rom generates 5 8 dot character patterns from 8-bit character codes (table 3 to 6). it can generate 240 5 8 dot character patterns. user-defined character patterns are also available using a mask-programmed rom (see ?odifying character patterns.? character generator ram (cg ram) the character generator ram allows the user to redefine the character patterns. in the case of 5 8 characters, up to eight may be redefined. write the character codes at the addresses shown as the left column of table 3 to 6 to show the character patterns stored in cg ram. see table 7 for the relationship between cg ram addresses and data and display patterns. segment ram (segram) the segment ram (segram) is used to enable control of segments such as an icon and a mark by the user program. for a 1-line display, segram is read from the com0 and the com17 output, and for 2- or 4-line displays, it is read from the com0 and the com33 output, to perform 60-segment display (80-segment display when using the extension driver). as shown in table 8, bits in segram corre- sponding to segments to be displayed are directly set by the mpu, regardless of the contents of ddram and cgram. segram data is stored in eight bits. the lower six bits control the display of each segment, and the upper two bits control segment blinking. timing generation circuit the timing generation circuit generates timing signals for the operation of internal circuits such as ddram, cgrom, cgram, and segram. ram read timing for display and internal opera- tion timing by mpu access are generated sepa- rately to avoid interfering with each other. therefore, when writing data to dd ram, for example, there will be no undesirable interfer- ences, such as flickering, in areas other than the display area. liquid crystal display driver circuit the liquid crystal display driver circuit consists of 34 common signal drivers and 60 segment signal drivers. when the character font and number of lines are selected by a program, the required common signal drivers automatically output drive waveforms, while the other common signal drivers continue to output non-selection waveforms. character pattern data is sent serially through a 60- bit shift register and latched when all needed data has arrived. the latched data then enables the driver to generate drive waveform outputs. sending serial data always starts at the display data character pattern corresponding to the last address of the display data ram (dd ram). since serial data is latched when the display data character pattern corresponding to the starting address enters the internal shift register, the hd66712 drives from the head display. cursor/blink control circuit the cursor/blink (or white-black inversion) control is used to produce a cursor or a flashing area on the display at a position corresponding to the location in stored in the address counter (ac). for example (figure 10), when the address counter is (08)h, a cursor is displayed at a position corre- sponding to ddram address (08)h. scroll control circuit the scroll control circuit is used to perform a smooth-scroll in the unit of dot. when the number of characters to be displayed is greater than that possible at one time on the liquid crystal module, this horizontal smooth scroll can be used to display all characters.
figure 10 cursor/blink display example hd66712 435 ac = (08)16 00 1 cursor position display position ddram address 01 2 02 3 03 4 04 5 05 6 06 7 07 8 08 9 09 10 0a 11
table 3 relationship between character codes and character patterns (rom code: a00) 436 hd66712 xxxx0000 xxxx0001 xxxx0010 xxxx0011 xxxx0100 xxxx0101 xxxx0110 xxxx0111 xxxx1000 xxxx1001 xxxx1010 xxxx1011 xxxx1100 xxxx1101 xxxx1110 xxxx1111 0000 0010 0011 0100 0101 0110 0111 1010 1011 1100 1101 1110 1111 upper bits lower bits cg ram (1) 0001 1000 1001 cg ram (2) cg ram (3) cg ram (4) cg ram (5) cg ram (6) cg ram (7) cg ram (8) cg ram (1) cg ram (2) cg ram (3) cg ram (4) cg ram (5) cg ram (6) cg ram (7) cg ram (8)
table 4 relationship between character codes and character pattern (rom code: a01) hd66712 437 xxxx0000 xxxx0001 xxxx0010 xxxx0011 xxxx0100 xxxx0101 xxxx0110 xxxx0111 xxxx1000 xxxx1001 xxxx1010 xxxx1011 xxxx1100 xxxx1101 xxxx1110 xxxx1111 0000 0010 0011 0100 0101 0110 0111 1010 1011 1100 1101 1110 1111 upper bits lower bits cg ram (1) 0001 1000 1001 cg ram (2) cg ram (3) cg ram (4) cg ram (5) cg ram (6) cg ram (7) cg ram (8) cg ram (1) cg ram (2) cg ram (3) cg ram (4) cg ram (5) cg ram (6) cg ram (7) cg ram (8)
table 5 relationship between character codes and character patterns (rom code: a02) note: the character codes of the characters enclosed in the bold frame are the same as those of the first edition of the iso8859 and the character code compatible. 438 hd66712 xxxx0000 xxxx0001 xxxx0010 xxxx0011 xxxx0100 xxxx0101 xxxx0110 xxxx0111 xxxx1000 xxxx1001 xxxx1010 xxxx1011 xxxx1100 xxxx1101 xxxx1110 xxxx1111 0000 0010 0011 0100 0101 0110 0111 1010 1011 1100 1101 1110 1111 upper bits lower bits cg ram (1) 0001 1000 1001 cg ram (2) cg ram (3) cg ram (4) cg ram (5) cg ram (6) cg ram (7) cg ram (8) cg ram (1) cg ram (2) cg ram (3) cg ram (4) cg ram (5) cg ram (6) cg ram (7) cg ram (8)
table 6 relationship between character codes and character pattern (rom code: a03) hd66712 439 xxxx0000 xxxx0001 xxxx0010 xxxx0011 xxxx0100 xxxx0101 xxxx0110 xxxx0111 xxxx1000 xxxx1001 xxxx1010 xxxx1011 xxxx1100 xxxx1101 xxxx1110 xxxx1111 0000 0010 0011 0100 0101 0110 0111 1010 1011 1100 1101 1110 1111 upper bits lower bits cg ram (1) 0001 1000 1001 cg ram (2) cg ram (3) cg ram (4) cg ram (5) cg ram (6) cg ram (7) cg ram (8) cg ram (1) cg ram (2) cg ram (3) cg ram (4) cg ram (5) cg ram (6) cg ram (7) cg ram (8)
table 7 example of relationships between character code (ddram) and character pattern(cgram data) 440 hd66712 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 character code (ddram data) cgram data lsb msb a 2 a 1 a 0 a 5 a 4 a 3 0 000 00 1 010 0 11 100 101 110 111 0 0 * 0 0 0 0 10001 10001 10001 01010 00100 00100 00100 00000 000 *** o 4 o 3 o 2 o 1 o 0 o 5 o 6 o 7 cgram address 1 1 1 00000 ** 1 000 00 1 0 1 0 011 100 101 11 0 1 1 * 0 0 0 0 10001 10001 10001 0 1 0 1 0 00100 00100 00 1 00 111 * character pattern (1) character pattern (8) d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 lsb msb a 2 a 1 a 0 a 5 a 4 a 3 o 4 o 3 o 2 o 1 o 0 o 5 o 6 o 7 0 000 001 010 011 100 101 110 111 0 0 * 0 0 0 0 10001 10001 10001 01010 00100 00100 00100 00000 000 ** 0 0 0 0 0 0 0 0 0 111 0000 1 000 00 1 010 0 11 100 101 110 1 1 * 0 0 0 0 10001 10001 10001 01010 00100 00100 00100 111 * 0 0 0 0 0 0 0 0 character pattern (1) character pattern (8) character code (ddram data) cgram address cgram data * a) when character pattern is 5 8 dots a) when character pattern is 6 8 dots
notes: 1. character code bits 0 to 2 correspond to cgram address bits 3 to 5 (3 bits: 8 types). 2. cgram address bits 0 to 2 designate the character pattern line position. the 8th line is the cursor position and its display is formed by a logical or with the cursor. 3. the character data is stored with the rightmost character element in bit 0, as shown in the figure above. characters of 5 dots in width (fw = 0) are stored in bits 0 to 4, and characters of 6 dots in width (fw = 1) are stored in bits 0 to 5. 4. when the upper four bits (bits 7 to 4) of the character code are 0, cgram is selected. bit 3 of the character code is invalid ( * ). therefore, for example, the character codes (00)h and (08)h correspond to the same cgram address. 5. a set bit in the cgram data corresponds to display selection, and 0 to non-selection. 6. when the be bit of the function set register is 1, pattern blinking control of the lower six bits is controlled using the upper two bits (bits 7 and 6) in cgram. when bit 7 is 1, of the lower six bits, only those which are set are blinked on the display. when bit 6 is 1, a bit 4 pattern can be blinked as for a 5-dot font width, and a bit 5 pattern can be blinked as for a 6-dot font width. * indicates no effect. hd66712 441
table 8 relationship between segram addresses and display patterns notes: 1. data set to segram is output when com0 and com17 are selected, as for a 1-line display, and output when com0 and com33 are selected, as for a 2-line or a 4-line display. com0 and com17 for a 1-line display and com0 and com33 for a 2-line or a 4-line display are the same signals. 2. s1 to s96 are pin numbers of the segment output driver. s1 is positioned to the left of the display. when the lcd-ii/f12 is used by one chip, segments from s1 to s60 are displayed. an extension driver displays the segments after s61. 3. after s80 output at 5-dot font and s96 output at 6-dot font, s1 output is repeated again. 4. as for a 5-dot font width, lower five bits (d4 to d0) are display on.off information of each segment. for a 6-dot character width, the lower six bits (d5 to d0) are the display information for each segment. 5. when the be bit of the function set register is 1, pattern blinking of the lower six bits is controlled using the upper two bits (bits 7 and 6) in segram. when bit 7 is 1, only a bit set to ??of the lower six bits is blinked on the display. when bit 6 is 1, only a bit 4 pattern can be blinked as for a 5-dot font width, and only a bit 5 pattern can be blinked as for 6-dot font width. 6. bit 5 (d5) is invalid for a 5-dot font width. 7. set bits in the segram data correspond to display selection, and zeros to non-selection. 442 hd66712 b1 b0 * s1 s2 s3 s4 s5 b1 b0 s1 s2 s3 s4 s5 s6 * s6 s7 s8 s9 s10 b1 b0 * s11 s12 s13 s14 s15 b1 b0 * s16 s17 s18 s19 s20 b1 b0 * s21 s22 s23 s24 s25 b1 b0 * s26 s27 s28 s29 s30 b1 b0 * s31 s32 s33 s34 s35 b1 b0 * * * * * * * * * s36 s41 s46 s51 s56 s61 s66 s71 s76 s37 s42 s47 s52 s7 s62 s67 s72 s77 s38 s43 s48 s53 s58 s63 s68 s73 s78 s39 s44 s49 s54 s59 s64 s69 s74 s79 s40 s45 s50 s55 s60 s65 s70 s75 s80 b1 b1 b1 b1 b1 b1 b1 b1 b1 b0 b0 b0 b0 b0 b0 b0 b0 b0 blinking control pattern on/off s7 s8 s9 s10 s11 s12 b1 b0 s13 s14 s15 s16 s17 s18 b1 b0 s19 s20 s21 s22 s23 s24 b1 b0 s25 s26 s27 s28 s29 s30 b1 b0 s31 s32 s33 s34 s35 s36 b1 b0 s37 s38 s39 s40 s41 s42 b1 b0 s43 s49 s55 s61 s67 s73 s79 s85 s91 s44 s50 s56 s62 s68 s74 s80 s86 s92 s45 s51 s57 s63 s69 s75 s81 s87 s93 s46 s52 s58 s64 s70 s76 s82 s88 s94 s47 s53 s59 s65 s71 s77 s83 s89 s95 s48 s54 s60 s66 s72 s78 s84 s90 s96 b1 b1 b1 b1 b1 b1 b1 b1 b1 b0 b0 b0 b0 b0 b0 b0 b0 b0 a 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 a 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 a 2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 segram address segram data blinking control pattern on/off a) 5-dot font width b) 6-dot font width a 3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
figure 11 correspondence between segram and segment display hd66712 443 seg56 seg57 seg58 seg59 seg60 seg61 seg62 seg63 seg64 seg65 seg1 seg2 seg3 seg4 seg5 seg6 seg7 seg8 seg9 seg10 seg56 seg57 seg58 seg59 seg60 seg11 seg12 seg55 seg61 seg62 seg63 seg64 seg65 seg66 displayed by lcd-ii/f12 i) 5-dot font width (fw = 0) ii) 6-dot font width (fw = 1) s1 s2 s3 s4 s5 s6 s7 s8 s9 s10 s56 s57 s58 s59 s60 s61 s62 s63 s64 s65 s1 s2 s3 s4 s7 s8 s9 s10 s11 s55 s56 s57 s58 s59 s6 s12 s61 s62 s63 s64 s60 s65 s66 s5 seg1 seg2 seg3 seg4 seg5 seg6 seg7 seg8 seg9 seg10 displayed by extension driver displayed by lcd-ii/f12 displayed by extension driver
444 hd66712 modifying character patterns character pattern development procedure the following operations correspond to the numbers listed in figure 12: 1. determine the correspondence between char- acter codes and character patterns. 2. create a listing indicating the correspondence between eprom addresses and data. 3. program the character patterns into an eprom. 4. send the eprom to hitachi. 5. computer processing of the eprom is per- formed at hitachi to create a character pattern listing, which is sent to the user. 6. if there are no problems within the character pattern listing, a trial lsi is created at hitachi and samples are sent to the user for evaluation. when it is confirmed by the user that the character patterns are correctly written, mass production of the lsi will proceed at hitachi.
figure 12 character pattern development procedure hd66712 445 determine character patterns create eprom address data listing write eprom eprom ? hitachi computer processing create character pattern listing evaluate character patterns ok? art work sample evaluation ok? masking trial sample no yes no yes m/t 1 3 2 4 5 6 user hitachi mass production start
446 hd66712 programming character patterns this section explains the correspondence between addresses and data used to program character patterns in eprom. programming to eprom the hd66712 character generator rom can generate 240 5 8 dot character patterns. table 9 shows correspondence between the eprom address data and the character pattern. handling unused character patterns 1. eprom data outside the character pattern area: this is ignored by the character gener- ator rom for display operation so any data is acceptable. 2. eprom data in cg ram area: always fill with zeros. 3. treatment of unused user patterns in the hd66712 eprom: according to the user application, these are handled in either of two ways: a when unused character patterns are not programmed: if an unused character code is written into dd ram, all its dots are lit, because the eprom is filled with 1s after it is erased. b when unused character patterns are programmed as 0s: nothing is displayed even if unused character codes are written into dd ram. (this is equivalent to a space.) table 9 example of correspondence between eprom address data and character pattern (5 8 dots) notes: 1. eprom addresses a 11 to a 4 correspond to a character code. 2. eprom addresses a 2 to a 0 specify the line position of the character pattern. eprom address a3 should be set to ?. 3. eprom data o 4 to o 0 correspond to character pattern data. 4. areas which are lit (indicated by shading) are stored as ?,?and unlit areas as ?. 5. the eighth line is also stored in the cgrom, and should also be programmed. if the eighth line is used for a cursor, this data should all be set to zero. 6. eprom data bits 0 7 to 0 5 are invalid. 0 should be written in all bits. a 10 a 9 a 8 a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0 000 00 1 010 011 100 101 11 0 111 1 000 1 o 4 o 3 o 2 o 1 o 0 1 0001 1 0001 01 010 0 0100 0 0100 00 1 00 0 0000 character code line position eprom address data lsb msb 0 0 0 0 0 0 0 0 ? a 11 0 1011001
hd66712 447 reset function initializing by internal reset circuit an internal reset circuit automatically initializes the hd66712 when the power is turned on. the following instructions are executed during the initialization. the busy flag (bf) is kept in the busy state until the initialization ends (bf = 1). the busy state lasts for 15 ms after v cc rises to 4.5 v or 40 ms after the v cc rises to 2.7 v. 1. display clear: (20)h to all ddram 2. set functions: dl = 1: 8-bit interface data n = 1: 2-line display re = 0: extension register write disable be = 0: cgram/segram blink off lp = 0: not in low power mode 3. control display on/off: d = 0: display off c = 0: cursor off b = 0: blinking off 4. set entry mode: i/d = 1: increment by 1 s = 0: no shift 5. set extension function: fw = 0: 5-dot character width b/w = 0: normal cursor (eighth line) nw = 0: 1- or 2-line display (depending on n) 6. enable scroll: hse = 0000: scroll unable 7. set scroll amount: hds = 000000: not scroll note: if the electrical characteristics conditions listed under the table power supply condi- tions using internal reset circuit are not met, the internal reset circuit will not operate normally and will fail to initialize the hd66712. initializing by hardware reset input the lcd-ii/f12 also has a reset input pin: reset*. if this pin is made low during operation, an internal reset and initialization is performed. this pin is ignored, however, during the internal reset period at power-on.
448 hd66712 interfacing to the mpu the hd66712 can send data in either two 4-bit operations or one 8-bit operation, thus allowing interfacing with 4- or 8-bit mpus. for 4-bit interface data, only four bus lines (db 4 to db 7 ) are used for transfer. bus lines db 0 to db 3 are disabled. the data transfer between the hd66712 and the mpu is completed after the 4- bit data has been transferred twice. as for the order of data transfer, the four high order bits (for 8-bit operation, db 4 to db 7 ) are transferred before the four low order bits (for 8-bit operation, db 0 to db 3 ). the busy flag must be checked (one instruction) after the 4-bit data has been transferred twice. two more 4-bit operations then transfer the busy flag and address counter data. for 8-bit interface data, all eight bus lines (db 0 to db 7 ) are used. when the im pin is low, the hd66712 uses a serial interface. see ?ransferring serial data. figure 13 4-bit transfer example rs r/ w e ir ir ir ir bf ac ac ac db db db db 7 6 5 4 instruction register (ir) write busy flag (bf) and address counter (ac) read data register (dr) read 7 6 5 4 ir ir ir ir 3 2 1 0 6 5 4 ac ac ac ac 3 2 1 0 dr dr dr dr 7 6 5 4 dr dr dr dr 3 2 1 0
hd66712 449 transferring serial data when the im pin (interface mode) is low, the hd66712 enters serial interface mode. a three-line clock-synchronous transfer method is used. the hd66712 receives serial input data (sid) and transmits serial output data (sod) by synchro- nizing with a transfer clock (sclk) sent from the master side. when the hd66712 interfaces with several chips, chip select pin (cs*) must be used. the transfer clock (sclk) input is activated by making chip select (cs*) low. in addition, the transfer counter of the lcd-ii/f12 can be reset and serial transfer synchronized by making chip select (cs*) high. here, since the data which was being sent at reset is cleared, restart the transfer from the first bit of this data. in the case of a minimum 1 to 1 transfer system with the lcd-ii/f12 used as a receiver only, an interface can be established by the transfer clock (sclk) and serial input data (sid). in this case, chip select (cs*) should be fixed to low. the transfer clock (sclk) is independent from operational clock (clk) of the lcd-ii/f12. how- ever, when several instructions are continuously transferred, the instruction execution time deter- mined by the operational clock (clk) (see con- tinuous transfer) must be considered since the lcd-ii/f12 does not have an internal transmit/ receive buffer. to begin with, transfer the start byte. by receiving five consecutive bits (synchronizing bit string) at the beginning of the start byte, the transfer counter of the lcd-ii/f12 is reset and serial transfer is synchronized. the 2 bits following the synchro- nizing bit string (5 bits) specify transfer direction (r/ w bit) and register select (rs bit). be sure to transfer 0 in the 8th bit. after receiving the start byte, instructions are received and the data/busy flag is transmitted. when the transfer direction and register select remain the same, data can be continuously trans- mitted or received. the transfer protocol is described in detail below. receiving (write) after receiving the start synchronization bits, the r/ w bit (= 0), and the rs bit with the start byte, an 8-bit instruction is received in 2 bytes: the lower 4 bits of the instruction are placed in the lsb of the first byte, and the higher 4 bits of the instruction are placed in the lsb of the second byte. be sure to transfer 0 in the following 4 bits of each byte. when instructions are continuously received with r/ w bit and rs bit unchanged, continuous transfer is possible (see ?ontinuous transfer?below).
figure 14 basic procedure for transferring serial data 450 hd66712 12345678910111213141516 123456789101112131415161718192021222324 11111r/ w rs0d0d1d2d30000d4d5d6d70000 starting byte instruction a) basic transfer serial data input (receive) cs * (input) sclk (input) sid (input) cs * (input) sclk (input) sid (input) sod (output) synchronizing bit string lower data upper data 1st byte 2nd byte b) basic transfer of serial data output (transmit) synchronizing bit string lower data upper data starting byte busy flag/data read 11111r/ w rs 000000000 d0 d1 d2 d3 d4 d5 d6 d7
hd66712 451 transmitting (read) after receiving the start synchronization bits, the r/ w bit (= 1), and the rs bit with the start byte, 8-bit read data is transmitted in the same way as receiving. when read data is continuously trans- mitted with r/ w bit and rs bit unchanged, con- tinuous transfer is possible (see ?ontinuous transfer?below). even at the time of the transmission (the data output), since the hd66712 monitors the start synchronization bit string (?1111? by the sid input, the hd66712 receives the r/w bit and rs bit after detecting the start synchronization. therefore, in the case of a continuous transfer, fix the sid input ?. continuous transfer when instructions are continuously received with the r/ w bit and rs bit unchanged, con- tinuous receive is possible without inserting a start byte between instructions. after receiving the last bit (the 8th bit in the 2nd byte) of an instruction, the system begins to execute it. to execute the next instruction, the instruction execution time of the lcd-ii/f12 must be considered. if the last bit (the 8th bit in the 2nd byte) of the next instruction is received during execution of the previous instruction, the instruction will be ignored. in addition, if the next unit of data is read before read execution of previous data is completed for busy flag/address counter/ram data, normal data is not sent. to transfer data normally, the busy flag must be checked. however, it is possible to transfer without reading the busy flag if wiring for transmission (sod pin) needs to be reduced or if the burden of polling on the cpu needs to be removed. in this case, insert a transfer wait so that the current instruction first completes execution during instruction transfer.
figure 15 procedure for continuous data transfer 452 hd66712 start byte instruction (1) 1st byte 2nd byte instruction (2) 1st byte 2nd byte start byte start byte instruction (1) 1st byte 2nd byte instruction (3) 1st byte 2nd byte instruction (2) 1st byte 2nd byte start byte busy read instruction (1) execution time instruction waiting time (not busy state) instruction (1) execution time instruction (2) execution time instruction (3) execution time wait wait wait wait start byte data read (1) data read (2) instruction (1) execution time instruction (2) execution time sclk (input) sid (input) sod (output) sclk (input) sid (input) sclk (input) sid (input) sod (output) i) continuous data write by boring processing ii) continuous data write by cpu wait insert iii) continuous data read by cpu wait insert
hd66712 453 instructions outline only the instruction register (ir) and the data register (dr) of the hd66712 can be controlled by the mpu. before starting internal operation of the hd66712, control information is temporarily stored in these registers to allow interfacing with various mpus, which operate at different speeds, or various peripheral control devices. the internal operation of the hd66712 is determined by signals sent from the mpu. these signals, which include register selection (rs), read/write (r/ w ), and the data bus (db 0 to db 7 ), make up the hd66712 instructions (table 12). there are four categories of instructions that: designate hd66712 functions, such as display format, data length, etc. set internal ram addresses perform data transfer with internal ram perform miscellaneous functions normally, instructions that perform data transfer with internal ram are used the most. however, auto-incrementation by 1 (or auto-decrementation by 1) of internal hd66712 ram addresses after each data write can lighten the program load of the mpu. since the display shift instruction (table 10) can perform concurrently with display data write, the user can minimize system development time with maximum programming efficiency. when an instruction is being executed for internal operation, no instruction other than the busy flag/ address read instruction can be executed. because the busy flag is set to 1 while an instruc- tion is being executed, check it to make sure it is 0 before sending another instruction from the mpu. note: be sure the hd66712 is not in the busy state (bf = 1) before sending an instruction from the mpu to the hd66712. if an instru- ction is sent without checking the busy flag, the time between the first instruction and next instruction will take much longer than the instruction time itself. refer to table 12 for the list of each instruction execution time.
454 hd66712 instruction description clear display clear display writes space code (20)h (character pattern for character code (20)h must be a blank pattern) into all dd ram addresses. it then sets dd ram address 0 into the address counter, and returns the display to its original status if it was shifted. in other words, the display disappears and the cursor or blinking goes to the left edge of the display (in the first line if 2 lines are displayed). it also sets i/d to 1 (increment mode) in entry mode. s of entry mode does not change. return home return home sets dd ram address 0 into the address counter, and returns the display to its original status if it was shifted. the dd ram contents do not change. the cursor or blinking goes to the left edge of the display (in the first line if 2 lines are displayed). in addition, flicker may occur in a moment at the time of this instruction issue. entry mode set i/d: increments (i/d = 1) or decrements (i/d = 0) the dd ram address by 1 when a character code is written into or read from dd ram. the cursor or blinking moves to the right when incremented by 1 and to the left when decremented by 1. the same applies to writing and reading of cg ram and seg ram. s: shifts the entire display either to the right (i/d = 0) or to the left (i/d = 1) when s is 1 during dd ram write. the display does not shift if s is 0. if s is 1, it will seem as if the cursor does not move but the display does. the display does not shift when reading from dd ram. also, writing into or reading out from cg ram and seg ram does not shift the display. in a low power mode (lp = 1), do not set s = 1 because the whole display does not normally shift. display on/off control when extension register enable bit (re) is 0, bits d, c, and b are accessed. d: the display is on when d is 1 and off when d is 0. when off, the display data remains in dd ram, but can be displayed instantly by setting d to 1. c: the cursor is displayed when c is 1 and not displayed when c is 0. even if the cursor dis- appears, the function of i/d or other specifications will not change during display data write. the cursor is displayed using 5 dots in the 8th line for 5 8 dot character font. b: the character indicated by the cursor blinks when b is 1. the blinking is displayed as switch- ing between all blank dots and displayed characters at a speed of 370-ms intervals when f cp or f osc is 270 khz. the cursor and blinking can be set to display simultaneously. (the blinking frequency changes according to f osc or the reciprocal of f cp . for example, when f cp is 300 khz, 370 270/300 = 333 ms.) extended function set when the extended register enable bit (re) is 1, fw, b/w, and nw bit shown below are accessed. once these registers are accessed, the set values are held even if the re bit is set to zero. fw: when fw is 1, each displayed character is controlled with a 6-dot width. the user font in cg ram is displayed with a 6-bit character width from bits 5 to 0. as for fonts stored in cg rom, no display area is assigned to the left most bit, and the font is displayed with a 5-bit character width. if the fw bit is changed, data in dd ram and cg ram seg ram is destroyed. therefore, set fw before data is written to ram. when font width is set to 6 dots, the frame frequency decreases to 5/6 compared to 5-dot time. see ?scillator circuit for details.
hd66712 455 b/w: when b/w is 1, the character at the cursor position is cyclically displayed with black-white inversion. at this time, bits c and b in display on/off control register are ?ont care.?when f cp or f osc is 270 khz, display is changed by switching every 370 ms. nw: when nw is 1, 4-line display is performed. at this time, bit n in the function set register is ?ont care. figure 16 example of display control i) cursor display example ii) blink display example white-black inverting display example iii) alternating display alternating display i) 5-dot character width ii) 6-dot character width a) cursor blink width control b) font width control
456 hd66712 cursor or display shift cursor or display shift shifts the cursor position or display to the right or left without writing or reading display data (table 10). this function is used to correct or search the display. in a 2-line display, the cursor moves to the second line when it passes the 40th digit of the first line. in a 4-line display, the cursor moves to the second line when it passes the 20th character of the line. note that, all line displays will shift at the same time. when the displayed data is shifted repeatedly each line moves only horizontally. the second line display does not shift into the first line position. when this instruction is executed, extended register enable bit (re) is reset. the address counter (ac) contents will not change if the only action performed is a display shift. in low power mode (lp = 1), whole-display shift cannot be normally performed. scroll enable when extended register enable bit (re) is 1, scroll enable bits can be set. this hse resister specifies scrolled line with the scroll quantity register. this register consists of 4 bits for each display line, so a specified line can be shifted by dot unit. when the bit 0 of hse is 1 in four line mode (nw = 1), the first line can be shifted, and the bit 1 is specified to shift the second line, the bit 2 is specified for the third line, and bit 3 is specified for the fourth line. when it shifts the first line in two line mode (n = 1, nw = 0), both the bit 0 and bit 1 should be set to 1. the bit 2 and bit 3 is specified for the second line. in 1 line mode (n = 0, nw = 0), the bit 0 and bit 1 should be specified. function set only when the extended register enable bit (re) is 1, the be and the lp bits shown below can be accessed. bits dl and n can be accessed regard- less of re. dl: sets the interface data length. data is sent or received in 8-bit lengths (db 7 to db 0 ) when dl is 1, and in 4-bit lengths (db 7 to db 4 ) when dl is 0. when 4-bit length is selected, data must be sent or received twice. n: when bit nw in the extended function set is 0, a 1- or a 2-line display is set. when n is 0, 1-line display is selected; when n is 1, 2-line display is selected. when nw is 1, a 4-line display is set. at this time, n is ?ont care. note: after changing the n or nw or lp bit, please issue the return home or clear display instruction to cancel to shift display. re: when bit re is 1, bit be in the extended function set register, the segram address set register, and the function set register can be accessed. when bit re is 0, the registers described above cannot be accessed, and the data in these registers is held. to maintain compatibility with the hd44780, the re bit should be fixed to 0. table 10 shift function s/c r/l 0 0 shifts the cursor position to the left. (ac is decremented by one.) 0 1 shifts the cursor position to the right. (ac is incremented by one.) 1 0 shifts the entire display to the left. the cursor follows the display shift. 1 1 shifts the entire display to the right. the cursor follows the display shift.
hd66712 457 be: when the re bit is 1, this bit can be rewritten. when this bit is 1, the user font in cgram and the segment in segram can be blinked according to the upper two bits of cgram and segram. lp: when bit re is 1, this bit can be rewritten. when lp is set to 1 and the ext pin is low (with- out an extended driver), the hd66712 operates in low power mode. in 1-line display mode, the hd66712 operates on a 4-division clock, and in a 2-line or a 4-line display mode, the hd66712 operates on a 2-division clock. according to these operations, instruction execution takes four times or twice as long. note that in low power mode, display shift cannot be performed. the frame frequency is reduced to 5/6 that of normal opera- tion. see ?scillator circuit?for details. note: perform the dl, n, nw, and fw fucntions at the head of the program before executing any instructions (except for the read busy flag and address instruction). from this point, if bits n, nw, or fw are changed after other instructions are executed, ram contents may be broken. set cg ram address a cg ram address can be set while the re bit is cleared to 0. set cg ram address into the address counter displayed by binary aaaaaa. after this address set, data is written to or read from the mpu for cg ram. set segram address only when the extended register enable (re) bit is 1, hs2 to hs0 and the segram address can be set. the segram address in the binary form aaaa is set to the address counter. after this address set, segram can be written to or read from by the mpu. set dd ram address a dd ram address can be set while the re bit is cleared to 0. set dd ram address sets the dd ram address binary aaaaaaa into the address counter. after this address set, data is written to or read from the mpu for dd ram. however, when n and nw is 0 (1-line display), aaaaaaa can be (00)h to (4f)h. when n is 1 and nw is 0 (2-line display), aaaaaaa is (00)h to (27)h for the first line, and (40)h to (67)h for the second line. when nw is 1 (4-line display), aaaaaaa is (00)h to (13)h for the first line, (20)h to (33)h for the second line, (40)h to (53)h for the third line, and (60)h to (73)h for the fourth line. set scroll quantity when extended registor enable bit (re) is 1, hds5 to hds0 can be set. hds5 to hds0 specifies horizontal scroll quantity to the left of the display in dot units. the hd66712 uses the unused ddram area to execute a desired horizontal smooth scroll from 1 to 48 dots. note: when performing a horizontal scroll as de- scribed above by connecting an extended driver, the maximum number of characters per line decreases by the quantity set by the above horizontal scroll. for example, when the maximum 24-dot scroll quantity (4 characters) is used with 6-dot font width and 4-line display, the maximum numbers of characters is 20 ?4 = 16. notice that in low power mode (lp = 1), display shift and scroll cannot be performed.
458 hd66712 read busy flag and address read busy flag and address reads the busy flag (bf) indicating that the system is now internally operating on a previously received instruction. if bf is 1, the internal operation is in progress. the next instruction will not be accepted until bf is reset to 0. check the bf status before the next write operation. at the same time, the value of the address counter in binary aaaaaaa is read out. this address counter is used by both cg, dd, and segram addresses, and its value is determined by the previous instruction. the address contents are the same as for cg ram, dd ram, and segram address set instructions. write data to cg, dd, or seg ram this instruction writes 8-bit binary data dddddddd to cg, dd or segram. cg, dd or segram is selected by the previous specifica- tion of the address set instruction (cg ram address set / dd ram address set / segram address set). after a write, the address is automati- cally incremented or decremented by 1 according to the entry mode. the entry mode also determines the display shift direction. read data from cg, dd, or seg ram this instruction reads 8-bit binary data dddddddd from cg, dd, or seg ram. cg, dd or segram is selected by the previous specification of the address set instruction. if no address is specified, the first data read will be invalid. when executing serial read instructions, the next address is normally read from the next address. an address set instruction need not be executed just before this read instruction when shifting the cursor by a cursor shift instruction (when reading from dd ram). a cursor shift instruction is the same as a set dd ram address instruction. after a read, the entry mode automatically in- creases or decreases the address by 1. however, a display shift is not executed regardless of the entry mode. note: the address counter (ac) is automatically incremented or decremented after write in- structions to cg, dd or seg ram. the ram data selected by the ac cannot be read out at this time even if read instruc- tions are executed. therefore, to read data correctly, execute either an address set in- struction or a cursor shift instruction (only with dd ram), or alternatively, execute a preliminary read instruction to ensure the address is correctly set up before accessing the data. table 11 hs5 to hs0 settings hds5 hds4 hds3 hds2 hds1 hds0 description 000000 no shift 000001 shift the display position to the left by one dot. 000010 shift the display position to the left by two dots. 000011 shift the display position to the left by three dots. . . . 101111 shift the display position to the left by forty-seven dots. 11 **** shift the display position to the left by forty-eight dots.
table 12 instructions execution code time (max) re (when f cp or instruction bit rs r/w db7 db6 db5 db4 db3 db2 db1 db0 description f osc is 270 khz) clear 0/1 0 0 00000001 clears entire display and 1.52 ms display sets dd ram address 0 in address counter. return 0/1 0 0 0000001 sets dd ram address 0 1.52 ms home in address counter. also returns display from being shifted to original position. ddram con- tents remain unchanged. entry 0/1 0 0 000001i/ds sets cursor move 37 s mode set direction and specifies display shift. these operations are performed during data write and read. display 0 0 0 00001dcb sets entire display (d) 37 s on/off on/off, cursor on/off (c), control and blinking of cursor position character (b). extension 1 0 0 00001fwb/wnw sets a font width, a 37 s function black-white inverting set cursor (b/w), and a 4-line display (nw). cursor or 0 0 0 0001s/cr/l moves cursor and shifts 37 s display display without changing shift dd ram contents. scroll enable 1 0 0 0001hsehsehsehse specifies which display 37 s lines to undergo horizontal smooth scroll. function 0 0 0 001dlnre sets interface data length 37 s set (dl), number of display lines (l), and extension register write enable (re). 100 001dlnrebelp sets cgram/segram 37 s blinking enable (be), and power-down mode (lp). lp is available when the ext pin is low. set 0 0 0 0 1 a cg a cg a cg a cg a cg a cg sets cg ram address. 37 s cgram cg ram data is sent and address received after this setting. set 1 0 0 0 1 ** a seg a seg a seg a seg sets segram address. 37 s segram segram data is sent and address set received after this setting. set ddram 0 0 0 1 a dd a dd a dd a dd a dd a dd a dd sets dd ram address. 37 s address dd ram data is sent and received after this setting. set scroll 1 0 0 1 * hds hdshds hds hds hds sets horizontal dot scroll 37 s quantity quantity. hd66712 459
table 12 instructions (cont) execution code time (max) re (when f cp or instruction bit rs r/w db7 db6 db5 db4 db3 db2 db1 db0 description f osc is 270 khz) read busy 0/1 0 1 bf ac ac ac ac ac ac ac reads busy flag (bf) 0 s flag & indicating internal opera- address tion is being performed and reads address counter contents. write data 0/1 1 0 write data writes data into dd ram, 7 s to ram cg ram, or segram. t add = 5.5 s * read data 0/1 1 1 read data reads data from dd ram, 37 s from ram cg ram, or segram. t add = 5.5 s * i/d = 1: increment dd ram: display data ram i/d = 0: decrement a dd : dd ram address (corresponds s = 1: accompanies display shift to cursor address) d = 1: display on cg ram: character generator ram c = 1: cursor on a cg : cg ram address b = 1: blink on segram: segment ram fw = 1: 6-dot font width a seg : segment ram address b/w = 1: black-white inverting cursor on hse: specifies horizontal scroll lines nw = 1: four lines hds: horizontal dot scroll quantity nw = 0: one or two lines ac: address counter used for both s/c = 1: display shift dd, cg, and seg ram s/c = 0: cursor move addresses. r/l = 1: shift to the right r/l = 0: shift to the left dl = 1: 8 bits, dl = 0: 4 bits n = 1: 2 lines, n = 0: 1 line re = 1: extension register access enable be = 1: cgram/segram blinking enable lp = 1: low-power mode bf = 1: internally operating bf = 0: instructions acceptable note: 1. ? indicates no effect. * after execution of the cg ram/dd ram data write or read instruction, the ram address counter is incremented or decremented by 1. the ram address counter is updated after the busy flag turns off. in figure 17, t add is the time elapsed after the busy flag turns off until the address counter is updated. 2. extension time changes as frequency changes. for example, when f is 300 khz, the execution time is: 37 s 270/300 = 33 s. 3. execution time in a low-power mode (lp = 1 and ext = low) becomes four times for a 1-line mode, and twice for a 2- or 4-line mode. 460 hd66712
figure 17 address counter update hd66712 461 busy state busy state (db pin) address counter (db to db pins) 7 06 t add a a + 1 t depends on the operation frequency. t = 1.5/(f or f ) seconds add add cp osc
462 hd66712 interfacing the hd66712 interface with 8-bit mpus: the hd66712 can interface directly with an 8-bit mpu using the e clock, or with an 8-bit mcu through an i/o port. when the number of i/o ports in the mcu, or the interfacing bus width, if limited, a 4-bit interface function is used. figure 18 example of 8-bit data transfer timing sequence r/ w e internal signal db7 internal operation data busy busy not busy data instruction write busy flag check busy flag check busy flag check instruction write rs
figure 19 8-bit mpu interface hd66712 463 c0 c1 c2 a0?7 e rs r/ w db0Cdb7 vma ?2 a15 a0 r/ w d0Cd7 e rs r/ w db0Cdb7 8 8 h8/325 hd6800 lcd-ii/f12 i) bus line interface ii) i/o port interface lcd-ii/f12
464 hd66712 interface with 4-bit mpus: the hd66712 can interface with a 4-bit mcu through an i/o port. 4- bit data representing high and low order bits must be transferred sequentially. the dl bit in function-set selects 4-bit or 8-bit interface data length. figure 20 example of 4-bit data transfer timing sequence figure 21 4-bit mpu interface e internal signal db7 internal operation instruction write busy flag check busy flag check instruction write rs ir7 busy not busy ir3 ac3 ac3 d7 d3 r/ w d15 d14 d13 r10Cr13 rs r/ w e db4Cdb7 hmcs4019r lcd-ii/f12 4
oscillator circuit figure 22 oscillator circuit figure 23 frame frequency hd66712 465 osc1 osc1 osc2 clock rf the oscillator frequency can be adjusted by oscillator resistance (rf). if rf is increased or power supply voltage is decreased, the oscillator frequency decreases. the recommended oscillator resistor is as follows. lcd-ii/f12 ?rf = 91 k w ?2% (v cc = 5 v) ?rf = 75 k w ?2% (v cc = 3 v) 1) when an external clock is used 2) when an internal oscillator is used lcd-ii/f12 1 2 3 4 32 33 1 2 3 32 33 v cc v1 v4 v5 com1 1-line selection period (2) 1 /33 duty cycle 1 frame 1 frame 1 2 3 4 16 17 1 2 3 16 17 1-line selection period v cc v1 v4 v5 com1 1 frame 1 frame (1) 1 /17 duty cycle item line selection period frame frequency normal display mode (lp = 0) 5-dot font width low power mode (lp = 1) 5-dot font width 200 clocks 79.4 hz 240 clocks 66.2 hz 60 clocks 66.2 hz 72 clocks 55.1 hz item line selection period frame frequency normal display mode (lp = 0) low power mode (lp = 1) 100 clocks 81.8 hz 120 clocks 68.2 hz 60 clocks 68.2 hz 72 clocks 56.8 hz 6-dot font width 6-dot font width 5-dot font width 5-dot font width 6-dot font width 6-dot font width note: at the calculation example above for displayed frame frequency, all oscillator frequencies are 270 khz (1 clock = 3.7 m s). note: at the calculation example above for displayed frame frequency, all oscillator frequencies are 270 khz (1 clock = 3.7 m s).
466 hd66712 power supply for liquid crystal display drive 1) when an external power supply is used 2) when an internal booster is used v cc v1 v2 v3 v4 v5 v cc r r r0 r r vr v ee v cc v1 v2 v3 v4 v5 v cc c1 c2 vci gnd v5out2 r r r0 r r c1 c2 vci gnd v5out2 r r r0 r r v5out3 v5out3 1f + 1f + 1f + 1f + 1f + (boosting twice) (boosting three times) v cc v1 v2 v3 v4 v5 v cc notes: 1. 2. 3. boosting output voltage should not exceed the power supply voltage (2) (15 v max.) in the absolute maximum ratings. especially, voltage of over 5 v should not be input to the reference voltage (vci) when boosting three times. vci input terminal is used for reference voltage and power supply for the internal booster. input current into the vci pin needs three times or more of load current through the bleeder resistor for lcd. so, when it adjusts lcd driving voltage (vlcd), input voltage should be controlled with transistor to supply lcd load current. please notice connection (+/? when it uses capacitors with poler. the vci must be set below the power supply (v cc ). ntc-type thermistor ntc-type thermistor gnd gnd gnd gnd
table 13 duty factor and power supply for liquid crystal display drive item data number of lines 1 2/4 duty factor 1/17 1/33 bias 1/5 1/6.7 divided resistance r r r r0 r 2.7r note: r changes depending on the size of liquid crystal panel. normally, r must be 4.7 k to 20 k . hd66712 467
468 hd66712 extension driver lsi interface by bringing the ext pin high, extended driver interface signals (cl1, cl2, d, and m) are output. table 14 relationships between the number of display lines and 40-output extension driver controller lcd-ii/f12 lcd-ii/f8 hd44780 hd66702 display lines 5-dot width 6-dot width 5-dot width 6-dot width 5-dot width 5-dot width 16 2 lines not required not required not required 1 1 not required 20 2 lines not required not required 1 1 2 not required 24 2 lines not required 1 1 2 2 1 40 2 lines disabled disabled disabled disabled 4 3 12 4 lines not required 1 1 1 disabled disabled 16 4 lines 1 1 1 2 disabled disabled 20 4 lines 1 2 2 3 disabled disabled note: the number of display lines can be extended to 32 2 lines or 20 4 lines in the lcd-ii/f12. the number of display lines can be extended to 30 2 lines or 20 4 lines in the lcd-ii/f8. figure 24 hd66712 and the extension driver connection com0? com33 seg1?eg60 ext seg1? seg60 gnd lcd-ii/f12 com0? com33 ext cl1 v cc cl2 m d cl1 lcd-ii/f12 seg1? seg60 extension driver seg1? seg40 cl2 d m a) 1-chip operation (ext = low, 5-dot font width) b) when using the extension driver (ext = high, 5-dot font width) 24 2-line display 32 2-line display
table 15 display start address in each mode number of lines 1-line mode 2-line mode 4-line mode output 5 dot 6 dot 5 dot 6 dot 5 dot/6 dot com1?om8 d001 d001 d001 d001 d001 com9?om16 d0c1 d0a1 d0c1 d0a1 d201 com17?om24 d401 d401 d401 com25?om32 d4c1 d4a1 d601 com0/com17 s00 s00 com0/com33 s00 s00 s00 notes: 1. the number of display lines is determined by setting the n/nw bit. the font width is determined by the fw bit. 2. d ** is the start address of display data ram (ddram). 3. s ** is the start address of segment ram (segram). 4. 1 following d ** indicates increment or decrement at display shift. hd66712 469
figure 25 correspondence between the display position at extension display and the ddram address 470 hd66712 00 01 02 03 04 05 06 11 12 13 0a 0b 0c 0d 0e 0f 10 07 08 09 40 41 42 43 44 45 46 51 52 53 4a 4b 4c 4d 4e 50 47 48 49 com1 to com8 com17 to com24 lcd-ii/f12 seg1?eg60 lcd-ii/f12 seg1?eg60 com9 to com16 com25 to com32 1 2 3 4 5 6 7 8 9 10 11121314151617181920 b) 6-dot font width: 24 2-line display a) 5-dot font width: 32 2-line display 4f 14 15 16 17 54 55 56 57 extension driver seg1?eg24 21 22 23 24 00 01 02 03 04 05 06 0a 0b 07 08 09 40 41 42 43 44 45 46 4a 4b 47 48 49 com1 to com8 com17 to com24 lcd-ii/f12 seg1?eg60 1234567891011121314151617181920 14 15 16 17 54 55 56 57 21 22 23 24 com9 to com16 com25 to com32 extension driver seg1?eg40 25 26 27 28 29 30 31 32 lcd-ii/f12 seg1?eg60 com1 to com8 com17 to com24 lcd-ii/f12 seg1?eg60 extension driver seg1?eg40 com9 to com16 com25 to com32 1 2 3 4 5 6 7 8 9 101112 1314151617181920 c) 5-dot font width: 20 ? 4-line display d) 6-dot font width: 20 ? 4-line display 11 12 13 0a 0b 0c 0d 0e 0f 10 07 08 09 61 62 63 2a 2b 2c 2d 2e 2f 60 27 28 29 51 52 53 4a 4b 4c 4d 4e 4f 50 47 48 49 71 72 73 6a 6b 6c 6d 6e 6f 70 67 68 69 00 01 02 03 04 05 06 20 21 22 23 24 25 26 40 41 42 43 44 45 46 60 61 62 63 64 65 66 com1 to com8 com17 to com24 lcd-ii/f12 seg1?eg60 extension driver (1) seg1?eg40 com9 to com16 com25 to com32 1 2 3 4 5 6 7 8 9 10 11121314151617181920 11 12 13 0a 0b 0c 0d 0e 0f 10 07 08 09 61 62 63 2a 2b 2c 2d 2e 2f 60 27 28 29 51 52 53 4a 4b 4c 4d 4e 4f 50 47 48 49 71 72 73 6a 6b 6c 6d 6e 6f 70 67 68 69 00 01 02 03 04 05 06 20 21 22 23 24 25 26 40 41 42 43 44 45 46 60 61 62 63 64 65 66 extension driver (2) seg1?eg20 1d 1e 1f 18 19 1a 1b 1c 5d 5e 5f 58 59 5a 5c 5b 11 12 13 0c 0d 0e 0f 10 51 52 53 4c 4d 4e 50 4f
hd66712 471 interface to liquid crystal display set the extended driver control signal output, the number of display lines, and the font width with the ext pin, an extended register nw, and the fw bit, respectively. the relationship between the number of display lines, ext pin, and register value is given below. table 16 relationship between display lines, ext pin, and register setting 5 dot font 6 dot font no. of no. of ext extended registor setting ext extended registor setting lines character pin driver n re nw fw pin driver n re nw fw duty 1 20 l 0 0 0 0 l 0 1 0 1 1/17 24 l 0 0 0 0 h 1 0 1 0 1 1/17 40 h 2 0 0 0 0 h 3 0 1 0 1 1/17 2 20 l 1 0 0 0 l 1 1 0 1 1/33 24 l 1 0 0 0 h 1 1 1 0 1 1/33 32 h 1 1 0 0 0 h 2 1 1 0 1 1/33 412 l * 11 0 h 1 * 1 1 1 1/33 16 h 1 * 11 0 h 1 * 1 1 1 1/33 20 h 1 * 11 0 h 2 * 1 1 1 1/33 note: ?means not required.
example of 5-dot font width connection figure 26 24 1-line + 60-segment display (5-dot font, 1/17 duty) figure 27 24 1-line + 60-segment display (5-dot font, 1/33 duty) 472 hd66712 com1 com2 com3 com4 com5 com6 com7 com8 com9 com10 com11 com12 com13 com14 com15 com16 seg1 seg2 seg3 seg4 seg5 seg60 com17 (com0) lcd-ii/f12 1121324 seg6 ext ? + ? x ? = note: com0 and com17 output the same signals. apply them according to the wiring pattern. lcd-ii/f12 com1 com2 com3 com4 com5 com6 com7 com8 com17 com18 com19 com20 com21 com22 com23 com24 com9 com10 com11 com12 com13 com14 com15 com16 com25 com26 com27 com28 com29 com30 com31 com32 seg1 seg2 seg3 seg4 seg5 seg60 com33 (com0) 1121324 seg6 ext ? + ? x ? = note: com0 and com33 output the same signals. apply them according to the wiring pattern.
figure 28 12 4-line + 60 segment display (5-dot font, 1/33 duty) figure 29 20 4-line + 80 segment display (5-dot font, 1/33 duty) hd66712 473 lcd-ii/f12 com1 com2 com3 com4 com5 com6 com7 com8 com9 com10 com11 com12 com13 com14 com15 com16 com56 com57 com58 com59 seg1 seg2 seg3 seg4 seg5 seg6 seg7 seg8 seg9 seg10 1 212 ext com17 com18 com19 com20 com21 com22 com23 com24 com25 com26 com27 com28 com29 com30 com31 com32 ? + ? x ? = com60 com33 (com0) note: com0 and com33 output the same signals. apply them according to the wiring pattern. lcd-ii/f12 com1 com2 com3 com4 com5 com6 com7 com8 com9 com10 com11 com12 com13 com14 com15 com16 seg1 seg2 seg3 seg4 seg5 seg56 seg57 seg58 seg59 seg60 1 12 20 ext com17 com18 com19 com20 com21 com22 com23 com24 com25 com26 com27 com28 com29 com30 com31 com32 ? + ? x ? = com33 (com0) 13 v cc seg1 seg2 seg3 seg4 seg5 extension driver note: com0 and com33 output the same signals. apply them according to the wiring pattern. seg36 seg37 seg38 seg39 seg40
figure 30 20 2-line + 60 segment display (6-dot font, 1/33 duty) 474 hd66712 lcd-ii/f12 com1 com2 com3 com4 com5 com6 com7 com8 com17 com18 com19 com20 com21 com22 com23 com24 com9 com10 com11 com12 com13 com14 com15 com16 com25 com26 com27 com28 com29 com30 com31 com32 seg1 seg2 seg3 seg4 seg5 seg55 seg56 seg57 seg58 seg59 com33 (com0) seg6 seg60 ext 110 11 20 ? + ? x ? = note: com0 and com33 output the same signals. apply them according to the wiring pattern.
hd66712 475 instruction and display correspondence 8-bit operation, 24-digit 1-line display with internal reset refer to table 17 for an example of an 24-digit 1-line display in 8-bit operation. the lcd- ii/f12 functions must be set by the function set instruction prior to the display. since the display data ram can store data for 80 characters, a character unit scroll can be performed by a display shift instruction. a dot unit smooth scroll can also be performed by a horizontal scroll instruction. since data of display ram (ddram) is not changed by a display shift instruction, the display can be returned to the first set display when the return home operation is performed. 4-bit operation, 24-digit 1-line display with internal reset the program must set all functions prior to the 4-bit operation (see table 18). when the power is turned on, 8-bit operation is automatically selected and the first write is performed as an 8- bit operation. since db 0 to db 3 are not con- nected, a rewrite is then required. however, since one operation is completed in two accesses for 4-bit operation, a rewrite is needed to set the functions. thus, db 4 to db 7 of the function set instruction is written twice. 8-bit operation, 24-digit 2-line display with internal reset for a 2-line display, the cursor automatically moves from the first to the second line after the 40th digit of the first line has been written. thus, if there are only 16 characters in the first line, the dd ram address must be again set after the 16th character is completed. (see table 19.) the display shift is performed for the first and second lines. if the shift is repeated, the display of the second line will not move to the first line. the same display will only shift within its own line for the number of times the shift is repeated. 8-bit operation, 12-digit 4-line display with internal reset the re bit must be set by the function set instruction and then the nw bit must be set by an extension function set instruction. in this case, 4-line display is always performed regard- less of the n bit setting (see table 20). in a 4-line display, the cursor automatically moves from the first to the second line after the 20th digit of the first line has been written. thus, if there are only 8 characters in the first line, the dd ram address must be set again after the 8th character is completed. display shifts are per- formed on all lines simultaneously. note: when using the internal reset, the electrical characteristics in the power supply condi- tions using internal reset circuit table must be satisfied. if not, the lcd-ii/f12 must be initialized by instructions. see the section, initializing by instruction.
table 17 8-bit operation, 24-digit 1-line display example with internal reset step instruction no. rs r/ w d7 d6 d5 d4 d3 d2 d1 d0 display operation 1 power supply on (the hd66712 is initialized by initialized. no display. the internal reset circuit) 2 function set sets to 8-bit operation and rs r/ w d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 selects 1-line display. 00001100 ** bit 2 must always be cleared. 3 return home return both display and cursor 0000000010 to the original position (address 0). 4 display on/off control turns on display and cursor. 0000001110 entire display is in space mode because of initialization. 5 entry mode set sets mode to increment the 0000000110 address by one and to shift the cursor to the right at the time of write to the ram. display is not shifted. 6 write data to cg ram/dd ram writes h. dd ram has 1001001000 already been selected by initialization when the power was turned on. 7 write data to cg ram/dd ram writes i. 1001001001 8 9 write data to cg ram/dd ram writes i. 1001001001 10 entry mode set sets mode to shift display at 0000000111 the time of write. 11 write data to cg ram/dd ram writes a space. 1000100000 476 hd66712 _ _ h_ hi_ hitachi_ hitachi_ itachi _
table 17 8-bit operation, 24-digit 1-line display example with internal reset (cont) step instruction no. rs r/ w d7 d6 d5 d4 d3 d2 d1 d0 display operation 12 write data to cg ram/dd ram writes m. 1001001101 13 14 write data to cg ram/dd ram writes o. 1001001111 15 cursor or display shift shifts only the cursor position 00000100 ** to the left. 16 cursor or display shift shifts only the cursor position 00000100 ** to the left. 17 write data to cg ram/dd ram writes c over k. 1001000011 the display moves to the left. 18 cursor or display shift shifts the display and cursor 00000111 ** position to the right. 19 cursor or display shift shifts the display and cursor 00000101 ** position to the right. 20 write data to cg ram/dd ram writes m. 1001001101 21 22 return home returns both display and cursor 0000000010 to the original position (address 0). hd66712 477 tachi m_ microko_ microko _ microko _ icroco _ microco _ microco_ icrocom_ hitachi _
table 18 4-bit operation, 24-digit 1-line display example with internal reset step instruction no. rs r/ w d7 d6 d5 d4 d3 d2 d1 d0 display operation 1 power supply on (the hd66712 is initialized by initialized. no display. the internal reset circuit) 2 function set sets to 4-bit operation. rs r/w d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 clear bit 2. in this case, 000010 operation is handled as 8 bits by initialization. * 1 3 function set sets 4-bit operation and selects 000010 1-line display. clear be, lp bits. 000100 4-bit operation starts from this step. 4 function set sets 4-bit operation and selects 000010 1 line display. clear bit 2 (re). 0000 ** 5 return home returns both display and cursor 000000 to the original position 000010 (address 0). 6 display on/off control turns on display and cursor. 000000 entire display is in space mode 001110 because of initialization. 7 entry mode set sets mode to increment the 000000 address by one and to shift the 000110 cursor to the right at the time of write to the dd/cg ram. display is not shifted. 8 write data to cg ram/dd ram writes h. 100100 ddram has already been 101000 selected by initialization. . based on 8-bit operation after . this instruction. . note: the control is the same as for 8-bit operation beyond step #8. 1. when db3 to db0 pins are open in 4-bit mode, the re, be, lp bits are set to ??at step #2. so, these bits are clear to ??at step #3. 478 hd66712 _ _ h_
table 19 8-bit operation, 24-digit 2-line display example with internal reset step instruction no. rs r/ w d7 d6 d5 d4 d3 d2 d1 d0 display operation 1 power supply on (the hd66712 is initialized by initialized. no display. the internal reset circuit) 2 function set sets to 8-bit operation and rs r/w db 7 db 6 db 5 db 4 db 3 db 2 db 1 db 0 selects 2-line display. 00001110 ** clear bit 2. 3 display on/off control turns on display and cursor. 0000001110 all display is in space mode because of initialization. 4 entry mode set sets mode to increment the 0000000110 address by one and to shift the cursor to the right at the time of write to the ram. display is not shifted. 5 write data to cg ram/dd ram writes ?.?dd ram has 1001001000 already been selected by initialization at power-on. 6 7 write data to cg ram/dd ram writes i. 1001001001 8 set dd ram address sets dd ram address so that 0011000000 the cursor is positioned at the head of the second line. hd66712 479 _ _ h_ hitachi_ hitachi _
table 19 8-bit operation, 24-digit 2-line display example with internal reset (cont) step instruction no. rs r/ w d7 d6 d5 d4 d3 d2 d1 d0 display operation 9 write data to cg ram/dd ram writes a space. 1001001101 10 11 write data to cg ram/dd ram writes o. 1001001111 12 entry mode set sets mode to shift display at 0000000111 the time of write. 13 write data to cg ram/dd ram writes m. 1001001101 14 15 return home returns both display and cursor 0000000010 to the original position (address 0). 480 hd66712 hitachi m_ hitachi microco_ hitachi microco_ itachi icrocom_ hitachi microcom _
table 20 8-bit operation, 12-digit 4-line display example with internal reset step instruction no. rs r/ w d7 d6 d5 d4 d3 d2 d1 d0 display operation 1 power supply on (the hd66712 is initialized by initialized. no display. the internal reset circuit) 2 function set sets 8-bit operation and 00001101 ** enables write to the extension register. 3 4-line mode set sets 4-line operation. 0000001001 4 return home return both display and cursor 0000000010 to the original position. 5 function set inhibits write to extension inhibit write to extension register register. invalidates selection 00001100 ** of 1-line/2-line by bit 3. 6 display on/off control turns on display and cursor. 0000001110 entire display is cleared because of initialization. 7 entry mode set sets mode to increment the 0000000110 address by one and to shift the cursor to the right when writing to ram. display is not shifted. 8 write data to cg ram/dd ram writes h. ddram has already 1001001000 been selected by initialization. 9 hd66712 481 _ _ h_
table 20 8-bit operation, 12-digit 4-line display example with internal reset (cont) step instruction no. rs r/ w d7 d6 d5 d4 d3 d2 d1 d0 display operation 10 write data to cg ram/dd ram writes i. 1001001001 11 set dd ram address sets dd ram address to (20)h 0010100000 so that the cursor is positioned at the beginning of the second line. 12 write data to cg ram writes 0. 1000110000 482 hd66712 hitachi_ hitachi _ hitachi 0_
hd66712 483 initializing by instruction if the power supply conditions for correctly operat- ing the internal reset circuit are not met, initializa- tion by instructions becomes necessary. initializing when a length of interface is 8-bit system. (see figure 31.) initializing when a length of interface is 4-bit system. (see figure 32.) figure 31 initializing flow of 8-bit interface power on wait for more than 4.1 ms wait for more than 100 ? rs 0 r/w 0 db 0 db 0 db 1 db 1 db db db db 76543210 * * * * rs 0 r/w 0 db 0 db 0 db 1 db 1 db db db db 76543210 * * * * rs 0 r/w 0 db 0 db 0 db 1 db 1 db db db db 76543210 * * * * rs 0 r/w 0 db 0 db 0 db 1 db 1 db n db 0 db db 76543210 * * 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 0 0 i/d 0 1 s initialization ends bf cannot be checked before this instruction. function set (interface is 8 bits long.) bf cannot be checked before this instruction. function set (interface is 8 bits long.) bf cannot be checked before this instruction. function set (interface is 8 bits long.) bf can be checked after the following instructions. when bf is not checked, the waiting time between instructions is longer than the execution instruction time. (see table 12.) function set display off display clear entry mode set ?wait for more than 15 ms after vcc rises to 4.5 v (v cc = 5 v during operation) ?wait for more than 40 ms after vcc rises to 2.7 v (v cc = 3 v during operation)
figure 32 initializing flow of 4-bit interface 484 hd66712 initialization ends ?wait for more than 15 ms after vcc rises to 4.5 v (v cc = 5 v during operation) ?wait for more than 40 ms after vcc rises to 2.7 v (v cc = 3 v during operation) bf cannot be checked before this instruction. function set (interface is 8 bits long) bf cannot be checked before this instruction. function set (interface is 8 bits long) bf cannot be checked before this instruction. function set (interface is 8 bits long) db 0 db 0 db 1 db 1 7654 rs 0 r/w 0 wait for more than 4.1 ms db 0 db 0 db 1 db 1 7654 rs 0 r/w 0 wait for more than 100 ? db 0 db 0 db 1 db 1 7654 rs 0 r/w 0 db 0 db 0 db 1 db 0 7654 rs 0 r/w 0 0 n 0 n 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 1 1 0 1 * 0 0 0 0 0 i/d 0 0 0 * 0 0 0 1 0 s 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bf can be checked after the following instructions. when bf is not checked, the waiting time between instructions is longer than the execution instruction time. (see table 12.) * 1 function set (4-bit mode) display off display clear entry mode set (i/d, s specification) function set (4-bit mode, n specification) be, le are clear to 0 power on function set (4-bit mode, n specification) * 1 * 1 * 2 important notice when db3 to db0 pins are open in 4-bit mode, the n, re, be, lp bits are set to ?.?in this case, instruction time becomes four times in a low power mode (lp = ??. the low power mode is available in this step, so instruction time takes four times. notes: 1. 2.
hd66712 485 horizontal dot scroll dot unit scrolls are performed by setting the hori- zontal dot scroll quantity resister (hds) when the extension register is enabled (re = ??. and the shifted line can be selected with the scroll enable register (hde). so, it can control dot unit shifts by each display line. to scroll smoothly, lcd-ii/f12 supports 6 dots- font width mode (fw = 1). the below figures are examples of scroll display. figure 33 example of dot scroll display no shift performed one dot shift to the left when 5-dots font width (fw = 0) two dots shift to the left three dots shift to the left four dots shift to the left when 6-dots font width (fw = 1) no shift performed one dot shift to the left two dots shift to the left three dots shift to the left four dots shift to the left five dots shift to the left icon mark and 1st to 3rd line are fixed, and only 4th line is sifted hds = 1000 (4th line scroll enable) example of 10 digits 4 lines with 6-dots fonts width mode
figure 34 method of smooth scroll display 486 hd66712 db7 db6 db5 db4 db3 db2 db1 db0 rs r/ w 00001dln 1 be lp enable extension resistor. 1 4th line scroll enable. one dot shift in 4th line to the left. two dots shift in 4th line to the left. three dots shift in 4th line to the left. cpu wait cpu wait cpu wait four dots shift in 4th line to the left. cpu wait 0010 000001 3 000001 1000 2 0010 000010 4 0010 000011 5 0010 000100 6 47 dots shift in 4th line to the left. cpu wait 48 dots shift in 4th line to the left. 0011 101111 49 0010 110000 50 note: when perfoming a dot scroll with an extended driver, the maximum number or characters per line decreases by quantity set by the dot scroll. for example, when the maximum 24-dot scroll quantity (4 characters) is used with 6-dot font width and 4-line display, the maximum numbers of character is 20 C 4 = 16. notice that in low power mode (lp = 1), display shift and dot scroll cannot be performed. 6-dots font width mode (fw = 1) 4 line display mode (nw = 1)
hd66712 487 low power mode when the extension driver is not used (ext = low) with extension register enabled (re = 1), the hd66712 enters low power mode by setting the low-power mode bit (lp) to 1. during low-power mode, as the internal operation clock is divided by 2 (2-line/4-line display mode) or by 4 (1-line display mode), the execution time of each instruction becomes two times or four times longer than normal. in addition, as the frame frequency decreases to 5/6, display quality might be affected. in addition, since the display is not shifted in low power mode, display shift must be cleared with the return home instruction before setting low power mode. the amount of horizontal scroll must also be cleared (hds = 000000). moreover, because the display enters a shift state after clearing low-power mode, the home return instruction must be used to clear display shift at that time. figure 35 usage of low power mode rs r/w db7 db6 db5 db4 db3 db2 db1 db0 00000000 0 rs r/ w db7 db6 db5 db4 db3 db2 db1 db0 00001dln be0 rs r/ w db7 db6 db5 db4 db3 db2 db1 db0 001 0000 rs r/ w db7 db6 db5 db4 db3 db2 db1 db0 00001dln be rs r/w db7 db6 db5 db4 db3 db2 db1 db0 00001dln be note: the execution time of an instruction in low-power mode becomes two times or four times longer then normal. the frame frequency also decreases by 5/6. return home extended register enable clear horizontal scroll quantity hds = 000000 set a low power mode clear low power mode low power operation 1 1 1 1 0 00 1 0 rs r/ w db7 db6 db5 db4 db3 db2 db1 db0 00000000 0 return home 1 note: up until this instruction, execution time is two times or four times longer than normal. note: because the display enters a shift state, be sure to execute this instruction.
absolute maximum ratings* item symbol unit value notes power supply voltage (1) v cc v ?.3 to +7.0 1 power supply voltage (2) v cc ? 5 v ?.3 to +15.0 1, 2 input voltage v t v ?.3 to v cc +0.3 1 operating temperature t opr ? ?0 to +75 3 storage temperature t stg ? ?5 to +125 4 note: * if the lsi is used above these absolute maximum ratings, it may become permanently damaged. using the lsi within the following electrical characteristic limits is strongly recommended for normal operation. if these electrical characteristic conditions are also exceeded, the lsi will malfunction and cause poor reliability. 488 hd66712
dc characteristics (v cc = 2.7 v to 5.5 v, t a = ?0 to +75? *3 ) item symbol min typ max unit test condition notes * input high voltage (1) v ih1 0.7v cc ? cc v6 (except osc 1 ) input low voltage (1) v il1 ?.3 0.2v cc vv cc = 2.7 to 3.0 v 6 (except osc 1 ) ?.3 0.6 v v cc = 3.0 to 4.5 v input high voltage (2) v ih2 0.7v cc ? cc v15 (osc 1 ) input low voltage (2) v il2 0.2v cc v15 (osc 1 ) output high voltage (1) v oh1 0.75v cc vi oh = 0.1 ma 7 (d 0 ? 7 ) output low voltage (1) v ol1 0.2v cc vi ol = 0.1 ma 7 (d 0 ? 7 ) output high voltage (2) v oh2 0.8v cc vi oh = 0.04 ma 8 (except d 0 ? 7 ) output low voltage (2) v ol2 0.2v cc vi ol = 0.04 ma 8 (except d 0 ? 7 ) driver on resistance r com 20 k id = 0.05 ma (com) 13 (com) v lcd = 4 v driver on resistance r seg 30 k id = 0.05 ma (seg) 13 (seg) v lcd = 4 v i/o leakage current i li ? 1 a v in = 0 to v cc 9 pull-up mos current ?p 10 50 120 a v cc = 3 v (d 0 ? 7 , reset * pin) vin = 0 v power supply current icc 0.15 0.30 ma r f oscillation, 10, 14 external clock v cc = 3v, f osc = 270 khz lcd voltage v lcd1 3.0 13.0 v v cc ? 5 , 1/5 bias 16 v lcd2 3.0 13.0 v v cc ? 5 , 1/6.7 bias 16 note: * refer to electrical characteristics notes following these tables. booster characteristics item symbol min typ max unit test condition notes * output voltage v up2 7.5 8.7 v v ci = 4.5 v, i 0 = 0.25 ma, 18, 19 (v5out2 pin) c = 1 f, f osc = 270 khz t a = 25? output voltage v up3 7.0 7.7 v v ci = 2.7 v, i 0 = 0.25 ma, 18, 19 (v5out3 pin) c = 1 f, f osc = 270 khz t a = 25? input voltage v ci 2.0 5.0 v vci v cc 18, 19 ta = 25? 20 note: * refer to electrical characteristics notes following these tables. hd66712 489
ac characteristics (v cc = 2.7 v to 5.5 v, t a = ?0 to +75? *3 ) clock characteristics (v cc = 2.7 v to 5.5 v, t a = ?0 to +75? *3 ) item symbol min typ max unit test condition notes * external external clock frequency f cp 125 270 410 khz 11 clock external clock duty duty 45 50 55 % operation external clock rise time t rcp 0.2 s external clock fall time t rcp 0.2 s r f clock oscillation frequency f osc 190 270 350 khz r f = 91 k , 12 oscillation v cc = 5 v note: * refer to the electrical characteristics notes section following these tables. system interface timing characteristics (1) (v cc = 2.7 v to 4.5 v, t a = ?0 to +75? *3 ) bus write operation item symbol min typ max unit test condition enable cycle time t cyce 1000 ns figure 36 enable pulse width (high level) pw eh 450 enable rise/fall time t er , t ef 25 address set-up time (rs, r/w to e) t as 60 address hold time t ah 20 data set-up time t dsw 195 data hold time t h 10 bus read operation item symbol min typ max unit test condition enable cycle time t cyce 1000 ns figure 37 enable pulse width (high level) pw eh 450 enable rise/fall time t er , t ef 25 address set-up time (rs, r/w to e) t as 60 address hold time t ah 20 data delay time t ddr 360 data hold time t dhr 5 490 hd66712
serial interface operation item symbol min typ max unit test condition serial clock cycle time t scyc 1 20 s figure 38 serial clock (high level width) t sch 400 ns serial clock (low level width) t scl 400 serial clock rise/fall time t scr , t scf 50 chip select set-up time t csu 60 chip select hold time t ch 20 serial input data set-up time t sisu 200 serial input data hold time t sih 200 serial output data delay time t sod 360 serial output data hold time t soh 0 system interface timing characteristics (2) (v cc = 4.5 v to 5.5 v, t a = ?0 to +75? *3 ) bus write operation item symbol min typ max unit test condition enable cycle time t cyce 500 ns figure 36 enable pulse width (high level) pw eh 230 enable rise/fall time t er , t ef 20 address set-up time (rs, r/w to e) t as 40 address hold time t ah 10 data set-up time t dsw 80 data hold time t h 10 bus read operation item symbol min typ max unit test condition enable cycle time t cyce 500 ns figure 37 enable pulse width (high level) pw eh 230 enable rise/fall time t er , t ef 20 address set-up time (rs, r/w to e) t as 40 address hold time t ah 10 data delay time t ddr 160 data hold time t dhr 5 hd66712 491
serial interface sequence item symbol min typ max unit test condition serial clock cycle time t scyc 0.5 20 s figure 38 serial clock (high level width) t sch 200 ns serial clock (low level width) t scl 200 serial clock rise/fall time t scr , t scf 50 chip select set-up time t csu 60 chip select hold time t ch 20 serial input data set-up time t sisu 100 serial input data hold time t sih 100 serial output data delay time t sod 160 serial output data hold time t soh 0 segment extension signal timing (v cc = 2.7 v to 5.5 v, t a = ?0 to +75? *3 ) item symbol min typ max unit test condition clock pulse width high level t cwh 800 ns figure 39 low level t cwl 800 clock set-up time t csu 500 data set-up time t su 300 data hold time t dh 300 m delay time t dm ?000 1000 clock rise/fall time t ct 100 reset timing (v cc = 2.7 v to 5.5 v, t a = ?0 to +75? *3 ) item symbol min typ max unit test condition reset low-level width t res 10 ms figure 40 power supply conditions using internal reset circuit item symbol min typ max unit test condition power supply rise time t rcc 0.1 10 ms figure 41 power supply off time t off 1 492 hd66712
electrical characteristics notes 1. all voltage values are referred to gnd = 0 v. if the lsi is used above the absolute maximum ratings, it may become permanently damaged. using the lsi within the following electrical characteristic is strongly recommended to ensure normal operation. if these electrical characteristic are also exceeded, the lsi may malfunction or exhibit poor reliability. 2. v cc 3 v 1 3 v 2 3 v 3 3 v 4 3 v 5 must be maintained. 3. for die products, specified up to 75?. 4. for die products, specified by the die shipment specification. 5. the following four circuits are i/o pin configurations except for liquid crystal display output. 6. applies to input pins and i/o pins, excluding the osc 1 pin. 7. applies to i/o pins. 8. applies to output pins. 9. current flowing through pull-up moss, excluding output drive moss. 10. input/output current is excluded. when input is at an intermediate level with cmos, the excessive current flows through the input circuit to the power supply. to avoid this from happening, the input level must be fixed high or low. hd66712 493 v cc pmos nmos v cc v cc pmos nmos (pull-up mos) pmos v cc pmos nmos v cc nmos nmos v cc pmos nmos (output circuit) (tristate) output enable data (pull-up mos) i/o pin pins: db /sod?b (mos with pull-up) 07 input pin pin: e/sclk, rs/cs * , rw/sid, im, ext, test (mos without pull-up) pins: reset * (mos with pull-up) output pin pins: cl , cl , m, d 12 v cc (input circuit) pmos pmos input enable
11. applies only to external clock operation. 12. applies only to the internal oscillator operation using oscillation resistor r f . 13. r com is the resistance between the power supply pins (v cc , v 1 , v 4 , v 5 ) and each common signal pin (com 0 to com 33 ). r seg is the resistance between the power supply pins (v cc , v 2 , v 3 , v 5 ) and each segment signal pin (seg 1 to seg 60 ). 494 hd66712 oscillator osc1 osc2 0.7 v 0.5 v 0.3 v cc cc cc th tl t rcp t fcp duty = 100% th th + tl open osc1 osc2 r f r : r : f f 75 k ?2% (when v = 3 v to 4 v) 91 k ?2% (when v = 4 v to 5 v) w w since the oscillation frequency varies depending on the osc1 and osc2 pin capacitance, the wiring length to these pins should be minimized. cc cc v cc = 5 v 500 400 300 270 200 100 50 100 150 91 r f (k w ) f osc (khz) typ. max. min. v cc = 3 v 500 400 300 270 200 100 50 100 150 r f (k w ) f osc (khz) typ. max. min. 75 referential data
14. the following graphs show the relationship between operation frequency and current consumption. 15. applies to the osc 1 pin. 16. each com and seg output voltage is within 0.15 v of the lcd voltage (v cc , v 1 , v 2 , v 3 , v 4 , v 5 ) when there is no load. 17. the test pin must be fixed to ground, and the im or ext pin must also be connected to v cc or ground. 18. booster characteristics test circuits are shown below. hd66712 495 1.8 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0.0 0 100 200 300 400 500 f osc or f cp (khz) i cc (ma) v cc = 5 v 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0.0 0 100 200 300 400 500 f osc or f cp (khz) i cc (ma) v cc = 3 v max. typ. max. (normal mode) typ. (normal mode) typ. (low power mode) gnd v cc 1 m f 1 m f vci c1 c2 v5out2 v5out3 + (boosting three times) + 1 m f + gnd v cc 1 m f vci c1 c2 v5out2 v5out3 (boosting twice) + 1 m f + rload rload i o i o
19. reference data the following graphs show the liquid crystal voltage booster characteristics. vup2 = v cc ?5out2 vup3 = v cc ?5out3 496 hd66712 2.0 3.0 4.0 5.0 11 10 9 8 7 6 5 4 boosting twice v ci (v) vup2 (v) test condition: v ci = v cc , f cp = 270 khz, t a = 25?, rload = 25 k w (1) vup2, vup3 vs v ci 2.0 3.0 4.0 5.0 15 14 13 12 11 10 9 8 7 6 boosting three times v ci (v) vup3 (v) test condition: v ci = v cc , f cp = 270 khz, ta = 25?, rload = 25 k w 0.0 0.5 1.0 1.5 9.0 8.5 8.0 7.5 7.0 6.5 6.0 boosting twice i o (ma) vup2 (v) test condition: v ci = v cc = 4.5 v, r f = 91 k w , t a = 25? (2) vup2, vup3 vs i o 2.0 test condition: v ci = v cc = 2.7 v, r f = 75 k w , t a = 25? 8.0 7.5 7.0 6.5 6.0 5.5 5.0 boosting three times i o (ma) vup3 (v) 0.0 0.5 1.0 1.5 2.0 boosting twice (3) vup2, vup3 vs t a 9.0 8.5 8.0 7.5 7.0 ?0 ?0 20 60 t a (?) test condition: v ci = v cc = 4.5 v, r f = 91 k w , i o = 0.25 ma 100 0 vup2 (v) typ. min. typ. min. typ. min. typ. min. 8.0 7.5 7.0 6.5 6.0 vup3 (v) boosting three times ?0 ?0 20 60 t a (?) test condition: v ci = v cc = 2.7 v, r f = 75 k w , i o = 0.25 ma 100 0 typ. typ.
20. must maintain (?igh? v cc 3 v ci (?ow?. hd66712 497 boosting twice (4) vup2, vup3 vs capacitance 9.0 8.5 8.0 7.5 7.0 0.5 1.0 c ( m f) test condition: v ci = v cc = 4.5 v, r f = 91 k w , i o = 0.25 ma 1.5 vup2 (v) typ. min. 9.0 8.5 8.0 7.5 7.0 vup2 (v) 0.5 1.0 test condition: v ci = v cc = 2.7 v, r f = 75 k w , i o = 0.25 ma 1.5 c ( m f) typ. min. boosting three times
load circuits ac characteristics test load circuits 498 hd66712 data bus: db0?b7, sod test point 50 pf segment extension signals: cl1, cl2, d, m 30 pf test point
timing characteristics figure 36 bus write operation figure 37 bus read operation hd66712 499 rs r/w e db0 to db7 v v ih1 il1 v v ih1 il1 t as t ah v il1 v il1 t ah pw eh t ef v v ih1 il1 v v ih1 il1 t er t dsw h t v v ih1 il1 v v ih1 il1 t cyce v il1 valid data rs r/ w e db0 to db7 v v ih1 il1 v v ih1 il1 t as t ah v ih1 v ih1 t ah pw eh t ef v v ih1 il1 v v ih1 il1 t ddr dhr t t er v il1 v v oh1 ol1 v v oh1 ol1 valid data t cyce
figure 38 serial interface timing figure 39 interface timing with extension driver 500 hd66712 cs * sclk sid sod t scyc t csu t sch t scr t scf t cwl t ch t sih t sisu t soh t sod v il1 v il1 v ih1 v il1 v il1 v ih1 v il1 v il1 v ih1 v ih1 v il1 v ih1 v il1 v oh1 v ol1 v oh1 v ol1 cl1 cl2 d m v oh2 v oh2 v ol2 t ct t cwh t cwh v oh2 t csu t cwl t ct t dh t su v ol2 t dm v v oh2 ol2 v ol2
figure 40 reset timing figure 41 power supply sequence hd66712 501 t res v il1 v il1 reset * note: when power is supplied, initializing by the internal reset circuit has priority. accordingly, the above reset * input is ignored during internal reset period. v cc 0.2 v 2.7 v/4.5 v * 2 0.2 v 0.2 v t rcc t off * 1 0.1 ms t 10 ms ? rcc t 1 ms off notes: 1. 2. 3. t off compensates for the power oscillation period caused by momentary power supply oscillations. specified at 4.5 v for 5-volt operation, and at 2.7 v for 3-volt operation. if the above electrical conditions are not satisfied, the internal reset circuit will not operate normally. in this case, initialized by instruction. (refer to the initializing by instruction section.)

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