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vishay siliconix dg9232, dg9233 document number: 70837 s11-0984?rev. f, 23-may-11 www.vishay.com 1 this document is subject to change without notice. the products described herein and this document ar e subject to specific disclaimers, set forth at www.vishay.com/doc?91000 low-voltage dual spst analog switch features ? low voltage operation (+ 2.7 v to + 5 v) ? low on-resistance - r ds (on): 20 ? ? fast switching - t on : 35 ns, t off : 20 ns ? low leakage - i com(on) : 200 pa max. ? low charge injection - q inj : 1 pc ? low power consumption ? ttl/cmos compatible ? esd protection > 2000 v (method 3015.7) ? available in msop-8 and soic-8 ? compliant to rohs directive 2002/95/ec applications ? battery operated systems ? portable test equipment ? sample and hold circuits ? cellular phones ? communication systems ? military radio ? pbx, pabx guidance and control systems description the dg9232, 9233 is a single-pole/single-throw monolithic cmos analog device designed for high performance switching of analog signals. combining low power, high speed (t on : 35 ns, t off : 20 ns), low on-resistance (r ds(on) : 20 ? ) and small physical size, the dg9232, 9233 is ideal for portable and battery powered applications requiring high performance and efficient use of board space. the dg9232, 9233 is built on vishay siliconix?s low voltage bcd-15 process. minimum esd protection, per method 3015.7 is 2000 v. an epitaxial layer prevents latchup. break-before -make is guaranteed for dg9232. 9233. each switch conducts equally well in both directions when on, and blocks up to the power supply level when off. benefits ? reduced power consumption ? simple logic interface ? high accuracy ? reduce board space functional block diagram and pin configuration logic "0" ?? 0.8 v logic "1" ?? 2.4 v logic "0" ?? 0.8 v logic "1" ?? 2.4 v * pb containing terminations are not rohs compliant, exemptions may apply nc 1 v+ com 1 in 1 in 2 com 2 gnd nc 2 1 2 3 4 8 7 6 5 top view no 1 v+ com 1 in 1 in 2 com 2 gnd no 2 1 2 3 4 8 7 6 5 top view truth table - dg9232 logic switch 0 on 1off truth table - dg9233 logic switch 0 off 1on ordering information temp range package part number - 40 c to 85 c soic-8 dg9232dy DG9232DY-E3 dg9232dy-t1 dg9232dy-t1-e3 dg9233dy dg9233dy-e3 dg9233dy-t1 dg9233dy-t1-e3 msop-8 dg9232dq-t1-e3 dg9233dq-t1-e3
www.vishay.com 2 document number: 70837 s11-0984?rev. f, 23-may-11 vishay siliconix dg9232, dg9233 this document is subject to change without notice. the products described herein and this document ar e subject to specific disclaimers, set forth at www.vishay.com/doc?91000 notes: a. signals on nc, no, or com or in exceeding v+ will be clamped by inte rnal diodes. limit forward diode current to maximum curr ent ratings. b. all leads welded or soldered to pc board. c. derate 6.5 mw/c above 70 c. notes: a. room = 25 c, full = as determined by the operating suffix. b. typical values are for design aid only, not guaranteed nor subject to production testing. c. the algebraic convention whereby the most negative value is a minimum and the most po sitive a maximum, is used in this datas heet. d. guarantee by design, nor s ubjected to production test. e. v in = input voltage to perform proper function. f. difference of min and max values. g. guaranteed by 5 v leakage tests, not production tested. absolute maximum ratings parameter limit unit reference v+ to gnd - 0.3 to + 13 v in, com, nc, no a - 0.3 to (v+ + 0.3) continuous current (any terminal) 20 ma peak current (pulsed at 1 ms, 10 % duty cycle) 40 esd (method 3015.7) > 2000 v storage temperature d suffix - 65 to 125 c power dissipation (packages) b 8-pin narrow body soic c 400 mw specifications (v+ = 3 v) parameter symbol test conditions otherwise unless specified v+ = 3 v, 10 %, v in = 0.8 v or 2.4 v e temp. a d suffix - 40 c to 85 c unit min. c typ. b max. c analog switch analog signal range d v analog full 0 3 v drain-source on-resistance r ds(on) v no or v nc = 1.5 v, v+ = 2.7 v i com = 5 ma room full 30 50 80 ? r ds(on) match d ? r ds(on) v no or v nc = 1.5 v room 0.4 2 r ds(on) flatness d r ds(on) flatness v no or v nc = 1 and 2 v room 4 8 no or nc off leakage current g i no/nc(off) v no or v nc = 1 v/2 v, v com = 2 v/1 v room full - 100 - 5000 5 100 5000 pa com off leakage current g i com(off) v com = 1 v/2 v, v no or v nc = 2 v/1 v room full - 100 - 5000 5 100 5000 channel-on leakage current g i com(on) v com = v no or v nc = 1 v/2 v room full - 200 - 10000 10 200 10000 digital control input current i inl or i inh full 1 a dynamic characteristics tu r n - o n t i m e t on v no or v nc = 1.5 v room full 50 120 200 ns tu r n - o f f t i m e t off room full 20 50 120 charge injection d q inj c l = 1 nf, v gen = 0 v, r gen = 0 ? room 1 5 pc off-isolation oirr r l = 50 ? , c l = 5 pf, f = 1 mhz room - 74 db crosstalk x ta l k room - 90 nc and no capacitance c s(off) f = 1 mhz room 7 pf channel-on capacitance c com(on) room 20 com-off capacitance c com(off) room 13 power supply positive supply range v+ 2.7 12 v power supply current i+ v+ = 3.3 v, v in = 0 or 3.3 v 1a
document number: 70837 s11-0984?rev. f, 23-may-11 www.vishay.com 3 vishay siliconix dg9232, dg9233 this document is subject to change without notice. the products described herein and this document ar e subject to specific disclaimers, set forth at www.vishay.com/doc?91000 notes: a. room = 25 c, full = as determined by the operating suffix. b. typical values are for design aid only, not guaranteed nor subject to production testing. c. the algebraic convention whereby the most negative value is a minimum and the most positive a maximum, is used in this datas heet. d. guarantee by design, nor subjected to production test. e. v in = input voltage to perform proper function. f. difference of min and max values. stresses beyond those listed under ?absolute maximum ratings? may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indi cated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended per iods may affect device reliability. specifications (v+ = 5 v) parameter symbol test conditions otherwise unless specified v+ = 5 v, 10 %, v in = 0.8 v or 2.4 v e temp. a d suffix - 40 c to 85c unit min. c typ. b max. c analog switch analog signal range d v analog full 0 5 v drain-source on-resistance r ds(on) v no or v nc = 3.5 v, v+ = 4.5 v i com = 5 ma room full 20 30 50 ? r ds(on) match d ? r ds(on) v no or v nc = 3.5 v room 0.4 2 r ds(on) flatness d r ds(on) flatness v no or v nc = 1, 2 and 3 v room 2 6 no or nc off leakage current g i no/nc(off) v no or v nc = 1 v/4 v, v com = 4 v/1 v room full - 100 - 5000 10 100 5000 pa com off leakage current i com(off) v com = 1 v/4 v, v no or v nc = 4 v/1 v room full - 100 - 5000 10 100 5000 channel-on leakage current i com(on) v com = v no or v nc = 1 v/4 v room full - 200 - 10000 200 10000 digital control input current i inl or i inh full 1 a dynamic characteristics tu r n - o n t i m e t on v no or v nc = 3.0 v room full 35 75 150 ns turn-off time t off room full 20 50 100 charge injection d q inj c l = 1 nf, v gen = 0 v, r gen = 0 ? room 2 5 pc off-isolation oirr r l = 50 ? , c l = 5 pf, f = 1 mhz room - 74 db crosstalk x ta l k room - 90 nc and no capacitance c (off) f = 1 mhz room 7 pf channel-on capacitance c d(on) room 20 com-off capacitance c d(off) room 13 power supply positive supply range v+ 2.7 12 v power supply current i+ v+ = 5.5 v, v in = 0 or 5.5 v 1a
www.vishay.com 4 document number: 70837 s11-0984?rev. f, 23-may-11 vishay siliconix dg9232, dg9233 this document is subject to change without notice. the products described herein and this document ar e subject to specific disclaimers, set forth at www.vishay.com/doc?91000 typical characteristics t a = 25 c, unless otherwise noted charge injection leakage current vs. temperature off-leakage vs. voltage at 25 c - 2.0 - 1.5 - 1.0 0.0 0.5 1.0 1.5 2.0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 v com q inj (pc) v+ = 3 v - 0.5 25 45 65 85 105 125 (a) i com(off) temperature (c) 10 na 1 na 100 pa 10 pa 1 pa 0.1 pa i com(on) i com(off) ?2.5 ?2.0 ?1.5 ?1.0 ?0.5 0.0 0.5 1.0 1.5 2.0 2.5 012345 v com v+ = 5 v i com i no/nc (pa) i off supply current vs. v in off-isolation vs. frequency r ds vs. v com - 500 0 500 1000 1500 2000 2500 3000 012345 v in v+ = 3 v v+ = 5 v i supply ( ? a) - 140 - 120 - 100 -80 -60 -40 frequency (hz) off-isolation (db) 0.1 m 1 m 10 m 0.01 m 0.001 m 12 15 18 21 24 27 30 012345 v+ = 3 v v+ = 5 v v com ( w ) r ds(on)
document number: 70837 s11-0984?rev. f, 23-may-11 www.vishay.com 5 vishay siliconix dg9232, dg9233 this document is subject to change without notice. the products described herein and this document ar e subject to specific disclaimers, set forth at www.vishay.com/doc?91000 typical characteristics t a = 25 c, unless otherwise noted r ds vs. v com t on/toff vs. power supply voltage v com 0 7 14 21 28 35 0.0 0.5 1.0 1.5 2.0 2.5 3.0 85 ? c 25 ? c 40 ? c ( ? ) r ds(on) 0 20 40 60 80 100 120 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 v+ t (ns) t on t off switching time vs. temperature input switching point vs. power supply voltage 0 10 20 30 40 50 60 70 - 60 - 30 0 30 60 90 120 / t on (ns) t off temperature (c) t off t on v+ = 3 v 0.50 0.75 1.00 1.25 1.50 1.75 2.00 2.25 23456 v+ v in (sw)
www.vishay.com 6 document number: 70837 s11-0984?rev. f, 23-may-11 vishay siliconix dg9232, dg9233 this document is subject to change without notice. the products described herein and this document ar e subject to specific disclaimers, set forth at www.vishay.com/doc?91000 test circuits figure 1. switching time switch input c l (includes fixture and stray capacitance) v+ in no or nc c l 35 pf com logic input r l 300 w v out gnd v+ 50 % 0 v 0 v logic input switch output t on t off logic "1" = switch on logic input waveforms inverted for switches that have the opposite logic sense. 0 v switch output v out =v com r l r l +r on + 3 v 0.9 x v out t r < 20 ns t f < 20 ns figure 2. break-before-make interval c l (includes fixture and stray capacitance) no or nc v 1 no or nc v 2 0 v 3 v 0 v logic input switch output v o v nc = v no t r < 5 ns t f < 5 ns 90 % t d t d com 1 v+ gnd v+ c l 35 pf r l 300 w com 2 figure 3. charge injection off on on in ? v out v out q = ? v out x c l c l com r gen v out nc or no 3 v in v gen gnd v+ v+ in depends on switch configuration: input polarity determined by sense of switch. +
document number: 70837 s11-0984?rev. f, 23-may-11 www.vishay.com 7 vishay siliconix dg9232, dg9233 this document is subject to change without notice. the products described herein and this document ar e subject to specific disclaimers, set forth at www.vishay.com/doc?91000 test circuits vishay siliconix maintains worldwide manufacturing capability. pro ducts may be manufactured at on e of several qualified locatio ns. reliability data for silicon tech- nology and package reliability represent a composite of all qua lified locations. for related documents such as package/tape dra wings, part marking, and reliability data, see http://www.vishay.com/ppg?70837 . figure 4. off-isolation in gnd nc or no 0 v, 2.4 v 10 nf com off isolation = 20 log v nc no v com r l analyzer v+ v+ com figure 5. channel off/on capacitance nc or no f = 1 mhz in com gnd 0 v, 2.4 v meter hp4192a impedance analyzer or equivalent 10 nf v+ v+
vishay siliconix package information document number: 71192 11-sep-06 www.vishay.com 1 dim millimeters inches min max min max a 1.35 1.75 0.053 0.069 a 1 0.10 0.20 0.004 0.008 b 0.35 0.51 0.014 0.020 c 0.19 0.25 0.0075 0.010 d 4.80 5.00 0.189 0.196 e 3.80 4.00 0.150 0.157 e 1.27 bsc 0.050 bsc h 5.80 6.20 0.228 0.244 h 0.25 0.50 0.010 0.020 l 0.50 0.93 0.020 0.037 q0808 s 0.44 0.64 0.018 0.026 ecn: c-06527-rev. i, 11-sep-06 dwg: 5498 4 3 1 2 5 6 8 7 h e h x 45 c all le a d s q 0.101 mm 0.004" l ba 1 a e d 0.25 mm (g a ge pl a ne) s oic (narrow): 8-lead jedec p a rt n u m b er: m s -012 s
notes: 1. die thickness allowable is 0.203 0.0127. 2. dimensioning and tolerances per ansi.y14.5m-1994. 3. dimensions ?d? and ?e 1 ? do not include mold flash or protrusions, and are measured at datum plane -h- , mold flash or protrusions shall not exceed 0.15 mm per side. 4. dimension is the length of terminal for soldering to a substrate. 5. terminal positions are shown for reference only. 6. formed leads shall be planar with respect to one another within 0.10 mm at seating plane. 7. the lead width dimension does not include dambar protrusion. allowable dambar protrusion shall be 0.08 mm total in excess of the lead width dimension at maximum material condition. dambar cannot be located on the lower radius or the lead foot. minimum space between protrusions and an adjacent lead to be 0.14 mm. see detail ?b? and section ?c-c?. 8. section ?c-c? to be determined at 0.10 mm to 0.25 mm from the lead tip. 9. controlling dimension: millimeters. 10. this part is compliant with jedec registration mo-187, variation aa and ba. 11. datums -a- and -b- to be determined datum plane -h- . 12. exposed pad area in bottom side is the same as teh leadframe pad size. 5 n n-1 a b c 0.20 (n/2) tips) 2x n/2 2 1 0.60 0.50 0.60 e top view e see detail ?b? -h- 3 d -a- seating plane a 1 a 6 c 0.10 side view 0.25 bsc 4 l -c- seating plane 0.07 r. min 2 places parting line detail ?a? (scale: 30/1) 0.48 max detail ?b? (scale: 30/1) dambar protrusion 7 c 0.08 m b s a s b b 1 with plating base metal c 1 c section ?c-c? scale: 100/1 (see note 8) see detail ?a? a 2 0.05 s c c ? 3 e 1 -b- end view e1 0.95 package information vishay siliconix document number: 71244 12-jul-02 www.vishay.com 1 msop: 8?leads jedec part number: mo-187, (variation aa and ba) n = 8l millimeters dim min nom max note a - - 1.10 a 1 0.05 0.10 0.15 a 2 0.75 0.85 0.95 b 0.25 - 0.38 8 b 1 0.25 0.30 0.33 8 c 0.13 - 0.23 c 1 0.13 0.15 0.18 d 3.00 bsc 3 e 4.90 bsc e 1 2.90 3.00 3.10 3 e 0.65 bsc e 1 1.95 bsc l 0.40 0.55 0.70 4 n 8 5 0 4 6 ecn: t-02080?rev. c, 15-jul-02 dwg: 5867
vishay siliconix trenchfet ? power mosfets application note 808 mounting little foot ? , so-8 power mosfets application note document number: 70740 www.vishay.com revision: 18-jun-07 1 wharton mcdaniel surface-mounted little foot power mosfets use integrated circuit and small-signal packages which have been been modified to provide the heat transfer capabilities required by power devices. leadframe materials and design, molding compounds, and die attach materials have been changed, while the footpr int of the packages remains the same. see application note 826, recommended minimum pad patterns with outline drawin g access for vishay siliconix mosfets, ( http://www.vishay.com/ppg?72286 ), for the basis of the pad design for a little foot so-8 power mosfet. in converting this recommended minimum pad to the pad set for a power mosfet, designers must make two connections: an electrical connection and a thermal connection, to draw heat away from the package. in the case of the so-8 p ackage, the thermal connections are very simple. pins 5, 6, 7, and 8 are the drain of the mosfet for a single mosfet package and are connected together. in a dual package, pi ns 5 and 6 are one drain, and pins 7 and 8 are the other drain. for a small-signal device or integrated circuit, typical co nnections would be made with traces that are 0.020 inches wi de. since the drain pins serve the additional function of providing the thermal connection to the package, this level of connection is inadequate. the total cross section of the copp er may be adequate to carry the current required for the a pplication, but it presents a large thermal impedance. also , heat spreads in a circular fashion from the heat source. in this case the drain pins are the heat sources wh en looking at heat spread on the pc board. figure 1. single mosfet so-8 pad pattern with copper spreading figure 2. dual mosfet so-8 pad pattern with copper spreading the minimum recommended pad patterns for the single-mosfet so-8 with copp er spreading (figure 1) and dual-mosfet so-8 with copper spreading (figure 2) show the starting point for utilizing th e board area available for the heat-spreading copper. to creat e this pattern, a plane of copper overlies the drain pins . the copper plane connects the drain pins electrically, but more importantly provides planar copper to draw heat fr om the drain leads and start the process of spreading the heat so it can be dissipated into the ambient air. these patterns use all the available area underneath the body for this purpose. since surface-mounted packag es are small, and reflow soldering is the most comm on way in which these are affixed to the pc board, ?t hermal? connections from the planar copper to the pads have not been used. even if additional planar copper area is used, there should be no problems in the soldering process. the actual solder connections are defined by the solder mask openings. by combining the basic footprint wi th the copper plane on the drain pins, the solder mask ge neration occurs automatically. a final item to keep in mind is the width of the power traces. the absolute minimum pow er trace width must be determined by the amount of current it has to carry. for thermal reasons, this minimum width should be at least 0.020 inches. the use of wide traces connected to the drain plane provides a low impedance path for heat to move away from the device. 0.027 0.69 0.07 8 1.9 8 0.2 5.07 0.196 5.0 0.2 88 7.3 0.050 1.27 0.027 0.69 0.07 8 1.9 8 0.2 5.07 0.0 88 2.25 0.2 88 7.3 0.050 1.27 0.0 88 2.25
application note 826 vishay siliconix www.vishay.com document number: 72606 22 revision: 21-jan-08 application note recommended minimum pads for so-8 0.246 (6.248) recommended mi nimum pads dimensions in inches/(mm) 0.172 (4.369) 0.152 (3.861) 0.047 (1.194) 0.028 (0.711) 0.050 (1.270) 0.022 (0.559) return to index return to index
legal disclaimer notice www.vishay.com vishay revision: 02-oct-12 1 document number: 91000 disclaimer all product, product specifications and data are subject to change without notice to improve reliability, function or design or otherwise. vishay intertechnology, inc., its affiliates, agents, and employee s, and all persons acting on it s or their behalf (collectivel y, vishay), disclaim any and all liability for any errors, inaccuracies or incompleteness contained in any datasheet or in any o ther disclosure relating to any product. vishay makes no warranty, repres entation or guarantee regarding the suitabilit y of the products for any particular purpose or the continuing production of any product. to the maximum extent permitted by applicable law, vi shay disclaims (i) any and all liability arising out of the application or use of any product, (ii) any and all liability, including without limitation specia l, consequential or incidental damages, and (iii) any and all i mplied warranties, including warra nties of fitness for particular purpose, non-infringement and merchantability. statements regarding the suitability of products for certain type s of applications are based on vishays knowledge of typical requirements that are often placed on vishay products in generic applications. such statements are not binding statements about the suitability of products for a particular application. it is the customers responsib ility to validate that a particu lar product with the properties descri bed in the product specification is suitable fo r use in a particular application. parameters provided in datasheets and/or specification s may vary in different applications an d performance may vary over time. all operating parameters, including typical pa rameters, must be validated for each customer application by the customers technical experts. product specifications do not expand or otherwise modify vish ays terms and condit ions of purchase, including but not limited to the warranty expressed therein. except as expressly indicate d in writing, vishay products are not designed for use in medical, life-saving, or life-sustaining applications or for any other application in which the failure of the vi shay product could result in personal injury or death. customers using or selling vishay products not expressly indicated for use in such applications do so at their own risk. pleas e contact authorized vishay personnel to ob tain written terms and conditions regarding products designed for such applications. no license, express or implied, by estoppel or otherwise, to any intellectual prope rty rights is granted by this document or by any conduct of vishay. product names and markings noted herein may be trad emarks of their respective owners. material category policy vishay intertechnology, inc. hereby certi fies that all its products that are id entified as rohs-compliant fulfill the definitions and restrictions defined under directive 2011/65/eu of the euro pean parliament and of the council of june 8, 2011 on the restriction of the use of certain hazardous substances in electrical and electronic equipment (eee) - recast, unless otherwis e specified as non-compliant. please note that some vishay documentation may still make reference to rohs directive 2002/95/ ec. we confirm that all the products identified as being compliant to directive 2002 /95/ec conform to directive 2011/65/eu. vishay intertechnology, inc. hereby certifi es that all its products that are identified as ha logen-free follow halogen-free requirements as per jedec js709a stan dards. please note that some vishay documentation may still make reference to the iec 61249-2-21 definition. we co nfirm that all the products identified as being compliant to iec 61249-2-21 conform to jedec js709a standards.

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