1518 doc #97030 data delay devices, inc. 1 2/7/97 3 mt. prospect ave. clifton, nj 07013 5-tap smd delay line t d /t r = 3 (series 1518) features packages 5 taps of equal delay increment delays to 200ns low profile epoxy encapsulated meets or exceeds mil-d-23859c functional description the 1518-series device is a fixed, single-input, five- output, passive delay line. the signal input (in) is reproduced at the outputs (t1-t5) in equal increments. the delay from in to t5 (t d ) and the characteristic impedance of the line (z) are determined by the dash number. the rise time (t r ) of the line is 30% of t d , and the 3db bandwidth is given by 1.05 / t d . the device is available in a 14-pin smd with two pinout options. part numbers are constructed according to the scheme shown at right. for example, 1518-101-500a is a 100ns, 50 w delay line with pinout code a. similarly, 1518-151- 501 a is 150ns, 500 w delay line with standard pinout. series specifications dielectric breakdown: 50 vdc distortion @ output: 10% max. operating temperature: -55 c to +125 c storage temperature: -55 c to +125 c temperature coefficient: 100 ppm/ c gnd in t5 t1 t2 t3 t4 gnd functional diagram package dimensions .290 1 7 8 14 .300 .100 .505 .018 .050 .425 .185 data delay devices, inc. 3 14 13 12 11 10 9 8 1 2 3 4 5 6 7 in n/c t2 n/c t4 t5 gnd n/c t1 n/c t3 n/c n/c n/c in signal input t1-t5 tap outputs gnd ground note: standard pinout shown alt. pinout available delay time expressed in nanoseconds ( ns) first two digits are significant figures last digit specifies # of zeros to follow impedance expressed in nanoseconds (ns) first two digits are significant figures last digit specifies # of zeros to follow pinout code see table omit for std pinout part number construction 1518 - xxx - zzz p delay specifications t d t i t r attenuation (%) typical ( ns) ( ns) ( ns) z=50 w w z=100 w w z=200 w w z=300 w w z=500 w w 5 1.0 3.0 n/a 5 n/a n/a n/a 10 2.0 4.0 3 5 5 n/a n/a 15 3.0 5.0 3 5 5 n/a n/a 20 4.0 6.0 3 5 5 5 n/a 25 5.0 7.0 3 5 5 5 7 30 6.0 10.0 3 5 5 5 7 40 8.0 13.0 3 5 5 5 7 50 10.0 15.0 3 5 5 7 7 60 12.0 20.0 3 5 6 7 8 75 15.0 25.0 3 5 6 7 8 80 16.0 26.0 4 5 6 7 8 100 20.0 30.0 4 5 6 7 8 110 22.0 32.0 4 5 6 7 8 125 25.0 40.0 4 5 6 7 8 150 30.0 50.0 n/a 5 8 10 10 180 36.0 60.0 n/a 7 8 10 10 200 50.0 70.0 n/a 8 10 12 12 notes: t i represents nominal tap-to-tap delay increment tolerance on t d = 5% or 2ns, whichever is greater tolerance on t i = 5% or 1ns, whichever is greater ?n/a? indicates that delay is not available at this z pinout codes code in t1 t2 t3 t4 t5 gnd std 1 13 3 11 5 6 7 a 1 12 4 10 6 7 8,14 1997 data delay devices
1518 doc #97030 data delay devices, inc. 2 2/7/97 tel: 973-773-2299 fax: 973-773-9672 http://www.datadelay.com passive delay line test specifications test conditions input: output: ambient temperature: 25 o c 3 o c r load : 10m w input pulse: high = 3.0v typical c load : 10pf low = 0.0v typical threshold: 50% (rising & falling) source impedance: 50 w max. rise/fall time: 3.0 ns max. (measured at 10% and 90% levels) pulse width (t d <= 75ns): pw in = 100ns period (t d <= 75ns): per in = 1000ns pulse width (t d > 75ns): pw in = 2 x t d period (t d > 75ns): per in = 10 x t d note: the above conditions are for test only and do not in any way restrict the operation of the device. timing diagram for testing t rise t fall per in pw in t rise t fall 10% 10% 50% 50% 90% 90% 50% 50% v ih v il v oh v ol input signal output signal t rise t fall 10% 10% 90% 90% in t1 out trig in trig test setup device under test (dut) oscilloscope pulse generator 50 w r out r in r in = r out = z line t2 t3 t4 t5
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