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freescale semiconductor data sheet: technical data document number: mpc5510 rev. 3, 3/2009 ? freescale semiconductor, inc., 2007-2009. all rights reserved. this document contains information on a prod uct under development. freescale reserves the right to change or discontinue this product without notice. mpc5510 tbd mapbga?225 15 mm x 15 mm qfn12 ##_mm_x_##mm sot-343r ##_mm_x_##mm pkg-tbd ## mm x ## mm mapbga?208 17 mm x 17 mm lqfp?144 20 mm x 20 mm lqfp?176 24 mm x 24 mm mpc5510 family features ? single issue, 32-bit cpu core complex (e200z1) ? compliant with the power architecture? embedded category ? includes an instruction set enhancement allowing variable length encoding (v le) for code size footprint reduction. with the optional encoding of mixed 16-bit and 32-bit instructions, it is possible to achieve significant code size footprint reduction. ? up to 1.5-mbyte on-chip flash with flash control unit (fcu) ? up to 80 kbytes on-chip sram ? memory protection unit (mpu) with up to sixteen region descriptors and 32-byte region granularity ? interrupt controller (i ntc) capable of handling selectable-priority interrupt sources ? frequency modulated phase-locked loop (fmpll) ? crossbar switch architecture for concurrent access to peripherals, flash, or ram from multiple bus masters ? 16-channel enhanced dir ect memory access controller (edma) ? boot assist module (bam) supports internal flash programming via a serial link (can or sci) ? timer supports input/output channels providing a range of 16-bit input capture, output compare, and pulse width modulation functions (emios200) ? up to 40-channel 12-bit anal og-to-digital converter (adc) ? up to four serial periphe ral interface (dspi) modules ? media local bus (mlb) emulation logic (works with two dspis, the e200z0, the edma , and system ram to create a 3-pin or 5-pin 256fs mlb protocol) ? up to eight serial communi cation interface (esci) modules ? up to six enhanced full can (flexcan) modules with configurable buffers ? one inter ic comm unication interface (i 2 c) module ? up to 144 configurable general purpose pins supporting input and output operations and 3.0v through 5.5v supply levels ? real-time counter (rtc_api) with clock source from external 32-khz crystal oscill ator, internal 32-khz or 16-mhz oscillator and supporting wake-up with selectable 1-second resolution and > 1-hour timeout, or 1-millisecond resolution with maximum timeout of one second ? up to eight periodic interrupt timers (pit) with 32-bit counter resolution ? nexus development inte rface (ndi) per ieee-isto 5001-2003 class two plus standard ? device/board test support per joint test action group (jtag) of ieee (ieee 1149.1) ? on-chip voltage regulator (vreg) for regulation of 5v input to 1.5v and 3.3v internal supply levels ? optional e200z0, second power architecture based i/o processor with vle instruction set ? optional flexray controller ? optional external bus interface (ebi) module mpc5510 microcontroller family data sheet
mpc5510 microcontroller family data sheet, rev. 3 freescale semiconductor 2 table of contents 1 pin assignments and reset states . . . . . . . . . . . . . . . . . . . . .4 1.1 signal properties and multiplexing summary . . . . . . . . .4 1.2 power and ground supply summary . . . . . . . . . . . . . .15 1.3 pinout ? 144 lqfp . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 1.4 pinout ? 176 lqfp . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 1.5 pinout ? 208 pbga. . . . . . . . . . . . . . . . . . . . . . . . . . . .19 2 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 2.1 maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 2.2 thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . .21 2.2.1 general notes for specifications at maximum junction temperature . . . . . . . . . . . . . . . . . . . .21 2.3 esd characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . .24 2.4 dc electrical specifications . . . . . . . . . . . . . . . . . . . . .25 2.5 operating current specifications . . . . . . . . . . . . . .27 2.6 i/o pad current specifications . . . . . . . . . . . . . . . . . . .29 2.7 low voltage characteristics . . . . . . . . . . . . . . . . . . . . .30 2.8 oscillators electrical characteristics. . . . . . . . . . . . . . .31 2.9 fmpll electrical characteristics . . . . . . . . . . . . . . . . .33 2.10 eqadc electrical characteristics . . . . . . . . . . . . . . . . .34 2.11 flash memory electrical characteristics. . . . . . . . . . . .35 2.12 pad ac specifications. . . . . . . . . . . . . . . . . . . . . . . . . .36 2.13 ac timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 2.13.1 reset and boot configuration pins . . . . . . . . . .37 2.13.2 external interrupt (irq) and non-maskable interrupt (nmi) pins . . . . . . . . . . . . . . . . . . . . .37 2.13.3 jtag (ieee 1149.1) interface . . . . . . . . . . . . . .38 2.13.4 nexus debug interface . . . . . . . . . . . . . . . . . . .41 2.13.5 external bus interface (ebi) . . . . . . . . . . . . . . .43 2.13.6 enhanced modular i/o subsystem (emios) . . .46 2.13.7 deserial serial peripheral interface (dspi) . . . .47 3 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52 4 product documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52 4.1 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53 list of tables table 1. mpc5510 signal properties . . . . . . . . . . . . . . . . . . . . . . .4 table 2. mpc5510 power/ground . . . . . . . . . . . . . . . . . . . . . . . .15 table 3. absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . .20 table 4. thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . .21 table 5. esd ratings, . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 table 6. dc electrical specifications. . . . . . . . . . . . . . . . . . . . . . .25 table 7. operating currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 table 8. i/o pad average dc current . . . . . . . . . . . . . . . . . . . . . .29 table 9. low voltage monitors . . . . . . . . . . . . . . . . . . . . . . . . . . .30 table 10. 3.3v high frequency external oscillator. . . . . . . . . . . .31 table 11. 5v low frequency (32 khz) external oscillator . . . . . .31 table 12. 5v high frequency (16 mhz) internal rc oscillator . . .32 table 13. 5v low frequency (32 khz) internal rc oscillator . . . 32 table 14. fmpll electrical specifications . . . . . . . . . . . . . . . . . 33 table 15. eqadc conversion specificat ions (operating) . . . . . . 34 table 16. flash program and erase specifications . . . . . . . . . . . 35 table 17. flash eeprom module life (full temperature range) 35 table 18. pad ac specifications (vdde = 3.0v - 5.5v) . . . . . . . 36 table 19. reset and boot configuration timing . . . . . . . . . . . . . 37 table 20. irq/nmi timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 table 21. jtag interface timing . . . . . . . . . . . . . . . . . . . . . . . . . 38 table 22. nexus debug port timing . . . . . . . . . . . . . . . . . . . . . . 41 table 23. external bus operation timing . . . . . . . . . . . . . . . . . . 43 table 24. emios timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 table 25. dspi timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 table 26. package information . . . . . . . . . . . . . . . . . . . . . . . . . . 52 table 27. revision history of mpc5510 data sheet . . . . . . . . . . 53 list of figures figure 1. mpc5510 family block diagram . . . . . . . . . . . . . . . . . . 3 figure 2. mpc5510 pinout ? 144 lqfp . . . . . . . . . . . . . . . . . . . 17 figure 3. mpc5510 pinout ? 176 lqfp . . . . . . . . . . . . . . . . . . . 18 figure 4. mpc5510 pinout ? 208 pbga . . . . . . . . . . . . . . . . . . . 19 figure 5. pad output delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 figure 6. reset and boot configuration timing. . . . . . . . . . . . . . 37 figure 7. irq and nmi timing. . . . . . . . . . . . . . . . . . . . . . . . . . . 37 figure 8. jtag test clock input timing. . . . . . . . . . . . . . . . . . . . 38 figure 9. jtag test access port timing . . . . . . . . . . . . . . . . . . . 39 figure 10. jtag jcomp timing . . . . . . . . . . . . . . . . . . . . . . . . . 39 figure 11. jtag boundary scan timing . . . . . . . . . . . . . . . . . . . 40 figure 12. nexus output timing . . . . . . . . . . . . . . . . . . . . . . . . . 41 figure 13. nexus tdi, tms, tdo timing . . . . . . . . . . . . . . . . . . 42 figure 14. clkout timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 figure 15. synchronous output timing . . . . . . . . . . . . . . . . . . . . 44 figure 16. synchronous input timing . . . . . . . . . . . . . . . . . . . . . 45 figure 17. address latch enable (ale) timing . . . . . . . . . . . . . 46 figure 18. dspi classic spi timing ? master, cpha = 0 . . . . . 48 figure 19. dspi classic spi timing ? master, cpha = 1 . . . . . 48 figure 20. dspi classic spi timing ? slave, cpha = 0 . . . . . . 49 figure 21. dspi classic spi timing ? slave, cpha = 1 . . . . . . 49 figure 22. dspi modified transfer format timing ? master, cpha = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 figure 23. dspi modified transfer format timing ? master, cpha = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 figure 24. dspi modified transfer format timing ? slave, cpha = 0 51 figure 25. dspi modified transfer format timing ? slave, cpha = 1 51 figure 26. dspi pcs strobe (pcss) timing . . . . . . . . . . . . . . . 51
mpc5510 microcontroller family data sheet, rev. 3 freescale semiconductor 3 figure 1. mpc5510 family block diagram e200z1 core legend esci data bus instruction bus private instruction bus oscillators vreg adc e200z0 core emios200 dspi i 2 c siu flexcan bam pit adc ? analog to digital converter modules bam ? boot assist module ebi ? external bus interface module ecc ? error correction code dspi ? serial peripherals interface controller module edma ? enhanced direct memory controller module emios200 ? timed input output module esci ? serial communications interface modules fcu ? flash controller unit flexcan ? controller area network controller modules flexray ? dual channel flexray controller fmpll ? frequency modulated phase locked loop module i 2 c ? inter ic controller modules intc ? interrupt controller module jtag ? joint test action group interface mlb ? media local bus emulation logic ndi ? nexus debug interface module pit ? periodic interrupt timer module siu ? system integration module vreg ? voltage regulator mpc5510 integer execution unit instruction unit ppc & vle multiply unit general purpose registers (32 x 32-bit) timers branch unit load/store unit jtag ndi intc flexray general purpose registers (32 x 32-bit) integer execution unit instruction unit vle branch unit load/store unit multiply unit crossbar switch (xbar) memory protection unit (mpu) fcu flash (ecc) sram (ecc) ebi ram controller peripheral bridge fmpll edma mlb
mpc5510 microcontroller family data sheet, rev. 3 pin assignments and reset states freescale semiconductor 4 1 pin assignments and reset states 1.1 signal properties and multiplexing summary table 1 shows the signal properties for each pin on the mpc5510. fo r all port pins, which have an associated pad configuration register (siu_pcr n register) to control its pin properties, the ?supported pin functions? column lists the functions associated with the programming of the siu_pcr n [pa] bit field in the following order: gpio, function1, function2 and function3. if fewer than three functions plus gpio are supported by a given pin, then the unused functions begin with function3, then function2, then function1. note that the gpio number is the same number as the corresponding pad configuration register (siu_pcr n ) number. table 1. mpc5510 signal properties pin name gpio (pcr) num 1 supported functions 2 description i/o type voltage 3 pad 4 type status during reset 5 status after reset 5 package pin locations 144 176 208 port a (16) pa 0 0 pa 0 an0 gpi eqadc analog input i i v dda ae + ih ? ? 9 9 e3 pa 1 1 pa 1 an1 gpi eqadc analog input i i v dda ae + ih ? ? 8 8 e2 pa 2 2 pa 2 an2 gpi eqadc analog input i i v dda ae + ih ? ? 7 7 e1 pa 3 3 pa 3 an3 gpi eqadc analog input i i v dda ae + ih ? ? 6 6 d3 pa 4 4 pa 4 an4 gpi eqadc analog input i i v dda ae + ih ? ? 5 5 d2 pa 5 5 pa 5 an5 gpi eqadc analog input i i v dda ae + ih ? ? 4 4 d1 pa 6 6 pa 6 an6 gpi eqadc analog input i i v dda ae + ih ? ? 3 3 c2 pa 7 7 pa 7 an7 gpi eqadc analog input i i v dda ae + ih ? ? 2 2 c1 pa 8 8 pa 8 an8/anw gpi eqadc analog input i i v dda ae + ih ? ? 143 175 a3 pa 9 9 pa 9 an9/anx gpi eqadc analog input i i v dda ae + ih ? ? 142 174 c4 pa 1 0 1 0 pa 1 0 an10/any gpi eqadc analog input i i v dda ae + ih ? ? 140 172 d5 pa 1 1 1 1 pa 1 1 an11/anz gpi eqadc analog input i i v dda ae + ih ? ? 139 171 c5 pa 1 2 1 2 pa 1 2 an12 gpi eqadc analog input i i v dda ae + ih ? ? 138 170 b5 pa 1 3 1 3 pa 1 3 an13 gpi eqadc analog input i i v dda ae + ih ? ? 137 169 a5 pa 1 4 1 4 pa 1 4 an14 extal32 6 gpi eqadc analog input 32 khz crystal oscillator input i i i v dda ae + ih ? ? 136 167 d6
pin assignments and reset states mpc5510 microcontroller family data sheet, rev. 3 freescale semiconductor 5 pa 1 5 1 5 pa 1 5 an15 xtal32 6 gpi eqadc analog input 32 khz crystal oscillator output i i o v dda ae + ih ? ? 135 165 c6 port b (16) pb0 16 pb0 an28 emios16 pcs_c5 gpio eqadc analog input 7 emios channel dspi_c peripheral chip select i/o i o o v dde1 a + sh ? ? 134 162 c7 pb1 17 pb1 an29 emios17 pcs_c4 gpio eqadc analog input 7 emios channel dspi_c peripheral chip select i/o i o o v dde1 a + sh ? ? 133 161 d7 pb2 18 pb2 an30 emios18 pcs_c3 gpio eqadc analog input 7 emios channel dspi_c peripheral chip select i/o i o o v dde1 a + sh ? ? 132 160 a8 pb3 19 pb3 an31 pcs_c2 gpio eqadc analog input 7 dspi_c peripheral chip select i/o i o v dde1 a + sh ? ? 131 159 b8 pb4 20 pb4 an32 pcs_c1 gpio eqadc analog input 7 dspi_c peripheral chip select i/o i o v dde1 a + sh ? ? 130 158 c8 pb5 21 pb5 an33 pcs_c0 gpio eqadc analog input 7 dspi_c peripheral chip select i/o i i/o v dde1 a + sh ? ? 129 157 d8 pb6 22 pb6 an34 sck_c gpio eqadc analog input 7 dspi_c clock i/o i i/o v dde1 a + sh ? ? 128 156 a9 pb7 23 pb7 an35 sout_c gpio eqadc analog input 7 dspi_c data output i/o i o v dde1 a + sh ? ? 127 153 b9 pb8 24 pb8 an36 sin_c gpio eqadc analog input 7 dspi_c data input i/o i i v dde1 a + sh ? ? 126 152 c9 pb9 25 pb9 an37 cntx_d pcs_b4 gpio eqadc analog input 7 can_d transmit dspi_b peripheral chip select i/o i o o v dde1 a + sh ? ? 125 151 d9 pb10 26 pb10 an38 cnrx_d pcs_b3 gpio eqadc analog input 7 can_d receive dspi_b peripheral chip select i/o i i o v dde1 a + sh ? ? 124 150 a10 pb11 27 pb11 an39 emios19 pcs_b5 gpio eqadc analog input 7 emios channel dspi_b peripheral chip select i/o i o o v dde1 a + sh ? ? 123 149 b10 table 1. mpc5510 signal properties (continued) pin name gpio (pcr) num 1 supported functions 2 description i/o type voltage 3 pad 4 type status during reset 5 status after reset 5 package pin locations 144 176 208
mpc5510 microcontroller family data sheet, rev. 3 pin assignments and reset states freescale semiconductor 6 pb12 28 pb12 txd_g pcs_b4 gpio sci_g transmit dspi_b peripheral chip select i/o o o v dde1 sh ? ? ? 164 a7 pb13 29 pb13 rxd_g pcs_b3 gpio sci_g receive dspi_b peripheral chip select i/o i o v dde1 sh ? ? ? 163 b7 pb14 30 pb14 txd_h gpio sci_h transmit i/o o v dde1 sh ? ? ? 148 c10 pb15 31 pb15 rxd_h gpio sci_h receive i/o i v dde1 sh ? ? ? 147 a11 port c (16) pc0 32 pc0 emios0 fr_a_tx_en ad24 gpio emios channel flexray channel a transmit enable ebi muxed address/data i/o i/o o i/o v dde1 mh ? ? 122 146 b11 pc1 33 pc1 emios1 fr_a_tx ad16 gpio emios channel flexray channel a transmit ebi muxed address/data i/o i/o o i/o v dde1 mh ? ? 121 145 c11 pc2 34 pc2 emios2 fr_a_rx ts gpio emios channel flexray channel a receive ebi transfer start i/o i/o i i/o v dde1 mh ? ? 120 144 d11 pc3 35 pc3 emios3 fr_dbg0 gpio emios channel flexray debug i/o i/o o v dde1 mh ? ? 117 141 a12 pc4 36 pc4 emios4 fr_dbg1 gpio emios channel flexray debug i/o i/o o v dde1 sh ? ? 116 140 b12 pc5 37 pc5 emios5 fr_dbg2 gpio emios channel flexray debug i/o i/o o v dde1 sh ? ? 115 139 c12 pc6 38 pc6 emios6 fr_dbg3 gpio emios channel flexray debug i/o i/o o v dde1 sh ? ? 114 138 d12 pc7 39 pc7 emios7 fr_b_rx gpio emios channel flexray channel b receive i/o i/o i v dde1 sh ? ? 113 137 a13 pc8 40 pc8 emios8 fr_b_tx ad15 gpio emios channel flexray channel b transmit ebi muxed address/data i/o i/o o i/o v dde1 mh ? ? 112 136 b13 pc9 41 pc9 emios9 fr_b_tx_en ad14 gpio emios channel flexray channel b transmit enable ebi muxed address/data i/o i/o o i/o v dde1 mh ? ? 111 135 c13 table 1. mpc5510 signal properties (continued) pin name gpio (pcr) num 1 supported functions 2 description i/o type voltage 3 pad 4 type status during reset 5 status after reset 5 package pin locations 144 176 208
pin assignments and reset states mpc5510 microcontroller family data sheet, rev. 3 freescale semiconductor 7 pc10 42 pc10 emios10 pcs_c5 sck_d gpio emios channel dspi_c peripheral chip select dspi_d clock i/o i/o o i/o v dde1 sh ? ? 110 134 a14 pc11 43 pc11 emios11 pcs_c4 sout_d gpio emios channel dspi_c peripheral chip select dspi_d serial out i/o i/o o o v dde1 sh ? ? 109 133 b14 pc12 44 pc12 emios12 psc_c3 sin_d gpio emios channel dspi_c peripheral chip select dspi_d serial in i/o i/o o i v dde1 sh ? ? 108 132 b16 pc13 45 pc13 emios13 pcs_a5 pcs_d0 gpio emios channel dspi_a peripheral chip select dspi_d peripheral chip select i/o i/o o o v dde1 sh ? ? 107 131 c15 pc14 46 pc14 emios14 pcs_a4 pcs_d1 gpio emios channel dspi_a peripheral chip select dspi_d peripheral chip select i/o i/o o o v dde1 sh ? ? 106 130 c16 pc15 47 pc15 emios15 pcs_a3 pcs_d2 gpio emios channel dspi_a peripheral chip select dspi_d peripheral chip select i/o i/o o o v dde1 sh ? ? 105 129 d14 port d (16) pd0 48 pd0 cntx_a pcs_d3 gpio can_a transmit dspi_d peripheral chip select i/o o o v dde1 sh ? ? 104 128 d15 pd1 49 pd1 cnrx_a pcs_d4 gpio can_a receive dspi_d peripheral chip select i/o i o v dde1 sh ? ? 103 127 d16 pd2 50 pd2 cnrx_b emios10 bootcfg pcs_d5 gpio can_b receive emios channel boot configuration dspi_d peripheral chip select i/o i o i o v dde1 sh bootcfg (pulldown) gpi (pulldown) 102 126 e14 pd3 51 pd3 cntx_b emios11 gpio can_b transmit emios channel i/o o o v dde1 sh ? ? 101 125 e15 pd4 52 pd4 cntx_c emios12 gpio can_c transmit emios channel i/o o o v dde1 sh ? ? 100 124 e16 pd5 53 pd5 cnrx_c emios13 gpio can_c receive emios channel i/o i o v dde1 sh ? ? 99 123 f13 table 1. mpc5510 signal properties (continued) pin name gpio (pcr) num 1 supported functions 2 description i/o type voltage 3 pad 4 type status during reset 5 status after reset 5 package pin locations 144 176 208
mpc5510 microcontroller family data sheet, rev. 3 pin assignments and reset states freescale semiconductor 8 pd6 54 pd6 txd_a emios14 gpio sci_a transmit emios channel i/o o o v dde1 sh ? ? 98 122 f14 pd7 55 pd7 rxd_a emios15 gpio sci_a receive emios channel i/o i o v dde1 sh ? ? 97 121 f15 pd8 56 pd8 txd_b scl_a gpio sci_b transmit i 2 c serial clock line i/o o i/o v dde1 sh ? ? 94 118 g13 pd9 57 pd9 rxd_b sda_a gpio sci_b receive i 2 c serial data line i/o i i/o v dde1 sh ? ? 93 117 f16 pd10 58 pd10 pcs_b2 cntx_f nmi0 gpio dspi_b peripheral chip select can_f transmit nmi input for z1 core i/o o o i v dde1 sh ? ? 92 116 g14 pd11 59 pd11 pcs_b1 cnrx_f nmi1 gpio dspi_b peripheral chip select can_f receive nmi input for z0 core i/o o i i v dde1 sh ? ? 91 115 g15 pd12 60 pd12 pcs_b0 emios9 gpio dspi_b peripheral chip select emios channel i/o i/o o v dde1 sh ? ? 90 114 h14 pd13 61 pd13 sck_b emios8 gpio dspi_b clock emios channel i/o i/o o v dde1 sh ? ? 89 113 h15 pd14 62 pd14 sout_b emios7 gpio dspi_b data output emios channel i/o o o v dde1 sh ? ? 88 110 j14 pd15 63 pd15 sin_b emios6 gpio dspi_b data input emios channel i/o i o v dde1 sh ? ? 87 107 k14 port e (16) pe0 64 pe0 pcs_a2 emios5 mlbclk gpio dspi_a peripheral chip select emios channel mlb clock i/o o o i v dde1 sh ? ? 86 106 k16 pe1 65 pe1 pcs_a1 emios4 mlbsi / mlbsig gpio dspi_a peripheral chip select emios channel mlb signal in (5-pin) / mlb bi-directional signal (3-pin) i/o o o i i/o v dde1 mh ? ? 85 103 l14 pe2 66 pe2 pcs_a0 emios3 mlbdi / mlbdat gpio dspi_a peripheral chip select emios channel mlb data in (5-pin) / mlb bi-directional data (3-pin) i/o i/o o i i/o v dde1 mh ? ? 84 101 l15 table 1. mpc5510 signal properties (continued) pin name gpio (pcr) num 1 supported functions 2 description i/o type voltage 3 pad 4 type status during reset 5 status after reset 5 package pin locations 144 176 208
pin assignments and reset states mpc5510 microcontroller family data sheet, rev. 3 freescale semiconductor 9 pe3 67 pe3 sck_a emios2 mlbso / mlbsig_bufen gpio dspi_a clock emios channel mlb signal out (5-pin) / mlb signal level shifter enable (3-pin) i/o i/o o o o v dde1 mh ? ? 83 100 m13 pe4 68 pe4 sout_a emios1 mlbdo / mlbdat_bufen gpio dspi_a data out emios channel mlb data out (5-pin) / mlb data level shifter enable (3-pin) i/o o o o o v dde1 mh ? ? 82 98 n14 pe5 69 pe5 sin_a emios0 mlb_slot / mlb_sigobs / mlb_datobs gpio dspi_a data in emios channel mlb slot debug / mlb clock adjust observe signal / mlb clock adjust observe data i/o i o o o o v dde1 mh ? ? 81 97 m15 pe6 70 pe6 clkout gpio system clock output i/o o v dde3 mh ? ? 67 83 p13 pe7 71 pe7 gpio i/o v dde1 sh ? ? ? ? h13 pe8 72 pe8 gpio i/o v dde1 sh ? ? ? ? h16 pe9 72 pe9 gpio i/o v dde1 sh ? ? ? ? j13 pe10 74 pe10 gpio i/o v dde1 sh ? ? ? 112 j16 pe11 75 pe11 gpio i/o v dde1 sh ? ? ? 111 j15 pe12 76 pe12 gpio i/o v dde1 sh ? ? ? 109 k13 pe13 77 pe13 gpio i/o v dde1 sh ? ? ? 108 l13 pe14 78 pe14 gpio i/o v dde1 sh ? ? ? 102 l16 pe15 79 pe15 gpio i/o v dde1 sh ? ? ? 99 m14 port f (16) pf0 80 pf0 rd_wr evti 8 gpio ebi read/write nexus event in i/o i/o i v dde3 mh ? ? 66 82 n12 pf1 81 pf1 t a mlbclk evto 8 gpio ebi transfer acknowledge mlb clock nexus event out i/o i/o i o v dde3 mh ? ? 65 81 p12 pf2 82 pf2 ad8 addr8 mlbsi / mlbsig mseo 8 gpio ebi muxed address/data ebi non muxed address mlb signal in (5-pin) / mlb bi-directional signal (3-pin) nexus message start/end out i/o i/o o i i/o o v dde3 mh ? ? 64 80 r12 table 1. mpc5510 signal properties (continued) pin name gpio (pcr) num 1 supported functions 2 description i/o type voltage 3 pad 4 type status during reset 5 status after reset 5 package pin locations 144 176 208
mpc5510 microcontroller family data sheet, rev. 3 pin assignments and reset states freescale semiconductor 10 pf3 83 pf3 ad9 addr9 mlbdi / mlbdat mcko 8 gpio ebi muxed address/data ebi non muxed address mlb data in (5-pin) / mlb bi-directional data (3-pin) nexus message clock out i/o i/o o i i/o o v dde3 mh ? ? 63 79 t12 pf4 84 pf4 ad10 addr10 mlbso / mlbsig_bufen mdo0 8 gpio ebi muxed address/data ebi non muxed address mlb signal out (5-pin) / mlb signal level shifter enable (3-pin) nexus message data out i/o i/o o o o o v dde3 mh ? ? 59 74 t10 pf5 85 pf5 ad11 addr11 mlbdo / mlbdat_bufen mdo1 8 gpio ebi muxed address/data ebi non muxed address mlb data out (5-pin) / mlb data level shifter enable (3-pin) nexus message data out i/o i/o o o o o v dde3 mh ? ? 58 72 r9 pf6 86 pf6 ad12 addr12 mlb_slot / mlb_sigobs / mlb_datobs mdo2 8 gpio ebi muxed address/data ebi non muxed address mlb slot debug / mlb clock adjust observe signal / mlb clock adjust observe data nexus message data out i/o i/o o o o o o v dde3 mh ? ? 57 68 t8 pf7 87 pf7 ad13 addr13 mdo3 8 gpio ebi muxed address/data ebi non muxed address nexus message data out i/o i/o o o v dde3 mh ? ? 56 66 p8 pf8 88 pf8 ad14 addr14 mdo4 8 gpio ebi muxed address/data ebi non muxed address nexus message data out i/o i/o o o v dde2 mh ? ? 55 65 n8 pf9 89 pf9 ad15 addr15 mdo5 8 gpio ebi muxed address/data ebi non muxed address nexus message data out i/o i/o o o v dde2 mh ? ? 54 64 t7 pf10 90 pf10 cs 1 txd_c mdo6 8 gpio ebi chip select sci_c transmit nexus message data out i/o o o o v dde2 mh ? ? 52 62 r7 pf11 91 pf11 cs 0 rxd_c mdo7 8 gpio ebi chip select sci_c receive nexus message data out i/o o i o v dde2 mh ? ? 51 61 p7 pf12 92 pf12 ts txd_d ale gpio ebi transfer start sci_d transmit ebi address latch enable i/o i/o o o v dde2 mh ? ? 50 60 n7 table 1. mpc5510 signal properties (continued) pin name gpio (pcr) num 1 supported functions 2 description i/o type voltage 3 pad 4 type status during reset 5 status after reset 5 package pin locations 144 176 208
pin assignments and reset states mpc5510 microcontroller family data sheet, rev. 3 freescale semiconductor 11 pf13 93 pf13 oe rxd_d gpio ebi output enable sci_d receive i/o o i v dde2 mh ? ? 49 59 r6 pf14 94 pf14 we0 bdip cntx_d gpio ebi write enable ebi burst data in progress can_d transmit i/o o o o v dde2 mh ? ? 45 55 p6 pf15 95 pf15 we1 tea cnrx_d gpio ebi write enable ebi transfer error acknowledge can_d receive i/o o i/o i v dde2 mh ? ? 44 54 n6 port g (16) pg0 96 pg0 ad16 emios16 gpio ebi muxed address/data emios channel i/o i/o i/o v dde2 mh ? ? 43 51 p5 pg1 97 pg1 ad17 emios17 sin_c gpio ebi muxed address/data emios channel dspi_c serial in i/o i/o i/o i v dde2 mh ? ? 42 50 t4 pg2 98 pg2 ad18 emios18 sout_c gpio ebi muxed address/data emios channel dspi_c serial out i/o i/o i/o o v dde2 mh ? ? 41 49 r4 pg3 99 pg3 ad19 emios19 sck_c gpio ebi muxed address/data emios channel dspi_c serial clock i/o i/o i/o i/o v dde2 mh ? ? 40 48 p4 pg4 100 pg4 ad20 emios20 pcs_c0 gpio ebi muxed address/data emios channel dspi_c peripheral chip select i/o i/o i/o i/o v dde2 mh ? ? 39 47 t3 pg5 101 pg5 ad21 emios21 gpio ebi muxed address/data emios channel i/o i/o i/o v dde2 mh ? ? 38 46 r3 pg6 102 pg6 ad22 emios22 gpio ebi muxed address/data emios channel i/o i/o i/o v dde2 mh ? ? 37 45 t2 pg7 103 pg7 ad23 emios23 rxd_c gpio ebi muxed address/data emios channel sci_c receive i/o i/o i/o i v dde2 mh ? ? 36 44 r1 pg8 104 pg8 ad24 pcs_a4 gpio ebi muxed address/data dspi_a peripheral chip select i/o i/o o v dde2 mh ? ? 35 43 p2 table 1. mpc5510 signal properties (continued) pin name gpio (pcr) num 1 supported functions 2 description i/o type voltage 3 pad 4 type status during reset 5 status after reset 5 package pin locations 144 176 208
mpc5510 microcontroller family data sheet, rev. 3 pin assignments and reset states freescale semiconductor 12 pg9 105 pg9 ad25 pcs_a3 txd_c gpio ebi muxed address/data dspi_a peripheral chip select sci_c transmit i/o i/o o o v dde2 mh ? ? 34 42 n3 pg10 106 pg10 ad26 pcs_a2 gpio ebi muxed address/data dspi_a peripheral chip select i/o i/o o v dde2 mh ? ? 30 38 n2 pg11 107 pg11 ad27 pcs_a1 gpio ebi muxed address/data dspi_a peripheral chip select i/o i/o o v dde2 mh ? ? 29 37 n1 pg12 108 pg12 ad28 pcs_a0 gpio ebi muxed address/data dspi_a peripheral chip select i/o i/o i/o v dde2 mh ? ? 28 36 m4 pg13 109 pg13 ad29 sck_a gpio ebi muxed address/data dspi_a clock i/o i/o i/o v dde2 mh ? ? 27 35 m3 pg14 110 pg14 ad30 sout_a gpio ebi muxed address/data dspi_a data out i/o i/o o v dde2 mh ? ? 26 34 m2 pg15 111 pg15 ad31 sin_a gpio ebi muxed address/data dspi_a data in i/o i/o i v dde2 mh ? ? 25 33 m1 port h (16) ph0 112 ph0 an27 emios20 scl_a gpio eqadc analog input 7 emios channel i 2 c_a serial clock i/o i o i/o v dde2 a + sh ? ? 24 32 l3 ph1 113 ph1 an26 emios21 sda_a gpio eqadc analog input 7 emios channel i 2 c_a serial data i/o i o i/o v dde2 a + sh ? ? 23 31 l2 ph2 114 ph2 an25 emios22 cs3 gpio eqadc analog input 7 emios channel ebi chip select i/o i o o v dde2 a + mh ? ? 22 30 l1 ph3 115 ph3 an24 emios23 cs2 gpio eqadc analog input 7 emios channel ebi chip select i/o i o o v dde2 a + mh ? ? 21 29 k4 ph4 116 ph4 an23 txd_e ma2 gpio eqadc analog input 7 sci_e transmit eqadc external mux address i/o i o o v dde2 a + sh ? ? 20 28 k3 ph5 117 ph5 an22 rxd_e ma1 gpio eqadc analog input 7 sci_e receive eqadc external mux address i/o i i o v dde2 a + sh ? ? 19 24 j3 table 1. mpc5510 signal properties (continued) pin name gpio (pcr) num 1 supported functions 2 description i/o type voltage 3 pad 4 type status during reset 5 status after reset 5 package pin locations 144 176 208
pin assignments and reset states mpc5510 microcontroller family data sheet, rev. 3 freescale semiconductor 13 ph6 118 ph6 an21 txd_f gpio eqadc analog input 7 sci_f transmit i/o i o v dde2 a + sh ? ? 18 23 j2 ph7 119 ph7 an20 rxd_f gpio eqadc analog input 7 sci_f receive i/o i i v dde2 a + sh ? ? 17 22 j1 ph8 120 ph8 an19 cntx_e ma0 gpio eqadc analog input 7 can_e transmit eqadc external mux address i/o i o o v dde2 a + sh ? ? 14 17 h1 ph9 121 ph9 an18/ant cnrx_e gpio eqadc analog input 7 can_e receive i/o i i v dde2 a + sh ? ? 13 14 g2 ph10 122 ph10 an17/ans cnrx_f gpio eqadc analog input 7 can_f receive i/o i i v dde2 a + sh ? ? 12 12 f4 ph11 123 ph11 an16/anr cntx_f gpio eqadc analog input 7 can_f transmit i/o i o v dde2 a + sh ? ? 11 11 f3 ph12 124 ph12 pcs_d5 gpio dspi_d peripheral chip select i/o o v dde2 sh ? ? ? ? f2 ph13 125 ph13 gpio i/o v dde2 sh ? ? ? ? f1 ph14 126 ph14 we2 gpio ebi write enable i/o o v dde2 mh ? ? ? 53 t5 ph15 127 ph15 we3 gpio ebi write enable i/o o v dde2 mh ? ? ? 52 r5 port j (16) pj0 128 pj0 ad0 gpio ebi muxed address/data i/o i/o v dde3 mh ? ? ? ? n11 pj1 129 pj1 ad1 gpio ebi muxed address/data i/o i/o v dde3 mh ? ? ? ? p11 pj2 130 pj2 ad2 gpio ebi muxed address/data i/o i/o v dde3 mh ? ? ? ? n10 pj3 131 pj3 ad3 gpio ebi muxed address/data i/o i/o v dde3 mh ? ? ? ? r10 pj4 132 pj4 ad4 gpio ebi muxed address/data i/o i/o v dde3 mh ? ? ? 75 p10 pj5 133 pj5 ad5 gpio ebi muxed address/data i/o i/o v dde3 mh ? ? ? 73 t9 pj6 134 pj6 ad6 gpio ebi muxed address/data i/o i/o v dde3 mh ? ? ? 69 p9 pj7 135 pj7 ad7 gpio ebi muxed address/data i/o i/o v dde3 mh ? ? ? 67 r8 table 1. mpc5510 signal properties (continued) pin name gpio (pcr) num 1 supported functions 2 description i/o type voltage 3 pad 4 type status during reset 5 status after reset 5 package pin locations 144 176 208
mpc5510 microcontroller family data sheet, rev. 3 pin assignments and reset states freescale semiconductor 14 pj8 136 pj8 pcs_d4 gpio dspi_d peripheral chip select i/o i/o v dde2 sh ? ? ? 27 k2 pj9 137 pj9 pcs_d3 gpio dspi_d peripheral chip select i/o i/o v dde2 sh ? ? ? 26 k1 pj10 138 pj10 pcs_d2 gpio dspi_d peripheral chip select i/o i/o v dde2 sh ? ? ? 25 j4 pj11 139 pj11 pcs_d1 gpio dspi_d peripheral chip select i/o i/o v dde2 sh ? ? ? 19 h3 pj12 140 pj12 pcs_d0 gpio dspi_d peripheral chip select i/o i/o v dde2 sh ? ? ? 18 h2 pj13 141 pj13 sck_d gpio dspi_d clock i/o i/o v dde2 sh ? ? ? 16 g4 pj14 142 pj14 sout_d gpio dspi_d serial out i/o o v dde2 sh ? ? ? 15 g3 pj15 143 pj15 sin_d gpio dspi_d serial in i/o i v dde2 sh ? ? ? 13 g1 port k (2) pk0 144 pk0 extal32 gpio 32 khz crystal oscillator input i i v dda ae + ih ? ? ? 168 b6 pk1 145 pk1 xtal32 gpio 32 khz crystal oscillator output i o v dda ae + ih ? ? ? 166 a6 miscellaneous pins (9) extal ? extal extclk main crystal oscillator input external clock input i i v ddsyn ae extal 75 91 n16 xtal ? xtal main crystal oscillator output o v ddsyn ae xtal 74 90 p16 tms ? tms jtag test mode select input i v dde3 sh tms (pull up) 72 88 t15 tck ? tck jtag test clock input i v dde3 ih tck (pull down) 71 87 r14 tdo ? tdo jtag test data output o v dde3 mh tdo (pull up 9 )7086t14 tdi ? tdi jtag test data input i v dde3 ih tdi (pull up) 69 85 r13 jcomp ? jcomp jtag compliancy i v dde3 ih jcomp (pull down) 68 84 t13 test 10 ? test test mode select i v dde3 ih test 62 78 r11 reset ? reset external reset i/o v dde2 sh reset (pull up) 10 10 e4 1 the gpio number is the same as the corre sponding pad configuration register (siu_pcr n ) number. 2 this column lists the functions associated with the programming of the siu_pcr n [pa] bit field in the following order: gpio, function 1, function 2, and function 3. the unused functions by a given pin begin with fu nction 3, then function 2, then function 1. 3 these are nominal voltages. each se gment provides the power and ground for the given set of i/o pins. 4 pad types: sh - bi-directional slow speed pad with input hysteres is; mh - bi-directional medium speed pad with input hysteresis ; ih - input only pad with input hysteresis; ae/a - analog pad. 5 a dash for the function in this column denote s the input and output buffer are turned off. table 1. mpc5510 signal properties (continued) pin name gpio (pcr) num 1 supported functions 2 description i/o type voltage 3 pad 4 type status during reset 5 status after reset 5 package pin locations 144 176 208
pin assignments and reset states mpc5510 microcontroller family data sheet, rev. 3 freescale semiconductor 15 1.2 power and ground supply summary 6 port a[14:15]?extal32 and xtal32 functions only apply on the 144lqfp. these functions are on po rtk[0:1] for the 176lqfp and 208bga. in the 176 lqfp and 208 bga packages, activity on pa14 should be minimized if the 32khz xtal is enabled. 7 this analog input pin has reduced analog-to-digital conversion accuracy compared to pa0?pa15. see eqadc spec #11 (total unadjusted error for single ended conversions with calibration) for further notes on this. 8 the nexus function is selected when the jtag tap controller is enabled via the jcomp pin and the appropriate bits in the np pcr register. the value of the pa field in the associated pcr re gister has no effect on the pin function when the nexus functio n is selected. 9 pullup is enabled only when jcomp is negated. 10 always connect the test pin to ground (vss). table 2. mpc5510 power/ground pin name function description voltage 1 1 these are nominal voltages. package pin locations 144 176 208 v ddr voltage regulator supply 5.0 v 46 56 t6 v dda analog power 5.0 v 144 176 a2 v rh 2 2 v rh is shorted to v dda in the 144lqfp and 176 lqfp packages. eqadc voltage reference high 5.0 v b3 v ssa analog ground ? 141 173 a4 v rl 3 eqadc voltage reference low ? b4 refbypc eqadc reference bypass capacitor v ssa 1 1 b1 v pp 4 flash program/erase power 5.0 v 78 94 p15 v ddsyn 5 clock synthesizer power 3.3 v 73 89 r16 v sssyn clock synthesizer ground ? 76 92 m16 v dde1 external i/o power 3.3 v ? 5.0 v 96,119 105,120, 143,155 a15,d10,e13, g16,k15 v dde2 16,33,48 21,41,58 h4,l4,n5,p1 v dde3 61 71,77 n9,t11 v sse1 external i/o ground ? 95,118 104,119, 142,154 shorted to v ss in the package v sse2 15,32,47 20,40,57 shorted to v ss in the package v sse3 60 70,76 shorted to v ss in the package v dd33 5 3.3 v i/o power 3.3 v 77 93 n15 v flash 5, 6 flash read power v dd 5 internal logic power 1.5 v 31,53,79 39,63,95 a1,a16,b2,b15, r2,r15,t1,t16 v ddf 5 flash internal logic power 79 95 shorted to v dd in the package v ss ground ? 80 96 c3,c14,d4,d13, g7-g10,h7-h10, j7-j10,k7-k10, n4,n13,p3,p14 v ssf flash internal logic ground shorted to v ss in the package
mpc5510 microcontroller family data sheet, rev. 3 pin assignments and reset states freescale semiconductor 16 3 v rl is shorted to v ssa in the 144lqfp and 176 lqfp packages. 4 v pp requires 5v for program/erase operations, but may be 0-5v otherwise. v pp should not go high or low when the device is in sleep mode. 5 voltage generated from internal voltage regulator and no external connection or load allowed except the required bypass capacitors. 6 v flash is shorted to v dd33 in the package.
pin assignments and reset states mpc5510 microcontroller family data sheet, rev. 3 freescale semiconductor 17 1.3 pinout ? 144 lqfp figure 2. mpc5510 pinout ? 144 lqfp pe0/pcs_a2/emios5/mlbclk 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 refbypc an7/pa7 an6/pa6 an5/pa5 an4/pa4 an3/pa3 an1/pa1 an0/pa0 reset cntx_f/an16/anr/ph11 cnrx_f/an17/ans/ph10 cnrx_e/an18/ant/ph9 ma0/cntx_e/an19/ph8 v sse2 v dde2 rxd_f/an20/ph7 txd_f/an21/ph6 ma1/rxd_e/an22/ph5 ma2/txd_e/an23/ph4 cs 2 /emios23/an24/ph3 cs 3 /emios22/an25/ph2 sda_a/emios21/an26/ph1 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 pc12/emios12/pcs_c3/sin_d pc13/emios13/pcs_a5/pcs_d0 pc14/emios14/pcs_a4/pcs_d1 pc15/emios15/pcs_a3/pcs_d2 pd0/cntx_a/pcs_d3 pd1/cnrx_a/pcs_d4 pd2/cnrx_b/emios10/bootcfg*/pcs_d5 pd3/cntx_b/emios11 pd4/cntx_c/emios12 pd5/cnrx_c/emios13 pd6/txd_a/emios14 pd7/rxd_a/emios15 v dde1 v sse1 pd8/txd_b/scl_a pd9/rxd_b/sda_a pd10/pcs_b2/cntx_f/nmi0 pd11/pcs_b1/cnrx_f/nmi1 pd12/pcs_b0/emios9 pd13/sck_b/emios8 pd14/sout_b/emios7 pe1/pcs_a1/emios4/mlbsi pe2/pcs_a0/emios3/mlbdi 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 v dda /v rh pa8/an8/anw pa9/an9/anx v ssa /v rl pa10/an10/any pa11/an11/anz pa12/an12 pa13/an13 pa14/an14/extal32 pa15/an15/xtal32 pb0/an28/emios16/pcs_c5 pb1/an29/emios17/pcs_c4 pb2/an30/emios18/pcs_c3 pb3/an31/pcs_c2 pb4/an32/pcs_c1 pb5/an33/pcs_c0 pb6/an34/sck_c pb7/an35/sout_c pb8/an36/sin_c pb9/an37/cntx_d/pcs_b4 pb10/an38/cnrx_d/pcs_b3 pb11/an39/emios19/pcs_b5 pc0/emios0/fr_a_tx_en /ad24 pc1/emios1/fr_a_tx/ad16 pc2/emios2/fr_a_rx/ts 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 emios22/ad22/pg6 emios21/ad21/pg5 pcs_c0/emios20/ad20/pg4 sck_c/emios19/ad19/pg3 sout_c/emios18/ad18/pg2 sin_c/emios17/ad17/pg1 emios16/ad16/pg0 cnrx_d/tea /we1 /pf15 cntx_d/bdip /we0 /pf14 v ddr v sse2 v dde2 rxd_d/oe /pf13 ale/txd_d/ts /pf12 mdo7/rxd_c/cs0 /pf11 mdo6/txd_c/cs1 /pf10 mdo5/addr15/ad15/pf9 mdo4/addr14/ad14/pf8 mdo3/addr13/ad13/pf7 mdo2/mlb_slot/addr12/ad12/pf6 mdo1/mlbdo/addr11/ad11/pf5 mdo0/mlbso/addr10/ad10/pf4 v sse3 v dde3 scl_a/emios20/an27/ph0 an2/pa2 pd15/sin_b/emios6 26 27 28 29 30 31 32 33 34 35 36 sin_a/ad31/pg15 sout_a/ad30/pg14 sck_a/ad29/pg13 pcs_a0/ad28/pg12 pcs_a1/ad27/pg11 pcs_a2/ad26/pg10 v sse2 v dde2 txd_c/pcs_a3/ad25/pg9 pcs_a4/ad24/pg8 rxd_c/emios23/ad23/pg7 83 82 81 80 79 78 77 76 75 74 73 pe3/sck_a/emios2//mlbso pe4/sout_a/emios1/mlbdo pe5/sin_a/emios0/mlb_slot v ss /v ssf v dd /v ddf v pp v dd33 /v flash v sssyn extal/extclk xtal v ddsyn 62 63 64 65 66 67 68 69 70 71 72 mcko/mlbdi/addr9/ad9/pf3 mseo /mlbsi/addr8/ad8/pf2 evto/mlbclk/ta /pf1 evti/rd_wr /pf0 clkout/pe6 jcomp tdi tdo tck tms 119 118 117 116 115 114 113 112 111 110 109 v dde1 v sse1 pc3/emios3/fr_dbg0 pc4/emios4/fr_dbg1 pc5/emios5/fr_dbg2 pc6/emios6/fr_dbg3 pc7/emios7/fr_b_rx pc8/emios8/fr_b_tx/ad15 pc9/emios9/fr_b_tx_en /ad14 pc10/emios10/pcs_c5/sck_d pc11/emios11/pcs_c4/sout_d denotes active during reset only * v dd v dd test 144 lqfp
mpc5510 microcontroller family data sheet, rev. 3 pin assignments and reset states freescale semiconductor 18 1.4 pinout ? 176 lqfp figure 3. mpc5510 pinout ? 176 lqfp pe0/pcs_a2/emios5/mlbclk 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 refbypc an7/pa7 an6/pa6 an5/pa5 an4/pa4 an3/pa3 an1/pa1 an0/pa0 reset cntx_f/an16/anr/ph11 cnrx_f/an17/ans/ph10 cnrx_e/an18/ant/ph9 ma0/cntx_e/an19/ph8 v sse2 v dde2 rxd_f/an20/ph7 txd_f/an21/ph6 ma1/rxd_e/an22/ph5 ma2/txd_e/an23/ph4 cs 2 /emios23/an24/ph3 cs 3 /emios22/an25/ph2 sda_a/emios21/an26/ph1 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 pc12/emios12/pcs_c3/sin_d pc13/emios13/pcs_a5/pcs_d0 pc14/emios14/pcs_a4/pcs_d1 pc15/emios15/pcs_a3/pcs_d2 pd0/cntx_a/pcs_d3 pd1/cnrx_a/pcs_d4 pd2/cnrx_b/emios10/bootcfg*/pcs_d5 pd3/cntx_b/emios11 pd4/cntx_c/emios12 pd5/cnrx_c/emios13 pd6/txd_a/emios14 pd7/rxd_a/emios15 v dde1 v sse1 pd8/txd_b/scl_a pd9/rxd_b/sda_a pd10/pcs_b2/cntx_f/nmi0 pd11/pcs_b1/cnrx_f/nmi1 pd12/pcs_b0/emios9 pd13/sck_b/emios8 pd14/sout_b/emios7 pe1/pcs_a1/emios4/mlbsi pe2/pcs_a0/emios3/mlbdi 176 175 174 173 172 171 170 169 168 167 166 165 164 163 162 161 160 159 158 157 156 155 154 153 152 v dda /v rh pa8/an8/anw pa9/an9/anx v ssa /v rl pa10/an10/any pa11/an11/anz pa12/an12 pa13/an13 pa14/an14 pa15/an15 pb0/an28/emios16/pcs_c5 pb1/an29/emios17/pcs_c4 pb2/an30/emios18/pcs_c3 pb3/an31/pcs_c2 pb4/an32/pcs_c1 pb5/an33/pcs_c0 pb6/an34/sck_c pb7/an35/sout_c pb8/an36/sin_c pb9/an37/cntx_d/pcs_b4 pb10/an38/cnrx_d/pcs_b3 pb11/an39/emios19/pcs_b5 pc0/emios0/fr_a_tx_en /ad24 pc1/emios1/fr_a_tx/ad16 pc2/emios2/fr_a_rx/ts 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 cntx_d/bdip /we0 /pf14 v ddr v sse2 v dde2 rxd_d/oe /pf13 ale/txd_d/ts /pf12 mdo7/rxd_c/cs0 /pf11 mdo6/txd_c/cs1 /pf10 mdo5/addr15/ad15/pf9 mdo4/addr14/ad14/pf8 mdo3/addr13/ad13/pf7 mdo2/mlb_slot/addr12/ad12/pf6 mdo1/mlbdo/addr11/ad11/pf5 mdo0/mlbso/addr10/ad10/pf4 v sse3 v dde3 scl_a/emios20/an27/ph0 an2/pa2 pd15/sin_b/emios6 26 27 28 29 30 31 32 33 34 35 36 sin_a/ad31/pg15 sout_a/ad30/pg14 sck_a/ad29/pg13 pcs_a0/ad28/pg12 pcs_a1/ad27/pg11 pcs_a2/ad26/pg10 v sse2 v dde2 txd_c/pcs_a3/ad25/pg9 pcs_a4/ad24/pg8 rxd_c/emios23/ad23/pg7 pe3/sck_a/emios2//mlbso pe4/sout_a/emios1/mlbdo pe5/sin_a/emios0/mlb_slot v ss /v ssf v dd /v ddf v pp v dd33 /v flash v sssyn extal/extclk xtal v ddsyn 78 79 80 81 82 83 84 85 86 87 88 mcko/mlbdi/addr9/ad9/pf3 mseo /mlbsi/addr8/ad8/pf2 evto/mlbclk/ta /pf1 evti/rd_wr /pf0 clkout/pe6 jcomp tdi tdo tck tms 151 150 149 148 147 146 145 144 143 142 141 v dde1 v sse1 pc3/emios3/fr_dbg0 pc4/emios4/fr_dbg1 pc5/emios5/fr_dbg2 pc6/emios6/fr_dbg3 pc7/emios7/fr_b_rx pc8/emios8/fr_b_tx/ad15 pc9/emios9/fr_b_tx_en /ad14 pc10/emios10/pcs_c5/sck_d pc11/emios11/pcs_c4/sout_d denotes active during reset only * v dd v dd vsup/test 176 lqfp 37 38 39 40 41 42 43 44 140 139 138 137 136 135 134 133 45 46 47 48 49 50 51 52 emios22/ad22/pg6 emios21/ad21/pg5 pcs_c0/emios20/ad20/pg4 sck_c/emios19/ad19/pg3 sout_c/emios18/ad18/pg2 sin_c/emios17/ad17/pg1 emios16/ad16/pg0 cnrx_d/tea /we1 /pf15 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 132 131 130 129 128 127 126 125 sin_d/pj15 sout_d/pj14 sck_d/pj13 pcs_d0/pj12 pcs_d1/pj11 pcs_d2/pj10 pcs_d3/pj9 pcs_d4/pj8 we3 /ph15 we2 /ph14 ad7/pj7 ad6/pj6 ad5/pj5 ad4/pj4 v dde3 v sse3 pe10 pe11 pe12 pe13 v dde1 v sse1 pe14 pe15 pb15/rxd_h pb14/txd_h v dde1 v sse1 pk0/extal32 pk1/xtal32 pb12/txd_g/pcs_b4 pb13/rxd_g/pcs_b3
pin assignments and reset states mpc5510 microcontroller family data sheet, rev. 3 freescale semiconductor 19 1.5 pinout ? 208 pbga figure 4. mpc5510 pinout ? 208 pbga v dd 12345678910111213141516 v dda pa8 v ssa pb2 pb6 pc3 pc7 pc10 v dde1 v dd a ref v dd v rh v rl pa12 pk0 pb3 pb7 pc0 pc4 pc8 pc11 v dd pc12 b v ss pa9 pa11 pa15 pb4 pb8 pb14 pc1 pc5 pc9 v ss pc13 pc14 c v ss pa10 pa14 pb5 v dde1 v ss pc15 pd0 pd1 d v dde1 pd2 pd3 pd4 e pd6 pd7 pd9 f pd8 g v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss pe8 h v ss v ss v ss v ss pe9 pd14 pe11 pe10 j pe12 pd15 v dde1 pe0 k pe13 pe1 pe14 l pe3 m v ss v dde2 pf0 v ss n v ss pg3 pf1 pf3 v ss v pp xtal p v dd pg5 pf2 tdi tck v dd r v dd pg6 pe6 jcomp v dd t a b c d e f g h j k l m 12345678910111213141516 pa13 208 pbga ball map (as viewed from top through the package) n p r t pb10 pb11 pd10 pd11 v dde1 pf15 pg4 pa6 pa3 reset pk1 pa7 pa5 pb9 pd13 pd12 pe7 pa4 pa0 ph10 pg7 extal pf14 tms pc6 pd5 pe2 pe15 pe5 v sssyn pe4 v dd33 pj0 pj2 v dde3 pf8 pf12 pa1 pa2 ph11 ph12 ph13 pj13 pj14 ph9 pj15 v dde2 pj11 pj12 ph8 pj10 ph5 ph6 ph7 ph3 ph4 pj8 pj9 v dde2 ph0 ph1 ph2 pg12 pg13 pg14 pg15 pg9 pg10 pg11 pg8 v dde2 pg0 pj1 pj4 pf7 pf11 pj6 pg2 pf13 ph15 test pj3 pj7 pf10 pf5 pg1 v ddr ph14 v dde3 pf4 pf6 pf9 pj5 tdo v ddsyn pb12 pb13 pb15 pb0 pc2 pb1 bypc
mpc5510 microcontroller family data sheet, rev. 3 electrical characteristics freescale semiconductor 20 2 electrical characteristics this section contains detailed information on power cons iderations, dc/ac electrical ch aracteristics, and ac timing specifications for the mcu. 2.1 maximum ratings table 3. absolute maximum ratings 1 1 functional operating conditions are given in the dc electrical s pecifications. absolute maximum ratings are stress ratings only , and functional operation at the maxima is not guaranteed. stre ss beyond the listed maxima may affect device reliability or cause permanent damage to the device. num characteristic symbol min max 2 2 absolute maximum voltages are currently maximum burn?in voltages . absolute maximum specificati ons for device stress have not yet been determined. unit 1 5.0v voltage regulator reference voltage v ddr ? 0.3 6.5 v 2 5.0v analog supply voltage (reference to v ssa )v dda ? 0.3 6.5 v 3 5.0v flash program/erase voltage v pp ? 0.3 6.5 v 4 3.3v ? 5.0v external i/o supply voltage 3 3 all functional non-supply i/o pins are clamped to v ss and v dde . v dde1 4 v dde2 4 v dde3 4 4 v dde1 , v dde2 , and v dde3 are separate power segments and may be powe red independently with no differential voltage constraints between the power segments. ? 0.3 ? 0.3 ? 0.3 6.5 6.5 6.5 v 5 dc input voltage 5 5 ac signal over and undershoot of the input voltages of up to +/ ? 2.0 volts is permitted for a cumulative duration of 60 hours over the complete lifetime of the device (injection current does not need to be limited for this duration). v in ?1.0 6 6 internal structures will hold the input voltage above -1.0 volt if the injection current limit of 2ma is met. 6.5 7 7 internal structures hold the inpu t voltage below this maximum voltage on all pads powered by v dde supplies, if the maximum injection current specification is met (2 ma for all pins) and v dde is within operating voltage specifications. v 6v ref differential voltage v rh ? v rl ? 0.3 5.5 v 7v rh to v dda differential voltage v rh ? v dda ? 5.5 5.5 v 8v rl to v ssa differential voltage v rl ? v ssa ? 0.3 0.3 v 9v ddr to v dda differential voltage v ddr ? v dda ? v dda 0.3 v 10 maximum dc digital input current 8 (per pin, applies to all digital mh, sh, and ih pins) 8 total injection current for all pins (including both digital and analog) must not exceed 25ma. i maxd ?2 2 ma 11 maximum dc analog input current 9 (per pin, applies to all analog ae and a pins) 9 total injection current for all anal og input pins must not exceed 15ma. i maxa ?3 3 ma 12 storage temperature range t stg ? 55.0 150.0 o c 13 maximum solder temperature 10 10 solder profile per cdf-aec-q100. t sdr ? 260.0 o c 14 moisture sensitivity level 11 11 moisture sensitivity per jedec test method a112. msl ? 3
electrical characteristics mpc5510 microcontroller family data sheet, rev. 3 freescale semiconductor 21 2.2 thermal characteristics 2.2.1 general notes for specifications at maximum junction temperature an estimation of the chip junction temperature, t j , can be obtained from the equation: t j = t a + (r ja p d ) eqn. 1 where: t a = ambient temperature for the package ( o c) eqn. 2 r ja = junction to ambient thermal resistance ( o c/w) eqn. 3 p d = power dissipation in the package (w) eqn. 4 the supplied thermal resistances are provided based on jedec jesd51 series of stan dards to provide consistent values for estimations and comparisons. the difference be tween the values determined on the single-l ayer (1s) board and on the four-layer board with two signal layers and a power and a ground plane (2s 2p) clearly demonstrate that th e effective thermal resistance of table 4. thermal characteristics num characteristic symbol unit value 208 mapbga 176 lqfp 144 lqfp 1 junction to ambient 1, 2 natural convection (single layer board) 1 junction temperature is a function of on-chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient temperature, air flow, power dissipa tion of other components on the board, and board thermal resistance. 2 per semi g38-87 and jedec jesd51-2 with the single layer board horizontal. r ja c/w 44 38 43 2 junction to ambient 1, 3 natural convection (four layer board 2s2p) 3 per jedec jesd51-6 with the board horizontal. r ja c/w 27 31 34 3 junction to ambient 1, 3 (@200 ft./min., single layer board) r jma c/w 35 30 34 4 junction to ambient 1, 3 (@200 ft./min., four layer board 2s2p) r jma c/w 24 25 28 5 junction to board 4 4 thermal resistance between the die and the printed circuit b oard per jedec jesd51-8. board temperature is measured on the top surface of the board near the package. r jb c/w 16 20 22 6 junction to case 5 5 indicates the average thermal resistance between the die and the case top surface as measured by the cold plate method (mil spec-883 method 1012.1) with the cold plat e temperature used for the case temperature. r jc c/w 8 6 7 7 junction to package top 6 natural convection 6 thermal characterization parameter indicating the tem perature difference between package top and the junction temperature per jedec jesd51-2. jt c/w 2 2 2
mpc5510 microcontroller family data sheet, rev. 3 electrical characteristics freescale semiconductor 22 the component is not a constant. it depends on the construction of the application board (number of planes), the effective size of the board which cools the component, ho w well the component is thermally and elect rically connected to the planes, and the power being dissipated by adjacent components. connect all the ground and power balls to the respective planes with one via per ball. using fewer vias to connect the package to the planes reduces the thermal perfor mance. thinner planes also reduce the thermal performance. when the clearance between through vias leave the planes virtually disconnected, the thermal performance is also greatly reduced. as a general rule, the value obtained on a single layer board is appropriate for the tightly packed printed circuit board. the value obtained on the board with the internal planes is usually appropriate if the application board has one oz (35 micron nominal thickness) internal planes, the components are well separated, and the overall power dissipation on the board is less than 0.02 w/cm 2 . the thermal performance of any component depends strongly on th e power dissipation of surrounding components. in addition, the ambient temperature varies widely wi thin the application. for many natura l convection and especially closed box applications, the board temperature at the perimeter (edge) of th e package is approximately the sa me as the local air temperatu re near the device. specifying the local ambient conditions explicitly as the board temperature provides a more precise descriptio n of the local ambient condi tions that determine the temperature of the device. at a known board temperature, the junction temperature is estimated using the following equation: t j = t b + (r jb p d ) eqn. 5 where: t j = junction temperature ( o c) eqn. 6 t b = board temperature at the package perimeter ( o c/w) eqn. 7 r jb = junction to board thermal resistance ( o c/w) per jesd51-8 eqn. 8 p d = power dissipation in the package (w) eqn. 9 when the heat loss from the package case to the air can be i gnored, acceptable predictions of j unction temperature can be made. the application board should be similar to the thermal test condition, with the component soldered to a board with internal planes. historically, the thermal resistance has frequently been expres sed as the sum of a junction to case thermal resistance and a ca se to ambient thermal resistance: r ja = r jc + r ca eqn. 10 where: r ja = junction to ambient thermal resistance ( o c/w) eqn. 11 r jc = junction to case thermal resistance ( o c/w) eqn. 12 r ca = case to ambient thermal resistance ( o c/w) eqn. 13 r jc is device related and cannot be influenced by the user. the user controls the thermal envi ronment to change the case to ambient thermal resistance, r ca . for instance, the user can chan ge the air flow around the device, add a heat sink, change the mounting arrangement on printed circuit board, or change the ther mal dissipation on the printed circuit board surrounding the
electrical characteristics mpc5510 microcontroller family data sheet, rev. 3 freescale semiconductor 23 device. this description is most useful for packages with heat sinks where some 90% of the heat flow is through the case to the heat sink to ambient. for most pa ckages, a better model is required. a more accurate two-resistor thermal model can be constructed from the junction to board ther mal resistance and the junction to case thermal resistance. the junction to cas e covers the situation where a heat sink will be used or where a substantial amo unt of heat is dissipated from the top of th e package. the junction to board thermal resistance describes the thermal performance when most of the heat is conducted to th e printed circuit board. this model can be used for either hand estimations or for a computational fluid dynamics (cfd) thermal model. to determine the junction temperature of the device in the application after prototypes are available, the thermal characterization parameter ( jt ) can be used to determine the junction temperat ure with a measurement of the temperature at the top center of the package case using the following equation: t j = t t + ( jt p d ) eqn. 14 where: t t = thermocouple temperature on top of the package ( o c) eqn. 15 jt = thermal characterization parameter ( o c/w) eqn. 16 p d = power dissipation in the package (w) eqn. 17 the thermal characterization parameter is measured per jesd51-2 specification using a 40-gauge type t thermocouple epoxied to the top center of the package case. the thermocouple should be positioned so that the thermocouple junction rests on the package. a small amount of epoxy is placed over the thermocouple juncti on and over about 1 mm of wire extending from the junction. the thermocouple wire is placed flat against the package case to av oid measurement errors caused by cooling effects of the thermocouple wire. references: semiconductor equipment and materials international 805 east middlefield rd mountain view, ca 94043 (415) 964-5111 mil-spec and eia/jesd (jedec) specifi cations are available from global engi neering documents at 800-854-7179 or 303-397-7956. jedec specifications are available on the web at http://www.jedec.org . 1. c.e. triplett and b. joiner, ?an experimental characterization of a 272 pbga within an automotive engine controller module,? proceedings of semi therm, san diego, 1998, pp. 47?54. 2. g. kromann, s. shidore, and s. addison, ?thermal mo deling of a pbga for air-cooled applications,? electronic packaging and production, pp. 53?58, march 1998. 3. b. joiner and v. adams, ?measurement and simulation of junction to board thermal resistance and its application in thermal modeling,? proceedings of se mitherm, san diego, 1999, pp. 212?220.
mpc5510 microcontroller family data sheet, rev. 3 electrical characteristics freescale semiconductor 24 2.3 esd characteristics table 5. esd ratings 1, 2 1 all esd testing is in conformity with cdf-aec-q100 stress test qualification for automotive grade integrated circuits. 2 a device will be defined as a failure if after exposure to esd pulses the device no longer m eets the device specification requirements. complete dc parametric and f unctional testing shall be performed per a pplicable device specification at room temperature followed by hot temperature, unless s pecified otherwise in the device specification characteristic symbol value unit esd for human body model (hbm) 2000 v hbm circuit description r1 1500 ohm c100 pf esd for field induced charge model (fdcm) 500 (all pins) v 750 (corner pins) number of pulses per pin: positive pulses (hbm) negative pulses (hbm) ? ? 1 1 ? ? interval of pulses ? 1 second
electrical characteristics mpc5510 microcontroller family data sheet, rev. 3 freescale semiconductor 25 2.4 dc electrical specifications table 6. dc electrical specifications num characteristic symbol min max unit 1a c parts operating junction temperature range operating ambient temperature range 1 t j t a ? 40 ? 40 105 85 o c o c 1b v parts operating junction temperature range operating ambient temperature range 1 t j t a ? 40 ? 40 120 105 o c o c 1c m parts 2 operating junction temperature range operating ambient temperature range 1 t j t a ? 40 ? 40 145 125 o c o c 2 5.0v voltage regulator reference voltage v ddr 4.5 5.25 v 3 5.0v analog supply voltage v dda 4.5 5.25 v 4 5.0v flash program/erase voltage 3 v pp 4.5 5.25 v 5 3.3v ? 5.0v external i/o supply voltage v dde1 4,5 v dde2 4 v dde3 4 3.0 3.0 3.0 5.5 5.5 5.5 v 6 pad (sh/mh/ih) input high voltage v ih 0.65 v dde v dde + 0.3 v 7 pad (sh/mh/ih) input low voltage v il v ss ? 0.3 0.35 v dde v 8 pad (sh/mh/ih) in put hysteresis v hys 0.1 v dde 0.2 v dde v 9 analog (ae/a) input voltage v indc v ssa ? 0.3 v dda + 0.3 see note 5 v 10 slow/medium i/o output high voltage i oh = ?1.0 ma i oh = ?0.2 ma v oh 0.80 v dde 0.95 v dde ? v 11 slow/medium i/o output low voltage i ol = 1.0 ma i oh = 0.2 ma v ol ?0.20 v dde 0.05 v dde v 12 input capacitance (digital pins: pad type mh,sh, ih with no a or ae) c in ?7pf 13 input capacitance (analog pins : pad type a, ae, and ae+ih) c in_a ?10pf 14 input capacitance (shared digital and analog pins: a with sh or mh) c in_m ?12pf 15 slow/medium i/o weak pull up/down absolute current 6 i act 10 170 a 16 i/o input leakage current 7 i inact_d ? 1.5 1.5 a 17 dc injection current (per pin) i ic ? 2.0 2.0 ma 18 analog input current, channel off 8 (analog pins ae and ae+ih) i inact_a ? 200 200 na 19 analog input current (shared digital and analog pins: a with sh or mh) i inact_ad ?1.5 1.5 a 20 v rh to v dda differential voltage v rh ? v dda ? 100 100 mv
mpc5510 microcontroller family data sheet, rev. 3 electrical characteristics freescale semiconductor 26 21 v rl to v ssa differential voltage v rl ? v ssa ? 100 100 mv 22 v ss to v ssa differential voltage v ss ? v ssa ? 100 100 mv 23 v sssyn to v ss differential voltage v sssyn ? v ss ?50 50 mv 24 v ddr to v dda differential voltage v ddr ? v dda ? 100 100 mv 25 slew rate on vdda, vddr, and vdde power supply pins 9 vramp 1 100 v/ms 26 capactive supply load vdd vdd33 vddsyn vload 800 200 200 ? ? nf 1 please refer to section 2.2.1, ?general notes for specificat ions at maximum junction temperature ? for more details about the relation between ambient temperature t a and device junction temperature t j . 2 m parts can?t go above 66 mhz. 3 v pp can drop to 0 volts during read-only operations and be fore entry to sleep mode, to reduce power consumption. 4 v dde1 , v dde2 , and v dde3 are separate power segments and may be powered independently with no differential voltage constraints between the power segments. 5 if v dde1 is below v dda than the analog input limits (spec #9 (analog (ae/a) input voltage) in ta b l e 6 ) will be based on the v dde1 voltage level. 6 absolute value of current, measured at v il and v ih . 7 weak pull up/down inactive. measured at v dde = 5.25 v. applies to pad types: sh and mh. 8 maximum leakage occurs at maximum operating temperature. leakage current decreases by approximately one-half for each 8 to 12 o c, in the ambient temperature range of 50 to 125 o c. applies to pad types: a and ae. 9 this applies to the ramp up rate from 0.3 volts to 3.0 volts. table 6. dc electrical specifications (continued) num characteristic symbol min max unit
electrical characteristics mpc5510 microcontroller family data sheet, rev. 3 freescale semiconductor 27 2.5 operating current sp ecifications table 7. operating currents num characteristic symbol typ 1 25c ambient 1 typ - nominal voltage levels and functional activity. max - maximum voltage levels and functional activity. typ 1 70c ambient max 1 -40?145c junction unit equations i total = i dde + i pp + i dda + i ddr i dde = i dde1 + i dde2 + i dde3 1v dde(1,2,3) current v dde(1,2,3) @ 3.0v - 5.5v static 2 , or when in sleep or stop dynamic 3 2 static state of pins is when input pins are disabled or not being toggled and driven to a valid input level, output pins are not toggling or driving against any current loads, and internal pull devices are disabled or not pulling against any current loads. 3 dynamic current from pins is applicat ion specific and depends on active pull devices, switching outputs, output capacitive and current loads, and switching inputs. refer to ta b l e 8 for more information. i dde 1 note 3 3 note 3 30 note 3 a ma 2v pp current v pp @ 0v (all modes) v pp @ 5.25v sleep mode stop mode run mode i pp 1 15 15 1 1 20 20 1 1 30 30 25 a a a ma 3v dda current v dda @ 4.5v - 5.25v run mode 4 sleep/stop 5 mode with 32kirc sleep/stop 5 mode with 32kosc sleep/stop 5 mode with 16mirc 4 run mode is a typical application with the adc, 16mirc, 32kirc running. 5 sleep/stop mode means that only the listed peripherals are on. all others are diabled. i dda 5 12 12 111 5 16 16 165 10 26 28 225 ma a a a 4v ddr current v ddr @ 4.5v - 5.25v sleep mode with xosc 6 (additonal) with rtc/api (additonal) each 8k ram block (additional) stop mode with xosc 6 (additonal) run mode (using 16 mhz irc) run mode (maximum @ 48 mhz) 7 run mode (maximum @ 66 mhz) 8 run mode (maximum @ 80mhz) 9 6 xosc: optionally enabled in sleep and stop modes (oscillator remains running from crystal but xosc clock output disabled). 7 run mode condition includes pll selected as source of system clock, xosc enabled with 40mhz crystal, all peripherals enabled, both cores running, and running a typical application using both sram and flash. i ddr 20 500 1 0.8 170 500 30 50 105 120 25 600 1 7 600 600 35 75 110 130 360 900 3 45 1500 900 40 90 120 135 a a a a a a ma ma ma ma
mpc5510 microcontroller family data sheet, rev. 3 electrical characteristics freescale semiconductor 28 8 run mode condition includes pll selected as source of system clock, xosc enabled with 40mhz crystal; all peripheral and cores enabled and running a typical application using both sram and flash. be sure to calculate the junction temperature, as the maximum current at maximum ambient temperature can exceed the maximum junction temperature. 9 run mode condition includes pll selected as source of system clock, xosc enabled with 40mhz crystal, all peripheral and cores enabled and running a typical application using both sram and flash. only for 208 mapbga and only 120c junction or lower. be sure to calc ulate the junction temperature, as the maximum current at maximum ambient temperature can exceed the maximum junction temperature
electrical characteristics mpc5510 microcontroller family data sheet, rev. 3 freescale semiconductor 29 2.6 i/o pad current specifications the power consumption of an i/o segment depends on the usage of the pins on a particular segment. the power consumption is the sum of all output pin currents for a particular segment. the output pin current can be calculated from table 8 based on the voltage, frequency, and load on the pin. use linear scaling to calculate pin cu rrents for voltage, frequency, and load parameters that fall outside the values given in table 8 . table 8. i/o pad average dc current 1 1 these values are estimated from simulation and ar e not tested. currents apply to output pins only. num pad type symbol frequency (mhz) load 2 (pf) 2 all loads are lumped. voltag e (v) slew rate control current (ma) 1slow (pad type sh) i drv_sh 25 50 5.25 11 8.0 210505.25013.2 3 2 50 5.25 00 0.7 4 2 200 5.25 00 2.4 5medium (pad type mh) i drv_mh 50 50 5.25 11 17.3 620505.25016.5 7 3.33 50 5.25 00 1.1 8 3.33 200 5.25 00 3.9
mpc5510 microcontroller family data sheet, rev. 3 electrical characteristics freescale semiconductor 30 2.7 low voltage characteristics table 9. low voltage monitors num characteristic symbol min typical max unit 1 power-on-reset assert level 1 v por ?0.70? v 2 low voltage monitor 1.5v 1 assert level de-assert level 1 monitors v dd v lv 1 5 a v lv 1 5 d ? ? 1.40 1.45 ? ? v 3 low voltage monitor 3.3v 2 assert level de-assert level 2 monitors v dd33 v lv 3 3 a v lv 3 3 d ? ? 3.05 3.10 ? ? v 4 low voltage monitor synthesizer 3 assert level de-assert level 3 monitors v ddsyn v lvsyna v lvsynd ? ? 3.05 3.10 ? ? v 5 low voltage monitor 5.0v low threshold 4 assert level de-assert level 4 monitors v dda v lv 5 l a v lv 5 l d 3.30 3.35 3.35 3.40 3.40 3.45 v 6 low voltage monitor 5.0v 4 assert level de-assert level v lv 5 a v lv 5 d 4.50 4.55 4.55 4.60 4.70 4.75 v 7 low voltage monitor 5.0v high threshold 4 assert level de-assert level v lv 5 h a v lv 5 h d 4.70 4.75 4.75 4.80 4.80 4.85 v
electrical characteristics mpc5510 microcontroller family data sheet, rev. 3 freescale semiconductor 31 2.8 oscillators electrical characteristics table 10. 3.3v high frequency external oscillator num characteristic symbol min. value max. value unit 1 frequency range 1 1 since this is an amplitude controlled oscillator the use of ov ertone oscillators is not reco mmended. only use fundamental frequency oscillators. f ref 4 2 2 when pll frequency modulation is active, reference frequencies less than 8mhz will distort the modulated waveform and the effects of this on emissi ons is not characterized. 40 mhz 2 duty cycle of reference t dc 40 60 % 3 extal input high voltage external crystal mode 3 external clock mode 3 this parameter is meant for those who do not use quartz crystals or resonators, but can osc, in crystal mode. in that case, v extal ? v xtal 400mv criteria has to be met for oscillator?s comparator to produce output clock. v ihext v xtal + 0.4 0.65 x v ddsyn v ddsyn + 0.3 v ddsyn + 0.3 v 4 extal input low voltage external crystal mode 3 external clock mode v ilext v ddsyn ? 0.3 v ddsyn ? 0.3 v xtal ? 0.4 0.35 x v ddsyn v 5 xtal current 4 4 i xtal is the oscillator bias current out of the xtal pin with both extal and xtal pins grounded. i xtal 26ma 6 total on-chip stray capacitance on xtal c s_xtal ?3pf 7 total on-chip stray capacitance on extal c s_extal ?3pf 8 crystal manufacturer?s recommended capacitive load c l see crystal specification see crystal specification pf 9 discrete load capacitance to be connected to extal c l_extal ?2 c l ? c s_extal ? c pcb_extal 5 5 c pcb_extal and c pcb_xtal are the measured pcb stray capacitances on extal and xtal, respectively pf 10 discrete load capacitance to be connected to xtal c l_xtal ?2 c l ? c s_xtal ? c pcb_xtal 5 pf 11 startup time t startup ?10ms table 11. 5v low frequency (32 khz) external oscillator num characteristic symbol min. value max. value unit 1 frequency range f ref32 32 38 khz 2 duty cycle of reference t dc32 40 60 % 3 xtal32 current 1 1 i xtal32 is the oscillator bias current out of the xta l32 pin with both extal32 and xtal32 pins grounded. i xtal32 0.5 3 a 4 crystal manufacturer?s recommended capacitive load c l32 see crystal specification see crystal specification pf 5 startup time t startup ?2s
mpc5510 microcontroller family data sheet, rev. 3 electrical characteristics freescale semiconductor 32 table 12. 5v high frequency (16 mhz) internal rc oscillator num characteristic symbol min typ max unit 1 frequency before trim 1 1 across process, voltage, and temperature f ut 12.8 16 22.3 mhz 2 frequency after loading factory trim 2 2 across voltage and temperature f t 15.1 16 16.9 mhz 3 application trim resolution 3 3 fixed voltage and temperature t s ?? 0 . 5% 4 application frequency trim step 3 f s ? 300 ? khz 5 start up time s t ? ? 500 ns table 13. 5v low frequency (32 khz) internal rc oscillator num characteristic symbol min typ max unit 1 frequency before trim 1 1 across process, voltage, and temperature f ut32 20.8 32.0 43.2 khz 2 frequency after loading factory trim 2 2 across voltage and temperature f t32 26 32.0 38 khz 3 application trim resolution 3 3 fixed voltage and temperature t s32 ?? 2% 4 application frequency trim step 3 f s32 ? 1 ? khz 5 start up time s t32 ? ? 100 s
electrical characteristics mpc5510 microcontroller family data sheet, rev. 3 freescale semiconductor 33 2.9 fmpll electrical characteristics table 14. fmpll electrical specifications 1 1 v ddsyn = 3.0v to 3.6 v, v sssyn = 0 v, ta = tl to th num characteristic symbol min. value max. value unit 1 system frequency 2 -40 o c t j 120 o c -40 o c t j 145 o c 2 the maximum value is without frequency modulation turned on. if frequency modulation is turned on, the maximum value (average frequency) must be de-rated by the percentage of modulation enabled. f sys 375 375 80000 3 66000 3 80 mhz is only available in the 208 pin package. khz 2 pll reference frequency (output of predivider) f pllref 410mhz 3 vco frequency 4 4 optimum performance is achieved with the highest vco frequency f easible based on the highest erfd that results in the desired pll frequency. f vco 192 500 mhz 4 pll frequency 5 -40 o c t j 120 o c -40 o c t j 145 o c 5 the vco frequency range is higher than the maximum allowable pl l frequency. the synthesizer co ntrol register 2?s enchanced reduced frequency divider (fmpll_syncr2[erfd]) in enhanced operation mode must be programmed to divide the vco frequency within the pll frequency range. f pll 3 3 80 3 66 mhz 5 loss of reference frequency 6 6 loss of reference frequency is the refere nce frequency detected by the pll which then transitions into self clocked mode. f lor 100 1000 khz 6 self clocked mode frequency 7 7 self clocked mode frequency is the frequency that the pll operates at when the refere nce frequency falls below f lor . f scm 13 35 mhz 7 pll lock time 8 8 this specification applies to the period required for the pll to relock after changing the enhanced multiplication factor divid er (emfd) bits in the synthesizer control r egister 1 (syncr1) in enhanced operation mode. t lpll ?750 s 8 frequency un-lock range f ul ? 4.0 4.0 % f sys 9 frequency lock range f lck ? 2.0 2.0 % f sys 10 clkout cycle-to-cycle jitter, 9, 10 9 jitter is the average deviation from the programmed frequen cy measured over the specified interval at maximum f sys . measurements are made with the device powe red by filtered supplies and clocked by a stable external clock signal. noise injected into the pll circuitry via v ddsyn and v sssyn and variation in crystal oscillator frequency increase the jitter percentage for a given interval. clkout divider set to divide-by-2. 10 values are with frequency modulation disabled. if frequency modulation is enabled, jitter is the sum of c jitter + c mod . c jitter ? 5 5 % f clkout 10a clkout jitter at 10 s period 9,10, 11 11 the pll % jitter reduces with more cycles. 10 s was picked for a reference point for lin (100 kbits), slower speeds will have even less % jitter. c jitter ? 0.05 0.05 % f clkout 11 frequency modulation depth 1% setting 12,13 (f sys max must not be exceeded) 12 modulation depth selected must not result in f sys value greater than the f sys maximum specified value. 13 these depth ranges are obtained by filtering the raw cycle-to-cycle clock frequency data to eliminate the presence of the the normal clock jitter riding on top of the fm waveform . the allowable modulation rates are 400 khz to 1 mhz. c mod 0.5 2 %f sys 12 frequency modulation depth 2% setting 12,13 (f sys max must not be exceeded) c mod 13%f sys
mpc5510 microcontroller family data sheet, rev. 3 electrical characteristics freescale semiconductor 34 2.10 eqadc electrical characteristics table 15. eqadc conversion specifications (operating) num characteristic symbol min max unit 1 adc clock (adclk) frequency 1 1 conversion characteristics vary with f adclk rate. reduced conversion accuracy occurs at maximum f adclk rate. the maximum value is based on 800ks/s and the minimum value is based on 20mhz oscillator clock frequency divided by a maximum 16 factor. f adclk 112mhz 2 conversion cycles cc 14+2 (or 16) 14+128 (or 142) adclk cycles 3 stop mode recovery time 2 2 the specified value is for the case when the 100nf capacitor is not connected to the refbypc pin. when the capacitor is connected to the refbpyc pin, the recovery time is 10ms. t sr 20 ? s 4 resolution ? 1.25 ? mv 5 inl: 12 mhz adc clock 3 3 at v rh ? v rl = 5.12 v, one lsb = 1.25 mv = one count. inl12 ? 10 counts 6 dnl: 12 mhz adc clock 3 dnl12 ? 10 counts 7 offset error with calibration 3 offwc ? 10 counts 8 full scale gain error with calibration gainwc ? 10 counts 9 disruptive input injection current 4, 5, 6, 7 4 below disruptive current conditions, the channel being stressed has conversion values of 0x3ff for analog inputs greater than v rh and 0x000 for values less than v rl . this assumes that v rh v dda and v rl v ssa due to the presence of the sample amplifier. other channels are not af fected by non-disruptive conditions. 5 exceeding limit may cause conversion error on stressed channels a nd on unstressed channels. transitions within the limit do not affect device reliability or cause permanent damage. 6 input must be current limited to the val ue specified. to determine the value of th e required current-limiting resistor, calcula te resistance values using v posclamp = v dda + 0.5v and v negclamp = ? 0.3 v, then use the larger of the calculated values. 7 condition applies to two adjacent pads on the internal pad. i inj ?1ma 10 incremental error due to injection current. all channels have same 10k < rs <100k 8 channel under test has rs=10k , i inj =i injmax ,i injmin 8 at v rh ? v rl = 5.12 v, one lsb = 1.25 mv = one count. this count error is in addition to the tue count error. e inj ? 6 counts 11 total unadjusted error for single ended conversions with calibration 3, 9, 10, 11, 12 9 the tue specification will always be better than the sum of the inl, dnl, offset, and gain errors due to canceling errors. 10 tue includes all internal device error such as internal reference variation (75% ref, 25% ref) 11 depending on the customer input impedance, the analog input leak age current (dc electrical specification) may affect the actual tue measured on analog channels shared digital pins. 12 it is possible to see up to one additional count added for th e 144 pin packages since the vrl and vrh functions are shared with the vssa and vdda, respectively . on analog pins above pa15, th e accuracy effects from adjacent digital port pin activity is application dependent because of frequency, level, noise, etc. tue ? 10 counts 12 source impedance 13 13 if r s is greater than 1 k ohm, be sure to ca lculate the affect of pin leakage and use the proper sampling time, to ensure that you get the accuracy required. r s ? 100k ohm
electrical characteristics mpc5510 microcontroller family data sheet, rev. 3 freescale semiconductor 35 2.11 flash memory electrical characteristics table 16. flash program and erase specifications 1 1 typical program and erase times assume nominal supply values and operation at 25 o c. num characteristic symbol min typ initial max 2 2 initial factory condition: < 100 program/erase cycles, nomial s upply values and operation at 25 o c. max 3 3 the maximum time is at worst case cond itions after the specified number of pr ogram/erase cycles. this maximum value is characterized but not guaranteed. unit 1 double word (64 bits) program time 4 4 this does not include software overhead. t dwprogram ? 10 ? 500 s 2 page (128 bits) program time 4 t pprogram ? 15 44 500 s 3 16 kbyte block pre-program and erase time t 16kpperase ? 325 525 5000 ms 4 64 kbyte block pre-program and erase time t 64kpperase ? 525 675 5000 ms 5 128 kbyte block pre-program and erase time t 128kpperase ? 675 1800 7500 ms 6 minimum operating frequency for program and erase operations ?25???mhz 7 wait states relative to system frequency pfcrpn[rwsc] = 0b000; pfcrpn[wwsc] = 0b01 pfcrpn[rwsc] = 0b001; pfcrpn[wwsc] = 0b01 pfcrpn[rwsc] = 0b010; pfcrpn[wwsc] = 0b01 t rwsc ? ? ? ? ? ? ? ? ? 25 50 80 mhz 8recovery time stop mode exit or stop bit negated sleep mode exit (with crp_recptr[fastrec]=1) 5 5 if crp_recptr[fastrec]=0, then hardware will wait 2340 system clocks before exiting from sleep mode to account for the flash recovery time. the default system clock source after sl eep is the 16mirc. a nominal frequency of 16mhz equates to a hardware wait of 146 s. t recover ? ? ? ? ? ? 20 120 s s table 17. flash eeprom module life (full temperature range) num characteristic symbol min typical 1 1 typical endurance is evaluated at 25c. product qualificati on is performed to the minimum specification. for additional information on the freescale definition of typical endurance, please refer to engineering bulletin eb619 ?typical endurance for nonvolatile memory.? unit 1 number of program/erase cycles per block over the operating temperature range (t j ) 16 kbyte and 64 kbyte blocks 128 kbyte blocks p/e 100,000 1000 ? 100,000 cycles 2 data retention blocks with 0 ? 1,000 p/e cycles blocks with 1,001 ? 100,000 p/e cycles retention 20 5 ?years
mpc5510 microcontroller family data sheet, rev. 3 electrical characteristics freescale semiconductor 36 2.12 pad ac specifications figure 5. pad output delay table 18. pad ac specifications (vdde = 3.0v - 5.5v) 1 1 these are worst case values that are estimated from simulation and not tested. the values in the table are simulated at vdde = 3.0v to 5.5v, t a = tl to th. num pad type src out delay 2, 3 (ns) 2 this parameter is supplied for reference an d is not tested. add a maxi mum of one system clock to the output delay for delay with respect to system clock. 3 delay and rise/fall are measured to 20% or 80% of the respective signal. rise/fall 3 , 4 (ns) 4 this parameter is guaranteed by characteriza tion before qualification ra ther than 100% tested. load drive (pf) 1 slow (sh) 11 39 23 50 120 87 200 01 101 52 50 188 111 200 00 507 248 50 597 312 200 2 medium (mh) 11 23 12 50 64 44 200 01 50 22 50 90 50 200 00 261 123 50 305 156 200 4 pull up/down (3.6v max) ? ? 7500 50 5 pull up/down (5.5v max) ? ? 9500 50 vdd/2 v oh v ol rising edge out delay falling edge out delay pad internal data input signal pad output
electrical characteristics mpc5510 microcontroller family data sheet, rev. 3 freescale semiconductor 37 2.13 ac timing 2.13.1 reset and boot configuration pins figure 6. reset and boot configuration timing 2.13.2 external interrupt (irq) and no n-maskable interrupt (nmi) pins figure 7. irq and nmi timing table 19. reset and boot configuration timing num characteristic symbol min max unit 1 reset pulse width t rpw 150 ? ns 2 bootcfg setup time after reset valid t rcsu ?100 s 3 bootcfg hold time from reset valid t rch 0? s table 20. irq/nmi timing num characteristic symbol min max unit 1 irq/nmi pulse width low t ipwl 3?t sys 2 irq/nmi pulse width high t ipwh 3?t sys 3 irq/nmi edge to edge time 1 1 applies when irq/nmi pins are configured for rising edge or falling edge events, but not both. t icyc 6?t sys 1 reset 3 bootcfg 2 irq/nmi 1,2 1,2 3
mpc5510 microcontroller family data sheet, rev. 3 electrical characteristics freescale semiconductor 38 2.13.3 jtag (ieee 1149.1) interface figure 8. jtag test clock input timing table 21. jtag interface timing 1 1 these specifications apply to jtag boundary scan only. jtag timing specified at vdde = 3.0v to 5.5v, t a = tl to th, and cl = 30pf with src = 0b11. num characteristic symbol min max unit 1tck cycle time t jcyc 100 ? ns 2 tck clock pulse width (measured at vdde/2) t jdc 40 60 ns 3 tck rise and fall times (40% ? 70%) t tckrise ?3ns 4 tms, tdi data setup time t tmss, t tdis 5?ns 5 tms, tdi data hold time t tmsh, t tdih 25 ? ns 6 tck low to tdo data valid t tdov ?20ns 7 tck low to tdo data invalid t tdoi 0?ns 8 tck low to tdo high impedance t tdohz ?20ns 9 jcomp assertion time t jcmppw 100 ? ns 10 jcomp setup time to tck low t jcmps 40 ? ns 11 tck falling edge to output valid t bsdv ?50ns 12 tck falling edge to output valid out of high impedance t bsdvz ?50ns 13 tck falling edge to output high impedance t bsdhz ?50ns 14 boundary scan input valid to tck rising edge t bsdst 50 ? ns 15 tck rising edge to boundary scan input invalid t bsdht 50 ? ns tck 1 2 3 3 2
electrical characteristics mpc5510 microcontroller family data sheet, rev. 3 freescale semiconductor 39 figure 9. jtag test access port timing figure 10. jtag jcomp timing tck 4 5 6 7 8 tms, tdi tdo tck jcomp 9 10
mpc5510 microcontroller family data sheet, rev. 3 electrical characteristics freescale semiconductor 40 figure 11. jtag boundary scan timing tck output signals input signals output signals 11 12 13 14 15
electrical characteristics mpc5510 microcontroller family data sheet, rev. 3 freescale semiconductor 41 2.13.4 nexus debug interface figure 12. nexus output timing table 22. nexus debug port timing 1 1 jtag specifications in this table apply when used for debug func tionality. all nexus timing rela tive to mcko is measured from 50% of mcko and 50% of the respective signal. ne xus timing specified at vdde = 3.0v to 5.5v, t a = tl to th, and cl = 30pf with src = 0b11. num characteristic symbol min max unit 1 mcko cycle time t mcyc 40 ? ns 2 mcko duty cycle t mdc 40 60 % 3 mcko low to mdo data valid 2 2 mdo, mseo , and evto data is held valid until next mcko low cycle. t mdov ?2 4.0 ns 4 mcko low to mseo data valid 2 t mseov ?2 4.0 ns 5 mcko low to evto data valid 2 t evtov ?2 4.0 ns 6 evti pulse width t evtipw 4.0 ? t tcyc 7 evto pulse width t evtopw 1t mcyc 8 tck cycle time 3 3 the system clock frequency needs to be th ree times faster that the tck frequency. t tcyc 40 ? ns 9 tck duty cycle t tdc 40 60 % 10 tdi, tms data setup time t ntdis, t ntmss 8?ns 11 tdi, tms data hold time t ntdih, t ntmsh 4?ns 12 tck low to tdo data valid t jov 08ns 1 2 3 4 5 mcko mdo mseo evto output data valid
mpc5510 microcontroller family data sheet, rev. 3 electrical characteristics freescale semiconductor 42 figure 13. nexus tdi, tms, tdo timing tdo 10 11 tms, tdi 12 tck
electrical characteristics mpc5510 microcontroller family data sheet, rev. 3 freescale semiconductor 43 2.13.5 external bus interface (ebi) figure 14. clkout timing table 23. external bus operation timing 1 1 ebi timing specified at vdde = 3.0v to 5.5v, t a = tl to th, and cl = 50pf with siu_pcr n [src] = 0b11. num characteristic symbol min max unit 1 clkout period 2 2 initialize siu_eccr[ebdf] to meet maximum external bus frequency. t c 40.0 ? ns 2 clkout duty cycle t cdc 45% 55% t c 3 clkout rise time t crt ?? 3 3 refer to medium high voltage (mh) pad ac specification in ta b l e 1 8 . ns 4 clkout fall time t cft ?? 3 ns 5 clkout positive edge to output signal invalid or high z (hold time) t coh 2.0 ? ns 6 clkout positive edge to output signal valid (output delay) t cov ? 10.0 ns 7 input signal valid to clkout posedge (setup time) t cis 20.0 ? ns 8 clkout posedge to input signal invalid (hold time) t cih 0?ns 9 ale pulse width high time t alepwh 20 ? ns 10 ale fall to ad invalid t alead 2?ns 1 2 2 3 4 clkout vdde/2 vol_f voh_f
mpc5510 microcontroller family data sheet, rev. 3 electrical characteristics freescale semiconductor 44 figure 15. synchronous output timing 6 5 5 clkout bus 5 output signal output vdde/2 vdde/2 vdde/2 vdde/2 6 5 vdde/2 6 ad[0:31] bdip c s[0:3] oe rd_wr ta tea ts w e[0:3] addr[8:15]
electrical characteristics mpc5510 microcontroller family data sheet, rev. 3 freescale semiconductor 45 figure 16. synchronous input timing 7 8 clkout input bus 7 8 input signal vdde/2 vdde/2 vdde/2 ad[0:31] rd_wr ta tea ts
mpc5510 microcontroller family data sheet, rev. 3 electrical characteristics freescale semiconductor 46 figure 17. address latch enable (ale) timing 2.13.6 enhanced modular i/o subsystem (emios) table 24. emios timing num characteristic symbol min max unit 1 emios input pulse width t mipw 4?t cyc 2 emios output pulse width t mopw 1?t cyc 10 clkout vdde/2 vdde/2 ad[0:31] ts 9 vdde/2 ale
electrical characteristics mpc5510 microcontroller family data sheet, rev. 3 freescale semiconductor 47 2.13.7 deserial serial peripheral interface (dspi) table 25. dspi timing 1 1 dspi timing specified at vdde = 3.0v to 5.5v, t a = tl to th, and cl = 50pf with src = 0b11. num characteristic symbol 66 mhz unit min max 1 sck cycle time 2,3 2 the minimum sck cycle time restricts the baud rate sele ction for given system clock rate. these numbers are calculated based on two mpc55xx devices communicating over a dspi link. 3 the actual minimum sck cycle time is limited by pad performance. t sck 60 ? ns 2 pcs to sck delay 4 4 the maximum value is programmable in dspi_ctarx[pssck] and dspi_ctarx[cssck] t csc 20 ? ns 3 after sck delay 5 5 the maximum value is programmable in dspi_ctarx[pasc] a nd dspi_ctarx[asc] t asc 20 ? ns 4 sck duty cycle t sdc t sck /2 ?2ns t sck /2 + 2ns ns 5slave access time (ss active to sout driven) t a ? 25 ns 6 slave sout disable time (ss inactive to sout high-z or invalid) t dis ? 25 ns 7 pcsx to pcss time t pcsc 4?ns 8pcss to pcsx time t pasc 5?ns 9 data setup time for inputs master (mtfe = 0) slave master (mtfe = 1, cpha = 0) 6 master (mtfe = 1, cpha = 1) 6 this number is calculated assuming the smpl_pt bit field in dspi_mcr is set to 0b10. t sui 35 5 5 35 ? ? ? ? ns ns ns ns 10 data hold time for inputs master (mtfe = 0) slave master (mtfe = 1, cpha = 0) 6 master (mtfe = 1, cpha = 1) t hi ?4 10 26 ?4 ? ? ? ? ns ns ns ns 11 data valid (after sck edge) master (mtfe = 0) slave master (mtfe = 1, cpha=0) master (mtfe = 1, cpha=1) t suo ? ? ? ? 15 35 30 15 ns ns ns ns 12 data hold time for outputs master (mtfe = 0) slave master (mtfe = 1, cpha = 0) master (mtfe = 1, cpha = 1) t ho ?15 5.5 0 ?15 ? ? ? ? ns ns ns ns
mpc5510 microcontroller family data sheet, rev. 3 electrical characteristics freescale semiconductor 48 figure 18. dspi classic spi timing ? master, cpha = 0 figure 19. dspi classic spi timing ? master, cpha = 1 data last data first data first data data last data sin sout pcsx sck output 4 9 12 1 11 10 4 sck output (cpol=0) (cpol=1) 3 2 data last data first data sin sout 12 11 10 last data data first data sck output sck output pcsx 9 (cpol=0) (cpol=1)
electrical characteristics mpc5510 microcontroller family data sheet, rev. 3 freescale semiconductor 49 figure 20. dspi classic spi timing ? slave, cpha = 0 figure 21. dspi classic spi timing ? slave, cpha = 1 last data first data 3 4 1 data data sin sout ss 4 5 6 9 11 10 12 sck input first data last data sck input 2 (cpol=0) (cpol=1) 5 6 9 12 11 10 last data last data sin sout ss first data first data data data sck input sck input (cpol=0) (cpol=1)
mpc5510 microcontroller family data sheet, rev. 3 electrical characteristics freescale semiconductor 50 figure 22. dspi modified transfer format timing ? master, cpha = 0 figure 23. dspi modified transfer format timing ? master, cpha = 1 pcsx 3 1 4 10 4 9 12 11 sck output sck output sin sout first data data last data first data data last data 2 (cpol=0) (cpol=1) pcsx 10 9 12 11 sck output sck output sin sout first data data last data first data data last data (cpol=0) (cpol=1)
electrical characteristics mpc5510 microcontroller family data sheet, rev. 3 freescale semiconductor 51 figure 24. dspi modified transfer format timing ? slave, cpha = 0 figure 25. dspi modified transfer format timing ? slave, cpha = 1 figure 26. dspi pcs strobe (pcss ) timing last data first data 3 4 1 data data sin sout ss 4 5 6 9 11 10 sck input first data last data sck input 2 (cpol=0) (cpol=1) 12 5 6 9 12 11 10 last data last data sin sout ss first data first data data data sck input sck input (cpol=0) (cpol=1) pcsx 7 8 pcss
mpc5510 microcontroller family data sheet, rev. 3 package information freescale semiconductor 52 3 package information the latest package outline drawings are available on the product summary pages on our web site: http://www.freescale.com/powerpc . the following table lists the package case numb er per device. use these numbers in the web page?s ?keyword? search engine to find the latest package outline drawings. 4 product documentation documentation is available from a local freescale distributor, a freescale sales office, the fr eescale literature distribution center, or through the freescal e world-wide web address at http://www.freescal e.com/powerpc . table 26. package information package package case number 144 lqfp 98ass23177w 176 lqfp 98ass23479w 208 mapbga 98ars23882w
product documentation mpc5510 microcontroller family data sheet, rev. 3 freescale semiconductor 53 4.1 revision history table 27 summarizes revisions to this document. table 27. revision history of mpc5510 data sheet revision date substantive changes rev. 0 9/2007 initial release. preliminary content. rev. 1 6/2008 (note: change descriptions refer to locations in rev. 0.) changed mpc5516 to mpc5510 family where appropriate. modified figure 1. mpc5510 family block diagram. deleted table 1. mpc5510 family comparison, maximum feature set deleted table 2. mpc5510 peripheral multiplexing examples corrected pk0 and pk1 pin assignments on 208 mapbga (table 3 and figure 4). modified table 4, footnote 4. modified table 8. dc electrical specifications and table footnotes. modified table 9. operating currents and table footnotes. modified table 12. 3.3v high frequency external oscillator, row 5. modified table 14. 5v high frequency (16 mhz) internal rc oscillator, row 2. modified table 16. fmpll electrical specifications, row 4. modified table 17. eqadc conversion specif ications (operating) and table footnotes. modified table 18. flash program and erasespecifications, row 5. modified table 19. flash eeprom module life (full temperature range), row 1 modified table 28. package information. rev. 2 12/2008 (note: change descriptions refer to locations in rev. 1.) modified table 1. mpc5510 signal properties: added note to test signal. modified table 6. dc electrical specifications: rows 1b, 5, 8, 9, 10, 11, 16, 19, 25, and footnotes. modified table 7. operating currents: max column header, rows 1, 2, 3, 4, and footnotes. modified table 9. low voltage monitors: rows 2, 3, 4, 6. modified table 10. 3.3v high frequence external oscillator: row 1 added footnote, removed duplicate footnote #3. modified table 11. 5v low frequency (32 khz) external oscillator: row 1. modified table 12. 5v high frequency (16 mhz) internal rc oscillator: row 2. modified table 13. 5v low frequency (32 khz) internal rc oscillator: row 2. modified table 14. fmpll electrical specifications: rows 1 and 4; added two new rows. modified table 15. eqadc conversion specifications (operating): rows 5, 6, 7, 8, 10, 11, and footnotes. modified figure 5. pad output delay: moved the dashed horizontal line up so that it crosses the signal midway between top and bottom. rev. 3 3/2009 (note: change descriptions refer to locations in rev. 2.) modified table 4. thermal characteristics: all values in 208 mapbga column. modified table 6. dc electrical specificatio ns: spec #1c, added footnote; spec #25, added footnote. modified table 7. operating currents; spec #5. modified table 9. low voltage monitors; spec #1. modified table 14. fmpll electrical specif ications: updated footnote 3; added spec #10a. modified table 15. eqadc conversion specific ations (operating): added another footnote. modified table 16: flash program and erase specifications: updated spec #7. modified figure 5: pad output delay: adjusted lower timing diagram. modified figure 8: jtag test clock input timing; updated so that it matche s the spec definitions.
document number: mpc5510 rev. 3 3/2009 how to reach us: home page: www.freescale.com web support: http://www.freescale.com/support usa/europe or locations not listed: freescale semiconductor, inc. technical information center, el516 2100 east elliot road tempe, arizona 85284 1-800-521-6274 or +1-480-768-2130 www.freescale.com/support europe, middle east, and africa: freescale halbleiter deutschland gmbh technical information center schatzbogen 7 81829 muenchen, germany +44 1296 380 456 (english) +46 8 52200080 (english) +49 89 92103 559 (german) +33 1 69 35 48 48 (french) www.freescale.com/support japan: freescale semiconductor japan ltd. headquarters arco tower 15f 1-8-1, shimo-meguro, meguro-ku, tokyo 153-0064 japan 0120 191014 or +81 3 5437 9125 support.japan@freescale.com asia/pacific: freescale semiconductor china ltd. exchange building 23f no. 118 jianguo road chaoyang district beijing 100022 china +86 10 5879 8000 support.asia@freescale.com for literature requests only: freescale semiconductor literature distribution center p.o. box 5405 denver, colorado 80217 1-800-441-2447 or +1-303-675-2140 fax: +1-303-675-2150 ldcforfreescalesemiconductor@hibbertgroup.com information in this document is provid ed solely to enable system and software implementers to use freescale semiconduc tor products. there are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document. freescale semiconductor reserves the right to make changes without further notice to any products herein. freescale semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does freescale semiconductor assume any liability arising out of the application or use of any product or circuit, and specif ically disclaims any and all liability, including without limitation consequential or incidental damages. ?typical? parameters that may be provided in freescale semiconductor data s heets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including ?typicals?, must be validated for each customer application by customer?s technical experts. freescale semiconductor does not convey any license under its patent rights nor the rights of others. freescale semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applic ations intended to support or sustain life, or for any other application in which the failure of the freescale semiconductor product could create a situation where personal injury or death may occur. should buyer purchase or use freescale semiconductor products for any such unintended or unauthorized application, buyer shall indemnify and hold freescale semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that freescale semiconductor was negligent regarding the design or manufacture of the part. rohs-compliant and/or pb-free versions of freescale products have the functionality and electrical characteristics as thei r non-rohs-compliant and/or non-pb-free counterparts. for further information, see http://www.freescale.com or contact your freescale sales representative. for information on freescale?s environmental products program, go to http://www.freescale.com/epp . freescale? and the freescale logo are trademarks of freescale semiconductor, inc. all other product or service names are the property of their respective owners. the power architecture and power.org word marks and the power and power.org logos and related marks are trademarks and service marks licensed by power.org. ? freescale semiconductor, inc. 2007-2009. all rights reserved.

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