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| digital equipment corporation maynard, massachusetts http://www.digital.com/semiconductor digital semiconductor 21140a pci fast ethernet lan controller data sheet order number: ecCqn7pfCte revision/update information : this is a revised document. it supersedes the digital semiconductor 21140a pci fast ethernet lan controller data sheet , ecCqn7peCte. . hardware version: this document describes the 21140Cad, the 21140Cae, and the 21140Caf.
important notice as of may 17, 1998, digital equipment corporations strongarm, pci bridge, and networking component businesses, along with the chip fabrication facility in hudson, massachusetts, were acquired by intel corporation and transferred to intel massachusetts, inc. as a result of this transaction, certain references to web sites, telephone numbers, and fax numbers have changed in the documentation. this information will be updated in the next version of this manual. copies of documents that have an ordering number and are referenced in this document, or other intel literature may be obtained by calling 1-800-332-2717 or by visiting intels website for developers at: http://developer.intel.com the intel massachusetts customer technology center continues to service your strongarm product, bridge product, and network product technical inquiries. please use the following information lines for support: for documentation and general information: intel massachusetts information line united states: 1C800C332C2717 outside united states: 1C303-675-2148 electronic mail address: techdoc@intel.com for technical support: intel massachusetts customer technology center phone (u.s. and international): 1C978C568C7474 fax: 1C978C568C6698 electronic mail address: techsup@intel.com december 1997 while digital believes the information included in this publication is correct as of the date of publication, it is subject to change without notice. this data sheet, including associated product update information, defines a particular variant of this product. please read the support, products, and documentation section in this document to determine how to obtain current product update and errata information. digital equipment corporation makes no representations that the use of its products in the manner described in this publication will not infringe on existing or future patent rights, nor do the descriptions contained in this publication imply the granting of licenses to make, use, or sell equipment or software in accordance with the description. ?digital equipment corporation 1997. all rights reserved. printed in u.s.a. digital, digital semiconductor, and the digital logo are trademarks of digital equipment corporation. digital semiconductor is a digital equipment corporation business. ieee is a registered trademark of the institute of electrical and electronic engineers, inc. microwire is a registered trademark of bankamerica corporation. all other trademarks and registered trademarks are the property of their respective owners. iii contents 1 21140a overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1.1 general description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1.2 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 1.3 microarchitecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2.1 signal reference tables. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.2 pin tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 2.3 signal grouping by function. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3 electrical and environmental specifications . . . . . . . . . . . . . . . . . . 22 3.1 voltage limit ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 3.2 temperature limit ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 3.3 supply current and power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 3.4 pci electrical parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 3.4.1 pci i/o voltage specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 3.4.2 pci reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 3.4.3 pci clock specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 3.4.4 other pci signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 3.5 serial, mii/sym, boot rom, serial rom, and general-purpose port interface specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 3.6 serial network port timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 3.6.1 serial 10-mb/s timingtransmit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 3.6.2 serial 10-mb/s timingcollision. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 3.6.3 serial 10 mb/s timingreceive, start of packet . . . . . . . . . . . . . . . . . . . . . 30 3.6.4 serial 10-mb/s timingreceive, start, and end of packet . . . . . . . . . . . . . 31 3.7 mii/sym port timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 3.7.1 mii/sym 10/100-mb/s and 10-mb/s timingtransmit . . . . . . . . . . . . . . . . . 32 3.7.2 mii/sym 10/100-mb/s timingreceive . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 3.7.3 mii/sym 10/100-mb/s timingsignal detect . . . . . . . . . . . . . . . . . . . . . . . . 35 3.7.4 mii/sym 10/100-mb/s timingreceive error. . . . . . . . . . . . . . . . . . . . . . . . 36 3.7.5 mii/sym 10/100-mb/s timingcarrier sense and collision . . . . . . . . . . . . . 36 3.8 boot rom port timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 3.8.1 boot rom read timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 3.8.2 boot rom write timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 3.9 serial rom port timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 3.10 external register timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 3.11 joint test action grouptest access port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 3.11.1 jtag dc specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 3.11.2 jtag boundary-scan timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 iv 4 mechanical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 a support, products, and documentation . . . . . . . . . . . . . . . . . . . . . . . 45 v figures 1 21140a block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2 21140a pinout diagram (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 3 pci reset timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 4 pci clock specification timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 5 timing diagram for other pci signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 6 serial network port timing diagramtransmit . . . . . . . . . . . . . . . . . . . . . . . . . . 28 7 serial network port timing diagramcollision . . . . . . . . . . . . . . . . . . . . . . . . . . 29 8 serial network port timing diagramreceive, start of packet. . . . . . . . . . . . . . 30 9 serial network port timing diagramreceive, end of packet . . . . . . . . . . . . . . 31 10 mii/sym port timing diagramtransmit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 11 mii/sym port timing diagramreceive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 12 mii/sym port timing diagramsignal detect . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 13 mii/sym port timing diagramreceive error. . . . . . . . . . . . . . . . . . . . . . . . . . . 36 14 mii/sym port timing diagramcarrier sense and collision . . . . . . . . . . . . . . . . 36 15 boot rom read timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 16 boot rom write timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 17 serial rom port timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 18 external register read timing diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 19 external register write timing diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 20 jtag boundary-scan timing diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 21 144-pin pqfp package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 vi tables 1 index to pinout tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2 logic signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 3 power pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 4 functional description of 21140a signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 5 input pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 6 output pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 7 input/output pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 8 open drain pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 9 signal functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 10 voltage limit ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 11 temperature limit ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 12 supply current and power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 13 i/o voltage specifications for 5.0-v levels. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 14 i/o voltage specification for 3.3-v levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 15 pci reset timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 16 pci clock specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 17 other pci signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 18 serial, mii/sym, boot rom, serial rom, and general-purpose port . . . . . . . . . 27 19 serial network port timingtransmit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 20 serial network port timingcollision . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 21 serial network port timingreceive, start, and end of packet . . . . . . . . . . . . . 31 22 mii/sym port timingtransmit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 23 mii/sym port timingreceive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 24 mii/sym port timingsignal detect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 25 mii/sym port timingreceive error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 26 mii/sym port timingcarrier sense and collision . . . . . . . . . . . . . . . . . . . . . . . 36 27 boot rom read timing specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 28 boot rom write timing specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 29 serial rom port timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 30 external register timing specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 31 jtag dc specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 32 jtag interface signal timing relationships. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 33 144-pin pqfp dimensional attributes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 21140a overview 1 1 21140a overview the digital semiconductor 21140a pci fast ethernet lan controller (21140a) supports the peripheral component interconnect (pci) bus. it provides a direct interface connection to the pci and adapts easily to most other standard buses. the 21140a software interface and data structures are optimized to minimize the host cpu load and to allow for maximum flexibility in the buffer descriptor management. the 21140a contains large onchip fifos, so no additional onboard memory is required. the 21140a provides an upgradable boot rom inter face. the 21140a has several additional features that are not available on the 21140, yet it remains pin and software compatible with the 21140. 1.1 general description the 21140a int erfaces with the pci bus by using onchip control and status registers (csrs), and a shared cpu memory area that is set up mainly during initialization. this minimizes the processor involvement in the 21140a operation during normal reception and transmission. traffic on the pci bus is also minimized by filtering out received runt frames and by automatically retransmitting collided frames without needing to repeat a fetch from shared memory. the 21140a is compliant with revisions 2.0 and 2.1 of the pci local bus specification . on the network side, the 21140a provides two ports: a serial standard 7-wire (srl) 10-mb/s port and a media-independent interface/symbol (mii/sym) 10/100-mb/s port. the 10-mb/s port provides a di rect interface to the external 10-mb/s front-end decoder (endec). the 10/100-mb/s port supports two operational modes: ? a direct interface to the external 10/ 100-mb/s endec. the 21140a includes the onchip physical coding sublayer (pcs) and the scrambler for efficient 100base-t (cat5 cable) implementation. ? a full implementation of the mii standard. the 21140a is also capable of functioning in a full-duplex environment for both the 10-mb/s and 10/100-mb/s ports. 2 21140a overview features 1.2 features the 21140a has the following features: ? offers a single-chip fast ethernet controller for pci local bus: - provides a glueless connection to the pci bus - supports two network ports: 10 mb/s and 10/100 mb/s ? provides a standard 10/100-mb/s mii supporting cat3 unshielded twisted-pair (utp), cat5 utp, shielded twisted-pair (stp) and fiber cables ? contains onchip scrambler and pcs for cat5 to significantly reduce cost of 100base-t solutions ? supports full-duplex operation on both 10-mb/s and 10/100-mb/s ports ? provides external and internal loopback capability on both ports ? contains a variety of flexible address filtering modes (including pe rfect, hash tables, inverse perfect, and promisc uous): - 16 perfect addresses (normal or inverse filtering) - 512 hash-filtered addresses - 512 hash-filtered multicast addresses and one perfect address - pass all multicast - promiscuous - pass all incoming packets with a status report ? offers a unique, patented solution to ethernet capture-effect problem ? contains large independent receive and transmit fifos; no additional onboard memory required ? includes a powerful onchip direct memory access (dma) with programmable burst size providing for low cpu utilization ? implements unique, patent-pending intelligent arbitration between dma channels preventing underflow or ov erflow ? supports pci clock frequency from dc to 33 mhz; network operational with pci clock from 20 mhz to 33 mhz ? supports an unlimited pci burst 21140a overview 3 microarchitecture ? supports pci read multiple command ? supports early interrupts on transmit and receive for improved performance ? implements low-power management with two power-saving modes (sleep or snooze) ? supports both pci 5.0-v and 3.3-v signaling environments ? supports either big or little endian byte ordering for bu ffers and descriptors ? contains 8-bit, general-purpose, programmable register and corresponding i/o pins ? provides led support for various network activity indications ? provides microwire interface for serial rom (1k and 4k eeprom) ? provides an upgradable boot rom interface of up to 256kb ? supports automatic loading of subsystem vendor id and subsystem id from serial rom to configuration register ? implements jtag-compatible test- access port with boundary-scan pins ? supports ieee 802.3, ansi 8802-3, and ethernet standards ? implements low-power, 3.3-v complementary metal-oxide semiconductor (cmos) process technology ? supports pci write and invalidate, and read line commands 1.3 microarchitecture the following list describes the 21140a hardware components, and figure 1 shows a block diagram of the 21140a: ? pci interfaceincludes all interface functions to the pci bus; handles all interconnect control signals; and executes pci dma and i/o transactions. ? dmacontains dual receive and transmit controller; handles data transfers between cpu memory and onchip memory. ? fifoscontains two fifos for receive and transmit; supports automatic packet deletion on receive (runt packets or after a collision) and packet retransmission after a collision on transmit. ? txmhandles all csma/cd mac 1 transmit operations, and transfers data from transmit fifo to the endec for transmission. 4 21140a overview microarchitecture ? rxmhandles all csma/cd receive operations, and transfers the data from the endec to the receive fifo. ? physical coding sublayerimplements the encoding and decoding sublayer of the 100base-tx (cat5) specification, including the squelch. ? scrambler/descramblerimplements the twisted-pair physical layer medium dependent (tp-pmd) scrambler/descrambler scheme. ? general-purpose registerenables software to use for input or output functions. ? serial interfacepro vides a 7-wire conventional int erface to the ethernet endec components. ? mii/sym interfaceprovides a full mii signal interface and a direct inte rface to the 10/100-mb/s endec for cat5. ? serial rom portprovides a direct inter face to the microwire rom for storage of the ethernet address and system parameters. ? boot rom portprovides an interface to perform read and write operations to the boot rom; supports accesses to bytes or longword (32-bit). also provides the ability to connect an external 8-bit register to the boot rom port. 1 media access control 21140a overview 5 microarchitecture figure 1 21140a block diagram rx fifo 32 16 4 1 4 1 16 10 mb/s serial interface physical coding sublayer mii/sym interface scrambler/ descrambler l j - 050 42.ai4 dma 8 general- purpose register board control signals 10 mb/s or 100 mb/s tx fifo 32 4 4 rxm txm 32 serial rom port serial rom 32 boot rom port boot rom/ external register pci pci interface 32 6 pinout 2 pinout the 21140a is packaged in a 144-pin plastic quad flat pack (pqfp). the tables in this section provide a description of the pins and their respective signal definitions. table 1 lists the tables in this section. figure 2 shows the 21140a pinout. table 1 index to pinout tables for this information... refer to... logic signals table 2 power pins table 3 functional signals description table 4 input pins table 5 output pins table 6 input/output pins table 7 open drain pins table 8 signal functions table 9 pinout 7 figure 2 21140a pinout diagram (top view) lj-04479.ai4 vss vdd mii_mdc mii_mdio nc br_a<1> br_a<0> br_ce_l br_ad<7> vdd br_ad<6> vss br_ad<5> br_ad<4> br_ad<3> br_ad<2> br_ad<1> br_ad<0> vss gep<7> gep<6> gep<5> gep<4> vdd sr_ck sr_di sr_do vdd vss vdd_clamp mii/sym_tclk rcv_match vdd mii/sym_rclk mii_crs mii_clsn mii_err sd mii_dv tdo tdi tms tck srl_txen srl_tclk srl_txd srl_rclk srl_rxen srl_rxd srl_clsn mii/srl sym_txd<4> mii/sym_txd<3> mii/sym_txd<2> vdd vss mii/sym_txd<1> mii/sym_txd<0> mii/sym_txen sym_link ad<9> vss ad<8> vdd ad<3> ad<2> ad<1> ad<0> vss vss c_be_l<2> frame_l irdy_l trdy_l devsel_l stop_l vdd perr_l serr_l par c_be_l<1> vss ad<15> ad<14> ad<13> vss ad<12> ad<11> vdd ad<10> 1 2 3 4 5 6 7 8 9 11 10 12 13 14 15 16 17 18 19 20 21 22 23 24 31 32 33 34 35 36 108 107 106 105 104 103 102 101 100 98 99 97 96 95 94 93 92 91 90 89 88 87 86 85 78 77 76 75 74 73 6 7 6 8 6 9 7 0 3 7 3 8 4 0 4 1 4 2 4 3 4 4 4 57 6 8901234 4 4 44555555 5 5 6 5 7 5 8 5 9 6 0 7 1 7 2 3 9 1 3 4 1 2 3 1 2 2 1 2 1 1 1 4 1 1 3 1 1 2 1 1 0 1 0 9 1 1 1 1 4 4 1 4 3 1 4 2 1 4 1 1 4 0 1 3 9 1 3 8 1 3 7 1 3 6 1 3 5 1 3 3 1 3 2 1 3 1 1 3 0 1 2 9 1 2 8 1 2 7 1 2 6 1 2 5 1 2 4 21140a vss gep<3> gep<2> gep<1> gep<0> sr_cs vdd c_be_l<3> int_l rst_l vdd vss pci_clk gnt_l req_l vss ad<30> ad<31> vss ad<29> ad<28> vss ad<27> ad<26> vdd ad<25> ad<24> idsel vss ad<23> vdd vss vss ad<17> ad<16> vss ad<22> ad<21> ad<20> vdd ad<19> ad<18> 25 26 27 28 29 30 84 83 82 81 80 79 vss sym_rxd<4> mii/sym_rxd<3> mii/sym_rxd<1> mii/sym_rxd<0> mii/sym_rxd<2> c_be_l<0> ad<7> ad<6> ad<5> ad<4> vss 6 1 6 2 6 3 6 4 6 5 6 6 1 2 0 1 1 9 1 1 8 1 1 6 1 1 5 1 1 7 8 pinout signal reference tables 2.1 signal reference tables table 2 provides an alphabetical list of the 21140a logic names and their pin numbers. table 3 provides a list of the 21140a power pin numbers. table 2 logic signals (sheet 1 of 2) signal pin number signal pin number signal pin number ad<0> 72 ad<24> 20 frame_l 39 ad<1> 71 ad<25> 19 gep<0> 80 ad<2> 69 ad<26> 17 gep<1> 81 ad<3> 68 ad<27> 16 gep<2> 82 ad<4> 66 ad<28> 14 gep<3> 83 ad<5> 65 ad<29> 13 gep<4> 86 ad<6> 63 ad<30> 11 gep<5> 87 ad<7> 62 ad<31> 10 gep<6> 88 ad<8> 60 br_a<0> 102 gep<7> 89 ad<9> 58 br_a<1> 103 gnt_l 7 ad<10> 57 br_ad<0> 91 idsel 22 ad<11> 55 br_ad<1> 92 int_l 1 ad<12> 54 br_ad<2> 93 irdy_l 40 ad<13> 52 br_ad<3> 94 mii_clsn 112 ad<14> 51 br_ad<4> 95 mii_crs 113 ad<15> 50 br_ad<5> 96 mii_dv 111 ad<16> 35 br_ad<6> 99 mii_err 110 ad<17> 34 br_ad<7> 100 mii_mdc 106 ad<18> 30 br_ce_l 101 mii_mdio 105 ad<19> 29 c_be_l<0> 61 mii/srl 133 ad<20> 27 c_be_l<1> 48 mii/sym_rclk 114 ad<21> 26 c_be_l<2> 38 mii/sym_rxd<0> 115 ad<22> 25 c_be_l<3> 21 mii/sym_rxd<1> 116 pinout 9 signal reference tables ad<23> 24 devsel_l 42 mii/sym_rxd<2> 117 mii/sym_rxd<3> 118 req_l 8 srl_tclk 139 mii/sym_tclk 123 rst_l 2 srl_txd 138 mii/sym_txd<0> 126 sd 109 srl_txen 140 mii/sym_txd<1> 127 serr_l 46 stop_l 43 mii/sym_txd<2> 130 sr_ck 78 sym_link 124 mii/sym_txd<3> 131 sr_cs 79 sym_rxd<4> 119 mii/sym_txen 125 sr_di 77 sym_txd<4> 132 nc 104 sr_do 76 tck 141 par 47 srl_clsn 134 tdi 143 pci_clk 5 srl_rclk 137 tdo 144 perr_l 45 srl_rxd 135 tms 142 rcv_match 122 srl_rxen 136 trdy_l 41 table 3 power pins signal pin numbers signal pin numbers vdd (3.3 v) 3, 6, 18, 28, vss ( gnd ) 4, 9, 12, 15, 31, 44, 56, 67, 23, 32, 33, 36, 75, 85, 98, 107, 37, 49, 53, 59, 121, 129 64, 70, 74, 84, 90, 97, 108, 120, 128 vdd_clamp (5.0 v or 3.3 v) 73 table 2 logic signals (sheet 2 of 2) signal pin number signal pin number signal pin number 10 pinout signal reference tables table 4 provides a functional description of each of the 21140a signals. these signals are listed alphabetically. the functional grouping of each pin is l isted in section 2.3. the following terms describe the 21140a pinout: ? address phase address and appropriate bus commands are driven during this cycle. ? data phase data and the appropriate byte enable codes are driven during this cycle. ? _l all pin names with the _l suffix are asserted low. the following abbreviations are used in table 4: i = input o = output i/o = input/output o/d = open drain p = power table 4 functional description of 21140a signals (sheet 1 of 9) signal type pin number description ad<31:0> i/o see table 2. 32-bit pci address and data lines. address and data bits are multiplexed on the same pins. during the first clock cycle of a transaction, the address bits contain a physical address (32 bits). during subsequent clock cycles, these same lines contain 32 bits of data. a 21140a bus transaction consists of an address phase followed by one or more data phases. the 21140a supports both read and write bursts (in master operation only). little and big endian byte ordering can be used. br_a<0> o 102 boot rom address line bit 0. in a 256kb configuration, this pin also carries in two consecutive address cycles, boot rom address bits 16 and 17. pinout 11 signal reference tables br_a<1> o 103 boot rom address line bit 1. this pin also latches the boot rom address and control lines by the two external latches. br_ad<7:0> i/o see table 2. boot rom address and data multiplexed lines bits 7 through 0. in the first of two consecutive address cycles, these lines contain the boot rom address bits 7 through 2, oe_l and we_l ; followed by boot rom address bits 15 through 8 in the second cycle. during the data cycle, bits 7 through 0 contain data. during operation with the external register, these lines are used to carry data bits 7 through 0 to and from the external register. br_ce_l o 101 boot rom or external register chip enable. this pin has an internal 5 k w pull-up resistor. c_be_l<3:0> i/o see table 2. bits 0 through 3 of the bus command and byte enable lines. bus command and byte enable are multiplexed on the same pci pins. during the address phase of the transaction, these 4 bits provide the bus command. during the data phase, these 4 bits provide the byte enable. the byte enable determines which byte lines carry valid data. for example, bit 0 applies to byte 0, and bit 3 applies to byte 3. devsel_l i/o 42 device select is asserted by the target of the current bus access. when the 21140a is the initiator of the current bus access, it expects the target to assert devsel_l within five bus cycles, confirming the access. if the target does not assert devsel_l within the required bus cycles, the 21140a aborts the cycle. to meet the timing requirements, the 21140a asserts this signal in a medium speed (within two bus cycles). table 4 functional description of 21140a signals (sheet 2 of 9) signal type pin number description 12 pinout signal reference tables frame_l i/o 39 the frame_l signal is driven by the 21140a (bus master) to indicate the beginning and duration of an access. the frame_l signal asserts to indicate the beginning of a bus transaction. while frame_l is asserted, data transfers continue. the frame_l signal deasserts to indicate that the next data phase is the final data phase transaction. gep<7:0> i/o see table 2. general-purpose pins can be used by software as either status pins or control pins. these pins can be configured by software to perform either input or output functions. gnt_l i 7 bus grant asserts to indicate to the 21140a that access to the bus is granted. idsel i 22 initialization device select asserts to indicate that the host is issuing a configuration cycle to the 21140a. int_l o/d 1 interrupt request asserts when one of the appropriate bits of csr5 sets and causes an interrupt, provided that the corresponding mask bit in csr7 is not asserted. interrupt request deasserts by writing a 1 into the appropriate csr5 bit. if more than one interrupt bit is asserted in csr5 and the host does not clear all input bits, the 21140a deasserts int_l for one cycle to support edge-triggered systems. this pin must be pulled up by an external resistor. table 4 functional description of 21140a signals (sheet 3 of 9) signal type pin number description pinout 13 signal reference tables irdy_l i/o 40 initiator ready indicates the bus masters ability to complete the current data phase of the transaction. a data phase is completed on any rising edge of the clock when both irdy_l and target ready trdy_l are asserted. wait cycles are inserted until both irdy_l and trdy_l are asserted together. when the 21140a is the bus master, irdy_l is asserted during write operations to indicate that valid data is present on the 32-bit ad lines. during read operations, the 21140a asserts irdy_l to indicate that it is ready to accept data. mii_clsn i 112 collision detected is asserted when detected by an external physical layer protocol (phy) device. mii_crs i 113 carrier sense is asserted by the phy when the media is active. mii_dv i 111 data valid is asserted by an external phy when receive data is present on the mii/sym_rxd lines and is deasserted at the end of the packet. this signal should be synchronized with the mii/sym_rclk signal. mii_err i 110 receive error asserts when a data decoding error is detected by an external phy device. this signal is synchronized to mii/sym_rclk and can be asserted for a minimum of one receive clock. when asserted during a packet reception, it sets the cyclic redundancy check (crc) error bit in the receive descriptor (rdes0). mii_mdc o 106 mii management data clock is sourced by the 21140a to the phy devices as a timing reference for the transfer of information on the mii_mdio signal. table 4 functional description of 21140a signals (sheet 4 of 9) signal type pin number description 14 pinout signal reference tables mii_mdio i/o 105 mii management data input/output transfers control information and status between the phy and the 21140a. mii/srl o 133 indicates the selected port: srl or mii/sym. when asserted, the mii/sym port is active. when deasserted, the srl port is active. mii/sym_rclk i 114 supports either the 25-mhz or 2.5-mhz receive clock. this clock is recovered by the phy. mii/sym_rxd<3:0> i see table 2. four parallel receive data lines when mii mode is selected. this data is driven by an external phy that attached the media and should be synchronized with the mii/sym_rclk signal. mii/sym_tclk i 123 supports the 25-mhz or 2.5-mhz transmit clock supplied by the external physical layer medium dependent (pmd) device. this clock should always be active. mii/sym_txd<3:0> o see table 2. four parallel transmit data lines. this data is synchronized to the assertion of the mii/sym_tclk signal and is latched by the external phy on the rising edge of the mii/sym_tclk signal. mii_txen o 125 transmit enable signals that the transmit is active to an external phy device. in pcs mode (csr6<23>), this signal reflects the transmit activity of the mac sublayer. nc o 104 no connection. par i/o 47 parity is calculated by the 21140a as an even parity bit for the 32-bit ad and 4-bit c_be_l lines. during address and data phases, parity is calculated on all the ad and c_be_l lines whether or not any of these lines carry meaningful information. table 4 functional description of 21140a signals (sheet 5 of 9) signal type pin number description pinout 15 signal reference tables pci_clk i 5 the clock provides the timing for the 21140a related pci bus transactions. all the bus signals are sampled on the rising edge of pci_clk . the clock frequency range is between 25 mhz and 33 mhz. perr_l i/o 45 parity error asserts when a data parity error is detected. when the 21140a is the bus master and a parity error is detected, the 21140a asserts both csr5 bit 13 (system error) and cfcs bit 24 (data parity report). next, it completes the current data burst transaction, then stops operation. after the host clears the system error, the 21140a continues its operation. the 21140a asserts perr_l when a data parity error is detected in either master-read or slave- write operations. this pin must be pulled up by an external resistor. rcv_match o 122 receive match indication is asserted when a received packet has passed address recognition. req_l o 8 bus request is asserted by the 21140a to indicate to the bus arbiter that it wants to use the bus. rst_l i 2 resets the 21140a to its initial state. this signal must be asserted for at least 10 active pci clock cycles. when in the reset state, all pci output pins are put into tristate and all pci o/d signals are floated. sd i 109 signal detect indication supplied by an external physical layer medium dependent (pmd) device. table 4 functional description of 21140a signals (sheet 6 of 9) signal type pin number description 16 pinout signal reference tables serr_l o/d 46 if an address parity error is detected and cfcs bit 8 ( serr_l enable) is enabled, the 21140a asserts both serr_l (system error) and cfcs bit 30 (signal system error). when an address parity error is detected, system error asserts two clocks after the failing address. this pin must be pulled up by an external resistor. sr_ck o 78 serial rom clock signal. sr_cs o 79 serial rom chip-select signal. this pin has an internal 2 k w pull-down resistor. sr_di o 77 serial rom data-in signal. sr_do i 76 serial rom data-out signal. this pin has an internal 5 k w pull-up resistor. srl_clsn i 134 collision detect signals a collision occurrence on the ethernet cable to the 21140a. it may be asserted and deasserted asynchronously by the external endec to the receive clock. srl_rclk i 137 receive clock carries the recovered receive clock supplied by an external endec. during idle periods, srl_rclk may be inactive. srl_rxd i 135 receive data carries the input receive data from the external endec. the incoming data should be synchronous with the srl_rclk signal. srl_rxen i 136 receive enable signals activity on the ethernet cable to the 21140a. it is asserted when receive data is present on the ethernet cable and is deasserted at the end of a frame. it may be asserted and deasserted asynchronously to the receive clock ( srl_rclk) by the external endec. table 4 functional description of 21140a signals (sheet 7 of 9) signal type pin number description pinout 17 signal reference tables srl_tclk i 139 transmit clock carries the transmit clock supplied by an external endec. this clock must always be active (even during reset). srl_txd o 138 transmit data carries the serial output data from the 21140a. this data is synchronized to the srl_tclk signal. srl_txen o 140 transmit enable signals an external endec that the 21140a transmit is in progress. stop_l i/o 43 stop indicator indicates that the current target is requesting the bus master to stop the current transaction. the 21140a responds to the assertion of stop_l when it is the bus master, either to disconnect, retry, or abort. sym_link o 124 indicates that the descrambler is locked to the input data signal. sym_rxd<4> i 119 receive data, together with the four receive lines mii/sym_rxd<3:0> , provide five parallel lines of data in symbol form for use in pcs mode (100base-t, csr6<23>). this data is driven by an external pmd device and should be synchronized to the mii/sym_rclk signal. sym_txd<4> o 132 transmit data, together with the four transmit lines mii/sym_txd<3:0> , provide five parallel lines of data in symbol form for use in pcs mode (100base-t, csr6<23>). this data is synchronized on the rising edge of the mii/sym_tclk signal. tck i 141 jtag clock shifts state information and test data into and out of the 21140a during jtag test operations. this pin should not be left unconnected. tdi i 143 jtag data in is used to serially shift test data and instructions into the 21140a during jtag test operations. this pin has an internal pull-up resistor and can be left unconnected. table 4 functional description of 21140a signals (sheet 8 of 9) signal type pin number description 18 pinout pin tables 2.2 pin tables this section contains four types of pin tables: ? table 5 lists the input pins. ? table 6 lists the output pins. ? table 7 lists the input/output pins. ? table 8 lists the open drain pins. tdo o 144 jtag data out is used to serially shift test data and instructions out of the 21140a during jtag test operations. tms i 142 jtag test mode select controls the state operation of jtag testing in the 21140a. this pin has an internal pull-up resistor and can be left unconnected. trdy_l i/o 41 target ready indicates the target agents ability to complete the current data phase of the transaction. a data phase is completed on any clock when both trdy_l and irdy_l are asserted. wait cycles are inserted until both irdy_l and trdy_l are asserted together. when the 21140a is the bus master, target ready is asserted by the bus slave on the read operation, indicating that valid data is present on the ad lines. during a write cycle, it indicates that the target is prepared to accept data. vdd p see table 3. 3.3-v supply input voltage. vdd_clamp p 73 5.0-v reference for 5.0-v signaling environments and 3.3 v for 3.3-v signaling environments. vss p see table 3. ground pins. table 4 functional description of 21140a signals (sheet 9 of 9) signal type pin number description pinout 19 pin tables table 5 input pins signal active level signal active level gnt_l low sd high idsel high sr_do mii_clsn high srl_clsn high mii_crs high srl_rclk mii_dv high srl_rxd mii_err high srl_rxen high mii/sym_rclk srl_tclk mii/sym_rxd<3:0> sym_rxd<4> mii/sym_tclk tck pci_clk tdi rst_l low tms table 6 output pins signal active level signal active level br_a<0> high req_l low br_a<1> high sr_ck br_ce_l low sr_cs high mii_mdc sr_di mii/srl srl_txd mii/sym_txd<3:0> srl_txen high mii_txen high sym_link high nc sym_txd<4> rcv_match high tdo high table 7 input/output pins (sheet 1 of 2) signal active level signal active level ad<31:0> irdy_l low br_ad<7:0> mii_mdio c_be_l<3:0> low par 20 pinout signal grouping by function 2.3 signal grouping by function table 9 lists the signals according to their interface function. devsel_l low perr_l low frame_l low stop_l low gep<7:0> trdy_l low table 8 open drain pins signal active level signal active level int_l low serr_l low table 9 signal functions (sheet 1 of 2) interface function signal pci address and data ad<31:0>, par arbitration gnt_l, req_l bus command and byte enable c_be_l<3:0> device select devsel_l, idsel error reporting perr_l, serr_l interrupt int_l system pci_clk, rst_l control signals frame_l, stop_l, irdy_l, trdy_l mii/symbol transmit data lines mii/sym_txd<3:0> network port receive data lines mii/sym_rxd<3:0> transmit, receive clocks mii/sym_tclk, mii/sym_rclk sym mode sym_rxd<4>, sym_txd<4> signal detection sd table 7 input/output pins (sheet 2 of 2) signal active level signal active level pinout 21 signal grouping by function transmit enable mii_txen collision detect mii_clsn error reporting mii_err data control mii_dv, mii_crs mii management data clock mii_mdc mii management data input/output mii_mdio serial network port transmit and receive data srl_txd, srl_rxd transmit control srl_txen, srl_tclk receive control srl_rxen, srl_rclk collision detect srl_clsn miscellaneous led indicators rcv_match, sym_link general-purpose pins gep<7:0> mii/sym and serial port select mii/srl test access port jtag test operations tck, tdi, tdo, tms serial rom port serial rom sr_ck, sr_cs, sr_di, sr_do boot rom rom interface br_a<1:0>, br_ad<7:0>, br_ce_l power 3.3-v and 5.0-v supply input vdd, vdd_clamp ground vss table 9 signal functions (sheet 2 of 2) interface function signal 22 electrical and environmental specifications voltage limit ratings 3 electrical and environmental specifications this section contains the electrical and environmental specifications for the 21140a. caution: stresses greater than the maximum or less than the minimum ratings can cause permanent damage to the 21140a. exposure to the maximum or minimum ratings for extended periods of time lessen the reliability of the 21140a. 3.1 voltage limit ratings table 10 lists the voltage limit ratings. 3.2 temperature limit ratings table 11 lists the temperature limit ratings. 1 in the 3.3-v signalling environment, vdd_clamp must not be more than +0.3 v above vdd . table 10 voltage limit ratings parameter minimum maximum power supply voltage +3.0 v +3.6 v vdd_clamp (3.3 v) 1 +3.0 v +3.6 v vdd_clamp (5.0 v) +4.75 v +5.25 v esd protection voltage 2000 v table 11 temperature limit ratings parameter minimum maximum storage temperature C55 c+125 c operating temperature 0 c70 c electrical and environmental specifications 23 supply current and power dissipation 3.3 supply current and power dissipation the values in table 12 are estimates based on a pci clock frequency of 33 mhz and a network data rate of 10 mb/s for srl and 10/100 mb/s for mii. 3.4 pci electrical parameters this section describes the pci characteristics for the 21140a. 3.4.1 pci i/o voltage specifications the 21140a meets the i/o voltage specifications listed in table 13 and table 14. 1 typical: vdd = 3.3 v, ta = 25c. 2 maximum: vdd = 3.6 v, ta = 0c. 1 input leakage currents include high-impedance output leakage for all bidirectional buffers with tristate outputs. 2 signals without pull-up resistors have a low output current of 3 ma. signals requiring pull-up resistors (including frame_l , trdy_l , irdy_l , devsel_l , stop_l , serr_l , and perr_l ) have a low output current of 6 ma. 3 parameter design guarantee. table 12 supply current and power dissipation typical 1 maximum 2 symbol idd (ma) power (mw) idd (ma) power (mw) normal power mode 125 413 180 648 snooze power mode 75 248 150 540 sleep power mode 60 198 125 450 table 13 i/o voltage specifications for 5.0-v levels symbol parameter condition minimum maximum v ih input high voltage 2.0 v vdd_clamp + 0.5 v v il input low voltage C0.5 v 0.8 v i i 1 input leakage current 0.5 v < v in < 2.7 v 70 a v oh output high voltage i out = C2 ma 2.4 v v ol 2 output low voltage i out = 3 ma, 6 ma 0.55 v cap 3 pin capacitance 5 pf 8 pf 24 electrical and environmental specifications pci electrical parameters 3.4.2 pci reset pci reset ( pci_rst ) is an asynchronous signal that must be active for at least 10 active pci clock ( pci_clk ) cycles. figure 3 shows the pci reset timing characteristics, and table 15 lists the pci reset signal limits. figure 3 pci reset timing diagram 1 input leakage currents include high-impedance output leakage for all bidirectional buffers with tristate outputs. 2 parameter design guarantee. table 14 i/o voltage specification for 3.3-v levels symbol parameter condition minimum maximum v ih input high voltage 0.475 * vdd_clamp vdd_clamp + 0.5 v v il input low voltage C0.5 v 0.325 * vdd_clamp i i 1 input leakage current 0.0 v < v in < vdd_clamp 10 a v oh output high voltage i out = C500 a 0.9 * vdd_clamp v ol output low voltage i out = 1500 a 0.1 * vdd_clamp cap 2 pin capacitance 5 pf 8 pf table 15 pci reset timing symbol parameter minimum maximum conditions trst pci_rst pulse width 10 * tcycle not applicable pci_clk active internal reset 10 cycles pci_clk 33 cycles pci_clk pci_clk pci_rst lj-03902.ai4 electrical and environmental specifications 25 pci electrical parameters 3.4.3 pci clock specifications the clock frequency range for the pci is between 20 mhz and 33 mhz. 1 figure 4 shows the pci clock specification timing characteristics and required measurement points for both 5-v and 3.3-v signaling environments. table 16 lists the frequency- derived clock specifications. figure 4 pci clock specification timing diagram 1 the pci clock frequency is from dc to 33 mhz; network operational with the pci clock from 20 mhz to 33 mhz. 1 rise and fall times are specified in terms of the edge rate measured in v/ns. parameter design guarantee. table 16 pci clock specifications symbol parameter minimum maximum tcycle cycle time 30 ns 50 ns thigh pci_clk high time 11 ns tlow pci_clk low time 11 ns tr/tf 1 pci_clk slew rate 1 v/ns 4 v/ns thigh tlow 2.0 v 5.0-v clock 3.3-v clock 0.8 v tr tf lj03910a.ai4 tcycle 0.475 * vdd_clamp 0.325 * vdd_clamp 26 electrical and environmental specifications pci electrical parameters 3.4.4 other pci signals figure 5 shows the timing diagram characteristics, and table 17 lists the other pci signals. this timing is identical to the timing for the general-purpose register signals. figure 5 timing diagram for other pci signals clk output input 1 vtest is 1.5 v in a 5.0-v signaling environment and is 0.4 * vdd_clamp in a 3.3-v signaling environment. vtest 1 tval (max) tval (min) ton toff tsu th lj04719a.ai4 electrical and environmental specifications 27 serial, mii/sym, boot rom, serial rom, and general-purpose port interface 3.5 serial, mii/sym, boot rom, serial rom, and general-purpose port interface specifications table 18 lists the specifications for the serial, mii /sym, boot rom, serial rom, and general-purpose port interfaces. 1 load for this measurement is as specified in revisions 2.0 and 2.1 of the pci local bus specification . 2 parameter design guarantee. 1 for pin sr_do , which has an internal pull-up resistor, the maximum leakage current of 1 ma can occur when vin = 0 v. 2 for br_ce_l , the maximum value is 1000.0 a. table 17 other pci signals symbol parameter minimum maximum tval 1 clk-to-signal valid delay 2 ns 11 ns ton 2 float-to-active delay from clk 2 ns toff active-to-float delay from clk 28 ns tsu input signal valid setup time before clk 7 ns th input signal hold time from clk 0 ns table 18 serial, mii/sym, boot rom, serial rom, and general-purpose port symbol definition condition minimum maximum units v oh output high voltage i oh = C4 ma 2.4 v v ol output low voltage i ol = 4 ma 0.4 v v ih input high voltage 2.0 v v il input low voltage 0.8 v i in input current v in = v cc or v ss C10.0 10.0 a i ip input leakage current on pin with internal pull-up resistor ( sr_do ) 0.0 electrical and environmental specifications 29 serial network port timing 3.6.2 serial 10-mb/s timingcollision figure 7 shows the serial network port collision timing characteristics, and table 20 lists the serial network port collision timing limit. figure 7 serial network port timing diagramcollision 1 parameter design guarantee. 1 parameter design guarantee. table 19 serial network port timingtransmit symbol definition minimum maximum units ttcl srl_tclk low time 45 55 ns ttch srl_tclk high time 45 55 ns ttcr 1 srl_tclk rise time 8 ns ttcf 1 srl_tclk fall time 8 ns ttdp srl_tclk fall time to srl_txd valid 26 ns ttdh srl_txd hold after srl_tclk fall time 5 ns ttep srl_tclk fall time to srl_txen valid 26 ns tteh srl_txen hold after srl_tclk fall time 5 ns table 20 serial network port timingcollision symbol definition minimum maximum units tclh 1 srl_clsn high time 20 ns tclh lj-04721.ai4 srl_clsn 30 electrical and environmental specifications serial network port timing 3.6.3 serial 10 mb/s timingreceive, start of packet figure 8 shows the serial network port timing characteristics in receive mode, start of packet; and table 21 lists the serial network port timing limits in receive mode, start of packet. figure 8 serial network port timing diagramreceive, start of packet trch trcl trcf trcr trds trdh trcc lj-04722.ai4 srl_rclk srl_rxd srl_rxen electrical and environmental specifications 31 serial network port timing 3.6.4 serial 10-mb/s timingreceive, start, and end of packet figure 9 shows the serial network port timing characteristics in receive mode, end of packet; and table 21 lists the serial network port timing limits in receive mode, end of packet. figure 9 serial network port timing diagramreceive, end of packet 1 parameter design guarantee. table 21 serial network port timingreceive, start, and end of packet symbol definition minimum maximum units trcc srl_rclk cycle time 85 118 ns trcl srl_rclk low time 38 80 ns trch srl_rclk high time 38 80 ns trcr 1 srl_rclk rise time 8 ns trcf 1 srl_rclk fall time 8 ns trds srl_rxd setup to srl_rclk fall time 10 ns trdh srl_rxd hold after srl_rclk fall time 5 ns trel srl_rxen low time 120 ns treh srl_rxen hold after srl_rclk rise time 10 100 ns lj-04723.ai4 treh trel bit n bit n_1 srl_rclk srl_rxd srl_rxen 32 electrical and environmental specifications mii/sym port timing 3.7 mii/sym port timing this section describes the mii/sym port timing limits. 3.7.1 mii/sym 10/100-mb/s and 10-mb/s timingtransmit figure 10 shows the mii/sym port transmit timing characteristics, and table 22 lists the mii/sym port transmit timing limits. figure 10 mii/sym port timing diagramtransmit mii/sym_tclk mii/sym_txd<3:0> mii/sym_txen tcl tch trv trh tcr tcf tcc lj-05017 .ai4 electrical and environmental specifications 33 mii/sym port timing 1 50 parts per million. 2 t = 1 for 100-mb/s operation and t = 10 for 10-mb/s operation. 3 outputs transmit data ( mii/sym_txd ) and transmit enable ( mii_txen ) are driven internally from the rising edge of mii/sym_tclk . table 22 mii/sym port timingtransmit symbol definition minimum typical maximum units tcc 1,2 mii/sym_tclk cycle time 40t ns tch 2 mii/sym_tclk high time 14t 26t ns tcl 2 mii/sym_tclk low time 14t 26t ns tcr mii/sym_tclk rise time 8 ns tcf mii/sym_tclk fall time 8 ns trv 3 mii_tclk rise to mii_txen valid time or mii/sym_tclk rise to mii/sym_txd valid time 20 ns trh mii_txen hold after mii_tclk rise time 5 ns 34 electrical and environmental specifications mii/sym port timing 3.7.2 mii/sym 10/100-mb/s timingreceive figure 11 shows the mii/sym port receive timing cha racteristics, and table 23 l ists the mii/sym port receive timing limits. figure 11 mii/sym port timing diagramreceive table 23 mii/sym port timingreceive (sheet 1 of 2) symbol definition minimum typical maximum units tcc 1,2 mii/sym_rclk cycle time 40t ns tch 2 mii/sym_rclk high time 14t 26t ns tcl 2 mii/sym_rclk low time 14t 26t ns tcr mii/sym_rclk rise time 8 ns tcf mii/sym_rclk fall time 8 ns mii/sym_rxd<3:0> mii_dv mii/sym_rclk lj-05018.ai4 tts tth tcl tch tcr tcf tcc electrical and environmental specifications 35 mii/sym port timing 3.7.3 mii/sym 10/100-mb/s timingsignal detect figure 12 shows the mii/sym port signal detect timing characteristics, and table 24 lists the mii/sym port signal detect timing limits. figure 12 mii/sym port timing diagramsignal detect 1 50 parts per million. 2 t = 1 for 100-mb/s operation and t = 10 for 10-mb/s operation. 3 inputs receive data ( mii/sym_rxd ) and data valid ( mii_dv ) are latched internally on the rising edge of mii/sym_rclk . 4 parameter design guarantee. 1 input signal detect ( sd ) is latched internally on the falling edge of sym_rclk . 2 parameter design guarantee. tts 3 mii/sym_rxd setup (both rise and fall transactions) to mii/sym_rclk rise time or mii_dv setup (both rise and fall transactions) to mii_rclk rise time 8 ns tth 4 mii/sym_rxd hold (both rise and fall transac- tions) after mii/sym_rclk rise time or mii_dv hold (both rise and fall transactions) after mii_rclk rise time 10 ns table 24 mii/sym port timingsignal detect symbol definition minimum maximum units tts sd 1 setup (both rise and fall transac- tions) to sym_rclk fall time 10 ns tth 2 sd 1 hold (both rise and fall transactions) after sym_rclk fall time 12 ns table 23 mii/sym port timingreceive (sheet 2 of 2) symbol definition minimum typical maximum units 12345 sym_rclk sd lj-03905.ai4 tts tth 36 electrical and environmental specifications mii/sym port timing 3.7.4 mii/sym 10/100-mb/s timingreceive error figure 13 shows the mii/sym port receive error tim ing characteristics, and table 25 lists the mii/sym port receive error timing limits. figure 13 mii/sym port timing diagramreceive error 3.7.5 mii/sym 10/100-mb/s timingcarrier sense and collision figure 14 shows the mii/sym port carrier sense and collision timing ch aracteristics, and table 26 lists the mii/sym port c arrier sense and col lision timing limits. figure 14 mii/sym port timing diagramcarrier sense and collision 1 input receive error ( mii_err ) is latched internally on the rising edge of mii_rclk . 2 parameter design guarantee. table 25 mii/sym port timingreceive error symbol definition minimum maximum units tts mii_err 1 setup (both rise and fall transactions) to mii_rclk rise time 10 ns tth 2 mii_err 1 hold (both rise and fall transactions) after mii_rclk rise time 10 ns table 26 mii/sym port timingcarrier sense and collision symbol definition minimum maximum units tclh mii_crs, mii_clsn high time 20 ns 12345 mii_rclk sd lj-03906.ai4 tts tth mii_clsn mii_crs l j - 039 2 9 .ai4 tclh electrical and environmental specifications 37 boot rom port timing 3.8 boot rom port timing this section describes the boot rom port timing. 3.8.1 boot rom read timing figure 15 shows the boot rom read timing cha racteri stics, and table 27 lists the boot rom read timing limits. figure 15 boot rom read timing diagram 1 parameter design guarantee. table 27 boot rom read timing specifications symbol parameter minimum maximum units tavav read cycle time 120 ns telqv br_ce_l to output delay 120 ns telqx 1 br_ce_l to output enable 0 ns tehqz 1 br_ce_l rising edge to output high impedance 55 ns toh 1 output hold from br_ce_l change 0 ns tads address setup to latch enable high 30 ns tadh address hold from latch enable high 30 ns br_a<1> br_a<0> br_ce_l br_ad<7:0> tadh tads tadh tads tavqv lj-0 5037.ai4 telqv tavav telqx toh tehqz address = <7:2> oe = 0, we = 1 address <15:8> address <16> address <0> address <17> data <7:0> valid address <1> scale=89% 38 electrical and environmental specifications boot rom port timing 3.8.2 boot rom write timing figure 16 shows the boot rom write timing characteristics, and table 28 lists the boot rom write timing limits. figure 16 boot rom write timing diagram 1 parameter design guarantee. table 28 boot rom write timing specifications symbol parameter minimum maximum units tavav write cycle time 120 ns teleh 1 br_ce_l pulse width 70 ns taveh 1 address setup to br_ce_l rising edge 50 ns tdveh 1 data setup to br_ce_l rising edge 50 ns tehdx 1 data hold from br_ce_l rising edge 10 ns tehax 1 address hold from br_ce_l high 15 ns tads address setup to latch enable high 30 ns tadh address hold from latch enable high 30 ns br_a<1> br_a<0> br_ce_l br_ad<7:0> tadh tads tadh tads address = <7:2> oe = 1, we = 0 address <15:8> address <16> address <0> address <17> data <7:0> address <1> lj-05038.ai4 teleh tavav tehdx tehax tdveh taveh electrical and environmental specifications 39 serial rom port timing 3.9 serial rom port timing figure 17 shows the serial rom port timing, and table 29 lists the cha racteri stics. this timing is identical to the timing for the mii management signals ( mii_mdio and mii_mdc ). figure 17 serial rom port timing diagram 1 parameter design guarantee. table 29 serial rom port timing characteristics symbol definition minimum maximum units tsr 1 rise time 10ns tsf 1 fall time 10 ns sr_cs, sr_ck, sr_di, tsr tsf lj-03909.ai4 sr_do 40 electrical and environmental specifications external register timing 3.10 external register timing figure 18 shows the external register read timing cha racteristics, and figure 19 shows its write timing characteristics. table 30 lists the external register timing specifications for both read and write operat ions. figure 18 external register read timing diagram figure 19 external register write timing diagram table 30 external register timing specifications (sheet 1 of 2) symbol parameter minimum maximum units teleh br_ce_l pulse width 120 ns read timing tpd br_ce_l low to br_ad<7:0> valid 20 ns br_a<0> br_ce_l br_ad<7:0> lj-05039.ai4 tpd tehqz data valid br_a<0> br_ce_l br_ad<7:0> lj-05040.ai4 teleh th ts data <7:0> electrical and environmental specifications 41 joint test action grouptest access port 3.11 joint test action grouptest access port this section provides the joint test action group (jtag) test access port specifications. 3.11.1 jtag dc specifications table 31 lists the dc specifications for the jtag pins. 3.11.2 jtag boundary-scan timing figure 20 shows the jtag boundary-scan timing, and table 32 lists the interface signal timing relationships. 1 parameter design guarantee. 1 for tdi and tms pins, which have internal pull-up resistors, the maximum leakage current of 1 ma can occur when vin = 0 v. tehqz 1 br_ce_l high to br_ad<7:0> high impedance 20 ns write timing ts data setup time prior to br_ce_l 30 ns th data hold after br_ce_l high 30 ns table 31 jtag dc specifications symbol definition conditions minimum maximum units v oh output high voltage i oh = C4 ma 2.4 v v ol output low voltage i ol = 4 ma 0.4 v v ih input high voltage 2.0 v v il input low voltage 0.8 v i ip input leakage current on pins with internal pull-up resistors ( tdi , tms ) 0.0 mechanical specifications 43 4 mechanical specifications the 21140a is contained in an industry standard 144-pin pqfp. table 33 lists the mechanical specifications, and figure 21 shows the mechanical layout of the 21140a. 1 ansi y14.5m-1982 american national standard dimensioning and tolerancing, section 1.3.2, defines basic (bsc) dimension as: a numerical value used to describe the theoretically exact size, profile, orientation, or location of a feature or datum target. it is the basis from which permissible variations are established by tolerances on other dimensions, in notes, or in feature control frames. 2 the value for this measurement is for reference only. table 33 144-pin pqfp dimensional attributes symbol dimension limit value (mm) a package overall height maximum 4.10 a1 package standoff height minimum 0.25 a2 package thickness minimum maximum 3.17 3.67 b lead width minimum maximum 0.22 0.38 c lead thickness minimum maximum 0.12 0.23 ccc coplanarity 0.1 d package overall width bsc 1 31.20 d1 package width bsc 28.00 ddd lead skew 0.13 e package overall length bsc 31.20 e1 package length bsc 28.00 e lead pitch bsc 0.65 l foot length minimum maximum 0.65 1.03 ll lead length reference 2 1.60 r ankle radius minimum maximum 0.13 0.3 44 mechanical specifications figure 21 144-pin pqfp package lj04510b .ai4 a // 0.13 c c - c - datum plane seating plane ccc - h - - basic dimension - reference dimension ( ) a c m ddd s b s 0 o - 7 o c detail "a" (a) a2 a1 l (ll) r note: all dimensions are in millimeters. see detail "a" d d1 144-pin pqfp b e e e1 pin 1 pin # direction - b - - a - support, products, and documentation 45 a support, products, and documentation to view current product update and errata revi sion information, please visit the digital semiconductor world wide web internet site. you may also visit this web site for technical support, a digital semiconductor product catalog , or help deciding which documentation best meets your needs: http://www.digital.com/semiconductor you can also contact the digital semiconductor information line or the digital semiconductor customer technology center for support. for documentation and general information: digital semiconductor information line united states and canada: 1 C800C332C2717 outside north america: 1C510C490C4753 electronic mail address: semiconductor@digital.com for technical support, product updates, and errata documentation: digital semiconductor customer technology center phone (u.s. and international): 1C978C568C7474 fax: 1C978C568C6698 electronic mail address: ctc@hlo.mts.dec.com 46 support, products, and documentation digital semiconductor products to order the digital semiconductor 21140a pci fast ethernet lan controller and evaluation boards, contact your local distributor. the following tables list some of the semiconductor products available from digital semiconductor. note: the following products and order numbers might have been revised. for the latest versions, contact your local distributor. evaluation board kits include an evaluation board, and can include a complete design kit, an installation kit, or an accessories kit. product order number digital semiconductor 21140a pci fast ethernet lan controller 21140Caf digital semiconductor 21143 pci/cardbus 10/100-mb/s ethernet lan con- troller (mqfp package) 21143Cpd digital semiconductor 21143 pci/cardbus 10/100-mb/s ethernet lan con- troller (lqfp package) 21143Ctd evaluation board kits order number digital semiconductor 21140a 10/100baseCtx evaluation board kit 21a40Ctx digital semiconductor 21143 pci 10/100baseCtx evaluation board kit 21a43C04 support, products, and documentation 47 digital semiconductor documentation the following table lists some of the available digital semiconductor documentation. to determine which documents apply to a particular device part number, visit the digital semiconductor documentation library on digital semiconductors world wide web internet site at: http://ftp.digital.com/pub/digital/info/semiconductor/literature/dsc-library.html thirdCparty documentation you can order the following third-party documentation directly from the vendor. title order number) digital semiconductor 21140a pci fast ethernet lan controller hardware reference manual ecCqn7nfCte digital semiconductor 21140a pci fast ethernet lan controller product brief ecCqn7mbCte digital semiconductor 21143 pci/cardbus 10/100-mb/s ethernet lan controller data sheet ecCqwc3fCte digital semiconductor 21143 pci/cardbus 10/100-mb/s ethernet lan controller hardware reference manual ecCqwc4fCte digital semiconductor 21143 pci/cardbus 10/100-mb/s ethernet lan controller product brief ecCqwc2bCte digital semiconductor 21143 connection to the network using physi- cal layer devices: an application note ecCqxy7aCte title vendor pci local bus specification, revision 2.1 pci multimedia design guide, revision 1.0 pci system design guide pci-to-pci bridge architecture specification, revision 1.0 pci bios specification, revision 2.1 pci special interest group u.s. 1C800C433C5177 international 1C503C797C4207 fax 1C503C234C6762 ieee 802.3 the institute of electrical and electronics engineers, inc. u.s. 1C800C701C4333 international 1C908C981C0060 fax 1C908C981C9667 |
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