View ADUCM360BCPZ128_7005898.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

low power, precision analog microcontroller with dual sigma - delta adc s, arm cortex - m3 data sheet aducm360 / aducm361 rev. b document feedback information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements o f patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trade marks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062 - 9106, u.s.a. tel: 781.329.4700 ? 2012C 2013 analog devices, inc. all rights reserved. technical support www.analog.com features analog i nput/ o utput dual 24- bit adcs ( aducm360 ) single 24- bit adc ( aducm361 ) programmable adc output rate (3.5 hz to 3.906 khz) simultaneous 50 hz/60 hz noise rejection at 50 sps c ontinuous c onversion m ode at 16.67 sps s ingle c onversion m ode flexible input mux for input channel selection to both adcs two 24- bit multi channel adc s (adc0 and adc1) 6 differential or 11 s ingle - e nded input channels 4 internal ch annels for monitoring dac, t emperature sensor, iovdd/4 , and avdd/4 (adc1 only ) programmable g ain (1 to 1 28) rms noise: 52 nv at 3. 53 hz, 200 nv at 50 hz programmable sensor excitation current sources on - chip precision v oltage reference single 12 - bit voltag e output dac npn mode for 4 ma to 20 ma loop applications microcontroller arm cortex - m3 32 - bit processor serial w ire download and debug internal w atch crystal for wake - up timer 16 mhz o scillator with 8 - way p rogrammable d ivider memory 128 kb flash/ee m emory , 8 kb sram in - circuit debug/download via s erial w ire and uart power s upply r ange: 1.8 v to 3.6 v (max imum ) power c onsumption , mc u active mode c ore consumes 290 a/ mhz overall system current consumption of 1.0 ma with core operating at 500 khz ( both adcs on, input buffers off, pga gain of 4, one spi port on, and all timers on) power c onsumption , p ower - down mode: 4 a ( wake - up t imer a ctive) on - c hip p eripherals uart, i 2 c , and 2 spi s erial i/o 16- bit pwm c ontroller 19- p in multif unction gpio p ort 2 general - p urpose t imer s wake - up t imer/ w atchdog t imer multic hannel dma and i nterrupt c ontroller package and t emperature r ange 48- lead , 7 mm 7 mm l fcsp specified for ?40c to + 125c operation development t ools low c ost quickstart development s ystem third - p arty c ompi ler and emulator tool s upport multiple f unctional s afety features for improved diagnostics applications industrial automation and process control intelligent precision sensing systems 4 ma to 20 ma loop - powered smart sensor systems medical devices, patient monitoring
aducm360/aducm361 da ta sheet rev. b | page 2 of 24 table of contents features .............................................................................................. 1 applications ....................................................................................... 1 revision hi story ............................................................................... 2 general description ......................................................................... 3 functional block diagrams ............................................................. 4 specif ications ..................................................................................... 6 microcontroller electrical specifications .................................. 6 rms noise resolution of adc0 and adc1 .......................... 10 i 2 c timing specifications .......................................................... 14 spi timing specifications ......................................................... 15 absolute maximum ratings ......................................................... 17 thermal resistance .................................................................... 17 esd caution ................................................................................ 17 pin configuration and function descri ptions ........................... 18 typical performance characteristics ........................................... 21 typical system configuration ...................................................... 22 outline dimensions ....................................................................... 23 ordering guide .......................................................................... 23 revision history 7 /13 rev. a to rev. b changes to features section and g eneral d escription section ....... 3 changes to figure 1 .......................................................................... 4 added figure 2, renumbered sequentially .................................. 5 changes to table 1 ............................................................................ 6 changes to table 2 and table 3 ..................................................... 10 changes to table 4 and table 5 ..................................................... 11 changes to table 6 and table 7 ..................................................... 12 changes to table 8 and table 9 ..................................................... 13 changes to table 16 ........................................................................ 17 changes to f igure 14 ...................................................................... 21 11 /12 rev . 0 to rev. a changes to pin 35 and pin 36 i n table 16 ................................... 18 9 /12 revision 0: initial version
data sheet aducm360/aducm361 rev. b | page 3 of 24 general description the aducm360 is a fully integr ated, 3.9 ksps, 24 - bit data acqui sition system that incorporates dual high performance , multi channel sigma - delta ( - ) analog - to - digital conve rters (adcs), a 32- bit arm cortex ? - m3 processor , and f lash/ee memory on a single chip. the aducm360 is designed for direct interfacing to external precision se nsors in both wired and battery - powered applications. the aducm361 contains all the features of the aducm360 except th at only one 24 - bit - adc ( adc1 ) is available . the aducm360 / aducm361 contain an on - chip 32 k hz oscillator and an internal 16 mhz high frequency oscillator. th e high frequency osc illator is routed through a programmable clock divider from which the operating frequency of the processor core clock is generated. the maximum core clock speed is 16 mhz ; this speed is not limited by operating voltage or temperature. the microcontroller c ore is a low power arm cortex - m3 processor , a 32 - bit risc machine that offer s up to 20 mips peak performance. the cortex - m3 processor incorporates a flexible , 11- channel dma controller that support s all wired communica - tion peripherals (spi, uart, and i 2 c) . also integrated on chip are 128 kb of nonvolatile flash/ee memory and 8 kb of sr am. the a nalog subsystem consists of dual adcs , each connected to a flexible input mux . both adcs can operate in fully differential and single - ended modes. other on - chip adc features include dual programmable excitation current sources, diagnostic current sources , and a bias voltage generator of avdd_reg/2 (900 mv) to set the common - mode voltage of an input channel. a low - side internal ground switc h is provided to allow power - down o f a n external circuit (for example, a bridge circuit) between conversions. the adcs contain two parallel filters : a s inc3 or s inc4 filter in parallel with a s inc2 filter . the s inc3 or s inc4 filter is used for precision measurements. the s inc2 filter is used for fast measure - ments and for the detection of s tep changes in the input signal. the devices contain a low noise, low drift internal band gap ref - erence, but they can be configured to accept one or two external reference sources in ratiometric mea surement configurations. an option to buffer the external reference inputs is provided on chip. a single - channel buffered voltage output dac is also provided on chip. the aducm360 / aducm361 integrate a range of on - chip peripherals , which can be configured under microcontroller software control as required in the application. the peripherals include uart, i 2 c, and dual spi s erial i/o communication controllers ; a 19- p in gpio p ort ; two general - p urpose t imers ; a w ake - up t imer ; and a s ystem w atchdog t imer . a 16 - bit pwm controller with six output channels is also provided. the aducm360 / aducm361 are specifically designed to operate in battery - powered applications where low power operation is critical. the microcontroller core can be configured in a normal operating mode that consum es 290 a/mhz (including f lash/ sram i dd ) . a n overall system current consumption of 1 ma can be achieved with both adcs on (input buffers off), pga gain of 4, one spi port on, and all timers on. the aducm360 / aducm361 can be configured in a number of low power operating modes under direct program control, including a hibernate mode (internal wake - up timer active) that consum es only 4 a. in hibernate mode, peripherals s uch as external interrupts or the internal wake - up timer can wake up the device. this mode allows the part to operate with ultralow power and still respond to asynchrono us external or periodic events. on - chip factory firmware supports in - circuit serial dow nload via a serial wire interface (2 - pin jtag system) and uart ; non - intrusive emulation is also supported via the serial wire interface. these features are incorporated in t o a low cost quickstart ? development system that support s this p recision a nalog m icr o - controller family. the part s operate from an external 1.8 v to 3.6 v voltage supply and are specified over an industrial temperature range of ? 40c to + 125c . more information on the aducm360 / aducm361 , see the ug - 367 user guide.
aducm360/aducm361 data sheet rev. b | page 4 of 24 functional block diagrams - ? modulator 24-bit - ? adc v ref ain0 dac, temp, iovdd/4, avdd/4 sinc3/4 filter 12-bit dac sinc2 filter on-chip 1.8v analog ldo on-chip 1.8v digital ldo power-on reset on-chip oscillator (1% typ) 16mhz gpio ports uart ports 2 spi ports i 2 c ports 19 general- purpose i/o ports memory 128kb flash 8kb sram dma and interrupt controller timer0 timer1 watchdog wake-up timer pwm serial wire debug, programming and debug arm cortex-m3 processor 16mhz v bias generator precision reference aducm360 buffer buffer buffer selectable v ref sources current sources ain1 ain2 dac reset xtalo xtali swdio swclk dvdd_reg avdd_reg avdd agnd ain3 ain4/iexc ain5/iexc ain6/iexc ain7/vbias0/iexc/ extref2in+ ain8/extref2in? ain9/dacbuff+ ain10 ain11/vbias1 iref gnd_sw vref? int_ref iovdd iovdd vref+ 09743-001 amp mod2 gain - ? modulator 24-bit - ? adc v ref sinc3/4 filter amp mod2 gain buf buf mux figure 1. aducm360 functional block diagram
data sheet aducm360/aducm361 rev. b | page 5 of 24 ain0 dac, temp, iovdd/4, avdd/4 12-bit dac sinc2 filter on-chip 1.8v analog ldo on-chip 1.8v digital ldo power-on reset on-chip oscillator (1% typ) 16mhz gpio ports uart ports 2 spi ports i 2 c ports 19 general- purpose i/o ports memory 128kb flash 8kb sram dma and interrupt controller timer0 timer1 watchdog wake-up timer pwm serial wire debug, programming and debug arm cortex-m3 processor 16mhz v bias generator precision reference aducm361 buffer buffer buffer selectable v ref sources current sources ain1 ain2 dac reset xtalo xtali swdio swclk dvdd_reg avdd_reg avdd agnd ain3 ain4/iexc ain5/iexc ain6/iexc ain7/vbias0/iexc/ extref2in+ ain8/extref2in? ain9/dacbuff+ ain10 ain11/vbias1 iref gnd_sw vref? int_ref iovdd iovdd vref+ 09743-014 - ? modulator 24-bit - ? adc v ref sinc3/4 filter amp mod2 gain buf mux figure 2. aducm361 functional block diagram
aducm360/aducm361 data sheet rev. b | page 6 of 24 specifications microcontroller elec trical specification s avdd/iovdd = 1.8 v to 3.6 v, i nternal 1.2 v reference, f core = 16 mhz, all specifications at t a = ?40c to +125c, unless otherwise noted. table 1. parameter test conditions/comments min typ max unit adc specifications adc0 and adc1 conversion rate 1 chop off 3.5 3906 hz chop on 3.5 1302 hz no missing codes 1 chop off, f adc 500 hz 24 bits chop on, f adc 250 hz 24 bits rms noise and data output rates see table 2 through table 9 integral nonline arity 1 gain = 1 , input buffer off 1 0 ppm of fsr gain = 2, 4, 8, or 16 15 ppm of fsr gain = 32, 64, or 128 20 ppm of fsr offset error 2 , 3 , 4 , 6 , 7 chop o ff ; offset error is in the order of the noise for the pro grammed gain and update rate following calibration 100/ g ain v chop on 1 1.0 v offset error drift vs. temperature 1 , 4 , 6 chop off , gain 4 1 /gain v /c chop o ff, gain 8 230 nv/c chop on 10 nv/c offset error lifetime stability 5 gain = 128 1 v/1000hr full - scale error 1 , 4 , 6 , 7 , 8 0.5/ g ain mv full - scale error lifetime stability 5 gain = 128 70 v/1000hr gain error drift vs. temperature 1 , 4 , 6 external reference gain = 1, 2 , 4, 8, or 16 3 ppm/c gain = 32, 64, or 128 6 ppm/c pga gain mismatch error 0.15 % power supply rejection 1 external reference chop on, adc input = 0.25 v, gain = 4 95 db chop off, adc input = 7.8 mv, gain = 128 80 db chop off, adc input = 1 v, gain = 1 90 db absolute input voltage range unbuffered mode agnd avdd v buffered mode gain = 1 is not available; see the infor - mation about silicon anomalies on the aducm360 / aducm361 product page gain 2 agnd + 0.1 avdd ? 0.1 v differential input voltage ranges 1 for gain = 32, 64, and 128, see table 3 and table 7 for allowable input ranges and noise values gain = 1 v ref v gain = 2 500 mv gain = 4 250 mv gain = 8 125 mv gain = 16 62.5 mv common - mode voltag e, v cm 1 ideally, v cm = ((ain+) + (ain ?))/2; gain = 2 to 128; input current varies with v cm (see figure 9 and figure 10) agnd avdd v input current 9 buffered mode gain > 1 (excluding ain4, ain5, ain6, an d ain7 pins) 1 na gain > 1 (ain4, ain5, ain6, and ain7 pins) 2 na unbuffered mode input current varies with input voltage 500 na/v
data sheet aducm360/aducm361 rev. b | page 7 of 24 parameter test conditions/comments min typ max unit average input current drift 1 buffered mode ain0, ain1, ain2, ai n3 5 pa/c ain4, ain5, ain6, ain7 16 pa/c ain8, ain9, ain10, ain11 9 pa/c unbuffered mode 250 pa/v/c common - mode rejection, dc 1 on adc input adc gain = 1, avdd < 2 v 65 100 db adc gain = 1, avdd > 2 v 80 100 db adc gain = 2 to 128 80 db common - mode rejection, 50 hz/60 hz 1 50 hz/60 hz 1 hz; f adc = 16.7 hz, chop on; f adc = 50 hz, chop off adc gain = 1 97 db adc gain = 2 to 128 90 db normal - mode rejection, 50 hz/60 hz 1 on adc input 50 hz/60 hz 1 hz; f adc = 16.7 hz, chop on; f adc = 50 hz, chop off 60 80 db temperature sensor 1 after user calibration voltage output at 25c processor powered down or in standby mode before measurement 82.1 mv voltage temperature coefficient (tc) 250 v/c accuracy 6 c ground switch r on 3.7 10 19 ? allowable current 1 20 k? resistor off, direct short to ground 20 ma voltage reference adc internal reference internal v ref 1.2 v initial accuracy measured at t a = 25c ?0.1 +0.1 % reference temperature coefficient (tc) 1 , 10 ?15 5 +15 ppm/c power supply rejection 1 82 90 db external reference inputs input range buffered mode agnd + 0.1 avdd ? 0.1 v unbuffe red mode minimum differential voltage between vref+ and vref? pins is 400 mv 0 avdd v input current buffered mode ?20 +10 +27 na unbuffered mode 500 na/v normal - mode rejection 1 80 db common -mo de rejection 1 85 100 db reference detect levels 1 400 mv excitation current sources output current available from each current source; value programmabl e from 10 a to 1 ma 10 50 1000 a initial tolerance at 25c 1 i out 50 a 5 % drift 1 using internal reference resistor 100 400 ppm/c using external 150 k? reference resistor between iref pin and agnd; resistor must have drift specification of 5 ppm/c 75 400 ppm/c initial current matching at 25c 1 matching between both current sources 0.5 % drift matching 1 50 ppm/c load regulation, avdd 1 avdd = 3.3 v 0.2 %/v output compliance 1 i out = 10 a to 210 a agnd ? 0.03 avdd ? 0.85 v i out > 210 a agnd ? 0.03 avdd ? 1.1 v
aducm360/aducm361 data sheet rev. b | page 8 of 24 parameter test conditions/comments min typ max unit dac channel specifications r l = 5 k?, c l = 100 pf voltage range internal reference 0 v ref v external reference 0 1.8 v dc specifications 11 resolution 12 bits relative accur acy 3 lsb differential nonlinearity guaranteed monotonic 0.5 1 lsb offset error 1.2 v internal reference 2 10 mv gain error v ref range (reference = 1.2 v) 0.5 % npn mode 1 resolution 12 bits relative accuracy 3 lsb differential nonlinearity 0.5 lsb offset error 0.35 ma gain error 0.75 ma output current range 0.008 23.6 ma interpolation mode 1 only monotonic to 14 bits resolution 14 bits relative accuracy for 14 - bit resolution 4 lsb differential nonlinearity monotonic (14 bits) 0.5 lsb offset error 1.2 v internal reference 2 mv gain error v ref range (reference = 1.2 v) 1 % avdd range 1 % dac ac characteristics 1 voltage output settling time 10 s digital -to - analog glitch energy 1 lsb change at major carry (maximum number of bits changes simultaneously in the dac0dat register) 20 nv - sec power - on reset (por) por trip level voltage at dvdd pin power - on level 1.6 v power - down level 1.6 v timeout from por 1 50 ms watchdog timer (wdt) 1 timeout period 0.00003 8192 sec timeout step size t3con[3:2] = 10 7.8125 ms flash/ee memory 1 endurance 12 10,000 cycles data retention 13 t j = 85c 10 years digital inputs all digital inputs input leakage current digital inputs except for the reset , swclk, and swdio pins logic 1 v inh = iovdd or v inh = 1.8 v 140 a internal pull - up disabled 1 na logic 0 v inl = 0 v 160 a internal pull - up disab led 10 na input leakage current reset , swclk, and swdio pins logic 1 140 a logic 0 160 a input capacitance 1 10 pf logic inputs input low voltage, v inl 0.2 iovdd v input high voltage, v inh 0.7 iovdd v
data sheet aducm360/aducm361 rev. b | page 9 of 24 parameter test conditions/comments min typ max unit logic outputs output high voltage, v oh i source = 1 ma iovdd ? 0.4 v output low voltage, v ol i sink = 1 ma 0.4 v crystal oscillator 1 32.768 khz cry stal inputs logic inputs, xtali only 14 input low voltage, v inl 0.8 v input high voltage, v inh 1.7 v xtali capacitance 6 pf xtalo capacitance 6 pf on - chip low power oscillator oscillator frequency 32.768 khz accuracy ?30 10 +30 % on - chip high frequency oscillator oscillator frequency 16 mhz accuracy ?40c to +125c ?1.8 +1.4 % long term stability 5 0.8 c/1000hr processor clock rate 1 nine programmable core clock selections within specified range 0.0625 0.5 16 mhz using an external clock 0.032768 16 mhz processor start - up time 1 at power - on includes kernel power - on execution time 41 ms after reset event includes kernel power - on execution time 1.44 ms from processor power - down (mode 1, mode 2, and mode 3) f clk is the cortex - m3 core clock 3 to 5 f clk from total halt or hibernate mode (mode 4 or mode 5) 30.8 s power requirements power supply voltages, v dd avdd, iovdd 1.8 3.6 v power consumption i dd (mcu active mode) 15, 16 processor clock rate = 16 mhz; all peripherals on (clksysdiv = 0) 5.5 ma processor clock rate = 8 mhz; all periphera ls on (clksysdiv = 1) 3 ma processor clock rate = 500 khz; both adcs on (input buffers off ) with pga gain = 4, 1 spi port on, all timers on 1 ma i dd (mcu powered down) full temperature range, total halt mode (mode 4) 4 a reduced temperature r ange, ?40c to +85c 4 a i dd , total (adc0) 16 pga enabled, gain 32 320 a pga gain = 4, 8, or 16, pga only 130 a gain = 32, 64, or 128, pga only 180 a input buffers 2 input buffers = 70 a 70 a digital interface and modulator 70 a i dd (adc1) input buffers off, gain = 4, 8, or 16 only 200 a external reference input buffers 60 a each 120 a 1 thes e numbers are not production tested, but are guaranteed by design and/or characterization data at production release. 2 tested at gain = 4 after initial offset calibration. 3 measured with an internal short. a system zero - scale calibration removes this err or. 4 a recalibration at any temperature removes these errors. 5 the long term stability specification is noncumulative. the drift in subsequent 1000 hour periods is significantly lower than in the first 1000 hour period. 6 these numbers do not include int ernal reference temperature drift. 7 factory calibrated at gain = 1.
aducm360/aducm361 data sheet rev. b | page 10 of 24 8 system calibration at a specific gain removes the error at this gain. 9 input current measured with one adc measuring a channel. if both adcs measure the same input channel, the input c urrent increases ( approximately doubles). 10 measured using the box method. 11 reference dac linearity is calculated using a reduced code range of 0x0ab to 0xf30. 12 endurance is qualified to 1 0,000 cycles as per jedec standard 22, method a117, and is measure d at ?40c, +25c, and +125c. typical endurance at 25c is 170,000 cycles. 13 retention lifetime equivalent at junction temperature (t j ) = 85c as per jedec standard 22, method a117 . retention lifetime derates with junction temperature. 14 voltage input lev els are relevant only if driving xtal input from a voltage source. if a crystal is connected directly, the internal crystal interface determine s the common - mode voltage. 15 typical additional supply current consumed during flash/ee memory program and erase cycles is 7 ma. 16 total i dd for adc includes figures for pga 32, input buffers, digital interface , and the - modulator. rms noise resolution of adc0 a nd adc1 internal reference (1.2 v) table 2 through table 5 provide rms noise specifications for adc0 and adc1 using the internal reference (1.2 v). table 2 and table 3 list the rms noise for both adcs with various gain and output update rate values. table 4 and table 5 list the typical output rms noise effective nu mber of bits (enob) in normal mode for both adcs with various gain and output update rate values. (peak - to - peak enob is shown in parentheses.) table 2. rms noise vs. gain and output update rate, internal reference (1.2 v) , gain = 1, 2, 4, 8, and 16 rms noise (v) update rate (hz) chop/sinc adcflt register value gain = 1 , v ref , adcxmde = 0x01 gain = 2, 500 mv, adcxmde = 0x 1 1 gain = 4, 25 0 mv, adcxmde = 0x 2 1 gain = 8, 125 mv, adcxmde = 0x31 gain = 16, 62.5 mv, adcxmde = 0x41 3. 5 3 on/sinc3 0x8d7c 1.05 0.45 0.23 0.135 0.072 30 off/sinc3 0x007e 2.1 1.37 0.63 0.37 0.22 50 off/sinc3 0x007d 3.7 1.6 0.83 0.47 0.29 100 off/sinc3 0x004d 5.45 2.41 1.13 0.63 0.38 488 off/sinc4 0x100f 10 4.7 2.2 1.3 0.79 976 off/sinc4 0x1007 13.5 6 .5 3.3 1.7 1.1 1953 off/sinc4 0x1003 19.3 10 4.7 2.6 1.55 3906 off/sinc4 0x1001 67.0 36 16.6 8.8 4.9 table 3. rms noise vs. gain and output update rate, internal reference (1.2 v), gain = 32, 6 4, and 128 rms noise (v) updat e rate (hz) chop/sinc adcflt register value gain = 32 , 1 62.5 mv, adcxmde = 0x49 gain = 32, 1 , 2 22.18 mv, adcxmde = 0x51 gain = 64, 3 15.625 mv, adcxmde = 0x 59 gain = 64, 3 , 4 10.3125 mv, adcxmde = 0x 61 gain = 128, 5 7.8125 mv, adcxmde = 0x6 9 gain = 128, 5 , 6 3.98 mv, adcxmde = 0x 7 1 3. 5 3 on/sinc3 0x8d7c 0.067 0.064 0.073 0.055 0.058 0.052 30 off/sinc3 0x007e 0.202 0.2 0.196 0.16 0.174 0.155 50 off/sinc3 0x007d 0.24 0.24 0.25 0.21 0.21 0.2 100 off/sinc3 0x004d 0.35 0.32 0.36 0.27 0.31 0.25 488 off/sinc4 0x100f 0.7 0.67 0.71 0.58 0.62 0.57 976 off/sinc4 0x1007 0.99 0.91 1.01 0.74 0.83 0.7 1953 off/sinc4 0x1003 1.78 1.3 1.48 1.15 1.25 1.0 3906 off/sinc4 0x1001 6.44 2.68 3.59 1.4 2.2 1.4 1 adcxmde = 0x49 sets the pga for a gain of 16 with a modulator gain of 2. the m odulator gain of 2 is implemented by adjusting the sampling cap acitor s into the modulator. adcxmde = 0x51 sets t he pga for a gain of 32 with the modulator gain off. adcxmde = 0x49 has slightly higher noise but supports a wider input range . 2 if avdd < 2.0 v and adcxmde = 0x51, the input range is 17.5 mv . 3 adcxmde = 0x59 sets the pga for a gain of 32 with a modulat or gain of 2. the m odulator gain of 2 is implemented by adjusting the sampling cap acitor s into the modulator. adcxmde = 0x61 sets the pga for a gain of 64 with the modulator gain off. adcxmde = 0x 5 9 has slightly higher noise but supports a wider input rang e . 4 if avdd < 2.0 v and adcxmde = 0x61, the input range is 8 . 7 1 5 mv . 5 adcxmde = 0x69 sets the pga for a gain of 64 with a modulator gain of 2. the m odulator gain of 2 is implemented by adjusting the sampling cap acitor s into the modulator. adcxmde = 0x71 sets the pga for a gain of 128 with the modulator gain off. adcxmde = 0x69 has slightly higher noise but supports a wider input range . 6 if avdd < 2.0 v and adcxmde = 0x71, the input range is 3.828 mv .
data sheet aducm360/aducm361 rev. b | page 11 of 24 table 4. typical output rms noise effective number of bits in normal mode , internal reference (1.2 v), gain = 1, 2, 4, 8, and 16 effective number of bi ts (enob) by input voltage range and gain 1 update rate (hz) chop/sinc gain = 1, v ref , adcxmde = 0x01 gain = 2, 500 mv, adcxmde = 0x11 gain = 4, 250 mv, adcxmde = 0x21 gain = 8, 125 mv, adcxmde = 0x31 gain = 16, 62.5 mv, adcxmde = 0x41 3. 5 3 on/s inc3 21.1 (18.4 p - p) 21.1 (18.4 p - p) 21.1 (18.3 p - p) 20.8 (18.1 p - p) 20.7 (18.0 p - p) 30 off/sinc3 20.1 (17.4 p - p) 19.5 (16.8 p - p) 19.6 (16.9 p - p) 19.4 (16.6 p - p) 19.1 (16.4 p - p) 50 off/sinc3 19.3 (16.6 p - p) 19.25 (16.5 p - p) 19.2 (16.5 p - p) 19.0 (16.3 p - p ) 18.7 (16.0 p - p) 100 off/sinc3 18.7 (16 .0 p - p) 18.66 (15.9 p - p) 18.75 (16.0 p - p) 18.6 (15.9 p - p) 18.3 (15.6 p - p) 488 off/sinc4 17.9 (15.2 p - p) 17.7 (15.0 p - p) 17.8 (15.1 p - p) 17.55 (14.8 p - p) 17.3 (14.5 p - p) 976 off/sinc4 17.4 (14.7 p - p) 17.2 (14.5 p - p ) 17.2 (14.5 p - p) 17.2 (14.4 p - p) 16.8 (14.1 p - p) 1953 off/sinc4 16.9 (14.2 p - p) 16.6 (13.9 p - p) 16.7 (14.0 p - p) 16.55 (13.8 p - p) 16.3 (13.6 p - p) 3906 off/sinc4 15.1 (12.4 p - p) 14.8 (12.0 p - p) 14.9 (12.2 p - p) 14.8 (12.1 p - p) 14.6 (11.9 p - p) 1 rms bits are calculated as follows: log 2 ((2 inp ut range )/ rms noise ); peak - to - peak (p - p) bits are calculated as follows: log 2 ((2 input range )/(6.6 rms noise )). table 5. typical output rms noise effective number of bits in normal mode , internal reference (1.2 v), gain = 32, 64, and 128 effective number of bits (enob) by input voltage range and gain 1 update rate (hz) chop/sinc gain = 32, 62.5 mv, adcxmde = 0x49 gain = 32, 22.18 mv, adcxmde = 0x51 gain = 64, 15.625 mv, adcxmde = 0x59 gain = 64, 10.3125 mv, adcxmde = 0x61 gain = 128, 7.8125 mv, adcxmde = 0x69 gain = 128, 3.98 mv, adcxmde = 0x71 3. 5 3 on/sinc3 19.8 (17.1 p - p) 19.4 (16.7 p - p) 18.7 (16.0 p - p) 18.5 (15.8 p - p) 18.0 (15.3 p - p) 17.2 (14.5 p - p) 30 off/sinc3 18.2 (15.5 p - p) 17.75 (15.0 p - p) 17.3 (14.6 p - p) 17.0 (14.25 p - p) 16.45 (13.7 p - p) 15.6 (12.9 p - p) 50 off/sinc3 18.0 (15.2 p - p) 17.5 (14.8 p - p) 16.93 (14.2 p - p) 16.6 (13.86 p - p) 1 6.2 (13.5 p - p) 15.3 (12.55 p - p) 100 off/sinc3 17.4 (14.7 p - p) 17.1 (14.35 p - p) 16.4 (13.7 p - p) 16.2 (13.5 p - p) 15.6 (12.9 p - p) 15.0 (12.2 p - p) 488 off/sinc4 16.4 (13.7 p - p) 16.0 (13.3 p - p) 15.4 (12.7 p - p) 15.1 (12.4 p - p) 14.6 (11.9 p - p) 13.8 (11.0 p - p) 976 off/sinc4 15.9 (13.2 p - p) 15.6 (12.85 p - p) 14.91 (12.2 p - p) 14.8 (12.0 p - p) 14.2 (11.5 p - p) 13.4 (10.75 p - p) 1953 off/sinc4 15.1 (12.4 p - p) 15.05 (12.3 p - p) 14.4 (11.6 p - p) 14.1 (11.4 p - p) 13.6 (10.9 p - p) 13.0 (10.2 p - p) 3906 off/sinc4 13.2 (10.5 p - p ) 14.0 (11.3 p - p) 13.1 (10.4 p - p) 13.8 (11.1 p - p) 12.8 (10.1 p - p) 12.5 (9.75 p - p) 1 rms bits are calculated as follows: log 2 ((2 input range )/ rms noise ); peak - to - peak (p - p) bits are calculated as follows: log 2 ((2 inp ut range )/(6.6 rms noise )).
aducm360/aducm361 data sheet rev. b | page 12 of 24 external reference (2.5 v) table 6 through table 9 provide rms noise specifications for adc0 and adc1 u sing the ex ternal r eference ( 2.5 v). table 6 and table 7 list the rms noise for both adcs with various gain and output update rate values. table 8 and table 9 list the typical output rms noise effective number of bits (enob) in normal mode for both adcs with various gain and output update rate values. (peak - to - peak enob is shown in parentheses.) table 6. rms noise vs. gain and output update rate, external reference (2.5 v), gain = 1, 2, 4, 8, and 16 rms noise (v) update rate (hz) chop/sinc adcft register value gain = 1, v ref , adcxmde = 0x01 gain = 2, 500 mv, adcxmde = 0x11 gain = 4, 250 mv, adcxmde = 0x21 gain = 8, 125 mv, adcxmde = 0x31 gain = 16, 62.5 mv, adcxmde = 0x41 3. 5 3 on/sinc3 0x8d7c 1.1 0.5 0.27 0.17 0.088 30 off/sinc3 0x007e 3 1.4 0.85 0.44 0.27 50 off/sinc3 0x007d 3.9 2.2 0.92 0.46 0.3 100 off/sinc3 0x004d 5.2 2.8 1.25 0.63 0.38 488 off/sinc4 0x100f 9.3 5.0 2.5 1.2 0.75 976 off/sinc4 0x1007 12.5 7 3.5 1.75 1.2 1953 off/sinc4 0x1003 20.0 10 5.7 2.6 1.71 3906 off/sinc4 0x1001 140.0 70.0 35.0 17.2 8.9 table 7. rms noise vs. gain and output update rate, exte rnal reference (2.5 v), gain = 32, 64, and 128 rms noise (v) update rate (hz) chop/sinc adcft register value gain = 32, 1 62.5 mv, adcxmde = 0x49 gain = 32, 1 , 2 22.18 mv, adcxmde = 0x51 gain = 64, 3 15. 625 mv, adcxmde = 0x59 gain = 64, 3 , 4 10.3125 mv, adcxmde = 0x61 gain = 128, 5 7.8125 mv, adcxmde = 0x69 gain = 128, 5 , 6 3.98 mv, adcxmde = 0x71 3. 5 3 on/sinc3 0x 8d7c 0.076 0.07 0.088 0.06 0.068 0.58 30 off/sinc3 0x007e 0.21 0.22 0.21 0.19 0.175 0.17 50 off/sinc3 0x007d 0.265 0.21 0.27 0.2 0.225 0.19 100 off/sinc3 0x004d 0.37 0.32 0.366 0.28 0.32 0.26 488 off/sinc4 0x100f 0.73 0.7 0.73 0.57 0.64 0.5 976 off/si nc4 0x1007 1.1 0.83 1.01 0.77 0.89 0.75 1953 off/sinc4 0x1003 2.05 1.3 1.6 1.24 1.3 1.1 3906 off/sinc4 0x1001 9.4 4.8 5.1 2.65 3.2 1.88 1 adcxmde = 0x49 sets the pga for a gain of 16 with a modulator gain of 2. the m odulator gain of 2 is implemented by adjusting the sampling cap acitor s into the modulator. adcxmde = 0x51 sets the pga for a gain of 32 with the m odulator gain off. adcxmde = 0x49 has slightly higher noise but supports a wider input range . 2 if avdd < 2.0 v and adcxmde = 0x51, the input range is 17.5 mv . 3 adcxmde = 0x59 sets the pga for a gain of 32 with a modulator gain of 2. the m odulator gain o f 2 is implemented by adjusting the sampling cap acitor s into the modulator. adcxmde = 0x61 sets the pga for a gain of 64 with the modulator gain off. adcxmde = 0x59 has slightly higher noise but supports a wider input range . 4 if avdd < 2.0 v and adcxmde = 0x61, the input range is 8 . 7 1 5 mv . 5 adcxmde = 0x69 sets the pga for a gain of 64 with a modulator gain of 2. the m odulator gain of 2 is implemented by adjusting the sampling cap acitor s into the modulator. adcxmde = 0x71 sets the pga for a gain of 128 wi th the modulator gain off. adcxmde = 0x69 has slightly higher noise but supports a wider input range . 6 if avdd < 2.0 v and adcxmde = 0x71, the input range is 3.828 mv .
data sheet aducm360/aducm361 rev. b | page 13 of 24 table 8. typical output rms noise effective number of bits in normal mode , externa l reference (2.5 v), gain = 1, 2, 4, 8, and 16 effective number of bits (enob) by input voltage range and gain 1 update rate (hz) chop/sinc gain = 1, v ref , adcxmde = 0x01 gain = 2, 500 mv, adcxmde = 0x11 gain = 4, 250 mv, adcxmde = 0x21 gain = 8, 125 mv, adcxmde = 0x31 gain = 16, 62.5 mv, adcxmde = 0x41 3. 5 3 on/sinc3 22.1 (19.4 p - p) 20.9 (18.2 p - p) 20.8 (18.1 p - p) 20.5 (17.7 p - p) 20.43 (17.7 p - p) 30 off/sinc3 20.7 (18 .0 p - p) 19.4 (16.7 p - p) 19.2 (16.4 p - p) 19.1 (16.4 p - p) 18.82 (16.1 p - p) 50 off/sinc3 20.3 (17.6 p - p) 18.8 (16.1 p - p) 19.05 (16.3 p - p) 19.05 (16.3 p - p) 18.66 (15.9 p - p) 100 off/sinc3 19.9 (17.2 p - p) 18.4 (15.7 p - p) 18.6 (15.9 p - p) 18.6 (15.9 p - p) 18.32 (15.6 p - p) 488 off/sinc4 19.0 (16.3 p - p) 17.6 (14.9 p - p) 17.6 (14.9 p - p) 17.7 (14.9 p - p) 17.34 (14.6 p - p) 976 off/sinc4 18.6 (15.9 p - p) 17.1 (14.4 p - p) 17.1 (14.4 p - p) 17.1 (14.4 p - p) 16.66 (13.9 p - p) 1953 off/sinc4 17.9 (15.2 p - p) 16.6 (13.9 p - p) 16.4 (13.7 p - p) 16.55 (13.8 p - p) 16.15 (13.4 p - p) 3906 off/sinc4 15.1 (12.4 p - p) 1 3.8 (11.1 p - p) 13.8 (11.1 p - p) 13.8 (11.1 p - p) 13.77 (11.05 p - p) 1 rms bits are calculated as follows: log 2 ((2 input range )/ rms noise ); peak - to - peak (p - p) bits are calculated as follows: log 2 ((2 input range )/(6.6 rms noise )). table 9. typical output rms noise effective number of bits in normal mode , external reference (2.5 v), gain = 32, 64, and 128 effective number of bits (enob) by i nput voltage range and gain 1 update rate (hz) chop/sinc gain = 32, 62.5 mv, adcxmde = 0x49 gain = 32, 22.18 mv, adcxmde = 0x51 gain = 64, 15.625 mv, adcxmde = 0x59 gain = 64, 10.3125 mv, adcxmde = 0x61 gain = 128, 7.8125 mv, adcxmde = 0x69 gain = 1 28, 3.98 mv, adcxmde = 0x71 3. 5 3 on/sinc3 19.6 (16.9 p - p) 19.3 (16.55 p - p) 18.4 (15.7 p - p) 18.4 (15.7 p - p) 17.8 (15.1 p - p) 17.1 (14.3 p - p) 30 off/sinc3 18.2 (15.5 p - p) 17.6 (14.9 p - p) 17.2 (14.5 p - p) 16.7 (14.0 p - p) 16.4 (13.7 p - p) 15.5 (12.8 p - p) 50 o ff/sinc3 17.8 (15.1 p - p) 17.7 (15.0 p - p) 16.8 (14.1 p - p) 16.65 (13.9 p - p) 16.1 (13.4 p - p) 15.35 (12.6 p - p) 100 off/sinc3 17.4 (14.6 p - p) 17.1 (14.35 p - p) 16.4 (13.7 p - p) 16.2 (13.4 p - p) 15.6 (12.85 p - p) 14.9 (12.2 p - p) 488 off/sinc4 16.4 (13.7 p - p) 16.0 (13.2 p - p) 15.4 (12.7 p - p) 15.1 (12.4 p - p) 14.6 (11.85 p - p) 14.0 (11.2 p - p) 976 off/sinc4 15.8 (13.1 p - p) 15.7 (13.0 p - p) 14.9 (12.2 p - p) 14.7 (12.0 p - p) 14.1 (11.4 p - p) 13.4 (10.6 p - p) 1953 off/sinc4 14.9 (12.1 p - p) 15.1 (12.3 p - p) 14.25 (11.5 p - p) 14.0 (11.3 p - p) 13.55 (10.8 p - p) 12.8 (10.1 p - p) 3906 off/sinc4 12.7 (10.0 p - p) 13.2 (10.4 p - p) 12.6 (9.9 p - p) 12.9 (10.2 p - p) 12.25 (9.5 p - p) 12.0 (9.3 p - p) 1 rms bits are calculated as follows: log 2 ((2 input range )/ rms noise ); peak - to - peak (p - p) bits are calculated as follows: log 2 ((2 input range )/(6.6 rms noise )).
aducm360/aducm361 data sheet rev. b | page 14 of 24 i 2 c timing specifications the capacitive load for each i 2 c bus line (c b ) is 400 pf maximum as per the i 2 c bus specifications. i 2 c timing is guaranteed by design, but is not production tested. table 10. i 2 c timing in fast mode (400 khz) parameter description min max unit t l serial clock (scl) low pulse width 1300 ns t h scl high pulse width 600 ns t shd start condition hold time 600 ns t dsu data setup time 100 ns t dhd data hold time 0 ns t rsu setup time for repeated start 600 ns t psu stop condition setup time 600 ns t buf bus free time between a stop cond ition and a start condition 1.3 ? s t r rise time for both scl and serial data (sda) 20 + 0.1 c b 300 ns t f fall time for both scl and sda 20 + 0.1 c b 300 ns t sup pulse width of suppressed spike 0 50 ns table 11. i 2 c timing in standard mode (100 khz) parameter description min max unit t l scl low pulse width 4.7 s t h scl high pulse width 4.0 ns t shd start condition hold time 4.7 s t dsu data setup time 250 ns t dhd data hold time 0 s t rsu setup time for repeated start 4.0 s t psu stop condition setup time 4.0 s t buf bus free time between a stop condit ion and a start condition 4.7 s t r rise time for both scl and sda 1 s t f fall time for both scl and sda 300 ns sda (i/o) t buf msb lsb ack msb 1 9 8 1 scl (i) ps stop condition start condition s(r) repeated start t sup t r t f t f t r t h t l t sup t dsu t dhd t rsu t dhd t dsu t shd t psu 09743-002 figure 3. i 2 c-compatible in terface timing
data sheet aducm360/aducm361 rev. b | page 15 of 24 spi timing specifications table 12. spi master mode timing parameter description min typ max unit t sl sclk low pulse width 1 (spidiv + 1) t uclk ns t sh sclk high pulse width 1 (spidiv + 1) t uclk ns t dav data output valid after sclk edge 0 35.5 ns t dosu data output setup time before sclk edge 1 (spidiv + 1) t uclk ns t dsu data input setup time before sclk edge 58.7 ns t dhd data input hold time after sclk edge 16 ns t df data output fall time 12 35.5 ns t dr data output rise time 12 35.5 ns t sr sclk rise time 12 35.5 ns t sf sclk fall time 12 35.5 ns 1 t uclk = 62.5 ns. it corresponds to the internal 16 mhz clock before the clock divider. sclk (polarity = 0) cs 1/2 sclk cycle sclk (polarity = 1) mosi msb bit 6 to bit 1 lsb miso msb in bit 6 to bit 1 lsb in t sh t cs t sl 3/4 sclk cycle t sfs t sr t sf t dr t df t dav t dsu t dhd 09743-003 figure 4. spi master mode timing (phase mode = 1) sclk (polarity = 0) sclk (polarity = 1) mosi msb bit 6 to bit 1 lsb miso msb in bit 6 to bit 1 lsb in t sh t sr t sf t dr t df t dav t dosu t dsu t dhd cs 1 sclk cycle t cs t sl 1 sclk cycle t sfs 09743-004 figure 5. spi master mode timing (phase mode = 0)
aducm360/aducm361 data sheet rev. b | page 16 of 24 table 13. spi slave mode timing parameter description min typ max unit t cs cs to sclk edge 62.5 ns t sl sclk low pulse width 1 (spidiv + 1) t uclk ns t sh sclk high pulse width 1 62.5 (spidiv + 1) t uclk ns t dav data output valid after sclk edge 49.1 ns t dsu data input setup time before sclk edge 20.2 ns t dhd data input hold time after sclk edge 10.1 ns t df data output fall time 12 35.5 ns t dr data output rise time 12 35.5 ns t sr sclk rise time 12 35.5 ns t sf sclk fall time 12 35.5 ns t docs data output valid after cs edge 25 ns t sfs cs high after sclk edge 0 ns 1 t uclk = 62.5 ns. it corresponds to the internal 16 mhz clock before the clock divider. sclk (polarity = 0) cs sclk (polarity = 1) t sh t sl t sr t sf t sfs miso msb bit 6 to bit 1 lsb mosi msb in bit 6 to bit 1 lsb in t dhd t dsu t dav t dr t df t cs 0 9743-005 figure 6. spi slave mode timing (phase mode = 1) sclk ( polarity = 0) cs sclk ( polarity = 1) t sh t sl t sr t sf t sfs miso msb bit 6 to bit 1 lsb mosi msb in bit 6 to bit 1 lsb in t dhd t dsu t dav t dr t df t docs t cs 09743-006 figure 7. spi slave mode timing (phase mode = 0)
data sheet aducm360/aducm361 rev. b | page 17 of 24 absolute maximum rat ing s table 14. parameter rating avdd to a gnd ?0.3 v to + 3.96 v iovdd to dgnd ?0.3 v to +3.96 v digital input voltage to dgnd ?0.3 v to + 3.96 v digital output voltage to dgnd ?0.3 v to + 3.96 v analog inputs to agnd ?0.3 v to +3.96 v operating temperature range ?40c to +125c storage temperature range ?65c to +150c junction temperature 150c esd r ating , all pins human body model (hbm) 2 .5 kv field - induced charged device model (ficdm) 1 kv peak solder reflow temperature snpb assemblies (10 sec to 30 sec) 240c pb - free assemblies ( 20 s ec to 40 sec) 260c stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operati onal section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. thermal resistance ja is specified for the worst - case conditions, that is, a device soldered in a circuit board for surface - mount packages. table 15 . thermal resistance package type ja unit 48- lead lfcsp_wq 27 c/w esd caution
aducm360/aducm361 data sheet rev. b | page 18 of 24 pin co nfiguration and func tion descriptions 1 2 3 p0.7/por/sout p0.6/irq2/sin p0.5/cts/irq1 4 p0.4/rts/eclko 5 p0.3/irq0/cs1 6 p0.2/mosi1/sda/sout 7 p0.1/sclk1/scl/sin 24 ain7/vbias0/iexc/extref2in+ 23 ain6/iexc 22 ain5/iexc 21 iref 20 int_ref 19 dac 18 a vdd_reg 17 a vdd 16 agnd 15 vref? 14 vref+ 13 gnd_sw 44 p1.6/irq6/pwm4/mosi0 45 p1.7/irq7/pwm5/cs0 46 p2.0/scl/uartclk 47 swclk 48 swdio 43 p1.5/irq5/pwm3/sclk0 42 p1.4/pwm2/miso0 41 p1.3/pwm1/dsr 40 p1.2/pwm0/ri 39 p1.1/irq4/pwmtrip/dtr 38 p1.0/irq3/pwmsync/extclk 37 iovdd t o p view (not to scale) aducm360/ aducm361 25 ain4/iexc 26 ain3 27 ain2 28 ain1 29 ain0 30 dvdd_reg 31 iovdd 32 x t ali 33 x t alo 34 p2.2/bm 35 p2.1/sda/uartdcd notes 1. the lfcs p has an exposed p ad th a t must be soldered t o a me t a l pl a te on the pcb for mechanica l reasons and t o dgnd. 36 reset 8 p0.0/miso1 9 ain 1 1/vbias1 10 ain10 1 1 ain9/dacbuff+ 12 ain8/extref2in? 09743-007 figure 8 . pin configuration table 16. pin function descriptions pin no. mnemonic description 1 reset reset p in, a ctive l ow input . an internal pull - up is provided. 2 p2.1/sda/uartdcd general - purpose input/ output p2.1/ i 2 c s erial d ata pin/uart d ata c arrier d etect p in. 3 p2.2/bm general - purpose input/output p2.2 / boot m ode i nput s elect p in. when this pin is held low during and for a short time aft er any re set sequence, the part enter s uart download mode. 4 xtal o external crystal oscillator output pin. optional 32.768 khz source for real - time clock. 5 xtal i external crystal oscillator input pin. optional 32.768 khz source for real - time clock. 6 i ovdd digital system supply p in. this pin must be connected to dgnd via a 0.1 f capacitor. 7 dvdd_reg this pin must be connected to dgnd via a 470 nf capacitor and to p in 18, avdd_reg . 8 ain0 adc analog input 0. this pin can be configured as a positive o r negative input to either adc in d ifferential or single - end ed mode. 9 ain1 adc analog input 1. this pin can be configured as a positive or negative input to either adc in d iff erential or single - end ed mode. 10 ain2 adc analog input 2. this pin can be con figured as a positive or negative input to either adc in d ifferential or single - end ed mode. 11 ain3 adc analog input 3. this pin can be configured as a positive or negative input to either adc in d iff erential or single - end ed mode. 12 ain4/iexc adc analog input 4 /excitation current source . this pin can be configured as a positive or negative input to either adc in d ifferential or single - end ed mode (ain4) . this pin can also be configured as the output pin for e xcitation c urrent s ource 0 or excitation curren t source 1 (iexc) . 13 gnd_sw sensor power swi tch to analog ground reference.
data sheet aducm360/aducm361 rev. b | page 19 of 24 pin no. mnemonic description 14 vref+ external reference positive input . a n external reference can be applied between the vref+ and vref ? pins . 15 vref? external reference negative input. an external reference can be applied between the vref+ and vref ? pins . 16 agnd analog system ground r eference p in. 17 avdd analog system supply p in. this pin must be connected to agnd via a 0.1 f capa citor. 18 avdd_reg internal analog regulator supply output. this pin must be connected to agnd via a 470 nf capacitor and to pin 7, dvdd_reg. 19 dac dac voltage output . 20 int_ref internal reference. this pin must be connected to ground via a 470 nf dec oupling capacitor. 21 iref optional r eference c urrent r esistor c onnection for the excitation c urrent s ources . the reference current used for the excitation current sources is set by a low drift ( 5 ppm/c ) external resistor connected to this pin . 22 ain5/ iexc adc analog input 5 /excitation current source . this pin can be configured as a positive or negative input to either adc in differential or single - ended mode (ain5). this pin can also be configured as the output pin for excitation current source 0 or ex citation current source 1 (iexc). 23 ain6/iexc adc analog input 6 /excitation current source . this pin can be configured as a positive or negative input to either adc in differential or single - ended mode (ain6). this pin can also be configured as the outpu t pin for excitation current source 0 or excitation current source 1 (iexc). 24 ain7/vbias0/iexc/extref2in+ adc analog input 7 / bias voltage output /excitation current source /external reference 2 positive input . this pin can be configured as a positive or n egative input to either adc in differential or single - ended mode (ain 7 ). this pin can also be configured as an analog output pin to generate a bias voltage, vbias0 of avdd_reg/2 (vbias0); as the output pin for excitation current source 0 or excitation curr ent source 1 (iexc) ; or as the positive input for external reference 2 (extref2in+) . 25 ain8/ext ref2in ? adc analog input 8/external reference 2 negative input. this pin can be configured as a positive or negative input to either adc in differential or sin gle - ended mode (ain 8 ). this pin can also be configured as the negative input for external reference 2 (extref2in?) . 26 ain9 /dacbuff+ adc analog input 9/noninverting input to the dac output buffer. this pin can be configured as a positive or negative input to either adc in differential or single - ended mode (ain9). this pin can also be configured as the noninverting input to the dac output buffer when the dac is configured for npn mode (dacbuff+) . 27 ain10 adc analog input 10. this pin can be configured as a positive or negative input to either adc in differential or single - ended mode. 28 ain11/vbias1 adc analog input 11/bias voltage output. this pin can be configured as a positive or negative input to either adc in differential or single - ended mode (ain11) . t his pin can also be configured as an analog output pin to generate a bias voltage, vbias1 of avdd_reg/2 (vbias1) . 29 p0.0/miso1 general - purpose input/output p0.0/spi1 master in put, slave o ut put pin. 30 p0.1/sclk1/scl/sin general - purpose input/output p 0.1/spi1 serial clock pin/i 2 c serial clock pin/ uart serial input (d ata i nput for the uart d ownloader ) . 31 p0.2/mosi1/sda/sout general - purpose input/output p0.2 / spi1 master output, slave in put pin/i 2 c serial data pin/ uart serial output (d ata o utput for th e uart d ownloader ). 32 p0.3/irq0/ cs1 general - purpose input/output p0.3 / external interrupt request 0 / spi1 chip select pin (active low). 33 p0.4/rts/eclko general - purpose input/output p0.4 / uart request -to - send signal / external clock o ut put pin for t est p urposes. 34 p0.5/cts/irq1 general - purpose input/output p0.5 / uart clear -to - send signal / external interrupt request 1. 35 p0.6/irq2/sin general - purpose input/output p0.6 / external interrupt request 2 / uart serial input . 36 p0.7/por/sout g eneral - purpose input/output p0.7 / power - o n reset pin ( a ctive h igh) / uart serial output . 37 iovdd digital system supply p in. this pin must be connected to dgnd via a 0.1 f capacitor. 38 p1.0/irq3/pwmsync/e xt clk general - purpose input/output p1.0 / external in terrupt request 3 / pwm e xternal sync hronization i nput/external c lock i nput p in. 39 p1.1/irq4/pwmtrip/dtr general - purpose input/output p1.1 / external interrupt request 4 / pwm e xternal t rip i nput/ uart data t erminal ready p in. 40 p1.2/pwm0/ri general - purpose input/output p1.2/pwm0 output/uart ring indicator p in. 41 p1.3/pwm1/dsr general - purpose input/output p1.3/pwm1 output/uart data set ready p in. 42 p1.4/pwm2/miso0 general - purpose input/output p1.4/pwm2 output / spi0 master in put, slave o ut put pin.
aducm360/aducm361 data sheet rev. b | page 20 of 24 pin no. mnemonic description 43 p1.5 /irq5/pwm3/sclk0 general - purpose input/output p1.5 / external interrupt request 5 / pwm3 output / spi0 serial clock pin. 44 p1.6/irq6/pwm4/mosi0 general - purpose input/output p1.6 / external interrupt request 6 / pwm4 output / spi0 master o ut put , slave input pin. 45 p1.7/irq7/pwm5/ cs0 general - purpose input/output p1.7 / external interrupt request 7 / pwm5 output / spi0 chip select pin (active low). 46 p2.0/scl/uartclk general - purpose input/output p2.0/ i 2 c serial clock pin /input clock pin for uart blo ck only. 47 swclk serial wire d ebug c lock i nput p in. 48 swdio serial wire debug d ata i nput/ o utput pin . ep exposed pad. the lfcsp has an exposed pad that must be soldered to a metal plate on the pcb for mechanical reasons and to dgnd .
data sheet aducm360/aducm361 rev. b | page 21 of 24 typical performa nce characteristics 60 50 40 30 20 input current (na) 10 0 ?10 0.5 1.0 1.5 common-mode vo lt age (v) 2.0 2.5 3.0 3.5 0 ?20 ?30 09743-008 i p i p ? i n i n figure 9 . input current vs. common - mode voltage (v cm ), gain = 4, adc i nput = 250 mv, av dd = 3.6 v, t a = 25 c , v cm = ((ain+) + (ain?))/2 5 4 3 2 1 0 input current (na) ?1 ?2 ?3 0.5 1.0 1.5 common-mode vo lt age (v) 2.0 2.5 3.0 3.5 0 ?4 ?5 09743-009 i p i p ? i n i n figure 10 . input current vs. common - mod e voltage (v cm ), gain = 128 , adc i nput = 7.8125 mv, av dd = 3.6 v, t a = 25 c , v cm = ((ain+) + (ain?))/2 ?40 ?20 0 20 14000000 12000000 10000000 8000000 6000000 4000000 2000000 40 temper a ture (c) adc codes 60 80 100 120 09743-010 figure 11 . adc codes (decimal values) vs. die temperature 0 50 100 150 200 250 0 200 400 600 800 1000 1200 settling time (ms) ca p aci t ance (nf) b oo s t = 0 b oo s t = 30 09743-0 1 1 figure 12 . vbias output settling ti me vs. load capacitance, t a = 25c, iovdd and avdd = 3. 3 v 0 5 10 15 20 25 30 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 pull-u p resis t ance (k?) volt age (v) 09743-012 figure 13 . digital input pin pull - up resistance value vs. voltage applied to digital pin, t a = 25 c , io v dd = 3. 4 v 0 10 20 30 40 50 60 0 0.5 1.0 1.5 2.0 pull-u p resis t ance (k?) volt age (v) 09743-013 figure 14 . digital inp ut pin pull - up resistance value vs. voltage applied to digital pin, t a = 25 c , io v dd = 1.8 v
aducm360/aducm361 data sheet rev. b | page 22 of 24 typical system confi guration figure 15 shows a typical aducm360 / aducm361 configuration . this figure illustrates some of the hardware considerations. the bottom of the lfcsp package has an exposed pad that must be soldered to a metal plate on the pcb for mechanical reasons and to d gn d . the metal plate of the pcb can be connected to ground. t he 0.47 f capacitor on the avdd _reg and dvdd _reg pins should be placed as close to the pins as possible. in noisy environments, an additional 1 nf capacitor can be added to iovdd and av dd . 1 2 3 p0.7/por/sout p0.6/irq2/sin p0.5/cts/irq1 4 p0.4/rts/eclko 5 p0.3/irq0/cs1 6 p0.2/mosi1/sda/sout 7 p0.1/sclk1/scl/sin 24 ain7/vbias0/ iexc/ extref2in+ 23 ain6/iexc 22 ain5/iexc 21 iref 20 int_ref 19 dac 18 avdd_reg 17 avdd 16 agnd 12pf 12pf 15 vref? 14 vref+ 13 gnd_sw 44 p1.6/irq6/ pwm4/mosi0 45 p1.7/irq7/ pwm5/cs0 46 p2.0/scl/ uartclk 47 swclk 48 swdio swclk swdio 43 p1.5/irq5/ pwm3/sclk0 42 p1.4/pwm2/ miso0 41 p1.3/pwm1/ dsr 40 p1.2/pwm0/ri 39 p1.1/irq4/pwmtrip/dtr 38 p1.0/irq3/pwmsync/extclk 37 iovdd aducm360 25 ain4/iexc 26 ain3 27 ain2 28 ain1 29 ain0 30 dvdd_reg dvdd dgnd 31 iovdd 32 xtali 33 xtalo 34 p2.2/bm 35 p2.1/sda/uartdcd 36 reset reset reset reset 8 p0.0/miso1 9 ain11/vbias1 10 ain10 11 ain9/dacbuff+ 12 ain8/extref2in? 0.47f 0.47f 0.1f 150k? gnd dgnd swio tx swclk rx 5v usb swdio interface board connector swclk dvdd dgnd dgnd 0.1f avdd 0.47f 0.1f 0.1f 1f 0.1f 560? 1.6? in out en gnd dgnd dgnd dgnd avdd dvdd agnd agnd agnd 4.7f 4.7f adp1720armz-3.3 09743-100 figure 15 . typical system configuration
data sheet aducm360/aducm361 rev. b | page 23 of 24 outline dimensions 112408-b for proper connection of the exposed pad, refer to the pin configuration and function descriptions section of this data sheet. compliant to jedec standards mo-220- wkkd . 1 0.50 bsc bot t om view top view pin 1 indic a t or 7.00 bsc sq 48 13 24 25 36 37 12 exposed pa d pin 1 indic a t or 5.20 5.10 sq 5.00 0.45 0.40 0.35 sea ting plane 0.80 0.75 0.70 0.05 max 0.02 nom 0.25 min 0.20 ref coplanarity 0.08 0.30 0.23 0.18 figure 16 . 48 - lead lead frame chip scale package [lfcsp_ w q] 7 mm 7 mm body, very very thin quad (cp - 48 - 4) dimensions shown in millimeter s ordering guide model 1 adc s f lash /sram temperature range package description package option ordering quantity ADUCM360BCPZ128 dual 24 - bit 128 kb/ 8 kb ? 40 c to +125 c 48- lead lfcsp_wq cp -48-4 ADUCM360BCPZ128 -r7 dual 24 - bit 128 kb/8 kb ?40c to +125c 48- lead lfcsp_wq cp -48-4 750 aducm361bcpz128 single 24 - bit 128 kb/8 kb ?40c to +125c 48- lead lfcsp_wq cp -48-4 aducm361 b cpz128 - r7 single 24 - bit 128 kb /8 kb ?40c to +125c 48 - lead lfcsp_wq cp - 48 - 4 750 eval - aducm36 0qspz aducm360 quick start p lus d evelopment s yste m 1 z = rohs compliant part.
aducm360/aducm361 data sheet rev. b | page 24 of 24 notes i 2 c refers to a communications protocol originally developed by philips semiconductors (now nxp semiconductors). ? 2012 C 2013 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d 09743 - 0 - 7/13(b)

▲Up To Search▲

Price & Availability of ADUCM360BCPZ128

	To Download ADUCM360BCPZ128 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .