View ATSAM3U1CB-AU_6998507.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

note: this is a summary document. the complete document is available on the atmel website at www.atmel.com. features ? core ? arm ? cortex ? -m3 revision 2.0 running at up to 96 mhz ? memory protection unit (mpu) ?thumb ? -2 instruction set ? memories ? from 64 to 256 kbytes embedded flash, 128-bit wide access, memory accelerator, dual bank ? from 16 to 48 kbytes embedded sram with dual banks ? 16 kbytes rom with embedded bootloader routines (uart, usb) and iap routines ? static memory controller (smc): sram, nor, nand support. nand flash controller with 4 kbyt es ram buffer and ecc ? system ? embedded voltage regulator for single supply operation ? por, bod and watchdog for safe reset ? quartz or resonator oscillat ors: 3 to 20 mhz main and optional low power 32.768 khz for rtc or device clock. ? high precision 8/12 mhz factory trimmed internal rc oscillator with 4 mhz default frequency for fast device startup ? slow clock internal rc oscillator as perman ent clock for device clock in low power mode ? one pll for device clock and one dedi cated pll for usb 2.0 high speed device ? up to 17 peripheral dma (pdc) ch annels and 4-channel central dma ? low power modes ? sleep and backup modes, down to 2.5 a in backup mode ? backup domain: vddbu pin, rtc, 32 backup registers ? ultra low power rtc: 0.6 a ? peripherals ? usb 2.0 device: 480 mbps, 4-kbyte fifo , up to 7 bidirectional endpoints, dedicated dma ? up to 4 usarts (iso7816, irda ? , flow control, spi, manchester support) and one uart ? up to 2 twi (i2c compatible), 1 spi , 1 ssc (i2s), 1 hsmci (sdio/sd/mmc) ? 3-channel 16-bit timer/counter (t c) for capture, compare and pwm ? 4-channel 16-b it pwm (pwmc) ? 32-bit real time timer (rtt) and rtc with cale ndar and alarm features ? 8-channel 12-bit 1msps adc with differenti al input mode and programmable gain stage, 8-channel 10-bit adc ? i/o ? up to 96 i/o lines with external interrup t capability (edge or level sensitivity), debouncing, glitch filtering and on-die series resistor termination ? three 32-bit parallel input/outputs (pio) ? packages ? 100-lead lqfp, 14 x 14 mm, pitch 0.5 mm ? 100-ball tfbga, 9 x 9 mm, pitch 0.8 mm ? 144-lead lqfp, 20 x 20 mm, pitch 0.5 mm ? 144-ball tfbga, 10 x 10 mm, pitch 0.8 mm at91sam arm-based flash mcu sam3u series summary 6430fs?atarm?10-feb-12
2 6430fs?atarm?10-feb-12 sam3u series 1. sam3u description atmel's sam3u series is a member of a family of flash microcontrollers based on the high per- formance 32-bit arm cortex-m3 risc processor. it operates at a maximum speed of 96 mhz and features up to 256 kbytes of flash and up to 52 kbytes of sram. the peripheral set includes a high speed usb device port with embedded transceiver, a high speed mci for sdio/sd/mmc, an external bus interface with nand flash controller, up to 4xusarts (sam3u1c/2c/4c have 3), up to 2xtwis (sam3u1c/2c/4c have 1), up to 5xspis sam3u1c/2c/4c have 4), as well as 4xpwm time rs, 3xgeneral purpose 16-bit timers, an rtc, a 12-bit adc and a 10-bit adc. the sam3u architecture is specific ally designed to sustain high speed data transfers. it includes a multi-layer bus ma trix as well as multiple sram banks, pdc and dma channels that enable it to run tasks in parallel and maximize data throughput. it can operate from 1.62v to 3.6v and comes in 100-pin and 144-pin lqfp and bga packages. the sam3u device is particularly well suited for usb applications: data loggers, pc peripherals and any high speed bridge (usb to sdio, u sb to spi, usb to external bus interface). 1.1 configuration summary the sam3u series differ in memory sizes, package and features list. table 1-1 summarizes the configurations of the six devices. note: 1. the sram size takes into account the 4-kbyte ram buffer of the nand flash controller (nfc) which can be used by the core if not used by the nfc. table 1-1. configuration summary device flash flash organization sram number of pios number of usarts number of twi fwup, shdn pins external bus interface hsmci data size package adc sam3u4e 2x128 kbytes dual plane 52 kbytes 96 4 2 yes 8 or 16 bits, 4 chip selects, 24-bit address 8 bits lqfp144 bga144 2 (8+ 8 channels) sam3u2e 128 kbytes single plane 36 kbytes 96 4 2 yes 8 or 16 bits, 4 chip selects 24-bit address 8 bits lqfp144 bga144 2 (8+ 8 channels) sam3u1e 64 kbytes single plane 20 kbytes 96 4 2 yes 8 or 16 bits, 4 chip selects, 24-bit address 8 bits lqfp144 bga144 2 (8+ 8 channels) sam3u4c 2 x 128 kbytes dual plane 52 kbytes 57 3 1 fwup 8 bits, 2 chip selects, 8-bit address 4 bits lqfp100 bga100 2 (4+ 4 channels) sam3u2c 128 kbytes single plane 36 kbytes 57 3 1 fwup 8 bits, 2 chip selects, 8- bit address 4 bits lqfp100 bga100 2 (4+ 4 channels) sam3u1c 64 kbytes single plane 20 kbytes 57 3 1 fwup 8 bits 2 chip selects, 8-bit address 4 bits lqfp100 bga100 2 (4+ 4 channels)
3 6430fs?atarm?10-feb-12 sam3u series 2. sam3u block diagram figure 2-1. 144-pin sam3u4/2/1e block diagram d0-d15 a0/nbs0 a2-a20 ncs0 ncs1 nrd nwr0/nwe nwr1/nbs1 apb a1 shdn fwup nandoe, nandwe slave master a23 nwait ebi static memory controller nand flash controller & ecc ncs2 ncs3 hsmci twi0 twi1 usart0 usart1 usart2 usart3 pwm tc0 tc1 tc2 ssc dma usb device hs 8-channel 12-bit adc 10-bit adc da0-da7 cda ck twck0-twck1 cts0-cts3 rtso-rts3 sck0-sck3 rdx0-rdx3 txd0-txd3 npcs0-npcs3 spck mosi miso pwmh0-pwmh3 tclk0-tclk2 tioa0-tioa2 tiob0-tiob2 tk tf td rd rf rk adtrg-ad12btrg ad0-ad7 vd d ana vbg dfsdp dfsdm dhsdp dhsdm vddutmii in-circuit emulator tdi tdo/traceswo tms/swdio tck/swclk jtagsel i/d a21/ nandale a22/ nandcle dcd0 dtr0 ri0 pdc 5-layer ahb bus matrix spi mpu dma pdc dsr0 n v i c s pdc pdc voltage regulator vddin vddout twd0-twd1 pwml0-pwml3 nandrdy nand flash sram (4kbytes) advref-ad12bvref ad12b0-ad12b7 flash unique identifier uart urxd utxd pdc plla tst pck0 -pck2 system controller vddbu xin nrst pmc upll xout wdt rtt osc 32k xin32 xout32 supc rstc 8 gpbreg osc 3-20 m pioa pioc piob por rtc rc 32k sm bod vddcore vddutmi rc osc. 12/8/4 m erase nrstb cortex-m3 processor fmax 96 mhz systick counter jtag & serial wire hs utmi transceiver peripheral dma controller peripheral bridge rom 16 kbytes 4-channel dma sram0 32 kbytes 16 kbytes 8 kbytes flash 2x128 kbytes 1x128 kbytes 1x64 kbytes sram1 16 kbytes 16 kbytes
4 6430fs?atarm?10-feb-12 sam3u series figure 2-2. 100-pin sam3u4/2/1c block diagram d0-d7 a0 a2-a7 ncs0 ncs1 nrd nwe apb a1 shdn fwup nandoe, nandwe slave master ebi static memory controller nand flash controller & ecc hsmci twi usart0 usart1 usart2 pwm tc0 tc1 tc2 ssc peripheral dma controller peripheral bridge rom 16 kbytes 4-channel dma dma usb device hs 4-channel 12-bit adc 10-bit adc da0-da3 cda ck twck0 cts0-cts2 rtso-rts2 sck0-sck2 rdx0-rdx2 txd0-txd2 npcs0-npcs3 spck mosi miso pwmh0-pwmh3 tclk0-tclk2 tioa0-tioa2 tiob0-tiob2 tk tf td rd rf rk adtrg-ad12btrg ad0-ad3 vddana vbg dfsdp dfsdm sram0 32 kbytes 16 kbytes 8 kbytes dhsdp dhsdm vddutmii in-circuit emulator tdi tdo/traceswo tms/swdio tck/swclk jtagsel i/d dcd0 dtr0 ri0 pdc 5-layer ahb bus matrix spi mpu dma pdc dsr0 n v i c flash 2x128 kbytes 1x128 kbytes 1x64 kbytes s sram1 16 kbytes 16 kbytes pdc pdc voltage regulator vddin vddout twd0 pwml0-pwml3 nandrdy nand flash sram (4kbytes) advref-ad12bvref ad12b0-ad12b3 flash unique identifier uart urxd utxd pdc plla tst pck0 -pck2 system controller vddbu xin nrst pmc upll xout wdt rtt osc 32k xin32 xout32 supc rstc 8 gpbreg osc 3-20 m pioa piob por rtc rc 32k sm bod vddcore vddutmi rc osc. 12/8/4 m erase nrstb cortex-m3 processor fmax 96 mhz systick counter jtag & serial wire hs utmi transceiver nandcle nandale
5 6430fs?atarm?10-feb-12 sam3u series 3. signal description table 3-1 gives details on the signal names classified by peripheral. table 3-1. signal description list signal name function type active level voltag e reference comments power supplies vddio peripherals i/o lines power supply power 1.62v to 3.6v vddin voltage regulator input power 1.8v to 3.6v vddout voltage regulator output power 1.8v vddutmii usb utmi+ interface power supply power 3.0v to 3.6v gndutmii usb utmi+ interface ground ground vddbu backup i/o lines power supply power 1.62v to 3.6v gndbu backup ground ground vddpll pll a, upll and osc 3-20 mhz power supply power 1.62 v to 1.95v gndpll pll a, upll and osc 3-20 mhz ground ground vddana adc analog power supply power 2.0v to 3.6v gndana adc analog ground ground vddcore core, memories and peripherals chip power supply power 1.62v to 1.95v gnd ground ground clocks, oscillators and plls xin main oscillator input input vddpll xout main oscillator output output xin32 slow clock oscillator input input vddbu xout32 slow clock oscillator output output vbg bias voltage reference analog pck0 - pck2 programmable clock output output vddio shutdown, wakeup logic shdn shut-down control output vddbu push/pull 0: the device is in backup mode 1: the device is running (not in backup mode) fwup force wake-up input input low needs external pull-up serial wire/jtag debug port (swj-dp) tck/swclk test clock/serial wire clock input vddio no pull-up resistor tdi test data in input no pull-up resistor tdo/traceswo test data out/trac e asynchronous data out output (4) tms/swdio test mode select/serial wire input/output input no pull-up resistor jtagsel jtag selection input high vddbu internal permanent pull-down
6 6430fs?atarm?10-feb-12 sam3u series flash memory erase flash and nvm configuration bits erase command input high vddbu internal permanent 15k pulldown reset/test nrst microcontroller reset i/o low vddio internal permanent pullup nrstb asynchronous microcontroller reset input low vddbu internal permanent pullup tst test select input internal permanent pulldown universal asynchronous receiver transceiver - uart urxd uart receive data input utxd uart transmit data output pio controller - pioa - piob - pioc pa0 - pa31 parallel io controller a i/o vddio ?schmitt trigger (1) reset state: ?pio input ?internal pullup enabled pb0 - pb31 parallel io controller b i/o ?schmitt trigger (2) reset state: ?pio input ?internal pullup enabled pc0 - pc31 parallel io controller c i/o ?schmitt trigger (3) reset state: ?pio input ?internal pullup enabled external bus interface d0 - d15 data bus i/o a0 - a23 address bus output nwait external wait signal input low static memory controller - smc ncs0 - ncs3 chip select lines output low nwr0 - nwr1 write signal output low nrd read signal output low nwe write enable output low nbs0 - nbs1 byte mask signal output low nand flash controller - nfc nandoe nand flash output enable output low nandwe nand flash write enable output low nandrdy nand ready input table 3-1. signal description list (continued) signal name function type active level voltag e reference comments
7 6430fs?atarm?10-feb-12 sam3u series high speed multimedia card interface - hsmci ck multimedia card clock i/o cda multimedia card slot a command i/o da0 - da7 multimedia card slot a data i/o universal synchronous asynchrono us receiver transmitter - usartx sckx usartx serial clock i/o txdx usartx transmit data i/o rxdx usartx receive data input rtsx usartx request to send output ctsx usartx clear to send input dtr0 usart0 data terminal ready i/o dsr0 usart0 data set ready input dcd0 usart0 data carrier detect input ri0 usart0 ring indicator input synchronous serial controller - ssc td ssc transmit data output rd ssc receive data input tk ssc transmit clock i/o rk ssc receive clock i/o tf ssc transmit frame sync i/o rf ssc receive frame sync i/o timer/counter - tc tclkx tc channel x external clock input input tioax tc channel x i/o line a i/o tiobx tc channel x i/o line b i/o pulse width modulation controller- pwmc pwmhx pwm waveform output high for channel x output pwmlx pwm waveform output low for channel x output only output in complementary mode when dead time insertion is enabled pwmfi0-2 pwm fault input input serial peripheral interface - spi miso master in slave out i/o mosi master out slave in i/o spck spi serial clock i/o npcs0 spi peripheral chip select 0 i/o low npcs1 - npcs3 spi peripheral chip select output low table 3-1. signal description list (continued) signal name function type active level voltag e reference comments
8 6430fs?atarm?10-feb-12 sam3u series notes: 1. pioa: schmitt trigger on all except pa14 on 100 and 144 packages. 2. piob: schmitt trigger on all except pb9 to pb16, pb25 to pb31 on 100 and 144 packages. 3. pioc: schmitt trigger on all except pc20 to pc27 on 144 package. 4. tdo pin is set in input mode when the cortex-m3 core is not in debug mode. thus an external pull-up (100 k ) must be added to avoid current consumption due to floating input. 3.1 design considerations in order to facilitate schematic capture when using a sam3u design, atmel provides a ?sche- matics checklist? application note. please visit http://www.atmel.com/products/at91/ for additional documentation. two-wire interface - twi twdx twix two-wire serial data i/o twckx twix two-wire serial clock i/o 12-bit analog-to-digi tal converter - adc12b ad12bx analog inputs analog ad12btrg adc trigger input ad12bvref adc reference analog 10-bit analog-to-digit al converter - adc adx analog inputs analog adtrg adc trigger input advref adc reference analog fast flash programming interface - ffpi pgmen0-pgmen2 programming enabling input vddio pgmm0-pgmm3 programming mode input pgmd0-pgmd15 programming data i/o pgmrdy programming ready output high pgmnvalid data direction output low pgmnoe programming read input low pgmck programming clock input pgmncmd programming command input low usb high speed device - udphs dfsdm usb device full speed data - analog vddutmii dfsdp usb device full speed data + analog dhsdm usb device high speed data - analog dhsdp usb device high speed data + analog table 3-1. signal description list (continued) signal name function type active level voltag e reference comments
9 6430fs?atarm?10-feb-12 sam3u series 4. package and pinout the sam3u4/2/1e is available in 144-lead lqfp and 144-ball tfbga packages. the sam3u4/2/1c is available in 100-lead lqfp and 100-ball tfbga packages. 4.1 sam3u4/2/1e package and pinout 4.1.1 144-ball tfbga package outline the 144-ball tfbga package has a 0.8 mm ball pitch and respects green standards. its dimensions are 10 x 10 x 1.4 mm. figure 4-1. orientation of the 144-ball tfbga package 4.1.2 144-lead lqfp package outline figure 4-2. orientation of the 144-lead lqfp package top view ball a1 12 1 2 3 4 5 6 7 8 9 10 11 abcdef ghj kl m 7 3 109 10 8 72 3 7 3 6 1 144
10 6430fs?atarm?10-feb-12 sam3u series 4.1.3 144-lead lqfp pinout table 4-1. 144-pin sam3u4/2/1e pinout 1 tdi 37 dhsdp 73 vddana 109 pa0/ pgmncmd 2 vddout 38 dhsdm 74 advref 110 pc0 3 vddin 39 vbg 75 gndana 111 pa1/ pgmrdy 4tdo/ traceswo 40 vddutmi 76 ad12bvref 112 pc1 5 pb31 41 dfsdm 77 pa22/ pgmd14 113 pa2/ pgmnoe 6 pb30 42 dfsdp 78 pa30 114 pc2 7tms/ swdio 43 gndutmi 79 pb3 115 pa3/ pgmnvalid 8 pb29 44 vddcore 80 pb4 116 pc3 9tck/ swclk 45 pa28 81 pc15 117 pa4/ pgmm0 10 pb28 46 pa29 82 pc16 118 pc4 11 nrst 47 pc22 83 pc17 119 pa5/ pgmm1 12 pb27 48 pa31 84 pc18 120 pc5 13 pb26 49 pc23 85 vddio 121 pa6/ pgmm2 14 pb25 50 vddcore 86 vddcore 122 pc6 15 pb24 51 vddio 87 pa13/ pgmd5 123 pa7/ pgmm3 16 vddcore 52 gnd 88 pa14/ pgmd6 124 pc7 17 vddio 53 pb0 89 pc10 125 vddcore 18 gnd 54 pc24 90 gnd 126 gnd 19 pb23 55 pb1 91 pa15/ pgmd7 127 vddio 20 pb22 56 pc25 92 pc11 128 pa8/ pgmd0 21 pb21 57 pb2 93 pa16/ pgmd8 129 pc8 22 pc21 58 pc26 94 pc12 130 pa9/ pgmd1 23 pb20 59 pb11 95 pa17/ pgmd9 131 pc9 24 pb19 60 gnd 96 pb16 132 pa10/ pgmd2 25 pb18 61 pb12 97 pb15 133 pa11/ pgmd3 26 pb17 62 pb13 98 pc13 134 pa12/ pgmd4 27 vddcore 63 pc27 99 pa18/ pgmd10 135 fwup 28 pc14 64 pa27 100 pa19/ pgmd11 136 shdn 29 pb14 65 pb5 101 pa20/ pgmd12 137 erase 30 pb10 66 pb6 102 pa21/ pgmd13 138 tst 31 pb9 67 pb7 103 pa23/ pgmd15 139 vddbu 32 pc19 68 pb8 104 vddio 140 gndbu 33 gndpll 69 pc28 105 pa24 141 nrstb 34 vddpll 70 pc29 106 pa25 142 jtagsel 35 xout 71 pc30 107 pa26 143 xout32 36 xin 72 pc31 108 pc20 144 xin32
11 6430fs?atarm?10-feb-12 sam3u series 4.1.4 144-ball tfbga pinout table 4-2. 144-ball sam3u4/2/1e pinout a1 vbg d1 dfsdm g1 pb0 k1 pb7 a2 vddutmi d2 dhsdm g2 pc26 k2 pc31 a3 pb9 d3 gndpll g3 pb2 k3 pc29 a4 pb10 d4 pc14 g4 pc25 k4 pb3 a5 pb19 d5 pb21 g5 pb1 k5 pb4 a6 pc21 d6 pb23 g6 gnd k6 pa14/pgmd6 a7 pb26 d7 pb24 g7 gnd k7 pa16/pgmd8 a8 tck/swclk d8 pb28 g8 vddcore k8 pa18/pgmd10 a9 pb30 d9 tdi g9 pc4 k9 pc20 a10 tdo/traceswo d10 vddbu g10 pa6/pgmm2 k10 pa1/pgmrdy a11 xin32 d11 pa10/pgmd2 g11 pa7/pgmm3 k11 pc1 a12 xout32 d12 pa11/pgmd3 g12 pc6 k12 pc2 b1 vddcore e1 pc22 h1 pc24 l1 pc30 b2 gndutmi e2 pa28 h2 pc27 l2 advref b3 xout e3 pc19 h3 pa27 l3 ad12bvref b4 pb14 e4 vddcore h4 pb12 l4 pa22/pgmd14 b5 pb17 e5 gnd h5 pb11 l5 pc17 b6 pb22 e6 vddio h6 gnd l6 pc10 b7 pb25 e7 gndbu h7 vddcore l7 pc12 b8 pb29 e8 nrst h8 pb16 l8 pa19/pgmd11 b9 vddin e9 pb31 h9 pb15 l9 pa23/pgmd15 b10 jtagsel e10 pa12/pgmd4 h10 pc3 l10 pa0/pgmncmd b11 erase e11 pa8/pgmd0 h11 pa5/pgmm1 l11 pa26 b12 shdn e12 pc8 h12 pc5 l12 pc0 c1 dfsdp f1 pa31 j1 pb5 m1 vddana c2 dhsdp f2 pa29 j2 pb6 m2 gndana c3 xin f3 pc23 j3 pc28 m3 pa30 c4 vddpll f4 vddcore j4 pb8 m4 pc15 c5 pb18 f5 vddio j5 pb13 m5 pc16 c6 pb20 f6 gnd j6 vddio m6 pc18 c7 pb27 f7 gnd j7 pa13/pgmd5 m7 pa15/pgmd7 c8 tms/swdio f8 vddio j8 pa17/pgmd9 m8 pc11 c9 vddout f9 pc9 j9 pc13 m9 pa20/pgmd12 c10 nrstb f10 pa9/pgmd1 j10 pa2/pgmnoe m10 pa21/pgmd13 c11 tst f11 vddcore j11 pa3/pgmnvalid m11 pa24 c12 fwup f12 pc7 j12 pa4/pgmm0 m12 pa25
12 6430fs?atarm?10-feb-12 sam3u series 4.2 sam3u4/2/1c package and pinout 4.2.1 100-lead lqfp package outline figure 4-3. orientation of the 100-lead lqfp package 4.2.2 100-ball tfbga package outline figure 4-4. orientation of the 100-ball tfbga package 51 76 75 50 26 25 1 100 1 2 3 4 5 6 7 8 9 10 a b c d e f g h j k top view
13 6430fs?atarm?10-feb-12 sam3u series 4.2.3 100-lead lqfp pinout table 4-3. 100-pin sam3u4/2/1c1 pinout 1 vddana 26 pa0/ pgmncmd 51 tdi 76 dhsdp 2 advref 27 pa1/ pgmrdy 52 vddout 77 dhsdm 3gndana 28pa2/ pgmnoe 53 vddin 78 vbg 4 ad12bvref 29 pa3/ pgmnvalid 54 tdo/ traceswo 79 vddutmi 5pa22/ pgmd14 30 pa4/ pgmm0 55 tms/ swdio 80 dfsdm 6 pa30 31 pa5/ pgmm1 56 tck/ swclk 81 dfsdp 7 pb3 32 pa6/ pgmm2 57 nrst 82 gndutmi 8 pb4 33 pa7/ pgmm3 58 pb24 83 vddcore 9 vddcore 34 vddcore 59 vddcore 84 pa28 10 pa13/ pgmd5 35 gnd 60 vddio 85 pa29 11 pa14/ pgmd6 36 vddio 61 gnd 86 pa31 12 pa15/ pgmd7 37 pa8/ pgmd0 62 pb23 87 vddcore 13 pa16/ pgmd8 38 pa9/ pgmd1 63 pb22 88 vddio 14 pa17/ pgmd9 39 pa10/ pgmd2 64 pb21 89 gnd 15 pb16 40 pa11/ pgmd3 65 pb20 90 pb0 16 pb15 41 pa12/ pgmd4 66 pb19 91 pb1 17 pa18/ pgmd10 42 fwup 67 pb18 92 pb2 18 pa19/ pgmd11 43 erase 68 pb17 93 pb11 19 pa20/ pgmd12 44 tst 69 pb14 94 pb12 20 pa21/ pgmd13 45 vddbu 70 pb10 95 pb13 21 pa23/ pgmd15 46 gndbu 71 pb9 96 pa27 22 vddio 47 nrstb 72 gndpll 97 pb5 23 pa24 48 jtagsel 73 vddpll 98 pb6 24 pa25 49 xout32 74 xout 99 pb7 25 pa26 50 xin32 75 xin 100 pb8
14 6430fs?atarm?10-feb-12 sam3u series 4.2.4 100-ball tfbga pinout table 4-4. 100-ball sam3u4/2/1c pinout a1 vbg c6 pb22 f1 pb1 h6 pa15/pgmd7 a2 xin c7 tms/swdio f2 pb12 h7 pa18/pgmd10 a3 xout c8 nrstb f3 vddio h8 pa24 a4 pb17 c9 jtagsel f4 pa31 h9 pa1/pgmrdy a5 pb21 c10 vddbu f5 vddio h10 pa2/pgmnoe a6 pb23 d1 dfsdm f6 gnd j1 pb6 a7 tck/swclk d2 dhsdm f7 pb16 j2 pb8 a8 vddin d3 vddpll f8 pa6/pgmm2 j3 advref a9 vddout d4 vddcore f9 vddcore j4 pa30 a10 xin32 d5 pb20 f10 pa7/pgmm3 j5 pb3 b1 vddcore d6 erase g1 pb11 j6 pa16/pgmd8 b2 gndutmi d7 tst g2 pb2 j7 pa19/pgmd11 b3 vddutmi d8 fwup g3 pb0 j8 pa21/pgmd13 b4 pb10 d9 pa11/pgmd3 g4 pb13 j9 pa26 b5 pb18 d10 pa12/pgmd4 g5 vddcore j10 pa0/pgmncmd b6 pb24 e1 pa29 g6 gnd k1 pb7 b7 nrst e2 gnd g7 pb15 k2 vddana b8 tdo/traceswo e3 pa28 g8 pa3/pgmnvalid k3 gndana b9 tdi e4 pb9 g9 pa5/pgmm1 k4 ad12bvref b10 xout32 e5 gndbu g10 pa4/pgmm0 k5 pb4 c1 dfsdp e6 vddio h1 vddcore k6 pa14/pgmd6 c2 dhsdp e7 vddcore h2 pb5 k7 pa17/pgmd9 c3 gndpll e8 pa10/pgmd2 h3 pa27 k8 pa20/pgmd12 c4 pb14 e9 pa9/pgmd1 h4 pa22/pgmd14 k9 pa23/pgmd15 c5 pb19 e10 pa8/pgmd0 h5 pa13/pgmd5 k10 pa25
15 6430fs?atarm?10-feb-12 sam3u series 5. power considerations 5.1 power supplies the sam3u product has several types of power supply pins: ? vddcore pins: power the core, the embedded memories and the peripherals; voltage ranges from 1.62v to 1.95v. ? vddio pins: power the peripherals i/o lines; voltage ranges from 1.62v to 3.6v. ? vddin pin: powers the voltage regulator ? vddout pin: it is the output of the voltage regulator. ? vddbu pin: powers the slow clock oscillator and a part of the system controller; voltage ranges from 1.62v to 3.6v. vddbu must be supplied before or at the same time than vddio and vddcore. ? vddpll pin: powers the pll a, upll and 3- 20 mhz oscillator; voltage ranges from 1.62v to 1.95v. ? vddutmi pin: powers the utmi+ interface; voltage ranges from 3.0v to 3.6v, 3.3v nominal. ? vddana pin: powers the adc cells; voltage ranges from 2.0v to 3.6v. ground pins gnd are common to vddcore and vddio pins power supplies. separated ground pins are provided for vd dbu, vddpll, vddutmi and vddana. these ground pins are respectively gndbu, gndpll, gndutmi and gndana. 5.2 voltage regulator the sam3u embeds a voltage regulator that is managed by the supply controller. this internal regulator is intended to supply the internal core of sam3u but can be used to sup- ply other parts in the application. it features two different operating modes: ? in normal mode, the voltage regulator consumes less than 700 a static current and draws 150 ma of output current. internal adaptive biasing adjusts the regulator quiescent current depending on the required load current. in wait mode or when the output current is low, quiescent current is only 7a. ? in shutdown mode, the voltage regulator consumes less than 1 a while its output is driven internally to gnd. the default output voltage is 1.80v and the start-up time to reach normal mode is inferior to 400 s. for adequate input and output power supply decoupling/bypassing, refer to ?voltage regulator? in the ?electrical characteristics? section of the product datasheet. 5.3 typical powe ring schematics the sam3u supports a 1.8v-3.6v single supply mode. the internal regulator input connected to the source and its output feed vddcore. figure 5-1 , figure 5-2 , figure 5-3 show the power schematics.
16 6430fs?atarm?10-feb-12 sam3u series figure 5-1. single supply note: restrictions with main supply < 2.0 v, usb and adc are not usable. with main supply 2.4v and < 3v, usb is not usable. with main supply 3v, all peripherals are usable. vddin voltage regulator vddout main supply (1.62v-3.6v) vddcore vddbu vddutmi vddio vddana vddpll
17 6430fs?atarm?10-feb-12 sam3u series figure 5-2. core externally supplied note: restrictions with main supply < 2.0 v, usb and adc are not usable. with main supply 2.4v and < 3v, usb is not usable. with main supply 3v, all peripherals are usable. vddin voltage regulator vddout main supply (1.62v-3.6v) vddcore vddcore supply (1.62v-1.95v) vddbu vddio vddana vddutmi vddpll
18 6430fs?atarm?10-feb-12 sam3u series figure 5-3. backup batteries used note: restrictions with main supply < 2.0 v, usb and adc are not usable. with main supply 2.4v and < 3v, usb is not usable. with main supply 3v, all peripherals are usable. vddin voltage regulator vddout main supply (1.62v-3.6v) vddcore backup batteries vddbu vddio vddana vddutmi vddpll fwup shdn
19 6430fs?atarm?10-feb-12 sam3u series 5.4 active mode active mode is the normal runn ing mode with the core clock runn ing from the fast rc oscillator, the main crystal oscillator or the plla. the po wer management controller can be used to adapt the frequency and to disable the peripheral clocks. 5.5 low power modes the various low power modes of the sam3u are described below: 5.5.1 backup mode the purpose of backup mode is to achieve the lo west power consumption possible in a system which is performing periodic wake-ups to perform tasks but not requiring fast startup time (<0.5ms). the supply controller, zero-power power-on reset, rtt, rtc, backup registers and 32 khz oscillator (rc or crystal oscillator selected by software in the supply controller) are running. the regulator and the core supply are off. backup mode is based on the cortex-m3 deep-sleep mode with the voltage regulator disabled. the sam3u series can be awakened from this mode through the force wake-up pin (fwup), and wake-up input pins wkup0 to wkup15, supply monitor, rtt or rtc wake-up event. cur- rent consumption is 2.5 a typical on vddbu. backup mode is enter ed by using wfe instructions with the sleepdeep bit in the system con- trol register of the cortex-m3 set to 1. (see the ?power management? description in the ?arm cortex m3 processor? section of the product datasheet). exit from backup mode happens if one of the following enable wake up events occurs: ? fwup pin (low level, configurable debouncing) ? wkupen0-15 pins (level transition, configurable debouncing) ?sm alarm ?rtc alarm ? rtt alarm 5.5.2 wait mode the purpose of the wait mode is to achieve very low power consumption while maintaining the whole device in a powered state for a startup time of less than 10 s. in this mode, the clocks of the core, peripherals and memories are stopped. however, the core, peripherals and memories power supplies are still powered. from this mode, a fast start up is available. this mode is entered via wait for event (wfe) instructions with lpm = 1 (low power mode bit in pmc_fsmr). the cortex-m3 is able to handle external events or internal events in order to wake-up the core (wfe). this is done by conf iguring the external lines wkup0-15 as fast startup wake-up pins (refer to section 5.7 ?fast start-up? ). rtc or rtt alarm and usb wake-up events can be used to wake up the cpu (exit from wfe). current consumption in wait mode is typically 15 a on vddin if the internal voltage regulator is used or 8 a on vddcore if an external regulator is used.
20 6430fs?atarm?10-feb-12 sam3u series entering wait mode: ? select the 4/8/12 mhz fast rc oscillator as main clock ? set the lpm bit in the pmc fast startup mode register (pmc_fsmr) ? execute the wait-for-event (wfe) instruction of the processor note: internal main cloc k resynchronization cycles are necessa ry between the writing of moscrcen bit and the effective entry in wait mode. depending on the user app lication, waiting for moscrcen bit to be cleared is recommended to en sure that the core will not execute undesired instructions. 5.5.3 sleep mode the purpose of sleep mode is to optimize power consumption of the device versus response time. in this mode, only the core clock is stopped. the peripheral clocks can be enabled. this mode is entered via wait for interrupt (wfi) or wait for event (wfe) instructions with lpm = 0 in pmc_fsmr. the processor can be awakened from an interrupt if wfi instruction of the cortex m3 is used, or from an event if the wfe instruction is used to enter this mode.
21 6430fs?atarm?10-feb-12 sam3u series 5.5.4 low power mode summary table the modes detailed above are the main low power modes. each part can be set to on or off sep- arately and wake up sources can be individually configured. table 5-1 below shows a summary of the configurations of the low power modes. notes: 1. when considering wake-up time, the time required to start the pll is not taken into accoun t. once started, the device w orks with the 4/8/12 mhz fast rc oscilla tor. the user has to add the pll start-up time if it is nee ded in the system . the wake-up time is defined as the time taken for wake up until the first instruction is fetched. 2. the external loads on pios are not taken into account in the calculation. 3. bod current consumption is not included. 4. current consumption on vddbu. 5. 8 a total current consumption - without using internal voltage regulator. 15 a total current consumption - using internal voltage regulator. 6. depends on mck frequency. 7. in this mode the core is supplied and not clocked but some peripherals can be clocked. table 5-1. low power mode conf iguration summary mode supc, 32 khz oscillator rtc rtt backup registers, por (vddbu region) regulator core memory peripherals mode entry potential wake up sources core at wake up pio state while in low power mode pio state at wake up consumption (2) (3) wake-up time (1) backup mode on off shdn =0 off (not powered) wfe +sleepdeep bit = 1 fwup pin wkup0-15 pins bod alarm rtc alarm rtt alarm reset previous state saved pioa & piob & pioc inputs with pull ups 2.5 a typ (4) < 0.5 ms wait mode on on shdn =1 powered (not clocked) wfe +sleepdeep bit = 0 +lpm bit = 1 any event from: fast startup through wkup0-15 pins rtc alarm rtt alarm usb wake-up clocked back previous state saved unchanged 8 a/15 a (5) < 10 s sleep mode on on shdn =1 powered (7) (not clocked) wfe or wfi +sleepdeep bit = 0 +lpm bit = 0 entry mode =wfi interrupt only; entry mode =wfe any enabled interrupt and/or any event from: fast start-up through wkup0-15 pins rtc alarm rtt alarm usb wake-up clocked back previous state saved unchanged (6) (6)
22 6430fs?atarm?10-feb-12 sam3u series 5.6 wake-up sources the wake-up events allow the device to exit backup mode. when a wake-up event is detected, the supply controller performs a sequence wh ich automatically reenables the core power supply. figure 5-4. wake-up source wkup15 fwup rtt_alarm rtc_alarm sm_int wkup0 wkup1 wkupt1 core supply restart debouncer wkupdbc wkups debouncer fwupdbc fwup wkupis0 wkupis1 wkupis15 rtten rtcen smen wkupen15 wkupen1 wkupen0 fwupen wkupt15 falling/rising edge detector wkupt0 falling/rising edge detector falling/rising edge detector falling edge detector slck slck
23 6430fs?atarm?10-feb-12 sam3u series 5.7 fast start-up the sam3u allows the processor to restart in a few microseconds while the processor is in wait mode. a fast start up can occur upon detection of a low level on one of the 19 wake-up inputs. the fast restart circuitry, as shown in figure 5-5 , is fully asynchronous and provides a fast start- up signal to the power management controller. as soon as the fast start-up signal is asserted, the pmc automatically restarts the embedded 4/ 8/12 mhz fast rc oscillator, switches the mas- ter clock on this 4/8/12 mhz clock and reenables the processor clock. figure 5-5. fast start-up sources rtcen rtc_alarm rtten rtt_alarm usben usb_wakeup fast_restart wkup15 fstt15 wkup1 wkup0 fstt0 fstt1 high/low level detector high/low level detector high/low level detector
24 6430fs?atarm?10-feb-12 sam3u series 6. input/output lines the sam3u has different kinds of input/output (i/o) lines, such as general purpose i/os (gpio) and system i/os. gpios can have alternate functi ons thanks to multiplexi ng capabilities of the pio controllers. the same gpio line can be used whether it is in io mode or used by the multi- plexed peripheral. system i/os are pins such as te st pin, oscillators, erase pin, analog inputs or debug pins. with a few exceptions, the i/os have input schmitt triggers. refer to the footnotes associated with ?pio controller - pioa - piob - pioc? on page 6 within table 3-1, ?signal description list? . 6.1 general purpos e i/o lines (gpio) gpio lines are managed by pio controllers. all i/os have several input or output modes such as, pull-up, input schmitt triggers, multi-drive (open-drain), glitch filters, debouncing or input change interrupt. programming of these modes is performed independently for each i/o line through the pio controller user interface. for more details, refer to the ?pio controller? section of the product datasheet. the input output buffers of the pio lines are supplied through vddio power supply rail. the sam3u embeds high speed pads able to handle up to 65 mhz for hsmci and spi clock lines and 35 mhz on other lines. see ?ac charac teristics? of the product datasheet for more details. typical pull-up value is 100 k for all i/os. each i/o line also embeds an odt (on-die termination), (see figure 6-1 below). odt consists of an internal series resistor termination scheme for impedance matching between the driver output (sam3) and the pcb track impedance preventing signal reflection. the series resistor helps to reduce i/os switching current (di/dt) thereby reducing in turn, emi. it also decreases overshoot and undershoot (ringing) due to inductance of interconnect between devices or between boards. in conclusion, odt he lps reducing signal integrity issues. figure 6-1. on-die termination schematic 6.2 system i/o lines system i/o lines are pins used by oscillators, test mode, reset, flash erase and jtag to name but a few. 6.3 serial wire jtag debug port (swj-dp) the swj-dp pins are tck/swclk, tms/sw dio, tdo/swo, tdi and commonly provided on a standard 20-pin jtag connector defined by arm. for more details about voltage reference and reset state, refer to table 3-1, ?signal description list? pcb tr a ce z0 ~ 50 ohm s receiver s am 3 driver with rodt zo u t ~ 10 ohm s z0 ~ zo u t + rodt odt 3 6 ohm s ty p.
25 6430fs?atarm?10-feb-12 sam3u series the jtagsel pin is used to select the jtag boundary scan when asserted at a high level. it integrates a permanent pull-down resistor of about 15 k to gndbu, so that it can be left uncon- nected for normal operations. by default, the jtag debug port is active. if the debugger host wants to switch to the serial wire debug port, it must provide a dedicated jtag sequence on tms/swdio and tck/swclk which disables the jtag-dp and enables the sw-dp. when the serial wire debug port is active, tdo/traceswo can be used for trace. the asynchronous trace output (traceswo) is multiplexed with tdo. so the asynchronous trace can only be used with sw-dp, not jtag-dp. all the jtag signals are supplied with vddio except jtagsel, supplied by vddbu. 6.4 test pin the tst pin is used for jtag boundary scan ma nufacturing test or fast flash programming mode of the sam3u series. the tst pin integrates a permanent pull-down resistor of about 15 k to gnd, so that it can be left unconnected for normal operations. to enter fast programming mode, see the ?fast flash programming interface? section of the product datasheet. for more on the manufacturing and test mode, refer to the ?debug and test? section of the product datasheet. 6.5 nrst pin the nrst pin is bidirectional. it is handled by the on-chip reset controller and can be driven low to provide a reset signal to the external components or asserted low externally to reset the microcontroller. it will reset the core and the peripherals, except the backup region (rtc, rtt and supply controller). there is no constraint on the length of the reset pulse and the reset con- troller can guarantee a minimum pulse length. the nrst pin integrates a permanent pull-up resistor to vddio of about 100 k . 6.6 nrstb pin the nrstb pin is input only and enables asynchronous reset of the sam3u when asserted low. the nrstb pin integrates a permanent pull-up resistor of about 15 k . this allows connection of a simple push button on the nrstb pin as a system-user reset. in all modes, this pin will reset the chip including the backup region (rtc, rtt and supply controller). it reacts as the power-on reset. it can be used as an external system reset source. in harsh environments, it is recommended to add an external capacitor (10 nf) between nrstb and vddbu. (for filtering values refer to ?i/o characteristics? in the ?e lectrical characteristics? section of the product datasheet.) it embeds an anti-glitch filter. 6.7 erase pin the erase pin is used to reinitialize the flash content and some of its nvm bits. it integrates a permanent pull-down resistor of about 15 k to gnd, so that it can be left unconnected for nor- mal operations. this pin is debounced by sclk to improve the glitch tolerance. when the erase pin is tied high during less than 100 ms, it is not taken into account. the pin must be tied high during more than 220 ms to perform the reinitialization of the flash.
26 6430fs?atarm?10-feb-12 sam3u series even in all low power modes, asse rting the pin will automatically st art-up the chip and erase the flash. 7. processor and architecture 7.1 arm cortex-m3 processor ? version 2.0 ? thumb-2 (isa) subset consisting of all base thumb-2 instructions, 16-bit and 32-bit. ? harvard processor architecture enabling simultaneous instruction fetch with data load/store. ? three-stage pipeline. ? single cycle 32-bit multiply. ? hardware divide. ? thumb and debug states. ? handler and thread modes. ? low latency isr entry and exit. 7.2 apb/ahb bridges the sam3u product embeds tw o separated apb/ahb bridges: ? low speed bridge ? high speed bridge this architecture enables to make concurrent accesses on both bridges. all the peripherals are on the low-speed bridge except spi, ssc and hsmci. the uart, 10-bit adc (adc), 12-bit adc (adc12b) , twi0-1, usart0-3, pwm have dedicated channels for the peripheral dma channels (pdc). these peripherals can not use the dma controller. the high speed bridge regroups the ssc, spi and hsmci. these three peripherals do not have pdc channels but can use the dma with the internal fifo for channel buffering. note that the peripherals of the two bridges are clocked by the same source: mck. 7.3 matrix masters the bus matrix of the sam3u device manages 5 masters, which means th at each master can perform an access concurrently with others to an available slave. each master has its own decoder and specifically defined bus. in order to simplify the address- ing, all the masters have the same decoding. table 7-1. list of bus matrix masters master 0 cortex-m3 instruction/data master 1 cortex-m3 system master 2 peripheral dma controller (pdc) master 3 usb device high speed dma master 4 dma controller
27 6430fs?atarm?10-feb-12 sam3u series 7.4 matrix slaves the bus matrix of the sam3u manages 10 slaves. each slave has its own arbiter, allowing a dif- ferent arbitration per slave. 7.5 master to slave access all the masters can normally access all the slaves. however, some paths do not make sense, for example allowing access from the usb device high speed dma to the internal peripherals. thus, these paths are forbidden or simply not wired, and shown as ??? in table 7-3 below. table 7-2. list of bus matrix slaves slave 0 internal sram0 slave 1 internal sram1 slave 2 internal rom slave 3 internal flash 0 slave 4 internal flash 1 slave 5 usb device high speed dual port ram (dpr) slave 6 nand flash controller ram slave 7 external bus interface slave 8 low speed peripheral bridge slave 9 high speed peripheral bridge table 7-3. sam3u master to slave access slaves masters 0 1 234 cortex-m3 i/d bus cortex-m3 s bus pdc usb device high speed dma dma controller 0 internal sram0 ?xxxx 1 internal sram1 ?xxxx 2 internal rom x ? x x x 3 internal flash 0 x???? 4 internal flash 1 x???? 5 usb device high speed dual port ram (dpr) ? x ? ? ? 6 nand flash controller ram ?xxxx 7 external bus interface ?xxxx 8 low speed peripheral bridge ? x x ? ? 9 high speed peripheral bridge ? x x ? ?
28 6430fs?atarm?10-feb-12 sam3u series 7.6 dma controller ? acting as one matrix master ? embeds 4 channels: ? 3 channels with 8 bytes/fifo for channel buffering ? 1 channel with 32 bytes/fifo for channel buffering ? linked list support with status write back operation at end of transfer ? word, halfword, byte transfer support. ? handles high speed transfer of spi, ssc and hsmci (peripheral to memory, memory to peripheral) ? memory to memory transfer ? can be triggered by pwm and t/c which enables to generate waveforms though the external bus interface the dma controller can handle the transfer between peripherals and memory and so receives the triggers from the peripherals listed below. the hardware interface numbers are also given in table 7-4 below. 7.7 peripheral dma controller ? handles data transfer between peripherals and memories ? nineteen channels ? two for each usart ? two for the uart ? two for each two wire interface ? one for the pwm ? one for each analog-to-digital converter ? low bus arbitration overhead ? one master clock cycle needed for a transfer from memory to peripheral ? two master clock cycles needed for a transfer from peripheral to memory ? next pointer management for reducing interrupt latency requirement table 7-4. dma controller instance name channel t/r dma channel hw interface number hsmci transmit/receive 0 spi transmit 1 spi receive 2 ssc transmit 3 ssc receive 4 pwm event line 0 trigger 5 pwm event line 1 trigger 6 tio output of timer counter channel 0 trigger 7
29 6430fs?atarm?10-feb-12 sam3u series the peripheral dma controller handles transfer requests from the channel according to the fol- lowing priorities (low to high priorities): 7.8 debug and test features ? debug access to all memory and registers in the system, including cortex-m3 register bank when the core is running, halted, or held in reset. ? serial wire debug port (sw-dp) and serial wire jtag debug port (swj-dp) debug access ? flash patch and breakpoint (fpb) unit for implementing break points and code patches ? data watchpoint and trace (dwt) unit for implementing watch points, data tracing, and system profiling ? instrumentation trace macrocell (itm) for support of printf style debugging ?ieee ? 1149.1 jtag boundary-scan on all digital pins table 7-5. peripheral dma controller instance name channel t/r twi1 transmit twi0 transmit pwm transmit uart transmit usart3 transmit usart2 transmit usart1 transmit usart0 transmit twi0 receive twi1 receive uart receive usart3 receive usart2 receive usart1 receive usart0 receive adc receive adc12b receive
30 6430fs?atarm?10-feb-12 sam3u series 8. product mapping figure 8-1. sam3u memory mapping addre ss memory s p a ce code 0x00000000 intern a l s ram 0x20000000 peripher a l s 0x40000000 extern a l s ram 0x60000000 re s erved 0xa0000000 s y s tem 0xe0000000 0xffffffff code 1 mbyte b it ba nd region 1 mbyte b it ba nd region boot memory 0x00000000 intern a l fl as h 0 0x00080000 intern a l fl as h 1 0x00100000 intern a l rom 0x00180000 re s erved 0x00200000 0x1fffffff intern a l s ram s ram0 0x20000000 s ram1 0x20080000 nfc ( s ram) 0x20100000 udph s (dma) 3 2 mbyte s b it ba nd a li as undefined 0x20180000 0x20200000 0x22000000 0x24000000 0x24000000 0x40000000 extern a l s ram chip s elect 0 0x60000000 chip s elect 1 0x61000000 chip s elect 2 0x62000000 chip s elect 3 0x63000000 re s erved 0x64000000 nfc 0x68000000 re s erved 0x69000000 0x9fffffff s y s tem controller s mc 0x400e0000 matrix 0x400e0200 pmc 5 0x400e0400 uart 8 0x400e0600 chipid 0x400e0740 efc0 6 0x400e0800 efc1 7 0x400e0a00 pioa 10 0x400e0c00 piob 11 0x400e0e00 pioc 12 0x400e1000 r s tc 0x400e1200 1 s upc +0x10 rtt +0x30 3 wdt +0x50 4 rtc +0x60 2 sysc gpbr +0x90 re s erved 0x400e1400 0x4007ffff offset id peripher a l block peripher a l s mci 17 0x40000000 ss c 21 0x40004000 s pi 20 0x40008000 re s erved 0x4000c000 tc0 tc0 0x40080000 22 tc0 tc1 +0x40 23 tc0 tc2 +0x80 24 twi0 18 0x40084000 twi1 19 0x40088000 pwm 25 0x4008c000 u s art0 13 0x40090000 u s art1 14 0x40094000 u s art2 15 0x40098000 u s art 3 16 0x4009c000 re s erved 0x400a0000 udph s 29 0x400a4000 adc12b 26 0x400a8000 adc 27 0x400ac000 dmac 28 0x400b0000 re s erved 0x400b3fff s y s tem controller 0x400e0000 0x400e2600 0x40100000 0x42000000 0x44000000 0x60000000 undefined re s erved re s erved re s erved 3 2 mbyte s b it ba nd a li as
31 6430fs?atarm?10-feb-12 sam3u series 9. memories the embedded and external memories are described below. 9.1 embedded memories 9.1.1 internal sram the sam3u4 (256 kbytes internal flash version) embeds a total of 48 kbytes high-speed sram (32 kbytes sram0 and 16 kbytes sram1). the sam3u2 (128 kbytes internal flash version) embeds a total of 32 kbytes high-speed sram (16 kbytes sram0 and 16 kbytes sram1). the sam3u1 (64 kbytes internal flash version) embeds a total of 16 kbytes high-speed sram (8 kbytes sram0 and 8 kbytes sram1). the sram0 is accessible over system co rtex-m3 bus at address 0x2000 0000 and sram1 at address 0x2008 0000. the user can see the sr am as contiguous at 0x20078000-0x20083fff (sam3u4), 0x2007c000-0x20083ffff (sam3u2) or 0x2007e000-0x20081ffff (sam3u1). the sram0 and sram1 are in the bit band region. the bit band alias region is from 0x2200 0000 and 0x23ff ffff. the nand flash controller embeds 4224 bytes of internal sram. if the nand flash controller is not used, these 4224 bytes of sram can be used as general purpose. it can be seen at address 0x2010 0000. 9.1.2 internal rom the sam3u product embeds an internal rom, which contains the sam-ba boot and ffpi program. at any time, the rom is mapped at address 0x0018 0000. 9.1.3 embedded flash 9.1.3.1 flash overview the flash of the sam3u4 (256 kbytes internal flash version) is organized in two banks of 512 pages (dual plane) of 256 bytes. the flash of the sam3u2 (128 kbytes internal flash version) is organized in one bank of 512 pages (single plane) of 256 bytes. the flash of the is sam3u1 (64kbytes inter nal flash version) organized in one bank of 256 pages (single plane) of 256 bytes. the flash contains a 128-byte write buffer, accessible through a 32-bit interface. 9.1.3.2 flash power supply the flash is supplied by vddcore. 9.1.3.3 enhanced embedded flash controller the enhanced embedded flash controller (eef c) manages accesses performed by the mas- ters of the system. it enab les reading the flash and writing t he write buffer. it also contains a user interface, mapped within the memory controller on the apb.
32 6430fs?atarm?10-feb-12 sam3u series the enhanced embedded flash controller ensures the interface of the flash block with the 32- bit internal bus. its 128-bit wide memory interface increases performance. the user can choose between high performance or lower current consumption by selecting either 128-bit or 64-bit access. it also manages the programming, erasing, locking and unlocking sequences of the flash using a full set of commands. one of the commands returns the embedded flash descriptor definition that informs the system about the flash organization, thus making the software generic. the sam3u4 (256 kbytes internal flash vers ion) embeds two eefc (eefc0 for flash0 and eefc1 for flash1) whereas the sam3u2/1 embeds one eefc. 9.1.3.4 lock regions in the sam3u4 (256 kbytes internal flash version) two enhanced embedded flash controllers each manage 16 lock bits to protect 32 regions of the flash against inadvertent flash erasing or programming commands. the sam3u4 (256 kbytes internal flash version) cont ains 32 lock regions and each lock region contains 32 pages of 256 bytes. each lock region has a size of 8 kbytes. the sam3u2 (128 kbytes internal flash version) enhanced embedded flash controller man- ages 16 lock bits to protect 32 regions of the flash against inadvertent flash erasing or programming commands. the sam3u2 (128 kbytes internal flash version) cont ains 16 lock regions and each lock region contains 32 pages of 256 bytes. each lock region has a size of 8 kbytes. the sam3u1 (64 kbytes internal flash version) embed ded flash controller manages 8 lock bits to protect 8 regions of the flash against inadv ertent flash erasing or programming commands. the sam3u1 (64 kbytes internal flash version) contains 8 lock regions and each lock region contains 32 pages of 256 bytes. each lock region has a size of 8 kbytes. if a locked-region?s erase or program command occurs, the command is aborted and the eefc triggers an interrupt. the lock bits are software programmable through the eefc user interface. the command ?set lock bit? enables the protection. the command ?clear lock bit? unlocks the lock region. asserting the erase pin clears the lock bits, thus unlocking the entire flash. 9.1.3.5 security bit feature the sam3u features a security bit, based on a specific general purpose nvm bit (gpnvm bit 0). when the security is enabled, any access to the flash, sram, core registers and internal peripherals either through the ice interface or through the fast flash programming interface, is forbidden. this ensures the confidentiality of the code programmed in the flash. this security bit can only be enabled, through the command ?set general purpose nvm bit 0? of the eefc user interface. disabling the security bit can only be achieved by asserting the erase pin at 1, and after a full flash erase is performed. when the security bit is deactivated, all accesses to the flash, sram, core registers and internal peripherals either through the ice interface or through the fast flash programming interface are permitted. it is important to note that th e assertion of the erase pin should always be longer than 200 ms. as the erase pin integrates a permanent pull-down , it can be left uncon nected during normal
33 6430fs?atarm?10-feb-12 sam3u series operation. however, it is safer to connect it directly to gnd fo r the final application. 9.1.3.6 calibration bits nvm bits are used to calibrate the brownout detector and the voltage regulator. these bits are factory configured and cannot be changed by the user. the erase pin has no effect on the cal- ibration bits. 9.1.3.7 unique identifier each device integrates its own 128-bit unique ident ifier. these bits are factory configured and cannot be changed by the user. the erase pin has no e ffect on the unique identifier. 9.1.3.8 fast flash programming interface the fast flash programming interface allows programming the device through either a serial jtag interface or through a multiplexed fully-handshaked parallel port. it allows gang program- ming with market-standard industrial programmers. the ffpi supports read, page program, page erase, full erase, lock, unlock and protect commands. the fast flash programming interface is enab led and the fast programming mode is entered when tst, nrstb and fwup pins are tied high during power up sequence and if all supplies are provided externally (do not use internal regulator for vddcore). please note that since the ffpi is a part of the sam-ba boot application, the device must boot from the rom. 9.1.3.9 sam-ba ? boot the sam-ba boot is a default boot program which provides an easy way to program in-situ the on-chip flash memory. the sam-ba boot assistant supports serial communication via the uart and usb. the sam-ba boot provides an interface with sam-ba graphic user interface (gui). the sam-ba boot is in rom and is mapped in fl ash at address 0x0 when gpnvm bit 1 is set to 0. 9.1.3.10 gpnvm bits the sam3u features three gpnvm bits that can be cleared or set respectively through the com- mands ?clear gpnvm bit? and ?set gpnv m bit? of the eefc user interface. the sam3u4 is equipped with two eefc, eefc 0 and eefc1. eefc1 does not feature the gpnvm bits. the gpnvm embedded on eefc0 applies to the two blocks in the sam3u4. table 9-1. general-purpose non-volatile memory bits gpnvmbit[#] function 0 security bit 1 boot mode selection 2 flash selection (flash 0 or flash 1) only on sam3u4 (256 kbytes internal flash version)
34 6430fs?atarm?10-feb-12 sam3u series 9.1.4 boot strategies the system always boots at address 0x0. to ens ure a maximum boot possibilities the memory layout can be changed via gpnvm. a general purpose nvm (gpnvm1) bit is used to boot either on the rom (default) or from the flash. the gpnvm bit can be cleared or set respectively through the commands ?clear general-pur- pose nvm bit? and ?set general-purpose nvm bit? of the eefc user interface. setting the gpnvm bit 1 selects the boot from the flash, clearing it selects the boot from the rom. asserting erase clears the gpnvm bit 1 and thus selects the boot from the rom by default. gpnvm2 enables to select if flash 0 or flash 1 is used for the boot. setting the gpnvm2 bit selects the boot from flash 1, clearing it selects the boot from flash 0. 9.2 external memories the sam3u offers an interface to a wide range of external memories and to any parallel peripheral. 9.2.1 static memory controller ? 8- or 16- bit data bus ? up to 24-bit address bus (up to 16 mbytes linear per chip select) ? up to 4 chips selects, configurable assignment ? multiple access modes supported ? byte write or byte select lines ? multiple device adaptability ? control signals programmable setup, pulse and hold time for each memory bank ? multiple wait state management ? programmable wait state generation ? external wait request ? programmable data float time ? slow clock mode supported 9.2.2 nand flash controller ? handles automatic read/write transfer through 4224 bytes sram buffer ? dma support ? supports slc nand flash technology ? programmable timing on a per chip select basis ? programmable flash data width 8-bit or 16-bit 9.2.3 nand flash error corrected code controller ? integrated in the nand flash controller ? single bit error correction and 2-bit random detection. ? automatic hamming code calculation while writing ? ecc value available in a register ? automatic hamming code calculation while reading
35 6430fs?atarm?10-feb-12 sam3u series ? error report, including error flag, correctable error flag and word address being detected erroneous ? supports 8- or 16-bit nand flash devices with 512-, 1024-, 2048- or 4096-byte pages 10. system controller the system controller is a set of peripherals, which allow handling of key elements of the system, such as power, resets, clocks, time, interrupts, watchdog, etc... the system controller user interface also embeds the registers used to configure the matrix. see the system controller block diagram in figure 10-1 on page 36 .
36 6430fs?atarm?10-feb-12 sam3u series figure 10-1. system controller block diagram s oftw a re controlled volt a ge reg u l a tor adc (front-end) m a trix s ram w a tchdog timer fl as h peripher a l s peripher a l bridge zero-power power-on re s et su pply monitor rtc power m a n a gement controller em b edded 3 2 khz rc o s cill a tor xt a l 3 2 khz o s cill a tor su pply controller em b edded 12 / 8 / 4 mhz rc o s cill a tor browno u t detector gener a l p u rpo s e b a ck u p regi s ter s cortex-m 3 re s et controller b a ck u p power su pply core power su pply plla vr_ s t a nd b y rtc_ a l a rm s lck proc_nre s et periph_nre s et ice_nre s et m as ter clock mck s lck vddcore_nre s et m a in clock mainck s lck nr s t mainck pllack f s tt0 - f s tt15 (1) xin 3 2 xout 3 2 o s c 3 2k_xt a l_en xtal s el s low clock s lck o s c 3 2k_rc_en vddcore_nre s et vddio vddcore vddout advref adx fwup b odcore_on b odcore_in rtt rtt_ a l a rm s lck xin xout vddbu vddin s hdn piox vddana u s b vddutmi u s bx b od bu p_on b od bu p_in su pc_interr u pt 3 - 20 mhz xtal o s cill a tor wkup0 - wkup15 nr s tb pioa/b/c inp u t / o u tp u t b u ffer s f s tt0 - f s tt15 a re po ss i b le f as t s t a rt u p s o u rce s , gener a ted b y wkup0-wkup15 pin s , bu t a re not phy s ic a l pin s . upll mainck upllck
37 6430fs?atarm?10-feb-12 sam3u series 10.1 system controller and peripheral mapping please refer to figure 8-1?sam3u memory mapping? on page 30 . all the peripherals are in the bit band region and are mapped in the bit band alias region. 10.2 power-on-reset, brownout and supply monitor the sam3u embeds three features to monitor, warn and/or reset the chip: ? power-on-reset on vddbu ? brownout detector on vddcore ? supply monitor on vddutmi 10.2.1 power-on-reset on vddbu the power-on-reset monitors vddbu. it is always activated and monitors voltage at start up but also during power down. if vddbu goes below the threshold voltage, the entire chip is reset. for more information, refer to the ?electrica l characteristics? section of the datasheet. 10.2.2 brownout detector on vddcore the brownout detector monitors v ddcore. it is active by default. it can be deactivated by soft- ware through the supply controller (supc_mr). it is especially recommended to disable it during low-power modes such as wait or sleep modes. if vddcore goes below the thresh old voltage, the reset of the co re is asserted. for more infor- mation, refer to the ?supply controller? and ?elect rical characteristics? sections of the product datasheet. 10.2.3 supply monitor on vddutmi the supply monitor monitors vddutmi. it is not active by default. it can be activated by soft- ware and is fully programmable with 16 steps fo r the threshold (between 1.9v to 3.4v). it is controlled by the supply controller. a sample mode is possible. it allows to divide the supply monitor power consumption by a factor of up to 2048. for more information, refer to the ?supply controller? and ?electrical characteristics? sections of the product datasheet. 10.3 reset controller the reset controller is capable to return to the software the source of the last reset, either a general reset, a wake-up reset, a software reset, a user reset or a watchdog reset. the reset controller controls the internal resets of the system and the nrst pin output. it is capable to shape a reset signal for the external devices, simplifying to a minimum connection of a push-button on the nrst pin to implement a manual reset. 10.4 supply controller the supply controller controls the power suppl ies of each section of the processor and the peripherals (via voltage regulator control). the supply controller has its own reset circuitr y and is clocked by the 32 khz slow clock generator. the reset circuitry is based on a zero-power power-on reset cell. the zero-power power-on reset allows the supply controller to start properly.
38 6430fs?atarm?10-feb-12 sam3u series the slow clock generator is based on a 32 kh z crystal oscillator and an embedded 32 khz rc oscillator. the slow clock defaul ts to the rc oscillator, but th e software can enable the crystal oscillator and select it as the slow clock source. the supply controller starts up the device by enabling the voltage regulator, then it generates the proper reset signals to the core power supply. it also enables to set the system in different low power modes and to wake it up from a wide range of events. 10.5 clock generator the clock generator is made up of: ? one low power 32768 hz slow clock oscillator with bypass mode ? one low power rc oscillator ? one 3 to 20 mhz crystal osc illator, which can be bypassed ? one fast rc oscillator factory programmed, 3 ou tput frequencies can be selected: 4, 8 or 12 mhz. by default 4 mhz is selected. 8 mhz and 12 mhz output are factory calibrated. ? one 480 mhz upll providing a clock for the usb high speed device controller. input frequency is 12 mhz (only). ? one 96 to 192 mhz programmable pll (pll a), capable to provide the clock mck to the processor and to the peripherals. the input frequency of the pll a is between 8 and 16 mhz. figure 10-2. clock generator block diagram power management controller xin xout main clock mainck upll clock upllck control status pll and divider a plla clock pllack 12m main oscillator pll b on chip 32k rc osc slow clock slck xin32 xout32 slow clock oscillator clock generator xtalsel hsck divider /6 /8 on chip 12/8/4 mhz rc osc mainsel
39 6430fs?atarm?10-feb-12 sam3u series 10.6 power management controller the power management controller provides all the clock signals to the system. it provides: ? the processor clock hclk ? the free running processor clock fclk ? the cortex systick external clock ? the master clock mck, in particular to the matrix and the memory interfaces ? the usb device hs clock udpck ? independent peripheral clocks, typically at the frequency of mck ? three programmable clock outputs: pck0, pck1 and pck2 the supply controller selects between the 32 khz rc oscillator or the crystal oscillator. the unused oscillator is disabled automatically so that powe r consumption is optimized. by default, at startup the chip runs out of th e master clock using the fast rc oscillator running at 4 mhz. figure 10-3. power management controller block diagram the systick calibration value is fixed at 10500, which allows the generation of a time base of 1 ms with systtick clock to 10.5 mhz (max hclk/8). mck periph_clk[..] int s lck mainck pllack pre s c a ler /1,/2,/4,...,/64 hck proce ss or clock controller s leep mode m as ter clock controller peripher a l s clock controller on/off u s b clock controller s lck mainck pllack pre s c a ler /1,/2,/4,...,/64 progr a mm ab le clock controller h s ck pck[..] pllbck pllbck udpck on/off on/off fclk s y s ttick divider / 8
40 6430fs?atarm?10-feb-12 sam3u series 10.7 watchdog timer ? 16-bit key-protected once-only programmable counter ? windowed, prevents the processor to be in a dead-lock on the watchdog access 10.8 systick timer ? 24-bit down counter ? self-reload capability ? flexible system timer 10.9 real-time timer ? real-time timer, allowing backup of time with different accuracies ? 32-bit free-running back-up counter ? integrates a 16-bit programmable prescaler running on slow clock ? alarm register capable to generate a wake-up of the system 10.10 real-time clock ? low power consumption ? full asynchronous design ? two hundred year calendar ? programmable periodic interrupt ? alarm and update parallel load ? control of alarm and update time/calendar data in 10.11 general-purpose back-up registers ? eight 32-bit general-purpose backup registers 10.12 nested vectored interrupt controller ? thirty maskable interrupts ? sixteen priority levels ? dynamic reprioritization of interrupts ? priority grouping ? selection of preempting interrupt levels and non preempting interrupt levels. ? support for tail-chaining and late arrival of interrupts. ? back-to-back interrupt processing without the overhead of state saving and restoration between interrupts. ? processor state automatically saved on interrupt entry, and restored on ? interrupt exit, with no instruction overhead.
41 6430fs?atarm?10-feb-12 sam3u series 10.13 chip identification ? chip identifier (chipid) registers permit recognition of the device and its revision. ? jtag id: 0x0582a03f ? jtag id: 0x0582a03f 10.14 pio controllers ? 3 pio controllers, pioa, piob, and pioc, controlling a maximum of 96 i/o lines ? each pio controller controls up to 32 programmable i/o lines ? pioa has 32 i/o lines ? piob has 32 i/o lines ? pioc has 32 i/o lines ? fully programmable through set/clear registers ? multiplexing of two peripheral functions per i/o line ? for each i/o line (whether assigned to a peripheral or used as general purpose i/o) ? input change, rising edge, falling ed ge, low level and level interrupt ? debouncing and glitch filter ? multi-drive option enables driving in open drain ? programmable pull up on each i/o line ? pin data status register, supplies visib ility of the level on the pin at any time ? synchronous output, provides set and clear of several i/o lines in a single write table 10-1. sam3u chip ids register - engineering samples chip name flash size kbyte pin count chipid_cidr chipid_exid sam3u4c 256 100 0x28000960 0x0 sam3u2c 128 100 0x280a0760 0x0 sam3u1c 64 100 0x28090560 0x0 sam3u4e 256 144 0x28100960 0x0 sam3u2e 128 144 0x281a0760 0x0 sam3u1e 64 144 0x28190560 0x0 table 10-2. sam3u chip ids register - revision a parts chip name flash size kbyte pin count chipid_cidr chipid_exid sam3u4c (rev a) 256 100 0x28000961 0x0 sam3u2c (rev a) 128 100 0x280a0761 0x0 sam3u1c (rev a) 64 100 0x28090561 0x0 sam3u4e (rev a) 256 144 0x28100961 0x0 sam3u2e (rev a) 128 144 0x281a0761 0x0 sam3u1e (rev a) 64 144 0x28190561 0x0
42 6430fs?atarm?10-feb-12 sam3u series 11. peripherals 11.1 peripheral identifiers table 11-1 defines the peripheral identifiers of the sam3u. a peripheral identifier is required for the control of the peripheral interrupt with the nested vectored interrupt controller and for the control of the peripheral clock with the power management controller. note that some peripherals are always clocked. please refer to the table below. table 11-1. peripheral identifiers instance id instance name nvic interrupt pmc clock control instance description 0supcx supply controller 1rstcx reset controller 2rtcx real time clock 3rttx real time timer 4wdtx watchdog timer 5pmcx power management controller 6 eefc0 x enhanced embedded flash controller 0 7 eefc1 x enhanced embedded flash controller 1 8uartx x universal asynchronous receiver transmitter 9smcx x static memory controller 10 pioa x x parallel i/o controller a, 11 piob x x parallel i/o controller b 12 pioc x x parallel i/o controller c 13 usart0 x x usart 0 14 usart1 x x usart 1 15 usart2 x x usart 2 16 usart3 x x usart 3 17 hsmci x x high speed multimedia card interface 18 twi0 x x two-wire interface 0 19 twi1 x x two-wire interface 1 20 spi x x serial peripheral interface 21 ssc x x synchronous serial controller 22 tc0 x x timer counter 0 23 tc1 x x timer counter 1 24 tc2 x x timer counter 2 25 pwm x x pulse width modulation controller 26 adc12b x x 12-bit adc controller 27 adc x x 10-bit adc controller 28 dmac x x dma controller 29 udphs x x usb device high speed
43 6430fs?atarm?10-feb-12 sam3u series 11.2 peripheral signal mult iplexing on i/o lines the sam3u features 3 pio controllers, pioa, piob and pioc that multiplex the i/o lines of the peripheral set. each pio controller controls up to 32 lines. each line can be assigned to one of two peripheral functions, a or b. the multiplexing tables in the following pages define how the i/o lines of peripherals a and b are multiplexed on the pio controllers. the two columns ?extra function? and ?comments? have been inserted in this table for the user?s own comments, they may be used to track how pins are defined in an application. note that some peripheral functions which are ou tput only, might be duplicated within the tables.
44 6430fs?atarm?10-feb-12 sam3u series 11.2.1 pio controller a multiplexing notes: 1. wake-up source in backup mode (managed by the supc). 2. fast start-up source in wait mode (managed by the pmc). 3. only on 144-pin version. table 11-2. multiplexing on pi o controller a (pioa) i/o line peripheral a periphe ral b extra function comments pa0 tiob0 npcs1 wkup0 (1)(2) pa1 tioa0 npcs2 wkup1 (1)(2) pa2 tclk0 adtrg wkup2 (1)(2) pa3 mcck pck1 pa4 mccda pwmh0 pa5 mcda0 pwmh1 pa 6 m c da 1 pwmh2 pa7 mcda2 pwml0 pa8 mcda3 pwml1 pa9 twd0 pwml2 wkup3 (1)(2) pa 1 0 t w c k 0 p w m l 3 w k u p 4 (1)(2) pa11 urxd pwmfi0 pa 1 2 u t x d p w m f i 1 pa 1 3 m i s o pa 1 4 m o s i pa15 spck pwmh2 pa16 npcs0 ncs1 wkup5 (1)(2) pa17 sck0 ad12btrg wkup6 (1)(2) pa 1 8 t x d 0 p w m f i 2 w k u p 7 (1)(2) pa19 rxd0 npcs3 wkup8 (1)(2) pa20 txd1 pwmh3 wkup9 (1)(2) pa21 rxd1 pck0 wkup10 (1)(2) pa22 txd2 rts1 ad12b0 pa23 rxd2 cts1 pa 2 4 t w d 1 (3) sck1 wkup11 (1)(2) pa 2 5 t w c k 1 (3) sck2 wkup12 (1)(2) pa26 td tclk2 pa27 rd pck0 pa 2 8 tk pwmh0 pa 2 9 r k p w m h 1 pa30 tf tioa2 ad12b1 pa 3 1 r f t i o b 2
45 6430fs?atarm?10-feb-12 sam3u series 11.2.2 pio controller b multiplexing notes: 1. wake-up source in backup mode (managed by the supc). 2. fast start-up source in wait mode (managed by the pmc). table 11-3. multiplexing on pi o controller b (piob) i/o line peripheral a peripheral b extra function comments pb0 pwmh0 a2 wkup13 (1)(2) pb1 pwmh1 a3 wkup14 (1)(2) pb2 pwmh2 a4 wkup15 (1)(2) pb3 pwmh3 a5 ad12b2 pb4 tclk1 a6 ad12b3 pb5 tioa1 a7 ad0 pb6 tiob1 d15 ad1 pb7 rts0 a0/nbs0 ad2 pb8 cts0 a1 ad3 pb9 d0 dtr0 pb10 d1 dsr0 pb11 d2 dcd0 pb12 d3 ri0 pb13 d4 pwmh0 pb14 d5 pwmh1 pb15 d6 pwmh2 pb16 d7 pwmh3 pb17 nandoe pwml0 pb18 nandwe pwml1 pb19 nrd pwml2 pb20 ncs0 pwml3 pb21 a21/nandale rts2 pb22 a22/nandcle cts2 pb23 nwr0/nwe pck2 pb24 nandrdy pck1 pb25 d8 pwml0 only on 144-pin version pb26 d9 pwml1 only on 144-pin version pb27 d10 pwml2 only on 144-pin version pb28 d11 pwml3 only on 144-pin version pb29 d12 only on 144-pin version pb30 d13 only on 144-pin version pb31 d14 only on 144-pin version
46 6430fs?atarm?10-feb-12 sam3u series 11.2.3 pio controller c multiplexing notes: 1. wake-up source in backup mode (managed by the supc). 2. fast start-up source in wait mode (managed by the pmc). table 11-4. multiplexing on pi o controller c (pioc) i/o line peripheral a peripheral b extra function comments pc0 a2 only on 144-pin version pc1 a3 only on 144-pin version pc2 a4 only on 144-pin version pc3 a5 npcs1 only on 144-pin version pc4 a6 npcs2 only on 144-pin version pc5 a7 npcs3 only on 144-pin version pc6 a8 pwml0 only on 144-pin version pc7 a9 pwml1 only on 144-pin version pc8 a10 pwml2 only on 144-pin version pc9 a11 pwml3 only on 144-pin version pc10 a12 cts3 only on 144-pin version pc11 a13 rts3 only on 144-pin version pc12 ncs1 txd3 only on 144-pin version pc13 a2 rxd3 only on 144-pin version pc14 a3 npcs2 only on 144-pin version pc15 nwr1/nbs1 ad12b4 only on 144-pin version pc16 ncs2 pwml3 ad12b5 only on 144-pin version pc17 ncs3 ad12b6 only on 144-pin version pc18 nwait ad12b7 only on 144-pin version pc19 sck3 npcs1 only on 144-pin version pc20 a14 only on 144-pin version pc21 a15 only on 144-pin version pc22 a16 only on 144-pin version pc23 a17 only on 144-pin version pc24 a18 pwmh0 only on 144-pin version pc25 a19 pwmh1 only on 144-pin version pc26 a20 pwmh2 only on 144-pin version pc27 a23 pwmh3 only on 144-pin version pc28 mcda4 ad4 only on 144-pin version pc29 pwml0 mcda5 ad5 only on 144-pin version pc30 pwml1 mcda6 ad6 only on 144-pin version pc31 pwml2 mcda7 ad7 only on 144-pin version
47 6430fs?atarm?10-feb-12 sam3u series 12. embedded peripherals overview 12.1 serial peripheral interface (spi) ? supports communication with serial external devices ? four chip selects with external decoder support allow communication with up to 15 peripherals ? serial memories, such as dataflash and 3-wire eeproms ? serial peripherals, such as adcs, dacs, lcd controllers, can controllers and sensors ? external co-processors ? master or slave serial peripheral bus interface ? 8- to 16-bit programmable data length per chip select ? programmable phase and polarity per chip select ? programmable transfer delays between consecutive transfers and between clock and data per chip select ? programmable delay between consecutive transfers ? selectable mode fault detection ? very fast transfers supported ? transfers with baud rates up to mck ? the chip select line may be left active to speed up transfers on the same device 12.2 two wire interface (twi) ? master, multi-master and slave mode operation ? compatibility with atmel two-wire interface, serial memory and i 2 c compatible devices ? one, two or three bytes for slave address ? sequential read/write operations ? bit rate: up to 400 kbit/s ? general call supported in slave mode ? connecting to pdc channel capabilities optimizes data transfers in master mode only ? one channel for the receiver, one channel for the transmitter ? next buffer support 12.3 universal asynchronous r eceiver transceiver (uart) ?two-pin uart ? implemented features are 100% compatible with the standard atmel usart ? independent receiver and transmitter with a common programmable baud rate generator ? even, odd, mark or space parity generation ? parity, framing and overrun error detection ? automatic echo, local loopback and remote loopback channel modes ? support for two pdc channels with connection to receiver and transmitter
48 6430fs?atarm?10-feb-12 sam3u series 12.4 universal synchronous asynchrono us receiver transmitter (usart) ? programmable baud rate generator ? 5- to 9-bit full-duplex synchronous or asynchronous serial communications ? 1, 1.5 or 2 stop bits in asynchronous mode or 1 or 2 stop bits in synchronous mode ? parity generation and error detection ? framing error detection, overrun error detection ? msb- or lsb-first ? optional break generation and detection ? by 8 or by-16 over-sampling receiver frequency ? hardware handshaking rts-cts ? receiver time-out and transmitter timeguard ? optional multi-drop mode with address generation and detection ? optional manchester encoding ? rs485 with driver control signal ? iso7816, t = 0 or t = 1 protocols for interfacing with smart cards ? nack handling, error counter with repetition and iteration limit ? spi mode ?master or slave ? serial clock programmable phase and polarity ? spi serial clock (sck) frequency up to mck/6 ? irda modulation and demodulation ? communication at up to 115.2 kbps ? test modes ? remote loopback, local loopback, automatic echo 12.5 serial synchronous controller (ssc) ? provides serial synchronous communication links used in audio and telecom applications (with codecs in master or slave modes, i 2 s, tdm buses, magnetic card reader, ...) ? contains an independent receiver and transmitter and a common clock divider ? offers a configurable frame sync and data length ? receiver and transmitter can be programmed to start automatically or on detection of different event on the frame sync signal ? receiver and transmitter include a data signal , a clock signal and a frame synchronization signal 12.6 timer counter (tc) ? three 16-bit timer counter channels ? wide range of functions including: ? frequency measurement ? event counting ? interval measurement
49 6430fs?atarm?10-feb-12 sam3u series ? pulse generation ?delay timing ? pulse width modulation ? up/down capabilities ? quadrature decoder logic ? each channel is user-configurable and contains: ? three external clock inputs ? five internal clock inputs ? two multi-purpose input/output signals ? two global registers that act on all three tc channels 12.7 pulse width modulatio n controller (pwm) ? 4 channels, one 16-bit counter per channel ? common clock generator, providing thirteen different clocks ? a modulo n counter providing eleven clocks ? two independent linear dividers working on modulo n counter outputs ? high frequency asynchronous clocking mode ? independent channel programming ? independent enable disable commands ? independent clock selection ? independent period and duty cycle, with double buffering ? programmable selection of the output waveform polarity ? programmable center or left aligned output waveform ? independent output override for each channel ? independent complementary outputs with 12-bit dead time generator for each channel ? independent enable disable commands ? independent clock selection ? independent period and duty cycle, with double buffering ? synchronous channel mode ? synchronous channels share the same counter ? mode to update the synchronous channels registers after a programmable number of periods ? connection to one pdc channel ? offers buffer transfer without processor intervention, to update duty cycle of synchronous channels ? two independent event lines which can send up to 8 triggers on adc within a period ? four programmable fault inputs providing asynchronous protection of outputs
50 6430fs?atarm?10-feb-12 sam3u series 12.8 high speed multimedia card interface (hsmci) ? compatibility with multimedia ca rd specification version 4.3 ? compatibility with sd memory ca rd specification version 2.0 ? compatibility with sdio specification version v2.0. ? compatibility with ce-ata specification 1.1 ? cards clock rate up to master clock divided by 2 ? boot operation mode support ? high speed mode support ? embedded power management to slow down clock rate when not used ? hsmci has one slot supporting ? one multimediacard bus (up to 30 cards) or ? one sd memory card ? one sdio card ? support for stream, block and multi-block data read and write ? supports connection to dma controller ? minimizes processor interventio n for large buffer transfers ? built in fifo (32 bytes) with large memory aperture supporting incremental access ? support for ce-ata completion signal disable command 12.9 usb high speed device port (udphs) ? usb v2.0 high-speed compliant, 480 mbits per second ? embedded usb v2.0 utmi+ high-speed transceiver ? embedded 4-kbyte dual-port ram for endpoints ? embedded 6 channels dma controller ? suspend/resume logic ? up to 2 or 3 banks for isochronous and bulk endpoints ? seven endpoints, configurable by software ? maximum configuration: seven endpoints: ? endpoint 0: 64 bytes, 1 bank mode ? endpoint 1 & 2: 512 bytes, 2 banks mode, hs isochronous capable ? endpoint 3 & 4:64 bytes, 3 banks mode ? endpoint 5 & 6: 1024 bytes, 3 banks mode, hs isochronous capable
51 6430fs?atarm?10-feb-12 sam3u series 12.10 analog-to-digital converter (adc) two adcs are embedded in the product. 12.10.1 12-bit high speed adc ? 8-channel adc ? 12-bit 1 msamples/sec. cyclic pipeline adc ? integrated 8-to-1 multiplexer ? 12-bit resolution ? selectable single ended or differential input voltage ? programmable gain for maximum full scale input range ? external voltage reference for better accuracy on low voltage inputs ? individual enable and disable of each channel ? multiple trigger sources ? hardware or software trigger ? external trigger pin ? timer counter 0 to 2 outputs tioa0 to tioa2 trigger ? pwm trigger ? sleep mode and conversion sequencer ? automatic wakeup on trigger and back to sleep mode after conversions of all enabled channels 12.10.2 10-bit low power adc ? 8-channel adc ? 10-bit 384 ksamples/sec. or 8-bit 533 ksam ples/sec. successive approximation register adc ? -2/+2 lsb integral non linearity, -1/+1 lsb differential non linearity ? integrated 8-to-1 multiplexer ? external voltage reference for better accuracy on low voltage inputs ? individual enable and disable of each channel ? multiple trigger sources ? hardware or software trigger ? external trigger pin ? timer counter 0 to 2 outputs tioa0 to tioa2 trigger ? pwm trigger ? sleep mode and conversion sequencer ? automatic wakeup on trigger and back to sleep mode after conversions of all enabled channels
52 6430fs?atarm?10-feb-12 sam3u series 13. package drawings figure 13-1. 100-ball lqfp package drawing
53 6430fs?atarm?10-feb-12 sam3u series figure 13-2. 100-ball tfbga package drawing
54 6430fs?atarm?10-feb-12 sam3u series figure 13-3. 144-lead lqfp package drawing notes: 1. this drawing is for general information only; refer to jedee drawing ms-026 for additional information. 2. the top package body size may be smaller than th e bottom package size by as much as 0.15 mm. 3. dimensions d1 and e1 do not include mold protrusions. allo wable protrusion is 0.25 mm per side. d1 and e1 are maximum plastic body size dimensions including mold mismatch. 4. b dimension by more than 0.08 mm. dambar cannot be located on the lower radius or the foot. minimum space between pro- trusion and an adjacent lead is 0.07 mm for 0.4 and 0.5 mm pitch packages. 5. these dimensions apply to the flat section of the lead between 0.10 mm and 0.25 mm from the lead tip. 6. a1 is defined as the distance from the seati ng place to the lowest point on the package body.
55 6430fs?atarm?10-feb-12 sam3u series figure 13-4. 144-ball tfbga package drawing all dimensions are in mm.
56 6430fs?atarm?10-feb-12 sam3u series 14. ordering information table 14-1. atsam3u4/2/1 ordering information ordering code mrl flash (kbytes) package package type temperature operating range atsam3u4ea-au a 256 lqfp144 green industrial -40c to 85c atsam3u4ea-cu a 256 tfbga 144 green industrial -40c to 85c atsam3u4ca-au a 256 lqfp 100 green industrial -40c to 85c atsam3u4ca-cu a 256 tfbga100 green industrial -40c to 85c atsam3u2ea-au a 128 lqfp144 green industrial -40c to 85c atsam3u2ea-cu a 128 tfbga144 green industrial -40c to 85c atsam3u2ca-au a 128 lqfp100 green industrial -40c to 85c atsam3u2ca-cu a 128 tfbga100 green industrial -40c to 85c atsam3u1ea-au a 64 lqfp144 green industrial -40c to 85c atsam3u1ea-cu a 64 tfbga144 green industrial -40c to 85c atsam3u1ca-au a 64 lqfp100 green industrial -40c to 85c atsam3u1ca-cu a 64 tfbga100 green industrial -40c to 85c atsam3u1eb-au b 64 lqfp144 green industrial -40c to 85c atsam3u1eb-cu b 64 tfbga144 green industrial -40c to 85c ATSAM3U1CB-AU b 64 lqfp100 green industrial -40c to 85c atsam3u1cb-cu b 64 tfbga100 green industrial -40c to 85c
57 6430fs?atarm?10-feb-12 sam3u series revision history in the tables that follow, the most recent version of the document appears first. ?rfo? indicates changes requested during the review and approval loop. doc. rev 6430fs comments change request ref. figure 14-1, ?atsam3u4/2/1 ordering information? , updated with mrl b devices replaced all mentions of 100-ball lfbga into 100-ball tfbga section 9.1.3.1 ?flash overview? , corrected wrong flash size for sam3u1- 256kbytes replaced by 64kbytes 8130 8044 8029 doc. rev 6430es comments change request ref. comment in front of rows pa24 and pa25 removed, and put as a footnote (3) for twd1 and twck1. figure 5-5, ?fast start-up sources? , ?falling/rising edge detector? changed to ?high/low level detector? in 3 blocks. table 11-2, ?multiplexing on pio controller a (pioa)? , ?peripheral b? column, pa2 and pa17 texts exchanged. 7724 7922 7954 doc. rev 6430ds comments change request ref. table 3-1, ?signal description list? , note (4) added to tdo output. 7635 twd1 and twck1 removed from figure 2-2, ?100-pin sam3u4/2/1c block diagram? .7624 section 10.13 ?chip identification? , (rev a) was removed from table 10-1 .7642 section 5.5.2 ?wait mode? , sentence starting with ?by configuring...? --> ?this is done by configuring...? 7492 a typo fixed in section 9.1.1 ?internal sram? : 4224 kbytes --> 4224 bytes. 7305 backpage, a typo fixed: ?tehincal? --> ?technical? 7536
58 6430fs?atarm?10-feb-12 sam3u series doc. rev 6430cs comments change request ref. section 2. ?sam3u block diagram? , changed orientation of block diagrams. section 5. ?power considerations? , fixed grammar in voltage ranges. section 3. ?signal description? , usart signal dcd0 is an input rfo 6681 figure 5-1 ?single supply? , main supply range is 1.8v-3.6v. figure 5-1 , figure 5-2 , figure 5-3 , updated ?note? below figures, ?with main supply <2.0v usb and adc are not usable. 6698 section 5.5 ?low power modes? , stray references to wupx pins, renamed wkupx 6711 table 5-1, ?low power mode configuration summary? , updated footnote ?5?. 6964 table 11-2, ?multiplexing on pio controller a (pioa)? , twd1 and twck1 only available on 144-pin version. 6686 section 10.13 ?chip identification? table 10-2, ?sam3u chip ids register - revision a parts? , added to datasheet. section 12.4 ?universal synchronous asynchronous receiver transmitter (usart)? ...?sck up to mck/6? 6951 rfo 7097 doc rev 6430bs comments change request ref. introduction: section 1. ?sam3u description? , updated: 52 kbytes of sram. 4x us arts (sam3u1c/2c/4c have 3), up to 2x twis (sam3u1c/2c/4c have 1), up to 5x spis sam3u1c/2c/4c have 4), table 1-1, ?config uration summary? ,ebi column updated, 8 bits for sam3u1c/2c/4c sam3u4/3/2c rows fwup replaces no in fwup,shdn pins column 6400 6642 figure 2-1 ?144-pin sam3u4/2/1e block diagram? and figure 2-2 ?100-pin sam3u4/2/1c block diagram? updated, sm cell removed; uart moved to peripheral area, added flash unique block, removed 12b from adc block, added systick counter and fmax 96 mhz to m3 block. fwup replaces wkup in fig 2-1, fwup added to fig 2-2 figure 2-2 ?100-pin sam3u4/2/1c block diagram? , nwr1/nbs1, nxrp0, a0 removed from block diagram. 6482/6642 rfo table 3-1, ?signal description list? , schmitt trigger added ?pio controller - pi oa - piob - pioc? . exception details given in footnote. vddin, vddout added to table. ?serial wire/jtag debug port (swj-dp)? replaced ice and jtag. this section of the table updated status of pulldowns and pullups specified. 6480 rfo section 4. ?package and pinout? , reorganized according to product. section 4.1 ?sam3u4/2/1e package and pinout? and section 4.2 ?sam3u4/2/1c package and pinout? , pinouts finalized in datasheet. 6471/rfo 6607 section 5.5.1 ?backup mode? , bod replaced by supply monitor/sm. fwup falling edge detector. figure 5-4 ?wake-up source? , boden replaced by smen. table 5-1, ?low power mode configuration summary? , pio state in low power modes, backup mode is; ?previous state saved. rfo 6645
59 6430fs?atarm?10-feb-12 sam3u series section 6.6 ?nrstb pin? , vddio changed to vddbu section 6. ?input/output lines? , replaces section 5.8 ?programmable i/o lines?. section 6.1 ?general purpose i/o lines (gpio)? and section 6.2 ?system i/o lines? , replace section 6. ?i/o line considerations?. figure 6-1 ?on-die termination schematic? , added. section 6.8 ?pio controllers?, removed. section 8. ?product mapping? , title changed from ?memories?. section 9. ?memories? , now comprises section 9.1 ?embedded memories? and section 9.2 ?external memories? . section 9.1.3.5 ?security bit feature? , updated 6646 6481/rfo table 7-3, ?sam3u master to slave access? , slave 9, high speed peripheral bridge line added. section 7.2 ? apb/ahb bridges? , reference to adc updated ?10-bit adc, 12-bit adc (adc12b)?. table 11-3, ?multiplexing on pio controller b (piob)? , adc12b2, adc12b3 properly listed. section 12.10.1 ?12-bit high speed adc? , section 12.10.2 ?10-bit low power adc? , titles changed. ?quadrature decoder logic? on page 49 , properly stated in list of tc functions. 6663 6397 section 12.10.1 ?12-bit high speed adc? , 2nd item on list updated. section 12.10.2 ?10-bit low power adc? , ksample values updated on 2nd item of list. rfo doc rev 6430bs comments (continued) change request ref. doc. rev comments change request ref. 6430as first issue
headquarters international atmel corporation 2325 orchard parkway san jose, ca 95131 usa tel: (+1) (408) 441-0311 fax: (+1) (408) 487-2600 atmel asia limited unit 01-5 & 16, 19f bea tower, millennium city 5 418 kwun tong road kwun tong, kowloon hong kong tel: (+852) 2245-6100 fax: (+852) 2722-1369 atmel munich gmbh business campus parkring 4 d-85748 garching b. munich germany tel: (+49) 89-31970-0 fax: (+49) 89-3194621 atmel japan 9f, tonetsu shinkawa bldg. 1-24-8 shinkawa chuo-ku, tokyo 104-0033 japan tel: (81) 3-3523-3551 fax: (81) 3-3523-7581 product contact web site www.atmel.com www.atmel.com/at91sam technical support at91sam support atmel technical support sales contacts www.atmel.com/contacts/ literature requests www.atmel.com/literature disclaimer: the information in this document is prov ided in connection with atmel products. no li cense, express or implied, by estoppel or otherwise, to any intellectual property right is granted by this document or in connection with the sale of atmel products. except as set forth in atmel?s terms and condi- tions of sale located on atmel?s web site, atmel assumes no li ability whatsoever and disclaims any express, implied or statutor y warranty relating to its products including, but not limited to, the implied warranty of merchantability, fitness for a particu lar purpose, or non-infringement. in no event shall atmel be liable for any direct, indirect, conseque ntial, punitive, special or i nciden- tal damages (including, without limi tation, damages for loss of profits, business interruption, or loss of information) arising out of the use or inability to use this document, even if at mel has been advised of the possibility of such damages. atmel makes no representations or warranties with respect to the accuracy or completeness of the cont ents of this document and reserves the rig ht to make changes to specifications and product descriptions at any time without notice. atmel does not make any commitment to update the information contained her ein. unless specifically provided otherwise, atmel products are not suitable for, and shall not be used in, automotive applications. atmel?s products are not int ended, authorized, or warranted for use as components in applications in tended to support or sustain life. ? 2011 atmel corporation . all rights reserved. atmel ? , logo and combinations thereof dataflash ? , sam-ba ? and others are registered trade- marks or trademarks of atmel corporation or its subsidiaries. arm ? , thumb ? -2 and the armpowered logo ? and others are registered trade- marks or trademarks arm ltd. windows ? and others are registered trademarks or trademarks of microsoft corporation in the us and/or other countries. other terms and product names may be trademarks of others. 6430fs?atarm?10-feb-12

▲Up To Search▲

Price & Availability of ATSAM3U1CB-AU

	To Download ATSAM3U1CB-AU Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .