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56f8300 16-bit digital signal controllers freescale.com 56f8367/56f8167 data sheet preliminary technical data mc56f8367 rev. 7.0 06/2006
56f8367 technical data, rev. 7.0 2 freescale semiconductor preliminary document revision history version history description of change rev 0 pre-release, alpha customers only rev 1.0 initial public release rev 2.0 added output voltage maximum value and note to clarify in table 10-1 .; also removed overall life expectancy note, since life ex pectancy is dependent on customer usage and must be determined by reliability engineer ing. clarified value and unit measure for maximum allowed p d in table 10-3 . corrected note about average value for flash data retention in table 10-4 . added new rohs-compliant orderable part numbers in table 13-1 . rev 3.0 added 160mapbga information, ta equation updated in table 10-4 and additional minor edits throughout data sheet rev 4.0 deleted formula for max ambient operating temperature (automotive) and max ambient operating temperature (industrial) and co rrected flash endurance to 10,000 in table 10-4 . added rohs-compliance and ?pb-free? language to back cover. rev 5.0 correcting mbga pin assignments in table 2-2 for mosi0 and miso0 rev 6.0 added information/corrected state during reset in table 2-2 . clarified external reference crystal frequency for pll in table 10-14 by increasing maximum value to 8.4mhz. rev 7.0 corrected clko and home1 labels in figure 11-2 and table 11-2 ; replaced ?tri-stated? with an explanation in state during reset column in table 2-2 . please see http://www.freescale.com for the most current data sheet revision.
56f8367 technical data, rev. 7.0 freescale semiconductor 3 preliminary 56f8367/56f8167 block diagram program controller and hardware looping unit data alu 16 x 16 + 36 -> 36-bit mac three 16-bit input registers four 36-bit accumulators address generation unit bit manipulation unit pll clock generator extal interrupt controller cop/ watchdog sci1 or gpiod 4 external address bus switch external bus interface unit 2 clkmode irqa irqb external data bus switch program memory 256k x 16 flash 2k x 16 ram boot rom 16k x 16 flash d ata memory 16k x 16 flash 16k x 16 flash pdb pdb xab1 xab2 xdb2 cdbr sci0 or gpioe spi0 or gpioe ipbus bridge (ipbb) integration module system p o r o s c decoding peripherals peripheral device selects rw control ipab ipwdb iprdb 2 system bus r/w control memory pab pab cdbw cdbr cdbw clock resets jtag/ eonce port digital reg analog reg low voltage supervisor v cap v dd v ss v dda v ssa 5 47 62 v pp 2 ocr_dis reset extboot emi_mode rsto 4 4 6 pwm outputs fault inputs pwma current sense inputs or gpioc 3 4 6 pwm outputs fault inputs pwmb current sense inputs or gpiod 3 quad timer d or gpioe quad timer c or gpioe ad0 ad1 adca 4 5 quadrature decoder 0 or quad timer a or gpioc flexcan 2 4 ad0 ad1 4 4 4 temp_sense quadrature decoder 1 or quad timer b or spi1 or gpioc 4 clko bus control 6 2 8 7 9 xtal ps / cs0 (gpiod8) rd wr d7-15 or gpiof0-8 d0-6 or gpiof9-15 gpiob0-3 (a16-19) a8-15 or gpioa0-7 a0-5 or gpioa8-13 a6-7 or gpioe2-3 vref adcb 16-bit 56800e core ds / cs1 (gpiod9) control gpio or emi cs or flexcan2 gpiod1 (cs3 or can2_rx ) gpiod0 (cs 2 or can2_tx) * configuration shown for on-chip 2.5v regulator 4 gpiob4 (a20, prescaler_clock) gpiob5-7 (a21-23, clk0-3**) 3 gpiod2-5 or c s4 -7 4 **see table 2-2 for explanation 2 ? up to 60 mips at 60mhz core frequency ? dsp and mcu functionality in a unified, c-efficient architecture ? access up to 4mb of off-ch ip program and 32mb of data memory ? chip select logic for glueless interface to rom and sram ? 512kb of program flash ? 4kb of program ram ? 32kb of data flash ? 32kb of data ram ? 32kb boot flash ? up to two 6-channel pwm modules ? four 4-channel, 12-bit adcs ? temperature sensor ? up to two quadrature decoders ? optional on-chip regulator ? up to two flexcan modules ? two serial communicat ion interfaces (scis) ? up to two serial peripheral interfaces (spis) ? up to four general-purpose quad timers ? computer operating properly (cop) / watchdog ? jtag/enhanced on-chip emulation (once?) for unobtrusive, real-time debugging ? up to 76 gpio lines ? 160-pin lqfp package and 160 mapbga 56f8367/56f8167 general description note: features in italics are not av ailable in the 56f8167 device.
56f8367 technical data, rev. 7.0 4 freescale semiconductor preliminary part 1: overview . . . . . . . . . . . . . . . . . . . . . . . 5 1.1. 56f8367/56f8167 features . . . . . . . . . . . . . 5 1.2. device description . . . . . . . . . . . . . . . . . . . . 7 1.3. award-winning development environment . 9 1.4. architecture block diagram . . . . . . . . . . . . 10 1.5. product documentation . . . . . . . . . . . . . . . 14 1.6. data sheet conventions . . . . . . . . . . . . . . 14 part 2: signal/connection descriptions . . . 15 2.1. introduction . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.2. signal pins . . . . . . . . . . . . . . . . . . . . . . . . . 18 part 3: on-chip clock synthesis (occs) . . 39 3.1. introduction . . . . . . . . . . . . . . . . . . . . . . . . . 39 3.2. external clock operation . . . . . . . . . . . . . . 39 3.3. registers . . . . . . . . . . . . . . . . . . . . . . . . . . 41 part 4: memory operating modes (mem) . . 41 4.1. introduction . . . . . . . . . . . . . . . . . . . . . . . . . 41 4.2. program map . . . . . . . . . . . . . . . . . . . . . . . 42 4.3. interrupt vector table . . . . . . . . . . . . . . . . . 43 4.4. data map . . . . . . . . . . . . . . . . . . . . . . . . . . 47 4.5. flash memory map . . . . . . . . . . . . . . . . . . . 47 4.6. eonce memory map . . . . . . . . . . . . . . . . . 49 4.7. peripheral memory mapped registers . . . . 49 4.8. factory programmed memory . . . . . . . . . . 80 part 5: interrupt controller (itcn) . . . . . . . . 81 5.1. introduction . . . . . . . . . . . . . . . . . . . . . . . . . 81 5.2. features . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 5.3. functional description . . . . . . . . . . . . . . . . 81 5.4. block diagram . . . . . . . . . . . . . . . . . . . . . . 83 5.5. operating modes . . . . . . . . . . . . . . . . . . . . 83 5.6. register descriptions . . . . . . . . . . . . . . . . . 84 5.7. resets . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 part 6: system integration module (sim) . 111 6.1. overview . . . . . . . . . . . . . . . . . . . . . . . . . 111 6.2. features . . . . . . . . . . . . . . . . . . . . . . . . . . 111 6.3. operating modes . . . . . . . . . . . . . . . . . . . 112 6.4. operating mode register . . . . . . . . . . . . . 112 6.5. register descriptions . . . . . . . . . . . . . . . . 113 6.6. clock generation overview . . . . . . . . . . . 127 6.7. power down modes overview . . . . . . . . . 128 6.8. stop and wait mode disable function . . . 128 6.9. resets . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 part 7: security features . . . . . . . . . . . . . . 129 7.1. operation with security enabled . . . . . . . 129 7.2. flash access blocking mechanisms . . . . 130 part 8: general purpose input/output (gpio) . . . . . . . . . . . . . . . . . . . . . . 132 8.1. introduction . . . . . . . . . . . . . . . . . . . . . . . . 132 8.2. memory maps . . . . . . . . . . . . . . . . . . . . . . 132 8.3. configuration . . . . . . . . . . . . . . . . . . . . . . . 133 part 9: joint test action group (jtag) . 137 9.1. 56f8367 information . . . . . . . . . . . . . . . . . 137 part 10: specifications . . . . . . . . . . . . . . . 138 10.1. general characteristics . . . . . . . . . . . . . . 138 10.2. dc electrical characteristics . . . . . . . . . . 142 10.3. ac electrical characteristics . . . . . . . . . . 146 10.4. flash memory characteristics . . . . . . . . . 146 10.5. external clock operation timing . . . . . . . 147 10.6. phase locked loop timing . . . . . . . . . . . 147 10.7. crystal oscillator timing . . . . . . . . . . . . . 148 10.8. external memory interface timing . . . . . . 148 10.9. reset, stop, wait, mode select, and interrupt timing . . . . . . . . . . . . . . 151 10.10. serial peripheral in terface (spi) timing . 153 10.11. quad timer timing . . . . . . . . . . . . . . . . 157 10.12. quadrature decoder timing . . . . . . . . . . 157 10.13. serial communication interface (sci) timing . . . . . . . . . . . . . . . . . . . . . 158 10.14. controller area network (can) timing . . . . . . . . . . . . . . . . . . . . . 159 10.15. jtag timing . . . . . . . . . . . . . . . . . . . . . 159 10.16. analog-to-digital converter (adc) parameters . . . . . . . . . . . . . . . . . 161 10.17. equivalent circuit fo r adc inputs . . . . . . 164 10.18. power consumption . . . . . . . . . . . . . . . . 164 part 11: packaging . . . . . . . . . . . . . . . . . . 166 11.1. 56f8367 package and pin-out information . . . . . . . . . . . . . . . . . . 166 11.2. 56f8167 package and pin-out information . . . . . . . . . . . . . . . . . . 173 part 12: design considerations . . . . . . . . 177 12.1. thermal design considerations . . . . . . . . 177 12.2. electrical design considerations . . . . . . . 178 12.3. power distribution and i/o ring implementation . . . . . . . . . . . . . . 179 part 13: ordering information . . . . . . . . . 180 table of contents
56f8367/56f8167 features 56f8367 technical data, rev. 7.0 freescale semiconductor 5 preliminary part 1 overview 1.1 56f8367/56f8167 features 1.1.1 core ? efficient 16-bit 56800e family controlle r engine with dual harvard architecture ? up to 60 million instructions per se cond (mips) at 60mhz core frequency ? single-cycle 16 16-bit parallel multiplier-accumulator (mac) ? four 36-bit accumulators, including extension bits ? arithmetic and logic multi-bit shifter ? parallel instruction set with unique dsp addressing modes ? hardware do and rep loops ? three internal address buses and one external address bus ? four internal data buses and one external data bus ? instruction set supports both dsp and controller functions ? controller-style addressing modes and instructions for compact code ? efficient c compiler and local variable support ? software subroutine and interrupt stac k with depth limited only by memory ? jtag/eonce debug programming interface 1.1.2 differences between devices table 1-1 outlines the key differences betw een the 56f8367 and 56f8167 devices. table 1-1 device differences feature 56f8367 56f8167 guaranteed speed 60mhz /60 mips 40mhz/40mips program ram 4kb not available data flash 32kb not available pwm 2 x 6 1 x 6 can 2 not available quad timer 4 2 quadrature decoder 2 x 4 1 x 4 temperature sensor 1 not available dedicated gpio ? 7
56f8367 technical data, rev. 7.0 6 freescale semiconductor preliminary 1.1.3 memory note: features in italics are not available in the 56f8167 device. ? harvard architecture permits as many as three simultaneous accesses to program and data memory ? flash security protection feature ? on-chip memory, including a low- cost, high-volume flash solution ? 512kb of program flash ? 4kb of program ram ? 32kb of data flash ? 32kb of data ram ? 32kb of boot flash ? off-chip memory expansio n capabilities provide a simple method for interfacing additional external memory and/or peripheral devices ? access up to 4mb of external program memo ry or 32mb of external data memory ? chip select logic for glueless interface to rom and sram ? eeprom emulation capability 1.1.4 peripheral circuits note: features in italics are not available in the 56f8167 device. ? pulse width modulator: ? in the 56f8367, two pulse width modulator modules, each with six pwm outputs, three current sense inputs, and three fault inputs; fault-tolerant de sign with dead time insertion; supports both center-aligned and edge-aligned modes ? in the 56f8167, one pulse width modulator module, with six pwm outputs, three current sense inputs, and three fault inputs; fault-tolerant design with dead time insertion; supports both center-aligned and edge-aligned modes ? four 12-bit, analog-to-digital converters (adcs), which support four simultaneous conversions with quad, 4-pin multiplexed inputs; adc and pwm modules can be synchronized through timer c, channels 2 and 3 ? quadrature decoder: ? in the 56f8367, two four-inp ut quadrature decoders or two additional quad timers ? in the 56f8167, one four-input quadrature decoder, which works in conjunction with quad timer a ? temperature sensor can be connected, on the board, to any of the adc inputs to monitor the on-chip temperature ?quad timer: ? in the 56f8367, four dedicated general-purpose quad timers totaling six dedicated pins: timer c with two pins and timer d with four pins ? in the 56f8167, two general-purpose quad timers ; timer a works in conj unction with quadrature decoder 0 or gpio and timer c works in conjunction with gpio ? up to two flexcan (can version 2.0 b-compliant) modules with 2-pin port for transmit and receive
device description 56f8367 technical data, rev. 7.0 freescale semiconductor 7 preliminary ? two serial communication interfaces (scis), each with two pins (or four additional gpio lines) ? up to two serial peripheral interfaces (spis), both w ith configurable 4-pin port (or eight additional gpio lines) ? in the 56f8367, spi1 can also be used as quadrature decoder 1, quad timer b or gpio ? in the 56f8167, spi1 can alternately be used only as gpio ? computer operating properly (cop) / watchdog timer ? two dedicated external interrupt pins ? up to 76 general purpose i/o (gpio) pins ? external reset input pi n for hardware reset ? external reset output pin for system reset ? integrated low-voltage interrupt module ? jtag/enhanced on-chip emulation (once) for unobtrusive, processor speed-independent debugging ? software-programmable, phase lock loop (pll)-based frequency sy nthesizer for the core clock 1.1.5 energy information ? fabricated in high-density cmos with 5v-tolerant, ttl-compatible digital inputs ? on-board 3.3v down to 2.6v voltage regulator for powering internal logic and memories; can be disabled ? on-chip regulators for digital and analog circuitry to lower cost and reduce noise ? wait and stop modes available ? adc smart power management ? each peripheral can be indivi dually disabled to save power 1.2 device description the 56f8367 and 56f8167 are memb ers of the 56800e core-based family of controllers. each combines, on a single chip, the processing powe r of a digital signal processor (d sp) and the functionality of a microcontroller with a flexible se t of peripherals to create an extr emely cost-effective solution. because of its low cost, configurati on flexibility, and compact progr am code, the 56f8367 and 56f8167 are well-suited for many applications. the device includes many peripherals that are especially useful for motion control, smart appliances, steppers, encoders, tachometers, limit switches, power supply and control, automotive control (56f8367 only), engine manageme nt, noise suppression, remote utility metering, industrial control for power, lighting, and automation applications. the 56800e core is based on a harv ard-style architecture c onsisting of three execution units operating in parallel, allowing as many as six operations per instruction cycle. the mcu-style programming model and optimized instruction set allow stra ightforward generation of efficien t, compact dsp and control code. the instruction set is also highly efficient for c/c++ compilers to en able rapid development of optimized control applications. the 56f8367 and 56f8167 support program execution from internal or external memories. two data operands can be accessed from the on -chip data ram per instruction cy cle. these devices also provide two external dedicated in terrupt lines and up to 76 general purpose input/output (gpio) lines, depending on peripheral configuration.
56f8367 technical data, rev. 7.0 8 freescale semiconductor preliminary 1.2.1 56f8367 features the 56f8367 controller includes 512kb of program fl ash and 32kb of data fl ash (each programmable through the jtag port) with 4kb of program ram and 32kb of data ram. it also supports program execution from external memory. a total of 32kb of boot flash is incorporated for ea sy customer inclusion of field-programmable software routines that can be used to program the main progr am and data flash memory areas. both program and data flash memories can be independently bulk erased or erased in page sizes. program flash page erase size is 1kb. boot and data flash pa ge erase size is 512 bytes. the boot flash memory can also be either bulk or page erased. a key application-specific feature of the 56f8367 is the inclusion of two puls e width modulator (pwm) modules. these modules each incorporate three comp lementary, individually programmable pwm signal output pairs (each module is also capable of supporti ng six independent pwm func tions, for a total of 12 pwm outputs) to enhance motor c ontrol functionality. complementar y operation permits programmable dead time insertion, distortion correction via curren t sensing by software, an d separate top and bottom output polarity control. the up-count er value is programmable to s upport a continuously variable pwm frequency. edge-aligned and center -aligned synchronous pulse width c ontrol (0% to 100% modulation) is supported. the device is capable of controlling most motor types: acim (ac induction motors); both bdc and bldc (brush and brushl ess dc motors); srm and vrm (s witched and variable reluctance motors); and stepper motors. the pwms incorporate fault protection a nd cycle-by-cycle current limiting with sufficient output drive capabi lity to directly drive standard optoisolators. a ?smoke-inhibit?, write-once protection feature for key parameters is also included. a patented pwm waveform distortion correction circuit is also provided. each pwm is double-buffered and includes interrupt controls to permit integral reload rates to be pr ogrammable from 1 to 16. the pwm m odules provide a reference output to synchronize the analog-to-digital converters through two channels of quad timer c. the 56f8367 incorporates two quadra ture decoders capabl e of capturing all four transitions on the two-phase inputs, permitting genera tion of a number proportional to actu al position. speed computation capabilities accommodate both fa st- and slow-moving shafts. an in tegrated watchdog timer in the quadrature decoder can be programmed with a time-out value to alarm when no shaft motion is detected. each input is filtered to ensure only true transitions are recorded. this controller also provides a fu ll set of standard pr ogrammable peripherals th at include two serial communications interfaces (scis); two serial peripheral interfaces (spi s); and four quad timers. any of these interfaces can be used as general purpose input /outputs (gpios) if that function is not required. two flex controller area network (flexcan) interfaces (c an version 2.0 b-compliant) and an internal interrupt controller are a part of the 56f8367. 1.2.2 56f8167 features the 56f8167 controller includes 128kb of program flash, programmable throug h the jtag port, with 8kb of data ram. it also supports pr ogram execution from external memory. a total of 8kb of boot flash is in corporated for easy customer incl usion of field-programmable software routines that can be used to pr ogram the main program flash memory area, which can be independently bulk erased or erased in pages. pr ogram flash page erase size is 1kb. boot flash page erase size is 512 bytes and the boot flash memory can al so be either bulk or page erased.
award-winning development environment 56f8367 technical data, rev. 7.0 freescale semiconductor 9 preliminary a key application-specific featur e of the 56f8167 is the inclusion of one pulse width modulator (pwm) module. this module incorporat es three complementary, individua lly programmable pwm signal output pairs and can also support six i ndependent pwm functions to enhance motor control functionality. complementary operation permits programmable dead time insertion, distorti on correction via current sensing by software, and separate top and bottom output polarity control. the up-counter value is programmable to support a continuously variable pwm frequency. edge-ali gned and center-aligned synchronous pulse width control (0 % to 100% modulation) is suppor ted. the device is capable of controlling most motor types: ac im (ac induction motors ); both bdc and bldc (brush and brushless dc motors); srm and vrm (switched and variable reluctance motors); and stepper motors. the pwm incorporates fault protection and cy cle-by-cycle current limiting with su fficient output drive capability to directly drive standard optoisolato rs. a ?smoke-inhibit?, write-once pr otection feature for key parameters is also included. a patented pwm waveform distortion correction circ uit is also provided. each pwm is double-buffered and includes in terrupt controls to permit integral re load rates to be programmable from 1 to 16. the pwm module provides reference outputs to synchronize the analog-to-digital converters through two channels of quad timer c. the 56f8167 incorporates a quadrature decoder capable of capturing all four tr ansitions on the two-phase inputs, permitting generation of a number proportional to actual position. speed co mputation capabilities accommodate both fast- and slow-m oving shafts. an integrated watchdog timer in the quadrature decoder can be programmed with a tim e-out value to alert when no shaft motion is detecte d. each input is filtered to ensure only true transitions are recorded. this controller also provides a fu ll set of standard pr ogrammable peripherals th at include two serial communications interfaces (scis); tw o serial peripheral interfaces (spi s); and two quad timers. any of these interfaces can be used as ge neral purpose input/outputs (gpios) if that function is not required. an internal interrupt controller is also a part of the 56f8167. 1.3 award-winning development environment processor expert tm (pe) provides a rapid application design (rad) tool that combines easy-to-use component-based software application cr eation with an expert knowledge system. the codewarrior integrated devel opment environment is a sophisti cated tool for code navigation, compiling, and debugging. a complete set of evaluation modules (evms) and development system cards will support concurrent e ngineering. together, pe, codewarrior and evms create a complete, scalable tools solution for easy, fast, and efficient development.
56f8367 technical data, rev. 7.0 10 freescale semiconductor preliminary 1.4 architecture block diagram note: features in italics are not available in the 56f8167 device and are shaded in the following figures. the 56f8367/56f8167 architecture is shown in figure 1-1 and figure 1-2 . figure 1-1 illustrates how the 56800e system buses communicate with internal memories, the external memory interface and the ipbus bridge. table 1-2 lists the internal buses in the 56800e arch itecture and provides a brief description of their function. figure 1-2 shows the peripherals and control bloc ks connected to the ipbus bridge. the figures do not show the on-board regulator and power and ground signa ls. they also do not show the multiplexing between peripherals or the dedicated gp ios. please see part 2, signal/connection descriptions, to see which signals are multiplexe d with those of other peripherals. also shown in figure 1-2 are connections betw een the pwm, timer c and adc blocks. these connections allow the pwm and/or timer c to control the timing of the start of adc conversions. the timer c channel indicated can generate periodic start (sync) signals to the adc to start its conversions. in another operating mode, th e pwm load interrupt (sync output) signa l is routed internally to the timer c input channel as indica ted. the timer can then be used to introduce a controllable delay before generating its output signal. the time r output then triggers the adc. to fully understand this interaction, please see the 56f8300 peripheral user manual for clarification on the opera tion of all three of these peripherals.
architecture block diagram 56f8367 technical data, rev. 7.0 freescale semiconductor 11 preliminary figure 1-1 system bus interfaces note: flash memories are encapsulate d within the flash memory (fm) module. flash control is accomplished by the i/o to the fm over the peripheral bus, while reads and writes are completed between the core and the flash memories. note: the primary data ram port is 32 bits wide. other data ports are 16 bits. 56800e program flash data ram emi data flash ipbus bridge boot flash flash memory module chip tap controller tap linking module jtag / eonce 5 24 pdb_m[15:0] pab[20:0] cdbw[31:0] xab1[23:0] cdbr_m[31:0] xab2[23:0] xdb2_m[15:0] ipbus external jtag port to flash control logic address data control 16 10 not available on the 56f8167 device. program ram
56f8367 technical data, rev. 7.0 12 freescale semiconductor preliminary figure 1-2 peripheral subsystem flexcan2 flexcan quadrature decoder 1 temp_sense timer b timer d timer a timer c spi 1 adcb adca gpio a spi 0 sci 0 sci 1 interrupt controller pwmb quadrature decoder 0 note: adc a and adc b use the same voltage reference circuit with v refh , v refp , v refmid , v refn , and v reflo pins. gpio b gpio c gpio d gpio e gpio f clkgen (osc/pll) por & lvi sim sync output sync output to/from ipbus bridge low voltage interrupt system por cop reset reset 13 2 2 13 2 8 8 1 2 2 4 4 4 4 ch3i ch2i ch2o ch3o pwma not available on the 56f8167 device. cop ipbus
architecture block diagram 56f8367 technical data, rev. 7.0 freescale semiconductor 13 preliminary table 1-2 bus signal names name function program memory interface pdb_m[15:0] program data bus for instruct ion word fetches or read operations. cdbw[15:0] primary core data bus used for program memory writes. (only these 16 bi ts of the cdbw[31:0] bus are used for writes to program memory.) pab[20:0] program memory address bus. data is returned on pdb_m bus. primary data memory interface bus cdbr_m[31:0] primary core data bus for memory reads. addressed via xab1 bus. cdbw[31:0] primary core data bus for memory writes. addressed via xab1 bus. xab1[23:0] primary data address bus. capable of addressing bytes 1 , words, and long data types. data is written on cdbw and returned on cdbr_m. also used to access memory-mapped i/o. 1. byte accesses can only occur in the bottom half of the memory address space. the msb of the address will be forced to 0. secondary data memory interface xdb2_m[15:0] secondary data bus used for secondary da ta address bus xab2 in the dual memory reads. xab2[23:0] secondary data address bus used for the second of two simultaneous accesses. capable of addressing only words. data is returned on xdb2_m. peripheral interface bus ipbus [15:0] peripheral bus accesses all on-chip peripherals registers. this bus operates at the same clock rate as the primary data memory and therefore ge nerates no delays when accessing the processor. write data is obtained from cdbw. read data is provided to cdbr_m.
56f8367 technical data, rev. 7.0 14 freescale semiconductor preliminary 1.5 product documentation the documents in table 1-2 are required for a complete desc ription and proper design with the 56f8367/56f8167 devices. documentation is availabl e from local freescale distributors, freescale semiconductor sales offices, fr eescale literature distribution centers, or online at http://www.freescale.com . table 1-3 chip documentation 1.6 data sheet conventions this data sheet uses the following conventions: topic description order number dsp56800e reference manual detailed description of the 56800e family architecture, and 16-bit controller core pr ocessor and the instruction set dsp56800eerm 56f8300 peripheral user manual detailed description of peripherals of the 56f8300 devices mc56f8300um 56f8300 sci/can bootloader user manual detailed description of the sci/can bootloaders 56f8300 family of devices mc56f83xxblum 56f8367/56f8167 technical data sheet electrical and timing specifications, pin descriptions, and package descriptions (this document) mc56f8367 errata details any chip issues that might be present mc56f8367e MC56F8167e overbar this is used to indicate a signal that is active when pulled low. for example, the reset pin is active when low. ?asserted? a high true (active high) signal is hi gh or a low true (active low) signal is low. ?deasserted? a high true (active high) signal is low or a low true (active low) signal is high. examples: signal/symbol logic state signal state voltage 1 1. values for vil, vol, vih, and voh are defined by individual product specifications. pin true asserted v il /v ol pin false deasserted v ih /v oh pin true asserted v ih /v oh pin false deasserted v il /v ol
introduction 56f8367 technical data, rev. 7.0 freescale semiconductor 15 preliminary part 2 signal/connection descriptions 2.1 introduction the input and output signals of the 56f8367 and 56f8167 are organized in to functional groups, as detailed in table 2-1 and as illustrated in figure 2-1 . in table 2-2 , each table row describe s the signal or signals present on a pin. table 2-1 functional group pin allocations functional group number of pins in package 56f8367 56f8167 power (v dd or v dda )99 power option control 1 1 ground (v ss or v ssa )77 supply capacitors 1 & v pp 1. if the on-chip regulator is disabled, the v cap pins serve as 2.5v v dd_core power inputs 66 pll and clock 4 4 address bus 24 24 data bus 16 16 bus control 10 10 interrupt and program control 6 6 pulse width modulator (pwm) ports 26 13 serial peripheral interface (spi) port 0 4 4 serial peripheral interface (spi) port 1 ? 4 quadrature decoder port 0 2 2. alternately, can function as quad timer pins 44 quadrature decoder port 1 3 3. pins in this section can function as quad timer, spi #1, or gpio 4? serial communications interface (sci) ports 2 44 can ports 2 ? analog to digital converter (adc) ports 21 21 timer module ports 6 2 jtag/enhanced on-chip emulation (eonce) 5 5 temperature sense 1 ? dedicated gpio ? 7
56f8367 technical data, rev. 7.0 16 freescale semiconductor preliminary figure 2-1 56f8367 signals iden tified by functional group 1 (160-pin lqfp) 1. alternate pin functionality is shown in parenthesis ; pin direction/type shown is the default functionality. v dd_io v dda_osc_pll v dda_adc v ss v ssa_adc other supply ports external address bus or gpio external data bus sci 0 or gpio sci 1 or gpiod 1 1 7 1 6 v pp 1 & v pp 2 2 power ground power ground a8 - a15 (gpioa0 - 7) txd0 (gpioe0) rxd0 (gpioe1) txd1 (gpiod6) rxd1 (gpiod7) tck tms tdi tdo trst quadrature decoder 0 or quad timer a phasea0 (ta0, gpioc4) phaseb0 (ta1, gpioc5) index0 (ta2, gpioc6) home0 (ta3, gpioc7) phaseb1 (tb1, mosi1, gpioc1) index1 (tb2, miso1, gpioc2) home1 (tb3, ss 1, gpioc3) pwma0 - 5 isa0 - 2 (gpioc8 - 10) faulta0 - 3 isb0 - 2 (gpiod10 - 12) faultb0 - 3 pwmb0 - 5 ana0 - 7 anb0 - 7 v ref can_rx can_tx tc0 - 1 (gpioe8 - 9) td0 - 3 (gpioe10 - 13) irqa irqb reset rsto spi0 or gpio pwma quadrature decoder 1 or quad timer b or spi 1 or gpio pwmb adcb adca flexcan quad timer c and d or gpio interrupt/ program control phasea1(tb0, sclk1, gpioc0) 8 8 gpiob0 - 7 (a16 - 23) 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 6 3 4 6 3 4 8 5 8 1 1 1 2 4 1 1 1 1 1 56f8367 temp_sense *v cap 1 - v cap 4 4 a0 - a5 (gpioa8 - 13) 6 a6 - a7 (gpioe2 - 3) 2 rd 1 wr 1 ps /cs0 (gpiodf8) 1 ds /cs1 (gpiofd9) 1 gpiod0 (cs2 , can2_tx) 1 jtag/ eonce port external bus control d7 - d15 (gpiof0 - 8) 9 d0 - d6 (gpiof9 - 15) 7 extboot mosi0 (gpioe5) miso0 (gpioe6) ss0 (gpioe7) 1 1 1 sclk0 1 1 emi_mode power ocr_dis 1 1 gpiod2 - 5 (cs4 - 7 ) 4 gpiod1 (cs3 , can2_rx) temperature sense 1 gpiob4 (a20, prescaler_clock) 1 gpiob5 (a21, sys_clk) 1 gpiob6 (a22, sys_clk2) 1 gpiob7 (a23, oscillator_clock) pll and clock extal xtal clko 1 1 1 clkmode 1 * when the on-chip regulator is disabl ed, these four pins become 2.5v v dd_core .
introduction 56f8367 technical data, rev. 7.0 freescale semiconductor 17 preliminary figure 2-2 56f8167 signals iden tified by functional group 1 (160-pin lqfp) 1. alternate pin functionality is shown in parenthesis ; pin direction/type shown is the default functionality. v dd_io v dda_adc v ss v ssa_adc other supply ports pll and clock external address bus or gpio external data bus or gpio sci 0 or gpio sci 1 or gpio 1 7 1 6 v pp 1 & v pp 2 2 power ground power ground a8 - a15 (gpioa0 - 7) txd0 (gpioe0) rxd0 (gpioe1) txd1 (gpiod6) rxd1 (gpiod7) tck tms tdi tdo trst quadrature decoder 0 or quad timer a or gpio phasea0 (ta0, gpioc4) phaseb0 (ta1, gpioc5) index0 (ta2, gpioc6) home0 (ta3, gpioc7) (mosi1, gpioc1) (miso1, gpioc2) (s s1 , gpioc3) (gpioc8 - 10) isb0 - 2 (gpiod10 - 12) faultb0 - 3 pwmb0 - 5 ana0 - 7 anb0 - 7 v ref tc0 - 1 (gpioe8 - 9) (gpioe10 - 13) irqa irqb reset rsto spi0 or gpio gpio spi 1 or gpio pwmb or gpio adcb adca interrupt / program control (sclk1, gpioc0) 8 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 3 6 3 4 8 5 8 2 4 1 1 1 1 1 56f8167 extal xtal clko 1 1 1 *v cap 1 - v cap 4 4 a0 - a5 (gpioa8 - 13) 6 a6 - a7 (gpioe2 - 3) 2 rd 1 wr 1 ps (cs0 , gpiod8) 1 ds (cs1 , gpiod9) 1 gpiod0 - 5 (cs2 - 7 ) 6 jtag/ eonce port external bus control or gpio extboot mosi0 (gpioe5) miso0 (gpioe6) ss0 (gpioe7) 1 1 1 sclk0 1 1 emi_mode ocr_dis 1 power clkmode 1 v dda_osc_pll 1 4 gpiob0 - 3 (a16 - 19) 1 gpiob4 (a20, prescaler_clock) 1 gpiob5 (a21, sys_clk) 1 gpiob6 (a22, sys_clk2) 1 gpiob7 (a23, oscillator_clock) d7 - d15 (gpiof0 - 8) d0 - d6 (gpiof9 - 15) 7 9 quad timer c or gpio * when the on-chip regulator is disa bled, these four pins become 2.5v v dd_core .
56f8367 technical data, rev. 7.0 18 freescale semiconductor preliminary 2.2 signal pins after reset, each pin is configured for its primary function (listed first). any alternate functionality must be programmed. note: signals in italics are not available in the 56f8167 device. note: the 160 map ball grid array is not available in the 56f8167 device. if the ?state during reset? lists more than one state fo r a pin, the first state is th e actual reset state. other states show the reset condition of the alternate function, which you ge t if the alternate pin function is selected without changing the confi guration of the a lternate peripheral. for ex ample, the a8/gpioa0 pin shows that it is tri-stated during reset. if the gpio a_per is changed to select the gpio function of the pin, it will become an input if no other registers are changed. note: lqfp pin numbers and mbga ball numbers do not al ways correlate in tabl e 2-2. please contact factory for exact correlation. table 2-2 signal and package info rmation for the 160-pin lqfp and mbga signal name pin no. ball no. type state during reset signal description v dd_io 1 f4 supply i/o power ? this pin supplies 3.3v power to the chip i/o interface and also the processor core through the on-chip voltage regulator, if it is enabled. v dd_io 16 k5 v dd_io 31 e5 v dd_io 42 k7 v dd_io 77 e9 v dd_io 96 k10 v dd_io 134 f11 v dda_adc 114 c14 supply adc power ? this pin supplies 3.3v power to the adc modules. it must be connected to a clean analog power supply. v dda_osc_ pll 92 k13 supply oscillator and pll power ? this pin supplies 3.3v power to the osc and to the internal regulator that in turn supplies the phase locked loop. it must be connected to a clean analog power supply.
signal pins 56f8367 technical data, rev. 7.0 freescale semiconductor 19 preliminary v ss 27 j4 supply v ss ? these pins provide ground for chip logic and i/o drivers. v ss 41 k11 v ss 74 g11 v ss 80 e7 v ss 125 j11 v ss 160 e6 v ssa_adc 115 d12 supply adc analog ground ? this pin supplies an analog ground to the adc modules. ocr_dis 91 k14 input input on-chip regulator disable ? tie this pin to v ss to enable the on-chip regulator tie this pin to v dd to disable the on-chip regulator this pin is intended to be a static dc signal from power-up to shut down. do not try to toggle this pin for power savings during operation. v cap 1* 62 k8 supply supply v cap 1 - 4 ? when ocr_dis is tied to v ss (regulator enabled), connect each pin to a 2.2 f or greater bypass capacitor in order to bypass the core logic voltage regulator, required for proper chip operation. when ocr_dis is tied to v dd (regulator disabled), these pins become v dd_core and should be connected to a regulated 2.5v power supply. note: this bypass is required even if the chip is powered with an external supply. v cap 2* 144 e8 v cap 3* 95 h11 v cap 4* 15 g4 * when the on-chip regulator is dis abled, these four pins become 2.5v v dd_core . v pp 1 141 a7 input input v pp 1 - 2 ? these pins should be left unconnected as an open circuit for normal functionality. v pp 2 2c2 clkmode 99 h12 input input clock input mode selection ? this input determines the function of the xtal and extal pins. 1 = external clock input on xtal is used to directly drive the input clock of the chip. the extal pin should be grounded. 0 = a crystal or ceramic resonat or should be connected between xtal and extal. extal 94 j12 input input external crystal oscillator input ? this input can be connected to an 8mhz external crystal. tie this pin low if xtal is driven by an external clock source. table 2-2 signal and package info rmation for the 160-pin lqfp and mbga signal name pin no. ball no. type state during reset signal description
56f8367 technical data, rev. 7.0 20 freescale semiconductor preliminary xtal 93 k12 input/ output chip-driven crystal oscillator output ? this output connects the internal crystal oscillator output to an external crystal. if an external clock is used, xtal must be used as the input and extal connected to gnd. the input clock can be selected to provide the clock directly to the core. this input clock can also be selected as the input clock for the on-chip pll. clko 3 d3 output in reset, output is disabled clock output ? this pin outputs a buffered clock signal. using the sim clko select register (sim_clkosr), this pin can be programmed as any of the following: disabled, clk_mstr (system clock), ipbus clock, oscillator output, prescaler clock and postscaler clock. other signals are also available for test purposes. see part 6.5.7 for details. a0 (gpioa8) 154 c3 output input/ output in reset, output is disabled, pull-up is enabled address bus ? a0 - a5 specify six of the address lines for external program or data memory accesses. depending upon the state of the dr v bit in the emi bus control register (bcr), a0 - a5 and emi c ontrol signals are tri-stated when the external bus is inactive. most designs will want to change the drv state to drv = 1 instead of using the default setting. port a gpio ? these six gpio pins can be individually programmed as input or output pins. after reset, the default state is address bus. to deactivate the internal pull-up resistor, clear the appropriate gpio bit in the gpioa_pur register. example: gpioa8, clear bit 8 in the gpioa_pur register. a1 (gpioa9) 10 e3 a2 (gpioa10) 11 e4 a3 (gpioa11) 12 f2 a4 (gpioa12) 13 f1 a5 (gpioa13) 14 f3 table 2-2 signal and package info rmation for the 160-pin lqfp and mbga signal name pin no. ball no. type state during reset signal description
signal pins 56f8367 technical data, rev. 7.0 freescale semiconductor 21 preliminary a6 (gpioe2) 17 g1 output schmitt input/ output in reset, output is disabled, pull-up is enabled address bus ? a6 - a7 specify two of the address lines for external program or data memory accesses. depending upon the state of the dr v bit in the emi bus control register (bcr), a6 - a7 and emi c ontrol signals are tri-stated when the external bus is inactive. most designs will want to change the drv state to drv = 1 instead of using the default setting. port e gpio ? these two gpio pins can be individually programmed as input or output pins. after reset, the default state is address bus. to deactivate the internal pull-up resistor, clear the appropriate gpio bit in the gpioe_pur register. example: gpioe2, clear bit 2 in the gpioe_pur register. a7 (gpioe3) 18 g3 a8 (gpioa0) 19 g2 output schmitt input/ output in reset, output is disabled, pull-up is enabled address bus ? a8 - a15 specify eight of the address lines for external program or data memory accesses. depending upon the state of the dr v bit in the emi bus control register (bcr), a8 - a15 and emi control signals are tri-stated when the external bus is inactive. most designs will want to change the drv state to drv = 1 instead of using the default setting. port a gpio ? these eight gpio pins can be individually programmed as input or output pins. after reset, the default state is address bus. to deactivate the internal pull-up resistor, clear the appropriate gpio bit in the gpioa_pur register. example: gpioa0, clear bit 0 in the gpioa_pur register. a9 (gpioa1) 20 h1 a10 (gpioa2) 21 h2 a11 (gpioa3) 22 h4 a12 (gpioa4) 23 h3 a13 (gpioa5) 24 j1 a14 (gpioa6) 25 j2 a15 (gpioa7) 26 j3 table 2-2 signal and package info rmation for the 160-pin lqfp and mbga signal name pin no. ball no. type state during reset signal description
56f8367 technical data, rev. 7.0 22 freescale semiconductor preliminary gpiob0 (a16) 33 l1 schmitt input/ output output input, pull-up enabled port b gpio ? these four gpio pins can be programmed as input or output pins. address bus ? a16 - a19 specify one of the address lines for external program or data memory accesses. depending upon the state of the dr v bit in the emi bus control register (bcr), a16 - a19 and em i control signals are tri-stated when the external bus is inactive. most designs will want to change the drv state to drv = 1 instead of using the default setting. after reset, the startup state of gpiob0 - gpiob3 (gpio or address) is determined as a function of extboot, emi_mode and the flash security setting. see table 4-4 for further information on when this pin is configured as an address pin at reset. in all cases, this state may be changed by writing to gpiob_per. to deactivate the internal pull-up resistor, clear the appropriate gpio bit in the gpiob_pur register. gpiob1 (a17) 34 l3 gpiob2 (a18) 35 l2 gpiob3 (a19) 36 m1 gpiob4 (a20) (prescaler_ clock) 37 m2 schmitt input/ output output output input, pull-up enabled port b gpio ? these four gpio pins can be programmed as input or output pins. address bus ? a20 - a23 specify one of the address lines for external program or data memory accesses. depending upon the state of the dr v bit in the emi bus control register (bcr), a20?a23 and emi cont rol signals are tri-stated when the external bus is inactive. most designs will want to change the drv state to drv = 1 instead of using the default setting. clock outputs ? can be used to monitor the prescaler_clock, sys_clk, sys_clk2 or oscillator_clock on gpiob4 through gpiob7, respectively. after reset, the default state is gpio. these pins can also be used to extend the external address bus to its full length or to view any of several system clocks. in these cases, the gpio_b_per can be used to individually disable the gpio. the clkosr register in the sim (see part 6.5.7 ) can then be used to choose between address and clock functions. gpiob5 (a21) (sys_clk) 46 n4 gpiob6 (a22) (sys_clk2) 47 p3 gpiob7 (a23) (oscillator_ clock) 48 m4 table 2-2 signal and package info rmation for the 160-pin lqfp and mbga signal name pin no. ball no. type state during reset signal description
signal pins 56f8367 technical data, rev. 7.0 freescale semiconductor 23 preliminary d0 (gpiof9) 70 p10 input/ output input/ output in reset, output is disabled, pull-up is enabled data bus ? d0 - d6 specify part of the data for external program or data memory accesses. depending upon the state of the dr v bit in the emi bus control register (bcr), d0?d6 are tri-st ated when the external bus is inactive. most designs will want to change the drv state to drv = 1 instead of using the default setting. port f gpio ? these seven gpio pins can be individually programmed as input or output pins. after reset, these pins default to the emi data bus function. to deactivate the internal pull-up resistor, clear the appropriate gpio bit in the gpiof_pur register. example: gpiof9, clear bit 9 in the gpiof_pur register. d1 (gpiof10) 71 n10 d2 (gpiof11) 83 p14 d3 (gpiof12) 86 l13 d4 (gpiof13) 88 l14 d5 (gpiof14) 89 l12 d6 (gpiof15) 90 l11 table 2-2 signal and package info rmation for the 160-pin lqfp and mbga signal name pin no. ball no. type state during reset signal description
56f8367 technical data, rev. 7.0 24 freescale semiconductor preliminary d7 (gpiof0) 28 k1 input/ output input/ output in reset, output is disabled, pull-up is enabled data bus ? d7 - d15 specify part of the data for external program or data memory accesses. depending upon the state of the drv bit in the emi bus control register (bcr), d7 - d15 are tri-st ated when the external bus is inactive. most designs will want to change the drv state to drv = 1 instead of using the default setting. port f gpio ? these nine gpio pins can be individually programmed as input or output pins. at reset, these pins default to data bus functionality. to deactivate the internal pull-up resistor, clear the appropriate gpio bit in the gpiof_pur register. example: gpiof0, clear bit 0 in the gpiof_pur register. d8 (gpiof1) 29 k3 d9 (gpiof2) 30 k2 d10 (gpiof3) 32 k4 d11 (gpiof4) 149 a5 d12 (gpiof5) 150 a4 d13 (gpiof6) 151 b5 d14 (gpiof7) 152 c4 d15 (gpiof8) 153 a3 rd 52 p5 output in reset, output is disabled, pull-up is enabled read enable ? rd is asserted during external memory read cycles. when rd is asserted low, pins d0 - d15 become inputs and an external device is enabled onto the data bus. when rd is deasserted high, the external data is latched inside the device. when rd is asserted, it qualifies the a0 - a23, ps , ds , and csn pins. rd can be connected directly to the oe pin of a static ram or rom. depending upon the state of the dr v bit in the emi bus control register (bcr), rd is tri-stated when the external bus is inactive. most designs will want to change the drv state to drv = 1 instead of using the default setting. to deactivate the internal pull-up resistor, set the ctrl bit in the sim_pudr register. table 2-2 signal and package info rmation for the 160-pin lqfp and mbga signal name pin no. ball no. type state during reset signal description
signal pins 56f8367 technical data, rev. 7.0 freescale semiconductor 25 preliminary wr 51 l4 output in reset, output is disabled, pull-up is enabled write enable ? wr is asserted during external memory write cycles. when wr is asserted low, pins d0 - d15 become outputs and the device puts data on the bus. when wr is deasserted high, the external data is latched inside the external device. when wr is asserted, it qualifies the a0 - a23, ps , ds , and csn pins. wr can be connected directly to the we pin of a static ram. depending upon the state of the dr v bit in the emi bus control register (bcr), wr is tri-stated when the external bus is inactive. most designs will want to change the drv state to drv = 1 instead of using the default setting. to deactivate the internal pull-up resistor, set the ctrl bit in the sim_pudr register. ps (cs0 ) (gpiod8) 53 n6 output input/ output in reset, output is disabled, pull-up is enabled program memory select ? this signal is actually cs0 in the emi, which is programmed at reset for compatibility with the 56f80x ps signal. ps is asserted low for external program memory access. depending upon the state of the dr v bit in the emi bus control register (bcr), cs0 is tri-stated when the external bus is inactive. cs0 resets to provide the ps function as defined on the 56f80x devices. port d gpio ? this gpio pin can be individually programmed as an input or output pin. to deactivate the internal pull-up resistor, clear bit 8 in the gpiod_pur register. ds (cs1 ) (gpiod9) 54 l5 output input/ output in reset, output is disabled, pull-up is enabled data memory select ? this signal is actually cs1 in the emi, which is programmed at reset for compatibility with the 56f80x ds signal. ds is asserted low for exte rnal data memory access. depending upon the state of the dr v bit in the emi bus control register (bcr), cs1 is tri-stated when the external bus is inactive. cs1 resets to provide the ds function as defined on the 56f80x devices. port d gpio ? this gpio pin can be individually programmed as an input or output pin. to deactivate the internal pull-up resistor, clear bit 9 in the gpiod_pur register. table 2-2 signal and package info rmation for the 160-pin lqfp and mbga signal name pin no. ball no. type state during reset signal description
56f8367 technical data, rev. 7.0 26 freescale semiconductor preliminary gpiod0 (cs2 ) ( can2_tx ) 55 p6 input/ output output open drain output input, pull-up enabled port d gpio ? this gpio pin can be individually programmed as an input or output pin. chip select ? cs2 may be programmed within the emi module to act as a chip select for specif ic areas of the external memory map. depending upon the state of the dr v bit in the emi bus control register (bcr), cs2 is tri-stated when the external bus is inactive. most designs will want to change the drv state to drv = 1 instead of using the default setting. flexcan2 transmit data ? can output. at reset, this pin is configured as gpio. this configuration can be changed by setting bit 0 in the gpio_d_per register. then change bit 4 in the sim_gps register to select the desired peripheral function. to deactivate the internal pull-up resistor, clear bit 0 in the gpiod_pur register. gpiod1 (cs3 ) ( can2_rx ) 56 l6 schmitt input/ output output schmitt input input, pull-up enabled port d gpio ? this gpio pin can be individually programmed as an input or output pin. chip select ? cs3 may be programmed within the emi module to act as a chip select for specif ic areas of the external memory map. depending upon the state of the dr v bit in the emi bus control register (bcr), cs3 is tri-stated when the external bus is inactive. most designs will want to change the drv state to drv = 1 instead of using the default setting. flexcan2 receive data ? this is the can input. this pin has an internal pull-up resistor. at reset, this pin is configured as gpio. this configuration can be changed by setting bit 1 in the gpio_d_per register. then change bit 5 in the sim_gps register to select the desired peripheral function. to deactivate the internal pull-up resistor, clear bit 1 in the gpiod_pur register. table 2-2 signal and package info rmation for the 160-pin lqfp and mbga signal name pin no. ball no. type state during reset signal description
signal pins 56f8367 technical data, rev. 7.0 freescale semiconductor 27 preliminary gpiod2 (cs4 ) 57 k6 input/ output output input, pull-up enabled port d gpio ? these four gpio pins can be individually programmed as input or output pins. chip select ? cs4 - cs7 may be programmed within the emi module to act as chip selects for specific areas of the external memory map. depending upon the state of the dr v bit in the emi bus control register (bcr), cs4 - cs7 are tri-stated when the external bus is inactive. most designs will want to change the drv state to drv = 1 instead of using the default setting. at reset, these pins are configured as gpio. to deactivate the internal pull-up resistor, clear the appropriate gpio bit in the gpiod_pur register. example: gpiod2, clear bit 2 in the gpiod_pur register. gpiod3 (cs5) 58 n7 gpiod4 (cs6 ) 59 p7 gpiod5 (cs7 ) 60 l7 txd0 (gpioe0) 4 b1 output input/ output in reset, output is disabled, pull-up is enabled transmit data ? sci0 transmit data output port e gpio ? this gpio pin can be individually programmed as an input or output pin. after reset, the default state is sci output. to deactivate the internal pull-up resistor, clear bit 0 in the gpioe_pur register. rxd0 (gpioe1) 5 d2 input input/ output input, pull-up enabled receive data ? sci0 receiv e data input port e gpio ? this gpio pin can be individually programmed as an input or output pin. after reset, the default state is sci output. to deactivate the internal pull-up resistor, clear bit 1 in the gpioe_pur register. table 2-2 signal and package info rmation for the 160-pin lqfp and mbga signal name pin no. ball no. type state during reset signal description
56f8367 technical data, rev. 7.0 28 freescale semiconductor preliminary txd1 (gpiod6) 49 p4 output input/ output in reset, output is disabled, pull-up is enabled transmit data ? sci1 transmit data output port d gpio ? this gpio pin can be individually programmed as an input or output pin. after reset, the default state is sci output. to deactivate the internal pull-up resistor, clear bit 6 in the gpiod_pur register. rxd1 (gpiod7) 50 n5 input input/ output input, pull-up enabled receive data ? sci1 receiv e data input port d gpio ? this gpio pin can be individually programmed as an input or output pin. after reset, the default state is sci input. to deactivate the internal pull-up resistor, clear bit 7 in the gpiod_pur register. tck 137 d8 schmitt input input, pulled low internally test clock input ? this input pin provides a gated clock to synchronize the test logic and shift serial data to the jtag/eonce port. the pin is connected internally to a pull-down resistor. tms 138 a8 schmitt input input, pulled high internally test mode select input ? this input pin is used to sequence the jtag tap controller?s st ate machine. it is sampled on the rising edge of tck and has an on-chip pull-up resistor. to deactivate the internal pull-up resistor, set the jtag bit in the sim_pudr register. tdi 139 b8 schmitt input input, pulled high internally test data input ? this input pin provides a serial input data stream to the jtag/eonce port. it is sampled on the rising edge of tck and has an on-chip pull-up resistor. to deactivate the internal pull-up resistor, set the jtag bit in the sim_pudr register. tdo 140 d7 output in reset, output is disabled, pull-up is enabled test data output ? this tri-stateable output pin provides a serial output data stream from the jtag/eonce port. it is driven in the shift-ir and shift-dr controller states, and changes on the falling edge of tck. table 2-2 signal and package info rmation for the 160-pin lqfp and mbga signal name pin no. ball no. type state during reset signal description
signal pins 56f8367 technical data, rev. 7.0 freescale semiconductor 29 preliminary trst 136 d9 schmitt input input, pulled high internally test reset ? as an input, a low signal on this pin provides a reset signal to the jtag tap controller. to ensure complete hardware reset, trst should be asserted whenever reset is asserted. the only exception occu rs in a debugging environment when a hardware device reset is required and the jtag/eonce module must not be reset. in this case, assert reset , but do not assert trst . to deactivate the internal pull-up resistor, set the jtag bit in the sim_pudr register. phasea0 (ta0) (gpioc4) 155 a2 schmitt input schmitt input/ output schmitt input/ output input, pull-up enabled phase a ? quadrature decoder 0, phasea input ta0 ? timer a, channel 0 port c gpio ? this gpio pin can be individually programmed as an input or output pin. after reset, the defau lt state is phasea0. to deactivate the internal pull-up resistor, clear bit 4 of the gpioc_pur register. phaseb0 (ta1) (gpioc5) 156 b4 schmitt input schmitt input/ output schmitt input/ output input, pull-up enabled phase b ? quadrature decoder 0, phaseb input ta1 ? timer a, channel port c gpio ? this gpio pin can be individually programmed as an input or output pin. after reset, the defau lt state is phaseb0. to deactivate the internal pull-up resistor, clear bit 5 of the gpioc_pur register. table 2-2 signal and package info rmation for the 160-pin lqfp and mbga signal name pin no. ball no. type state during reset signal description
56f8367 technical data, rev. 7.0 30 freescale semiconductor preliminary index0 (ta2) (gpopc6) 157 a1 schmitt input schmitt input/ output schmitt input/ output input, pull-up enabled index ? quadrature decoder 0, index input ta2 ? timer a, channel 2 port c gpio ? this gpio pin can be individually programmed as an input or output pin. after reset, the defau lt state is index0. to deactivate the internal pull-up resistor, clear bit 6 of the gpioc_pur register. home0 (ta3) (gpioc7) 158 b3 schmitt input schmitt input/ output schmitt input/ output input, pull-up enabled home ? quadrature decoder 0, home input ta3 ? timer a, channel 3 port c gpio ? this gpio pin can be individually programmed as an input or output pin. after reset, the default state is home0. to deactivate the internal pull-up resistor, clear bit 7 of the gpioc_pur register. sclk0 (gpioe4) 146 a6 schmitt input/ output schmitt input/ output input, pull-up enabled spi 0 serial clock ? in the master mode, this pin serves as an output, clocking slaved listeners. in slave mode, this pin serves as the data clock input. port e gpio ? this gpio pin can be individually programmed as an input or output pin. after reset, the default state is sclk0. to deactivate the internal pull-up resistor, clear bit 4 in the gpioe_pur register. table 2-2 signal and package info rmation for the 160-pin lqfp and mbga signal name pin no. ball no. type state during reset signal description
signal pins 56f8367 technical data, rev. 7.0 freescale semiconductor 31 preliminary mosi0 (gpioe5) 148 b6 input/ output input/ output in reset, output is disabled, pull-up is enabled spi 0 master out/slave in ? this serial data pin is an output from a master device and an input to a slave device. the master device places data on the mosi lin e a half-cycle before the clock edge the slave device uses to latch the data. port e gpio ? this gpio pin can be individually programmed as an input or output pin. after reset, the defau lt state is mosi0. to deactivate the internal pull-up resistor, clear bit 5 in the gpioe_pur register. miso0 (gpioe6) 147 d4 input/ output input/ output input, pull-up enabled spi 0 master in/slave out ? this serial data pin is an input to a master device and an output from a slave device. the miso line of a slave device is placed in th e high-impedance state if the slave device is not selected. the slave device places data on the miso line a half-cycle before the clock edge the master device uses to latch the data. port e gpio ? this gpio pin can be individually programmed as an input or output pin. after reset, the defau lt state is miso0. to deactivate the internal pull-up resistor, clear bit 6 in the gpioe_pur register. ss0 (gpioe7) 145 d5 input input/ output input, pull-up enabled spi 0 slave selec t ? ss0 is used in slave mode to indicate to the spi module that the current transfer is to be received. port e gpio ? this gpio pin can be individually programmed as input or output pin. after reset, the default state is ss0 . to deactivate the internal pull-up resistor, clear bit 7 in the gpioe_pur register. table 2-2 signal and package info rmation for the 160-pin lqfp and mbga signal name pin no. ball no. type state during reset signal description
56f8367 technical data, rev. 7.0 32 freescale semiconductor preliminary phasea1 (tb0) (sclk1) (gpioc0) 6c1schmitt input schmitt input/ output schmitt input/ output schmitt input/ output input, pull-up enabled phase a1 ? quadrature decoder 1, phasea input for decoder 1. tb0 ? timer b, channel 0 spi 1 serial clock ? in the master mode, this pin serves as an output, clocking slaved listeners. in slave mode, this pin serves as the data clock input. to activate the spi function, set the phsa_alt bit in th e sim_gps register. for details, see part 6.5.8 . port c gpio ? this gpio pin can be individually programmed as an input or output pin. in the 56f8367, the default state after reset is phasea1. in the 56f8167, the default state is not one of the functions offered and must be reconfigured. to deactivate the internal pull-up resistor, clear bit 0 in the gpioc_pur register. phaseb1 (tb1) (mosi1) (gpioc1) 7d1schmitt input schmitt input/ output schmitt input/ output schmitt input/ output input, pull-up enabled phase b1 ? quadrature decoder 1, phaseb input for decoder 1. tb1 ? timer b, channel 1 spi 1 master out/slave in ? this serial data pin is an output from a master device and an input to a slave device. the master device places data on the mosi lin e a half-cycle before the clock edge the slave device uses to latch the data. to activate the spi function, set the phsb_alt bit in the sim_gps register. for details, see part 6.5.8 . port c gpio ? this gpio pin can be individually programmed as an input or output pin. in the 56f8367, the default state after reset is phaseb1. in the 56f8167, the default state is not one of the functions offered and must be reconfigured. to deactivate the internal pull-up resistor, clear bit 1 in the gpioc_pur register. table 2-2 signal and package info rmation for the 160-pin lqfp and mbga signal name pin no. ball no. type state during reset signal description
signal pins 56f8367 technical data, rev. 7.0 freescale semiconductor 33 preliminary index1 (tb2) (miso1) (gpioc2) 8e2schmitt input schmitt input/ output schmitt input/ output schmitt input/ output input, pull-up enabled index1 ? quadrature deco der 1, index input tb2 ? timer b, channel 2 spi 1 master in/slave out ? this serial data pin is an input to a master device and an output from a slave device. the miso line of a slave device is placed in th e high-impedance state if the slave device is not selected. the slave device places data on the miso line a half-cycle before the clock edge the master device uses to latch the data. to activate the spi function, set the index_alt bit in the sim_gps register. for details, see part 6.5.8 . port c gpio ? this gpio pin can be individually programmed as an input or output pin. in the 56f8367, the default state after reset is index1. in the 56f8167, the default state is not one of the functions offered and must be reconfigured. to deactivate the internal pull-up resistor, clear bit 2 in the gpioc_pur register. home1 (tb3) (ss1 ) (gpioc3) 9e1schmitt input schmitt input/ output schmitt input schmitt input/ output input, pull-up enabled home ? quadrature decoder 1, home input tb3 ? timer b, channel 3 spi 1 slave select ? in the master mode, this pin is used to arbitrate multiple masters. in slave mode, this pin is used to select the slave. to activate the spi fu nction, set the home_alt bit in the sim_gps register. for details, see part 6.5.8 . port c gpio ? this gpio pin can be individually programmed as an input or output pin. in the 56f8367, the default state after reset is home1. in the 56f8167, the default state is not one of the functions offered and must be reconfigured. to deactivate the internal pull-up resistor, clear bit 3 in the gpioc_pur register. table 2-2 signal and package info rmation for the 160-pin lqfp and mbga signal name pin no. ball no. type state during reset signal description
56f8367 technical data, rev. 7.0 34 freescale semiconductor preliminary pwma0 73 m11 output in reset, output is disabled, pull-up is enabled pwma0 - 5 ? these are six pwma outputs. pwma1 75 p12 pwma2 76 n11 pwma3 78 m12 pwma4 79 p13 pwma5 81 n12 isa0 (gpioc8) 126 a11 schmitt input schmitt input/ output input, pull-up enabled isa0 - 2 ? these three input current status pins are used for top/bottom pulse width correction in complementary channel operation for pwma. port c gpio ? these gpio pins can be individually programmed as input or output pins. in the 56f8367, these pins default to isa functionality after reset. in the 56f8167, the default state is not one of the functions offered and must be reconfigured. to deactivate the internal pull-up resistor, clear the appropriate bit of the gpioc_pur register. for details, see part 6.5.8 . isa1 (gpioc9) 127 c11 isa2 (gpioc10) 128 d11 faulta0 82 n13 schmitt input input, pull-up enabled faulta0 - 2 ? these three fault input pins are used for disabling selected pwma outputs in cases where fault conditions originate off-chip. to deactivate the internal pull-up resistor, set the pwma0 bit in the sim_pudr regist er. for details, see part 6.5.8 . faulta1 84 n14 faulta2 85 m13 faulta3 87 m14 schmitt input input, pull-up enabled faulta3 ? this fault input pin is used for disabling selected pwma outputs in cases where faul t conditions originate off-chip. to deactivate the internal pull-up resistor, set the pwma1 bit in the sim_pudr register. see part 6.5.6 for details. pwmb0 38 n1 output in reset, output is disabled, pull-up is enabled pwmb0 - 5 ? six pwmb output pins. pwmb1 39 p1 pwmb2 40 n2 pwmb3 43 n3 pwmb4 44 p2 pwmb5 45 m3 table 2-2 signal and package info rmation for the 160-pin lqfp and mbga signal name pin no. ball no. type state during reset signal description
signal pins 56f8367 technical data, rev. 7.0 freescale semiconductor 35 preliminary isb0 (gpiod10) 61 n8 schmitt input schmitt input/ output input, pull-up enabled isb0 - 2 ? these three input current status pins are used for top/bottom pulse width correction in complementary channel operation for pwmb. port d gpio ? these gpio pins can be individually programmed as input or output pins. at reset, these pins default to isb functionality. to deactivate the internal pull-up resistor, clear the appropriate bit of the gpiod_pur register. for details, see part 6.5.8 . isb1 (gpiod11) 63 l8 isb2 (gpiod12) 64 p8 faultb0 67 n9 schmitt input input, pull-up enabled faultb0 - 3 ? these four fault input pins are used for disabling selected pwmb outputs in cases where fault conditions originate off-chip. to deactivate the internal pull-up resistor, set the pwmb bit in the sim_pudr register. for details, see part 6.5.8 . faultb1 68 l9 faultb2 69 l10 faultb3 72 p11 ana0 100 g13 input analog input ana0 - 3 ? analog inputs to adc a, channel 0 ana1 101 h13 ana2 102 g12 ana3 103 f13 ana4 104 f12 input analog input ana4 - 7 ? analog inputs to adc a, channel 1 ana5 105 h14 ana6 106 g14 ana7 107 e13 v refh 113 d14 input analog input v refh ? analog reference voltage high. v refh must be less than or equal to v dda_adc. v refp 112 d13 input/ output analog input/ output v refp , v refmid & v refn ? internal pins for voltage reference which are brought off-chip so t hey can be bypassed. connect to a 0.1 f low esr capacitor. v refmid 111 e14 v refn 110 f14 v reflo 109 e12 input analog input v reflo ? analog reference voltage low. this should normally be connected to a low-noise v ss . table 2-2 signal and package info rmation for the 160-pin lqfp and mbga signal name pin no. ball no. type state during reset signal description
56f8367 technical data, rev. 7.0 36 freescale semiconductor preliminary anb0 116 c13 input analog input anb0 - 3 ? analog inputs to adc b, channel 0 anb1 117 b14 anb2 118 c12 anb3 119 b13 anb4 120 a14 input analog input anb4 - 7 ? analog inputs to adc b, channel 1 anb5 121 a13 anb6 122 b12 anb7 123 a12 temp_ sense 108 e11 output analog output temperature sense diode ? this signal connects to an on-chip diode that can be connected to one of the adc inputs and used to monitor the temperature of the die. must be bypassed with a 0.01 f capacitor. can_rx 143 b7 schmitt input input, pull-up enabled flexcan receive data ? this is the can input. this pin has an internal pull-up resistor. to deactivate the internal pull-up resistor, set the can bit in the sim_pudr register. can_tx 142 d6 open drain output open drain output flexcan transmit data ? can output with internal pull-up enable at reset.* * note : if a pin is configured as ope n drain output mode, internal pull-up will automatically be disabled when it outputs low. internal pull-up will be enabled unless it has been manually disabled by clearing the corresponding bit in the puren register of the gpio module, when it outputs high. if a pin is configured as push-pu ll output mode, internal pull-up will automatically be disabled, whether it outputs low or high. tc0 (gpioe8) 133 a9 schmitt input/ output schmitt input/ output input, pull-up enabled tc0 ? timer c, channel 0 and 1 port e gpio ? these gpio pins can be individually programmed as input or output pins. at reset, these pins default to timer functionality. to deactivate the internal pull-up resistor, clear the appropriate bit of the gpioe_pur register. tc1 (gpioe9) 135 b9 table 2-2 signal and package info rmation for the 160-pin lqfp and mbga signal name pin no. ball no. type state during reset signal description
signal pins 56f8367 technical data, rev. 7.0 freescale semiconductor 37 preliminary td0 (gpioe10) 129 b10 schmitt input/ output schmitt input/ output input, pull-up enabled td0 - 3 ? timer d, channels 0, 1, 2 and 3 port e gpio ? these gpio pins can be individually programmed as input or output pins. at reset, these pins default to timer functionality. to deactivate the internal pull-up resistor, clear the appropriate bit of the gpioe_pur register. see part 6.5.6 for details. td1 (gpioe11) 130 a10 td2 (gpioe12) 131 d10 td3 (gpioe13) 132 e10 irqa 65 k9 schmitt input input, pull-up enabled external interrupt request a and b ? the irqa and irqb inputs are asynchronous external interrupt requests during stop and wait mode operation. during other operating modes, they are synchronized external interrupt requests, which indicate an external device is requesting serv ice. they can be programmed to be level-sensitive or negative-edge triggered. to deactivate the internal pull-up resistor, set the irq bit in the sim_pudr register. see part 6.5.6 for details. irqb 66 p9 reset 98 j14 schmitt input input, pull-up enabled reset ? this input is a direct hardware reset on the processor. when reset is asserted low, the device is initialized and placed in the reset state. a schmitt trigger input is used for noise immunity. when the reset pin is deasserted, the initial chip operating mode is latched from the extboot pin. the internal reset signal will be deasserted synchronous with the internal clocks after a fixed numbe r of internal clocks. to ensure complete hardware reset, reset and trst should be asserted together. the only exception occurs in a debugging environment when a hardware device reset is required and the jtag/eonce module must not be reset. in this case, assert reset but do not assert trst . note: the internal power-on reset will assert on initial power-up. to deactivate the internal pull-up resistor, set the reset bit in the sim_pudr register. see part 6.5.6 for details. rsto 97 j13 output output reset output ? this output reflects the internal reset state of the chip. table 2-2 signal and package info rmation for the 160-pin lqfp and mbga signal name pin no. ball no. type state during reset signal description
56f8367 technical data, rev. 7.0 38 freescale semiconductor preliminary extboot 124 b11 schmitt input input, pull-up enabled external boot ? this input is tied to v dd to force the device to boot from off-chip memory (assuming that the on-chip flash memory is not in a secure state). otherwise, it is tied to ground. for details, see table 4-4 . note: when this pin is tied low, the customer boot software should disable the internal pull-up resistor by setting the xboot bit of the sim_pudr; see part 6.5.6 . emi_mode 159 b2 schmitt input input, pull-up enabled external memory mode ? this input is tied to v dd in order to enable an extra four address lines, for a total of 20 address lines out of reset. this function is also affected by extboot and the flash security mode. for details, see table 4-4 . if a 20-bit address bus is not desired, then this pin is tied to ground. note: when this pin is tied low, the customer boot software should disable the internal pull-up resistor by setting the emi_mode bit of the sim_pudr; see part 6.5.6 . table 2-2 signal and package info rmation for the 160-pin lqfp and mbga signal name pin no. ball no. type state during reset signal description
introduction 56f8367 technical data, rev. 7.0 freescale semiconductor 39 preliminary part 3 on-chip clock synthesis (occs) 3.1 introduction refer to the occs chapter of the 56f8300 peripheral user manual for a full description of the occs. the material contained here identifies th e specific features of the occs design. figure 3-1 shows the specific occs block diagram to refe rence in the occs chapter of the 56f8300 peripheral user manual . figure 3-1 occs block diagram 3.2 external clock operation the system clock can be derived from an external cr ystal, ceramic resonator, or an external system clock signal. to generate a reference fr equency using the internal oscillato r, a reference cr ystal or ceramic resonator must be connected be tween the extal and xtal pins. 3.2.1 crystal oscillator the internal oscillator is also designed to interfac e with a parallel-resonant crystal resonator in the frequency range specified fo r the external crystal in table 10-13 . a recommended crystal oscillator circuit is shown in figure 3-2 . follow the crystal supplier?s recommenda tions when selecti ng a crystal, since crystal parameters determine the component values required to provide maximu m stability and reliable mux extal xtal feedback lck prescaler clk postscaler clk f out/2 crystal osc loss of reference clock detector lock detector zsrc bus interface & control f out f ref plldb pllcod pllcid bus interface loss of reference clock interrupt sys_clk2 source to sim mux clkmode 2 prescaler ( 1,2,4,8 ) postscaler ( 1,2,4,8 ) mstr_osc pll x (1 to 128)
56f8367 technical data, rev. 7.0 40 freescale semiconductor preliminary start-up. the crystal and associated components should be mounted as ne ar as possible to the extal and xtal pins to minimize output dist ortion and start-up stabilization time. figure 3-2 connecting to a crystal oscillator note: the occs_cohl bit must be set to 1 when a crys tal oscillator is used. the reset condition on the occs_cohl bit is 0. please see the cohl bit in the oscillator co ntrol (osctl) register, discussed in the 56f8300 peripheral user manual . 3.2.2 ceramic resonator (default) it is also possible to drive the in ternal oscillator with a ceramic re sonator, assuming the overall system design can tolerate the reduced signal integrity. a typical ceramic resonato r circuit is shown in figure 3-3 . refer to the supplier?s recommendations when select ing a ceramic resonator a nd associated components. the resonator and components should be mounted as near as possible to th e extal and xtal pins. figure 3-3 connecting a ceramic resonator note: the occs_cohl bit must be set to 0 when a cera mic resonator is used. th e reset condition on the occs_cohl bit is 0. please see the cohl bit in the oscillator co ntrol (osctl) register, discussed in the 56f8300 peripheral user manual . 3.2.3 external clock source the recommended method of connecting an external clock is given in figure 3-4 . the external clock source is connected to xt al and the extal pin is grounded. when using an external clock source, set r z r z sample external crystal parameters: r z = 750 k ? note: if the operating temperature range is limited to below 85 o c (105 o c junction), then r z = 10 meg ? clkmode = 0 crystal frequency = 4 - 8mhz (optimized for 8mhz) extal extal xtal xtal cl1 cl2 sample external ceramic resonator parameters: r z = 750 k ? resonator frequency = 4 - 8mhz (optimized for 8mhz) 3 terminal 2 terminal clkmode = 0 cl1 cl2 c1 c2 extal xtal extal xtal r z r z
registers 56f8367 technical data, rev. 7.0 freescale semiconductor 41 preliminary the occs_cohl bit high as well. figure 3-4 connecting an ex ternal clock register 3.3 registers when referring to the register definitions for the occs in the 56f8300 peripheral user manual , use the register definitions without the internal relaxation oscillat or, since the 56 f8367/56f8167 do not contain this oscillator. part 4 memory operating modes (mem) 4.1 introduction the 56f8367 and 56f8167 devices are 16- bit motor-control chips based on the 56800e core. these parts use a harvard-style architecture wi th two independent memory spaces for data and program. on-chip ram and flash memory are used in both spaces. this chapter provides memory maps for: ? program address space including the interrupt vector table ? data address space including the eonce memory and peripheral memory maps on-chip memory sizes for each device are summarized in table 4-1 . flash memories? restrictions are identified in the ?use restrictions? column of table 4-1 . note: data flash and program ram are not available on the 56f8167 device. table 4-1 chip memo ry configurations on-chip memory 56f8367 56f8167 use restrictions program flash 512kb 512kb erase/program via fl ash interface unit and word writes to cdbw data flash 32kb ? erase/program via flash interf ace unit and word writes to cdbw. data flash can be read via one of cdbr or xdb2, but not both simultaneously program ram 4kb ? none data ram 32kb 32kb none program boot flash 32kb 32kb erase/program via flash interface unit and word to cdwb xtal extal external v ss clock note: when using an external clocking source with this configuration, the in put ?clkmode? should be high and the cohl bit in the osctl register should be set to 1.
56f8367 technical data, rev. 7.0 42 freescale semiconductor preliminary 4.2 program map the operating mode control bits (ma and mb) in the operating mode register (omr) control the program memory map. at reset, thes e bits are set as indicated in table 4-2 . table 4-4 shows the memory map configurations that are possibl e at reset. after reset, the omr ma bit can be ch anged and will have an effect on the p-space memory map, as shown in table 4-3 . changing the omr mb bit will have no effect. the device?s external memory interface (emi) can ope rate much like the 56f80x fa mily?s emi, or it can be operated in a mode si milar to that used on other products in the 56800 e family. initially, cs0 and cs1 are configured as ps and ds , in a mode compatible with earlier 56800 devices. eighteen address lin es are required to shadow the first 192k of internal program space when booting externally for development purposes . therefore, the entire compleme nt of on-chip memory cannot be accessed using a 16-bit 56800-co mpatible address bus. to address th is situation, the emi_mode pin can be used to configure four gpio pins as address[19:16] upon reset (sof tware reconfiguration of the highest address lines [a20-23] is required if th e full address range is to be used.) the emi_mode bit also affects the re set vector address, as provided in table 4-4 . additional pins must be configured as address or chip select si gnals to access addresse s at p: $10 0000 and above. note: program ram is not avail able on the 56f8167 device. table 4-2 omr mb/ma value at reset omr mb = flash secured state 1, 2 1. this bit is only configured at reset. if the flash secured state changes, this will not be reflected in mb until the next res et. 2. changing mb in software will not affect flash memory security. omr ma = extboot pin chip operating mode 00 mode 0 ? internal boot; emi is configured to use 16 address lines; flash memory is secured; external p-space is not allowed; the eonce is disabled 01 not valid; cannot boot externally if the flas h is secured and will actually configure to 00 state 10 mode 0 ? internal boot; emi is configured to use 16 address lines 11 mode 1 ? external boot; flash memory is not secured; emi configuration is determined by the state of the emi_mode pin table 4-3 changing omr ma va lue during normal operation omr ma chip operating mode 0 use internal p-space memory map configuration 1 use external p-space memory map conf iguration ? if mb = 0 at reset, changing this bit has no effect.
interrupt vector table 56f8367 technical data, rev. 7.0 freescale semiconductor 43 preliminary 4.3 interrupt vector table table 4-5 provides the reset and interrupt priority structure, including on- chip peripherals. the table is organized with higher-priority vect ors at the top and lower-priority interrupts lower in the table. the priority of an interrupt can be assigned to different levels, as indicated, allowing some control over interrupt priorities. all le vel 3 interrupts will be serviced before level 2, and so on. for a selected priority level, the lowest vector num ber has the highest priority. table 4-4 program memory map at reset begin/end address mode 0 (ma = 0) mode 1 1 (ma = 1) 1. if flash security mode is enabled, extboot mode 1 cannot be used. see security features, part 7 . internal boot external boot internal boot 16-bit external address bus emi_mode = 0 2 , 3 16-bit external address bus 2. this mode provides maximum compatibility with 56f80x parts while operating externally. 3. ?emi_mode = 0? when emi_mode pin is tied to ground at boot up. emi_mode = 1 4 20-bit external address bus 4. ?emi_mode = 1? when emi_mode pin is tied to v dd at boot up. p:$1f ffff p:$10 0000 external program memory 5 5. not accessible in reset configuration, since the address is above p:$00 ffff. the higher bit address/gpio (and/or chip selects) pins must be reconfigured before this external memory is accessible. external program memory 5 external program memory 6 6. not accessible in reset configuration, since the address is above p:$0f ffff. the higher bit address/gpio (and/or chip selects) pins must be reconfigured before this external memory is accessible. p:$0f ffff p:$05 0000 external program memory cop reset address = 04 0002 7 boot location = 04 0000 7 7. booting from this external address allows prototyping of the internal boot flash. p:$04 ffff p:$04 f800 on-chip program ram 4kb p:$04 f7ff p:$04 4000 reserved 92kb p:$04 3fff p:$04 0000 boot flash 32kb cop reset address = 04 0002 boot location = 04 0000 boot flash 32kb (not used for boot in this mode) p:$03 ffff p:$02 0000 internal program flash 8 256kb internal program flash 256kb p:$01 ffff p:$01 0000 internal program flash 8 256kb 8. two independent program flash blocks allow one to be programmed/erased while executing from another. each block must have its own mass erase. internal program flash 128kb p:$00 ffff p:$00 0000 external program memory cop reset address = 00 0002 boot location = 00 0000
56f8367 technical data, rev. 7.0 44 freescale semiconductor preliminary the location of the vector table is determined by the vector base address (vba) register. please see part 5.6.11 for the reset value of the vba. in some configurations, the reset a ddress and cop reset address will co rrespond to vector 0 and 1 of the interrupt vector table. in these instances, the first tw o locations in the vector ta ble must contain branch or jmp instructions. all other entries must contain jsr instructions. note: pwma, flexcan, quadrature decoder 1, and q uad timers b and d are not available on the 56f8167 device. table 4-5 interrupt v ector table contents 1 peripheral vector number priority level vector base address + interrupt function reserved for reset overlay 2 reserved for cop reset overlay 2 core 2 3 p:$04 illegal instruction core 3 3 p:$06 sw interrupt 3 core 4 3 p:$08 hw stack overflow core 5 3 p:$0a misaligned long word access core 6 1-3 p:$0c once step counter core 7 1-3 p:$0e once breakpoint unit 0 reserved core 9 1-3 p:$12 once trace buffer core 10 1-3 p:$14 once transmit register empty core 11 1-3 p:$16 once receive register full reserved core 14 2 p:$1c sw interrupt 2 core 15 1 p:$1e sw interrupt 1 core 16 0 p:$20 sw interrupt 0 core 17 0-2 p:$22 irqa core 18 0-2 p:$24 irqb reserved lvi 20 0-2 p:$28 low-voltage detector (power sense) pll 21 0-2 p:$2a pll fm 22 0-2 p:$2c fm access error interrupt fm 23 0-2 p:$2e fm command complete fm 24 0-2 p:$30 fm command, data and address buffers empty reserved
interrupt vector table 56f8367 technical data, rev. 7.0 freescale semiconductor 45 preliminary flexcan 26 0-2 p:$34 flexcan bus off flexcan 27 0-2 p:$36 flexcan error flexcan 28 0-2 p:$38 flexcan wake up flexcan 29 0-2 p:$3a flexcan message buffer interrupt gpiof 30 0-2 p:$3c gpio f gpioe 31 0-2 p:$3e gpio e gpiod 32 0-2 p:$40 gpio d gpioc 33 0-2 p:$42 gpio c gpiob 34 0-2 p:$44 gpio b gpioa 35 0-2 p:$46 gpio a reserved spi1 38 0-2 p:$4c spi 1 receiver full spi1 39 0-2 p:$4e spi 1 transmitter empty spi0 40 0-2 p:$50 spi 0 receiver full spi0 41 0-2 p:$52 spi 0 transmitter empty sci1 42 0-2 p:$54 sci 1 transmitter empty sci1 43 0-2 p:$56 sci 1 transmitter idle reserved sci1 45 0-2 p:$5a sci 1 receiver error sci1 46 0-2 p:$5c sci 1 receiver full dec1 47 0-2 p:$5e quadrature decoder #1 home switch or watchdog dec1 48 0-2 p:$60 quadrature decoder #1 index pulse dec0 49 0-2 p:$62 quadrature decoder #0 home switch or watchdog dec0 50 0-2 p:$64 quadrature decoder #0 index pulse reserved tmrd 52 0-2 p:$68 timer d, channel 0 tmrd 53 0-2 p:$6a timer d, channel 1 tmrd 54 0-2 p:$6c timer d, channel 2 tmrd 55 0-2 p:$6e timer d, channel 3 tmrc 56 0-2 p:$70 timer c, channel 0 tmrc 57 0-2 p:$72 timer c, channel 1 tmrc 58 0-2 p:$74 timer c, channel 2 tmrc 59 0-2 p:$76 timer c, channel 3 table 4-5 interrupt vector table contents 1 (continued) peripheral vector number priority level vector base address + interrupt function
56f8367 technical data, rev. 7.0 46 freescale semiconductor preliminary tmrb 60 0-2 p:$78 timer b, channel 0 tmrb 61 0-2 p:$7a timer b, channel 1 tmrb 62 0-2 p:$7c timer b, channel 2 tmrb 63 0-2 p:$7e timer b, channel 3 tmra 64 0-2 p:$80 timer a, channel 0 tmra 65 0-2 p:$82 timer a, channel 1 tmra 66 0-2 p:$84 timer a, channel 2 tmra 67 0-2 p:$86 timer a, channel 3 sci0 68 0-2 p:$88 sci 0 transmitter empty sci0 69 0-2 p:$8a sci 0 transmitter idle reserved sci0 71 0-2 p:$8e sci 0 receiver error sci0 72 0-2 p:$90 sci 0 receiver full adcb 73 0-2 p:$92 adc b conversion compete / end of scan adca 74 0-2 p:$94 adc a conversion complete / end of scan adcb 75 0-2 p:$96 adc b zero crossing or limit error adca 76 0-2 p:$98 adc a zero crossing or limit error pwmb 77 0-2 p:$9a reload pwm b pwma 78 0-2 p:$9c reload pwm a pwmb 79 0-2 p:$9e pwm b fault pwma 80 0-2 p:$a0 pwm a fault core 81 - 1 p:$a2 sw interrupt lp flexcan2 82 0-2 p:$a4 flexcan bus off flexcan2 83 0-2 p:$a6 flexcan error flexcan2 84 0-2 p:$a8 flexcan wake up flexcan2 85 0-2 p:$aa flexcan message buffer interrupt 1. two words are allocated for each entry in the vector table. this does not allow the full address range to be referenced from the vector table, providing only 19 bits of address. 2. if the vba is set to $0200 (or vba = 0000 for mode 1, emi_mode = 0), the first two locations of the vector table are the chi p reset addresses; therefore, these locations are not interrupt vectors. 2. table 4-5 interrupt vector table contents 1 (continued) peripheral vector number priority level vector base address + interrupt function
data map 56f8367 technical data, rev. 7.0 freescale semiconductor 47 preliminary 4.4 data map note: data flash is not available on the 56f8167 device. 4.5 flash memory map figure 4-1 illustrates the flash memory (fm) map on the system bus. the flash memory is divided into three functional blocks. the program and boot memories reside on the program memory buses. they are c ontrolled by one set of ba nked registers. data memory flash resides on the data memory buses and is controlled separately by its own se t of banked registers. the top nine words of the program memory flash are treated as special memory locations. the content of these words is used to control the operation of the flash c ontroller. because these words are part of the flash memory content, their state is maintained dur ing power down and reset. during chip initialization, the content of these memory locations is loaded into flash memory contro l registers, detailed in the flash memory chapter of the 56f8300 peripheral user manual . these configuration parameters are located between $03_fff7 and $03_ffff. table 4-6 data memory map 1 1. all addresses are 16-bit word addresses, not byte addresses. begin/end address ex = 0 2 2. in the operating mode register (omr). ex = 1 x:$ff ffff x:$ff ff00 eonce 256 locations allocated eonce 256 locations allocated x:$ff feff x:$01 0000 external memory external memory x:$00 ffff x:$00 f000 on-chip peripherals 4096 locations allocated on-chip peripherals 4096 locations allocated x:$00 efff x:$00 8000 external memory external memory x:$00 7fff x:$00 4000 on-chip data flash 32kb x:$00 3fff x:$00 0000 on-chip data ram 32kb 3 3. the data ram is organized as an 8k x 32-bit memo ry to allow single-cycle, long-word operations.
56f8367 technical data, rev. 7.0 48 freescale semiconductor preliminary figure 4-1 flash array memory maps table 4-7 shows the page and sector sizes used wi thin each flash memory block on the chip. note: data flash is not available on the 56f8167 device. please see 56f8300 peripheral user manual for additional flash information. table 4-7 flash me mory partitions flash size sectors sec tor size page size program flash 512kb 16 16k x 16 bits 1024 x 16 bits data flash 32kb 16 1024 x 16 bits 256 x 16 bits boot flash 32kb 4 4k x 16 bits 512 x 16 bits data memory data_flash_start + $3fff data_flash_start + $0000 fm_base + $14 fm_base + $00 boot_flash_start + $3fff boot_flash_start = $04_0000 fm_prog_mem_top = $01_ffff block 0 odd (2 bytes) $00_0003 block 0 even (2 bytes) $00_0002 block 0 odd (2 bytes) $00_0001 block 0 even (2 bytes) $00_0000 block 1 odd (2 bytes) $02_0003 block 1 even (2 bytes) $02_0002 block 1 odd (2 bytes) $02_0001 block 1 even (2 bytes) $02_0000 program memory 32kb boot 256kb program configure field 256kb program banked registers unbanked registers 32kb prog_flash_start + $03_ffff prog_flash_start + $02_0000 prog_flash_start + $01_ffff prog_flash_start = $00_0000 note: data flash is not available in the 56f8167 device.
eonce memory map 56f8367 technical data, rev. 7.0 freescale semiconductor 49 preliminary 4.6 eonce memory map 4.7 peripheral memory mapped registers on-chip peripheral registers are pa rt of the data memory map on th e 56800e series. these locations may be accessed with the same addressing modes used for ordinary data memory, except all peripheral registers should be read/writt en using word accesses only. table 4-8 eonce memory map address register acronym register name reserved x:$ff ff8a oescr external signal control register reserved x:$ff ff8e obcntr breakpoint unit [0] counter reserved x:$ff ff90 obmsk (32 bits) breakpoint 1 unit [0] mask register x:$ff ff91 ? breakpoint 1 unit [0] mask register x:$ff ff92 obar2 (32 bits) breakpoint 2 unit [0] address register x:$ff ff93 ? breakpoint 2 unit [0] address register x:$ff ff94 obar1 (24 bits) breakpoint 1 unit [0] address register x:$ff ff95 ? breakpoint 1 unit [0] address register x:$ff ff96 obcr (24 bits) breakpoint unit [0] control register x:$ff ff97 ? breakpoint unit [0] control register x:$ff ff98 otb (21-24 bits/stage) trace buffer register stages x:$ff ff99 ? trace buffer register stages x:$ff ff9a otbpr (8 bits) trace buffer pointer register x:$ff ff9b otbcr trace buffer control register x:$ff ff9c obase (8 bits) peripheral base address register x:$ff ff9d osr status register x:$ff ff9e oscntr (24 bits) instruction step counter x:$ff ff9f ? instruction step counter :x:$ff ffa0 ocr (bits) control register reserved x:$ff fffc oclsr (8 bits) core lock / unlock status register x:$ff fffd otxrxsr (8 bits) transmit and receive status and control register x:$ff fffe otx / orx (32 bits) transmit register / receive register x:$ff ffff otx1 / orx1 transmit register upper word receive register upper word
56f8367 technical data, rev. 7.0 50 freescale semiconductor preliminary table 4-9 summarizes base addresses for the set of peripherals on the 56f8367 and 56f8167 devices. peripherals are listed in order of the base address. the following tables list all of the peripheral registers requi red to control or access the peripherals. note: features in italics are not available on the 56f8167 device. table 4-9 data memory periph eral base address map summary peripheral prefix base address table number external memory interface emi x:$00 f020 4-10 timer a tmra x:$00 f040 4-11 timer b tmrb x:$00 f080 4-12 timer c tmrc x:$00 f0c0 4-13 timer d tmrd x:$00 f100 4-14 pwm a pwma x:$00 f140 4-15 pwm b pwmb x:$00 f160 4-16 quadrature decoder 0 dec0 x:$00 f180 4-17 quadrature decoder 1 dec1 x:$00 f190 4-18 itcn itcn x:$00 f1a0 4-19 adc a adca x:$00 f200 4-20 adc b adcb x:$00 f240 4-21 temperature sensor tsensor x:$00 f270 4-22 sci #0 sci0 x:$00 f280 4-23 sci #1 sci1 x:$00 f290 4-24 spi #0 spi0 x:$00 f2a0 4-25 spi #1 spi1 x:$00 f2b0 4-26 cop cop x:$00 f2c0 4-27 pll, osc clkgen x:$00 f2d0 4-28 gpio port a gpioa x:$00 f2e0 4-29 gpio port b gpiob x:$00 f300 4-30 gpio port c gpioc x:$00 f310 4-31 gpio port d gpiod x:$00 f320 4-32 gpio port e gpioe x:$00 f330 4-33 gpio port f gpiof x:$00 f340 4-34 sim sim x:$00 f350 4-35
peripheral memory mapped registers 56f8367 technical data, rev. 7.0 freescale semiconductor 51 preliminary power supervisor lvi x:$00 f360 4-36 fm fm x:$00 f400 4-37 flexcan fc x:$00 f800 4-38 flexcan2 fc2 x:$00 fa00 4-39 table 4-10 external memory in tegration registers address map (emi_base = $00 f020) register acronym address offset register description reset value csbar 0 $0 chip select base address register 0 0x0004 = 64k when extboot = 0 or emi_mode = 0 0x0008 = 1m when emi_mode = 1 (selects entire program space for sc0) csbar 1 $1 chip select base address register 1 0x0004 = 64k when emi_mode = 0 0x0008 = 1m when emi_mode = 1 (selects a0 - 19 addressable data space for cs1) csbar 2 $2 chip select base address register 2 csbar 3 $3 chip select base address register 3 csbar 4 $4 chip select base address register 4 csbar 5 $5 chip select base address register 5 csbar 6 $6 chip select base address register 6 csbar 7 $7 chip select base address register 7 csor 0 $8 chip select option register 0 0x5fcb programmed for chip select for program space, word wide, read and write, 11 waits csor 1 $9 chip select option register 1 0x5 fab programmed for chip select for data space, word wide, read and write, 11 waits csor 2 $a chip select option register 2 csor 3 $b chip select option register 3 csor 4 $c chip select option register 4 csor 5 $d chip select option register 5 csor 6 $e chip select option register 6 csor 7 $f chip select option register 7 cstc 0 $10 chip select timing control register 0 cstc 1 $11 chip select timing control register 1 table 4-9 data memory peripheral base address map su mmary (continued) peripheral prefix base address table number
56f8367 technical data, rev. 7.0 52 freescale semiconductor preliminary cstc 2 $12 chip select timing control register 2 cstc 3 $13 chip select timing control register 3 cstc 4 $14 chip select timing control register 4 cstc 5 $15 chip select timing control register 5 cstc 6 $16 chip select timing control register 6 cstc 7 $17 chip select timing control register 7 bcr $18 bus control register 0x016b sets the default number of wait states to 11 for both read and write accesses table 4-11 quad timer a registers address map (tmra_base = $00 f040) register acronym address offset register description tmra0_cmp1 $0 compare register 1 tmra0_cmp2 $1 compare register 2 tmra0_cap $2 capture register tmra0_load $3 load register tmra0_hold $4 hold register tmra0_cntr $5 counter register tmra0_ctrl $6 control register tmra0_scr $7 status and control register tmra0_cmpld1 $8 comparator load register 1 tmra0_cmpld2 $9 comparator load register 2 tmra0_comscr $a comparator st atus and control register reserved tmra1_cmp1 $10 compare register 1 tmra1_cmp2 $11 compare register 2 tmra1_cap $12 capture register tmra1_load $13 load register tmra1_hold $14 hold register tmra1_cntr $15 counter register tmra1_ctrl $16 control register tmra1_scr $17 status and control register tmra1_cmpld1 $18 comparator load register 1 tmra1_cmpld2 $19 comparator load register 2 tmra1_comscr $1a comparator st atus and control register table 4-10 external memory integrat ion registers address map (continued) (emi_base = $00 f020) register acronym address offset register description reset value
peripheral memory mapped registers 56f8367 technical data, rev. 7.0 freescale semiconductor 53 preliminary reserved tmra2_cmp1 $20 compare register 1 tmra2_cmp2 $21 compare register 2 tmra2_cap $22 capture register tmra2_load $23 load register tmra2_hold $24 hold register tmra2_cntr $25 counter register tmra2_ctrl $26 control register tmra2_scr $27 status and control register tmra2_cmpld1 $28 comparator load register 1 tmra2_cmpld2 $29 comparator load register 2 tmra2_comscr $2a comparator st atus and control register reserved tmra3_cmp1 $30 compare register 1 tmra3_cmp2 $31 compare register 2 tmra3_cap $32 capture register tmra3_load $33 load register tmra3_hold $34 hold register tmra3_cntr $35 counter register tmra3_ctrl $36 control register tmra3_scr $37 status and control register tmra3_cmpld1 $38 comparator load register 1 tmra3_cmpld2 $39 comparator load register 2 tmra3_comscr $3a comparator st atus and control register table 4-12 quad timer b registers address map (tmrb_base = $00 f080) quad timer b is not avail able in the 56f8167 device register acronym address offset register description tmrb0_cmp1 $0 compare register 1 tmrb0_cmp2 $1 compare register 2 tmrb0_cap $2 capture register tmrb0_load $3 load register tmrb0_hold $4 hold register table 4-11 quad timer a regi sters address map (continued) (tmra_base = $00 f040) register acronym address offset register description
56f8367 technical data, rev. 7.0 54 freescale semiconductor preliminary tmrb0_cntr $5 counter register tmrb0_ctrl $6 control register tmrb0_scr $7 status and control register tmrb0_cmpld1 $8 comparat or load register 1 tmrb0_cmpld2 $9 comparat or load register 2 tmrb0_comscr $a comparator st atus and control register reserved tmrb1_cmp1 $10 compare register 1 tmrb1_cmp2 $11 compare register 2 tmrb1_cap $12 capture register tmrb1_load $13 load register tmrb1_hold $14 hold register tmrb1_cntr $15 counter register tmrb1_ctrl $16 control register tmrb1_scr $17 status and control register tmrb1_cmpld1 $18 comparator load register 1 tmrb1_cmpld2 $19 comparator load register 2 tmrb1_comscr $1a comparator st atus and control register reserved tmrb2_cmp1 $20 compare register 1 tmrb2_cmp2 $21 compare register 2 tmrb2_cap $22 capture register tmrb2_load $23 load register tmrb2_hold $24 hold register tmrb2_cntr $25 counter register tmrb2_ctrl $26 control register tmrb2_scr $27 status and control register tmrb2_cmpld1 $28 comparator load register 1 tmrb2_cmpld2 $29 comparator load register 2 tmrb2_comscr $2a comparator st atus and control register reserved tmrb3_cmp1 $30 compare register 1 tmrb3_cmp2 $31 compare register 2 tmrb3_cap $32 capture register table 4-12 quad timer b regi sters address map (continued) (tmrb_base = $00 f080) quad timer b is not avail able in the 56f8167 device register acronym address offset register description
peripheral memory mapped registers 56f8367 technical data, rev. 7.0 freescale semiconductor 55 preliminary tmrb3_load $33 load register tmrb3_hold $34 hold register tmrb3_cntr $35 counter register tmrb3_ctrl $36 control register tmrb3_scr $37 status and control register tmrb3_cmpld1 $38 comparator load register 1 tmrb3_cmpld2 $39 comparator load register 2 tmrb3_comscr $3a comparator st atus and control register table 4-13 quad timer c registers address map (tmrc_base = $00 f0c0) register acronym address o ffset register description tmrc0_cmp1 $0 compare register 1 tmrc0_cmp2 $1 compare register 2 tmrc0_cap $2 capture register tmrc0_load $3 load register tmrc0_hold $4 hold register tmrc0_cntr $5 counter register tmrc0_ctrl $6 control register tmrc0_scr $7 status and control register tmrc0_cmpld1 $8 comparator load register 1 tmrc0_cmpld2 $9 comparator load register 2 tmrc0_comscr $a comparator status and control register reserved tmrc1_cmp1 $10 compare register 1 tmrc1_cmp2 $11 compare register 2 tmrc1_cap $12 capture register tmrc1_load $13 load register tmrc1_hold $14 hold register tmrc1_cntr $15 counter register tmrc1_ctrl $16 control register tmrc1_scr $17 status and control register tmrc1_cmpld1 $18 comparator load register 1 table 4-12 quad timer b regi sters address map (continued) (tmrb_base = $00 f080) quad timer b is not avail able in the 56f8167 device register acronym address offset register description
56f8367 technical data, rev. 7.0 56 freescale semiconductor preliminary tmrc1_cmpld2 $19 comparator load register 2 tmrc1_comscr $1a comparator status and control register reserved tmrc2_cmp1 $20 compare register 1 tmrc2_cmp2 $21 compare register 2 tmrc2_cap $22 capture register tmrc2_load $23 load register tmrc2_hold $24 hold register tmrc2_cntr $25 counter register tmrc2_ctrl $26 control register tmrc2_scr $27 status and control register tmrc2_cmpld1 $28 comparator load register 1 tmrc2_cmpld2 $29 comparator load register 2 tmrc2_comscr $2a comparator status and control register reserved tmrc3_cmp1 $30 compare register 1 tmrc3_cmp2 $31 compare register 2 tmrc3_cap $32 capture register tmrc3_load $33 load register tmrc3_hold $34 hold register tmrc3_cntr $35 counter register tmrc3_ctrl $36 control register tmrc3_scr $37 status and control register tmrc3_cmpld1 $38 comparator load register 1 tmrc3_cmpld2 $39 comparator load register 2 tmrc3_comscr $3a comparator status and control register table 4-14 quad timer d registers address map (tmrd_base = $00 f100) quad timer d is not avail able in the 56f8167 device register acronym address o ffset register description tmrd0_cmp1 $0 compare register 1 tmrd0_cmp2 $1 compare register 2 tmrd0_cap $2 capture register table 4-13 quad timer c regi sters address map (continued) (tmrc_base = $00 f0c0) register acronym address o ffset register description
peripheral memory mapped registers 56f8367 technical data, rev. 7.0 freescale semiconductor 57 preliminary tmrd0_load $3 load register tmrd0_hold $4 hold register tmrd0_cntr $5 counter register tmrd0_ctrl $6 control register tmrd0_scr $7 status and control register tmrd0_cmpld1 $8 comparator load register 1 tmrd0_cmpld2 $9 comparator load register 2 tmrd0_comscr $a comparator status and control register reserved tmrd1_cmp1 $10 compare register 1 tmrd1_cmp2 $11 compare register 2 tmrd1_cap $12 capture register tmrd1_load $13 load register tmrd1_hold $14 hold register tmrd1_cntr $15 counter register tmrd1_ctrl $16 control register tmrd1_scr $17 status and control register tmrd1_cmpld1 $18 comparator load register 1 tmrd1_cmpld2 $19 comparator load register 2 tmrd1_comscr $1a comparator status and control register reserved tmrd2_cmp1 $20 compare register 1 tmrd2_cmp2 $21 compare register 2 tmrd2_cap $22 capture register tmrd2_load $23 load register tmrd2_hold $24 hold register tmrd2_cntr $25 counter register tmrd2_ctrl $26 control register tmrd2_scr $27 status and control register tmrd2_cmpld1 $28 comparator load register 1 tmrd2_cmpld2 $29 comparator load register 2 tmrd2_comscr $2a comparator status and control register reserved table 4-14 quad timer d regi sters address map (continued) (tmrd_base = $00 f100) quad timer d is not avail able in the 56f8167 device register acronym address o ffset register description
56f8367 technical data, rev. 7.0 58 freescale semiconductor preliminary tmrd3_cmp1 $30 compare register 1 tmrd3_cmp2 $31 compare register 2 tmrd3_cap $32 capture register tmrd3_load $33 load register tmrd3_hold $34 hold register tmrd3_cntr $35 counter register tmrd3_ctrl $36 control register tmrd3_scr $37 status and control register tmrd3_cmpld1 $38 comparator load register 1 tmrd3_cmpld2 $39 comparator load register 2 tmrd3_comscr $3a comparator status and control register table 4-15 pulse width modula tor a registers address map (pwma_base = $00 f140) pwma is not availabl e in the 56f8167 device register acronym address offset register description pwma_pmctl $0 control register pwma_pmfctl $1 fault control register pwma_pmfsa $2 fault status acknowledge register pwma_pmout $3 output control register pwma_pmcnt $4 counter register pwma_pwmcm $5 counter modulo register pwma_pwmval0 $6 value register 0 pwma_pwmval1 $7 value register 1 pwma_pwmval2 $8 value register 2 pwma_pwmval3 $9 value register 3 pwma_pwmval4 $a value register 4 pwma_pwmval5 $b value register 5 pwma_pmdeadtm $c dead time register pwma_pmdismap1 $d disable mapping register 1 pwma_pmdismap2 $e disable mapping register 2 pwma_pmcfg $f configure register pwma_pmccr $10 channel control register table 4-14 quad timer d regi sters address map (continued) (tmrd_base = $00 f100) quad timer d is not avail able in the 56f8167 device register acronym address o ffset register description
peripheral memory mapped registers 56f8367 technical data, rev. 7.0 freescale semiconductor 59 preliminary pwma_pmport $11 port register pwma_pmiccr $12 pwm internal correction control register table 4-16 pulse width modula tor b registers address map (pwmb_base = $00 f160) register acronym address o ffset register description pwmb_pmctl $0 control register pwmb_pmfctl $1 fault control register pwmb_pmfsa $2 fault status acknowledge register pwmb_pmout $3 output control register pwmb_pmcnt $4 counter register pwmb_pwmcm $5 counter modulo register pwmb_pwmval0 $6 value register 0 pwmb_pwmval1 $7 value register 1 pwmb_pwmval2 $8 value register 2 pwmb_pwmval3 $9 value register 3 pwmb_pwmval4 $a value register 4 pwmb_pwmval5 $b value register 5 pwmb_pmdeadtm $c dead time register pwmb_pmdismap1 $d disable mapping register 1 pwmb_pmdismap2 $e disable mapping register 2 pwmb_pmcfg $f configure register pwmb_pmccr $10 channel control register pwmb_pmport $11 port register pwmb_pmiccr $12 pwm internal correction control register table 4-17 quadrature decode r 0 registers address map (dec0_base = $00 f180) register acronym address o ffset register description dec0_deccr $0 decoder control register dec0_fir $1 filter interval register dec0_wtr $2 watchdog time-out register dec0_posd $3 position diff erence counter register dec0_posdh $4 position differ ence counter hold register table 4-15 pulse width modulator a registers address map (continued) (pwma_base = $00 f140) pwma is not availabl e in the 56f8167 device register acronym address offset register description
56f8367 technical data, rev. 7.0 60 freescale semiconductor preliminary dec0_rev $5 revolution counter register dec0_revh $6 revolution hold register dec0_upos $7 upper position counter register dec0_lpos $8 lower position counter register dec0_uposh $9 upper position hold register dec0_lposh $a lower position hold register dec0_uir $b upper initialization register dec0_lir $c lower initialization register dec0_imr $d input monitor register table 4-18 quadrature decode r 1 registers address map (dec1_base = $00 f190) quadrature decoder 1 is not available in the 56f8167 device register acronym address offset register description dec1_deccr $0 decoder control register dec1_fir $1 filter interval register dec1_wtr $2 watchdog time-out register dec1_posd $3 position difference counter register dec1_posdh $4 position difference counter hold register dec1_rev $5 revolution counter register dec1_revh $6 revolution hold register dec1_upos $7 upper position counter register dec1_lpos $8 lower position counter register dec1_uposh $9 upper position hold register dec1_lposh $a lower position hold register dec1_uir $b upper initialization register dec1_lir $c lower initialization register dec1_imr $d input monitor register table 4-17 quadrature decoder 0 registers address map (continued) (dec0_base = $00 f180) register acronym address o ffset register description
peripheral memory mapped registers 56f8367 technical data, rev. 7.0 freescale semiconductor 61 preliminary table 4-19 interrupt contro l registers address map (itcn_base = $00 f1a0) register acronym address offset register description ipr 0 $0 interrupt priority register 0 ipr 1 $1 interrupt priority register 1 ipr 2 $2 interrupt priority register 2 ipr 3 $3 interrupt priority register 3 ipr 4 $4 interrupt priority register 4 ipr 5 $5 interrupt priority register 5 ipr 6 $6 interrupt priority register 6 ipr 7 $7 interrupt priority register 7 ipr 8 $8 interrupt priority register 8 ipr 9 $9 interrupt priority register 9 vba $a vector base address register fim0 $b fast interrupt match register 0 fival0 $c fast interrupt vector address low 0 register fivah0 $d fast interrupt vector address high 0 register fim1 $e fast interrupt match register 1 fival1 $f fast interrupt vector address low 1 register fivah1 $10 fast interrupt vector address high 1 register irqp 0 $11 irq pending register 0 irqp 1 $12 irq pending register 1 irqp 2 $13 irq pending register 2 irqp 3 $14 irq pending register 3 irqp 4 $15 irq pending register 4 irqp 5 $16 irq pending register 5 reserved ictl $1d interrupt control register reserved ipr10 $1f interrupt priority register 10
56f8367 technical data, rev. 7.0 62 freescale semiconductor preliminary table 4-20 analog-to-digital c onverter registers address map (adca_base = $00 f200) register acronym address offset register description adca_cr 1 $0 control register 1 adca_cr 2 $1 control register 2 adca_zcc $2 zero crossing control register adca_lst 1 $3 channel list register 1 adca_lst 2 $4 channel list register 2 adca_sdis $5 sample disable register adca_stat $6 status register adca_lstat $7 limit status register adca_zcstat $8 zero crossing status register adca_rslt 0 $9 result register 0 adca_rslt 1 $a result register 1 adca_rslt 2 $b result register 2 adca_rslt 3 $c result register 3 adca_rslt 4 $d result register 4 adca_rslt 5 $e result register 5 adca_rslt 6 $f result register 6 adca_rslt 7 $10 result register 7 adca_llmt 0 $11 low limit register 0 adca_llmt 1 $12 low limit register 1 adca_llmt 2 $13 low limit register 2 adca_llmt 3 $14 low limit register 3 adca_llmt 4 $15 low limit register 4 adca_llmt 5 $16 low limit register 5 adca_llmt 6 $17 low limit register 6 adca_llmt 7 $18 low limit register 7 adca_hlmt 0 $19 high limit register 0 adca_hlmt 1 $1a high limit register 1 adca_hlmt 2 $1b high limit register 2 adca_hlmt 3 $1c high limit register 3 adca_hlmt 4 $1d high limit register 4 adca_hlmt 5 $1e high limit register 5 adca_hlmt 6 $1f high limit register 6 adca_hlmt 7 $20 high limit register 7
peripheral memory mapped registers 56f8367 technical data, rev. 7.0 freescale semiconductor 63 preliminary adca_ofs 0 $21 offset register 0 adca_ofs 1 $22 offset register 1 adca_ofs 2 $23 offset register 2 adca_ofs 3 $24 offset register 3 adca_ofs 4 $25 offset register 4 adca_ofs 5 $26 offset register 5 adca_ofs 6 $27 offset register 6 adca_ofs 7 $28 offset register 7 adca_power $29 power control register adca_cal $2a adc calibration register table 4-21 analog-to-digital c onverter registers address map (adcb_base = $00 f240) register acronym address offset register description adcb_cr 1 $0 control register 1 adcb_cr 2 $1 control register 2 adcb_zcc $2 zero crossing control register adcb_lst 1 $3 channel list register 1 adcb_lst 2 $4 channel list register 2 adcb_sdis $5 sample disable register adcb_stat $6 status register adcb_lstat $7 limit status register adcb_zcstat $8 zero crossing status register adcb_rslt 0 $9 result register 0 adcb_rslt 1 $a result register 1 adcb_rslt 2 $b result register 2 adcb_rslt 3 $c result register 3 adcb_rslt 4 $d result register 4 adcb_rslt 5 $e result register 5 adcb_rslt 6 $f result register 6 adcb_rslt 7 $10 result register 7 adcb_llmt 0 $11 low limit register 0 table 4-20 analog-to-digit al converter register s address map (continued) (adca_base = $00 f200) register acronym address offset register description
56f8367 technical data, rev. 7.0 64 freescale semiconductor preliminary adcb_llmt 1 $12 low limit register 1 adcb_llmt 2 $13 low limit register 2 adcb_llmt 3 $14 low limit register 3 adcb_llmt 4 $15 low limit register 4 adcb_llmt 5 $16 low limit register 5 adcb_llmt 6 $17 low limit register 6 adcb_llmt 7 $18 low limit register 7 adcb_hlmt 0 $19 high limit register 0 adcb_hlmt 1 $1a high limit register 1 adcb_hlmt 2 $1b high limit register 2 adcb_hlmt 3 $1c high limit register 3 adcb_hlmt 4 $1d high limit register 4 adcb_hlmt 5 $1e high limit register 5 adcb_hlmt 6 $1f high limit register 6 adcb_hlmt 7 $20 high limit register 7 adcb_ofs 0 $21 offset register 0 adcb_ofs 1 $22 offset register 1 adcb_ofs 2 $23 offset register 2 adcb_ofs 3 $24 offset register 3 adcb_ofs 4 $25 offset register 4 adcb_ofs 5 $26 offset register 5 adcb_ofs 6 $27 offset register 6 adcb_ofs 7 $28 offset register 7 adcb_power $29 power control register adcb_cal $2a adc calibration register table 4-22 temperature sens or register address map (tsensor_base = $00 f270) temperature sensor is not available in th e 56f8167 device register acronym address offset register description tsensor_cntl $0 control register table 4-21 analog-to-digit al converter register s address map (continued) (adcb_base = $00 f240) register acronym address offset register description
peripheral memory mapped registers 56f8367 technical data, rev. 7.0 freescale semiconductor 65 preliminary table 4-23 serial communication in terface 0 registers address map (sci0_base = $00 f280) register acronym address o ffset register description sci0_scibr $0 baud rate register sci0_scicr $1 control register reserved sci0_scisr $3 status register sci0_scidr $4 data register table 4-24 serial communication in terface 1 registers address map (sci1_base = $00 f290) register acronym address o ffset register description sci1_scibr $0 baud rate register sci1_scicr $1 control register reserved sci1_scisr $3 status register sci1_scidr $4 data register table 4-25 serial peripheral in terface 0 registers address map (spi0_base = $00 f2a0) register acronym address offset register description spi0_spscr $0 status and control register spi0_spdsr $1 data size register spi0_spdrr $2 data receive register spi0_spdtr $3 data transmitter register table 4-26 serial peripheral in terface 1 registers address map (spi1_base = $00 f2b0) register acronym address offset register description spi1_spscr $0 status and control register spi1_spdsr $1 data size register spi1_spdrr $2 data receive register spi1_spdtr $3 data transmitter register
56f8367 technical data, rev. 7.0 66 freescale semiconductor preliminary table 4-27 computer operating properly registers address map (cop_base = $00 f2c0) register acronym address offset register description copctl $0 control register copto $1 time out register copctr $2 counter register table 4-28 clock generation module registers address map (clkgen_base = $00 f2d0) register acronym address offset register description pllcr $0 control register plldb $1 divide-by register pllsr $2 status register reserved shutdown $4 shutdown register osctl $5 oscillator control register table 4-29 gpioa re gisters address map (gpioa_base = $00 f2e0) register acronym address offset register description reset value gpioa_pur $0 pull-up enable register 0 x 3fff gpioa_dr $1 data register 0 x 0000 gpioa_ddr $2 data direction register 0 x 0000 gpioa_per $3 peripheral enable register 0 x 3fff gpioa_iar $4 interrupt assert register 0 x 0000 gpioa_ienr $5 interrupt enable register 0 x 0000 gpioa_ipolr $6 interrupt polarity register 0 x 0000 gpioa_ipr $7 interrupt pending register 0 x 0000 gpioa_iesr $8 interrupt edge -sensitive register 0 x 0000 gpioa_ppmode $9 push-pull mode register 0 x 3fff gpioa_rawdata $a raw data input register ?
peripheral memory mapped registers 56f8367 technical data, rev. 7.0 freescale semiconductor 67 preliminary table 4-30 gpiob re gisters address map (gpiob_base = $00 f300) register acronym address offset register description reset value gpiob_pur $0 pull-up enable register 0 x 00ff gpiob_dr $1 data register 0 x 0000 gpiob_ddr $2 data direction register 0 x 0000 gpiob_per $3 peripheral enable register 0 x 000f for 20-bit emi address at reset. 0 x 0000 for all other cases. see table 4-4 for details. gpiob_iar $4 interrupt assert register 0 x 0000 gpiob_ienr $5 interrupt enable register 0 x 0000 gpiob_ipolr $6 interrupt polarity register 0 x 0000 gpiob_ipr $7 interrupt pending register 0 x 0000 gpiob_iesr $8 interrupt edge-s ensitive register 0 x 0000 gpiob_ppmode $9 push-pull mode register 0 x 0000 gpiob_rawdata $a raw data input register ? table 4-31 gpioc re gisters address map (gpioc_base = $00f310) register acronym address offset register description reset value gpioc_pur $0 pull-up enable register 0 x 07ff gpioc_dr $1 data register 0 x 0000 gpioc_ddr $2 data direction register 0 x 0000 gpioc_per $3 peripheral enable register 0 x 07ff gpioc_iar $4 interrupt assert register 0 x 0000 gpioc_ienr $5 interrupt enable register 0 x 0000 gpioc_ipolr $6 interrupt polarity register 0 x 0000 gpioc_ipr $7 interrupt pending register 0 x 0000 gpioc_iesr $8 interrupt edge-sensitive register 0 x 0000 gpioc_ppmode $9 push-pull mode register 0 x 07ff gpioc_rawdata $a raw data input register ?
56f8367 technical data, rev. 7.0 68 freescale semiconductor preliminary table 4-32 gpiod re gisters address map (gpiod_base = $00 f320) register acronym address offset register description reset value gpiod_pur $0 pull-up enable register 0 x 1fff gpiod_dr $1 data register 0 x 0000 gpiod_ddr $2 data direction register 0 x 0000 gpiod_per $3 peripheral enable register 0 x 1fc0 gpiod_iar $4 interrupt assert register 0 x 0000 gpiod_ienr $5 interrupt enable register 0 x 0000 gpiod_ipolr $6 interrupt polarity register 0 x 0000 gpiod_ipr $7 interrupt pending register 0 x 0000 gpiod_iesr $8 interrupt edge -sensitive register 0 x 0000 gpiod_ppmode $9 push-pull mode register gpiod_rawdata $a raw data input register ? table 4-33 gpioe registers address map (gpioe_base = $00 f330) register acronym address offset register description reset value gpioe_pur $0 pull-up enable register 0 x 3fff gpioe_dr $1 data register 0 x 0000 gpioe_ddr $2 data direction register 0 x 0000 gpioe_per $3 peripheral enable register 0 x 3fff gpioe_iar $4 interrupt assert register 0 x 0000 gpioe_ienr $5 interrupt enable register 0 x 0000 gpioe_ipolr $6 interrupt polarity register 0 x 0000 gpioe_ipr $7 interrupt pending register 0 x 0000 gpioe_iesr $8 interrupt edge-sensitive register 0 x 0000 gpioe_ppmode $9 push-pull mode register 0 x 3fff gpioe_rawdata $a raw data input register ?
peripheral memory mapped registers 56f8367 technical data, rev. 7.0 freescale semiconductor 69 preliminary table 4-34 gpiof regi sters address map (gpiof_base = $00 f340) register acronym address offset register description reset value gpiof_pur $0 pull-up enable register 0 x ffff gpiof_dr $1 data register 0 x 0000 gpiof_ddr $2 data direction register 0 x 0000 gpiof_per $3 peripheral enable register 0 x ffff gpiof_iar $4 interrupt assert register 0 x 0000 gpiof_ienr $5 interrupt enable register 0 x 0000 gpiof_ipolr $6 interrupt polarity register 0 x 0000 gpiof_ipr $7 interrupt pending register 0 x 0000 gpiof_iesr $8 interrupt edge-s ensitive register 0 x 0000 gpiof_ppmode $9 push-pull mode register 0 x ffff gpiof_rawdata $a raw data input register ? table 4-35 system integration module registers address map (sim_base = $00 f350) register acronym address o ffset register description sim_control $0 control register sim_rststs $1 reset status register sim_scr0 $2 software control register 0 sim_scr1 $3 software control register 1 sim_scr2 $4 software control register 2 sim_scr3 $5 software control register 3 sim_msh_id $6 most significant half jtag id sim_lsh_id $7 least significant half jtag id sim_pudr $8 pull-up disable register reserved sim_clkosr $a clock out select register sim_gps $b quad decoder 1 / time r b / spi 1 select register sim_pce $c peripheral clock enable register sim_isalh $d i/o short address location high register sim_isall $e i/o short address location low register sim_pce2 $f peripheral clock enable register 2
56f8367 technical data, rev. 7.0 70 freescale semiconductor preliminary table 4-36 power supervisor registers address map (lvi_base = $00 f360) register acronym address offset register description lvi_control $0 control register lvi_status $1 status register table 4-37 flash module registers address map (fm_base = $00 f400) register acronym address o ffset register description fmclkd $0 clock divider register fmmcr $1 module control register reserved fmsech $3 security high half register fmsecl $4 security low half register reserved reserved fmprot $10 protection register (banked) fmprotb $11 protection boot register (banked) reserved fmustat $13 user status register (banked) fmcmd $14 command register (banked) reserved reserved fmopt 0 $1a 16-bit information option register 0 hot temperature adc reading of temperature sensor; value set during factory test fmopt 1 $1b 16-bit information option register 1 not used fmopt 2 $1c 16-bit information option register 2 room temperature adc readi ng of temperature sensor; value set during factory test table 4-38 flexcan re gisters address map (fc_base = $00 f800) flexcan is not availa ble in the 56f8167 device register acronym address offset register description fcmcr $0 module configuration register reserved
peripheral memory mapped registers 56f8367 technical data, rev. 7.0 freescale semiconductor 71 preliminary fcctl0 $3 control register 0 register fcctl1 $4 control register 1 register fctmr $5 free-running timer register fcmaxmb $6 maximum message buffer configuration register reserved fcrxgmask_h $8 receive gl obal mask high register fcrxgmask_l $9 receive gl obal mask low register fcrx14mask_h $a receive buff er 14 mask high register fcrx14mask_l $b receive buff er 14 mask low register fcrx15mask_h $c receive buff er 15 mask high register fcrx15mask_l $d receive buff er 15 mask low register reserved fcstatus $10 error and status register fcimask1 $11 interrupt masks 1 register fciflag1 $12 interrupt flags 1 register fcr/t_error_cntrs $13 receive and transmit error counters register reserved reserved reserved fcmb0_control $40 message buffer 0 control / status register fcmb0_id_high $41 message buffer 0 id high register fcmb0_id_low $42 message buffer 0 id low register fcmb0_data $43 message buffer 0 data register fcmb0_data $44 message buffer 0 data register fcmb0_data $45 message buffer 0 data register fcmb0_data $46 message buffer 0 data register reserved fcmsb1_control $48 message buffer 1 control / status register fcmsb1_id_high $49 message buffer 1 id high register fcmsb1_id_low $4a message buffer 1 id low register fcmb1_data $4b message buffer 1 data register fcmb1_data $4c message buffer 1 data register table 4-38 flexcan register s address map (continued) (fc_base = $00 f800) flexcan is not availa ble in the 56f8167 device register acronym address offset register description
56f8367 technical data, rev. 7.0 72 freescale semiconductor preliminary fcmb1_data $4d message buffer 1 data register fcmb1_data $4e message buffer 1 data register reserved fcmb2_control $50 message buffer 2 control / status register fcmb2_id_high $51 message buffer 2 id high register fcmb2_id_low $52 message buffer 2 id low register fcmb2_data $53 message buffer 2 data register fcmb2_data $54 message buffer 2 data register fcmb2_data $55 message buffer 2 data register fcmb2_data $56 message buffer 2 data register reserved fcmb3_control $58 message buffer 3 control / status register fcmb3_id_high $59 message buffer 3 id high register fcmb3_id_low $5a message buffer 3 id low register fcmb3_data $5b message buffer 3 data register fcmb3_data $5c message buffer 3 data register fcmb3_data $5d message buffer 3 data register fcmb3_data $5e message buffer 3 data register reserved fcmb4_control $60 message buffer 4 control / status register fcmb4_id_high $61 message buffer 4 id high register fcmb4_id_low $62 message buffer 4 id low register fcmb4_data $63 message buffer 4 data register fcmb4_data $64 message buffer 4 data register fcmb4_data $65 message buffer 4 data register fcmb4_data $66 message buffer 4 data register reserved fcmb5_control $68 message buffer 5 control / status register fcmb5_id_high $69 message buffer 5 id high register fcmb5_id_low $6a message buffer 5 id low register fcmb5_data $6b message buffer 5 data register fcmb5_data $6c message buffer 5 data register table 4-38 flexcan register s address map (continued) (fc_base = $00 f800) flexcan is not availa ble in the 56f8167 device register acronym address offset register description
peripheral memory mapped registers 56f8367 technical data, rev. 7.0 freescale semiconductor 73 preliminary fcmb5_data $6d message buffer 5 data register fcmb5_data $6e message buffer 5 data register reserved fcmb6_control $70 message buffer 6 control / status register fcmb6_id_high $71 message buffer 6 id high register fcmb6_id_low $72 message buffer 6 id low register fcmb6_data $73 message buffer 6 data register fcmb6_data $74 message buffer 6 data register fcmb6_data $75 message buffer 6 data register fcmb6_data $76 message buffer 6 data register reserved fcmb7_control $78 message buffer 7 control / status register fcmb7_id_high $79 message buffer 7 id high register fcmb7_id_low $7a message buffer 7 id low register fcmb7_data $7b message buffer 7 data register fcmb7_data $7c message buffer 7 data register fcmb7_data $7d message buffer 7 data register fcmb7_data $7e message buffer 7 data register reserved fcmb8_control $80 message buffer 8 control / status register fcmb8_id_high $81 message buffer 8 id high register fcmb8_id_low $82 message buffer 8 id low register fcmb8_data $83 message buffer 8 data register fcmb8_data $84 message buffer 8 data register fcmb8_data $85 message buffer 8 data register fcmb8_data $86 message buffer 8 data register reserved fcmb9_control $88 message buffer 9 control / status register fcmb9_id_high $89 message buffer 9 id high register fcmb9_id_low $8a message buffer 9 id low register fcmb9_data $8b message buffer 9 data register fcmb9_data $8c message buffer 9 data register table 4-38 flexcan register s address map (continued) (fc_base = $00 f800) flexcan is not availa ble in the 56f8167 device register acronym address offset register description
56f8367 technical data, rev. 7.0 74 freescale semiconductor preliminary fcmb9_data $8d message buffer 9 data register fcmb9_data $8e message buffer 9 data register reserved fcmb10_control $90 message buffer 10 control / status register fcmb10_id_high $91 message buffer 10 id high register fcmb10_id_low $92 message buffer 10 id low register fcmb10_data $93 message buffer 10 data register fcmb10_data $94 message buffer 10 data register fcmb10_data $95 message buffer 10 data register fcmb10_data $96 message buffer 10 data register reserved fcmb11_control $98 message buffer 11 control / status register fcmb11_id_high $99 message buffer 11 id high register fcmb11_id_low $9a message buffer 11 id low register fcmb11_data $9b message buffer 11 data register fcmb11_data $9c message buffer 11 data register fcmb11_data $9d message buffer 11 data register fcmb11_data $9e message buffer 11 data register reserved fcmb12_control $a0 message buffer 12 control / status register fcmb12_id_high $a1 message buffer 12 id high register fcmb12_id_low $a2 message buffer 12 id low register fcmb12_data $a3 message buffer 12 data register fcmb12_data $a4 message buffer 12 data register fcmb12_data $a5 message buffer 12 data register fcmb12_data $a6 message buffer 12 data register reserved fcmb13_control $a8 message buffer 13 control / status register fcmb13_id_high $a9 message buffer 13 id high register fcmb13_id_low $aa message buffer 13 id low register fcmb13_data $ab message buffer 13 data register fcmb13_data $ac message buffer 13 data register fcmb13_data $ad message buffer 13 data register fcmb13_data $ae message buffer 13 data register table 4-38 flexcan register s address map (continued) (fc_base = $00 f800) flexcan is not availa ble in the 56f8167 device register acronym address offset register description
peripheral memory mapped registers 56f8367 technical data, rev. 7.0 freescale semiconductor 75 preliminary reserved fcmb14_control $b0 message buffer 14 control / status register fcmb14_id_high $b1 message buffer 14 id high register fcmb14_id_low $b2 message buffer 14 id low register fcmb14_data $b3 message buffer 14 data register fcmb14_data $b4 message buffer 14 data register fcmb14_data $b5 message buffer 14 data register fcmb14_data $b6 message buffer 14 data register reserved fcmb15_control $b8 message buffer 15 control / status register fcmb15_id_high $b9 message buffer 15 id high register fcmb15_id_low $ba message buffer 15 id low register fcmb15_data $bb message buffer 15 data register fcmb15_data $bc message buffer 15 data register fcmb15_data $bd message buffer 15 data register fcmb15_data $be message buffer 15 data register reserved table 4-39 flexcan2 re gisters address map (fc2_base = $00 fa00) flexcan2 is not availabl e in the 56f8167 device register acronym address offset register description fc2mcr $0 module configuration register reserved fc2ctl0 $3 control register 0 register fc2ctl1 $4 control register 1 register fc2tmr $5 free-running timer register fc2maxmb $6 maximum message buffer configuration register fc2imask2 $7 interrupt masks 2 register fc2rxgmask_h $8 receive global mask high register fc2rxgmask_l $9 receive global mask low register fc2rx14mask_h $a receive buff er 14 mask high register fc2rx14mask_l $b receive buff er 14 mask low register table 4-38 flexcan register s address map (continued) (fc_base = $00 f800) flexcan is not availa ble in the 56f8167 device register acronym address offset register description
56f8367 technical data, rev. 7.0 76 freescale semiconductor preliminary fc2rx15mask_h $c receive buff er 15 mask high register fc2rx15mask_l $d receive buff er 15 mask low register reserved fc2status $10 error and status register fc2imask1 $11 interrupt masks 1 register fc2iflag1 $12 interrupt flags 1 register fc2r/t_error_cntrs $13 receive and transmit error counters register reserved fc2iflag 2 $1b interrupt flags 2 register reserved fc2mb0_control $40 message buffer 0 control / status register fc2mb0_id_high $41 message buffer 0 id high register fc2mb0_id_low $42 message buffer 0 id low register fc2mb0_data $43 message buffer 0 data register fc2mb0_data $44 message buffer 0 data register fc2mb0_data $45 message buffer 0 data register fc2mb0_data $46 message buffer 0 data register reserved fc2msb1_control $48 message buffer 1 control / status register fc2msb1_id_high $49 message buffer 1 id high register fc2msb1_id_low $4a message buffer 1 id low register fc2mb1_data $4b message buffer 1 data register fc2mb1_data $4c message buffer 1 data register fc2mb1_data $4d message buffer 1 data register fc2mb1_data $4e message buffer 1 data register reserved fc2mb2_control $50 message buffer 2 control / status register fc2mb2_id_high $51 message buffer 2 id high register fc2mb2_id_low $52 message buffer 2 id low register fc2mb2_data $53 message buffer 2 data register fc2mb2_data $54 message buffer 2 data register fc2mb2_data $55 message buffer 2 data register fc2mb2_data $56 message buffer 2 data register reserved table 4-39 flexcan2 regist ers address map (continued) (fc2_base = $00 fa00) flexcan2 is not availabl e in the 56f8167 device register acronym address offset register description
peripheral memory mapped registers 56f8367 technical data, rev. 7.0 freescale semiconductor 77 preliminary fc2mb3_control $58 message buffer 3 control / status register fc2mb3_id_high $59 message buffer 3 id high register fc2mb3_id_low $5a message buffer 3 id low register fc2mb3_data $5b message buffer 3 data register fc2mb3_data $5c message buffer 3 data register fc2mb3_data $5d message buffer 3 data register fc2mb3_data $5e message buffer 3 data register reserved fc2mb4_control $60 message buffer 4 control / status register fc2mb4_id_high $61 message buffer 4 id high register fc2mb4_id_low $62 message buffer 4 id low register fc2mb4_data $63 message buffer 4 data register fc2mb4_data $64 message buffer 4 data register fc2mb4_data $65 message buffer 4 data register fc2mb4_data $66 message buffer 4 data register reserved fc2mb5_control $68 message buffer 5 control / status register fc2mb5_id_high $69 message buffer 5 id high register fc2mb5_id_low $6a message buffer 5 id low register fc2mb5_data $6b message buffer 5 data register fc2mb5_data $6c message buffer 5 data register fc2mb5_data $6d message buffer 5 data register fc2mb5_data $6e message buffer 5 data register reserved fc2mb6_control $70 message buffer 6 control / status register fc2mb6_id_high $71 message buffer 6 id high register fc2mb6_id_low $72 message buffer 6 id low register fc2mb6_data $73 message buffer 6 data register fc2mb6_data $74 message buffer 6 data register fc2mb6_data $75 message buffer 6 data register fc2mb6_data $76 message buffer 6 data register reserved fc2mb7_control $78 message buffer 7 control / status register fc2mb7_id_high $79 message buffer 7 id high register table 4-39 flexcan2 regist ers address map (continued) (fc2_base = $00 fa00) flexcan2 is not availabl e in the 56f8167 device register acronym address offset register description
56f8367 technical data, rev. 7.0 78 freescale semiconductor preliminary fc2mb7_id_low $7a message buffer 7 id low register fc2mb7_data $7b message buffer 7 data register fc2mb7_data $7c message buffer 7 data register fc2mb7_data $7d message buffer 7 data register fc2mb7_data $7e message buffer 7 data register reserved fc2mb8_control $80 message buffer 8 contro l /status register fc2mb8_id_high $81 message buffer 8 id high register fc2mb8_id_low $82 message buffer 8 id low register fc2mb8_data $83 message buffer 8 data register fc2mb8_data $84 message buffer 8 data register fc2mb8_data $85 message buffer 8 data register fc2mb8_data $86 message buffer 8 data register reserved fc2mb9_control $88 message buffer 9 control / status register fc2mb9_id_high $89 message buffer 9 id high register fc2mb9_id_low $8a message buffer 9 id low register fc2mb9_data $8b message buffer 9 data register fc2mb9_data $8c message buffer 9 data register fc2mb9_data $8d message buffer 9 data register fc2mb9_data $8e message buffer 9 data register reserved fc2mb10_control $90 message buffer 10 control / status register fc2mb10_id_high $91 message buffer 10 id high register fc2mb10_id_low $92 message buffer 10 id low register fc2mb10_data $93 message buffer 10 data register fc2mb10_data $94 message buffer 10 data register fc2mb10_data $95 message buffer 10 data register fc2mb10_data $96 message buffer 10 data register reserved fc2mb11_control $98 message buffer 11 control / status register fc2mb11_id_high $99 message buffer 11 id high register fc2mb11_id_low $9a message buffer 11 id low register fc2mb11_data $9b message buffer 11 data register table 4-39 flexcan2 regist ers address map (continued) (fc2_base = $00 fa00) flexcan2 is not availabl e in the 56f8167 device register acronym address offset register description
peripheral memory mapped registers 56f8367 technical data, rev. 7.0 freescale semiconductor 79 preliminary fc2mb11_data $9c message buffer 11 data register fc2mb11_data $9d message buffer 11 data register fc2mb11_data $9e message buffer 11 data register reserved fc2mb12_control $a0 message buffer 12 control / status register fc2mb12_id_high $a1 message buffer 12 id high register fc2mb12_id_low $a2 message buffer 12 id low register fc2mb12_data $a3 message buffer 12 data register fc2mb12_data $a4 message buffer 12 data register fc2mb12_data $a5 message buffer 12 data register fc2mb12_data $a6 message buffer 12 data register reserved fc2mb13_control $a8 message buffer 13 control / status register fc2mb13_id_high $a9 message buffer 13 id high register fc2mb13_id_low $aa message buffer 13 id low register fc2mb13_data $ab message buffer 13 data register fc2mb13_data $ac message buffer 13 data register fc2mb13_data $ad message buffer 13 data register fc2mb13_data $ae message buffer 13 data register reserved fc2mb14_control $b0 message buffer 14 control / status register fc2mb14_id_high $b1 message buffer 14 id high register fc2mb14_id_low $b2 message buffer 14 id low register fc2mb14_data $b3 message buffer 14 data register fc2mb14_data $b4 message buffer 14 data register fc2mb14_data $b5 message buffer 14 data register fc2mb14_data $b6 message buffer 14 data register reserved fc2mb15_control $b8 message buffer 15 control / status register fc2mb15_id_high $b9 message buffer 15 id high register fc2mb15_id_low $ba message buffer 15 id low register fc2mb15_data $bb message buffer 15 data register fc2mb15_data $bc message buffer 15 data register fc2mb15_data $bd message buffer 15 data register table 4-39 flexcan2 regist ers address map (continued) (fc2_base = $00 fa00) flexcan2 is not availabl e in the 56f8167 device register acronym address offset register description
56f8367 technical data, rev. 7.0 80 freescale semiconductor preliminary 4.8 factory programmed memory the boot flash memory block is programmed during manufacturing wi th a default serial bootloader program. the serial bootloader appli cation can be used to load a user application into the program and data flash ( not available in the 56f8167 device ) memories of the device. the 56f83xx sci/can bootloader user manual (mc56f83xxblum) provides detailed information on this firmware. an application note, production flash programming (an1973) , details how the serial bootloader program can be used to perform production flash programming of the on-board flash memo ries as well as other potential methods. like all the flash memory blocks, the boot flash can be erased a nd programmed by the user. the serial bootloader application is programmed as an aid to the end user, but is not required to be used or maintained in the boot flash memory. fc2mb15_data $be message buffer 15 data register reserved table 4-39 flexcan2 regist ers address map (continued) (fc2_base = $00 fa00) flexcan2 is not availabl e in the 56f8167 device register acronym address offset register description
introduction 56f8367 technical data, rev. 7.0 freescale semiconductor 81 preliminary part 5 interrupt controller (itcn) 5.1 introduction the interrupt controller (itcn) m odule is used to arbitr ate between various inte rrupt requests (irqs), to signal to the 56800e core when an interr upt of sufficient priority exists, and what address to jump in order to service this interrupt. 5.2 features the itcn module design includes these distinctive features: ? programmable priority levels for each irq ? two programmable fast interrupts ? notification to sim module to restar t clocks out of wait and stop modes ? drives initial address on the address bus after reset for further information, see table 4-5 , interrupt vector table contents. 5.3 functional description the interrupt controller is a slave on the ipbus. it contains registers allowing each of the 86 interrupt sources to be set to one of four pr iority levels, excluding certain inte rrupts of fixed priority. next, all of the interrupt requests of a given level are priority en coded to determine the lowest numerical value of the active interrupt requests for that leve l. within a given priority level, 0 is the highest prio rity, while number 85 is the lowest. 5.3.1 normal interrupt handling once the itcn has determined that an interrupt is to be serviced and which interrupt has the highest priority, an interrupt vect or address is generated. no rmal interrupt handling con catenates the vba and the vector number to determine th e vector address. in this way, an offset is generated into the vector table for each interrupt. 5.3.2 interrupt nesting interrupt exceptions may be nested to allow an irq of higher priori ty than the current exception to be serviced. the following tables define the nesting requirements for each priority level. table 5-1 interrupt mask bit definition sr[9] 1 1. core status register bits indicating current interrupt mask within the core. sr[8] 1 permitted exceptions masked exceptions 0 0 priorities 0, 1, 2, 3 none 0 1 priorities 1, 2, 3 priority 0 1 0 priorities 2, 3 priorities 0, 1 1 1 priority 3 priorities 0, 1, 2
56f8367 technical data, rev. 7.0 82 freescale semiconductor preliminary 5.3.3 fast interrupt handling fast interrupts are described in the dsp56800e reference manual . the interrupt c ontroller recognizes fast interrupts before the core does. a fast interrupt is defined (to the itcn) by: 1. setting the priority of the interrupt as level 2, with the appropriate field in the ipr registers 2. setting the fimn register to the appropriate vector number 3. setting the fivaln and fivahn registers with the address of the code for the fast interrupt when an interrupt occurs, its vector number is compar ed with the fim0 and fim1 register values. if a match occurs, and it is a level 2 interrupt, the itcn handles it as a fast interrupt. the itcn takes the vector address from the appropriate fivaln and fivahn registers, instead of generating an addr ess that is an offset from the vba. the core then fetches the instruction from the indicated vector adddress and if it is not a js r, the core starts its fast interrupt handling. table 5-2. interrupt priority encoding ipic_level[1:0] 1 1. see ipic field definition in part 5.6.30.2 current interr upt priority level required nested exception priority 00 no interrupt or swilp priorities 0, 1, 2, 3 01 priority 0 priorities 1, 2, 3 01 priority 1 priorities 2, 3 11 priorities 2 or 3 priority 3
block diagram 56f8367 technical data, rev. 7.0 freescale semiconductor 83 preliminary 5.4 block diagram figure 5-1 interrupt controller block diagram 5.5 operating modes the itcn module design contains two major modes of operation: ? functional mode the itcn is in this mode by default. ? wait and stop modes during wait and stop modes, the syst em clocks and the 56800e core are turned off. the itcn will signal a pending irq to the system integr ation module (sim) to restart the clocks and service the irq. an irq can only wake up the core if the irq is enabled pr ior to entering the wait or stop mode. also, the irqa and irqb signals automatically become low- level sensitive in these modes even if the control register bits are set to make them falling- edge sensitive. this is because there is no clock available to detect the falling edge. a peripheral which requires a clock to generate interrupts will not be able to generate interrupts during stop mode. the flexcan module can wake the device from st op mode, and a reset will do just that, or irqa and irqb can wake it up. priority level 2->4 decode int1 priority level 2->4 decode int82 level 0 82->7 priority encoder any0 level 3 82->7 priority encoder any3 int vab ipic control 7 7 pic_en iack sr[9:8]
56f8367 technical data, rev. 7.0 84 freescale semiconductor preliminary 5.6 register descriptions a register address is the sum of a base address and an addr ess offset. the base addr ess is defined at the system level and the addres s offset is defined at the module level. the itcn peripheral has 24 registers. table 5-3 itcn register summary (itcn_base = $00f1a0) register acronym base address + register name section location ipr0 $0 interrupt priority register 0 5.6.1 ipr1 $1 interrupt priority register 1 5.6.2 ipr2 $2 interrupt priority register 2 5.6.3 ipr3 $3 interrupt priority register 3 5.6.4 ipr4 $4 interrupt priority register 4 5.6.5 ipr5 $5 interrupt priority register 5 5.6.6 ipr6 $6 interrupt priority register 6 5.6.7 ipr7 $7 interrupt priority register 7 5.6.8 ipr8 $8 interrupt priority register 8 5.6.9 ipr9 $9 interrupt priority register 9 5.6.10 vba $a vector base address register 5.6.11 fim0 $b fast interrupt 0 match register 5.6.12 fival0 $c fast interrupt 0 vector address low register 5.6.13 fivah0 $d fast interrupt 0 vector address high register 5.6.14 fim1 $e fast interrupt 1 match register 5.6.15 fival1 $f fast interrupt 1 vector address low register 5.6.16 fivah1 $10 fast interrupt 1 vector address high register 5.6.17 irqp0 $11 irq pending register 0 5.6.18 irqp1 $12 irq pending register 1 5.6.19 irqp2 $13 irq pending register 2 5.6.20 irqp3 $14 irq pending register 3 5.6.21 irqp4 $15 irq pending register 4 5.6.22 irqp5 $16 irq pending register 5 5.6.23 reserved ictl $1d interrupt control register 5.6.30 reserved ipr10 $1f interrupt priority register 10 5.6.32 note : the ipr10 is not available in the 56f8167 device.
register descriptions 56f8367 technical data, rev. 7.0 freescale semiconductor 85 preliminary add. offset register name 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 $0 ipr0 r 0 0 bkpt_u0 ipl stpcnt ipl 0 0 0 0 0 0 0 0 0 0 w $1 ipr1 r 0 0 0 0 0 0 0 0 0 0 rx_reg ipl tx_reg ipl trbuf ipl w $2 ipr2 r fmcbe ipl fmcc ipl fmerr ipl lock ipl lvi ipl 0 0 irqb ipl irqa ipl w $3 ipr3 r gpiod ipl gpioe ipl gpiof ipl fcmsgbuf ipl fcwkup ipl fcerr ipl fcboff ipl 0 0 w $4 ipr4 r spi0_rcv ipl spi1_xmit ipl spi1_rcv ipl 0 0 0 0 gpioa ipl gpiob ipl gpioc ipl w $5 ipr5 r dec1_xirq ipl dec1_hirq ipl sci1_rcv ipl sci1_rerr ipl 0 0 sci1_tidl ipl sci1_xmit ipl spi0_xmit ipl w $6 ipr6 r tmrc0 ipl tmrd3 ipl tmrd2 ipl tmrd1 ipl tmrd0 ipl 0 0 dec0_xirq ipl dec0_hirq ipl w $7 ipr7 r tmra0 ipl tmrb3 ipl tmrb2 ipl tmrb1 ipl tmrb0 ipl tmrc3 ipl tmrc2 ipl tmrc1 ipl w $8 ipr8 r sci0_rcv ipl sci0_rerr ipl 0 0 sci0_tidl ipl sci0_xmit ipl tmra3 ipl tmra2 ipl tmra1 ipl w $9 ipr9 r pwma f ipl pwmb f ipl pwma_rl ipl pwmb_rl ipl adca_zc ipl abcb_zc ipl adca_cc ipl adcb_cc ipl w $a vba r 0 0 0 vector base address w $b vba0 r 0 0 0 0 0 0 0 0 0 fast interrupt 0 w $c fival0 r fast interrupt 0 vector address low w $d fivah0 r 0 0 0 0 0 0 0 0 0 0 0 fast interrupt 0 vector address high w $e fim1 r 0 0 0 0 0 0 0 0 0 fast interrupt 1 w $f fival1 r fast interrupt 1 vector address low w $10 fivah1 r 0 0 0 0 0 0 0 0 0 0 0 fast interrupt 1 vector address high w $11 irqp0 r pending [16:2] 1 w $12 irqp1 r pending [32:17] w $13 irqp2 r pending [48:33] w $14 irqp3 r pending [64:49] w $15 irqp4 r pending [80:65] w $16 irqp5 r 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 pend- ing [81] w reserved $1d ictl r int ipic vab int_dis 1 irqb state irqa state irqb edg irqa edg w reserved $1f ipr10 r 0 0 0 0 0 0 0 0 flexcan2 msgbug ipl flexcan2 wkup ipl flexcan2 err ipl flexcan2 boff ipl w = reserved figure 5-2 itcn register map summary
56f8367 technical data, rev. 7.0 86 freescale semiconductor preliminary 5.6.1 interrupt priority register 0 (ipr0) figure 5-3 interrupt prio rity register 0 (ipr0) 5.6.1.1 reserved?bits 15?14 this bit field is reserved or not implemented. it is read as 0 a nd cannot be modified by writing. 5.6.1.2 eonce breakpoint unit 0 inte rrupt priority level (bkpt_u0 ipl)? bits13?12 this field is used to set the interr upt priority levels for irqs. this ir q is limited to priorities 1 through 3. it is disabled by default. ? 00 = irq disabled (default) ? 01 = irq is priority level 1 ? 10 = irq is priority level 2 ? 11 = irq is priority level 3 5.6.1.3 eonce step counter interrupt priority level (stpcnt ipl)? bits 11?10 this field is used to set the interr upt priority level for irqs. this irq is limited to prio rities 1 through 3. it is disabled by default. ? 00 = irq disabled (default) ? 01 = irq is priority level 1 ? 10 = irq is priority level 2 ? 11 = irq is priority level 3 5.6.1.4 reserved?bits 9?0 this bit field is reserved or not implemented. it is read as 0 a nd cannot be modified by writing. 5.6.2 interrupt priority register 1 (ipr1) figure 5-4 interrupt prio rity register 1 (ipr1) base + $0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read 0 0 bkpt_u0ipl stpcnt ipl 0 0 0 0 0 0 0 0 0 0 write reset 0 0 0 0 0 0 0 000000000 base + $1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read 0 0 0 0 0 0 0 0 0 0 rx_reg ipl tx_reg ipl trbuf ipl write reset 0 0 0 0 0 0 0 000000000
register descriptions 56f8367 technical data, rev. 7.0 freescale semiconductor 87 preliminary 5.6.2.1 reserved?bits 15?6 this bit field is reserved or not implemented. it is read as 0 a nd cannot be modified by writing. 5.6.2.2 eonce receive register full interrupt priority level (rx_reg ipl)?bits 5?4 this field is used to set the interr upt priority level for irqs. this irq is limited to prio rities 1 through 3. it is disabled by default. ? 00 = irq disabled (default) ? 01 = irq is priority level 1 ? 10 = irq is priority level 2 ? 11 = irq is priority level 3 5.6.2.3 eonce transmit regist er empty interrupt priority level (tx_reg ipl)?bits 3?2 this field is used to set the interr upt priority level for irqs. this irq is limited to prio rities 1 through 3. it is disabled by default. ? 00 = irq disabled (default) ? 01 = irq is priority level 1 ? 10 = irq is priority level 2 ? 11 = irq is priority level 3 5.6.2.4 eonce trace buffer interrupt priority level (trbuf ipl)?bits 1?0 this field is used to set the interr upt priority level for irqs. this irq is limited to prio rities 1 through 3. it is disabled by default. ? 00 = irq disabled (default) ? 01 = irq is priority level 1 ? 10 = irq is priority level 2 ? 11 = irq is priority level 3 5.6.3 interrupt priority register 2 (ipr2) figure 5-5 interrupt prio rity register 2 (ipr2) base + $2 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read fmcbe ipl fmcc ipl fmerr ipl lock ipl lvi ipl 0 0 irqb ipl irqa ipl write reset 0000000000000000
56f8367 technical data, rev. 7.0 88 freescale semiconductor preliminary 5.6.3.1 flash memory command, da ta, address buffers empty interrupt priority level (fmcbe ipl)?bits 15?14 this field is used to set the interr upt priority level for irqs. this irq is limited to prio rities 0 through 2. it is disabled by default. ? 00 = irq disabled (default) ? 01 = irq is priority level 0 ? 10 = irq is priority level 1 ? 11 = irq is priority level 2 5.6.3.2 flash memory command co mplete priority level (fmcc ipl)? bits 13?12 this field is used to set the interr upt priority level for irqs. this irq is limited to prio rities 0 through 2. it is disabled by default. ? 00 = irq disabled (default) ? 01 = irq is priority level 0 ? 10 = irq is priority level 1 ? 11 = irq is priority level 2 5.6.3.3 flash memory error interrupt priority level (fmerr ipl)?bits 11?10 this field is used to set the interr upt priority level for irqs. this irq is limited to prio rities 0 through 2. it is disabled by default. ? 00 = irq disabled (default) ? 01 = irq is priority level 0 ? 10 = irq is priority level 1 ? 11 = irq is priority level 2 5.6.3.4 pll loss of lock interrupt pr iority level (lock ipl)?bits 9?8 this field is used to set the interr upt priority level for irqs. this irq is limited to prio rities 0 through 2. it is disabled by default. ? 00 = irq disabled (default) ? 01 = irq is priority level 0 ? 10 = irq is priority level 1 ? 11 = irq is priority level 2
register descriptions 56f8367 technical data, rev. 7.0 freescale semiconductor 89 preliminary 5.6.3.5 low voltage detector interru pt priority level (lvi ipl)?bits 7?6 this field is used to set the interr upt priority level for irqs. this irq is limited to prio rities 0 through 2. it is disabled by default. ? 00 = irq disabled (default) ? 01 = irq is priority level 0 ? 10 = irq is priority level 1 ? 11 = irq is priority level 2 5.6.3.6 reserved?bits 5?4 this bit field is reserved or not implemented. it is read as 0 a nd cannot be modified by writing. 5.6.3.7 external irq b interrupt priority level (irqb ipl)?bits 3?2 this field is used to set the interr upt priority level for irqs. this irq is limited to prio rities 0 through 2. it is disabled by default. ? 00 = irq disabled (default) ? 01 = irq is priority level 0 ? 10 = irq is priority level 1 ? 11 = irq is priority level 2 5.6.3.8 external irq a interrupt priority level (irqa ipl)?bits 1?0 this field is used to set the interr upt priority level for irqs. this irq is limited to prio rities 0 through 2. it is disabled by default. ? 00 = irq disabled (default) ? 01 = irq is priority level 0 ? 10 = irq is priority level 1 ? 11 = irq is priority level 2 5.6.4 interrupt priority register 3 (ipr3) figure 5-6 interrupt prio rity register 3 (ipr3) 5.6.4.1 gpiod interrupt priorit y level (gpiod ipl)?bits 15?14 this field is used to set the interr upt priority level for irqs. this irq is limited to prio rities 0 through 2. they are disabled by default. ? 00 = irq disabled (default) ? 01 = irq is priority level 0 ? 10 = irq is priority level 1 ? 11 = irq is priority level 2 base + $3 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read gpiod ipl gpioe ipl gpiofipl fcmsgbuf ipl fcwkup ipl fcerr ipl fcboff ipl 0 0 write reset 000000 0 0 0 0 0 0 0 0 0 0
56f8367 technical data, rev. 7.0 90 freescale semiconductor preliminary 5.6.4.2 gpioe interrupt priorit y level (gpioe ipl)?bits 13?12 this field is used to set the interr upt priority level for irqs. this irq is limited to prio rities 0 through 2. they are disabled by default. ? 00 = irq disabled (default) ? 01 = irq is priority level 0 ? 10 = irq is priority level 1 ? 11 = irq is priority level 2 5.6.4.3 gpiof interrupt priorit y level (gpiof ipl)?bits 11?10 this field is used to set the interr upt priority level for irqs. this irq is limited to prio rities 0 through 2. they are disabled by default. ? 00 = irq disabled (default) ? 01 = irq is priority level 0 ? 10 = irq is priority level 1 ? 11 = irq is priority level 2 5.6.4.4 flexcan message buffer inte rrupt priority level (fcmsgbuf ipl)? bits 9?8 this field is used to set the interr upt priority level for irqs. this irq is limited to prio rities 0 through 2. they are disabled by default. ? 00 = irq disabled (default) ? 01 = irq is priority level 0 ? 10 = irq is priority level 1 ? 11 = irq is priority level 2 5.6.4.5 flexcan wake up interrupt pr iority level (fcw kup ipl)?bits 7?6 this field is used to set the interr upt priority level for irqs. this irq is limited to prio rities 0 through 2. they are disabled by default. ? 00 = irq disabled (default) ? 01 = irq is priority level 0 ? 10 = irq is priority level 1 ? 11 = irq is priority level 2 5.6.4.6 flexcan error interrupt prio rity level (fcerr ipl)? bits 5?4 this field is used to set the interr upt priority level for irqs. this irq is limited to prio rities 0 through 2. they are disabled by default. ? 00 = irq disabled (default) ? 01 = irq is priority level 0 ? 10 = irq is priority level 1 ? 11 = irq is priority level 2
register descriptions 56f8367 technical data, rev. 7.0 freescale semiconductor 91 preliminary 5.6.4.7 flexcan bus off interrupt priority level (fcboff ipl)? bits 3?2 this field is used to set the interr upt priority level for irqs. this irq is limited to prio rities 0 through 2. they are disabled by default. ? 00 = irq disabled (default) ? 01 = irq is priority level 0 ? 10 = irq is priority level 1 ? 11 = irq is priority level 2 5.6.4.8 reserved?bits 1?0 this bit field is reserved or not implemented. it is read as 0 a nd cannot be modified by writing. 5.6.5 interrupt priority register 4 (ipr4) figure 5-7 interrupt prio rity register 4 (ipr4) 5.6.5.1 spi0 receiver full interrupt priority level (spi0_rcv ipl)?bits 15?14 this field is used to set the interr upt priority level for irqs. this irq is limited to prio rities 0 through 2. they are disabled by default. ? 00 = irq disabled (default) ? 01 = irq is priority level 0 ? 10 = irq is priority level 1 ? 11 = irq is priority level 2 5.6.5.2 spi1 transmit empty inte rrupt priority level (spi1_xmit ipl)? bits 13?12 this field is used to set the interr upt priority level for irqs. this irq is limited to prio rities 0 through 2. they are disabled by default. ? 00 = irq disabled (default) ? 01 = irq is priority level 0 ? 10 = irq is priority level 1 ? 11 = irq is priority level 2 base + $4 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read spi0_rcv ipl spi1_xmit ipl spi1_rcv ipl 0 0 0 0 gpioa ipl gpiob ipl gpioc ipl write reset 0000000000000000
56f8367 technical data, rev. 7.0 92 freescale semiconductor preliminary 5.6.5.3 spi1 receiver full interrupt priority level (spi1_rcv ipl)?bits 11?10 this field is used to set the interr upt priority level for irqs. this irq is limited to prio rities 0 through 2. they are disabled by default. ? 00 = irq disabled (default) ? 01 = irq is priority level 0 ? 10 = irq is priority level 1 ? 11 = irq is priority level 2 5.6.5.4 reserved?bits 9?6 this bit field is reserved or not implemented. it is read as 0 a nd cannot be modified by writing. 5.6.5.5 gpioa interrupt priority level (gpioa ipl)?bits 5?4 this field is used to set the interr upt priority level for irqs. this irq is limited to prio rities 0 through 2. they are disabled by default. ? 00 = irq disabled (default) ? 01 = irq is priority level 0 ? 10 = irq is priority level 1 ? 11 = irq is priority level 2 5.6.5.6 gpiob interrupt priority level (gpiob ipl)?bits 3?2 this field is used to set the interr upt priority level for irqs. this irq is limited to prio rities 0 through 2. they are disabled by default. ? 00 = irq disabled (default) ? 01 = irq is priority level 0 ? 10 = irq is priority level 1 ? 11 = irq is priority level 2 5.6.5.7 gpioc interrupt priority level (gpioc ipl)?bits 1?0 this field is used to set the interr upt priority level for irqs. this irq is limited to prio rities 0 through 2. they are disabled by default. ? 00 = irq disabled (default) ? 01 = irq is priority level 0 ? 10 = irq is priority level 1 ? 11 = irq is priority level 2
register descriptions 56f8367 technical data, rev. 7.0 freescale semiconductor 93 preliminary 5.6.6 interrupt priority register 5 (ipr5) figure 5-8 interrupt prio rity register 5 (ipr5) 5.6.6.1 quadrature decoder 1 index puls e interrupt priority level (dec1_xirq ipl)?bits 15?14 this field is used to set the interr upt priority level for irqs. this irq is limited to prio rities 0 through 2. they are disabled by default. ? 00 = irq disabled (default) ? 01 = irq is priority level 0 ? 10 = irq is priority level 1 ? 11 = irq is priority level 2 5.6.6.2 quadrature decoder 1 home si gnal transition or watchdog timer interrupt priority level (d ec1_hirq ipl)?bits 13?12 this field is used to set the interr upt priority level for irqs. this irq is limited to prio rities 0 through 2. they are disabled by default. ? 00 = irq disabled (default) ? 01 = irq is priority level 0 ? 10 = irq is priority level 1 ? 11 = irq is priority level 2 5.6.6.3 sci1 receiver full interrupt priority level (sci1_rcv ipl)?bits 11?10 this field is used to set the interr upt priority level for irqs. this irq is limited to prio rities 0 through 2. they are disabled by default. ? 00 = irq disabled (default) ? 01 = irq is priority level 0 ? 10 = irq is priority level 1 ? 11 = irq is priority level 2 5.6.6.4 sci1 receiver error interrupt priority level (sci1_rerr ipl)?bits 9?8 this field is used to set the interr upt priority level for irqs. this irq is limited to prio rities 0 through 2. they are disabled by default. ? 00 = irq disabled (default) ? 01 = irq is priority level 0 ? 10 = irq is priority level 1 ? 11 = irq is priority level 2 base + $5 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read dec1_xirq ipl dec1_hirq ipl sci1_rcv ipl sci1_rerr ipl 0 0 sci1_tidl ipl sci1_xmit ipl spi0_xmit ipl write reset 000000 0 0 00000000
56f8367 technical data, rev. 7.0 94 freescale semiconductor preliminary 5.6.6.5 reserved?bits 7?6 this bit field is reserved or not implemented. it is read as 0 a nd cannot be modified by writing. 5.6.6.6 sci1 transmitter idle interrupt priority level (sci1_ tidl ipl)?bits 5?4 this field is used to set the interr upt priority level for irqs. this irq is limited to prio rities 0 through 2. they are disabled by default. ? 00 = irq disabled (default) ? 01 = irq is priority level 0 ? 10 = irq is priority level 1 ? 11 = irq is priority level 2 5.6.6.7 sci1 transmitter empty inte rrupt priority level (sci1_xmit ipl)? bits 3?2 this field is used to set the interr upt priority level for irqs. this irq is limited to prio rities 0 through 2. they are disabled by default. ? 00 = irq disabled (default) ? 01 = irq is priority level 0 ? 10 = irq is priority level 1 ? 11 = irq is priority level 2 5.6.6.8 spi0 transmitter empty inte rrupt priority level (spi_xmit ipl)? bits 1?0 this field is used to set the interr upt priority level for irqs. this irq is limited to prio rities 0 through 2. they are disabled by default. ? 00 = irq disabled (default) ? 01 = irq is priority level 0 ? 10 = irq is priority level 1 ? 11 = irq is priority level 2 5.6.7 interrupt priority register 6 (ipr6) figure 5-9 interrupt prio rity register 6 (ipr6) base + $6 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read tmrc0 ipl tmrd3 ipl tmrd2 ipl tmrd1 ipl tmrd0 ipl 0 0 dec0_xirq ipl dec0_hirq ipl write reset 0000000000000000
register descriptions 56f8367 technical data, rev. 7.0 freescale semiconductor 95 preliminary 5.6.7.1 timer c, channel 0 interrupt priority level (tmrc0 ipl)?bits 15?14 this field is used to set the interr upt priority level for irqs. this irq is limited to prio rities 0 through 2. they are disabled by default. ? 00 = irq disabled (default) ? 01 = irq is priority level 0 ? 10 = irq is priority level 1 ? 11 = irq is priority level 2 5.6.7.2 timer d, channel 3 interrupt priority level (tmrd3 ipl)?bits 13?12 this field is used to set the interr upt priority level for irqs. this irq is limited to prio rities 0 through 2. they are disabled by default. ? 00 = irq disabled (default) ? 01 = irq is priority level 0 ? 10 = irq is priority level 1 ? 11 = irq is priority level 2 5.6.7.3 timer d, channel 2 interrupt priority level (tmrd2 ipl)?bits 11?10 this field is used to set the interr upt priority level for irqs. this irq is limited to prio rities 0 through 2. they are disabled by default. ? 00 = irq disabled (default) ? 01 = irq is priority level 0 ? 10 = irq is priority level 1 ? 11 = irq is priority level 2 5.6.7.4 timer d, channel 1 interr upt priority level (tm rd1 ipl)?bits 9?8 this field is used to set the interr upt priority level for irqs. this irq is limited to prio rities 0 through 2. they are disabled by default. ? 00 = irq disabled (default) ? 01 = irq is priority level 0 ? 10 = irq is priority level 1 ? 11 = irq is priority level 2 5.6.7.5 timer d, channel 0 interr upt priority level (tm rd0 ipl)?bits 7?6 this field is used to set the interr upt priority level for irqs. this irq is limited to prio rities 0 through 2. they are disabled by default. ? 00 = irq disabled (default) ? 01 = irq is priority level 0 ? 10 = irq is priority level 1 ? 11 = irq is priority level 2
56f8367 technical data, rev. 7.0 96 freescale semiconductor preliminary 5.6.7.6 reserved?bits 5?4 this bit field is reserved or not implemented. it is read as 0 a nd cannot be modified by writing. 5.6.7.7 quadrature decoder 0, i ndex pulse interrupt priority level (dec0_xirq ipl)?bits 3?2 this field is used to set the interr upt priority level for irqs. this irq is limited to prio rities 0 through 2. they are disabled by default. ? 00 = irq disabled (default) ? 01 = irq is priority level 0 ? 10 = irq is priority level 1 ? 11 = irq is priority level 2 5.6.7.8 quadrature decoder 0, home signal transition or watchdog timer interrupt priority level (d ec0_hirq ipl)?bits 1?0 this field is used to set the interr upt priority level for irqs. this irq is limited to prio rities 0 through 2. they are disabled by default. ? 00 = irq disabled (default) ? 01 = irq is priority level 0 ? 10 = irq is priority level 1 ? 11 = irq is priority level 2 5.6.8 interrupt priority register 7 (ipr7) figure 5-10 interrupt prio rity register (ipr7) 5.6.8.1 timer a, channel 0 interrupt priority level (tmra0 ipl)?bits 15?14 this field is used to set the interr upt priority level for irqs. this irq is limited to prio rities 0 through 2. they are disabled by default. ? 00 = irq disabled (default) ? 01 = irq is priority level 0 ? 10 = irq is priority level 1 ? 11 = irq is priority level 2 base + $7 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read tmra0 ipl tmrb3 ipl tmrb2 ipl tmrb1 ipl tmrb0 ipl tmrc3 ipl tmrc2 ipl tmrc1 ipl write reset 0000000000000000
register descriptions 56f8367 technical data, rev. 7.0 freescale semiconductor 97 preliminary 5.6.8.2 timer b, channel 3 interrupt priority level (tmrb3 ipl)?bits 13?12 this field is used to set the interr upt priority level for irqs. this irq is limited to prio rities 0 through 2. they are disabled by default. ? 00 = irq disabled (default) ? 01 = irq is priority level 0 ? 10 = irq is priority level 1 ? 11 = irq is priority level 2 5.6.8.3 timer b, channel 2 interrupt priority level (tmrb2 ipl)?bits 11?10 this field is used to set the interr upt priority level for irqs. this irq is limited to prio rities 0 through 2. they are disabled by default. ? 00 = irq disabled (default) ? 01 = irq is priority level 0 ? 10 = irq is priority level 1 ? 11 = irq is priority level 2 5.6.8.4 timer b, channel 1 interr upt priority level (tm rb1 ipl)?bits 9?8 this field is used to set the interr upt priority level for irqs. this irq is limited to prio rities 0 through 2. they are disabled by default. ? 00 = irq disabled (default) ? 01 = irq is priority level 0 ? 10 = irq is priority level 1 ? 11 = irq is priority level 2 5.6.8.5 timer b, channel 0 interr upt priority level (tm rb0 ipl)?bits 7?6 this field is used to set the interr upt priority level for irqs. this irq is limited to prio rities 0 through 2. they are disabled by default. ? 00 = irq disabled (default) ? 01 = irq is priority level 0 ? 10 = irq is priority level 1 ? 11 = irq is priority level 2 5.6.8.6 timer c, channel 3 interr upt priority level (tm rc3 ipl)?bits 5?4 this field is used to set the interr upt priority level for irqs. this irq is limited to prio rities 0 through 2. they are disabled by default. ? 00 = irq disabled (default) ? 01 = irq is priority level 0 ? 10 = irq is priority level 1 ? 11 = irq is priority level 2
56f8367 technical data, rev. 7.0 98 freescale semiconductor preliminary 5.6.8.7 timer c, channel 2 interr upt priority level (tm rc2 ipl)?bits 3?2 this field is used to set the interr upt priority level for irqs. this irq is limited to prio rities 0 through 2. they are disabled by default. ? 00 = irq disabled (default) ? 01 = irq is priority level 0 ? 10 = irq is priority level 1 ? 11 = irq is priority level 2 5.6.8.8 timer c, channel 1 interr upt priority level (tm rc1 ipl)?bits 1?0 this field is used to set the interr upt priority level for irqs. this irq is limited to prio rities 0 through 2. they are disabled by default. ? 00 = irq disabled (default) ? 01 = irq is priority level 0 ? 10 = irq is priority level 1 ? 11 = irq is priority level 2 5.6.9 interrupt priority register 8 (ipr8) figure 5-11 interrupt priority register 8 (ipr8) 5.6.9.1 sci0 receiver full interrupt priority level (sci0_rcv ipl)?bits 15?14 this field is used to set the interr upt priority level for irqs. this irq is limited to prio rities 0 through 2. they are disabled by default. ? 00 = irq disabled (default) ? 01 = irq is priority level 0 ? 10 = irq is priority level 1 ? 11 = irq is priority level 2 5.6.9.2 sci0 receiver error inte rrupt priority level (sci0_rerr ipl)? bits 13?12 this field is used to set the interr upt priority level for irqs. this irq is limited to prio rities 0 through 2. they are disabled by default. ? 00 = irq disabled (default) ? 01 = irq is priority level 0 ? 10 = irq is priority level 1 ? 11 = irq is priority level 2 base + $8 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read sci0_rcv ipl sci0_rerr ipl 0 0 sci0_tidl ipl sci0_xmit ipl tmra3 ipl tmra2 ipl tmra1 ipl write reset 0000000000000000
register descriptions 56f8367 technical data, rev. 7.0 freescale semiconductor 99 preliminary 5.6.9.3 reserved?bits 11?10 this bit field is reserved or not implemented. it is read as 0 a nd cannot be modified by writing. 5.6.9.4 sci0 transmitter idle interrupt priority level (sci0_ tidl ipl)?bits 9?8 this field is used to set the interr upt priority level for irqs. this irq is limited to prio rities 0 through 2. they are disabled by default. ? 00 = irq disabled (default) ? 01 = irq is priority level 0 ? 10 = irq is priority level 1 ? 11 = irq is priority level 2 5.6.9.5 sci0 transmitter empty inte rrupt priority level (sci0_xmit ipl)? bits 7?6 this field is used to set the interr upt priority level for irqs. this irq is limited to prio rities 0 through 2. they are disabled by default. ? 00 = irq disabled (default) ? 01 = irq is priority level 0 ? 10 = irq is priority level 1 ? 11 = irq is priority level 2 5.6.9.6 timer a, channel 3 interr upt priority level (tm ra3 ipl)?bits 5?4 this field is used to set the interr upt priority level for irqs. this irq is limited to prio rities 0 through 2. they are disabled by default. ? 00 = irq disabled (default) ? 01 = irq is priority level 0 ? 10 = irq is priority level 1 ? 11 = irq is priority level 2 5.6.9.7 timer a, channel 2 interr upt priority level (tm ra2 ipl)?bits 3?2 this field is used to set the interr upt priority level for irqs. this irq is limited to prio rities 0 through 2. they are disabled by default. ? 00 = irq disabled (default) ? 01 = irq is priority level 0 ? 10 = irq is priority level 1 ? 11 = irq is priority level 2
56f8367 technical data, rev. 7.0 100 freescale semiconductor preliminary 5.6.9.8 timer a, channel 1 interr upt priority level (tm ra1 ipl)?bits 1?0 this field is used to set the interr upt priority level for irqs. this irq is limited to prio rities 0 through 2. they are disabled by default. ? 00 = irq disabled (default) ? 01 = irq is priority level 0 ? 10 = irq is priority level 1 ? 11 = irq is priority level 2 5.6.10 interrupt priority register 9 (ipr9) figure 5-12 interrupt priority register 9 (ipr9) 5.6.10.1 pwm a fault interrupt pri ority level (pwma_f ipl)?bits 15?14 this field is used to set the interr upt priority level for irqs. this irq is limited to prio rities 0 through 2. they are disabled by default. ? 00 = irq disabled (default) ? 01 = irq is priority level 0 ? 10 = irq is priority level 1 ? 11 = irq is priority level 2 5.6.10.2 pwm b fault interrupt pri ority level (pwmb_f ipl)?bits 13?12 this field is used to set the interr upt priority level for irqs. this irq is limited to prio rities 0 through 2. they are disabled by default. ? 00 = irq disabled (default) ? 01 = irq is priority level 0 ? 10 = irq is priority level 1 ? 11 = irq is priority level 2 5.6.10.3 reload pwm a i nterrupt priority level (pwma_rl ipl)?bits 11?10 this field is used to set the interr upt priority level for irqs. this irq is limited to prio rities 0 through 2. they are disabled by default. ? 00 = irq disabled (default) ? 01 = irq is priority level 0 ? 10 = irq is priority level 1 ? 11 = irq is priority level 2 base + $9 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read pwma_f ipl pwmb_f ipl pwma_rl ipl pwm_rl ipl adca_zc ipl abcb_zc ipl adca_cc ipl adcb_cc ipl write reset 0000000000000000
register descriptions 56f8367 technical data, rev. 7.0 freescale semiconductor 101 preliminary 5.6.10.4 reload pwm b interrupt priority level (pwmb_rl ipl)?bits 9?8 this field is used to set the interr upt priority level for irqs. this irq is limited to prio rities 0 through 2. they are disabled by default. ? 00 = irq disabled (default) ? 01 = irq is priority level 0 ? 10 = irq is priority level 1 ? 11 = irq is priority level 2 5.6.10.5 adc a zero crossing or limit error interrupt priority level (adca_zc ipl)?bits 7?6 this field is used to set the interr upt priority level for irqs. this irq is limited to prio rities 0 through 0. they are disabled by default. ? 00 = irq disabled (default) ? 01 = irq is priority level 0 ? 10 = irq is priority level 1 ? 11 = irq is priority level 2 5.6.10.6 adc b zero crossing or limit error interrupt priority level (adcb_zc ipl)?bits 5?4 this field is used to set the interr upt priority level for irqs. this irq is limited to prio rities 0 through 2. they are disabled by default. ? 00 = irq disabled (default) ? 01 = irq is priority level 0 ? 10 = irq is priority level 1 ? 11 = irq is priority level 2 5.6.10.7 adc a conversion comp lete interrupt priority level (adca_cc ipl)?bits 3?2 this field is used to set the interr upt priority level for irqs. this irq is limited to prio rities 0 through 2. they are disabled by default. ? 00 = irq disabled (default) ? 01 = irq is priority level 0 ? 10 = irq is priority level 1 ? 11 = irq is priority level 2
56f8367 technical data, rev. 7.0 102 freescale semiconductor preliminary 5.6.10.8 adc b conversion comp lete interrupt priority level (adcb_cc ipl)?bits 1?0 this field is used to set the interr upt priority level for irqs. this irq is limited to prio rities 0 through 2. they are disabled by default. ? 00 = irq disabled (default) ? 01 = irq is priority level 0 ? 10 = irq is priority level 1 ? 11 = irq is priority level 2 5.6.11 vector base address register (vba) figure 5-13 vector base address register (vba) 5.6.11.1 reserved?bits 15?13 this bit field is reserved or not implemented. it is read as 0 a nd cannot be modified by writing. 5.6.11.2 interrupt vector base address (vector base address)? bits 12?0 the contents of this register determ ine the location of the vector addre ss table. the value in this register is used as the upper 13 bi ts of the interrupt vector address bus (vab[20:0]). the lo wer eight bits are determined based upon the highest-pri ority interrupt. they are then a ppended onto vba be fore presenting the full vab to the 56800e core; see part 5.3.1 for details. 5.6.12 fast interrupt 0 match register (fim0) figure 5-14 fast interrupt 0 match register (fim0) 5.6.12.1 reserved?bits 15?7 this bit field is reserved or not implemented. it is read as 0 a nd cannot be modified by writing. 5.6.12.2 fast interrupt 0 vector number (fast inte rrupt 0)?bits 6?0 this value determines which irq will be a fast interrupt 0. fast interrupts vector directly to a service routine based on values in the fast interrupt vector address registers without having to go to a jump table first; see part 5.3.3 . irqs used as fast interrupts must be set to priority level 2. unexpected results will base + $a 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read 0 0 0 vector base address write reset 0000000000000000 base + $b 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read 0 0 0 0 0 0 0 0 0 fast interrupt 0 write reset 0000000000000000
register descriptions 56f8367 technical data, rev. 7.0 freescale semiconductor 103 preliminary occur if a fast interrupt vector is set to any other priority. fast interrupts automatically become the highest-priority level 2 interrupt, regardless of their lo cation in the interrupt tabl e, prior to being declared as fast interrupt. fast interrupt 0 has priority over fast interrupt 1. to determine the vector number of each irq, refer to table 4-5 . 5.6.13 fast interrupt 0 vector address low register (fival0) figure 5-15 fast interrupt 0 vect or address low register (fival0) 5.6.13.1 fast interrupt 0 vector address low (fi val0)?bits 15?0 the lower 16 bits of the vector a ddress are used for fast interrupt 0. this register is combined with fivah0 to form the 21-bit vector address for fa st interrupt 0 defined in the fim0 register. 5.6.14 fast interrupt 0 vector address high register (fivah0) figure 5-16 fast interr upt 0 vector address high register (fivah0) 5.6.14.1 reserved?bits 15?5 this bit field is reserved or not implemented. it is read as 0 a nd cannot be modified by writing. 5.6.14.2 fast interrupt 0 vector address high (fi vah0)?bits 4?0 the upper five bits of the vector a ddress are used for fast interrupt 0. this regi ster is combined with fival0 to form the 21-bit vect or address for fast interrupt 0 defined in the fim0 register. 5.6.15 fast interrupt 1 match register (fim1) figure 5-17 fast interrupt 1 match register (fim1) 5.6.15.1 reserved?bits 15?7 this bit field is reserved or not implemented. it is read as 0, but cannot be modified by writing. base + $c 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read fast interrupt 0 vector address low write reset 0000000000000000 base + $d 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read 0 0 0 0 0 0 0 0 0 0 0 fast interrupt 0 vector address high write reset 0000000000000000 base + $e 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read 0 0 0 0 0 0 0 0 0 fast interrupt 1 write reset 0000000000000000
56f8367 technical data, rev. 7.0 104 freescale semiconductor preliminary 5.6.15.2 fast interrupt 1 vector number (fast inte rrupt 1)?bits 6?0 this value determines which irq will be a fast interrupt 1. fast interrupts vector directly to a service routine based on values in the fast interrupt vector address registers without having to go to a jump table first; see part 5.3.3 . irqs used as fast interrupts must be set to priority level 2. unexpected results will occur if a fast interrupt vector is set to any other priority. fast interrupts automatically become the highest-priority level 2 interrupt, regardless of their lo cation in the interrupt tabl e, prior to being declared as fast interrupt. fast interrupt 0 has priority over fast interrupt 1. to determine the vector number of each irq, refer to table 4-5 . 5.6.16 fast interrupt 1 vector address low register (fival1) figure 5-18 fast interrupt 1 vect or address low register (fival1) 5.6.16.1 fast interrupt 1 vector address low (fi val1)?bits 15?0 the lower 16 bits of vector address are used for fast interrupt 1. this register is combined with fivah1 to form the 21-bit vector address for fast interrupt 1 defined in the fim1 register. 5.6.17 fast interrupt 1 vector address high register (fivah1) figure 5-19 fast interr upt 1 vector address high register (fivah1) 5.6.17.1 reserved?bits 15?5 this bit field is reserved or not implemented. it is read as 0 a nd cannot be modified by writing. 5.6.17.2 fast interrupt 1 vector address high (fi vah1)?bits 4?0 the upper five bits of vector address are used fo r fast interrupt 1. this regi ster is combined with fival1 to form the 21-bit vector address for fast interrupt 1 defined in the fim1 register. 5.6.18 irq pending 0 register (irqp0) figure 5-20 irq pending 0 register (irqp0) base + $f 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read fast interrupt 1 vector address low write reset 0000000000000000 base + $10 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read 0 0 0 0 0 0 0 0 0 0 0 fast interrupt 1 vector address high write reset 0000000000000000 base + $11 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read pending [16:2] 1 write reset 1111111111111111
register descriptions 56f8367 technical data, rev. 7.0 freescale semiconductor 105 preliminary 5.6.18.1 irq pending (pending)?bits 16?2 this register combines with the ot her five to represent th e pending irqs for inte rrupt vector numbers 2 through 81. ? 0 = irq pending for this vector number ? 1 = no irq pending for this vector number 5.6.18.2 reserved?bit 0 this bit is reserved or not implemented. it is read as 1 and cannot be modified by writing. 5.6.19 irq pending 1 register (irqp1) figure 5-21 irq pending 1 register (irqp1) 5.6.19.1 irq pending (pending)?bits 32?17 this register combines with the ot her five to represent th e pending irqs for inte rrupt vector numbers 2 through 81. ? 0 = irq pending for this vector number ? 1 = no irq pending for this vector number 5.6.20 irq pending 2 register (irqp2) figure 5-22 irq pending 2 register (irqp2) 5.6.20.1 irq pending (pending)?bits 48?33 this register combines with the ot her five to represent th e pending irqs for inte rrupt vector numbers 2 through 81. ? 0 = irq pending for this vector number ? 1 = no irq pending for this vector number $base + $12 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read pending [32:17] write reset 1111111111111111 base + $13 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read pending [48:33] write reset 1111111111111111
56f8367 technical data, rev. 7.0 106 freescale semiconductor preliminary 5.6.21 irq pending 3 register (irqp3) figure 5-23 irq pending 3 register (irqp3) 5.6.21.1 irq pending (pending)?bits 64?49 this register combines with the ot her five to represent th e pending irqs for inte rrupt vector numbers 2 through 81. ? 0 = irq pending for this vector number ? 1 = no irq pending for this vector number 5.6.22 irq pending 4 register (irqp4) figure 5-24 irq pending 4 register (irqp4) 5.6.22.1 irq pending (pending)?bits 80?65 this register combines with the ot her five to represent th e pending irqs for inte rrupt vector numbers 2 through 81. ? 0 = irq pending for this vector number ? 1 = no irq pending for this vector number 5.6.23 irq pending 5 register (irqp5) figure 5-25 irq pending register 5 (irqp5) 5.6.23.1 reserved?bits 96?86 this bit field is reserved or not implemented. the b its are read as 1 and cannot be modified by writing. base + $14 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read pending [64:49] write reset 1111111111111111 base + $15 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read pending [80:65] write reset 1111111111111111 base + $16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read 1 1 1 1 1 1 1 1 1 1 1 pending[85:81] write reset 111111111111111 1
register descriptions 56f8367 technical data, rev. 7.0 freescale semiconductor 107 preliminary 5.6.23.2 irq pending (pending)?bits 81?85 this register combines with the ot her five to represent th e pending irqs for inte rrupt vector numbers 2 through 85. ? 0 = irq pending for this vector number ? 1 = no irq pending for this vector number 5.6.24 reserved ?base + 17 5.6.25 reserved? base + 18 5.6.26 reserved ?base + 19 5.6.27 reserved ?base + 1a 5.6.28 reserved ?base + 1b 5.6.29 reserved ?base + 1c 5.6.30 itcn control register (ictl) figure 5-26 itcn cont rol register (ictl) 5.6.30.1 interrupt (int)?bit 15 this read-only bit reflects the state of th e interrupt to the 56800e core. ? 0 = no interrupt is be ing sent to the 56800e core ? 1 = an interrupt is be ing sent to the 56800e core 5.6.30.2 interrupt priority level (ipic)?bits 14?13 these read-only bits reflect the state of the new interrupt priority level bits be ing presented to the 56800e core at the time the last irq wa s taken. this field is only updated when the 56800e core jumps to a new interrupt service routine. note: nested interrupts may cause this field to be update d before the original inte rrupt service routine can read it. ? 00 = required nested exception prio rity levels are 0, 1, 2, or 3 ? 01 = required nested exception pr iority levels are 1, 2, or 3 ? 10 = required nested exceptio n priority levels are 2 or 3 ? 11 = required nested exception priority level is 3 base + $1d 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read int ipic vab int_dis 1 irqb state irqa state irqb edg irqa edg write reset 0 0 0 1000000 0 1 1 1 0 0
56f8367 technical data, rev. 7.0 108 freescale semiconductor preliminary 5.6.30.3 vector number - vec tor address bus (vab)?bits 12?6 this read-only field shows the vector number (vab[7:1]) used at the time the last irq was taken. this field is only updated when the 56800e core ju mps to a new interrupt service routine. note: nested interrupts may cause this field to be update d before the original inte rrupt service routine can read it. 5.6.30.4 interrupt disable (int_dis)?bit 5 this bit allows all interrupts to be disabled. ? 0 = normal operation (default) ? 1 = all interrupts disabled 5.6.30.5 reserved?bit 4 this bit field is reserved or not implemented. it is read as 1 a nd cannot be modified by writing. 5.6.30.6 irqb state pin (irqb state)?bit 3 this read-only bit reflects the state of the external irqb pin. 5.6.30.7 irqa state pin (irqa state)?bit 2 this read-only bit reflects the state of the external irqa pin. 5.6.30.8 irqb edge pin (irqb edg)?bit 1 this bit controls whether the external irqb interrupt is edge- or level- sensitive. during stop and wait modes, it is automatically level-sensitive. ?0 = irqb interrupt is a low-le vel sensitive (default) ?1 = irqb interrupt is falling-edge sensitive 5.6.30.9 irqa edge pin (irqa edg)?bit 0 this bit controls whet her the external irqa interrupt is edge- or level-sensitive. during stop and wait modes, it is automatically level-sensitive. ?0 = irqa interrupt is a low-level sensitive (default) ?1 = irqa interrupt is falling-edge sensitive 5.6.31 reserved ?base + $1e 5.6.32 interrupt priority register 10 (ipr10) note: this register is not avai lable in the 56f8167 device. base + $1f 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read 0 0 0 0 0 0 0 0 flexcan2_ msgbuf ipl flexcan2_ wkup ipl flexcan2_ err ipl flexcan2_ boff ipl write reset 0001000000000000
register descriptions 56f8367 technical data, rev. 7.0 freescale semiconductor 109 preliminary 5.6.32.1 reserved?bits 15 - 8 this bit field is reserved or not implemented. it is read as 0 a nd cannot be modified by writing. 5.6.32.2 flexcan2 message buffer interrupt priority level (flexcan2_msgbuf ipl)?bits 7 - 6 this field is used to set the interr upt priority level for irqs. this irq is limited to prio rities 0 through 2. they are disabled by default. ? 00 = irq disabled (default) ? 01 = irq is priority level 0 ? 10 = irq is priority level 1 ? 11 = irq is priority level 2 5.6.32.3 flexcan2 wake up interr upt priority level (fl excan2_wkup ipl)? bits 5 - 4 this field is used to set the interr upt priority level for irqs. this irq is limited to prio rities 0 through 2. they are disabled by default. ? 00 = irq disabled (default) ? 01 = irq is priority level 0 ? 10 = irq is priority level 1 ? 11 = irq is priority level 2 5.6.32.4 flexcan2 error interrupt priorit y level (flexcan2_err ipl)?bits 3 - 2 this field is used to set the interr upt priority level for irqs. this irq is limited to prio rities 0 through 2. they are disabled by default. ? 00 = irq disabled (default) ? 01 = irq is priority level 0 ? 10 = irq is priority level 1 ? 11 = irq is priority level 2 5.6.32.5 flexcan2 bus-off interrupt priority level (flexcan2_boff ipl)? bits 1 - 0 this field is used to set the interr upt priority level for irqs. this irq is limited to prio rities 0 through 2. they are disabled by default. ? 00 = irq disabled (default) ? 01 = irq is priority level 0 ? 10 = irq is priority level 1 ? 11 = irq is priority level 2
56f8367 technical data, rev. 7.0 110 freescale semiconductor preliminary 5.7 resets 5.7.1 reset handshake timing the itcn provides the 56800e core with a reset vector addres s whenever reset is asserted. the reset vector will be presented until the second rising clock edge after reset is released. 5.7.2 itcn after reset after reset, all of the itcn regist ers are in their default states. this means all interrupts are disabled, except the core irqs wi th fixed priorities: ? illegal instruction ? sw interrupt 3 ? hw stack overflow ? misaligned long word access ? sw interrupt 2 ? sw interrupt 1 ? sw interrupt 0 ? sw interrupt lp these interrupts are enabled at their fixed priority levels.
overview 56f8367 technical data, rev. 7.0 freescale semiconductor 111 preliminary part 6 system integration module (sim) 6.1 overview the sim module is a system catchall for the glue logic that ties together the system-on-chip. it controls distribution of resets and clocks and provides a number of control feat ures. the system integration module is responsible for the following functions: ? reset sequencing ? clock generation & distribution ? stop/wait control ? pull-up enables for selected peripherals ? system status registers ? registers for software access to the jtag id of the chip ? enforcing flash security these are discussed in more detail in the sections that follow. 6.2 features the sim has the following features: ? flash security feature prevents unauthorized ac cess to code/data contained in on-chip flash memory ? power-saving clock gating for peripheral ? three power modes (run, wait, st op) to control power utilization ? stop mode shuts down 56800e core, system clock, peripheral clock, and pll operation ? stop mode entry can optionally disable pll and oscilla tor (low power vs. fast restart); must be done explicitly ? wait mode shuts down the 56800e core, and unnecessary system clock operation ? run mode supports full part operation ? controls to enable/disable the 5680 0e core wait and stop instructions ? calculates base delay for reset extension based upon por or r eset operations. reset delay will be either 3 x 32 clocks for reset, except for por, which is 2 21 clock cycles. ? controls reset sequencing after reset ? software-initiated reset ? four 16-bit registers reset only by a power-on r eset usable for general purpose software control ? system control register ? registers for software access to the jtag id of the chip
56f8367 technical data, rev. 7.0 112 freescale semiconductor preliminary 6.3 operating modes since the sim is responsible for di stributing clocks and re sets across the chip, it must understand the various chip operating modes and ta ke appropriate action. these are: ? reset mode, which has two submodes: ? por and reset operation the 56800e core and all peripherals are reset. this occurs when the internal por is asserted or the reset pin is asserted. ? cop reset and software reset operation the 56800e core and all peripherals are reset. the ma bit within the omr is not changed. this allows the software to determine the boot mode (internal or external boot) to be used on the next reset. ? run mode this is the primary mode of opera tion for this device. in this mode, the 56800e co ntrols chip operation ? debug mode the 56800e is controlled via jtag/eonce when in debug mode. all peripherals, except the cop and pwms, continue to run. cop is disabled and pwm outputs are optionally switched off to disable any motor from being driven; see the pwm chapter in the 56f8300 peripheral user manual for details. ? wait mode in wait mode, the core clock and memory clocks are disabled. optionally, the cop can be stopped. similarly, it is an option to switch off pwm output s to disable any motor from being driven. all other peripherals continue to run. ? stop mode when in stop mode, the 56800e core, memory, and most peripheral clocks are shut down. optionally, the cop and can can be stopped. for lowest power cons umption in stop mode, the pll can be shut down. this must be done explicitly before entering stop mode, since there is no automatic mech anism for this. the can (along with any non-gated interru pt) is capable of waking the chip up from stop mode, but is not fully functional in stop mode. 6.4 operating mode register figure 6-1 omr the reset state for mb a nd ma will depend on the fl ash secured state. see part 4.2 and part 7 for detailed information on how the operating mode register (omr) ma a nd mb bits operate in this device. for all other bits, see the dsp56800e reference manual . note: the omr is not a memory map regi ster; it is directly accessible in code through the acronym omr. bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 nl cm xp sd r sa ex 0 mb ma type r/w r/w r/w r/w r/w r/w r/w r/w r/w reset 00000000000000xx
register descriptions 56f8367 technical data, rev. 7.0 freescale semiconductor 113 preliminary 6.5 register descriptions table 6-1 sim registers (sim_base = $00 f350) address offset address acronym register name section location base + $0 sim_control control register 6.5.1 base + $1 sim_rststs reset status register 6.5.2 base + $2 sim_scr0 softwa re control register 0 6.5.3 base + $3 sim_scr1 softwa re control register 1 6.5.3 base + $4 sim_scr2 softwa re control register 2 6.5.3 base + $5 sim_scr3 softwa re control register 3 6.5.3 base + $6 sim_msh_id most si gnificant half of jtag id 6.5.4 base + $7 sim_lsh_id least significant half of jtag id 6.5.5 base + $8 sim_pudr pull-up disable register 6.5.6 reserved base + $a sim_clkosr cl ko select register 6.5.7 base + $b sim_gps gpio peripheral select register 6.5.8 base + $c sim_pce peripheral clock enable register 6.5.9 base + $d sim_isalh i/o short address location high register 6.5.10 base + $e sim_isall i/o short address location low register 6.5.10 base + $f sim_pce2 peripheral clock enable register 2 6.5.11
56f8367 technical data, rev. 7.0 114 freescale semiconductor preliminary 6.5.1 sim control regi ster (sim_control) figure 6-3 sim control re gister (sim_control) 6.5.1.1 reserved?bits 15?7 this bit field is reserved or not implemented. it is read as 0 a nd cannot be modified by writing. add. offset register name 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 $0 sim_ control r 0 0 0 0 0 0 0 0 0 emi_ mode once ebl 0 sw rst stop_ disable wait_ disable w $1 sim_ rststs r 0 0 0 0 0 0 0 0 0 0 swr copr extr por 0 0 w $2 sim_scr0 r field w $3 sim_scr1 r field w $4 sim_scr2 r field w $5 sim_scr3 r field w $6 sim_msh_ id r 0 0 0 0 0 0 0 1 1 1 0 1 0 1 1 0 w $7 sim_lsh_id r 1 1 0 1 0 0 0 0 0 0 0 1 1 1 0 1 w $8 sim_pudr r 0 pwma 1 can emi_ mode reset irq xboot pwmb pwma 0 0 ctrl 0 jtag 0 0 0 w reserved $a sim_ clkosr r 0 0 0 0 0 0 a23 a22 a21 a20 clkdis clkosel w $b sim_gps r 0 0 0 0 0 0 0 0 0 0 d1 d0 c3 c2 c1 c0 w $c sim_pce r emi adcb adca can dec1 dec0 tmrd tmrc tmrb tmra sci1 sci0 spi1 spi0 pwm b pwm a w $d sim_isalh r 1 1 1 1 1 1 1 1 1 1 1 1 1 1 isal[23:22] w $e sim_isall r isal[21:6] w $f sim_pce2 r 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 can2 w = reserved figure 6-2 sim register map summary base + $0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read 0 0 0 0 0 0 0 0 0 emi_ mode once ebl sw rst stop_ disable wait_ disable write reset 0000000000 000000
register descriptions 56f8367 technical data, rev. 7.0 freescale semiconductor 115 preliminary 6.5.1.2 emi_mode (emi_mode)?bit 6 this bit reflects the current (non-cloc ked) state of the emi_mode pin. du ring reset, this bit, coupled with the extboot signal, is used to initia lize address bits [1 9:16] either as gpio or as address. these settings can be explicitly overwritten using th e appropriate gpio peripheral enable register at any time after reset. in addition, this pin can be used as a general purpose input pin after reset. ? 0 = external address bits [19:16 ] are initially programmed as gpio ? 1 = when booted with extboot = 1, a[19:16] ar e initially programmed as address. if extboot is 0, they are initialized as gpio. 6.5.1.3 once enable (once ebl)?bit 5 ? 0 = once clock to 56800e core en abled when core tap is enabled ? 1 = once clock to 56800e core is always enabled 6.5.1.4 software reset (sw rst)?bit 4 this bit is always read as 0. writing a 1 to this bit will cause the part to reset. 6.5.1.5 stop disable (s top_disable)?bits 3?2 ? 00 - stop mode will be entered when th e 56800e core executes a stop instruction ? 01 - the 56800e stop instruction will not caus e entry into stop mode; stop_disable can be reprogrammed in the future ? 10 - the 56800e stop instruction will not cause entr y into stop mode; stop_disable can then only be changed by resetting the device ? 11 - same operation as 10 6.5.1.6 wait disable (wait_disable)?bits 1?0 ? 00 - wait mode will be entered when the 56 800e core executes a wait instruction ? 01 - the 56800e wait instruction will not ca use entry into wait mode; wait_disable can be reprogrammed in the future ? 10 - the hawkv2 wait instruction will not cause entry into wait mode; wait_disable can then only be changed by re setting the device ? 11 - same operation as 10 6.5.2 sim reset status register (sim_rststs) bits in this register are set upon any system reset and are initialized only by a power-on reset (por). a reset (other than por) will only set bits in the regist er; bits are not cleared. only software should clear this register. figure 6-4 sim reset status register (sim_rststs) base + $1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read 0 0 o 0 0 0 0 0 0 0 swr copr extr por 0 0 write reset 0000000000 00
56f8367 technical data, rev. 7.0 116 freescale semiconductor preliminary 6.5.2.1 reserved?bits 15?6 this bit field is reserved or not implemented. it is read as 0 a nd cannot be modified by writing. 6.5.2.2 software reset (swr)?bit 5 when 1, this bit indicates that the pr evious reset occurred as a result of a software reset (write to sw rst bit in the sim_control register). this bit will be cleared by any hardware reset or by software. writing a 0 to this bit position will set the bit, while writing a 1 to the bit will clear it. 6.5.2.3 cop reset (copr)?bit 4 when 1, the copr bit indicates the computer operating properly (cop) timer-gene rated reset has occurred. this bit will be cleared by a power-on reset or by software. writing a 0 to this bit position will set the bit, while writing a 1 to the bit will clear it. 6.5.2.4 external reset (extr)?bit 3 if 1, the extr bit indicates an exte rnal system reset has occurred. this bit will be cleared by a power-on reset or by software. writin g a 0 to this bit position will set the bit, while writ ing a 1 to the bit position will clear it. basically, when the extr bit is 1, th e previous system reset was caused by the external reset pin being asserted low. 6.5.2.5 power-on reset (por)?bit 2 when 1, the por bit indicates a powe r-on reset occurred some time in the past. this bit can only be cleared by software or by another type of reset. writ ing a 0 to this bit will se t the bit while writing a 1 to the bit position will clear the bit. in summary, if th e bit is 1, the previous sy stem reset was due to a power-on reset. 6.5.2.6 reserved?bits 1?0 this bit field is reserved or not implemented. it is read as 0 a nd cannot be modified by writing. 6.5.3 sim software cont rol registers (sim_scr0, sim_scr1, sim_scr2, and sim_scr3) only sim_scr0 is shown below. sim_scr1, sim_scr2, and sim_scr3 are identical in functionality. figure 6-5 sim software cont rol register 0 (sim_scr0) 6.5.3.1 software control data 1 (field)?bits 15?0 this register is reset only by th e power-on reset (por). it has no part-specific functionality and is intended for use by a software develope r to contain data that will be unaffected by the other re set sources (reset pin, software reset, and cop reset). base + $2 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read field write por 0 0 0 0 0 0 0 0000 0 0000
register descriptions 56f8367 technical data, rev. 7.0 freescale semiconductor 117 preliminary 6.5.4 most significant half of jtag id (sim_msh_id) this read-only register displays the most significant half of the jtag id for the ch ip. this register reads $01d6. figure 6-6 most significant ha lf of jtag id (sim_msh_id) 6.5.5 least significant half of jtag id (sim_lsh_id) this read-only register displays th e least significant half of the jtag id for the chip. this register reads $d01d. figure 6-7 least significant ha lf of jtag id (sim_lsh_id) 6.5.6 sim pull-up disable register (sim_pudr) most of the pins on the chip have on-chip pull-up resi stors. pins which can operat e as gpio can have these resistors disabled via the gpio fu nction. non-gpio pins can have th eir pull-ups disabled by setting the appropriate bit in this re gister. disabling pull-ups is done on a peripheral-by-per ipheral basis (for pins not muxed with gpio). each bit in the register (see figure 6-8 ) corresponds to a functi onal group of pins. see table 2-2 to identify which pins can deactivate the internal pull-up resistor. figure 6-8 sim pull-up disa ble register (sim_pudr) 6.5.6.1 reserved ?bit 15 this bit field is reserved or not implemented. it is read as 0 a nd cannot be modified by writing. 6.5.6.2 pwma1?bit 14 this bit controls the pull-up resistors on the faulta3 pin. base + $6 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read 0 0 0 0 0 0 0 1 1 1 0 1 0 1 1 0 write reset 0 0 0 0 0 0 0 1110 1 0110 base + $7 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read 1 1 0 1 0 0 0 0 0 0 0 1 1 1 0 1 write reset 1 1 0 1 0 0 0 0000 1 1101 base + $8 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read 0 pwma1 can emi_ mode reset irq xboot pwmb pwma0 0 ctrl 0 jtag 000 write reset 0000 000 0 0 0000000
56f8367 technical data, rev. 7.0 118 freescale semiconductor preliminary 6.5.6.3 can?bit 13 this bit controls the pull-up resistors on the can_rx pin. 6.5.6.4 emi_mode?bit 12 this bit controls the pull-up resistors on the emi_mode pin. 6.5.6.5 reset ?bit 11 this bit controls the pull-up resistors on the reset pin. 6.5.6.6 irq?bit 10 this bit controls the pull-up resistors on the irqa and irqb pins. 6.5.6.7 xboot?bit 9 this bit controls the pull-up resistors on the extboot pin. note: in this package, this input pin is double-bonded with the adjacent v ss pin and this bit should be changed to a 1 in order to reduce power consumption. 6.5.6.8 pwmb?bit 8 this bit controls the pull-up resistors on th e faultb0, faultb1, fau ltb2, and faultb3 pins. 6.5.6.9 pwma0?bit 7 this bit controls the pull-up resistors on the faulta0, faulta1, and faulta2 pins. 6.5.6.10 reserved?bit 6 this bit field is reserved or not implemented. it is read as 0 a nd cannot be modified by writing. 6.5.6.11 ctrl?bit 5 this bit controls the pull-up resistors on the wr and rd pins. 6.5.6.12 reserved?bit 4 this bit field is reserved or not implemented. it is read as 0 a nd cannot be modified by writing. 6.5.6.13 jtag?bit 3 this bit controls the pull-up resistors on the trst , tms and tdi pins. 6.5.6.14 reserved?bit 2?0 this bit field is reserved or not implemented. it is read as 0 a nd cannot be modified by writing. 6.5.7 clko select re gister (sim_clkosr) the clko select register can be used to multiplex out any one of the clocks generated inside the clock generation and sim modules. the default value is sys_clk. all ot her clocks primarily muxed out are for test purposes only, and are subject to significant phase shift at high frequencies.
register descriptions 56f8367 technical data, rev. 7.0 freescale semiconductor 119 preliminary the upper four bits of the gpiob register can function as gpio, [a23: 20], or as additional clock output signals. gpio has priority and is enabled/disabled via the gpiob_ per. if gpiob[7:4] are programmed to operate as peripheral outputs, then the choice between [a23:20] and additi onal clock outputs is done here in the clkosr. the default st ate is for the peripheral function of gpiob[7:4] to be programmed as [a23:20]. this can be changed by altering [a23:20] as shown in figure 6-9 . figure 6-9 clko select register (sim_clkosr) 6.5.7.1 reserved?bits 15?10 this bit field is reserved or not implemented. it is read as 0 a nd cannot be modified by writing. 6.5.7.2 alternate gpiob peripher al function for a23 (a23)?bit 9 ? 0 = peripheral output function of gpiob7 is defined to be a23 ? 1 = peripheral output function of gpiob7 is defined to be the oscillator_clock (mstr_osc in figure 3-4 ) 6.5.7.3 alternate gpiob peripher al function for a22 (a22)?bit 8 ? 0 = peripheral output function of gpiob6 is defined to be a22 ? 1 = peripheral output function of gpiob6 is defined to be sys_clk2 6.5.7.4 alternate gpiob peripher al function for a21 (a21)?bit 7 ? 0 = peripheral output function of gpiob5 is defined to be a21 ? 1 = peripheral output function of gpiob5 is defined to be sys_clk 6.5.7.5 alternate gpiob peripher al function fpr a20 (a20)?bit 6 ? 0 = peripheral output function of gpiob4 is defined to be a20 ? 1 = peripheral output function of gpiob4 is defined to be the prescaler_clock (fref in figure 3-4 ) 6.5.7.6 clockout disable (clkdis)?bit 5 ? 0 = clkout output is enabled and will output the signal indicated by clkosel ? 1 = clkout is tri-stated 6.5.7.7 clockout select (clkosel)?bits 4?0 selects clock to be muxed out on the clko pin. ? 00000 = sys_clk (from occs - default) ? 00001 = reserved for factory test?56800e clock ? 00010 = reserved for factory test?xram clock ? 00011 = reserved for factory test?pflash odd clock base + $a 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read 0 0 0 0 0 0 a23 a22 a21 a20 clk dis clkosel write reset 0 0 0 0 0 0 0 0001 0 0000
56f8367 technical data, rev. 7.0 120 freescale semiconductor preliminary ? 00100 = reserved for factory test?pflash even clock ? 00101 = reserved for factory test?bflash clock ? 00110 = reserved for factory test?dflash clock ? 00111 = oscillator output ? 01000 = f out (from occs) ? 01001 = reserved for factory test?ipb clock ? 01010 = reserved for factory test?feedb ack (from occs, this is path to pll) ? 01011 = reserved for factory test?prescaler clock (from occs) ? 01100 = reserved for factory test?postscaler clock (from occs) ? 01101 = reserved for fact ory test?sys_clk2 (from occs) ? 01110 = reserved for factory test?sys_clk_div2 ? 01111 = reserved for factory test?sys_clk_d ? 10000 = adca clock ? 10001 = adcb clock 6.5.8 gpio peripheral sel ect register (sim_gps) some gpio pads can have more than one peripheral selected as the alternate function instead of gpio. for these pads, this regist er selects which of the al ternate peripherals are actua lly selected for the gpio peripheral function. this app lies to gpioc, pins 0-3, an d to gpiod, pins 0 and 1. the gpioc peripheral select regist er can be used to multiplex out any one of the three alternate peripherals for gpioc. the default peripheral is quad decoder 1 and quad timer b ( not available in the 56f8167 device ); these peripherals work together. the four i/o pins associated with gpioc can function as gpio, quad decoder 1/quad timerb , or as spi 1 signals. gpio is not the de fault and is enabled/disabled via the gpioc_per, as shown in figure 6-10 and table 6-2 . when gpioc[3:0] are programmed to operate as peripheral i/o, then the choice between decoder/timer and sp i inputs/outputs is made in the si m_gps register and in conjunction with the quad timer status and control registers (s cr). the default state is for the peripheral function of gpioc[3:0] to be programmed as decoder functions. this can be changed by alteri ng the appropriate controls in the indicated registers.
register descriptions 56f8367 technical data, rev. 7.0 freescale semiconductor 121 preliminary figure 6-10 overall control of gp ioc pads using sim_gps control two input/output pins associated with gpiod can function as gpio , emi (default peripheral) or can2 (not available on the 56f8167 device) signals. gpio is the default a nd is enabled/disabled via the gpiod_per, as shown in figure 6-11 and table 6-3 . when gpiod[1:0] are programmed to operate as peripheral input/output, then the choice between emi and can2 inputs/outputs is made here in the gps. table 6-2 control of gpioc pads using sim_gps control 1 1. this applies to the four pins that serve as quad decoder / quad timer / spi / gpioc functions. a separate set of control bits is used for each pin. pin function control registers comments gpioc_per gpioc_dtr sim_gps quad timer scr register oen bits gpio input 0 0 ? ? gpio output 0 1 ? ? quad timer input / quad decoder input 2 2. reset configuration 1 ? 0 0 see the ?switch matrix for inputs to the timer? table in the 56f8300 peripheral user manual for the definition of timer inputs based on the quad decoder mode configuration. quad timer output / quad decoder input 3 3. quad decoder pins are always inputs and function in conjunction with the quad timer pins. 1? 0 1 spi input 1 ? 1 ? see spi controls for determining the direction of each of the spi pins. spi output 1 ? 1 ? gpioc_per register gpio controlled i/o pad control sim_ gps register quad timer controlled spi controlled 0 1 0 1
56f8367 technical data, rev. 7.0 122 freescale semiconductor preliminary figure 6-11 overall control of gp iod pads using sim_gps control figure 6-12 gpio peripheral se lect register (sim_gps) 6.5.8.1 reserved?bits 15?6 this bit field is reserved or not implemented. it is read as 0 a nd cannot be modified by writing. table 6-3 control of gpiod pads using sim_gps control 1 1. this applies to the two pins that serve as emi csn / can2 / gpiod functions. a separate set of control bits is used for each pin. pin function control registers comments gpiod_per gpiod_ddr sim_gps gpio input 0 0 ? gpio output 0 1 ? emi i/o 1 ? 0 emi csn pins are always outputs can2 1 ? 1 can2_tx is always an output can2_rx is always an input base + $b 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read 0 0 0 0 0 0 0 0 0 0 d1 d0 c3 c2 c1 c0 write reset 000000000000 0 0 0 0 gpiod_per register gpio controlled i/o pad control sim_ gps register emi controlled can2 controlled 0 1 0 1
register descriptions 56f8367 technical data, rev. 7.0 freescale semiconductor 123 preliminary 6.5.8.2 gpiod1 (d1)?bit 5 this bit selects the alternate function for gpiod1. ?0 = cs3 ?1 = can2_rx 6.5.8.3 gpiod0 (d0)?bit 4 ?0 = cs2 ?1 = can2_tx 6.5.8.4 gpioc3 (c3)?bit 3 this bit selects the alternate function for gpioc3. ? 0 = home1/tb3 (default - see ?sw itch matrix mode? bits of the qu ad decoder deccr register in the 56f8300 peripheral user manual ) ? 1 = ss1 6.5.8.5 gpioc2 (c2)?bit 2 this bit selects the alternate function for gpioc2. ? 0 = index1/tb2 (default) ?1 = miso1 6.5.8.6 gpioc1 (c1)?bit 1 this bit selects the alternate function for gpioc1. ? 0 = phaseb1/tb1 (default) ?1 = mosi1 6.5.8.7 gpioc0 (c0)?bit 0 this bit selects the alternate function for gpioc0. ? 0 = phasea1/tb0 (default) ? 1 = sclk1 6.5.9 peripheral clock enable register (sim_pce) the peripheral clock enable register is used enable or disable cloc ks to the peripherals as a power savings feature. the clocks can be individually controlled for each peripheral on the chip. figure 6-13 peripheral clock en able register (sim_pce) base + $c 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read emi adcb adca can dec1 dec0 tmrd tmrc tmrb tmr a sci 1 sci 0 spi 1 spi 0 pwmb pwma write reset 11 111 1 1 1 1 1 1 1 1 1 1 1
56f8367 technical data, rev. 7.0 124 freescale semiconductor preliminary 6.5.9.1 external memory in terface enable (emi)?bit 15 each bit controls clocks to the indicated peripheral. ? 1 = clocks are enabled ? 0 = the clock is not provided to the peripheral (the peripheral is disabled) 6.5.9.2 analog-to-digital conv erter b enable (adcb)?bit 14 each bit controls clocks to the indicated peripheral. ? 1 = clocks are enabled ? 0 = the clock is not provided to the peripheral (the peripheral is disabled) 6.5.9.3 analog-to-digital conv erter a enable (adca)?bit 13 each bit controls clocks to the indicated peripheral. ? 1 = clocks are enabled ? 0 = the clock is not provided to the peripheral (the peripheral is disabled) 6.5.9.4 flexcan enable (can)?bit 12 each bit controls clocks to the indicated peripheral. ? 1 = clocks are enabled ? 0 = the clock is not provided to the peripheral (the peripheral is disabled) 6.5.9.5 decoder 1 enable (dec1)?bit 11 each bit controls clocks to the indicated peripheral. ? 1 = clocks are enabled ? 0 = the clock is not provided to the peripheral (the peripheral is disabled) 6.5.9.6 decoder 0 enable (dec0)?bit 10 each bit controls clocks to the indicated peripheral. ? 1 = clocks are enabled ? 0 = the clock is not provided to the peripheral (the peripheral is disabled) 6.5.9.7 quad timer d enable (tmrd)?bit 9 each bit controls clocks to the indicated peripheral. ? 1 = clocks are enabled ? 0 = the clock is not provided to the peripheral (the peripheral is disabled) 6.5.9.8 quad timer c enable (tmrc)?bit 8 each bit controls clocks to the indicated peripheral. ? 1 = clocks are enabled ? 0 = the clock is not provided to the peripheral (the peripheral is disabled)
register descriptions 56f8367 technical data, rev. 7.0 freescale semiconductor 125 preliminary 6.5.9.9 quad timer b enable (tmrb)?bit 7 each bit controls clocks to the indicated peripheral. ? 1 = clocks are enabled ? 0 = the clock is not provided to the peripheral (the peripheral is disabled) 6.5.9.10 quad timer a enable (tmra)?bit 6 each bit controls clocks to the indicated peripheral. ? 1 = clocks are enabled ? 0 = the clock is not provided to the peripheral (the peripheral is disabled) 6.5.9.11 serial communications interface 1 enable (sci1)?bit 5 each bit controls clocks to the indicated peripheral. ? 1 = clocks are enabled ? 0 = the clock is not provided to the peripheral (the peripheral is disabled) 6.5.9.12 serial communications interface 0 enable (sci0)?bit 4 each bit controls clocks to the indicated peripheral. ? 1 = clocks are enabled ? 0 = the clock is not provided to the peripheral (the peripheral is disabled) 6.5.9.13 serial peripheral i nterface 1 enable (spi1)?bit 3 each bit controls clocks to the indicated peripheral. ? 1 = clocks are enabled ? 0 = the clock is not provided to the peripheral (the peripheral is disabled) 6.5.9.14 serial peripheral i nterface 0 enable (spi0)?bit 2 each bit controls clocks to the indicated peripheral. ? 1 = clocks are enabled ? 0 = the clock is not provided to the peripheral (the peripheral is disabled) 6.5.9.15 pulse width mod ulator b enable (pwmb)?1 each bit controls clocks to the indicated peripheral. ? 1 = clocks are enabled ? 0 = the clock is not provided to the peripheral (the peripheral is disabled) 6.5.9.16 pulse width mod ulator a enable (pwma)?0 each bit controls clocks to the indicated peripheral. ? 1 = clocks are enabled ? 0 = the clock is not provided to the peripheral (the peripheral is disabled)
56f8367 technical data, rev. 7.0 126 freescale semiconductor preliminary 6.5.10 i/o short address location re gister (sim_isalh and sim_isall) the i/o short address locat ion registers are used to specify the memory refe renced via the i/o short address mode. the i/o short address m ode allows the instruction to spec ify the lower six bits of address; the upper address bits are not directly controllable. this register set allows limited control of the full address, as shown in figure 6-14 . note: if this register is set to something other than the top of memory (eonce register space) and the ex bit in the omr is set to 1, the jtag port cannot access the on-chip eonce register s, and debug functions will be affected. figure 6-14 i/o short address determination with this register set, an interrupt driver can set the sim_isall register pair to point to its peripheral registers and then use the i/o short addressing mode to reference them. the isr should restore this register to its previous contents prio r to returning from interrupt. note: the default value of this register set points to the eonce registers. note: the pipeline delay between setting this register set and using shor t i/o addressing with the new value is three cycles. figure 6-15 i/o short address locati on high register (sim_isalh) 6.5.10.1 input/output short addr ess low (isal[23:22])?bit 1?0 this field represents the upper two address bi ts of the ?hard code d? i/o short address. base + $d 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read 1 1 1 1 1 1 1 1 1 1 1 1 1 1 isal[23:22] write reset 111111 1 1 1111 1 1 11 instruction portion ? hard coded? address portion 6 bits from i/o short address mode instruction 16 bits from sim_isall register 2 bits from sim_isalh register full 24-bit for short i/o address
clock generation overview 56f8367 technical data, rev. 7.0 freescale semiconductor 127 preliminary figure 6-16 i/o short address lo cation low register (sim_isal) 6.5.10.2 input/output short addr ess low (isal[2 1:6])?bit 15?0 this field represents the lower 16 address bi ts of the ?hard code d? i/o short address. 6.5.11 peripheral clock enab le register 2 (sim_pce2) the peripheral clock enable register 2 is used to enable or disabl e clocks to the peripherals as a power-saving feaure. the clocks can be individua lly controller for each peripheral on the chip. 6.5.11.1 reserved?bits 15?1 this bit field is reserved or not implemented. it is read as 0 a nd cannot be modified by writing. 6.5.11.2 can2 enable?bit 0 each bit controls clocks to the indicated peripheral. ? 1 = clocks are enabled ? 0 = the clock is not provided to the peripheral (the peripheral is disabled) 6.6 clock generation overview the sim uses an internal master clock from the occs (clkgen) m odule to produce the peripheral and system (core and memory ) clocks. the maximum master clock frequency is 120mhz. peripheral and system clocks are generate d at half the master cl ock frequency and therefor e at a maximum 60mhz. the sim provides power modes (stop, wa it) and clock enables (sim_pce register, clk_dis, once_ebl) to control which clocks are in operation. the occs, power modes, a nd clock enables provide a flexible means to manage power consumption. power utilization can be minimized in several ways. in the occs, crysta l oscillator, and pll may be shut down when not in use. when the pll is in use, its prescaler and postscaler can be used to limit pll and master clock frequency. power modes permit system and/or peripheral clocks to be disabled when unused. clock enables provide the means to disable individual clocks. some pe ripherals provide further controls to disable unused sub-functions. refer to part 3 on-chip cloc k synthesis (occs) , and the 56f8300 peripheral user manual for further details. base + $e 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read isal[21:6] write reset 111111 1 1 1111 1 1 11 base + $d 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 can 2 write reset 000000 0 0 0000 0 0 01
56f8367 technical data, rev. 7.0 128 freescale semiconductor preliminary 6.7 power down modes overview the 56f8367/56f8167 operate in one of three power-down modes as shown in table 6-3 . all peripherals, except th e cop/watchdog timer, run of f the ipbus clock frequenc y, which is the same as the main processor frequency in this archit ecture. the maximum frequency of operation is sys_clk = 60mhz. refer to the pce register in part 6.5.9 and adc power modes. power is a function of the system frequency which can be controlled through the occs. 6.8 stop and wait mode disable function figure 6-17 stop disable circuit table 6-4 clock operati on in power down modes mode core clocks peripheral clocks description run active active device is fully functional wait core and memory clocks disabled active peripherals are active and can produce interrupts if they have not been masked off. interrupts will cause the core to come out of its suspended state and resume normal operation. typically used for power-conscious applications. stop system clocks conti nue to be ge nerated in the sim, but most are gated prior to reaching memory, core and peripherals. the only possible recoveries from stop mode are: 1. can traffic (1st message will be lost) 2. non-clocked interrupts 3. cop reset 4. external reset 5. power-on reset d-flop dq c d-flop d q c r 56800e stop_dis permanent disable reprogrammable disable clock select reset note: wait disable circuit is similar
resets 56f8367 technical data, rev. 7.0 freescale semiconductor 129 preliminary the 56800e core contains both stop and wait instructions. both put the cpu to sleep. for lowest power consumption in stop mode, the pll can be shut down. th is must be done explic itly before entering stop mode, since there is no au tomatic mechanism for this. when the pll is shut down, the 56800e system clock must be set e qual to the oscillator output. some applications require the 56800e stop/wait instructions be disabled. to disable those instructions, write to the sim control register (sim_control) described in part 6.5.1 . this procedure can be on either a permanen t or temporary basis. permanently assi gned applications la st only until their next reset. 6.9 resets the sim supports four sour ces of reset. the two as ynchronous sources are the ex ternal reset pin and the power-on reset (por). the two s ynchronous sources are the software reset, which is generated within the sim itself by writting to the sim_c ontrol register, and the cop reset. reset begins with the assertion of any of the reset sour ces. release of reset to various blocks is sequenced to permit proper operation of the device. a por reset is first extended for 2 21 clock cycles to permit stabilization of the clock source, followed by a 32 cl ock window in which sim clocking is initiated. it is then followed by a 32 clock window in which periphera ls are released to impl ement flash security, and, finally, followed by a 32 clock window in which the core is initialized. after completion of the described reset sequence, application code will begin execution. resets may be asserted asynchronous ly, but are always released internally on a rising edge of the system clock. part 7 security features the 56f8367/56f8167 offer security fe atures intended to prevent unauthorized users from reading the contents of the flash memory (fm) array. the flash security consists of several hardware interlocks that block the means by which an unauthorized user could gain access to the flash array. however, part of the security must lie with the user?s code. an extrem e example would be user?s code that dumps the contents of the internal program, as this code would defeat the purpose of security. at the same time, the user may also wi sh to put a ?backdoor? in his program. as an exampl e, the user downloads a security key through the sci, allo wing access to a programmi ng routine that updates parameters stored in another section of the flash. 7.1 operation with security enabled once the user has programmed the flash with his application code, the de vice can be secured by programming the security byt es located in the fm c onfiguration field, which o ccupies a portion of the fm array. these non-volatile bytes will keep the part secured through reset a nd through power-down of the device. only two bytes within this field are used to enable or disable security. re fer to the flash memory section in the 56f8300 peripheral user manual for the state of the security bytes and the resulting state
56f8367 technical data, rev. 7.0 130 freescale semiconductor preliminary of security. when flash security mode is enabled in ac cordance with the method described in the flash memory module specification, the de vice will disable external p-space accesses rest ricting code execution to internal memory, disable extboot=1 mode, and disable the core eonce debug capabilities. normal program execution is otherwise unaffected. 7.2 flash access blocking mechanisms the 56f8367/56f8167 have several operat ing functional and test modes. effective flash security must address operating mode sele ction and anticipate modes in which the on-chip flash can be compromised and read without explicit user pe rmission. methods to block these are outlined in the next subsections. 7.2.1 forced operating mode selection at boot time, the sim determines in which func tional modes the device will operate. these are: ? internal boot mode ? external boot mode ? secure mode when flash security is enabled as described in the flash memory module specification, the device will boot in internal boot mode, disable all access to external p-space, and start executing code from the boot flash at address 0x02_0000. this security affords protection only to applications in which the device operates in internal flash security mode. therefore, the security feature cannot be used unless al l executing code resides on-chip. when security is enabled, any atte mpt to override the default intern al operating mode by asserting the extboot pin in conjunction wi th reset will be ignored. 7.2.2 disabling eonce access on-chip flash can be read by issui ng commands across the eonce port, which is the debug interface for the 56800e core. the trst , tclk, tms, tdo, and td i pins comprise a jtag interface onto which the eonce port functionality is mapped. when the device boots, the chip-l evel jtag tap (test access port) is active and provides the chip?s boundary s can capability and access to the id register. proper implementation of flash security requires that no acce ss to the eonce port is provided when security is enabled. the 56800e core has an input which disa bles reading of internal memory via the jtag/eonce. the fm sets this input at reset to a value determined by the contents of the fm security bytes. 7.2.3 flash lockout recovery if a user inadvertently enables fl ash security on the devi ce, a built-in lockout re covery mechanism can be used to reenable access to the devi ce. this mechanism completely reases all on-chip flash, thus disabling flash security. access to this recovery mechanism is built into codewarrior via an instruction in memory configuration (. cfg ) files. add, or uncomment the following configuration command: unlock_flash_on_connect 1 for more information, please see codewarrior mc56f83xx/dsp5685x family targeting manual .
flash access blocking mechanisms 56f8367 technical data, rev. 7.0 freescale semiconductor 131 preliminary the lockout_recovery instruction ha s an associated 7-bit data re gister (dr) that is used to control the clock divider ci rcuit within the fm module. this divide r, fm_clkdiv[6:0], is used to control the period of the clock used for timed events in the fm erase algorithm. this re gister must be set with appropriate values before the lockout sequence can begin. refer to the jtag section of the 56f8300 peripheral user manual for more details on setting this register value. the value of the jtag fm_clk div[6:0] will replace th e value of the fm regist er fmclkd that divides down the system clock for time d events, as illustrated in figure 7-1 . fm_clkdiv[6] will map to the prdiv8 bit, and fm_clkdiv[5:0] will map to the div[5:0] bits. the combination of prdiv8 and div must divide the fm input clock down to a frequency of 150khz-200khz. the ?writing the fmclkd register ? section in the flash memory chapter of the 56f8300 peripheral user manual gives specific equations for calculati ng the correct values. figure 7-1 jtag to fm connection for lockout recovery two examples of fm_clk div calculations follow. example 1: if the system clock is the 8mhz crystal frequency because the pl l has not been set up, the input clock will be be low 12.8mhz, so prdiv8 = fm_clkdiv[6] = 0. using the following equation yields a div value of 19 for a clock of 200khz, and a div value of 20 for a clock of 190khz. this translates into an fm_clkdiv[6:0] value of $13 or $14, respectively. sys_clk jtag fmclkd divider 7 7 7 2 fm_clkdiv fm_erase flash memory clock input sys_clk (2) ) ( < < (div + 1) 150[khz] 200[khz]
56f8367 technical data, rev. 7.0 132 freescale semiconductor preliminary example 2: in this example, the system clock has been set up with a value of 32mhz, making the fm input clock 16mhz. because that is greater than 12.8mhz, prdiv8 = fm_cl kdiv[6] = 1. using the following equation yields a div value of 9 for a clock of 200khz, and a div value of 10 for a clock of 181khz. this translates to an fm_clkdiv[ 6:0] value of $49 or $4a, respectively. once the lockout_recovery instruction has been sh ifted into the instruct ion register, the clock divider value must be shifted into the corresponding 7- bit data register. after th e data register has been updated, the user must transition the tap controller into the r un-test/idle state for the lockout sequence to commence. the controller must remain in this state until the erase sequence has completed. for details, see the jtag section in the 56f8300 peripheral user manual . note: once the lockout recovery sequence has completed, the user must reset both the jtag tap controller (by asserting trst ) and the device (by asserting external chip reset ) to return to normal unsecured operation. 7.2.4 product analysis the recommended method of unsecuring a programmed device for product analys is of field failures is via the backdoor key access. the customer would need to supply technical support with the backdoor key and the protocol to acce ss the backdoor routine in the flash. a dditionally, the keyen bit that allows backdoor key access must be set. an alternative method for performing analysis on a s ecured microcontroller woul d be to mass-erase and reprogram the flash with the original code, but modify the security bytes. to insure that a customer does not inadvertently lo ck himself out of the devi ce during progr amming, it is recommended that he program the backdoor access key first, his applic ation code second, and the security bytes within the fm c onfiguration field last. part 8 general purpose input/output (gpio) 8.1 introduction this section is intended to supplemen t the gpio information found in the 56f8300 peripheral user manual and contains only chip-specific information. this information supe rcedes the generic information in the 56f8300 peripheral user manual . 8.2 memory maps the width of the gpio port defines how many bits are implemented in eac h of the gpio re gisters. based on this and the default function of each of the gpio pins, the re set values of the gpiox_pur and gpiox_per registers will ch ange from port to port. table 8-3 defines the actual re set values of these registers. sys_clk (2)(8) ) ( < < (div + 1) 150[khz] 200[khz]
configuration 56f8367 technical data, rev. 7.0 freescale semiconductor 133 preliminary 8.3 configuration there are six gpio ports defi ned on the 56f8367/56f8167. the width of each port and the associated peripheral function is shown in table 8-1 and table 8-2 . the specific mapping of gpio port pins is shown in table 8-3 . table 8-1 56f8367 gpio ports configuration gpio port port width available pins in 56f8367 peripheral function reset function a14 14 14 pins - emi address pins emi address b8 8 8 pins - emi address pins emi address c11 11 4 pins -dec1 / tmrb / spi1 4 pins -dec0 / tmra 3 pins -pwma current sense dec1 / tmrb dec0 / tmra pwma current sense d13 13 6 pins - emi csn 2 pins - sci1 2 pins - emi csn 3 pins -pwmb current sense emi chip selects sci1 emi chip selects pwmb current sense e14 14 2 pins - sci0 2 pins - emi address pins 4 pins - spi0 2 pins - tmrc 4 pins - tmrd sci0 emi address spi0 tmrc tmrd f16 16 16 pins - emi data emi data table 8-2 56f8167 gpio ports configuration gpio port port width available pins in 56f8167 peripheral function reset function a14 14 14 pins - emi address pins emi address b8 8 8 pins - emi address pins emi address c11 11 4 pins - spi1 4 pins - dec0 / tmra 3 pins - dedicated gpio spi1 dec0 / tmra gpio d13 13 6 pins - emi csn 2 pins - sci1 2 pins - emi csn 3 pins -pwmb current sense emi chip selects sci1 emi chip selects pwmb current sense
56f8367 technical data, rev. 7.0 134 freescale semiconductor preliminary e 14 14 2 pins - sci0 2 pins - emi address pins 4 pins - spi0 2 pins - tmrc 4 pins - dedicated gpio sci0 emi address spi0 tmrc gpio f16 16 16 pins - emi data emi data table 8-3 gpio external signals map pins in italics are not a vailable in the 56f8167 device gpio port gpio bit reset function functional signal package pin gpioa 0peripheral a8 19 1peripheral a9 20 2 peripheral a10 21 3 peripheral a11 22 4 peripheral a12 23 5 peripheral a13 24 6 peripheral a14 25 7 peripheral a15 26 8 peripheral a0 154 9peripheral a1 10 10 peripheral a2 11 11 peripheral a3 12 12 peripheral a4 13 13 peripheral a5 14 table 8-2 56f8167 gpio port s configuration (continued) gpio port port width available pins in 56f8167 peripheral function reset function
configuration 56f8367 technical data, rev. 7.0 freescale semiconductor 135 preliminary gpiob 0 gpio 1 a16 33 1 gpio 1 a17 34 2 gpio 1 a18 35 3 gpio 1 a19 36 4 gpio a20 / prescaler_clock 37 5 gpio a21 / sys_clk 46 6 gpio a22 / sys_clk2 47 7 gpio a23 / oscillator_clock 48 1 this is a function of the emi_mode, extbo ot, and flash security settings at reset. gpioc 0peripheral phasea1 / tb0 / sclk1 1 6 1peripheral phaseb1 / tb1 / mosi1 1 7 2peripheral index1 / tb2 / miso1 1 8 3peripheral home1 / tb3 / ssi1 1 9 4 peripheral phasea0 / ta0 155 5 peripheral phaseb0 / ta1 156 6 peripheral index0 / ta2 157 7 peripheral home0 / ta3 158 8peripheral isa0 126 9peripheral isa1 127 10 peripheral isa2 128 table 8-3 gpio external signals map (continued) pins in italics are not a vailable in the 56f8167 device gpio port gpio bit reset function functional signal package pin
56f8367 technical data, rev. 7.0 136 freescale semiconductor preliminary gpiod 0 gpio cs2 / can2_tx 55 1 gpio cs3 / can2_rx 56 2 gpio cs4 57 3 gpio cs5 58 4 gpio cs6 59 5 gpio cs7 60 6peripheral txd1 49 7peripheral rxd1 50 8peripheral ps / cs0 53 9peripheral ds / cs1 54 10 peripheral isb0 61 11 peripheral isb1 63 12 peripheral isb2 64 gpioe 0peripheral txd0 4 1peripheral rxd0 5 2peripheral a6 17 3peripheral a7 18 4 peripheral sclk0 146 5 peripheral mosi0 148 6 peripheral miso0 147 7 peripheral ss0 145 8 peripheral tc0 133 9 peripheral tc1 135 10 peripheral td0 129 11 peripheral td1 130 12 peripheral td2 131 13 peripheral td3 132 table 8-3 gpio external signals map (continued) pins in italics are not a vailable in the 56f8167 device gpio port gpio bit reset function functional signal package pin
56f8367 information 56f8367 technical data, rev. 7.0 freescale semiconductor 137 preliminary part 9 joint test action group (jtag) 9.1 56f8367 information please contact your freescale marketing representative or authorized distributor for device/package-specifi c bsdl information. gpiof 0peripheral d7 28 1peripheral d8 29 2peripheral d9 30 3 peripheral d10 32 4 peripheral d11 149 5 peripheral d12 150 6 peripheral d13 151 7 peripheral d14 152 8 peripheral d15 153 9peripheral d0 70 10 peripheral d1 71 11 peripheral d2 83 12 peripheral d3 86 13 peripheral d4 88 14 peripheral d5 89 15 peripheral d6 90 1. see part 6.5.8 to determine how to select peripherals from this set table 8-3 gpio external signals map (continued) pins in italics are not a vailable in the 56f8167 device gpio port gpio bit reset function functional signal package pin
56f8367 technical data, rev. 7.0 138 freescale semiconductor preliminary part 10 specifications 10.1 general characteristics the 56f8367/56f8167 are fabricated in high-density cmos with 5v-t olerant ttl-compatible digital inputs. the term ?5v-tolerant? refers to the capabili ty of an i/o pin, built on a 3.3v-compatible process technology, to withstand a voltage up to 5.5v without damaging the devi ce. many systems have a mixture of devices designed for 3.3v and 5v power supplies. in such syte ms, a bus may carry both 3.3v- and 5v-compatible i/o voltage levels (a standard 3.3v i/o is designed to receive a maximum voltage of 3.3v 10% during normal operation without causing damage). this 5v-tolerant capability therefore offers the power savings of 3.3v i/o levels combined with th e ability to receive 5v levels without damage. absolute maximum ratings in table 10-1 are stress ratings only, and f unctional operation at the maximum is not guaranteed. stress beyond these ratings may affect device reliabi lity or cause permanent damage to the device. note: all specifications meet both automotive and industria l requirements unless individual specifications are listed. note: the 56f8167 device is guaranteed to 40hmz and speci fied to meet industria l requirements only. caution this device contains protective circuitry to guard against damage due to high static voltage or electrical fields. however, normal precautions are advised to avoid application of any voltages higher than maximum-rated voltages to this high-impedance circuit. reliability of operation is enhanced if unused inputs are tied to an appropriate voltage level.
general characteristics 56f8367 technical data, rev. 7.0 freescale semiconductor 139 preliminary note: the 56f8167 device is specified to meet industrial requirements onl y; can is not available on the 56f8167 device. note: pins in italics are not available in the 56f8167 device. pin group 1: txd0-1, rxd0-1, ss0 , miso0, mosi0 pin group 2: phasea0, phasea1 , phaseb0, phaseb1 , index0, index1 , home0, home1 , isb0-2, isa0-2 , td2-3 , tc0-1, sclk0 pin group 3: rsto , tdo pin group 4: can_tx pin group 5: a0-5, d0-15, gpiod0-5, ps , ds pin group 6: a6-15, gpiob0-7, td0-1 pin group 7: clko, wr , rd pin group 8: pwma0-5, pwmb0-5 pin group 9: irqa , irqb , reset , extboot, trst , tms, tdi, can_rx , emi_mode, faulta0-3 , faultb0-3 pin group 10: tck pin group 11: xtal, extal pin group 12: ana0-7, anb0-7 pin group 13: ocr_dis, clkmode table 10-1 absolute maximum ratings (v ss = v ssa_adc = 0) characteristic symbol notes min max unit supply voltage v dd_io -0.3 4.0 v adc supply voltage v dda_adc, v refh v refh must be less than or equal to v dda_adc -0.3 4.0 v oscillator / pll supply voltage v dda_osc_pll -0.3 4.0 v internal logic core supply voltage v dd_core ocr_dis is high -0.3 3.0 v input voltage (digital) v in pin groups 1, 2, 5, 6, 9, 10 -0.3 6.0 v input voltage (analog) v ina pin groups 11, 12, 13 -0.3 4.0 v output voltage v out pin groups 1, 2, 3, 5, 6, 7, 8 -0.3 4.0 6.0 1 1. if corresponding gpio pin is configured as open drain. v output voltage (open drain) v od pin group 4 -0.3 6.0 v ambient temperature (automotive) t a -40 125 c ambient temperature (industrial) t a -40 105 c junction temperat ure (automotive) t j -40 150 c junction temperature (industrial) t j -40 125 c storage temperature (automotive) t stg -55 150 c storage temperature (industrial) t stg -55 150 c
56f8367 technical data, rev. 7.0 140 freescale semiconductor preliminary 1. theta-ja determined on 2s2p test boards is frequently lowe r than would be observed in an application. determined on 2s2p the r- mal test board. 2. junction to ambient thermal resistance, theta-ja (r ja ) was simulated to be equivalent to the jedec specification jesd51-2 in a horizontal configuration in natural c onvection. theta-ja was also simulated on a thermal test board with two internal plan es (2s2p, where ?s? is the number of signal layers and ?p? is the number of planes) per jesd51-6 and jesd51-7. the correct name for theta-ja for forced convection or with the non-single layer boards is theta-jma. 3. junction to case thermal resistance, theta-jc (r jc ), was simulated to be equivalent to the measured values using the cold plate technique with the cold plate temperature used as the "cas e" temperature. the basic cold plate measurement technique is described by mil-std 883d, method 1012.1. this is the correct thermal metric to use to calculate thermal performance when the package is being used with a heat sink. 4. thermal characterization parameter, psi-jt ( jt ), is the "resistance" from junction to reference point thermocouple on top cen- ter of case as defined in jesd51-2. jt is a useful value to use to estimate junction temperature in steady-state customer en- vironments. 5. junction temperature is a function of on-chip power dissipati on, package thermal resistance, mounting site (board) temperatu re, ambient temperature, air flow, power dissipation of other components on the board, and board thermal resistance. 6. see part 12.1 for more details on thermal design considerations. 7. tj = junction temperature ta = ambient temperature tbd = numbers will be available late q4 2005 table 10-2 56f8367/56f8167 electrostat ic discharge (esd) protection characteristic min typ max unit esd for human body model (hbm) 2000 ? ? v esd for machine model (mm) 200 ? ? v esd for charge device model (cdm) 500 ? ? v table 10-3 thermal characteristics 6 characteristic comments symbol value value unit notes 160-pin lqfp 160mapbga junction to ambient natural convection r ja 38.5 39.90 c/w 2 junction to ambient (@1m/sec) r jma 35.4 46.8 c/w 2 junction to ambient natural convection four layer board (2s2p) r jma (2s2p) 33 tbd c/w 1, 2 junction to ambient (@1m/sec) four layer board (2s2p) r jma (2s2p) 31.5 tbd c/w 1, 2 junction to case r jc 8.6 tbd c/w 3 junction to center of case jt 0.8 tbd c/w 4, 5 i/o pin power dissipation p i/o user-determined w power dissipation p d p d = (i dd x v dd + p i/o )w maximum allowed p d p dmax (tj - ta) / r ja 7 w
general characteristics 56f8367 technical data, rev. 7.0 freescale semiconductor 141 preliminary note: the 56f8167 device is guaranteed to 40hmz and speci fied to meet industria l requirements only; can is not available on the 56f8167 device. note: total chip source or sink current cannot exceed 200ma see pin groups in table 10-1 . table 10-4 recommended operating conditions (v reflo = 0v, v ss = v ssa_adc = 0v , v dda = v dda_adc = v dda_osc_pll ) characteristic symbol notes min typ max unit supply voltage v dd_io 33.33.6 v adc supply voltage v dda_adc v refh v refh must be less than or equal to v dda_adc 33.33.6 v oscillator / pll supply voltage v dda_osc _pll 33.33.6 v internal logic core supply voltage v dd_core ocr_dis is high 2.25 2.5 2.75 v device clock frequency fsysclk 0 ? 60 mhz input high voltage (digital) v ih pin groups 1, 2, 5, 6, 9, 10 2?5.5 v input high voltage (analog) v iha pin group 13 2?v dda +0.3 v input high voltage (xtal/extal, xtal is not driven by an external clock) v ihc pin group 11 v dda -0.8 ? v dda +0.3 v input high voltage (xtal/extal, xtal is driven by an external clock) v ihc pin group 11 2?v dda +0.3 v input low voltage v il pin groups 1, 2, 5, 6, 9, 10, 11, 13 -0.3 ? 0.8 v output high source current v oh = 2.4v (v oh min.) i oh pin groups 1, 2, 3 ? ? -4 ma pin groups 5, 6, 7 ?? -8 pin group 8 ?? -12 output low sink current v ol = 0.4v (v ol max) i ol pin groups 1, 2, 3, 4 ?? 4 ma pin groups 5, 6, 7 ?? 8 pin group 8 ?? 12 ambient operating temperature (automotive) t a -40 ? 125 c ambient operating temperature (industrial) t a -40 ? 105 c flash enduranc e (automotive) (program erase cycles) n f t a = -40c to 125c 10,000 ? ? cycles flash endurance (industrial) (program erase cycles) n f t a = -40c to 105c 10,000 ? ? cycles flash data retention t r t j <= 85c avg 15 ? ? years
56f8367 technical data, rev. 7.0 142 freescale semiconductor preliminary 10.2 dc electrical characteristics note: the 56f8167 device is specified to meet industrial requirements onl y; can is not available on the 56f8167 device. see pin groups in table 10-1 . table 10-5 dc electr ical characteristics at recommended operating conditions;see table 10-4 characteristic symbol notes min typ max unit test conditions output high voltage v oh 2.4 ? ? vi oh = i ohmax output low voltage v ol ??0.4 vi ol = i olmax digital input current high pull-up enabled or disabled i ih pin groups 1, 2, 5, 6, 9 ?0+/- 2.5 av in = 3.0v to 5.5v digital input current high with pull-down i ih pin group 10 40 80 160 av in = 3.0v to 5.5v analog input current high i iha pin group 13 ?0+/- 2.5 av in = v dda adc input current high i ihadc pin group 12 ?0+/- 10 av in = v dda digital input current low pull-up enabled i il pin groups 1, 2, 5, 6, 9 -200 -100 -500 av in = 0v digital input current low pull-up disabled i il pin groups 1, 2, 5, 6, 9 ?0+/- 2.5 av in = 0v digital input current low with pull-down i il pin group 10 ?0+/- 2.5 av in = 0v analog input current low i ila pin group 13 ?0+/- 2.5 av in = 0v adc input current low i iladc pin group 12 ?0+/- 10 av in = 0v extal input current low clock input i extal ?0+/- 2.5 av in = v dda or 0v xtal input current low clock input i xtal clkmode = high ?0+/- 2.5 av in = v dda or 0v clkmode = low ? ? 200 av in = v dda or 0v output current high impedance state i oz pin groups 1, 2, 3, 4, 5, 6, 7, 8,14 ?0+/- 2.5 av out = 3.0v to 5.5v or 0v schmitt trigger input hysteresis v hys pin groups 2, 6, 9, 10 ?0.3? v ? input capacitance (extal/xtal) c inc ?4.5? pf ? output capacitance (extal/xtal) c outc ?5.5? pf ? input capacitance c in ?6? pf ? output capacitance c out ?6? pf ?
dc electrical characteristics 56f8367 technical data, rev. 7.0 freescale semiconductor 143 preliminary table 10-6 power-on reset low voltage parameters characteristic symbol min typ max units por trip point por 1.75 1.8 1.9 v lvi, 2.5 volt supply, trip point 1 1. when v dd_core drops below v ei2.5 , an interrupt is generated. v ei2.5 ?2.14? v lvi, 3.3 volt supply, trip point 2 2. when v dd_core drops below v ei3.3 , an interrupt is generated. v ei3.3 ?2.7? v bias current i bias ?110130 a table 10-7 current consumption pe r power supply pin (typical) on-chip regulator enab led (ocr_dis = low) mode i dd_io 1 1. no output switching 2. includes processor core current supplied by internal voltage regulator i dd_adc i dd_osc_pll test conditions run1_mac 155ma 50ma 2.5ma ? 60mhz device clock ? all peripheral clocks are enabled ? all peripherals running ? continuous mac instructions with fetches from data ram ? adc powered on and clocked wait3 91ma 70 a2.5ma ? 60mhz device clock ? all peripheral clocks are enabled ? adc powered off stop1 6ma 0 a165 a ? 8mhz device clock ? all peripheral clocks are off ? adc powered off ? pll powered off stop2 5.1ma 0 a155 a ? external clock is off ? all peripheral clocks are off ? adc powered off ? pll powered off
56f8367 technical data, rev. 7.0 144 freescale semiconductor preliminary table 10-8 current consumption pe r power supply pin (typical) on-chip regulator disabled (ocr_dis = high) mode i dd_core i dd_io 1 1. no output switching i dd_adc i dd_osc_pll test conditions run1_mac 150ma 13 a50ma 2.5ma ? 60mhz device clock ? all peripheral clocks are enabled ? all peripherals running ? continuous mac instructions with fetches from data ram ? adc powered on and clocked wait3 86ma 13 a70 a2.5ma ? 60mhz device clock ? all peripheral clocks are enabled ? adc powered off stop1 950 a13 a0 a165 a ? 8mhz device clock ? all peripheral clocks are off ? adc powered off ? pll powered off stop2 100 a13 a0 a155 a ? external clock is off ? all peripheral clocks are off ? adc powered off ? pll powered off table 10-9. regulator parameters characteristic symbol min typical max unit unloaded output voltage (0ma load) v rnl 2.25 ? 2.75 v loaded output voltage (200 ma load) v rl 2.25 ? 2.75 v line regulation @ 250 ma load (v dd 33 ranges from 3.0 to 3.6) v r 2.25 ? 2.75 v short circuit current ( output shorted to ground) iss ? ? 700 ma bias current i bias ?5.8 7 ma power-down current i pd ?0 2 a short-circuit tolerance (output shorted to ground) t rsc ? ? 30 minutes
dc electrical characteristics 56f8367 technical data, rev. 7.0 freescale semiconductor 145 preliminary 10.2.1 temperature sense note: temperature sensor is not av ailable in the 56f8167 device. table 10-10. pll parameters characteristics symbol min typical max unit pll start-up time t ps 0.3 0.5 10 ms resonator start-up time t rs 0.1 0.18 1 ms min-max period variation t pv 120 ? 200 ps peak-to-peak jitter t pj ??175ps bias current i bias ?1.5 2 ma quiescent current, power-down mode i pd ?100150 a table 10-11 temperature sense parametrics characteristics symbol min typical max unit slope (gain) 1 m ? 7.762 ? mv/c room trim temp. 1, 2 1. includes the adc conversion of the analog temperature sense voltage. 2. the adc is not calibrated for the conversion of the tem perature sensor trim value stored in the flash memory at fmopt0 and fmopt1. t rt 24 26 28 c hot trim temp. (industrial) 1,2 t ht 122 125 128 c hot trim temp. (automotive) 1,2 t ht 147 150 153 c output voltage @ v dda_adc = 3.3v, t j =0c 1 v ts0 ?1.370? v supply voltage v dda_adc 3.0 3.3 3.6 v supply current - off i dd-off ??10 a supply current - on i dd-on ??250 a accuracy 3,1 from -40c to 150c using v ts = mt + v ts0 3. see application note, an1980, fo r methods to increase accuracy. t acc -6.7 0 6.7 c resolution 4, 5,1 4. assuming a 12-bit range from 0v to 3.3v. 5. typical resolution ca lculated using equation, r es ?0.104? c / bit r es = (v refh - v reflo ) x 1 2 12 m
56f8367 technical data, rev. 7.0 146 freescale semiconductor preliminary 10.3 ac electrical characteristics tests are conducted using the input levels specified in table 10-5 . unless otherwise specified, propagation delays are measured fr om the 50% to the 50% point, and rise and fall times are measured between the 10% and 90% points, as shown in figure 10-1 . figure 10-1 input signal measurement references figure 10-2 shows the definitions of the following signal states: ? active state, when a bus or signal is driven, and enters a low impedance state ? tri-stated, when a bus or signal is placed in a high impedance state ? data valid state, when a signal level has reached v ol or v oh ? data invalid state, when a signal level is in transition between v ol and v oh figure 10-2 signal states 10.4 flash memory characteristics table 10-12 flash timing parameters characteristic symbol min typ max unit program time 1 1. there is additional overhead which is part of the programming sequence. see the 56f8300 peripheral user manual for details. program time is per 16-bit word in flash me mory. two words at a time can be programmed within the pro- gram flash module, as it contains two interleaved memories. t prog 20 ? ? s erase time 2 2. specifies page erase time. there are 512 bytes per page in the data and boot flash memories. the program flash module uses two interleaved flash memories, increasing the effective page size to 1024 bytes. t erase 20 ? ? ms mass erase time t me 100 ? ? ms v ih v il fall time input signal note: the midpoint is v il + (v ih ? v il )/2. midpoint1 low high 90% 50% 10% rise time data invalid state data1 data2 valid data tri-stated data3 valid data2 data3 data1 valid data active data active
external clock operation timing 56f8367 technical data, rev. 7.0 freescale semiconductor 147 preliminary 10.5 external clock operation timing figure 10-3 external clock timing 10.6 phase locked loop timing table 10-13 external clock op eration timing requirements 1 1. parameters listed are guaranteed by design. characteristic symbol min typ max unit frequency of operation (external clock driver) 2 2. see figure 10-3 for details on using the recommended connection of an external clock driver. f osc 0?120mhz clock pulse width 3 3. the high or low pulse width must be no smaller than 8.0ns or the chip will not function. t pw 3.0 ? ? ns external clock input rise time 4 4. external clock input rise time is measured from 10% to 90%. t rise ? ? 10 ns external clock input fall time 5 5. external clock input fall time is measured from 90% to 10%. t fall ? ? 10 ns table 10-14 pll timing characteristic symbol min typ max unit external reference cryst al frequency for the pll 1 1. an externally supplied reference clock should be as free as possible from any phase jitter for the pll to work correctly. the pll is optimized for 8mhz input crystal. f osc 488.4mhz pll output frequency 2 (f out ) 2. zclk may not exceed 60mhz. for additional information on zclk and (f out /2), please refer to the occs chapter in the 56f8300 peripheral user manual . f op 160 ? 260 mhz pll stabilization time 3 -40 to +125 c 3. this is the minimum time required after the pll set up is changed to ensure reliable operation. t plls ?110ms external clock v ih v il note: the midpoint is v il + (v ih ? v il )/2. 90% 50% 10% 90% 50% 10% t pw t pw t fall t rise
56f8367 technical data, rev. 7.0 148 freescale semiconductor preliminary 10.7 crystal oscillator timing 10.8 external memory interface timing the external memory interface is designed to access static memory a nd peripheral devices. figure 10-4 shows sample timing and parame ters that are detailed in table 10-16 . the timing of each parameter consists of both a fixe d delay portion and a clock related portion, as well as user controlled wait states. the equation: t = d + p * (m + w) should be used to determine the actual time of each parameter. the terms in this equation are defined as: when using the xtal clock input di rectly as the chip clock without prescaling (zsrc selects prescaler clock and prescaler set to 1), the emi quadrature clock is generated using both e dges of the extal clock input. in this situation only, parame ter values must be adjusted for the duty cycle at xtal. dcaoe and dcaeo are used to make this duty cycle adjustment where needed. table 10-15 crystal o scillator parameters characteristic symbol min typ max unit crystal start-up time t cs 4510ms resonator start-up time t rs 0.1 0.18 1 ms crystal esr r esr ??120ohms crystal peak-to-peak jitter t d 70 ? 250 ps crystal min-max period variation t pv 0.12 ? 1.5 ns resonator peak-to-peak jitter t rj ??300ps resonator min-max period variation t rp ??300ps bias current, high-drive mode i biash ?250290 a bias current, low-drive mode i biasl ?80110 a quiescent current, power-down mode i pd ?0 1 a t = parameter delay time d = fixed portion of the delay, due to on-chip path delays p = period of the system clock, which determines the execution rate of the part (i.e., when the device is operating at 60mhz, p = 16.67 ns) m = fixed portion of a clock period inherent in th e design; this number is adjusted to account for possible derating of clock duty cycle w = sum of the applicable wait state controls. the ?wait state controls? column of table 10-16 shows the applicable controls for each parameter and the emi chapter of the 56f8300 peripheral user manual details what each wait state field controls.
external memory interface timing 56f8367 technical data, rev. 7.0 freescale semiconductor 149 preliminary dcaoe and dcaeo are calculated as follows: the timing of write cycles is different when wws = 0 than when wws > 0. therefore, some parameters contain two sets of numbers to a ccount for this difference. use the ?wait states conf iguration? column of table 10-16 to make the appropriate selection. figure 10-4 external memory interface timing note: when multiple lines are given for the same wait stat e configuration, calculate each and then select the smallest or most negative. dcaoe = = 0.5 - max xtal duty cycle, if zsrc selects pr escaler clock and the prescaler is set to 1 0.0 all other cases dcaeo = = min xtal duty cycle - 0.5, if zsrc selects pr escaler clock and the pr escaler is set to 1 0.0 all other cases example of dcaoe and dcaeo calculation: assuming prescaler is set for 1 and prescaler clock is selected by zsrc, if xtal duty cycle ranges between 45% and 60% high; dcaoe = .50 - .60 = - 0.1 dcaeo = .45 - .50 = - 0.05 t drd t rdd t ad t doh t dos t dwr t rdwr t wac t wrrd t wr t awr t wrwr t ardd t rda t rdrd t rd t arda data out data in a0-axx,cs rd wr d0-d15 note: during read-modify-write instructions and inter nal instructions, the address lines do not change state.
56f8367 technical data, rev. 7.0 150 freescale semiconductor preliminary table 10-16 external memory interface timing characteristic symbol wait states configuration dm wait states controls unit address valid to wr asserted t awr wws=0 -2.076 0.50 wwss ns wws>0 -1.795 0.75 + dcaoe wr width asserted to wr deasserted t wr wws=0 -0.094 0.25 + dcaoe wws ns wws>0 -0.012 0 data out valid to wr asserted t dwr wws=0 -9.321 0.25 + dcaeo wwss ns wws=0 -1.160 0.00 wws>0 -8.631 0.50 wws>0 -0.879 0.25 + dcaoe valid data out hold time after wr deasserted t doh -2.086 0.25 + dcaeo wwsh ns valid data out set-up time to wr deasserted t dos -0.563 0.25 + dcaoe wws,wwss ns -8.315 0.50 valid address after wr deasserted t wac -3.432 0.25 + dcaeo wwsh ns rd deasserted to address invalid t rda -1.780 0.00 rwsh ns address valid to rd deasserted t ardd -2.120 1.00 rwss,rws ns valid input data hold after rd deasserted t drd 0.00 n/a 1 1. n/a since device captures data before it deasserts rd ? ns rd assertion width t rd 0.279 1.00 rws ns address valid to input data valid t ad -15.723 1.00 rwss,rws ns -20.642 1.25 + dcaoe address valid to rd asserted t arda -2.603 0.00 rwss ns rd asserted to input data valid t rdd -13.120 1.00 rwss,rws ns -18.039 1.25 + dcaoe wr deasserted to rd asserted t wrrd -2.135 0.25 + dcaeo wwsh,rwss ns rd deasserted to rd asserted t rdrd -0.483 2 2. if rwss = rwsh = 0, and the chip select does not change, then rd does not deassert during back-to-back reads. 0.00 rwss,rwsh mdar 3, 4 3. substitute bmdar for mdar if there is no chip select 4. mdar is active in this calculation only when the chip select changes. ns wr deasserted to wr asserted t wrwr wws=0 -1.608 0.75 + dcaeo wwss, wwsh ns wws>0 -0.918 1.00 rd deasserted to wr asserted t rdwr wws=0 -0.096 0.50 rwsh, wwss, mdar 3 ns wws>0 0.084 0.75 + dcaoe
reset, stop, wait, mode select, and interrupt timing 56f8367 technical data, rev. 7.0 freescale semiconductor 151 preliminary 10.9 reset, stop, wait, mode select, and interrupt timing table 10-17 reset, stop, wait, mode select, and interrupt timing 1,2 1. in the formulas, t = clock cycle. for an operating freq uency of 60mhz, t = 16.67ns. at 8mhz (used during reset and stop modes), t = 125ns. 2. parameters listed are guaranteed by design. characteristic symbol typical min typical max unit see figure reset assertion to address, data and control signals high impedance t raz ?21ns 10-5 minimum reset assertion duration t ra 16t ? ns 10-5 reset deassertion to first external address output 3 3. during power-on reset, it is possible to use the device?s internal reset stretching circuitry to extend this period to 2 21 t. t rda 63t 64t ns 10-5 edge-sensitive interrupt request width t irw 1.5t ? ns 10-6 irqa , irqb assertion to external data memory access out valid, caused by first instruction execution in the interrupt service routine t idm 18t ? ns 10-7 t idm - fast 14t ? irqa , irqb assertion to general purpose output valid, caused by first instruction execution in the interrupt service routine t ig 18t ? ns 10-7 t ig - fast 14t ? delay from irqa assertion (exiting wait) to external data memory access 4 4. the minimum is specified for the duration of an edge-sensitive irqa interrupt required to recover from the stop state. this is not the minimum required so that the irqa interrupt is accepted. t iri 22t ? ns 10-8 t iri -fast 18t ? delay from irqa assertion to external data memory access (exiting stop) t if 22t ? ns 10-9 t if - fast 18t ? irqa width assertion to recover from stop state 5 5. the interrupt instruction fetch is visible on the pins only in mode 3. t iw 1.5t ? ns 10-9
56f8367 technical data, rev. 7.0 152 freescale semiconductor preliminary figure 10-5 asynchronous reset timing figure 10-6 external interrupt ti ming (negative edge-sensitive) figure 10-7 external level-s ensitive interrupt timing first fetch t ra t raz t rda a0?a15, d0?d15 ps , ds , rd , wr reset first fetch irqa , irqb t irw t idm a0?a15, ps , ds , rd , wr irqa , irqb first interrupt instruction execution a) first interrupt in struction execution t ig general purpose i/o pin irqa , irqb b) general purpose i/o
serial peripheral interface (spi) timing 56f8367 technical data, rev. 7.0 freescale semiconductor 153 preliminary figure 10-8 interrupt fr om wait state timing figure 10-9 recovery from stop state using asynchronous interrupt timing 10.10 serial peripheral interface (spi) timing table 10-18 spi timing 1 characteristic symbol min max unit see figure cycle time master slave t c 50 50 ? ? ns ns 10-10 , 10-11 , 10-12 , 10-13 enable lead time master slave t eld ? 25 ? ? ns ns 10-13 enable lag time master slave t elg ? 100 ? ? ns ns 10-13 clock (sck) high time master slave t ch 17.6 25 ? ? ns ns 10-10 , 10-11 , 10-12 , 10-13 clock (sck) low time master slave t cl 24.1 25 ? ? ns ns 10-13 instruction fetch t iri irqa , irqb first interrupt vector a0?a15, ps , ds , rd , wr not irqa interrupt vector t iw irqa t if a0?a15, ps , ds , rd , wr first instruction fetch
56f8367 technical data, rev. 7.0 154 freescale semiconductor preliminary data set-up time required for inputs master slave t ds 20 0 ? ? ns ns 10-10 , 10-11 , 10-12 , 10-13 data hold time required for inputs master slave t dh 0 2 ? ? ns ns 10-10 , 10-11 , 10-12 , 10-13 access time (time to data active from high-impedance state) slave t a 4.8 15 ns 10-13 disable time (hold time to high-impedance state) slave t d 3.7 15.2 ns 10-13 data valid for outputs master slave (after enable edge) t dv ? ? 4.5 20.4 ns ns 10-10 , 10-11 , 10-12 , 10-13 data invalid master slave t di 0 0 ? ? ns ns 10-10 , 10-11 , 10-12 rise time master slave t r ? ? 11.5 10.0 ns ns 10-10 , 10-11 , 10-12 , 10-13 fall time master slave t f ? ? 9.7 9.0 ns ns 10-10 , 10-11 , 10-12 , 10-13 1. parameters listed are guaranteed by design. table 10-18 spi timing 1 (continued) characteristic symbol min max unit see figure
serial peripheral interface (spi) timing 56f8367 technical data, rev. 7.0 freescale semiconductor 155 preliminary figure 10-10 spi master timing (cpha = 0) figure 10-11 spi master timing (cpha = 1) sclk (cpol = 0) (output) sclk (cpol = 1) (output) miso (input) mosi (output) msb in bits 14?1 lsb in t f t c t cl t cl t r t r t f t ds t dh t ch t di t dv t di (ref) t r master msb out bits 14?1 master lsb out ss (input) t ch ss is held high on master t f sclk (cpol = 0) (output) sclk (cpol = 1) (output) miso (input) mosi (output) msb in bits 14?1 lsb in t r t c t cl t cl t f t ch t dv (ref) t dv t di (ref) t r t f master msb out bits 14? 1 master lsb out ss (input) t ch ss is held high on master t ds t dh t di t r t f
56f8367 technical data, rev. 7.0 156 freescale semiconductor preliminary figure 10-12 spi slave timing (cpha = 0) figure 10-13 spi slave timing (cpha = 1) sclk (cpol = 0) (input) sclk (cpol = 1) (input) miso (output) mosi (input) slave msb out bits 14?1 t c t cl t cl t f t ch t di msb in bits 14?1 lsb in ss (input) t ch t dh t r t elg t eld t f slave lsb out t d t a t ds t dv t di t r sclk (cpol = 0) (input) sclk (cpol = 1) (input) miso (output) mosi (input) slave msb out bits 14?1 t c t cl t cl t ch t di msb in bits 14?1 lsb in ss (input) t ch t dh t f t r slave lsb out t d t a t eld t dv t f t r t elg t dv t ds
quad timer timing 56f8367 technical data, rev. 7.0 freescale semiconductor 157 preliminary 10.11 quad timer timing figure 10-14 timer timing 10.12 quadrature decoder timing table 10-19 timer timing 1, 2 1. in the formulas listed, t = the clock cycle. for 60mhz operation, t = 16.67ns. 2. parameters listed are guaranteed by design. characteristic symbol min max unit see figure timer input period p in 2t + 6 ? ns 10-14 timer input high / low period p inhl 1t + 3 ? ns 10-14 timer output period p out 1t - 3 ? ns 10-14 timer output high / low period p outhl 0.5t - 3 ? ns 10-14 table 10-20 quadrature decoder timing 1, 2 1. in the formulas listed, t = the clo ck cycle. for 60mhz operation, t=16.67ns. 2. parameters listed are guaranteed by design. characteristic symbol min max unit see figure quadrature input period p in 4t + 12 ? ns 10-15 quadrature input high / low period p hl 2t + 6 ? ns 10-15 quadrature phase period p ph 1t + 3 ? ns 10-15 p out p outhl p outhl p in p inhl p inhl timer inputs timer outputs
56f8367 technical data, rev. 7.0 158 freescale semiconductor preliminary figure 10-15 quadrature decoder timing 10.13 serial communication interface (sci) timing figure 10-16 rxd pulse width figure 10-17 txd pulse width table 10-21 sci timing 1 1. parameters listed are guaranteed by design. characteristic symbol min max unit see figure baud rate 2 2. f max is the frequency of operation of the system clock, zclk, in mhz, which is 60mhz for the 56f8367 device , and 40mhz for the 56f8167 device. br ? (f max /16) mbps ? rxd 3 pulse width 3. the rxd pin in sci0 is named rxd0 a nd the rxd pin in sci1 is named rxd1. rxd pw 0.965/br 1.04/br ns 10-16 txd 4 pulse width 4. the txd pin in sci0 is named txd0 and the txd pin in sci1 is named txd1. txd pw 0.965/br 1.04/br ns 10-17 phase b (input) p in p hl p hl phase a (input) p in p hl p hl p ph p ph p ph p ph rxd pw rxd sci receive data pin (input) txd pw txd sci receive data pin (input)
controller area network (can) timing 56f8367 technical data, rev. 7.0 freescale semiconductor 159 preliminary 10.14 controller ar ea network (can) timing note: can is not available in the 56f8167 device. figure 10-18 bus wakeup detection 10.15 jtag timing table 10-22 can timing 1 1. parameters listed are guaranteed by design characteristic symbol min max unit see figure baud rate br can ? 1 mbps ? bus wake up detection t wakeup 5 ? s 10-18 table 10-23 jtag timing characteristic symbol min max unit see figure tck frequency of operation using eonce 1 1. tck frequency of operation must be less than 1/8 the processor rate. f op dc sys_clk/8 mhz 10-19 tck frequency of operation not using eonce 1 f op dc sys_clk/4 mhz 10-19 tck clock pulse width t pw 50 ? ns 10-19 tms, tdi data set-up time t ds 5?ns 10-20 tms, tdi data hold time t dh 5?ns 10-20 tck low to tdo data valid t dv ?30ns 10-20 tck low to tdo tri-state t ts ?30ns 10-20 trst assertion time t trst 2t 2 2. t = processor clock period (nominally 1/60mhz) ?ns 10-21 t wakeup can_rx can receive data pin (input)
56f8367 technical data, rev. 7.0 160 freescale semiconductor preliminary figure 10-19 test clo ck input timing diagram figure 10-20 test access port timing diagram figure 10-21 trst timing diagram tck (input) v m v il v m = v il + (v ih ? v il )/2 t pw 1/f op t pw v m v ih input data valid output data valid output data valid t ds t dh t dv t ts t dv tck (input) tdi (input) tdo (output) tdo (output ) tdo (output) tms trst (input) t trst
analog-to-digital converter (adc) parameters 56f8367 technical data, rev. 7.0 freescale semiconductor 161 preliminary 10.16 analog-to-digital converter (adc) parameters table 10-24 adc parameters characteristic symbol min typ max unit input voltages v adin v refl ?v refh v resolution r es 12 ? 12 bits integral non-linearity 1 inl ? +/- 2.4 +/- 3.2 lsb 2 differential non-linearity dnl ? +/- 0.7 < +1 lsb 2 monotonicity guaranteed adc internal clock f adic 0.5 ? 5 mhz conversion range r ad v refl ?v refh v adc channel power-up time t adpu 5616 t aic cycles 3 adc reference circuit power-up time 4 t vref ??25ms conversion time t adc ?6? t aic cycles 3 sample time t ads ?1? t aic cycles 3 input capacitance c adi ?5?pf input injection current 5 , per pin i adi ?? 3ma input injection current, total i adit ??20ma v refh current i vrefh ?1.2 3ma adc a current i adca ?25?ma adc b current i adcb ?25?ma quiescent current i adcq ?010 a uncalibrated gain error (ideal = 1) e gain ? .+/- .004 +/- .01 ? uncalibrated offset voltage v offset ? +/- 27 +/- 40 mv calibrated absolute error 6 ae cal ? see figure 10-22 ?lsbs calibration factor 1 7 cf1 ? 0.002289 ? ? calibration factor 2 cf2 ? -25.6 ? ? crosstalk between channels ? ? -60 ? db common mode voltage v common ?(v refh - v reflo ) / 2 ? v signal-to-noise ratio snr ? 64.6 ? db
56f8367 technical data, rev. 7.0 162 freescale semiconductor preliminary signal-to-noise plus distortion ratio sinad ? 59.1 ? db total harmonic distortion thd ? 60.6 ? db spurious free dynamic range sfdr ? 61.1 ? db effective number of bits 8 enob ? 9.6 ? bits 1. inl measured from v in = .1v refh to v in = .9v refh 10% to 90% input signal range 2. lsb = least significant bit 3. adc clock cycles 4. assumes each voltage reference pin is bypassed with 0.1 f ceramic capacitors to ground 5. the current that can be injected or sourced from an uns elected adc signal input without impacting the performance of the adc. this allows the adc to operate in noisy industrial environments where inductive flyback is possible. 6. absolute error includes the effects of both gain error and offset error. 7. please see the 56f8300peripheral user?s manual for additional information on adc calibration. 8. enob = (sinad - 1.76)/6.02 table 10-24 adc parameters (continued) characteristic symbol min typ max unit
analog-to-digital converter (adc) parameters 56f8367 technical data, rev. 7.0 freescale semiconductor 163 preliminary figure 10-22 adc absolute error over pr ocessing and temperature extremes before and after calibration for vdc in = 0.60v and 2.70v note: the absolute error data shown in the graphs above refl ects the effects of both gain error and offset error. the data was taken on 25 parts: three each from fo ur processing corner lots as well as five from one nominally processed lot, each at three temperatures: -40c, 27c, and 150c (giving the 75 data points shown above), for two input dc voltages: 0.60v and 2.70v. the data indicates that for the given population of parts, calibra tion significantly reduced (by as much as 24%) the collective variation (spread) of the absolute error of the popul ation. it also significantly reduced (by as much as 38%) the mean (average) of the absolute error a nd thereby brought it significantly cl oser to the ideal value of zero. although not guaranteed, it is believ ed that calibration wi ll produce results similar to those shown above for any population of parts including those which represent processing and temperature extremes.
56f8367 technical data, rev. 7.0 164 freescale semiconductor preliminary 10.17 equivalent circuit for adc inputs figure 10-23 illustrates the adc input circuit during samp le & hold. s1 and s2 are always open/closed at the same time that s3 is clos ed/open. when s1/s2 are closed & s3 is open, one input of the sample and hold circuit moves to v refh - v refh / 2, while the other charges to th e analog input voltage. when the switches are flipped, the charge on c1 and c2 are averaged via s3, wi th the result that a single-ended analog input is switched to a differential voltage centered about v refh - v refh / 2. the switches switch on every cycle of the adc clock ( open one-half adc clock, cl osed one-half adc cloc k). note that there are additional capacitances associated with the analog input pad, routing, etc., but these do not filter into the s/h output voltage, as s1 provides is olation during the charge-sharing phase. one aspect of this circuit is that there is an on-going input current, which is a function of the analog input voltage, v ref and the adc clock frequency. 1. parasitic capacitance due to package, pin- to-pin and pin-to-package base coupling; 1.8pf 2. parasitic capacitance due to the chip bond pad, esd protection devices and signal routing; 2.04pf 3. equivalent resistance for the esd isolati on resistor and the channel select mux; 500 ohms 4. sampling capacitor at the sample and hold circuit. capaci tor c1 is normally disconnected from the input and is only connected to it at sampling time; 1pf figure 10-23 equivalent ci rcuit for a/d loading 10.18 power consumption this section provides additional de tail which can be used to optimize power consumption for a given application. power consumption is given by the following equation: a, the internal [static component], is comprised of the dc bias currents for the oscillator, leakage current, pll, and voltage referen ces. these sources operate independent ly of processor state or operating frequency. b, the internal [state-dependent component], re flects the supply current required by certain on-chip resources only when those resources are in use. these include ram, flash memory and the adcs. total power = a: internal [static component] +b: internal [state-d ependent component] +c: internal [dynamic component] +d: external [dynamic component] +e: external [static] 1 2 3 analog input 4 v refh - v refh / 2 s1 s2 s3 c1 c2 s/h c1 = c2 = 1pf
power consumption 56f8367 technical data, rev. 7.0 freescale semiconductor 165 preliminary c, the internal [dynamic component], is classic c*v 2 *f cmos power dissipation corresponding to the 56800e core and standard cell logic. d, the external [dynamic component], reflects power dissipated on-chip as a result of capacitive loading on the external pins of the chip. this is also commonly described as c*v 2 *f, although simulations on two of the io cell types used on the device reveal that the power-versu s-load curve does have a non-zero y-intercept. power due to capacitive loading on output pins is (first order) a f unction of the capacitive load and frequency at which the outputs change. table 10-20 provides coefficients for calculating power dissipated in the io cells as a function of capacitive load. in these cases: totalpower = ((intercept +slope*cload)*frequency/10mhz) where: ? summation is performed over all ou tput pins with capacitive loads ? totalpower is expressed in mw ? cload is expressed in pf because of the low duty cycle on most device pins , power dissipation due to capacitive loads was found to be fairly low when averaged ove r a period of time. the one possible exception to this is if the chip is using the external address and data buses at a rate approaching the maximum system rate. in this case, power from these buses can be significant. e, the external [static component], reflects the effects of placing resistive load s on the outputs of the device. sum the total of all v 2 /r or iv to arrive at the resistive load contribution to power. assume v = 0.5 for the purposes of these rough ca lculations. for instance, if there is a total of 8 pwm outputs driving 10ma into leds, then p = 8*.5*.01 = 40mw. in previous discussions, power consum ption due to parasitics associated with pure input pins is ignored, as it is assumed to be negligible. table 10-25 i/o loading coefficients at 10mhz intercept slope pdu08dgz_me 1.3 0.11mw / pf pdu04dgz_me 1.15mw 0.11mw / pf
56f8367 technical data, rev. 7.0 166 freescale semiconductor preliminary part 11 packaging note: the 160 map ball grid array is not available in the 56f8167 device. 11.1 56f8367 package an d pin-out information this section contains package and pin-out inform ation for the 56f8367. this device comes in a 160-pin low-profile quad flat pack (lqfp) and 160 map ball grid array . figure 11-1 shows the package lay-out for the 160-pin lqfp, and figure 11-2 for the160 map ball grid array. figure 11-5 shows the mechanical parameters for the lqfp package and figure 11-3 for the mapbga, table 11-1 lists the pin-out for the 160-pin lqfp and table 11-2 lists the pin-out for the 160 mapbga. figure 11-1 top view, 56f836 7 160-pin lqfp package v dd_io v pp 2 clko txd0 rxd0 phasea1 phaseb1 index1 home1 a1 a2 a3 a4 a5 v cap 4 v dd_io a6 a7 a8 a9 a10 a11 a12 a13 a14 a15 v ss d7 d8 d9 v dd_io d10 gpiob0 gpiob1 gpiob2 gpiob3 pin 1 orientation mark 121 41 gpiob4 pwmb0 pwmb1 pwmb2 v ss emi_mode home0 index0 phaseb0 phasea0 a0 d15 d14 d13 d12 d11 mosi0 miso0 sclk0 ss0 v cap 2 can_rx can_tx v pp 1 tdo tdi tms tck trst tc1 v dd_io tc0 td3 td2 td1 td0 isa2 isa1 isa0 v ss extboot anb7 anb6 anb5 v ss v dd_io pwmb3 pwmb4 pwmb5 gpiob5 gpiob6 gpiob7 txd1 rxd1 wr rd ps ds gpiod0 gpiod1 gpiod2 gpiod3 gpiod4 gpiod5 isb0 v cap 1 isb1 isb2 irqa faultb0 faultb1 faultb2 d0 d1 faultb3 pwma0 v ss pwma1 pwma2 v dd_io pwma3 pwma4 v ss anb4 anb3 anb2 anb1 anb0 v ssa_adc v dda_adc v refh v refp v refmid v refn v reflo temp_sense ana7 ana6 ana5 ana4 ana3 ana2 ana1 ana0 clkmode reset rsto v dd_io v cap 3 extal xtal vdda_osc_pll ocr_dis d6 d5 d4 faulta3 d3 faulta2 faulta1 d2 faulta0 pwma5 81 irqb * when the on-chip regulator is disabl ed, these four pins become 2.5v v dd_core .
56f8367 package and pin-out information 56f8367 technical data, rev. 7.0 freescale semiconductor 167 preliminary table 11-1 56f8367 160-pin lqfp packag e identification by pin number pin no. signal name pin no. signal name pin no. signal name pin no. signal name 1v dd_io 41 v ss 81 pwma5 121 anb5 2v pp 242 v dd_io 82 faulta0 122 anb6 3 clko 43 pwmb3 83 d2 123 anb7 4 txd0 44 pwmb4 84 faulta1 124 extboot 5rxd045pwmb585 faulta2 125 v ss 6 phasea1 46 gpiob5 86 d3 126 isa0 7 phaseb1 47 gpiob6 87 faulta3 127 isa1 8 index1 48 gpiob7 88 d4 128 isa2 9 home1 49 txd1 89 d5 129 td0 10 a1 50 rxd1 90 d6 130 td1 11 a2 51 wr 91 ocr_dis 131 td2 12 a3 52 rd 92 v dda_osc_pll 132 td3 13 a4 53 ps 93 xtal 133 tc0 14 a5 54 ds 94 extal 134 v dd_io 15 v cap 4* 55 gpiod0 95 v cap 3* 135 tc1 16 v dd_io 56 gpiod1 96 v dd_io 136 trst 17 a6 57 gpiod2 97 rsto 137 tck 18 a7 58 gpiod3 98 reset 138 tms 19 a8 59 gpiod4 99 clkmode 139 tdi 20 a9 60 gpiod5 100 ana0 140 tdo 21 a10 61 isb0 101 ana1 141 v pp 1 22 a11 62 v cap 1* 102 ana2 142 can_tx 23 a12 63 isb1 103 ana3 143 can_rx 24 a13 64 isb2 104 ana4 144 v cap 2* 25 a14 65 irqa 105 ana5 145 ss0 * when the on-chip regulator is disabl ed, these four pins become 2.5v v dd_core .
56f8367 technical data, rev. 7.0 168 freescale semiconductor preliminary 26 a15 66 irqb 106 ana6 146 sclk0 27 v ss 67 faultb0 107 ana7 147 miso0 28 d7 68 faultb1 108 temp_sense 148 mosi0 29 d8 69 faultb2 109 v reflo 149 d11 30 d9 70 d0 110 v refn 150 d12 31 v dd_io 71 d1 111 v refmid 151 d13 32 d10 72 faultb3 112 v refp 152 d14 33 gpiob0 73 pwma0 113 v refh 153 d15 34 gpiob1 74 v ss 114 v dda_adc 154 a0 35 gpiob2 75 pwma1 115 v ssa_adc 155 phasea0 36 gpiob3 76 pwma2 116 anb0 156 phaseb0 37 gpiob4 77 v dd_io 117 anb1 157 index0 38 pwmb0 78 pwma3 118 anb2 158 home0 39 pwmb1 79 pwma4 119 anb3 159 emi_mode 40 pwmb2 80 v ss 120 anb4 160 v ss table 11-1 56f8367 160-pin lqfp package id entification by pin number (continued) pin no. signal name pin no. signal name pin no. signal name pin no. signal name
56f8367 package and pin-out information 56f8367 technical data, rev. 7.0 freescale semiconductor 169 preliminary figure 11-2 top view, 56f8367 160-pin mapbga package v pp 2 temp_ sense v refp 123 4 567 8 91011121314 a b c d e f g h j k l m n p v dda_ osc_pll clko txd0 rxd0 phasea1 phaseb1 index1 home1 a1 a2 a3 a4 a5 v cap 4 a6 a7 a8 a9 a10 a11 a12 a13 a14 a15 d7 d8 d9 d10 gpiob1 gpiob2 gpiob0 gpiob3 gpiob4 pwmb0 pwmb1 pwmb2 pwmb3 pwmb4 pwmb5 gpiob5 gpiob6 gpiob7 txd1 rxd1 wr rd ps ds gpiod0 gpiod1 gpiod2 gpiod3 gpiod4 gpiod5 isb0 v cap 1 isb1 isb2 irqa irqb faultb0 faultb1 faultb2 d0 d1 faultb3 pwma1 pwma0 pwma2 pwma3 pwma4 pwma5 faulta0 d2 faulta1 d3 faulta2 faulta3 d4 d5 d6 ocr_dis xtal extal v cap 3 rsto reset clko mode ana0 ana1 ana2 ana3 ana4 ana5 ana6 ana7 v reflo v refn v refmid v refh v dda_adc v ssa_adc anb0 anb1 anb2 anb3 anb4 anb5 anb6 anb7 extboot isa0 isa1 isa2 td0 td1 td2 td3 tc0 tc1 trst tck tms tdi tdo v pp 1 can_tx can_rx v cap 2 ss0 sclk0 miso0 mosi0 d11 d12 d13 d14 d15 a0 phasea0 phaseb0 index0 home0 emi_ mode v dd_io v dd_io v dd_io v ss v ss v dd_io v ss v dd_io v ss v ss v ss v dd_io v dd_io
56f8367 technical data, rev. 7.0 170 freescale semiconductor preliminary table 11-2 56f8367 -160 mapbga package identi fication by pin number ball no. signal name ball no. signal name ball no. signal name ball no. signal name f4 v dd_io k11 v ss n12 pwma5 a13 anb5 c2 v pp 2k7v dd_io n13 faulta0 b12 anb6 d3 clko n3 pwmb3 p14 d2 a12 anb7 b1 txd0 p2 pwmb4 n14 faulta1 b11 extboot d2 rxd0 m3 pwmb5 m13 faulta2 j11 v ss c1 phasea1 n4 gpiob5 l13 d3 a11 isa0 d1 phaseb1 p3 gpiob6 m14 faulta3 c11 isa1 e2 index1 m4 gpiob7 l14 d4 d11 isa2 e1 home1 p4 txd1 l12 d5 b10 td0 e3 a1 n5 rxd1 l11 d6 a10 td1 e4 a2 l4 wr k14 ocr_dis d10 td2 f2 a3 p5 rd k13 v dda_osc_pll e10 td3 f1 a4 n6 ps k12 xtal a9 tc0 f3 a5 l5 ds j12 extal f11 v dd_io g4 v cap 4* p6 gpiod0 h11 v cap 3* b9 tc1 k5 v dd_io l6 gpiod1 k10 v dd_io d9 trst g1 a6 k6 gpiod2 j13 rsto d8 tck g3 a7 n7 gpiod3 j14 reset a8 tms g2 a8 p7 gpiod4 h12 clkmode b8 tdi h1 a9 l7 gpiod5 g13 ana0 d7 tdo h2 a10 n8 isb0 h13 ana1 a7 v pp 1 h4 a11 k8 v cap 1* g12 ana2 d6 can_tx h3 a12 l8 isb1 f13 ana3 b7 can_rx j1 a13 p8 isb2 f12 ana4 e8 v cap 2* j2 a14 k9 irqa h14 ana5 d5 ss0 * when the on-chip regulator is disabl ed, these four pins become 2.5v v dd_core .
56f8367 package and pin-out information 56f8367 technical data, rev. 7.0 freescale semiconductor 171 preliminary j3 a15 p9 irqb g14 ana6 a6 sclk0 j4 v ss n9 faultb0 e13 ana7 d4 miso0 k1 d7 l9 faultb1 e11 temp_sense b6 mosi0 k3 d8 l10 faultb2 e12 v reflo a5 d11 k2 d9 p10 d0 f14 v refn a4 d12 e5 v dd_io n10 d1 e14 v refmid b5 d13 k4 d10 p11 faultb3 d13 v refp c4 d14 l1 gpiob0 m11 pwma0 d14 v refh a3 d15 l3 gpiob1 g11 v ss c14 v dda_adc c3 a0 l2 gpiob2 p12 pwma1 d12 v ssa_adc a2 phasea0 m1 gpiob3 n11 pwma2 c13 anb0 b4 phaseb0 m2 gpiob4 e9 v dd_io b14 anb1 a1 index0 n1 pwmb0 m12 pwma3 c12 anb2 b3 home0 p1 pwmb1 p13 pwma4 b13 anb3 b2 emi_mode n2 pwmb2 e7 v ss a14 anb4 e6 v ss table 11-2 56f8367 -160 mapbga package id entification by pin number (continued) ball no. signal name ball no. signal name ball no. signal name ball no. signal name please see http://www.freescale.com for the most current mechanical drawing.
56f8367 technical data, rev. 7.0 172 freescale semiconductor preliminary figure 11-3 160 mapbga m echanical information notes: 1. dimensions are in millimeters. 2. interpret dimensions and tolerances per asme y14.5m, 1994. 3. dimension b is measured at the maximum solder ball diameter, parallel to datum plane z. 4. datum z (seating plane) is defined by the spherical crowns of the solder balls. 5. parallelism measurement shall exclude any effect of mark on top surface of package. case 1268-01 issue o x 0.20 laser mark for pin 1 identification in this area e 13x d e m s a1 a2 a 0.15 z 0.30 z z rotated 90 clockwise detail k 5 view m-m e 13x s x 0.30 y z 0.10 z 3 b 160x metalized mark for pin 1 identification in this area 14 13 12 11 10 9 6 5 4 3 2 1 a b c d e f g h j k l m n p 4 160x dim min max millimeters a 1.32 1.75 a1 0.27 0.47 a2 1.18 ref b 0.35 0.65 d 15.00 bsc e 15.00 bsc e 1.00 bsc s 0.50 bsc y k
56f8167 package and pin-out information 56f8367 technical data, rev. 7.0 freescale semiconductor 173 preliminary 11.2 56f8167 package an d pin-out information this section contains package and pin-out inform ation for the 56f8167. this device comes in a 160-pin low-profile quad flat pack (lqfp). figure 11-4 shows the package outline for the 160-pin lqfp, figure 11-5 shows the mechanical parameters for this package, and table 11-3 lists the pin-out for the 160-pin lqfp. figure 11-4 top view, 56f816 7 160-pin lqfp package v dd_io v pp 2 clko txd0 rxd0 sclk1 mosi1 miso1 ss1 a1 a2 a3 a4 a5 v cap 4* v dd_io a6 a7 a8 a9 a10 a11 a12 a13 a14 a15 v ss d7 d8 d9 v dd_io d10 gpiob0 gpiob1 gpiob2 gpiob3 pin 1 orientation mark 121 41 gpiob4 pwmb0 pwmb1 pwmb2 v ss emi_mode home0 index0 phaseb0 phasea0 a0 d15 d14 d13 d12 d11 mosi0 miso0 sclk0 ss0 v cap 2* nc nc v pp 1 tdo tdi tms tck trst tc1 v dd_io tc0 gpioe13 gpioe12 gpioe11 gpioe10 gpioc10 gpioc9 gpioc8 v ss extboot anb7 anb6 anb5 v ss v dd_io pwmb3 pwmb4 pwmb5 gpiob5 gpiob6 gpiob7 txd1 rxd1 wr rd ps ds gpiod0 gpiod1 gpiod2 gpiod3 gpiod4 gpiod5 isb0 v cap 1* isb1 isb2 irqa irqb faultb0 faultb1 faultb2 d0 d1 faultb3 nc v ss nc nc v dd_io nc nc v ss anb4 anb3 anb2 anb1 anb0 v ssa_adc v dda_adc v refh v refp v refmid v refn v reflo nc ana7 ana6 ana5 ana4 ana3 ana2 ana1 ana0 clkmode reset rsto v dd_io v cap 3* extal xtal vdda_osc_pll ocr_dis d6 d5 d4 nc d3 nc nc d2 nc nc 81 * when the on-chip regulator is disabl ed, these four pins become 2.5v v dd_core .
56f8367 technical data, rev. 7.0 174 freescale semiconductor preliminary table 11-3 56f8167 160-pin lqfp packag e identification by pin number pin no. signal name pin no. signal name pin no. signal name pin no. signal name 1v dd_io 41 v ss 81 nc 121 anb5 2v pp 242 v dd_io 82 nc 122 anb6 3 clko 43 pwmb3 83 d2 123 anb7 4 txd0 44 pwmb4 84 nc 124 extboot 5rxd045pwmb585 nc 125 v ss 6 sclk1 46 gpiob5 86 d3 126 gpioc8 7 mosi1 47 gpiob6 87 nc 127 gpioc9 8 miso1 48 gpiob7 88 d4 128 gpioc10 9 ss1 49 txd1 89 d5 129 gpioe10 10 a1 50 rxd1 90 d6 130 gpioe11 11 a2 51 wr 91 ocr_dis 131 gpioe12 12 a3 52 rd 92 v dda_osc_pll 132 gpioe13 13 a4 53 ps 93 xtal 133 tc0 14 a5 54 ds 94 extal 134 v dd_io 15 v cap 4* 55 gpiod0 95 v cap 3* 135 tc1 16 v dd_io 56 gpiod1 96 v dd_io 136 trst 17 a6 57 gpiod2 97 rsto 137 tck 18 a7 58 gpiod3 98 reset 138 tms 19 a8 59 gpiod4 99 clkmode 139 tdi 20 a9 60 gpiod5 100 ana0 140 tdo 21 a10 61 isb0 101 ana1 141 v pp 1 22 a11 62 v cap 1* 102 ana2 142 nc 23 a12 63 isb1 103 ana3 143 nc 24 a13 64 isb2 104 ana4 144 v cap 2* 25 a14 65 irqa 105 ana5 145 ss0 * when the on-chip regulator is disabl ed, these four pins become 2.5v v dd_core
56f8167 package and pin-out information 56f8367 technical data, rev. 7.0 freescale semiconductor 175 preliminary 26 a15 66 irqb 106 ana6 146 sclk0 27 v ss 67 faultb0 107 ana7 147 miso0 28 d7 68 faultb1 108 nc 148 mosi0 29 d8 69 faultb2 109 v reflo 149 d11 30 d9 70 d0 110 v refn 150 d12 31 v dd_io 71 d1 111 v refmid 151 d13 32 d10 72 faultb3 112 v refp 152 d14 33 gpiob0 73 nc 113 v refh 153 d15 34 gpiob1 74 v ss 114 v dda_adc 154 a0 35 gpiob2 75 nc 115 v ssa_adc 155 phasea0 36 gpiob3 76 nc 116 anb0 156 phaseb0 37 gpiob4 77 v dd_io 117 anb1 157 index0 38 pwmb0 78 nc 118 anb2 158 home0 39 pwmb1 79 nc 119 anb3 159 emi_mode 40 pwmb2 80 v ss 120 anb4 160 v ss table 11-3 56f8167 160-pin lqfp package id entification by pin number (continued) pin no. signal name pin no. signal name pin no. signal name pin no. signal name
56f8367 technical data, rev. 7.0 176 freescale semiconductor preliminary figure 11-5 160-pin lqfp mechanical information dim min max millimeters a --- 1.60 a1 0.05 0.15 a2 1.35 1.45 b 0.17 0.27 b1 0.17 0.23 c 0.09 0.20 c1 0.09 0.16 d 26.00 bsc d1 24.00 bsc e 0.50 bsc e 26.00 bsc e1 24.00 bsc l 0.45 0.75 l1 1.00 ref r1 0.08 --- r2 0.08 0.20 s 0.20 --- 0 7 1 0 --- 2 11 13 3 11 13 0.25 6 notes: 1. dimensions are in millimeters. 2. interpret dimensions and tolerances per asme y14.5m, 1994. 3. datums a, b, and d to be determined where the leads exit the plastic body at datum plane h. 4. dimensions d1 and e1 do not include mold protrusion. allowable protrusion is 0.25mm per side. dimensions d1 and e1 are maximum plastic body size dimensions including mold mismatch. 5. dimension b does not include dambar protrusion. allowable dambar protrusion shall not cause the lead width to exceed the maximum b dimension by more than 0.08mm. dambar can not be located on the lower radius or the foot. minimum space between a protrusion and an adjacent lead is 0.07mm. 6. exact shape of corners may vary. d b a d gg d 2 d1 2 e1 2 d1 e1 e 2 e a-b 0.20 d h a-b m 0.08 d c 4x a-b 0.20 d c 160x 0.08 c c seating plane 156x e 4x e/2 160x e detail f 2 1 3 a a2 a1 s l (l1) r1 r2 h gage plane detail f c (b) b c1 section g-g please see http://www.freescale.com for th e most current mechanical drawing.
thermal design considerations 56f8367 technical data, rev. 7.0 freescale semiconductor 177 preliminary part 12 design considerations 12.1 thermal desi gn considerations an estimation of the chip junction temperature, t j , can be obtained from the equation: t j = t a + (r j x p d ) where: the junction-to-ambient thermal resi stance is an industry-standard va lue that provides a quick and easy estimation of thermal perf ormance. unfortunately, there are two values in common usage: the value determined on a single-layer board and the value obtained on a board wi th two planes. for packages such as the pbga, these values can be different by a factor of two. which value is closer to the application depends on the power diss ipated by other components on the board. the value obtained on a single-layer board is appropriate for the tightly packed printed circuit board. the va lue obtained on the board with the internal planes is usually appropriate if the board has low-power dissipation and the components are well separated. when a heat sink is used, the thermal resistance is expressed as the sum of a junction-to-case thermal resistance and a case-to-ambient thermal resistance: r j = r jc + r c where: r jc is device-related and cannot be influenced by the us er. the user controls th e thermal environment to change the case-to-ambient thermal resistance, r ca . for instance, the user can change the size of the heat sink, the air flow around the device, the interface mate rial, the mounting arrange ment on printed circuit board, or change the thermal dissipation on th e printed circuit board surrounding the device. to determine the junction temperature of the device in the application when heat sinks are not used, the thermal characterization parameter ( jt ) can be used to determine th e junction temperature with a measurement of the temperature at the top center of the package case using the following equation: t j = t t + ( jt x p d ) where: t a = ambient temperature for the package ( o c) r j = junction-to-ambient thermal resistance ( o c/w) p d = power dissipation in the package (w) r ja = package junction-to-ambient thermal resistance c/w r jc = package junction-to-case thermal resistance c/w r ca = package case-to-ambient thermal resistance c/w t t = thermocouple temperature on top of package ( o c) jt = thermal characteri zation parameter ( o c)/w p d = power dissipation in package (w)
56f8367 technical data, rev. 7.0 178 freescale semiconductor preliminary the thermal characterization parameter is measured per jesd51-2 specification using a 40-gauge type t thermocouple epoxied to the top ce nter of the package case. the th ermocouple should be positioned so that the thermocouple junction re sts on the package. a small amount of epoxy is placed over the thermocouple junction and over about 1mm of wire extending from the junction. the thermocouple wire is placed flat against the package case to avoid measurement errors caused by cooling effects of the thermocouple wire. when heat sink is used, the junction temperature is determined from a ther mocouple inserted at the interface between the case of the p ackage and the interface material. a clearance slot or hole is normally required in the heat sink. minimizing the size of the clearan ce is important to mi nimize the change in thermal performance caused by removing part of the thermal interface to the heat sink. because of the experimental difficulties with th is technique, many engine ers measure the heat si nk temperature and then back-calculate the case temperatur e using a separate measurement of the thermal resistance of the interface. from this case temperat ure, the junction temperature is de termined from th e junction-to-case thermal resistance. 12.2 electrical design considerations use the following list of considerat ions to assure correct operation: ? provide a low-impedance path from the board power supply to each v dd pin on the hybrid controller, and from the board ground to each v ss (gnd) pin ? the minimum bypass requirement is to place six 0.01?0.1 f capacitors positioned as close as possible to the package supply pins. the recomm ended bypass configuration is to place one bypass capacitor on each of the v dd /v ss pairs, including v dda /v ssa. ceramic and tantalum capacitors tend to provide better performance tolerances. ? ensure that capacitor leads and associated prin ted circuit traces that connect to the chip v dd and v ss (gnd) pins are less than 0.5 inch per capacitor lead ? use at least a four-layer printed circui t board (pcb) with two inner layers for v dd and v ss ? bypass the v dd and v ss layers of the pcb with approximately 100 f, preferably with a high-grade capacitor such as a tantalum capacitor ? because the device?s output signals have fast rise and fall times, pcb trace lengths should be minimal caution this device contains protective circuitry to guard against damage due to high static voltage or electrical fields. however, normal precautions are advised to avoid application of any voltages higher than maximum-rated voltages to this high-impedance circuit. reliability of operation is enhanced if unused inputs are tied to an appropriate voltage level.
power distribution and i/o ring implementation 56f8367 technical data, rev. 7.0 freescale semiconductor 179 preliminary ? consider all device loads as well as parasitic capacitance due to pcb traces when calculating capacitance. this is especially critical in system s with higher capacitive loads that co uld create higher transient currents in the v dd and v ss circuits. ? take special care to minimize noise levels on the v ref , v dda and v ssa pins ? designs that utilize the trst pin for jtag port or eonce module functionality (such as development or debugging systems) should allow a means to assert trst whenever reset is asserted, as well as a means to assert trst independently of reset . designs that do not require debugging functionality, such as consumer products, should tie these pins together. ? because the flash memory is programmed through the jtag/eonce port, the designer should provide an interface to this port to allo w in-circuit flash programming 12.3 power distribution and i/o ring implementation figure 12-1 illustrates the general power control incorporated in the 56f8367/56f8167. this chip contains two internal power regulators. one of them is powered from the v dda_osc_pll pin and cannot be turned off. this regul ator controls power to the internal cl ock generation circuitr y. the other regulator is powered from the v dd_io pins and provides power to all of the internal digi tal logic of the core, all peripherals and the internal memo ries. this regulator can be turned off, if an external v dd_core voltage is externally applied to the v cap pins. in summary, the entire ch ip can be supplied from a single 3.3 volt supp ly if the large core regulator is enabled. if the regulator is not enabled, a dual supply 3.3v/2.5v configurat ion can also be used. notes: ? flash, ram and internal logic are powered from the core regulator output ?v pp 1 and v pp 2 are not connected in the customer system ? all circuitry, analog and digital, shares a common v ss bus figure 12-1 power management reg core v cap i/o adc v dd v ss reg v dda_osc_pll osc v ssa_adc v dda_adc v refh v refp v refmid v refn v reflo
56f8367 technical data, rev. 7.0 180 freescale semiconductor preliminary part 13 ordering information table 13-1 lists the pertinent information needed to pl ace an order. consult a freescale semiconductor sales office or authorized di stributor to determine availability and to order parts. *this package is rohs compliant. table 13-1 ordering information part supply voltage package type pin count frequency (mhz) ambient temperature range order number mc56f8367 3.0?3.6 v low-profile quad flat pack (lqfp) 160 60 -40 to + 105 c mc56f8367vpy60 MC56F8167 3.0?3.6 v low-profile quad flat pack (lqfp) 160 40 -40 to + 105 c MC56F8167vpy mc56f8367 3.0?3.6 v low-profile quad flat pack (lqfp) 160 60 -40 to + 105 c mc56f8367vpye* mc56f8367 3.0?3.6 v low-profile quad flat pack (lqfp) 160 60 -40 to + 125 c mc56f8367mpye* MC56F8167 3.0?3.6 v low-profile quad flat pack (lqfp) 160 40 -40 to + 105 c MC56F8167vpye* mc56f8367 3.0?3.6 v mold array process ball grid array (mapbga) 160 60 -40 to + 105 c mc56f8367vvf*
power distribution and i/o ring implementation 56f8367 technical data, rev. 7.0 freescale semiconductor 181 preliminary
56f8367 technical data, rev. 7.0 182 freescale semiconductor preliminary
power distribution and i/o ring implementation 56f8367 technical data, rev. 7.0 freescale semiconductor 183 preliminary
how to reach us: home page: www.freescale.com e-mail: support@freescale.com usa/europe or locations not listed: freescale semiconductor technical information center, ch370 1300 n. alma school road chandler, arizona 85224 +1-800-521-6274 or +1-480-768-2130 support@freescale.com europe, middle east, and africa: freescale halbleiter deutschland gmbh technical information center schatzbogen 7 81829 muenchen, germany +44 1296 380 456 (english) +46 8 52200080 (english) +49 89 92103 559 (german) +33 1 69 35 48 48 (french) support@freescale.com japan: freescale semiconductor japan ltd. headquarters arco tower 15f 1-8-1, shimo-meguro, meguro-ku, tokyo 153-0064, japan 0120 191014 or +81 3 5437 9125 support.japan@freescale.com asia/pacific: freescale semiconductor hong kong ltd. technical information center 2 dai king street tai po industrial estate tai po, n.t., hong kong +800 2666 8080 support.asia@freescale.com for literature requests only: freescale semiconductor literature distribution center p.o. box 5405 denver, colorado 80217 1-800-441-2447 or 303-675-2140 fax: 303-675-2150 ldcforfreescalesemiconductor@hibbertgroup.com freescale? and the freescale logo are trademarks of freescale semiconductor, inc. all other product or service names are the property of their respective owners. this product incorporates superflash? technology licensed from sst. ? freescale semiconductor, inc. 2005, 2006. all rights reserved. mc56f8367 rev. 7.0 06/2006 information in this document is provided solely to enable system and software implementers to use freescale semiconductor products. there are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document. freescale semiconductor reserves the right to make changes without further notice to any products herein. freescale semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does freescale semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. ?typical? parameters that may be provided in freescale semiconductor data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including ?typicals?, must be validated for each customer application by customer?s technical ex perts. freescale semiconductor does not convey any license under its patent rights nor the rights of others. freescale semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the freescale semiconductor product could create a situation where personal injury or death may occur. should buyer purchase or use freescale semiconductor products for any such unintended or unauthorized application, buyer shall indemnify and hold freescale semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that freescale semiconductor was negligent regarding the design or manufacture of the part. rohs-compliant and/or pb-free versions of freescale products have the functionality and electrical characteristics of their non-rohs-compliant and/or non-pb-free counterparts. for further information, see http://www.freescale.com or contact your freescale sales representative. for information on freescale?s environmental products program, go to http://www.freescale.com/epp .

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