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mp2930 4-phase pwm controller with 8-bit dac code mp2930 rev. 0.9 www.monolithicpower.com 1 1/27/2010 mps proprietary information. unaut horized photocopy and duplication prohibited. ? 2010 mps. all rights reserved. the future of analog ic technology description the mp2930 is a 4-phase, synchronous buck switching regulator controller for regulating microprocessor core voltage. mp2930 also uses dual edge pwm mode to realize fast load transient with fewer capacitors. for meeting the requirement of microprocessor output voltage drops tightly as load current increases, output current is sensed to realize voltage droop function. accurate current balancing is included in mp2930 to provide current balance for each channel. 8-bit id input with selectable vr11 code and extended vr10 code can set output voltage dynamically. the mp2930 also provides accurate and reliable over current protection and over voltage protection. features ? 2-, 3- or 4-phase operation ? channel-current balancing ? voltage droop vs. load current ? precision resistor or dcr current sensing ? 8-bit id input with selectable between vr11 and vr10 code at 6.25mv per bit ? adjustable switching frequency ? over current protection ? over voltage protection ? available in a 40-pin qfn6x6 package applications ? power modules ? desktop, server, core voltage ? pols (memory) ?mps? and ?the future of analog ic technology? are registered trademarks of monolithic power systems, inc. typical application (4-phase buck converter)
mp2930 - 4-phase pwm controller with 8-bit dac code mp2930 rev. 0.9 www.monolithicpower.com 2 1/27/2010 mps proprietary information. unaut horized photocopy and duplication prohibited. ? 2010 mps. all rights reserved. ordering information * for tape & reel, add suffix ?z (e.g. mp2930eqk?z); for rohs compliant packaging, add suffix ?lf; (e.g. mp2930eqk ?lf?z). package reference top view id6 id5 id4 id3 id2 id1 id0 vrsel ofs dac isen3+ isen3- isen2- isen2+ pwm2 pwm4 isen4+ isen4- isen1- isen1+ ref comp fb idroop vdiff rgnd vsen sd vcc pwm1 id7 tm vr_hot vr_fan vr_rdy ss fs en_vtt en_pwr pwm3 1 2 3 4 5 6 7 8 11 12 13 14 15 16 23 22 21 25 24 31 32 33 34 35 36 37 38 39 28 27 26 30 29 17 18 19 20 9 10 40 absolute maxi mum ratings (1) supply voltage vcc ..................................... 6v all other pins ..................... -0.3v to vcc + 0.3v continuous power dissipation (t a = +25c) (2) ............................................................. 3.9w junction temperature ...............................150 c storage temperature.............. ?65 c to +150 c esd rating human body model .................................... 2kv machine model .......................................... 200v charged device model ............................. 1.5kv recommended operating conditions (3) supply voltage vcc ........................... +5v 5% operating junct.temp. ........... ?20 c to +125 c thermal resistance (4) ja jc qfn40 (6mm x 6mm) ............. 32 ...... 3.5 .. c/w notes: 1) exceeding these ratings may damage the device. 2) the maximum allowable power dissipation is a function of the maximum junction temperature t j (max) , the junction-to- ambient thermal resistance ja , and the ambient temperature t a . the maximum allowable continuous power dissipation at any ambient temperature is calculated by p d (max) = (t j (max) - t a ) / ja . exceeding the maximum allowable power dissipation will cause excessive die temperature, and the regulator will go into thermal shutdown. internal thermal shutdown circuitry protects the device from permanent damage. 3) the device is not guaranteed to function outside of its operating conditions. 4) measured on jesd51-7, 4-layer pcb. part number* package top marking free air temperature (t a ) mp2930eqk qfn (6mm x 6mm) 2930e ?20 c to +85 c
mp2930 - 4-phase pwm controller with 8-bit dac code mp2930 rev. 0.9 www.monolithicpower.com 3 1/27/2010 mps proprietary information. unaut horized photocopy and duplication prohibited. ? 2010 mps. all rights reserved. electrical characteristics operating conditions: v cc = 5v, unless otherwise noted. parameter test conditions min typ max units v cc supply current nominal supply vcc=5vdc; en_pwr=5vdc; rt=100k ? , isen1=isen2=isen3=isen4=- 70ua 18 26 ma shutdown supply vcc=5vdc; en_pwr=0vdc; rt=100 k ? 14 21 ma power-on reset and enable vcc rising 4.3 4.5 4.7 v por threshold vcc falling 3.7 3.9 4.2 v rising 0.850 0.875 0.910 v hysteresis - 130 - mv en_pwr threshold falling 0.720 0.745 0.75 v rising 0.850 0.875 0.910 v hysteresis - 130 - mv en_vtt threshold falling 0.720 0.745 0.75 v reference voltage and dac system accuracy of mp2930 (id =1v to 1.6v, tj=0 c to +70 c) -0.5 - 0.5 G id system accuracy of mp2930 (id =0.5v to 1v, tj=0 c to +70 c) -0.9 0.9 G id id pull-up -60 -40 -20 ua id input low level - - 0.4 v id input high level 0.8 - - v vrsel input low level - - 0.4 v vrsel input high level 0.8 - - v dac source current - 4 7 ma dac sink current - - 300 ua ref source current 45 50 55 ua ref sink current 45 50 55 ua pin-adjustable offset offset resistor connected to ground 380 400 420 mv voltage at ofs pin voltage below vcc, offset resistor connected to vcc 1.55 1.600 1.65 v oscillators accuracy of switching frequency setting rt=100k ? 225 250 275 khz adjustment range of switching frequency 0.08 - 1.0 mhz soft-start ramp rate rs=100k ? - 2.344 - mv/us adjustment range of soft-start ramp rage 0.625 - 6.25 mv/us pwm generator sawtooth amplitude - 1.25 - v
mp2930 - 4-phase pwm controller with 8-bit dac code mp2930 rev. 0.9 www.monolithicpower.com 4 1/27/2010 mps proprietary information. unaut horized photocopy and duplication prohibited. ? 2010 mps. all rights reserved. electrical characteristics (continued) operating conditions: v cc = 5v, unless otherwise noted. parameter test conditions min typ max units error amplifier open-loop gain rl=10k ? to ground - 96 - db open-loop bandwidth - 80 - mhz slew rage - 25 - v/us maximum output voltage 3.8 4.3 4.9 v output high voltage @ 2ma 3.6 - - v output low voltage @ 2ma - - 1.8 v remote-sense amplifier bandwidth - 20 - mhz output high current vsen-rgnd=2.5v -500 - 500 ua output high current vsen-rgnd=0.6 -500 - 500 ua pwm output pwm output voltage low threshold iload=500ua - - 0.5 v pwm output voltage high threshold iload=500ua 4.3 - - v current sense and over-current protection sensed current tolerance(idroop) isen1=isen2=isen3=isen4=60u a 57 60 63 ua overcurrent trip level for average current 72 85 98 ua peak current limit for individual channel 100 120 140 ua thermal monitoring and fan control tm input voltage for vr_fan trip 1.55 1.65 1.75 v tm input voltage for vr_fan reset 1.85 1.95 2.05 v tm input voltage for vr_hot trip 1.3 1.4 1.5 v tm input voltage for vr_hot reset 1.55 1.65 1.75 v leakage current of vr_fan with externally pull-up resistor connected to vcc - - 30 ua vr_ran low voltage ivr_fan=4ma - - 0.4 v leakage current of vr_hot with externally pull-up resistor connected to vcc - - 30 ua vr_hot low voltage ivr_hot=4ma - - 0.4 v vr ready and protection monitors leakage current of vr_rdy with externally pull-up resistor connected to vcc - - 30 ua vr_rdy low voltage ivr_rdy=4ma - - 0.4 v undervoltage threshold vdiff falling 48 50 52 G id vr_rdy reset voltage vdiff rising 58 60 62 G id before valid id 1.250 1.27 5 1.300 v overvoltage protection threshold after valid id, the voltage above id 150 175 200 mv overvoltage protection reset hysteresis - 100 - mv
mp2930 - 4-phase pwm controller with 8-bit dac code mp2930 rev. 0.9 www.monolithicpower.com 5 1/27/2010 mps proprietary information. unaut horized photocopy and duplication prohibited. ? 2010 mps. all rights reserved. pin functions pin # name description 1 id6 2 id5 3 id4 4 id3 5 id2 6 id1 7 id0 id inputs from microprocessor. these c odes determine output regulation voltage. 8 vrsel select internal id code. when it is tied to gnd, the extended vr10 is selected. when it?s floated or tied to high, vr11 code is selected. 9 ofs offset between ref and dac program pin. the ofs pin can be used to program a dc offset current which will generate a dc offs et voltage between the ref and dac pins. the polarity of the offset is selected by c onnecting the resistor to gnd or vcc. for no offset, the ofs pin should be left unconnected. 10 dac internal dac reference output determined by id codes 11 ref error amplifier input. a capacitor 0.1uf is used between ref and gnd to smooth the voltage transition during dynamic id operations. 12 comp error amplifier output pin. tie to compensation network 13 fb output voltage feedback pin. 14 idroop current proportional to load current is flowed out through this pin 15 vdiff remote sense amplif ier output. vdiff-gnd=vsen-rgnd 16 rgnd remote sense amplifier input. remote output gnd 17 vsen remote sense amplifier input. remote output. 18 sd shutdown driver mos @ hiz state. mp 2930 cooperates with mps drmos mp86981 and sd pin is connected to the en of mp86981. 19 vcc power supply. connect this pin directly to a +5v supply. 20 pwm1 phase 1 pwm output. 21 isen1+ 22 isen1- phase 1 current sense amplifier differential input 23 isen4+ 24 isen4- phase 4 current sense amplifier differential input 25 pwm4 phase 4 pwm output. connect pwm4 to vcc to configure for 3-phase operation. 26 pwm2 phase 2 pwm output. 27 isen2+ 28 isen2- phase 1 current sense amplifier differential input 29 isen3- 30 isen3+ phase 3 current sense amplifier differential input 31 pwm3 phase 3 pwm output. connect pwm3 to vcc to configure for 2-phase operation. 32 en_pwr enable pin. it is used to synchronize powe r-up of the controller and mosfet driver ics. 33 en_vtt enable pin. it is controlled by output of vtt voltage regulator in the mother board.
mp2930 - 4-phase pwm controller with 8-bit dac code mp2930 rev. 0.9 www.monolithicpower.com 6 1/27/2010 mps proprietary information. unaut horized photocopy and duplication prohibited. ? 2010 mps. all rights reserved. pin functions (continued) pin # name description 34 fs pwm frequency set pin. a resistor from fs to gnd will set the switching frequency. 35 ss soft start oscillator frequency set pin. a re sistor from ss to gnd will set up the soft- start ramp rate. 36 vr_rdy open drain logic output. when soft start completed and output voltage is regulated in the value determined by id setting, vr_rdy is logic high. 37 vr_fan open drain logic output. it is open when vr temperature reaches certain value 38 vr_hot open drain logic output. it is open when vr temperature reaches certain value 39 tm ntc resistor in this pin is used to moni tor inductor temperature. connect this pin through an ntc thermistor to gnd and a resist or to vcc of the controller. the voltage at this pin is reverse proport ional to the vr temperature. 40 id7 id input
mp2930 - 4-phase pwm controller with 8-bit dac code mp2930 rev. 0.9 www.monolithicpower.com 7 1/27/2010 mps proprietary information. unaut horized photocopy and duplication prohibited. ? 2010 mps. all rights reserved. typical performanc e characteristics v in =12v, vid =1.2v, l=0.3h, fsw=600khz, inductor dcr sensing, 4-phase operation, t a =+25c, unless otherwise noted. shutdown supply current vs. v cc switching frequency vs. r t i out =0a switching frequency vs. temperature switching frequency vs. output current line regulation i out =80a efficiency normal supply current vs. v cc 12 13 14 15 16 17 18 19 20 3.5 4 4.5 5 5.5 6 6.5 v cc (v) 3.5 4 4.5 5 5.5 6 6.5 v cc (v) normal supply current (ma) 12 13 14 15 16 17 18 shutdown supply current (ma) 0 200 400 600 800 1000 1200 0 50 100 150 200 250 300 350 switching frequency (khz) 560 580 600 620 640 660 0 102030405060708090 output current (a) switching frequency (khz) 560 580 600 620 640 660 switching frequency (khz) -40 -20 0 20 40 60 80 100 20 30 40 50 60 70 80 90 300 400 500 600 700 800 900 overcurrent trip point (a) 1.10 1.12 1.14 1.16 1.18 1.20 1.22 0 102030405060708090 output current (a) output voltage (v) -2.0 -1.5 -1.0 -0.5 0.0 0.5 1.0 1.5 2.0 6 8 10 12 14 16 18 input voltage (v) normalized output voltage (%) 50 55 60 65 70 75 80 85 90 0102030405060708090 output current (a) efficiency (%)
mp2930 - 4-phase pwm controller with 8-bit dac code mp2930 rev. 0.9 www.monolithicpower.com 8 1/27/2010 mps proprietary information. unaut horized photocopy and duplication prohibited. ? 2010 mps. all rights reserved. typical performanc e characteristics (continued) v in =12v, vid =1.2v, l=0.3h, fsw=600khz, inductor dcr sensing, 4-phase operation, t a =+25c, unless otherwise noted. v out 500mv/div. en_vtt 2v/div. vr_rdy 5v/div. sd 5v/div. v out 500mv/div. en_vtt 2v/div. vr_rdy 5v/div. sd 5v/div. v out 500mv/div. vr_rdy 5v/div. sd 5v/div. 400us/div. 1us/div. 1us/div. 1us/div. 400ms/div. 4ms/div. 4ms/div. 400ns/div. 400ns/div. en_vtt startup i out = 0a en_vtt shutdown i out = 0a inductor current of 4-phase i out = 0a inductor current of 4-phase i out = 30a v out /ac 50mv/div. v out /ac 10mv/div. v out /ac 50mv/div. load step-up response i out =0a to 50a @ 500a/us load step-down response i out =50a to 0a @ 500a/us output ripple voltage i out = 40a ocp entry i ocp =83a, risistive sensing ocp recorvey risistive sensing i l1 2a/div. i l2 2a/div. i l3 2a/div. i l4 2a/div. i l1 2a/div. i l2 2a/div. i l3 2a/div. i l4 2a/div. i l1 10a/div. v out 500mv/div. vr_rdy 5v/div. sd 5v/div. i l1 10a/div. pwm2 5v/div. pwm3 5v/div. pwm4 5v/div. pwm2 5v/div. pwm3 5v/div. pwm4 5v/div. pwm2 5v/div. pwm3 5v/div. pwm4 5v/div.
mp2930 - 4-phase pwm controller with 8-bit dac code mp2930 rev. 0.9 www.monolithicpower.com 9 1/27/2010 mps proprietary information. unaut horized photocopy and duplication prohibited. ? 2010 mps. all rights reserved. block diagram ss isen4- isen4+ isen3- isen3+ isen2- isen2+ isen1- isen1+ i_trip rgnd id7 id6 id5 id4 id3 id2 id1 id0 vrsel dac ofs ref fb comp idroop vr_hot vr_fan tm sd gnd pwm4 pwm3 pwm2 pwm1 en_pwr en_vtt 0.875 0.875 vsen vdiff vr_rdy fs n n x1 ovp power-on reset (por) clock and ramp genetator soft-start and fault logic +175mv dynamic vid d/a offset e/a ocp channel detect channel current sense channel current balance and peak current limit pwm modulator pwm modulator pwm modulator pwm modulator shutdown driver mos @ hiz state thermal monitor n 1 vcc figure 1?functional block diagram
mp2930 - 4-phase pwm controller with 8-bit dac code mp2930 rev. 0.9 www.monolithicpower.com 10 1/27/2010 mps proprietary information. unaut horized photocopy and duplication prohibited. ? 2010 mps. all rights reserved. operation multiphase power conversion the mp2930 is a multiphase regulators and it can be programmed for 2-, 3- or 4-channel operation for microprocessor core. the switching of each channel in a multiphase converter is timed to be symmetrically out-of- phase with each of the other channels. the interleaving work of each phase can help to reduce of ripple current amplitude and to reduce input ripple current. pwm operation under steady state conditions the operation of the mp2930 appears to be that of a conventional trailing edge modulator. conventional analysis and design methods can be used for steady state and small signal operation. under load transition condition, the mp2930 can turn on all phase together to improve the load transient. it can achieve excellent transient performance and reduce the demand on the output capacitors. the default channel setting for the mp2930 is four and the timing of each channel is set by the number of active channels. the cycle time of the pulse signal is the inverse of the switching frequency set by the resistor between the fs pin and gnd. for 4-channel operation, the channel firing order is 4-3-2-1: pwm3 pulse happens 1/4 of a cycle after pwm4, pwm2 output follows another 1/4 of a cycle after pwm3, and pwm1 delays another 1/4 of a cycle after pwm2. for 3-channel operation, the channel firing order is 3-2-1. connecting pwm4 to vcc selects 3-phase operation and the pulse times are spaced in 1/3 cycle increments. if pwm3 is connected to vcc, 2-phase operation is selected and the pwm2 pulse happens 1/2 of a cycle after pwm pulse. switching frequency the mp2930 switching frequency is set by the external resistor r t between the fs pin and gnd. the resistor r t can be estimated by: equation (1). sw 10 t f 10 2.5 r = (1) where f sw is the switching frequency of each phase. current sensing mp2930 has cycle by cycle current sense for fast response. mp2930 adopts inductor dcr sensing, or resistive sensing techniques. the sense current, i sen , is proportional to the inductor current. the sensed current is used for current balance, load-line regulation, and overcurrent protection. inductor dcr sensing the mp2930 can adopt a lossless current sensing scheme, commonly referred to as inductor dcr sensing, as shown in figure 2. figure 2?dcr sensing configuration equation (2) shows the s-domain equivalent voltage across the inductor v l . () dcr l s l i l v + ? ? = (2) a simple rc network across the inductor extracts the dcr voltage, as shown in figure 2. the voltage on the capacitor v c is proportional to the channel current i l , see equation (3). () () 1 rc s l i dcr 1 dcr l s c v + ? ? ? ? ? ? ? ? ? + ? = (3)
mp2930 - 4-phase pwm controller with 8-bit dac code mp2930 rev. 0.9 www.monolithicpower.com 11 1/27/2010 mps proprietary information. unaut horized photocopy and duplication prohibited. ? 2010 mps. all rights reserved. if the rc network components are selected such that the rc time constant (=r*c) matches the inductor time constant (=l/dcr), the voltage across the capacitor v c is equal to the voltage drop across the dcr, i.e., proportional to the channel current. therefore, the current out of isen+ pin (i sen ), is proportional to the inductor current and it can be seen form equation (4). isen r dcr l i sen i ? = (4) resistive sensing for accurate current sense, a current-sense resistor r sense in series with each output inductor can serve as the current sense element (see figure 3). this technique is more accurate, but reduces overall converter efficiency due to the additional power loss on the current sense resistor r sense . equation (5) shows the ratio of the channel current to the sensed current i sen . isen r sense r l i sen i ? = (5) figure 3?sense resistor in series with inductors the inductor dcr value will increase as the temperature increases. therefore the sensed current will increase as the temperature of the current sense element increases. in order to compensate the temperature effect on the sensed current signal, a positive temperature coefficient (ptc) resistor can be selected for the sense resistor r isen . channel-current balance the sensed current i n from each active channel is summed together and divided by the number of active channels. the resulting average current (i avg ) provides a measure of the total load current. channel current balance is achieved by comparing the sensed current of each channel to the average current to make an appropriate adjustment to the pwm duty cycle of each channel. channel current balance is essential in achieving the thermal advantage of multiphase operation. with good current balance, the power loss is equally dissipated over multiple devices and a greater area. voltage regulation the compensation network shown in figure 4 assures that the steady-state error in the output voltage is limited only to the error in the reference voltage (output of the dac) and offset errors in the ofs current source, remote- sense and error amplifiers. figure 4?output voltage and load-line regulation with offset adjustment
mp2930 - 4-phase pwm controller with 8-bit dac code mp2930 rev. 0.9 www.monolithicpower.com 12 1/27/2010 mps proprietary information. unaut horized photocopy and duplication prohibited. ? 2010 mps. all rights reserved. the output of the error amplifier (v comp ) is compared to sawtooth waveforms to generate the pwm signals. the pwm signals control the timing of the mp86981 and regulate the converter output to the specified reference voltage. the internal and external circuitry, which control voltage regulation are shown in figure 4. the mp2930 incorporates an internal differential remote-sense amplifier in the feedback path, which results in a more accurate means of sensing output voltage. connect the microprocessor sense pins to the non-inverting input (vsen) and inverting input (rgnd) of the remote-sense amplifier. the remote-sense output (vdiff) is connected to the inverting input of the error amplifier through an external resistor. each id input offers a 45a pull-up to an internal 2.5v source for use with open-drain outputs. the pull-up current diminishes to zero above the logic threshold to protect voltage- sensitive output devices. external pull-up resistors can augment the pull-up current sources if case leakage into the driving device is greater than 45a. table 1?vr10 id table (with 6.25mv extension) id4 400mv id3 200mv id2 100mv id1 50mv id0 25mv id5 12.5mv id6 6.25mv voltage (v) 0 1 0 1 0 1 1 1.60000 0 1 0 1 0 1 0 1.59375 0 1 0 1 1 0 1 1.58750 0 1 0 1 1 0 0 1.58125 0 1 0 1 1 1 1 1.57500 0 1 0 1 1 1 0 1.56875 0 1 1 0 0 0 1 1.56250 0 1 1 0 0 0 0 1.55625 0 1 1 0 0 1 1 1.55000 0 1 1 0 0 1 0 1.54375 0 1 1 0 1 0 1 1.53750 0 1 1 0 1 0 0 1.53125 0 1 1 0 1 1 1 1.52500 0 1 1 0 1 1 0 1.51875 0 1 1 1 0 0 1 1.51250 0 1 1 1 0 0 0 1.50625 table 1?vr10 id table (with 6.25mv extension) continued id4 400mv id3 200mv id2 100mv id1 50mv id0 25mv id5 12.5mv id6 6.25mv voltage (v) 0 1 1 1 0 1 1 1.50000 0 1 1 1 0 1 0 1.49375 0 1 1 1 1 0 1 1.4875 0 1 1 1 1 0 0 1.48125 0 1 1 1 1 1 1 1.47500 0 1 1 1 1 1 0 1.46875 1 0 0 0 0 0 1 1.46250 1 0 0 0 0 0 0 1.45625 1 0 0 0 0 1 1 1.45000 1 0 0 0 0 1 0 1.44375 1 0 0 0 1 0 1 1.43750 1 0 0 0 1 0 0 1.43125 1 0 0 0 1 1 1 1.42500 1 0 0 0 1 1 0 1.41875 1 0 0 1 0 0 1 1.41250 1 0 0 1 0 0 0 1.40625 1 0 0 1 0 1 1 1.40000 1 0 0 1 0 1 0 1.39375 1 0 0 1 1 0 1 1.38750 1 0 0 1 1 0 0 1.38125 1 0 0 1 1 1 1 1.37500 1 0 0 1 1 1 0 1.36875 1 0 1 0 0 0 1 1.36250 1 0 1 0 0 0 0 1.35625 1 0 1 0 0 1 1 1.35000 1 0 1 0 0 1 0 1.34375 1 0 1 0 1 0 1 1.33750 1 0 1 0 1 0 0 1.33125 1 0 1 0 1 1 1 1.32500 1 0 1 0 1 1 0 1.31875 1 0 1 1 0 0 1 1.31250 1 0 1 1 0 0 0 1.30625 1 0 1 1 0 1 1 1.30000 1 0 1 1 0 1 0 1.29375 1 0 1 1 1 0 1 1.28750 1 0 1 1 1 0 0 1.28125 1 0 1 1 1 1 1 1.27500 1 0 1 1 1 1 0 1.26875
mp2930 - 4-phase pwm controller with 8-bit dac code mp2930 rev. 0.9 www.monolithicpower.com 13 1/27/2010 mps proprietary information. unaut horized photocopy and duplication prohibited. ? 2010 mps. all rights reserved. table 1?vr10 id table (with 6.25mv extension) continued id4 400mv id3 200mv id2 100mv id1 50mv id0 25mv id5 12.5mv id6 6.25mv voltage (v) 1 1 0 0 0 0 1 1.26250 1 1 0 0 0 0 0 1.25625 1 1 0 0 0 1 1 1.25000 1 1 0 0 0 1 0 1.24375 1 1 0 0 1 0 1 1.23750 1 1 0 0 1 0 0 1.23125 1 1 0 0 1 1 1 1.22500 1 1 0 0 1 1 0 1.21875 1 1 0 1 0 0 1 1.21250 1 1 0 1 0 0 0 1.20625 1 1 0 1 0 1 1 1.20000 1 1 0 1 0 1 0 1.19375 1 1 0 1 1 0 1 1.18750 1 1 0 1 1 0 0 1.18125 1 1 0 1 1 1 1 1.17500 1 1 0 1 1 1 0 1.16875 1 1 1 0 0 0 1 1.16250 1 1 1 0 0 0 0 1.15625 1 1 1 0 0 1 1 1.15000 1 1 1 0 0 1 0 1.14375 1 1 1 0 1 0 1 1.13750 1 1 1 0 1 0 0 1.13125 1 1 1 0 1 1 1 1.12500 1 1 1 0 1 1 0 1.11875 1 1 1 1 0 0 1 1.11250 1 1 1 1 0 0 0 1.10625 1 1 1 1 0 1 1 1.10000 1 1 1 1 0 1 0 1.09375 1 1 1 1 1 0 1 off 1 1 1 1 1 0 0 off 1 1 1 1 1 1 1 off 1 1 1 1 1 1 0 off 0 0 0 0 0 0 1 1.08750 0 0 0 0 0 0 0 1.08125 0 0 0 0 0 1 1 1.07500 0 0 0 0 0 1 0 1.06875 0 0 0 0 1 0 1 1.06250 table 1?vr10 id table (with 6.25mv extension) continued id4 400mv id3 200mv id2 100mv id1 50mv id0 25mv id5 12.5mv id6 6.25mv voltage (v) 0 0 0 0 1 0 0 1.05625 0 0 0 0 1 1 1 1.05000 0 0 0 0 1 1 0 1.04375 0 0 0 1 0 0 1 1.03750 0 0 0 1 0 0 0 1.03125 0 0 0 1 0 1 1 1.02500 0 0 0 1 0 1 0 1.01875 0 0 0 1 1 0 1 1.01250 0 0 0 1 1 0 0 1.00625 0 0 0 1 1 1 1 1.00000 0 0 0 1 1 1 0 0.99375 0 0 1 0 0 0 1 0.9875 0 0 1 0 0 0 0 0.98125 0 0 1 0 0 1 1 0.97500 0 0 1 0 0 1 0 0.96875 0 0 1 0 1 0 1 0.9625 0 0 1 0 1 0 0 0.95625 0 0 1 0 1 1 1 0.95000 0 0 1 0 1 1 0 0.94375 0 0 1 1 0 0 1 0.93750 0 0 1 1 0 0 0 0.93125 0 0 1 1 0 1 1 0.92500 0 0 1 1 0 1 0 0.91875 0 0 1 1 1 0 1 0.91250 0 0 1 1 1 0 0 0.90625 0 0 1 1 1 1 1 0.90000 0 0 1 1 1 1 0 0.89375 0 1 0 0 0 0 1 0.88750 0 1 0 0 0 0 0 0.88125 0 1 0 0 0 1 1 0.87500 0 1 0 0 0 1 0 0.86875 0 1 0 0 1 0 1 0.86250 0 1 0 0 1 0 0 0.85625 0 1 0 0 1 1 1 0.85000 0 1 0 0 1 1 0 0.84375 0 1 0 1 0 0 1 0.83750 0 1 0 1 0 0 0 0.83125
mp2930 - 4-phase pwm controller with 8-bit dac code mp2930 rev. 0.9 www.monolithicpower.com 14 1/27/2010 mps proprietary information. unaut horized photocopy and duplication prohibited. ? 2010 mps. all rights reserved. table 2?vr11 id 8-bit id7 id6 id5 id4 id3 id2 id1 id0 voltage 0 0 0 0 0 0 0 0 off 0 0 0 0 0 0 0 1 off 0 0 0 0 0 0 1 0 1.60000 0 0 0 0 0 0 1 1 1.59375 0 0 0 0 0 1 0 0 1.58750 0 0 0 0 0 1 0 1 1.58125 0 0 0 0 0 1 1 0 1.57500 0 0 0 0 0 1 1 1 1.56875 0 0 0 0 1 0 0 0 1.56250 0 0 0 0 1 0 0 1 1.55625 0 0 0 0 1 0 1 0 1.55000 0 0 0 0 1 0 1 1 1.54375 0 0 0 0 1 1 0 0 1.53750 0 0 0 0 1 1 0 1 1.53125 0 0 0 0 1 1 1 0 1.52500 0 0 0 0 1 1 1 1 1.51875 0 0 0 1 0 0 0 0 1.51250 0 0 0 1 0 0 0 1 1.50625 0 0 0 1 0 0 1 0 1.50000 0 0 0 1 0 0 1 1 1.49375 0 0 0 1 0 1 0 0 1.48750 0 0 0 1 0 1 0 1 1.48125 0 0 0 1 0 1 1 0 1.47500 0 0 0 1 0 1 1 1 1.46875 0 0 0 1 1 0 0 0 1.46250 0 0 0 1 1 0 0 1 1.45625 0 0 1 0 0 1 1 1 1.36875 0 0 1 0 1 0 0 0 1.36250 0 0 1 0 1 0 0 1 1.35625 0 0 1 0 1 0 1 0 1.35000 0 0 1 0 1 0 1 1 1.34375 0 0 1 0 1 1 0 0 1.33750 0 0 1 0 1 1 0 1 1.33125 0 0 1 0 1 1 1 0 1.32500 0 0 1 0 1 1 1 1 1.31875 0 0 1 1 0 0 0 0 1.31250 0 0 1 1 0 0 0 1 1.30625 0 0 1 1 0 0 1 0 1.30000 table 2?vr11 id 8-bit continued id7 id6 id5 id4 id3 id2 id1 id0 voltage 0 0 1 1 0 0 1 1 1.29375 0 0 1 1 0 1 0 0 1.28750 0 0 1 1 0 1 0 1 1.28125 0 0 1 1 0 1 1 0 1.27500 0 0 1 1 0 1 1 1 1.26875 0 0 1 1 1 0 0 0 1.26250 0 0 1 1 1 0 0 1 1.25625 0 0 1 1 1 0 1 0 1.25000 0 0 1 1 1 0 1 1 1.24375 0 0 1 1 1 1 0 0 1.23750 0 0 1 1 1 1 0 1 1.23125 0 0 1 1 1 1 1 0 1.22500 0 0 1 1 1 1 1 1 1.21875 0 1 0 0 0 0 0 0 1.21250 0 1 0 0 0 0 0 1 1.20625 0 1 0 0 0 0 1 0 1.20000 0 1 0 0 0 0 1 1 1.19375 0 1 0 0 0 1 0 0 1.18750 0 1 0 0 0 1 0 1 1.18125 0 1 0 0 0 1 1 0 1.17500 0 1 0 0 0 1 1 1 1.16875 0 1 0 0 1 0 0 0 1.16250 0 1 0 0 1 0 0 1 1.15625 0 1 0 0 1 0 1 0 1.15000 0 1 0 0 1 0 1 1 1.14375 0 1 0 0 1 1 0 0 1.13750 0 1 0 0 1 1 0 1 1.13125 0 1 0 0 1 1 1 0 1.12500 0 1 0 0 1 1 1 1 1.11875 0 1 0 1 0 0 0 0 1.11250 0 1 0 1 0 0 0 1 1.10625 0 1 0 1 0 0 1 0 1.10000 0 1 0 1 0 0 1 1 1.09375 0 1 0 1 0 1 0 0 1.08750 0 1 0 1 0 1 0 1 1.08125 0 1 0 1 0 1 1 0 1.07500 0 1 0 1 0 1 1 1 1.06875 0 1 0 1 1 0 0 0 1.06250
mp2930 - 4-phase pwm controller with 8-bit dac code mp2930 rev. 0.9 www.monolithicpower.com 15 1/27/2010 mps proprietary information. unaut horized photocopy and duplication prohibited. ? 2010 mps. all rights reserved. table 2?vr11 id 8-bit continued id7 id6 id5 id4 id3 id2 id1 id0 voltage 0 1 0 1 1 0 0 1 1.05625 0 1 0 1 1 0 1 0 1.05000 0 1 0 1 1 0 1 1 1.04375 0 1 0 1 1 1 0 0 1.03750 0 1 0 1 1 1 0 1 1.03125 0 1 0 1 1 1 1 0 1.02500 0 1 0 1 1 1 1 1 1.01875 0 1 1 0 0 0 0 0 1.01250 0 1 1 0 0 0 0 1 1.00625 0 1 1 0 0 0 1 0 1.00000 0 1 1 0 0 0 1 1 0.99375 0 1 1 0 0 1 0 0 0.98750 0 1 1 0 0 1 0 1 0.98125 0 1 1 0 0 1 1 0 0.97500 0 1 1 0 0 1 1 1 0.96875 0 1 1 0 1 0 0 0 0.96250 0 1 1 0 1 0 0 1 0.95625 0 1 1 0 1 0 1 0 0.95000 0 1 1 0 1 0 1 1 0.94375 0 1 1 0 1 1 0 0 0.93750 0 1 1 0 1 1 0 1 0.93125 0 1 1 0 1 1 1 0 0.92500 0 1 1 0 1 1 1 1 0.91875 0 1 1 1 0 0 0 0 0.91250 0 1 1 1 0 0 0 1 0.90625 0 1 1 1 0 0 1 0 0.90000 0 1 1 1 0 0 1 1 0.89375 0 1 1 1 0 1 0 0 0.88750 0 1 1 1 0 1 0 1 0.88125 0 1 1 1 0 1 1 0 0.87500 0 1 1 1 0 1 1 1 0.86875 0 1 1 1 1 0 0 0 0.86250 0 1 1 1 1 0 0 1 0.85625 0 1 1 1 1 0 1 0 0.85000 0 1 1 1 1 0 1 1 0.84375 0 1 1 1 1 1 0 0 0.83750 0 1 1 1 1 1 0 1 0.83125 0 1 1 1 1 1 1 0 0.82500 table 2?vr11 id 8-bit continued id7 id6 id5 id4 id3 id2 id1 id0 voltage 0 1 1 1 1 1 1 1 0.81875 1 0 0 0 0 0 0 0 0.81250 1 0 0 0 0 0 0 1 0.80625 1 0 0 0 0 0 1 0 0.80000 1 0 0 0 0 0 1 1 0.79375 1 0 0 0 0 1 0 0 0.78750 1 0 0 0 0 1 0 1 0.78125 1 0 0 0 0 1 1 0 0.77500 1 0 0 0 0 1 1 1 0.76875 1 0 0 0 1 0 0 0 0.76250 1 0 0 0 1 0 0 1 0.75625 1 0 0 0 1 0 1 0 0.75000 1 0 0 0 1 0 1 1 0.74375 1 0 0 0 1 1 0 0 0.73750 1 0 0 0 1 1 0 1 0.73125 1 0 0 0 1 1 1 0 0.72500 1 0 0 0 1 1 1 1 0.71875 1 0 0 1 0 0 0 0 0.71250 1 0 0 1 0 0 0 1 0.70625 1 0 0 1 0 0 1 0 0.70000 1 0 0 1 0 0 1 1 0.69375 1 0 0 1 0 1 0 0 0.68750 1 0 0 1 0 1 0 1 0.68125 1 0 0 1 0 1 1 0 0.67500 1 0 0 1 0 1 1 1 0.66875 1 0 0 1 1 0 0 0 0.66250 1 0 0 1 1 0 0 1 0.65625 1 0 0 1 1 0 1 0 0.65000 1 0 0 1 1 0 1 1 0.64375 1 0 0 1 1 1 0 0 0.63750 1 0 0 1 1 1 0 1 0.63125 1 0 0 1 1 1 1 0 0.62500 1 0 0 1 1 1 1 1 0.61875 1 0 1 0 0 0 0 0 0.61250 1 0 1 0 0 0 0 1 0.60625 1 0 1 0 0 0 1 0 0.60000 1 0 1 0 0 0 1 1 0.59375 1 0 1 0 0 1 0 0 0.58750
mp2930 - 4-phase pwm controller with 8-bit dac code mp2930 rev. 0.9 www.monolithicpower.com 16 1/27/2010 mps proprietary information. unaut horized photocopy and duplication prohibited. ? 2010 mps. all rights reserved. table 2?vr11 id 8-bit continued id7 id6 id5 id4 id3 id2 id1 id0 voltage 1 0 1 0 0 1 0 1 0.58125 1 0 1 0 0 1 1 0 0.57500 1 0 1 0 0 1 1 1 0.56875 1 0 1 0 1 0 0 0 0.56250 1 0 1 0 1 0 0 1 0.55625 1 0 1 0 1 0 1 0 0.55000 1 0 1 0 1 0 1 1 0.54375 1 0 1 0 1 1 0 0 0.53750 1 0 1 0 1 1 0 1 0.53125 1 0 1 0 1 1 1 0 0.52500 1 0 1 0 1 1 1 1 0.51875 1 0 1 1 0 0 0 0 0.51250 1 0 1 1 0 0 0 1 0.50625 1 0 1 1 0 0 1 0 0.50000 1 1 1 1 1 1 1 0 off 1 1 1 1 1 1 1 1 off load-line regulation as the load current increases from zero, the output voltage will drop from the id table value by an amount proportional to load current to achieve the load-line. adding a droop can help to reduce the output voltage spike that result from fast load-current demand changes. as shown in figure 4, a current proportional to the average current of all active channels (i avg ) flows from fb through a load-line regulation resistor r fb . the voltage drop across r fb is proportional to the output current. it can be derived from equation (6): fb r avg i droop v = (6) the regulated output voltage is reduced by the droop voltage v droop . the output voltage is a function a load current, it?s derived by combining equation (6) with the appropriate sensing current expression defined by the current sense method employed in equation (7). ? ? ? ? ? ? ? ? ? ? = fb r isen r x r n out i ofs v ref v out v (7) where v ref is the reference voltage, v ofs is the programmed offset voltage, i out is the total output current of the converter, r isen is the sense resistor connected to the isen+ pin, and r fb is the feedback resistor, n is the active channel number, and r x is the dcr, or r sense depending on the sensing method. therefore the equivalent load-line impedance (droop impedance), can be derived from equation (8): isen r x r n fb r ll r = (8) output voltage offset programming the mp2930 can adjust the offset voltage accurately. when a resistor r ofs , is connected between ofs to vcc, the voltage across it is regulated to 1.6v. this causes a proportional current (i ofs ) to flow into ofs. if r ofs is connected to gnd, the voltage across it is regulated to 0.4v, and i ofs flows out of ofs. a resistor between dac and ref, r ref , is selected so that the product (i ofs x r ofs ) is equal to the desired offset voltage. these functions are shown in figure 5. figure 5?output voltage offset programming
mp2930 - 4-phase pwm controller with 8-bit dac code mp2930 rev. 0.9 www.monolithicpower.com 17 1/27/2010 mps proprietary information. unaut horized photocopy and duplication prohibited. ? 2010 mps. all rights reserved. once the desired output offset voltage has been determined, use equations (9) and (10) to set r ofs : for positive offset (connect r ofs to vcc): offset v ref r 1.6 ofs r = (9) for negative offset (connect r ofs to gnd): offset v ref r 0 ofs r = 4 . (10) the maximum negative offset for mp2930 is 150mv. dynamic id the microprocessors core voltage can be directed by making changes to the id inputs during regulator operation. the power management solution is required to monitor the dac inputs and respond to on-the- fly id changes in a controlled manner. in order to ensure the smooth transition of output voltage during id change, an id step change smoothing network, composed of r ref and c ref , as shown in figure 5, can be used. the selection of r ref is based on the desired offset voltage as detailed above in ?output voltage offset programming?. the selection of c ref is based on the time duration for 1-bit id change and the allowable delay time. assuming the microprocessor controls the id change at 1-bit every t vid , the relationship between the time constant of r ref and c ref network and t vid is given by equation (11): vid t ref r ref c = (11) enable and disable proper conditions must exist on the enable inputs and vcc prior to converter initialization. when the conditions are met, the controller begins soft-start. once the output voltage is within the proper window of operation, vr_rdy asserts logic high. while in shutdown mode, the pwm outputs are held in a high-impedance state, and the sd signal is pulled low to assure the mp86981 remain off. the following input conditions must be met before the mp2930 is released from shutdown mode. 1. the bias voltage applied at vcc must reach the internal power-on reset (por) rising threshold. hysteresis between the rising and falling thresholds assure that once enabled, the mp2930 will not inadvertently turn off unless the bias voltage drops substantially. 2. the mp2930 features an enable input (en_pwr) for power sequencing between the controller bias voltage and another voltage rail. the enable comparator holds the mp2930 in shutdown until the voltage at en_pwr rises above 0.875v. the enable comparator has about 130mv of hysteresis to prevent bounce. 3. the voltage on en_vtt must be higher than 0.875v to enable the controller. this pin is typically connected to the output of vtt vr. figure 6?power sequencing using threshold sensitive enable (en) function when all conditions are satisfied, mp2930 begins the soft-start and ramps the output voltage to 1.1v first. after remaining at 1.1v for some time, mp2930 reads the id code at id input pins. if the id code is valid, mp2930 will regulate the output to the final id setting. if the id code is off code, mp2930 will shutdown,
mp2930 - 4-phase pwm controller with 8-bit dac code mp2930 rev. 0.9 www.monolithicpower.com 18 1/27/2010 mps proprietary information. unaut horized photocopy and duplication prohibited. ? 2010 mps. all rights reserved. and cycling vcc, en_pwr or en_vtt is needed to restart. soft-start mp2930 based vr has 4 periods during soft- start as shown in figure 7. after vcc, en_vtt and en_pwr reach their por/enable thresholds, the controller will have fixed delay period t d1 . after this delay period, the vr will begin first soft-start ramp until the output voltage reaches 1.1v voltage. then, the controller will regulate the vr voltage at 1.1v for another fixed period t d3 . at the end of t d3 period, mp2930 reads the id signals. if the id code is valid, mp2930 will initiate the second soft-start ramp until the voltage reaches the id voltage minus offset voltage. the soft-start time is the sum of the 4 periods, as shown in equation (12): d4 t d3 t d2 t d1 t ss t + + + = (12) t d1 is a fixed delay with the typical value as 1.36ms. t d3 is determined by the fixed 85s plus the time to obtain valid id voltage. if the id is valid before the output reaches the 1.1v, the minimum time to validate the id input is 500ns. therefore the minimum t d3 is about 86s. during t d2 and t d4 , mp2930 digitally controls the dac voltage change at 6.25mv per step. the time for each step is determined by the frequency of the soft-start oscillator which is defined by the resistor r ss from ss pin to gnd. the second soft-start ramp time t d2 and t d4 can be calculated based on equations (13) and (14): (us) 6.25 ss r 1.1 d2 t 25 3 2 = (13) ( ) 25 3 2 ? = (14) for example, when id is set to 1.5v and the r ss is set at 100k ? , the first soft-start ramp time t d2 will be 469s and the second soft-start ramp time t d4 will be 171s. after the dac voltage reaches the final id setting, vr_rdy will be set to high with the fixed delay t d5 . the typical value for t d5 is 85s. figure 7?soft-start waveforms fault monitoring and protection the mp2930 actively monitors output voltage and current to detect fault conditions. one common power good indicator is provided for linking to external system monitors. the schematic in figure 8 outlines the interaction between the fault monitors and the vr_rdy signal. vr_rdy signal the vr_rdy pin is an open-drain logic output to indicate that the soft-start period has completed and the output voltage is within the regulated range. vr_rdy is pulled low during shutdown and releases high after a successful soft-start and a fixed delay t d5 . vr_rdy will be pulled low when an undervoltage or overvoltage condition is detected, or the controller is disabled by a reset from en_pwr, en_vtt, por, or id off-code. undervoltage detection the undervoltage threshold is set at 50% of the id code. when the output voltage at vsen is below the undervoltage threshold, vr_rdy is pulled low. overvoltage protection regardless of the vr being enabled or not, the mp2930 overvoltage protection (ovp) circuit will be active after its por. the ovp thresholds are different at different operation conditions. when vr is not enabled and during the soft- start intervals t d1 , t d2 and t d3 , the ovp threshold is 1.275v. once the controller detects valid id
mp2930 - 4-phase pwm controller with 8-bit dac code mp2930 rev. 0.9 www.monolithicpower.com 19 1/27/2010 mps proprietary information. unaut horized photocopy and duplication prohibited. ? 2010 mps. all rights reserved. input, the ovp trip point will be changed to dac + 175mv. two actions are taken by the mp2930 to protect the microprocessor load when an overvoltage condition occurs. figure 8?vr_rdy and protection circuitry at the beginning of an overvoltage event, all pwm outputs are commanded low instantly (>20ns). this causes the mp86981 to turn on the lower mosfets and pull the output voltage below a level to avoid damaging the load. when the vdiff voltage falls below the dac + 75mv, pwm signals enter a high-impedance state, and the sd pin is pulled low to turn off the mp86981. once an overvoltage condition is detected, normal pwm operation ceases until the mp2930 is reset. cycling the voltage on en_pwr, en_vtt or vcc below the por- falling threshold will reset the controller. cycling the id codes will not reset the controller. overcurrent protection mp2930 has two levels of overcurrent protection. each phase is protected from a sustained overcurrent condition by limiting its peak current, while the combined phase currents are protected on an instantaneous basis. in instantaneous protection mode, the mp2930 utilizes the sensed average current i avg to detect an overcurrent condition. the average current is continually compared with a constant 85a reference current, as shown in figure 8. once the average current exceeds the reference current, a comparator triggers the converter to shutdown. at the beginning of overcurrent shutdown, the controller places all pwm signals in a high- impedance state within 20ns to turn off the mp86981. the system remains in this state about 12ms. if the controller is still enabled at the end of this wait period, it will attempt a soft- start. if the fault remains, the hiccup mode will continue indefinitely until either controller is disabled or the fault is cleared. note that the energy delivered during hiccup mode is much less than during full-load operation, so there is no thermal hazard during this kind of operation. figure 9?overcurrent behavior in hiccup mode. fsw = 600khz for the individual channel overcurrent protection, the mp2930 continuously compares the sensed current signal of each channel with the 120a reference current. if one channel current exceeds the reference current, mp2930 will pull pwm signal of this channel to low for the rest of the switching cycle. this pwm signal can be turned on next cycle if the sensed channel current is less than the 120a reference current. the peak current limit of individual channel will not trigger the converter to shutdown.
mp2930 - 4-phase pwm controller with 8-bit dac code mp2930 rev. 0.9 www.monolithicpower.com 20 1/27/2010 mps proprietary information. unaut horized photocopy and duplication prohibited. ? 2010 mps. all rights reserved. thermal monitoring (vr_hot/vr_fan) there are two thermal signals to indicate the temperature status of the voltage regulator: vr_hot and vr_fan. both vr_fan and vr_hot pins are open-drain outputs, and external pull-up resistors are required. those signals are valid after the controller is enabled. the vr_fan signal indicates that the temperature of the voltage regulator is high and more cooling airflow is needed. the vr_hot signal can be used to inform the system that the temperature of the voltage regulator is too high and the cpu should reduce its power consumption. figure 10?block diagram of thermal monitoring function the diagram of thermal monitoring function block is shown in figure 10. one ntc resistor should be placed close to the power stage of the voltage regulator to sense the operational temperature, and one pull-up resistor is needed to form the voltage divider for the tm pin. as the temperature of the power stage increases, the resistance of the ntc will reduce, resulting in the reduced voltage at the tm pin. there are two comparators with hysteresis to compare the tm pin voltage to the fixed thresholds for vr_fan and vr_hot signals respectively. the vr_fan signal is set to high when the tm voltage is lower than 33% of vcc voltage, and is pulled to gnd when the tm voltage increases to above 39% of vcc voltage. the vr_fan signal is set to high when the tm voltage goes below 28% of vcc voltage, and is pulled to gnd when the tm voltage goes back to above 33% of vcc voltage. figure 11 shows the operation of those signals. figure 11?vr_hot and vr_fan signal vs. tm voltage current sense output the current from the idroop pin is the sensed average current. in typical application, the idroop pin is connected to the fb pin for the application where load line is required. when load line function is not needed, the idroop pin can be used to obtain the load current information: with one resistor from the idroop pin to gnd, the voltage at the idroop pin will be proportional to the load current in equation (15): load i isen r x r n idroop r idroop v = (15) where v idroop is the voltage at the idroop pin, r idroop is the resistor between the idroop pin and gnd, i load is the total output current of the converter, r isen is the sense resistor connected to the isen+ pin, n is the active channel number, and r x is the resistance of the current sense element, either the dcr of the inductor or r sense depending on the sensing method. r idroop should be chosen to ensure that the voltage at the idroop pin is less than 2v under the maximum load current. if the idroop pin is not used, tie it to gnd.
mp2930 - 4-phase pwm controller with 8-bit dac code mp2930 rev. 0.9 www.monolithicpower.com 21 1/27/2010 mps proprietary information. unaut horized photocopy and duplication prohibited. ? 2010 mps. all rights reserved. application information current sensing resistor the resistors connected to the isen+ pins determine the gains in the load-line regulation loop and the channel-current balance loop as well as setting the overcurrent trip point. select values for these resistors by using equation (16): n ocp i 6 10 85 x r isen r ? = (16) where r isen is the sense resistor connected to the isen+ pin, n is the active channel number, r x is the resistance of the current sense element, either the dcr of the inductor or r sense depending on the sensing method, and i ocp is the desired overcurrent trip point. typically, i ocp can be chosen to be 1.3x the maximum load current of the specific application. load-line regulation resistor the load-line regulation resistor is labeled r fb in figure 4. its value depends on the desired load-line requirement of the application. the desired load-line can be calculated by using equation (17): fl i droop v ll r = (17) where i fl is the full load current of the specific application, and v rdroop is the desired voltage droop under the full load condition. based on the desired load-line r ll , the load-line regulation resistor can be calculated by using equation (18): x r ll r isen nr fb r = (18) where n is the active channel number, r isen is the sense resistor connected to the isen+ pin, and r x is the resistance of the current sense, either the dcr of the inductor or r sense depending on the sensing method. compensation there are two distinct methods for achieving the compensation. compensating load-line regulated converter the load-line regulated converter behaves in a similar manner to a peak-current mode controller because the two poles at the output- filter l-c resonant frequency split with the introduction of current information into the control loop. the final location of these poles is determined by the system function, the gain of the current signal, and the value of the compensation components, r c and c c . treating the system as though it were a voltage-mode regulator by compensating the l- c poles and the esr zero of the voltage-mode. figure 12? compensation circuit for mp2930 with load-line regulation the feedback resistor, r fb , has already been chosen as outlined in ?load-line regulation resistor?. select a target bandwidth for the compensated system, f 0 . the target bandwidth must be large enough to assure adequate transient performance, but smaller than 1/3 of the per-channel switching frequency. the values of the compensation components depend on the relationships of f 0 to the l-c pole frequency and the esr zero frequency. the optional capacitor c 2 , (22pf to 150pf) is sometimes needed to bypass noise away from the pwm comparator (see figure 12).
mp2930 - 4-phase pwm controller with 8-bit dac code mp2930 rev. 0.9 www.monolithicpower.com 22 1/27/2010 mps proprietary information. unaut horized photocopy and duplication prohibited. ? 2010 mps. all rights reserved. compensation without load-line regulation the non load-line regulated converter is accurately modeled as a voltage-mode regulator with two poles at the l-c resonant frequency and a zero at the esr frequency. a type-iii controller, as shown in figure 13, provides the necessary compensation. figure 13?compensation circuit for mp2930 without load-line regulation the first step is to choose the desired bandwidth, f 0 , of the compensated system. choose a frequency high enough to assure adequate transient performance but not higher than 1/3 of the switching frequency. the type-iii compensator has an extra high-frequency pole, f hf . a good general rule is to choose f hf =10f 0 , but it can be higher if desired. choosing f hf to be lower than 10f 0 can cause problems with too much phase shift below the system bandwidth. designing the output filter the output inductors and the output capacitor bank together to form a low-pass filter responsible for smoothing the pulsating voltage at the phase nodes. the output filter also must provide the transient energy until the regulator can respond. in high-speed converters, the output capacitor bank is usually the most costly (and often the largest) part of the circuit. the critical load parameters in choosing the output capacitors are the maximum size of the load step, ? i; the load-current slew rate, di/dt; and the maximum allowable output voltage deviation under transient loading, ? v max . capacitors are characterized according to their capacitance, esr, and esl (equivalent series inductance). at the beginning of the load transient, the output capacitors supply all of the transient current. the output voltage will initially deviate by an amount approximated by the voltage drop across the esl. as the load current increases, the voltage drop across the esr increases linearly until the load current reaches its final value. the capacitors selected must have sufficiently low esl and esr so that the total output voltage deviation is less than the allowable maximum. neglecting the contribution of inductor current and regulator response, the output voltage initially deviates by an amount in equation (19): () () ? i esr dt di esl ? v + (19) the filter capacitor must have sufficiently low esl and esr so that ? v < ? v max . the esr of the bulk capacitors also creates the majority of the output voltage ripple. as the bulk capacitors sink and source the inductor ac ripple current, a voltage develops across the bulk-capacitor esr. thus, once the output capacitors are selected, the maximum allowable ripple voltage, v p-p(max) determines the lower limit on the inductance. () ( ) ( ) max p - p v in v s f out v out nv - in v esr l (20) since the capacitors are supplying a decreasing portion of the load current while the regulator recovers from the transient, the capacitor voltage becomes slightly depleted. the output inductors must be capable of assuming the entire load current before the output voltage decreases more than ? v max . this places an upper limit on inductance. selecting the switching frequency there are a number of variables to consider when choosing the switching frequency, as there are considerable effects on the upper- mosfet loss calculation. the lower limit is established by the requirement for fast transient response and small output voltage ripple as outlined in ?output filter design?. choose the
mp2930 - 4-phase pwm controller with 8-bit dac code mp2930 rev. 0.9 www.monolithicpower.com 23 1/27/2010 mps proprietary information. unaut horized photocopy and duplication prohibited. ? 2010 mps. all rights reserved. lowest switching frequency that allows the regulator to meet the transient-response requirements. selecting the input capacitor the input capacitors are responsible for sourcing the ac component of the input current flowing into the upper mosfets. their rms current capacity must be sufficient to handle the ac component of the current drawn by the upper mosfets which is related to duty cycle and the number of active phases. low capacitance, high-frequency ceramic capacitors are needed in addition to the bulk capacitors to suppress leading and falling edge voltage spikes. select low esl ceramic capacitors and place one as close as possible to each upper mosfet drain to minimize board parasitic impedances and maximize suppression. pc board layout for best performance of the mp2930, the following guidelines should be strictly followed: within the allotted implementation area, place the switching components first. switching component placement should take into account power dissipation. align the output inductors and mosfets such that space between the components is minimized while creating the phase plane. if possible, duplicate the same placement of these components for each phase. next, place the input and output capacitors. position one high frequency ceramic input capacitor next to each upper mosfet drain. place the input capacitors as close to the upper mosfet drains as dictated by the component size and dimensions. locate the output capacitors between the inductors and the load, while keeping them in close proximity to the microprocessor socket.
mp2930 - 4-phase pwm controller with 8-bit dac code notice: the information in this document is subject to change wi thout notice. users should warrant and guarantee that third party intellectual property rights are not infringed upon w hen integrating mps products into any application. mps will not assume any legal responsibility for any said applications. mp2930 rev. 0.9 www.monolithicpower.com 24 1/27/2010 mps proprietary information. unaut horized photocopy and duplication prohibited. ? 2010 mps. all rights reserved. package information qfn40 (6mm x 6mm) side view top view 5.90 6.10 5.90 6.10 0.80 1.00 0.00 0.05 0.20 ref pin 1 id marking note: 1) all dimensions are in millimeters. 2) exposed paddle size does not include mold flash. 3) lead coplanarity shall be 0.10 millimeter max. 4) drawing conforms to jedec mo-220, variation vjjd-5. 5) drawing is not to scale. pin 1 id option a 0.30x45 o typ. pin 1 id option b r0.25 typ. detail a pin 1 id index area 1 40 31 30 21 20 11 10 bottom view pin 1 id see detail a 4.50 4.80 4.50 4.80 0.50 bsc 0.35 0.45 0.18 0.30 recommended land pattern 0.70 0.50 0.90 4.70 5.90

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