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oki semiconductor pedl9041a-02 issue date: mar. 15, 2002 ml9041a-xxa/xxb preliminary dot matrix lcd controller driver 1/64 general description the ml9041a used in combination with an 8-bit or 4-bit microcontroller controls the operation of a character type dot matrix lcd. features ? easy interfacing with 8-bit or 4-bit microcontroller ? switchable between serial and parallel interfaces ? dot-matrix lcd controller/driver for a small (5 7 dots) or large (5 10 dots) font ? built-in circuit allowing automatic resetting at power-on ? built-in 17 common signal drivers and 100 segment signal drivers ? built-in character generation rom capable of generating 160 small characters (5 7 dots) or 32 large characters (5 10 dots) ? creation of character patterns by programming: up to 8 small character patterns (5 8 dots) or up to 4 large character patterns (5 11 dots) ? built-in rc oscillation circuit using external or internal resistors ? program-selectable duties: 1/9 duty (1 line: 5 7 dots + cursor + arbitrator), 1/12 duty (1 line: 5 10 dots + cursor + arbitrator), or 1/17 duty (2 lines: 5 7 dots + cursor + arbitrator) ? built-in bias dividing resistors to drive the lcd ? bi-directional transfer of segment outputs ? bi-directional transfer of common outputs ? 100-dot arbitrator display ? line display shifting ? built-in contrast control circuit ? built-in voltage multiplier circuit ? gold bump chip with dummy bumps on both sides of the chip: ml9041a-xxa cvwa without dummy bumps on both sides of the chip: ml9041a-xxb cvwa *xx indicates a character generator rom code number. *01a and 01b indicate general character generator rom code numbers.
pedl9041a-02 oki semiconductor ml9041a-xxa/xxb 2/64 block diagram v dd gnd osc 1 osc r osc 2 rs 1 rs 0 r/ w e c s s/ p sht si so db 0 to db 3 4 db 4 to db 7 4 t 1 t 2 t 3 v 1 v 2 v 3b v 3 a v 4 v 5 v 5in timing generator 8 i/o buffer 8 instruction decoder (id) parallel- serial converter 7 8 8 8 data register (dr) 5 com 1 seg 1 com 17 test circuit lcd bias voltage dividing circuit 5 8 busy flag (bf) expansion instruction register (er) voltage multiplier circuit address counter (adc) expansion instruction decoder (ed) character generator ram (cg ram) 8 8 display data ram (dd ram) arbitrator ram (ab ram) cursor blink controller 5 5 csr 17-bit shift register common signal driver 100-bit shift register 100-bit latch segment signal - driver seg 100 ssr be v cc v c v in character generator rom (cg rom) instruction register (ir) contrast control circuit
pedl9041a-02 oki semiconductor ml9041a-xxa/xxb 3/64 i/o circuits v dd p n applied to pins ssr, csr, s/ p , and be v dd p n a pplied to pins t 1 , t 2 , and t 3 v dd p n v dd a pplied to pins r/ w , rs 1 , and rs 0 a t serial i/f a t parallel i/f a t serial i/f a t parallel i/f a pplied to pin si a pplied to pin e a pplied to pin sht a pplied to pin cs : ?1? ( cs = ?0?) : ?0? ( cs = ?1?) : ?0? a t serial i/f a t parallel i/f : ?1? ( cs = ?1?) : ?0? ( cs = ?0?) : ?1? : ?0? : ?1? a t serial i/f a t parallel i/f : ?0? : ?1? v dd p v dd p n v dd p n a pplied to pins db 0 to db 7 output enable signal v dd pp v dd n a pplied to pin so output enable signal
pedl9041a-02 oki semiconductor ml9041a-xxa/xxb 4/64 pin descriptions symbol description r/ w the input pin with a pull-up resistor to select read (?h?) or write (?l?) in the parallel i/f mode. this pin should be open in the serial l/f mode. rs 0 , rs 1 the input pins with a pull-up resistor to select a register in the parallel l/f mode. this pin should be open in the serial i/f mode. e the input pin for data input/output between the cpu and the ml9041a and for activating instructions in the parallel l/f mode. this pin should be open in the serial l/f mode. db 0 to db 3 the input/output pins to transfer data of lower-order 4 bits between the cpu and the ml9041a in the parallel l/f mode. the pins are not used for the 4-bit interface and serial interface. each pin is equipped with a pull-up resistor, so this pin should be open when not used. db 4 to db 7 the input/output pins to transfer data of upper 4 bits between the cpu and the ml9041a in the parallel l/f mode. the pins are not used for the serial interface. each pin is equipped with a pull-up resistor, so this pin should be open in the serial i/f mode when not used. osc 1 osc 2 osc r the clock oscillation pins required for lcd drive signals and the operation of the ml9041a by instructions sent from the cpu. to input external clock, the osc 1 pin should be used. the osc r and the osc 2 pins should be open. to start oscillation with an external resistor, the resistor should be connected between the osc 1 and osc 2 pins. the osc r pin should be open. to start oscillation with an internal resistor, the osc 2 and osc r pins should be short-circuited outside the ml9041a. the osc 1 pin should be open. com 1 to com 17 the lcd common signal output pins. for 1/9 duty, non-selectable voltage waveforms are output via com 10 to com 17 . for 1/12 duty, non-selectable voltage waveforms are output via com 13 to com 17 . seg 1 to seg 100 the lcd segment signal output pins. rs 1 rs 0 name of register h h data register h l instruction register l l expansion instruction register
pedl9041a-02 oki semiconductor ml9041a-xxa/xxb 5/64 symbol description csr the input pin to select the transfer direction of the common signal output data. at 1/n duty, data is transferred from com1 to comn when ?l? is applied to this pin and transferred from comn to com1 when ?h? is applied to this pin. ssr the input pin to select the transfer direction of the segment signal output data. ?l?: data transfer from seg 1 to seg 100 ?h?: data transfer from seg 100 to seg 1 v 1 , v 2 , v 3a , v 3b , v 4 the pins to output bias voltages to the lcd. for 1/4 bias : the v 2 and v 3b pins are shorted. for 1/5 bias : the v 3a and v 3b pins are shorted. be the input pin to enable or disable the voltage multiplier circuit. "l" disables the voltage multiplier circuit. "h" enables the voltage multiplier circuit. the voltage multiplier circuit doubles the input voltage between v dd and v in and the multiplied voltage referenced to v dd is output to the v 5in pin. the voltage multiplier circuit can be used only when generating a level lower than gnd. v in the pin to input voltage to the voltage multiplier. v 5 , v 5in the pins to supply the lcd drive voltage. the lcd drive voltage is supplied to the v 5 pin when the voltage multiplier is not used (be = ?0?) and the internal contrast adjusting circuit is also not used. at this time, the v 5in pin should be open. the lcd drive voltage is supplied to the v 5in pin when the voltage multiplier is not used (be = ?0?) but the internal contrast adjusting circuit is used. at this time, the v 5 pin should be open. when the voltage multiplier is used (be = ?1?), the v 5 pin should be open (the multiplied voltage is output to the v 5in pin). in this case, the internal contrast adjusting circuit must be used. capacitors for the voltage multiplier should be connected between the v dd pin and the v 5in pin. v c the pin to connect the positive pin of the capacitor for the voltage multiplier. leave the pin open when the voltage multiplier circuit is not used. v cc the pin to connect the negative pin of the capacitor used for the voltage multiplier. leave the pin open when the voltage multiplier circuit is not used.
pedl9041a-02 oki semiconductor ml9041a-xxa/xxb 6/64 symbol description t 1 , t 2 , t 3 the input pins for test circuits (normally open). each of these pins is equipped with a pull-down resistor, so this pin should be left open. v dd the power supply pin. gnd the ground level input pin. s/ p the input pin to select the serial or parallel interface. ?l? selects the parallel interface. ?h? selects the serial interface. cs the pin to enable this ic in the serial l/f mode. ?l? enables this ic. ?h? disables this ic. this pin should be open in the parallel l/f mode. sht the pin to input shift clock in the serial l/f mode. data inputting to the si pin is carried out synchronizing with the rising edge of this clock signal. data outputting from the so pin is carried out synchronizing with the falling edge of this clock signal. this pin should be open in the parallel l/f mode. sl the pin to input data in the serial l/f mode. data inputting to this pin is carried out synchronizing with the rising edge of the sht signal. this pin should be open in the parallel l/f mode. so the pin to output data in the serial l/f mode. data inputting to this pin is carried out synchronizing with the falling edge of the sht signal. this pin should be open in the parallel l/f mode. dummy nc pin. leave this pin open.
pedl9041a-02 oki semiconductor ml9041a-xxa/xxb 7/64 absolute maximum ratings (gnd = 0 v) parameter symbol condition rating unit applicable pins supply voltage v dd ta = 25c ?0.3 to +6.5 v v dd ?gnd lcd driving voltage v 1 , v 2 , v 3 , v 4 , v 5 ta = 25c v dd ?7.5 to v dd +0.3 v v 1 , v 4 , v 5 , v 5in , v 2 , v 3a , v 3b input voltage v i ta = 25c ?0.3 to v dd +0.3 v r/ w , e, sht , csr, s/ p , ssr, sl, rs 0 , rs 1 , be, cs , t 1 to t 3 , db 0 to db 7 , v in storage temperature t stg ? ?55 to +150 c ? recommended operating conditions (gnd = 0 v) parameter symbol condition range unit applicable pins supply voltage v dd ? 2.7 to 5.5 v v dd ?gnd lcd driving voltage v dd ?v 5 (see note) ? 3.3 to 7.0 v v dd ?v 5 (v 5in ) voltage multipler operating voltage v mul be = ?1? 2.7 to 3.5 v v dd ?v in operating temperature t op ? ?40 to +85 c ? note: this voltage should be applied across v dd and v 5 . the following voltages are output to the v 1 , v 2 , v 3a (v 3b ) and v 4 pins: ? 1/4 bias v 1 = {v dd ? (v dd ? v 5 )/4} 0.15 v v 2 = v 3b = {v dd ? (v dd ? v 5 )/2} 0.15 v v 4 = {v dd ? 3 (v dd ? v 5 )/4 } 0.15 v ? 1/5 bias v 1 = {v dd ? (v dd ? v 5 )/5} 0.15 v v 2 = {v dd ? 2 (v dd ? v 5 )/5} 0.15 v v 3a = v 3b = {v dd ? 3 (v dd ? v 5 )/5} 0.15 v v 4 = {v dd ? 4 (v dd ? v 5 )/5} 0.15 v the voltages at the v 1 , v 2 , v 3a (v 3b ), v 4 and v 5 pins should satisfy v dd > v 1 > v 2 > v 3a (v 3b ) > v 4 > v 5 . (higher lower) * if the chip is attached on a substrate using cog technology, the chip tends to be susceptible to electrical characteristics of the chip due to trace resistance on the glass substrate. it is recommended to use the chip by confirming that it operates on the glass substrate properly. trace resistance, especially, v dd and v ss trace resistance, between the chip on the lcd panel and the flexible cable should be designed as low as possible. trace resistance that cannot be very well decreased, larger size of the lcd panel, or greater trace capacitance between the microcontroller and the ml9041a device can cause device malfunction. in order to avoid the device malfunction, power noise should be reduced by serial interfacing of the microcontroller and the ml9041a device. * do not apply short-circuiting across output pins and across an output pin and an input/output pin or the power supply pin in the output mode.
pedl9041a-02 oki semiconductor ml9041a-xxa/xxb 8/64 electrical characteristics dc characteristics (gnd = 0 v, v dd = 2.7 to 5.5 v, ta = ?40 to +85c) parameter symbol condition min. typ. max. unit applicable pin ?h? input voltage v ih 0.8v dd ?v dd ?l? input voltage v il ? 0 ? 0.2v dd v r/ w , rs 0 , rs 1 , e, db 0 to db 7 , sht , s/ p , sl, cs , osc 1 , ssr, csr, be ?h? output voltage 1 v oh1 i oh = ?0.1 ma 0.75v dd ?? ?l? output voltage 1 v ol1 i ol = +0.1 ma ? ? 0.2v dd vdb 0 to db 7 , so ?h? output voltage 2 v oh2 i oh = ?13 a0.9v dd ?? ?l? output voltage 2 v ol2 i ol = +13 a??0.1v dd vosc 2 v ch l och = ?4 av dd ?0.3 ? v dd v cmh l ocmh = 4 av 1 ?0.3 ? v 1 +0.3 v cml l ocml = 4 av 4 ?0.3 ? v 4 +0.3 com voltage drop v cl l ocl = +4 a v dd ?v 5 = 5 v note 1 v 5 ?v 5 +0.3 v com 1 to com 17 v sh l osh = ?4 av dd ?0.3 ? v dd v smh l osmh = 4 av 2 ?0.3 ? v 2 +0.3 v sml l osml = 4 av 3 ?0.3 ? v 3 +0.3 seg voltage drop v sl l osl = +4 a v dd ?v 5 = 5 v note 1 v 5 ?v 5 +0.3 v seg 1 to seg 100 input leakage current | iil | v dd = 5 v, v i = 5 v or 0 v ? ? 1.0 a e, ssr, csr, be, sht , s/ p , cs , sl v dd = 5 v, v i = gnd 10 25 61 input current 1 | ii1 | v dd = 5 v, v i = v dd , excluding current flowing through the pull-up resistor and the output driving mos ??2.0 a r/ w , rs 0 , rs 1 , db 0 to db 7 , so v dd = 5 v, v i = v dd 15 45 105 input current 2 | ii2 | v dd = 5 v, v i = gnd excluding current flowing through the pull-down resistor ??2.0 at 1 , t 2 , t 3 supply current l dd v dd = 5 v note 2 ? ? 1.2 ma v dd ?gnd lcd bias resistor r lb 2.5 4.0 6.0 k ? v dd , v 1 , v 2 , v 3a , v 3b , v 4 , v 5 oscillation frequency of external resistor rf f osc1 rf = 180 k ? 2% note 3 175 270 400 khz osc 1 , osc 2 oscillation frequency of internal resistor rf f osc2 osc 1 : open note 4 osc 2 and osc r : short- circuited 140 270 480 khz osc 1 , osc 2 , osc r clock input frequency f in osc 2 , osc r : open input from osc 1 125 ? 480 khz input clock duty f duty note 5 45 50 55 % input clock rise time f rf note 6 ? ? 0.2 s external clock input clock fall time f ff note 6 ? ? 0.2 s osc 1
pedl9041a-02 oki semiconductor ml9041a-xxa/xxb 9/64 (gnd = 0 v, v dd = 2.7 to 5.5 v, ta = ?40 to +85c) parameter symbol condition min. typ. max. unit applicable pins voltage multiplier input voltage v mul note 7 2.7 ? 3.5 v v dd ?v in 1/5 bias 4.1 ? (v dd ?v in ) 2 voltage multiplier output voltage v 5out v dd = 2.7 v, v in = 0 v f = 125 khz a capacitor for the voltage multiplier = 1 to 4.7 f no load be = ?h? 1/4 bias 3.9 ? (v dd ?v in ) 2 vv dd ?v 5in v dd = 5 v, v 5in = ?2 v, 1/5 bias, contrast data: 1f, no load 6.6 ? ? v dd = 5 v, v 5in = ?2 v, 1/4 bias, contrast data: 1f, no load 6.6 ? ? v dd = 4.1 v, v 5in = 0 v, 1/5 bias, contrast data: 1f, no load 3.8 ? ? v lcd max v dd = 3.9 v, v 5in = 0 v, 1/4 bias, contrast data: 1f, no load 3.6 ? ? v v dd = 5 v, v 5in = ?2 v, 1/5 bias, contrast data: 00, no load 4.0 ? 4.6 v dd = 5 v, v 5in = ?2 v, 1/4 bias, contrast data: 00, no load 3.6 ? 4.2 v dd = 4.1 v, v 5in = 0 v, 1/5 bias, contrast data: 00, no load 2.2 ? 2.8 maximum and minimum lcd drive voltages when internal variable resistors are used. note 8 v lcd min v dd = 3.9 v, v 5in = 0 v, 1/4 bias, contrast data: 00, no load 1.9 ? 2.5 v v dd ?v 5 v lcd1 1/5 bias 3.3 ? 7.0 bias voltage for driving lcd v lcd2 v dd ?v 5 note 9 1/4 bias 3.3 ? 7.0 vv 5 note 1: applied to the voltage drop occurring between any of the v dd , v 1 , v 4 and v 5 pins and any of the common pins (com 1 to com 17 ) when the current of 4 a flows in or flows out at one common pin. also applied to the voltage drop occurring between any of the v dd , v 2 , v 3a (v 3b ) and v 5 pins and any of the segment pins (seg 1 to seg 100 ) when the current of 4 a flows in or flows out at one common pin. the current of 4 a flows out when the output level is v dd or flows in when the output level is v 5 . note 2: applied to the current flowing into the v dd pin when the external clock (f osc2 = f in = 270 khz) is fed to the internal r f oscillation or osc 1 under the following conditions: v dd = 5 v gnd = v 5 = 0 v, v 1 , v 2 , v 3a (v 3b ) and v 4 : open e, ssr, csr, and be: ?l? (fixed) other input pins: ?l? or ?h? (fixed) other output pins: no load
pedl9041a-02 oki semiconductor ml9041a-xxa/xxb 10/64 note 3: note 4: osc 1 osc r osc 2 the wire between osc 2 and osc r should be as short as possible. keep osc 1 open. osc 1 osc r osc 2 the wire between osc 1 and r f and the wire between osc 2 and r f should be as short as possible. keep osc r open. r f = 180 k ? 2% note 5: t hw t lw v dd 2 f in waveform v dd 2 v dd 2 a pplied to the pulses entering from the osc 1 pin f duty = t hw /(t hw + t lw ) 100 (%) note 6: 0.8v dd a pplied to the pulses entering from the osc 1 pin 0.8v dd 0.2v dd 0.2v dd t rf t ff note 7: the maximum value of the voltage multiplier input voltage should be set at 3.5 v, and the minimum value of the voltage multiplier input voltage should be set so that the voltage multiplier output voltage meets the specification for the bias voltage for driving lcd after contrast adjustment. note 8: if using the built-in contrast control circuit, control the circuit so that the voltage of v dd -v 5 is the minimum value of the bias voltage for driving lcd or higher. note 9: for 1/4 bias, v 2 and v 3b pins are short-circuited. v 3a pin is open. for 1/5 bias, v 3a and v 3b pins are short-circuited. v 2 pin is open.
pedl9041a-02 oki semiconductor ml9041a-xxa/xxb 11/64 switching characteristics (the following ratings are subject to change after es evaluation.) ? parallel interface mode the timing for the input from the cpu (see 1) and the timing for the output to the cpu (see 2) are as shown below: 1) write mode (timing for input from the cpu) (v dd = 2.7 to 5.5 v, ta = ?40 to +85c) parameter symbol min. typ. max. unit r/ w , rs 0 , rs 1 setup time t b 40 ? ? ns e pulse width t w 450 ? ? ns r/ w , rs 0 , rs 1 hold time t a 10 ? ? ns e rise time t r ? ? 25 ns e fall time t f ? ? 25 ns e pulse width t l 430 ? ? ns e cycle time t c 1000 ? ? ns db 0 to db 7 input data hold time t i 195 ? ? ns db 0 to db 7 input data setup time t h 10 ? ? ns rs 1 , rs 0 v ih v il v ih v il v il v il v il v il v il v ih v ih v ih v il v ih v il r/ w e db 0 to db 7 t l t b t w t r t f t a t h t i input data t c
pedl9041a-02 oki semiconductor ml9041a-xxa/xxb 12/64 2) read mode (timing for output to the cpu) (v dd = 2.7 to 5.5 v, ta = ?40 to +85c) parameter symbol min. typ. max. unit r/ w , rs 1 , rs 0 setup time t b 40 ? ? ns e pulse width t w 450 ? ? ns r/ w , rs 1 , rs 0 hold time t a 10 ? ? ns e rise time t r ? ? 25 ns e fall time t f ? ? 25 ns e pulse width t l 430 ? ? ns e cycle time t c 1000 ? ? ns db 0 to db 7 output data delay time t d ? ? 350 ns db 0 to db 7 output data hold time t o 20 ? ? ns note: a load capacitance of each of db 0 to db 7 must be 50 pf or less. rs 1 , rs 0 v ih v il v ih v il v ih v ih v il v il v il v ih v ih v oh v ol v oh v ol r/ w e db 0 to db 7 t l t b t w t r t f t a t o t d output data t c
pedl9041a-02 oki semiconductor ml9041a-xxa/xxb 13/64 ? serial interface mode (v dd = 2.7 to 5.5 v, ta = ?40 to +85c) parameter symbol min. typ. max. unit sht cycle time t scy 500 ? ? ns cs setup time t csu 100 ? ? ns cs hold time t ch 100 ? ? ns cs ?h? pulse width t cswh 200 ? ? ns sht setup time t ssu 60 ? ? ns sht hold time t sh 200 ? ? ns sht ?h? pulse width t swh 200 ? ? ns sht ?l? pulse width t swl 200 ? ? ns sht rise time t sr ??50ns sht fall time t sf ??50ns sl setup time t disu 100 ? ? ns sl hold time t dih 100 ? ? ns data output delay time t dod ? ? 160 ns data output hold time t cdh 0??ns v ih v il v ih v il si v il t scy t dod t dod v ol v oh v oh t cdh c s so sh t t csu t ssu t swl t sr t swh t sf t sh t ch v ih v il v ih v ih v ih v il t disu t dih v ih t cswh v ih v il v ih v ih
pedl9041a-02 oki semiconductor ml9041a-xxa/xxb 14/64 functional description instruction register (ir), data register (dr), and expansion instruction register (er) these registers are selected by setting the level of the register selection input pins rs 0 and rs 1 . the dr is selected when both rs 0 and rs 1 are ?h?. the ir is selected when rs 0 is ?l? and rs 1 is ?h?. the er is selected when both rs 0 and rs 1 are ?l?. (when rs 0 is ?h? and rs 1 is ?l?, the ml9041a is not selected.) the ir stores an instruction code and sets the address code of the display data ram (ddram) or the character generator ram (cgram). the microcontroller (cpu) can write to the ir but cannot read from the ir. the er stores a contrast adjusting code and sets the address code of the arbitrator ram (abram). the cpu can write to or read from the er. the dr stores data to be written in the ddram, abram and cgram and also stores data read from the ddram, abram and cgram. the data written in the dr by the cpu is automatically written in the ddram, abram or cgram. when an address code is written in the ir or er, the data of the specified address is automatically transferred from the ddram, abram or cgram to the dr. the data of the ddram, abram and cgram can be checked by allowing the cpu to read the data stored in the dr. after the cpu writes data in the dr, the data of the next address in the ddram, abram or cgram is selected to be ready for the next writing by the cpu. similarly, after the cpu reads the data in the dr, the data of the next address in the ddram, abram or cgram is set in the dr to be ready for the next reading by the cpu. writing in or reading from these 3 registers is controlled by changing the status of the r/ w (read/write) pin. table 1 r/ w w w w pin status and register operation r/ w rs 0 rs 1 operation l l h writing in the ir h l h reading the busy flag (bf) and the address counter (adc) l h h writing in the dr h h h reading from the dr l l l writing in the er h l l reading the contrast code l h l disabled (not in a busy state, not performing the writes) hh l disabled (not in a busy state, not performing the reads. note data read by the cpu is undefined since the data bus is high impedance.) busy flag (bf) the status ?1? of the busy flag (bf) indicates that the ml9041a is carrying out internal operation. when the bf is ?1?, any new instruction is ignored. when r/ w = ?h?, rs 0 = ?l? and rs 1 = ?h?, the data in the bf is output to the db 7 . new instructions should be input when the bf is ?0?. when the bf is ?1?, the output code of the address counter (adc) is undefined.
pedl9041a-02 oki semiconductor ml9041a-xxa/xxb 15/64 address counter (adc) the address counter provides a read/write address for the ddram, abram or cgram and also provides a cursor display address. when an instruction code specifying ddram, abram or cgram address setting is input to the pre-defined register, the register selects the specified ddram, abram or cgram and transfers the address code to the adc. the address data in the adc is automatically incremented (or decremented) by 1 after the display data is written in or read from the ddram, abram or cgram. the data in the adc is output to db 0 to db 6 when r/ w = ?h?, rs 0 = ?l?, rs 1 = ?h? and bf = ?0?. timing generator the timing generator generates timing signals for the internal operation of the ml9041a activated by the instruction sent from the cpu or for the operation of the internal circuits of the ml9041a such as ddram, abram, cgram and cgrom. timing signals are generated so that the internal operation carried out for lcd displaying will not be interfered by the internal operation initiated by accessing from the cpu. for example, when the cpu writes data in the ddram, the display of the lcd not corresponding to the written data is not affected.
pedl9041a-02 oki semiconductor ml9041a-xxa/xxb 16/64 display data ram (ddram) this ram stores the 8-bit character codes (see table 2). the ddram addresses correspond to the display positions (digits) of the lcd as shown below. the ddram addresses (to be set in the adc) are represented in hexadecimal. msb lsb db 6 db 5 db 4 db 3 db 2 db 1 db 0 hexadecimal hexadecimal 2 0 a dc 0 1 0 0 1 0 1 a dc (example) representation of ddram address = 12 1) relationship between ddram addresses and display positions (1-line display mode) 00 01 02 03 04 12 13 digit 1 2 3 4 5 19 20 left end right end display position dd ram address (hexadecimal) in the 1-line display mode, the ml9041a can display up to 20 characters from digit 1 to digit 20. while the ddram has addresses ?00? to ?4f? for up to 80 character codes, the area not used for display can be used as a ram area for general data. when the display is shifted by instruction, the relationship between the lcd display and the ddram address changes as shown below: 4f 00 01 02 11 12 digit 1 234 1920 (display shifted to the right) 01 02 03 04 13 14 digit 1 234 05 51920 (display shifted to the left)
pedl9041a-02 oki semiconductor ml9041a-xxa/xxb 17/64 2) relationship between ddram addresses and display positions (2-line display mode) in the 2-line mode, the ml9041a can display up to 40 characters (20 characters per line) from digit 1 to digit 20. 00 01 02 03 04 digit 1 2345 12 13 19 20 40 41 42 43 44 52 53 line 1 line 2 display position dd ram address (hexadecimal) note: the ddram address at digit 20 in the first line is not consecutive to the ddram address at digit 1 in the second line. when the display is shifted by instruction, the relationship between the lcd display and the ddram address changes as shown below: 27 00 01 02 digit 1 234 11 12 19 20 67 40 41 42 51 52 line 1 line 2 01 02 03 04 digit 1 234 13 14 19 20 41 42 43 44 03 5 43 05 5 45 53 54 line 1 line 2 (display shifted to the right) (display shifted to the left)
pedl9041a-02 oki semiconductor ml9041a-xxa/xxb 18/64 character generator rom (cgrom) the cgrom generates small character patterns (5 7 dots, 160 patterns) or large character patterns (5 10 dots, 32 patterns) from the 8-bit character code signals in the ddram. when the 8-bit character code corresponding to a character pattern in the cgrom is written in the ddram, the character pattern is displayed in the display position specified by the ddram address. character codes 20 to 7f and a0 to ff are contained in the character code area in the cg rom. character codes 20 to 7f and a0 to df are contained in the character code area for the 5 7-dot character patterns. character codes e0 to ff are contained in the rom area for 5 10-dot character patterns. the general character generator rom codes are 01a/01b. the relationship between character codes and general purpose character patterns are indicated in table 2.
pedl9041a-02 oki semiconductor ml9041a-xxa/xxb 19/64 character generator ram (cgram) the cgram is used to generate user-specific character patterns that are not in the cgrom. cgram (64 bytes = 512 bits) can store up to 8 small character patterns (5 8 dots) or up to 4 large character patterns (5 11 dots). when displaying a character pattern stored in the cgram, write an 8-bit character code (00 to 07 or 08 to 0f; hex.) assigned in table 2 to the ddram. this enables outputting the character pattern to the lcd display position corresponding to the ddram address. the cursor or blink is also displayed even when a cgram or abram address is set in the adc. therefore, the cursor or blink display should be inhibited while the adc is holding a cgram or abram address. the following describes how character patterns are written in and read from the cgram. 1) small character patterns (5 8 dots) (see table 3-1.) (1) a method of writing character patterns to the cgram from the cpu the three cgram address bit weights 0 to 2 select one of the lines constituting a character pattern. first, set the mode to increment or decrement from the cpu, and then input the cgram address. write each line of the character pattern in the cgram through db 0 to db 7 . the data lines db 0 to db 7 correspond to the cgram data bit weights 0 to 7, respectively (see table 3- 1). input data ?1? represents the on status of an lcd dot and ?0? represents the off status. since the adc is automatically incremented or decremented by 1 after the data is written to the cgram, it is not necessary to set the cgram address again. the bottom line of a character pattern (the cgram address bit weights 0 to 2 are all ?1?, which means 7 in hexadecimal) is the cursor line. the on/off pattern of this line is ored with the cursor pattern for displaying on the lcd. therefore, the pattern data for the cursor position should be all zeros to display the cursor. whereas the data given by the cgram data bit weights 0 to 4 is output to the lcd as display data, the data given by the cgram data bit weights 5 to 7 is not. therefore, the cgram data bit weights 5 to 7 can be used as a ram area. (2) a method of displaying cgram character patterns on the lcd the cgram is selected when the higher-order 4 bits of a character code are all zeros. since bit weight 3 of a character code is not used, the character pattern ?0? in table 3-1 can be selected using the character code ?00? or ?08? in hexadecimal. when the 8-bit character code corresponding to a character pattern in the cgram is written to the ddram, the character pattern is displayed in the display position specified by the ddram address. (the ddram data bit weights 0 to 2 correspond to the cgram address bit weights 3 to 5, respectively.)
pedl9041a-02 oki semiconductor ml9041a-xxa/xxb 20/64 2) large character patterns (5 11 dots) (see table 3-2.) (1) a method of writing character patterns to the cgram from the cpu the four cgram address bit weights 0 to 3 select one of the lines constituting a character pattern. first, set the mode to increment or decrement from the cpu, and then input the cgram address. write each line of the character pattern code in the cgram through db 0 to db 7 . the data lines db 0 to db 7 correspond to the cgram data bit weights 0 to 7, respectively (see table 3- 2). input data ?1? represents the on status of an lcd dot and ?0? represents the off status. since the adc is automatically incremented or decremented by 1 after the data is written to the cgram, it is not necessary to set the cgram address again. the bottom line of a character pattern (the cgram address bit weights 0 to 3 are all ?1?, which means a in hexadecimal) is a cursor line. the on/off pattern of this line is ored with the cursor pattern for displaying on the lcd. therefore, the pattern data for the cursor position should be all zeros to display the cursor. whereas cgram data bit weights 0 to 4 are output as display data to the lcd when cgram address bit weights 0 to 3 are ?0? to ?a? in hexadecimal, the data given by the cgram data bit weights 5 to 7 or the cgram addresses b to f in hexadecimal is not. these bits can be written and read as a ram area. (2) a method of displaying cgram character patterns on the lcd the cgram is selected when the higher-order 4 bits of a character code are all zeros. since bit weights 0 and 3 of a character code are not used, the character pattern ?g? in table 3-2 can be selected with a character code ?02?, ?03?, ?0a? or ?0b? in hexadecimal. when the 8-bit character code corresponding to a character pattern in the cgram is written to the ddram, the character pattern is displayed in the display position specified by the ddram address. (the ddram data bit weights 1 and 2 correspond to the cgram address bit weights 4 and 5, respectively.)
pedl9041a-02 oki semiconductor ml9041a-xxa/xxb 21/64 arbitrator ram (abram) the arbitrator ram (abram) stores arbitrator display data. 100 dots can be displayed in both 1-line and 2-line display modes. the arbitrator ram has the addresses (hexadecimal) from ?00? to ?1f? and the valid display address area is from 00 to 19 (0h to 13h). the area of 20 to 31 (14h to 1fh) not used for display can be used as a data ram area for general data. even if the display is shifted by instruction, the arbitrator display is not shifted. a capacity of 8 bits by 32 addresses (= 256 bits) is available for data write. first set the mode to increment or decrement from the cpu, and then input the abram address. write display-on data in the abram through db 0 to db 7 . db 0 to db 7 correspond to the abram data bit weights 0 to 7 respectively. input data ?1? represents the on status of an lcd dot and ?0? represents the off status. since adc is automatically incremented or decremented by 1 after the data is written to the abram, it is not necessary to set the abram address again. whereas abram data bit weights 0 to 4 are output as display data to the lcd, the abram data bit weights 5 to 7 are not. these bits can be used as a ram area. the cursor or blink is also displayed even when a cgram or abram address is set in the adc. therefore, the cursor or blink display should be inhibited while the adc is holding a cgram or abram address. msb lsb db 6 db 5 db 4 db 3 db 2 db 1 db 0 hexadecimal hexadecimal a dc the arbitrator ram can store a maximum of 100 dots of the arbitrator display-on data in units of 5 dots. the relationship with the lcd display positions is shown below. * * e4 e3 e2 e1 e0 db 6 * db 7 db 5 db 4 db 3 db 2 db 1 db 0 * don?t care display - on data e4 e0 5xsn+1 5xsn+5 configuration of input display data input data relationship between display-on data and segment pins sn = abram address ( 0 to 19 )
pedl9041a-02 oki semiconductor ml9041a-xxa/xxb 22/64 table 2 relationship between character codes and character patterns of the ml9041a- 01a/01b (general character codes) the character code area in the cg rom: character codes 20h to 7fh, a0h to ffh. 5 7-dot rom area: 20h to 7fh, a0h to dfh 5 10-dot rom area: e0h to ffh the cg ram area : character codes 00h to 0fh 00h: 20h: 28h: ( 30h: 0 38h: 8 21h: ! 29h: ) 31h: 1 39h: 9 22h: " 2ah: * 32h: 2 3ah: : 23h: # 2bh: + 33h: 3 3bh: ; 24h: $ 2ch: , 34h: 4 3ch: < 25h: % 2dh: - 35h: 5 3dh: = 26h: & 2eh: . 36h: 6 3eh: > 27h: ' 2fh: / 37h: 7 3fh: ? 40h: @ 48h: h 50h: p 41h: a 49h: i 51h: q 42h: b 4ah: j 52h: r 43h: c 4bh: k 53h: s 44h: d 4ch: l 54h: t 45h: e 4dh: m 55h: u 46h: f 4eh: n 56h: v 47h: g 4fh: o 57h: w 01h: 02h: 03h: 04h: 05h: 06h: 07h: 08h: 09h: 0ah: 0bh: 0ch: 0dh: 0eh: 0fh: cg ram(1) cg ram(2) cg ram(3) cg ram(4) cg ram(5) cg ram(6) cg ram(7) cg ram(8) cg ram(1) cg ram(2) cg ram(3) cg ram(4) cg ram(5) cg ram(6) cg ram(7) cg ram(8)
pedl9041a-02 oki semiconductor ml9041a-xxa/xxb 23/64
pedl9041a-02 oki semiconductor ml9041a-xxa/xxb 24/64
pedl9041a-02 oki semiconductor ml9041a-xxa/xxb 25/64 table 3-1 relationship between cgram address bits, cgram data bits (character pattern) and ddram data bits (character code) in 5 7 dot character mode. (examples) cg ram data ( character p attern ) ( character code ) dd ram data 01110 10001 10001 10001 10001 10001 01110 00000 76543210 76543210 lsb msb lsb msb lsb 0000 000 10001 10010 10100 11000 10100 10010 10001 00000 0000 001 01110 00100 00100 00100 00100 00100 01110 00000 0000 111 cg ram address 543210 msb 000000 001 010 011 100 101 110 111 001000 001 010 011 100 101 110 111 111000 001 010 011 100 101 110 111 : don?t care
pedl9041a-02 oki semiconductor ml9041a-xxa/xxb 26/64 table 3-2 relationship between cgram address bits, cgram data bits (character pattern) and ddram data bits (character code) in 5 10 dot character mode (examples) cg ram cg ram data address ( character p attern ) (character code) dd ram data 543210 76543210 76543210 lsb msb msb lsb msb lsb 0000 00 000000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 0000 01 00000 00000 01111 10001 10001 10001 01111 00001 00001 01110 00000 0000 11 00000 00000 11011 01010 10001 10001 01110 00000 00000 00000 00000 01000 01111 10010 01111 01010 11111 00010 00000 00000 00000 00000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 010000 110000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 : don?t care
pedl9041a-02 oki semiconductor ml9041a-xxa/xxb 27/64 cursor/blink control circuit this circuit generates the cursor and blink of the lcd. the operation of this circuit is controlled by the program of the cpu. the cursor/blink display is carried out in the position corresponding to the ddram address set in the adc (address counter). for example, when the adc stores a value of ?07? (hexadecimal), the cursor or blink is displayed as follows: 0 db 6 db 0 000111 7 0 00 01 02 03 04 07 08 digit 1 2345 89 cursor/blink position 12 13 19 20 67 05 06 00 01 02 03 04 07 08 digit 1 2345 89 cursor/blink position 12 13 19 20 67 05 06 40 41 42 43 44 47 48 52 53 45 46 first line a dc in 1-line display mode in 2-line display mode second line note: the cursor or blink is also displayed even when a cgram or abram address is set in the adc. therefore, the cursor or blink display should be inhibited while the adc is holding a cgram or abram address.
pedl9041a-02 oki semiconductor ml9041a-xxa/xxb 28/64 lcd display circuit (com1 to com17, seg1 to seg100, ssr and csr) the ml9041a has 17 common signal outputs and 100 segment signal outputs to display 20 characters (in the 1- line display mode) or 40 characters (in the 2-line display mode). the character pattern is converted into serial data and transferred in series through the shift register. the transfer direction of serial data is determined by the ssr pin. the shift direction of common signals is determined by the csr pin. the following tables show the transfer and shift directions: ssr transfer direction l seg 1 seg 100 h seg 100 seg 1 csr duty as bit shift direction arbitrator?s common pin l1/9l com1 com9 com9 l1/9h com1 com9 com1 l1/12l com1 com12 com12 l1/12h com1 com12 com1 l1/17l com1 com17 com17 l1/17h com1 com17 com1 h1/9l com9 com1 com1 h1/9h com9 com1 com9 h 1/12 l com12 com1 com1 h 1/12 h com12 com1 com12 h 1/17 l com17 com1 com1 h 1/17 h com17 com1 com17 * refer to the expansion instruction codes section about the as bit. signals to be input to the ssr and csr pins should be determined at power-on and be kept unchanged.
pedl9041a-02 oki semiconductor ml9041a-xxa/xxb 29/64 built-in reset circuit the ml9041a is automatically initialized when the power is turned on. during initialization, the busy flag (bf) is ?1? and the ml9041a does not accept any instruction from the cpu (other than the read bf instruction). the busy flag is ?1? for about 15 ms after the v dd becomes 2.7 v or higher. during this initialization, the ml9041a performs the following instructions: 1) display clearing 2) cpu interface data length = 8 bits (dl = ?1?) 3) 1-line lcd display (n = ?0?) 4) font size = 5 7 dots (f = ?0?) 5) adc counting = increment (i/d = ?1?) 6) display shifting = none (s = ?0?) 7) display = off (d = ?0?) 8) cursor = off (c = ?0?) 9) blinking = off (b = ?0?) 10) arbitrator = displayed in the lower line (as = ?0?) 11) setting 1fh (hexadecimal) to the contrast data to use the built-in reset circuit, the power supply conditions shown below should be satisfied. otherwise, the built-in reset circuit may not work properly. in such a case, initialize the ml9041a with the instructions from the cpu. the use of a battery always requires such initialization from the cpu. (see ?initial setting of instructions?) t on 2.7 v 0.2 v 0.2 v 0.2 v t off 0.1 ms t on 100 ms 1 ms t off figure 1 power-on and power-off waveform
pedl9041a-02 oki semiconductor ml9041a-xxa/xxb 30/64 i/f with cpu parallel interface mode the ml9041a can transfer either 8 bits once or 4 bits twice on the data bus for interfacing with any 8-bit or 4-bit microcontroller (cpu). 1) 8-bit interface data length the ml9041a uses all of the 8 data bus lines db 0 to db 7 at a time to transfer data to and from the cpu. 2) 4-bit interface data length the ml9041a uses only the higher-order 4 data bus lines db 4 to db 7 twice to transfer 8-bit data to and from the cpu. the ml9041a first transfers the higher-order 4 bits of 8-bit data (db 4 to db 7 in the case of 8-bit interface data length) and then the lower-order 4 bits of the data (db 0 to db 3 in the case of 8-bit interface data length). the lower-order 4 bits of data should always be transferred even when only the transfer of the higher-order 4 bits of data is required. (example: reading the busy flag) two transfers of 4 bits of data complete the transfer of a set of 8-bit data. therefore, when only one access is made, the following data transfer cannot be completed properly.
pedl9041a-02 oki semiconductor ml9041a-xxa/xxb 31/64 rs 0 r/ w e busy (internal operation) ir 7 db 6 db 5 db 4 db 3 db 2 db 1 db 0 db 7 busy no busy dr 7 ir 6 dr 6 adc 6 ir 5 dr 5 adc 5 ir 4 dr 4 adc 4 ir 3 dr 3 adc 3 ir 2 dr 2 adc 2 ir 1 dr 1 adc 1 ir 0 dr 0 adc 0 rs 1 writing in ir (instruction register) reading bf (busy flag) and adc (address counter) writing in dr (data register) figure 2 8-bit data transfer rs 0 r/ w e busy (internal operation) db 7 db 6 db 5 db 4 ir 7 busy no busy dr 7 dr 3 adc 3 adc 5 dr 6 dr 2 adc 2 dr 5 dr 1 adc 1 adc 4 dr 4 dr 0 adc 0 adc 6 ir 3 ir 6 ir 2 ir 5 ir 1 ir 4 ir 0 rs 1 writing in ir (instruction register) reading bf (busy flag) and adc (address counter) writing in dr (data register) figure 3 4-bit data transfer
pedl9041a-02 oki semiconductor ml9041a-xxa/xxb 32/64 serial interface mode in the serial i/f mode, the ml9041a interfaces with the cpu via the cs , sht , si and so pins. writing and reading operations are executed in units of 16 bits after the cs signal falls down. if the cs signal rises up before the completion of 16-bit unit access, this access is ignored. when the bf bit is ?1?, the ml9041a cannot accept any other instructions. before inputting a new instruction, check that the bf bit is ?0?. any access when the bf bit is ?1? is ignored. data format is lsb-first. examples of access in the serial i/f mode note 1: higher 5 bits of each instruction must be input at a ?h? level. note 2: lower 8 bits are ?don?t care? when the instructions in the read mode are set. note 3: after one instruction is input, the next instruction must be input after the cs pin is pulled at a ?h? level. 1 ) write mode cs sht busy si so 2 ) read mode cs sht busy si so rs1 1 d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 15 16 1 11111 r/ w rs0 11 12 13 14 78910 3456 d 5 d 6 d 7 1 d 1 d 2 d 3 d 4 12 11111 r/ w rs0 rs1 d 0 78 1 13 14 15 16 91011 3456 ( internal o p eration ) ( internal o p eration ) 12 12
pedl9041a-02 oki semiconductor ml9041a-xxa/xxb 33/64 instruction codes table of instruction codes code instruction rs 1 rs 0 r/ w db 7 db 6 db 5 db 4 db 3 db 2 db 1 db 0 function execution time f = 270 khz display clear 1 0 0 0 0 0 0 0 0 0 1 clears all the displayed digits of the lcd and sets the ddram address 0 in the address counter. the arbitrator data is cleared. 1.52 ms cursor home 1 0 0 0 0 0 0 0 0 1 x sets the ddram address 0 in the address counter and shifts the display back to the original. the content of the ddram remains unchanged. 1.52 ms entry mode setting 1 0 0 0 0 0 0 0 1 i/d s determines the direction of movement of the cursor and whether or not to shift the display. this instruction is executed when data is written or read. 37 s display on/off control 10 0 0000 1dcb sets lcd display on/off (d), cursor on/off or cursor-position character blinking on/off. 37 s cursor/display shift 10 0 0001s/cr/lxx moves the cursor or shifts the display without changing the content of the ddram. 37 s function setting 1 0 0 0 0 1 dl n f x x sets the interface data length (dl), the number of display lines (n) or the type of character font (f). 37 s cgram address setting 10 0 01 acg sets on cgram address. after that, cgram data is transferred to and from the cpu. 37 s ddram address setting 10 0 1 add sets a ddram address. after that, ddram data is transferred to and from the cpu. 37 s busy flag/ address read 10 1bf adc reads the busy flag (indicating that the ml9041a is operating) and the content of the address counter. 0 s ram data write 1 1 0 write data writes data in ddram, abram or cgram. 37 s ram data read 1 1 1 read data reads data from ddram, abram or cgram. 37 s arbitrator display line set 0 0 0 0 0 0 0 0 0 1 as sets the arbitrator display line. 37 s contrast control data write 00 0 001 write (contrast data) data writes data to control the contrast of the lcd. 37 s contrast control data read 00 1 000 read (contrast data) data reads data to control the contrast of the lcd. 37 s abram address setting 00 0 011 aab sets an abram address. after that, abram data is transferred to and from the cpu. 37 s ? i/d = ?1? (increment) i/d = ?0? (decrement) s = ?1? (shifts the display.) s/c = ?1? (shifts display.) s/c = ?0? (moves the cursor.) r/l = ?1? (right shift) r/l = ?0? (left shift) d/l = ?1? (8-bit data) dl = ?0? (4-bit data) n = ?1? (2 lines) n = ?0? (1 line) f = ?1? (5 x 10 dots) f = ?0? (5 x 7 dots) bf = ?1? (busy) bf = ?0? (ready to accept an instruction) b = ?1? (enables blinking) c = ?1? (displays the cursor.) d = ?1? (displays a character pattern.) as = ?1? (arbitrator displays as = ?0? (arbitrator displays arbitrator on the arbitrator on the upper line) lower line) dd ram: display data ram cg ram: character generator ram abram: arbitrator data ram acg: cgram address add: ddram address (corresponds to the cursor address) aab: abram address adc: address counter (used by ddram, abram and cgram) the execution time is dependent upon frequen- cies. : don't care
pedl9041a-02 oki semiconductor ml9041a-xxa/xxb 34/64 instruction codes an instruction code is a signal sent from the cpu to access the ml9041a. the ml9041a starts operation as instructed by the code received. the busy status of the ml9041a is rather longer than the cycle time of the cpu, since the internal processing of the ml9041a starts at a timing which does not affect the display on the lcd. in the busy status (busy flag is ?1?), the ml9041a cannot input the busy flag read instruction only. therefore, the cpu should ensure that the busy flag is ?0? before sending an instruction code to the ml9041a. 1) display clear rs 1 1 rs 0 0 r/ w 0 db 7 0 db 6 0 db 5 0 db 4 0 db 3 0 db 2 0 db 1 0 db 0 1 instruction code: when this instruction is executed, the lcd display including arbitrator display is cleared and the i/d entry mode is set to ?increment?. the value of ?s? (display shifting) remains unchanged. the position of the cursor or blink being displayed moves to the left end of the lcd (or the left end of the line 1 in the 2-line display mode). note: all ddram and abram data turn to ?20? and ?00? in hexadecimal, respectively. the value of the address counter (adc) turns to the one corresponding to the address ?00? (hexadecimal) of the ddram. the execution time of this instruction is 1.52 ms (maximum) at an oscillation frequency of 270 khz. 2) cursor home rs 1 1 rs 0 0 r/ w 0 db 7 0 db 6 0 db 5 0 db 4 0 db 3 0 db 2 0 db 1 1 db 0 instruction code: : don?t care when this instruction is executed, the cursor or blink position moves to the left end of the lcd (or the left end of line 1 in the 2-line display mode). if the display has been shifted, the display returns to the original display position before shifting. note: the value of the address counter (adc) goes to the one corresponding to the address ?00? (hexadecimal) of the ddram). the execution time of this instruction is 1.52 ms (maximum) at an oscillation frequency of 270 khz.
pedl9041a-02 oki semiconductor ml9041a-xxa/xxb 35/64 3) entry mode setting rs 1 1 rs 0 0 r/ w 0 db 7 0 db 6 0 db 5 0 db 4 0 db 3 0 db 2 1 db 1 i/d db 0 s instruction code: (1) when the i/d is set, the cursor or blink shifts to the right by 1 character position (id= ?1?; increment) or to the left by 1 character position (i/d= ?0?; decrement) after an 8-bit character code is written to or read from the ddram. at the same time, the address counter (adc) is also incremented by 1 (when i/d = ?1?; increment) or decremented by 1 (when i/d = ?0?; decrement). after a character pattern is written to or read from the cgram, the address counter (adc) is incremented by 1 (when i/d = ?1?; increment) or decremented by 1 (when i/d = ?0?; decrement). also after data is written to or read from the abram, the address counter (adc) is incremented by 1 (when i/d = ?1?; increment) or decremented by 1 (when i/d = ?0?; decrement). (2) when s = ?1?, the cursor or blink stops and the entire display shifts to the left (i/d = ?1?) or to the right (i/d = ?0?) by 1 character position after a character code is written to the ddram. in the case of s = ?1?, when a character code is read from the ddram, when a character pattern is written to or read from the cgram or when data is written to or read from the abram, normal read/write is carried out without shifting of the entire display. (the entire display does not shift, but the cursor or blink shifts to the right (i/d = ?1?) or to the left (i/d = ?0?) by 1 character position.) when s = ?0?, the display does not shift, but normal write/read is performed. note: the execution time of this instruction is 37 s (maximum) at an oscillation frequency of 270 khz. 4) display on/off control rs 1 1 rs 0 0 r/ w 0 db 7 0 db 6 0 db 5 0 db 4 0 db 3 1 db 2 d db 1 c db 0 b instruction code: (1) the ?d? bit (db2) of this instruction determines whether or not to display character patterns on the lcd. when the ?d? bit is ?1?, character patterns are displayed on the lcd. when the ?d? bit is ?0?, character patterns are not displayed on the lcd and the cursor/blinking also disappear. note: unlike the display clear instruction, this instruction does not change the character code in the ddram and abram. (2) when the ?c? bit (db1) is ?0?, the cursor turns off. when both the ?c? and ?d? bits are ?1?, the cursor turns on. (3) when the ?b? bit (db0) is ?0?, blinking is canceled. when both the ?b? and ?d? bits are ?1?, blinking is performed. in the blinking mode, all dots including those of the cursor, the character pattern and the cursor are alternately displayed. note: the execution time of this instruction is 37 s (maximum) at an oscillation frequency of 270 khz.
pedl9041a-02 oki semiconductor ml9041a-xxa/xxb 36/64 5) cursor/display shift rs 1 1 rs 0 0 r/ w 0 db 7 0 db 6 0 db 5 0 db 4 1 db 3 s/c db 2 r/l db 1 db 0 instruction code: : don?t care s/c = ?0?, r/l = ?0? this instruction shifts left the cursor and blink positions by 1 (decrements the content of the adc by 1). s/c = ?0?, r/l = ?1? this instruction shifts right the cursor and blink positions by 1 (increments the content of the adc by 1). s/c = ?1?, r/l = ?0? this instruction shifts left the entire display by 1 character position. the cursor and blink positions move to the left together with the entire display. the arbitrator display is not shifted. (the content of the adc remains unchanged.) s/c = ?1?, r/l = ?1? this instruction shifts right the entire display by 1 character position. the cursor and blink positions move to the right together with the entire display. the arbitrator display is not shifted. (the content of the adc remains unchanged.) in the 2-line mode, the cursor or blink moves from the first line to the second line when the cursor at digit 40 (27; hex) of the first line is shifted right. when the entire display is shifted, the character pattern, cursor or blink will not move between the lines (from line 1 to line 2 or vice versa). note: the execution time of this instruction is 37 s at an oscillation frequency (osc) of 270 khz. 6) function setting rs 1 1 rs 0 0 r/ w 0 db 7 0 db 6 0 db 5 1 db 4 dl db 3 n db 2 f db 1 db 0 : don?t care instruction code: (1) when the ?dl? bit (db 4 ) of this instruction is ?1?, the data transfer to and from the cpu is performed once by the use of 8 bits db 7 to db 0 . when the ?dl? bit (db 4 ) of this instruction is ?0?, the data transfer to and from the cpu is performed twice by the use of 4 bits db 7 to db 4 . (2) the 2-line display mode is selected when the ?n? bit (db 3 ) of this instruction is ?1?. the 1-line display mode is selected when the ?n? bit is ?0?. (3) the character font represented by 5 7 dots is selected when the ?f? bit (db 2 ) of this instruction is ?1?. the character font represented by 5 10 dots is selected when the ?f? bit is ?1? and the ?n? bit is ?0?. after the ml9041a is powered on, this function setting should be carried out before execution of any instruction except the busy flag read. after this function setting, no instructions other than the dl set instruction can be executed. in the serial i/f mode, dl setting is ignored. nf number of display lines font size duty number of biases number of common signals 00 1 5 7 1/9 4 9 01 1 5 10 1/12 4 12 10 2 5 7 1/17 5 17 11 2 5 7 1/17 5 17 note: the execution time of this instruction is 37 s at an oscillation frequency (osc) of 270 khz.
pedl9041a-02 oki semiconductor ml9041a-xxa/xxb 37/64 7) cgram address setting rs 1 1 rs 0 0 r/ w 0 db 7 0 db 6 1 db 5 c 5 db 4 c 4 db 3 c 3 db 2 c 2 db 1 c 1 db 0 c 0 instruction code: this instruction sets the cgram address to the data represented by the bits c 5 to c 0 (binary). the cgram addresses are valid until ddram or abram addresses are set. the cpu writes or reads character patterns starting from the one represented by the cgram address bits c 5 to c 0 set in the instruction code at that time. note: the execution time of this instruction is 37 s at an oscillation frequency (osc) of 270 khz. 8) ddram address setting rs 1 1 rs 0 0 r/ w 0 db 7 1 db 6 d 6 db 5 d 5 db 4 d 4 db 3 d 3 db 2 d 2 db 1 d 1 db 0 d 0 instruction code: this instruction sets the ddram address to the data represented by the bits d 6 to d 0 (binary). the ddram addresses are valid until cgram or abram addresses are set. the cpu writes or reads character codes starting from the one represented by the ddram address bits d 6 to d 0 set in the instruction code at that time. in the 1-line mode (the ?n? bit is ?0?), the ddram address represented by bits d 6 to d 0 (binary) should be in the range ?00? to ?4f? in hexadecimal. in the 2-line mode (the ?n? bit is ?1?), the ddram address represented by bits d 6 to d 0 (binary) should be in the range ?00? to ?27? or ?40? to ?67? in hexadecimal. if an address other than above is input, the ml9041a cannot properly write a character code in or read it from the ddram. note: the execution time of this instruction is 37 s at an oscillation frequency (osc) of 270 khz. 9) ddram/abram/cgram data write rs 1 1 rs 0 1 r/ w 0 db 7 e 7 db 6 e 6 db 5 e 5 db 4 e 4 db 3 e 3 db 2 e 2 db 1 e 1 db 0 e 0 instruction code: a character code (e 7 to e 0 ) is written to the ddram, display-on data (e 7 to e 0 ) to the abram or a character pattern (e 7 to e 0 ) to the cgram. the ddram, abram or cgram is selected at the preceding address setting. after data is written, the address counter (adc) is incremented or decremented as set by the entry mode setting instruction (see 3). note: the execution time of this instruction is 37 s at an oscillation frequency (osc) of 270 khz.
pedl9041a-02 oki semiconductor ml9041a-xxa/xxb 38/64 10) busy flag/address counter read (execution time: 0 s) rs 1 1 rs 0 0 r/ w 1 db 7 bf db 6 o 6 db 5 o 5 db 4 o 4 db 3 o 3 db 2 o 2 db 1 o 1 db 0 o 0 instruction code: the ?bf? bit (db7) of this instruction tells whether the ml9041a is busy in internal operation (bf = ?1?) or not (bf = ?0?). when the ?bf? bit is ?1?, the ml9041a cannot accept any other instructions. before inputting a new instruction, check that the ?bf? bit is ?0?. when the ?bf? bit is ?0?, the ml9041a outputs the correct value of the address counter. the value of the address counter is equal to the ddram, abram or cgram address. which of the ddram, abram and cgram addresses is set in the counter is determined by the preceding address setting. when the ?bf? bit is ?1?, the value of the address counter is not always correct because it may have been incremented or decremented by 1 during internal operation. 11) ddram/abram/cgram data read rs 1 1 rs 0 1 r/ w 1 db 7 p 7 db 6 p 6 db 5 p 5 db 4 p 4 db 3 p 3 db 2 p 2 db 1 p 1 db 0 p 0 instruction code: a character code (p 7 to p 0 ) is read from the ddram, display-on data (p 7 to p 0 ) from the abram or a character pattern (p 7 to p 0 ) from the cgram. the ddram, abram or cgram is selected at the preceding address setting. after data is read, the address counter (adc) is incremented or decremented as set by the entry mode setting instruction (see 3). note: conditions for reading correct data (1) the ddram, abram or cgram setting instruction is input before this data read instruction is input. (2) when reading a character code from the ddram, the cursor/display shift instruction (see 5) is input before this data read instruction is input. (3) when two or more consecutive ram data read instructions are executed, the following read data is correct. correct data is not output under conditions other than the cases (1), (2) and (3) above. note: the execution time of this instruction is 37 s at an oscillation frequency (osc) of 270 khz.
pedl9041a-02 oki semiconductor ml9041a-xxa/xxb 39/64 expansion instruction codes the busy status of the ml9041a is rather longer than the cycle time of the cpu, since the internal processing of the ml9041a starts at a timing which does not affect the display on the lcd. in the busy status (busy flag is ?1?), the ml9041a executes the busy flag read instruction only. therefore, the cpu should ensure that the busy flag is ?0? before sending an expansion instruction code to the ml9041a. 1) arbitrator display line set rs 1 0 rs 0 0 r/ w 0 db 7 0 db 6 0 db 5 0 db 4 0 db 3 0 db 2 0 db 1 1 db 0 as expansion instruction code: this expansion instruction code sets the arbitrator display line. the relationship between the status of this bit and the common outputs is as follows: for display examples, refer to lcd drive waveforms section. csr duty as bit shift direction arbitrator?s common pin l1/9 l com1 com9 com9 l1/9 h com1 com9 com1 l1/12 l com1 com12 com12 l1/12 h com1 com12 com1 l1/17 l com1 com17 com17 l1/17 h com1 com17 com1 h1/9 l com9 com1 com1 h1/9 h com9 com1 com9 h1/12 l com12 com1 com1 h1/12 h com12 com1 com12 h1/17 l com17 com1 com1 h1/17 h com17 com1 com17 note: the execution time of this instruction is 37 s at an oscillation frequency (osc) of 270 khz. 2) contrast adjusting data write rs 1 0 rs 0 0 r/ w 0 db 7 0 db 6 0 db 5 1 db 4 f 4 db 3 f 3 db 2 f 2 db 1 f 1 db 0 f 0 expansion instruction code: this instruction writes contrast adjusting data (f 4 to f 0 ) to the contrast register. after contrast adjusting data is written in the register, the potential (vlcd) output to the v 5 pin varies according to the data written. the vlcd becomes maximum when the content of the contrast register is ?1f? (hexadecimal) and becomes minimum when it is ?00? (hexadecimal). note: the execution time of this instruction is 37 s at an oscillation frequency (osc) of 270 khz.
pedl9041a-02 oki semiconductor ml9041a-xxa/xxb 40/64 3) contrast adjusting data read rs 1 0 rs 0 0 r/ w 1 db 7 0 db 6 0 db 5 0 db 4 g 4 db 3 g 3 db 2 g 2 db 1 g 1 db 0 g 0 expansion instruction code: this instruction reads contrast adjusting data (g 4 to g 0 ) from the contrast register. note: the execution time of this instruction is 37 s at an oscillation frequency (osc) of 270 khz. 4) abram address setting rs 1 0 rs 0 0 r/ w 1 db 7 0 db 6 1 db 5 1 db 4 h 4 db 3 h 3 db 2 h 2 db 1 h 1 db 0 h 0 expansion instruction code: this instruction sets the abram address to the data represented by the bits h 4 to h 0 (binary). the abram addresses are valid until cgram or ddram addresses are set. the cpu writes or reads the display-on data starting from the one represented by the abram address bits h 4 to h 0 set in the instruction code at that time. when the abram address represented by bits h 4 to h 0 (binary) is in the range ?00? to ?13? in hexadecimal, data is output to the lcd as the arbitrator. note: the execution time of this instruction is 37 s at an oscillation frequency (osc) of 270 khz.
pedl9041a-02 oki semiconductor ml9041a-xxa/xxb 41/64 examples of combinations of ml9041a and lcd panel (1) driving the lcd of one 20-character line under the conditions of the 1-line display mode and the character font of 5 7 dots (1/9 duty, as = ?0?, csr = ?l?, ssr = ?h?) com 1 character cursor a rbitrator com 8 com 9 seg 100 seg 1 ml9041a ? com 10 to com 17 output display-off common signals. (1/9 duty, as = ?1?, csr = ?l?, ssr = ?h?) com 1 com 2 character cursor com 9 seg 100 seg 1 ml9041a a rbitrator ? com 10 to com 17 output display-off common signals.
pedl9041a-02 oki semiconductor ml9041a-xxa/xxb 42/64 (1/9 duty, as = ?0?, csr = ?h?, ssr = ?l?) com 9 character cursor a rbitrator com 2 com 1 seg 1 seg 100 ml9041a ? com 10 to com 17 output display-off common signals. (1/9 duty, as = ?1?, csr = ?h?, ssr = ?l?) com 8 com 9 character cursor com 1 seg 1 seg 100 ml9041a a rbitrator ? com 10 to com 17 output display-off common signals.
pedl9041a-02 oki semiconductor ml9041a-xxa/xxb 43/64 (2) driving the lcd of one 20-character line under the conditions of the 1-line display mode and the character font of 5 10 dots (1/12 duty, as = ?0?, csr = ?l?, ssh = ?h?) com 1 com 11 com 12 seg 100 seg 1 ml9041a character cursor a rbitrator ? com 13 to com 17 output display-off common signals. (1/12 duty, as = ?1?, csr = ?l?, ssr = ?h?) com 1 com 2 com 12 seg 100 seg 1 ml9041a character cursor a rbitrator ? com 13 to com 17 output display-off common signals.
pedl9041a-02 oki semiconductor ml9041a-xxa/xxb 44/64 (1/12 duty, as = ?0?, csr = ?h?, ssr = ?l?) com 12 com 2 com 1 seg 1 seg 100 ml9041a character cursor a rbitrator ? com 13 to com 17 output display-off common signals. (1/12 duty, as = ?1?, csr = ?h?, ssr = ?l?) com 12 com 11 com 1 seg 1 seg 100 ml9041a character cursor a rbitrator ? com 13 to com 17 output display-off common signals.
pedl9041a-02 oki semiconductor ml9041a-xxa/xxb 45/64 (3) driving the lcd of two 20-character lines under the conditions of the 2-line display mode and the character font of 5 7 dots (1/17 duty, as = ?0?, csr = ?l?, ssr = ?h?) com 1 com 8 seg 100 seg 1 ml9041a com 9 com 16 com 17 character cursor character cursor a rbitrator (1/17 duty, as = ?1?, csr = ?l?, ssr = ?h?) com 2 com 1 com 9 seg 100 seg 1 ml9041a com 10 com 17 character cursor character cursor a rbitrator
pedl9041a-02 oki semiconductor ml9041a-xxa/xxb 46/64 (1/17 duty, as = ?0?, csr = ?h?, ssr = ?l?) com 17 com 10 seg 1 seg 100 ml9041a com 9 com 2 com 1 character cursor character cursor a rbitrator (1/17 duty, as = ?1?, csr = ?h?, ssr = ?l?) com 16 com 17 com 9 seg 1 seg 100 ml9041a com 8 com 1 character cursor character cursor a rbitrator
pedl9041a-02 oki semiconductor ml9041a-xxa/xxb 47/64 examples of vlcd generation circuits ? with 1/4bias, a built-in contrast adjusting circuit and a voltage multiplier ml9041a be v in v cc v c v 5in v 5 v 4 v 3b v 3a v 2 v 1 v dd reference potential for voltage multiplier ? with 1/4 bias, a built-in contrast adjusting circuit ? with 1/4 bias, no built-in contrast adjusting circuit and the v 5 level input from an external circuit and the v 5 level input from an external circuit ml9041a be v in v cc v c v 5in v 5 v 4 v 3b v 3a v 2 v 1 v dd v 5 level ml9041a be v in v cc v c v 5in v 5 v 4 v 3b v 3a v 2 v 1 v dd v 5 level
pedl9041a-02 oki semiconductor ml9041a-xxa/xxb 48/64 ? with 1/5 bias, a built-in contrast adjusting circuit and a voltage multiplier ml9041a be v in v cc v c v 5in v 5 v 4 v 3b v 3a v 2 v 1 v dd reference potential for voltage multiplier ? with 1/5 bias, a built-in contrast adjusting circuit ? with 1/5 bias, no built-in contrast adjusting circuit and the v 5 level input from an external circuit and the v 5 level input from an external circuit ml9041a be v in v cc v c v 5in v 5 v 4 v 3b v 3a v 2 v 1 v dd v 5 level ml9041a be v in v cc v c v 5in v 5 v 4 v 3b v 3a v 2 v 1 v dd v 5 level
pedl9041a-02 oki semiconductor ml9041a-xxa/xxb 49/64 lcd drive waveforms the com and seg waveforms (ac signal waveforms for display) vary according to the duty (1/9, 1/12 and 1/17 duties). see 1) to 3) below. the relationship between the duty ratio and the frame frequency is as follows: duty ratio frame frequency 1/9 75.0 hz 1/12 56.3 hz 1/17 79.4 hz note: at an oscillation frequency (osc) of 270 khz 1) com and seg waveforms on 1/9 duty v dd 1 frame v 1 v 2 , v 3b v 4 v 5 v dd v 1 v 2 , v 3b v 4 v 5 v dd v 1 v 2 , v 3b v 4 v 5 v dd v 1 v 2 , v 3b v 4 v 5 com 1 (csr = ?l?, as = ?l?) com 2 (csr = ?l?, as = ?h?) com 9 (csr = ?h?, as = ?l?) com 8 (csr = ?h?, as = ?h?) (first character line) com 2 (csr = ?l?, as = ?l?) com 3 (csr = ?l?, as = ?h?) com 8 (csr = ?h?, as = ?l?) com 7 (csr = ?h?, as = ?h?) (second character line) com 8 (csr = ?l?, as = ?l?) com 9 (csr = ?l?, as = ?h?) com 2 (csr = ?h?, as = ?l?) com 1 (csr = ?h?, as = ?h?) (cursor line) com 9 (csr = ?l?, as = ?l?) com 1 (csr = ?l?, as = ?h?) com 1 (csr = ?h?, as = ?l?) com 9 (csr = ?h?, as = ?h?) (arbitrator line) v dd v 1 v 2 , v 3b v 4 v 5 com 10 to com 17 v dd v 1 v 2 , v 3b v 4 v 5 seg display turning-off waveform display turning-on waveform 89 1 2 3 4 7 8 9 1 2 3 4 7 8 9 1 2 21 9 8 7 6 3 2 1 9 8 7 6 3 2 1 9 8 csr = ?h? csr = ?l?
pedl9041a-02 oki semiconductor ml9041a-xxa/xxb 50/64 2) com and seg waveforms on 1/12 duty v dd 1 frame v 1 v 2 , v 3b v 4 v 5 v dd v 1 v 2 , v 3b v 4 v 5 v dd v 1 v 2 , v 3b v 4 v 5 v dd v 1 v 2 , v 3b v 4 v 5 v dd v 1 v 2 , v 3b v 4 v 5 v dd v 1 v 2 , v 3b v 4 v 5 display turning-off waveform display turning-on waveform com 1 (csr = ?l?, as = ?l?) com 2 (csr = ?l?, as = ?h?) com 12 (csr = ?h?, as = ?l?) com 11 (csr = ?h?, as = ?h?) (first character line) com 2 (csr = ?l?, as = ?l?) com 3 (csr = ?l?, as = ?h?) com 11 (csr = ?h?, as = ?l?) com 10 (csr = ?h?, as = ?h?) (second character line) com 11 (csr = ?l?, as = ?l?) com 12 (csr = ?l?, as = ?h?) com 2 (csr = ?h?, as = ?l?) com 1 (csr = ?h?, as = ?h?) (cursor line) com 12 (csr = ?l?, as = ?l?) com 1 (csr = ?l?, as = ?h?) com 1 (csr = ?h?, as = ?l?) com 12 (csr = ?h?, as = ?h?) (arbitrator line) com 13 to com 17 seg 21 12 11 10 9 8 7 4 3 2 1 12 11 10 9 8 7 csr = ?h? 11 12 1 2 3 4 5 6 9 10 11 12 1 2 3 4 5 6 csr = ?l?
pedl9041a-02 oki semiconductor ml9041a-xxa/xxb 51/64 3) com and seg waveforms on 1/17 duty v dd 1 frame v 1 v 2 v 3a (v 3b ) v 4 display turning-off waveform display turning-on waveform v 5 v dd v 1 v 2 v 3a (v 3b ) v 4 v 5 v dd v 1 v 2 v 3a (v 3b ) v 4 v 5 v dd v 1 v 2 v 3a (v 3b ) v 4 seg v 5 v dd v 1 v 2 v 3a (v 3b ) v 4 v 5 com 1 (csr = ?l?, as = ?l?) com 2 (csr = ?l?, as = ?h?) com 17 (csr = ?h?, as = ?l?) com 16 (csr = ?h?, as = ?h?) (first character line) com 2 (csr = ?l?, as = ?l?) com 3 (csr = ?l?, as = ?h?) com 16 (csr = ?h?, as = ?l?) com 15 (csr = ?h?, as = ?h?) (second character line) com 16 (csr = ?l?, as = ?l?) com 17 (csr = ?l?, as = ?h?) com 2 (csr = ?h?, as = ?l?) com 1 (csr = ?h?, as = ?h?) (cursor line) com 17 (csr = ?l?, as = ?l?) com 1 (csr = ?l?, as = ?h?) com 1 (csr = ?h?, as = ?l?) com 17 (csr = ?h?, as = ?h?) (arbitrator line) 16 17 1 2 3 4 5 6 7 8 9 10 11 12 13 16 17 1 2 3 4 csr = ?l? 21 17 16 15 14 13 12 11 10 9 8 7 6 5 2 1 17 16 15 14 csr = ?h?
pedl9041a-02 oki semiconductor ml9041a-xxa/xxb 52/64 initial setting of instructions (a) data transfer from and to the cpu using 8 bits of db 0 to db 7 1) turn on the power. 2) wait for 15 ms or more after v dd has reached 2.7 v or higher. 3) set ?8 bits? with the function setting instruction. 4) wait for 4.1 ms or more. 5) set ?8 bits? with the function setting instruction. 6) wait for 100 s or more. 7) set ?8 bits? with the function setting instruction. 8) check the busy flag for no busy (or wait for 100 s or more). 9) set ?8 bits?, ?number of lcd lines? and ?font size? with the function setting instruction. (after this, the number of lcd lines and the font size cannot be changed.) 10) check the busy flag for no busy. 11) execute the display on/off control instruction, display clear instruction, entry mode setting instruction and arbitrator display line setting instruction. 12) check the busy flag for no busy. 13) initialization is completed. an example of instruction code for 3), 5) and 7) rs 1 1 rs 0 0 r/ w 0 db 7 0 db 6 0 db 5 1 db 4 1 db 3 db 2 db 1 db 0 : don?t care (b) data transfer from and to the cpu using 4 bits of db 4 to db 7 1) turn on the power. 2) wait for 15 ms or more after v dd has reached 2.7 v or higher. 3) set ?8 bits? with the function setting instruction. 4) wait for 4.1 ms or more. 5) set ?8 bits? with the function setting instruction. 6) wait for 100 s or more. 7) set ?8 bits? with the function setting instruction. 8) check the busy flag for no busy (or wait for 100 s or longer). 9) set ?4 bits? with the function setting instruction. 10) wait for 100 s or longer. 11) set ?4 bits?, ?number of lcd lines? and ?font size? with the function setting instruction. (after this, the number of lcd lines and the font size cannot be changed.) 12) check the busy flag for no busy. 13) execute the display on/off control instruction, display clear instruction, entry mode setting instruction and arbitrator display line setting instruction. 14) check the busy flag for no busy. 15) initialization is completed. an example of instruction code for 3), 5) and 7) rs 1 1 rs 0 0 r/ w 0 db 7 0 db 6 0 db 5 1 db 4 1
pedl9041a-02 oki semiconductor ml9041a-xxa/xxb 53/64 an example of instruction code for 9) rs 1 1 rs 0 0 r/ w 0 db 7 0 db 6 0 db 5 1 db 4 0 *: from 11), input data twice by the use of 4-bit data. *: in 13), check the busy flag for no busy before executing each instruction. (c) data transfer from and to the cpu using the serial i/f 1) turn on the power. 2) wait for 15 ms or more after v dd has reached 2.7 v or higher. 3) check the busy flag for no busy. 4) set ?number of lcd lines? and ?font size? with the function setting instruction. (after this, the number of lcd lines and the font size cannot be changed.) 5) check the busy flag for no busy. 6) execute the display on/off control instruction, the display clear instruction, the entry mode instruction and the arbitrator display line setting instruction. 7) check the busy flag for no busy. 8) initialization is completed. *: in 6), check the busy flag for no busy before executing each instruction.
pedl9041a-02 oki semiconductor ml9041a-xxa/xxb 54/64 ml9041a-xxa cvwa pad configuration pad layout chip size: 10.62 2.55 mm chip thickness: 62520 m bump size (1): 72 72 m (pad no. 1-62, 183-189) bump size (2): 54 96 m (pad no. 63-182) y x 182 183 62 189 56 1 63 55 pad coordinates pad symbol x ( m) y ( m) pad symbol x ( m) y ( m) 1v 1 ?5103 ?1100 21 db 3 ?1323 ?1100 2v 2 ?4914 ?1100 22 db 2 ?1134 ?1100 3v 3a ?4725 ?1100 23 db 1 ?945 ?1100 4v 3b ?4536 ?1100 24 db 0 ?756 ?1100 5v 4 ?4347 ?1100 25 e ?567 ?1100 6v 5 ?4158 ?1100 26 r/ w ?378 ?1100 7v 5in ?3969 ?1100 27 rs 0 ?189 ?1100 8v cc ?3780 ?1100 28 rs 1 0 ?1100 9v c ?3591 ?1100 29 so 189 ?1100 10 v ln ?3402 ?1100 30 sl 378 ?1100 11 be ?3213 ?1100 31 sht 567 ?1100 12 v dd ?3024 ?1100 32 cs 756 ?1100 13 csr ?2835 ?1100 33 osc 2 945 ?1100 14 ssr ?2646 ?1100 34 osc r 1134 ?1100 15 s/ p ?2457 ?1100 35 osc 1 1323 ?1100 16 v ss ?2268 ?1100 36 t 3 1512 ?1100 17 db 7 ?2079 ?1100 37 t 2 1701 ?1100 18 db 6 ?1890 ?1100 38 t 1 1890 ?1100 19 db 5 ?1701 ?1100 39 com 1 2079 ?1100 20 db 4 ?1512 ?1100 40 com 2 2268 ?1100
pedl9041a-02 oki semiconductor ml9041a-xxa/xxb 55/64 pad symbol x ( m) y ( m) pad symbol x ( m) y ( m) 41 com 3 2457 ?1100 81 seg 92 3486 1088 42 com 4 2646 ?1100 82 seg 91 3402 1088 43 com 5 2835 ?1100 83 seg 90 3318 1088 44 com 6 3024 ?1100 84 seg 89 3234 1088 45 com 7 3213 ?1100 85 seg 88 3150 1088 46 com 8 3402 ?1100 86 seg 87 3066 1088 47 com 9 3591 ?1100 87 seg 86 2982 1088 48 com 10 3780 ?1100 88 seg 85 2898 1088 49 com 11 3969 ?1100 89 seg 84 2814 1088 50 com 12 4158 ?1100 90 seg 83 2730 1088 51 com 13 4347 ?1100 91 seg 82 2646 1088 52 com 14 4536 ?1100 92 seg 81 2562 1088 53 com 15 4725 ?1100 93 seg 80 2478 1088 54 com 16 4914 ?1100 94 seg 79 2394 1088 55 com 17 5103 ?1100 95 seg 78 2310 1088 56 dummy 5184 ?720 96 seg 77 2226 1088 57 dummy 5184 ?480 97 seg 76 2142 1088 58 dummy 5184 ?240 98 seg 75 2058 1088 59 dummy 5184 0 99 seg 74 1974 1088 60 dummy 5184 240 100 seg 73 1890 1088 61 dummy 5184 480 101 seg 72 1806 1088 62 dummy 5184 720 102 seg 71 1722 1088 63 dummy 4998 1088 103 seg 70 1638 1088 64 dummy 4914 1088 104 seg 69 1554 1088 65 dummy 4830 1088 105 seg 68 1470 1088 66 dummy 4746 1088 106 seg 67 1386 1088 67 dummy 4662 1088 107 seg 66 1302 1088 68 dummy 4578 1088 108 seg 65 1218 1088 69 dummy 4494 1088 109 seg 64 1134 1088 70 dummy 4410 1088 110 seg 63 1050 1088 71 dummy 4326 1088 111 seg 62 966 1088 72 dummy 4242 1088 112 seg 61 882 1088 73 seg 100 4158 1088 113 seg 60 798 1088 74 seg 99 4074 1088 114 seg 59 714 1088 75 seg 98 3990 1088 115 seg 58 630 1088 76 seg 97 3906 1088 116 seg 57 546 1088 77 seg 96 3822 1088 117 seg 56 462 1088 78 seg 95 3738 1088 118 seg 55 378 1088 79 seg 94 3654 1088 119 seg 54 294 1088 80 seg 93 3570 1088 120 seg 53 210 1088
pedl9041a-02 oki semiconductor ml9041a-xxa/xxb 56/64 pad symbol x ( m) y ( m) pad symbol x ( m) y ( m) 121 seg 52 126 1088 156 seg 17 ?2814 1088 122 seg 51 42 1088 157 seg 16 ?2898 1088 123 seg 50 ?42 1088 158 seg 15 ?2982 1088 124 seg 49 ?126 1088 159 seg 14 ?3066 1088 125 seg 48 ?210 1088 160 seg 13 ?3150 1088 126 seg 47 ?294 1088 161 seg 12 ?3234 1088 127 seg 46 ?378 1088 162 seg 11 ?3318 1088 128 seg 45 ?462 1088 163 seg 10 ?3402 1088 129 seg 44 ?546 1088 164 seg 9 ?3486 1088 130 seg 43 ?630 1088 165 seg 8 ?3570 1088 131 seg 42 ?714 1088 166 seg 7 ?3654 1088 132 seg 41 ?798 1088 167 seg 6 ?3738 1088 133 seg 40 ?882 1088 168 seg 5 ?3822 1088 134 seg 39 ?966 1088 169 seg 4 ?3906 1088 135 seg 38 ?1050 1088 170 seg 3 ?3990 1088 136 seg 37 ?1134 1088 171 seg 2 ?4074 1088 137 seg 36 ?1218 1088 172 seg 1 ?4158 1088 138 seg 35 ?1302 1088 173 dummy ?4242 1088 139 seg 34 ?1386 1088 174 dummy ?4326 1088 140 seg 33 ?1470 1088 175 dummy ?4410 1088 141 seg 32 ?1554 1088 176 dummy ?4494 1088 142 seg 31 ?1638 1088 177 dummy ?4578 1088 143 seg 30 ?1722 1088 178 dummy ?4662 1088 144 seg 29 ?1806 1088 179 dummy ?4746 1088 145 seg 28 ?1890 1088 180 dummy ?4830 1088 146 seg 27 ?1974 1088 181 dummy ?4914 1088 147 seg 26 ?2058 1088 182 dummy ?4998 1088 148 seg 25 ?2142 1088 183 dummy ?5184 720 149 seg 24 ?2226 1088 184 dummy ?5184 480 150 seg 23 ?2310 1088 185 dummy ?5184 240 151 seg 22 ?2394 1088 186 dummy ?5184 0 152 seg 21 ?2478 1088 187 dummy ?5184 ?240 153 seg 20 ?2562 1088 188 dummy ?5184 ?480 154 seg 19 ?2646 1088 189 dummy ?5184 ?720 155 seg 18 ?2730 1088
pedl9041a-02 oki semiconductor ml9041a-xxa/xxb 57/64 ml9041a-xxacvwa alignment mark specification alignment mark coordinates alignment mark x ( m) y ( m) a ?5100 960 b 5100 960 c 5100 ?840 alignment mark layer metal layers alignment mark specification symbol parameter mark size ( m) a alignment mark width ? 25.2 b alignment mark size ? 100.2 mark a 26.8 mark b 17.1 c distance between mark and internal pattern (min) mark c 87.3 mark a 57.3 mark b 57.3 d distance between mark and adjacent pad metal layer (min) mark c 36.3 mark a 69.1 mark b 69.1 e distance between mark and adjacent pad bump (min) mark c 49.0 a b c x ..................................................................................................... (0,0) y a b a b internal pattern c d e bump metal bump metal
pedl9041a-02 oki semiconductor ml9041a-xxa/xxb 58/64 ml9041a-xxb cvwa pad configuration pad layout y x 175 1 56 55 note: the ml9041a-xxb does not have the dummy pads corresponding to the pad numbers 56 to 62 and 183 to 189 for the ml9041a-xxa. pad coordinates pad symbol x ( m) y ( m) pad symbol x ( m) y ( m) 1v 1 ?5103 ?1100 21 db 3 ?1323 ?1100 2v 2 ?4914 ?1100 22 db 2 ?1134 ?1100 3v 3a ?4725 ?1100 23 db 1 ?945 ?1100 4v 3b ?4536 ?1100 24 db 0 ?756 ?1100 5v 4 ?4347 ?1100 25 e ?567 ?1100 6v 5 ?4158 ?1100 26 r/ w ?378 ?1100 7v 5in ?3969 ?1100 27 rs 0 ?189 ?1100 8v cc ?3780 ?1100 28 rs 1 0 ?1100 9v c ?3591 ?1100 29 so 189 ?1100 10 v ln ?3402 ?1100 30 sl 378 ?1100 11 be ?3213 ?1100 31 sht 567 ?1100 12 v dd ?3024 ?1100 32 cs 756 ?1100 13 csr ?2835 ?1100 33 osc 2 945 ?1100 14 ssr ?2646 ?1100 34 osc r 1134 ?1100 15 s/ p ?2457 ?1100 35 osc 1 1323 ?1100 16 v ss ?2268 ?1100 36 t 3 1512 ?1100 17 db 7 ?2079 ?1100 37 t 2 1701 ?1100 18 db 6 ?1890 ?1100 38 t 1 1890 ?1100 19 db 5 ?1701 ?1100 39 com 1 2079 ?1100 20 db 4 ?1512 ?1100 40 com 2 2268 ?1100 chip size: 10.62 2.55 mm chip thickness: 62520 m bump size (1): 72 72 m (pad no. 1-55) bump size (2): 54 96 m (pad no. 56-175)
pedl9041a-02 oki semiconductor ml9041a-xxa/xxb 59/64 pad symbol x ( m) y ( m) pad symbol x ( m) y ( m) 41 com 3 2457 ?1100 81 seg 85 2898 1088 42 com 4 2646 ?1100 82 seg 84 2814 1088 43 com 5 2835 ?1100 83 seg 83 2730 1088 44 com 6 3024 ?1100 84 seg 82 2646 1088 45 com 7 3213 ?1100 85 seg 81 2562 1088 46 com 8 3402 ?1100 86 seg 80 2478 1088 47 com 9 3591 ?1100 87 seg 79 2394 1088 48 com 10 3780 ?1100 88 seg 78 2310 1088 49 com 11 3969 ?1100 89 seg 77 2226 1088 50 com 12 4158 ?1100 90 seg 76 2142 1088 51 com 13 4347 ?1100 91 seg 75 2058 1088 52 com 14 4536 ?1100 92 seg 74 1974 1088 53 com 15 4725 ?1100 93 seg 73 1890 1088 54 com 16 4914 ?1100 94 seg 72 1806 1088 55 com 17 5103 ?1100 95 seg 71 1722 1088 56 dummy 4998 1088 96 seg 70 1638 1088 57 dummy 4914 1088 97 seg 69 1554 1088 58 dummy 4830 1088 98 seg 68 1470 1088 59 dummy 4746 1088 99 seg 67 1386 1088 60 dummy 4662 1088 100 seg 66 1302 1088 61 dummy 4578 1088 101 seg 65 1218 1088 62 dummy 4494 1088 102 seg 64 1134 1088 63 dummy 4410 1088 103 seg 63 1050 1088 64 dummy 4326 1088 104 seg 62 966 1088 65 dummy 4242 1088 105 seg 61 882 1088 66 seg 100 4158 1088 106 seg 60 798 1088 67 seg 99 4074 1088 107 seg 59 714 1088 68 seg 98 3990 1088 108 seg 58 630 1088 69 seg 97 3906 1088 109 seg 57 546 1088 70 seg 96 3822 1088 110 seg 56 462 1088 71 seg 95 3738 1088 111 seg 55 378 1088 72 seg 94 3654 1088 112 seg 54 294 1088 73 seg 93 3570 1088 113 seg 53 210 1088 74 seg 92 3486 1088 114 seg 52 126 1088 75 seg 91 3402 1088 115 seg 51 42 1088 76 seg 90 3318 1088 116 seg 50 ?42 1088 77 seg 89 3234 1088 117 seg 49 ?126 1088 78 seg 88 3150 1088 118 seg 48 ?210 1088 79 seg 87 3066 1088 119 seg 47 ?294 1088 80 seg 86 2982 1088 120 seg 46 ?378 1088
pedl9041a-02 oki semiconductor ml9041a-xxa/xxb 60/64 pad symbol x ( m) y ( m) pad symbol x ( m) y ( m) 121 seg 45 ?462 1088 149 seg 17 ?2814 1088 122 seg 44 ?546 1088 150 seg 16 ?2898 1088 123 seg 43 ?630 1088 151 seg 15 ?2982 1088 124 seg 42 ?714 1088 152 seg 14 ?3066 1088 125 seg 41 ?798 1088 153 seg 13 ?3150 1088 126 seg 40 ?882 1088 154 seg 12 ?3234 1088 127 seg 39 ?966 1088 155 seg 11 ?3318 1088 128 seg 38 ?1050 1088 156 seg 10 ?3402 1088 129 seg 37 ?1134 1088 157 seg 9 ?3486 1088 130 seg 36 ?1218 1088 158 seg 8 ?3570 1088 131 seg 35 ?1302 1088 159 seg 7 ?3654 1088 132 seg 34 ?1386 1088 160 seg 6 ?3738 1088 133 seg 33 ?1470 1088 161 seg 5 ?3822 1088 134 seg 32 ?1554 1088 162 seg 4 ?3906 1088 135 seg 31 ?1638 1088 163 seg 3 ?3990 1088 136 seg 30 ?1722 1088 164 seg 2 ?4074 1088 137 seg 29 ?1806 1088 165 seg 1 ?4158 1088 138 seg 28 ?1890 1088 166 dummy ?4242 1088 139 seg 27 ?1974 1088 167 dummy ?4326 1088 140 seg 26 ?2058 1088 168 dummy ?4410 1088 141 seg 25 ?2142 1088 169 dummy ?4494 1088 142 seg 24 ?2226 1088 170 dummy ?4578 1088 143 seg 23 ?2310 1088 171 dummy ?4662 1088 144 seg 22 ?2394 1088 172 dummy ?4746 1088 145 seg 21 ?2478 1088 173 dummy ?4830 1088 146 seg 20 ?2562 1088 174 dummy ?4914 1088 147 seg 19 ?2646 1088 175 dummy ?4998 1088 148 seg 18 ?2730 1088
pedl9041a-02 oki semiconductor ml9041a-xxa/xxb 61/64 ml9041a-xxbcvwa alignment mark specification alignment mark coordinates alignment mark x ( m) y ( m) a ?5100 960 b 5100 960 c 5100 ?840 alignment mark layer metal layers alignment mark specification symbol parameter mark size ( m) a alignment mark width ? 25.2 b alignment mark size ? 100.2 mark a 26.8 mark b 17.1 c distance between mark and internal pattern (min) mark c 87.3 mark a 57.3 mark b 57.3 d distance between mark and adjacent pad metal layer (min) mark c 164.7 mark a 69.1 mark b 69.1 e distance between mark and adjacent pad bump (min) mark c 173.7 a b c x y .................................................................................................. (0,0) a b a b internal pattern c d e bump metal bump metal
pedl9041a-02 oki semiconductor ml9041a-xxa/xxb 62/64 ml9041a-xxa/xxbcvwa gold bump specification gold bump specification (unit: m) symbol parameter min typ max a bump pitch (min section: output section) 84 ? ? b bump size (output section: pitch direction) 49 54 59 c bump size (output section: depth direction) 91 96 101 d bump-to-bump distance (output section: pitch direction) 25 30 35 e bump size (input section: pitch direction) 67 72 77 f bump size (input section: depth direction) 67 72 77 g bump-to-bump distance (input section: pitch direction) 112 117 122 h sliding of total bump pitches ? ? 2 bump height 10 15 20 bump height dispersion inside chip (range) ? ? 4 j bump edge height ? ? 5 k shear strength (g) 30 ? ? l bump hardness (hv: 25 g load) 50 90 130 chip size; 10.62 mm 2.55 mm chip thickness; 625 20 m top view and cross section view a be cf df top view cross section view i j i
pedl9041a-02 oki semiconductor ml9041a-xxa/xxb 63/64 revision history page document no. date previous edition current edition description version1 d ec. 2 001 ? ? preli m inary f i rst edi t i on 11 partially changed the content of section ?features?. 55 changed descriptions of symbol be. changed descriptions of symbols v c and v cc . 66 changed description of symbol s/ p . added symbol dummy and descriptions. 88 integrated parameters ? ?h? input voltage 1? and ? ?h? input voltage 2?, and parameters ? ?l? input voltage 1? and ? ?l? input voltage 2?. changed min. value of ? ?l? input voltage? from ?0.3 to 0. changed condition of parameter ?input current 2? from v 1 = v dd to v 1 = gnd. changed a symbol in column ?applicable pin? from cs to cs . 10 10 changed note 6. 12 12 added note. 13 13 added cs ?h? pulse width. 19 19 partially changed section (1) of 1). 20 20 partially changed section (2). 21 21 partially changed section ?arbitrator ram (abram)?. 27 27 changed the figure for adc. 32 32 changed timing diagrams. added note 3. 35 35 partially changed section 3). changed caption 4) from ?display mode setting? to ?display on/off control?. partially changed section (1) of 4). 36 36 partially changed section (3) of 6). 37 37 partially changed section 7), section 8), and section 9). 38 38 partially changed section 11). 40 40 partially changed section 4). pedl9041a-02 mar. 15, 2002 53 53 partially added the content of section 4) in (c).
pedl9041a-02 oki semiconductor ml9041a-xxa/xxb 64/64 notice 1. the information contained herein can change without notice owing to product and/or technical improvements. before using the product, please make sure that the information being referred to is up-to-date. 2. the outline of action and examples for application circuits described herein have been chosen as an explanation for the standard action and performance of the product. when planning to use the product, please ensure that the external conditions are reflected in the actual circuit, assembly, and program designs. 3. when designing your product, please use our product below the specified maximum ratings and within the specified operating ranges including, but not limited to, operating voltage, power dissipation, and operating temperature. 4. oki assumes no responsibility or liability whatsoever for any failure or unusual or unexpected operation resulting from misuse, neglect, improper installation, repair, alteration or accident, improper handling, or unusual physical or electrical stress including, but not limited to, exposure to parameters beyond the specified maximum ratings or operation outside the specified operating range. 5. neither indemnity against nor license of a third party?s industrial and intellectual property right, etc. is granted by us in connection with the use of the product and/or the information and drawings contained herein. no responsibility is assumed by us for any infringement of a third party?s right which may result from the use thereof. 6. the products listed in this document are intended for use in general electronics equipment for commercial applications (e.g., office automation, communication equipment, measurement equipment, consumer electronics, etc.). these products are not authorized for use in any system or application that requires special or enhanced quality and reliability characteristics nor in any system or application where the failure of such system or application may result in the loss or damage of property, or death or injury to humans. such applications include, but are not limited to, traffic and automotive equipment, safety devices, aerospace equipment, nuclear power control, medical equipment, and life-support systems. 7. certain products in this document may need government approval before they can be exported to particular countries. the purchaser assumes the responsibility of determining the legality of export of these products and will take appropriate and necessary steps at their own expense for these. 8. no part of the contents contained herein may be reprinted or reproduced without our prior permission. copyright 2002 oki electric industry co., ltd.

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