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intel ? pxa27x processor family memory subsystem datasheet product features the intel ? pxa27x processor family memory subsystem is a stacked device combining high- performance intel strataflash ? memory die with or without low-power sdram die in intel ? stacked package. the flash memory features 1.8 v low-power operations with flexible multi- partitions, dual operation read-while-write or read-while-erase, asynchronous and synchronous reads up to 52 mhz on 0.13 m etox? viii flash technology. the lpsdram memory features 1.8 v low-power operation up to 104 mhz. the pxa27x processor memory subsystem is stacked on top of intel ? pxa27x processor for an optimized small form-factor package solution for cellular and pda applications. device architecture flash die density: 128-, 256-mbit lpsdram die density: 256-mbit flash + lpdram combo (x16) flash + flash combo (x32) device voltage core: v cc = 1.8 v (typ) i/o: v ccq = 1.8 v (typ) device packaging ball count: 336 balls area: 14x14 mm height: 1.55 mm sdram architecture and performance clock rate: 104 mhz four internal banks burst length: 1, 2, 4, 8, or full page quality and reliability extended temp: C 25 c to +85 c minimum 100 k flash block erase cycle 0.13 m etox ? viii flash technology flash architecture read-while-write or erase asymmetrical blocking structure 8-mbit partition sizes (128-mbit die) 16-mbit partition sizes (256-mbit die) 16-kword parameter blocks (bottom) 64-kword main blocks 2-kbit one-time programmable (otp) protection register zero-latency block locking absolute write protection with block lock down using f-vpp and f-wp# flash performance 85 ns initial access 25 ns async page-mode read 14 ns sync read (t chqv ) 52 mhz clk buffered enhanced factory programming (buffered efp): 5 s/byte (typ) buffered programming at 7 s/byte (typ) flash software intel ? fdi, intel ? psm, and intel ? vfm common flash interface (cfi) basic/extended command set 301855-001 july 2004 notice: this document contains preliminary information on new products in production. the specifications are subject to change without notice. verify with your local intel sales office that you have the latest datasheet before finalizing a design.
2 intel? pxa27x processor family memory subsystem atasheet iformaio i is om is proi i oio i i ? pros. o is xprss or impi sopp or oris o a ia propr ris is ra is om. xp as proi i is rms a oiios of sa for s pros i assms o iaii asor a i isaims a xprss or impi arra rai o sa aor s of i pros ii iaii or arrais rai o fiss for a pariar prpos mraaii or ifrim of a pa opri or or ia propr ri. intel products are not intended for use in medical life savin life sustainin applications. intel may mae chanes to specifications and product descriptions at any time without notice. esiners must not rely on the absence or characteristics of any features or instructions mared reserved or undefined. int el reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arisin from future chanes to them. intel? pxa27x processor family memory subsystem may contain desin defects or errors nown as errata which may cause the product to deviate from published specifications. urrent characteried errata are available on reuest. ontact your local intel sales office to obtain the latest specifications and before placin your product order. opies of documents which have an orderin number and are referenced in this document or other intel literature may be obtaine d by callin 100 5725 or by visitin intels website at httpwww.intel.com. opyriht intel orporation 200. all rights reserved. *other names and brands may be claimed as the property of others.
datasheet intel? pxa27x processor family memory subsystem 3 contents contents part 1: electrical, mechanical, and thermal specifications (emts) ........ 7 1 introduction ............................................................................................................................... 9 1.1 nomenclature ................................................................................................................ .......9 1.2 acronyms .................................................................................................................... ........10 1.3 conventions................................................................................................................. .......10 2 device overview ....................................................................................................................13 2.1 intel strataflash? memory die...........................................................................................13 2.2 device description.......................................................................................................... ....14 2.3 intel? pxa27x processor memory s ubsystem block diagram ..........................................20 3 package information ............................................................................................................23 3.1 package mechanical information........................................................................................23 4 ballout and signal descriptions ......................................................................................27 4.1 ballout diagrams ............................................................................................................ ....27 4.2 signal descriptions ......................................................................................................... ....31 5 maximum ratings and operating conditions ...........................................................35 5.1 absolute maximum ratings ................................................................................................35 5.2 operating conditions ........................................................................................................ ..36 6 electrical specifications .....................................................................................................37 6.1 flash dc current characteristics .......................................................................................37 6.2 flash dc voltage characteristics .......................................................................................38 6.3 lpsdram dc characteristics ...........................................................................................39 7 ac characteristics ................................................................................................................41 7.1 ac test conditions.......................................................................................................... ...41 7.2 flash ac read specifications ............................................................................................42 7.3 flash ac write specifications ............................................................................................47 7.4 flash program and erase characteristics ..........................................................................51 7.5 lpsdram die capacitance ...............................................................................................51 7.6 lpsdram ac characteristics............................................................................................52 8 power and reset specifications .....................................................................................55 8.1 flash power-up and power-down .....................................................................................55 8.2 flash output disable ........................................................................................................ ..55 8.3 flash standby............................................................................................................... ......55 8.4 flash reset................................................................................................................. ........55 8.5 flash power supply decoupling.........................................................................................56 8.6 flash automatic power saving ...........................................................................................57 8.7 lpsdram power-up sequence and initialization ..............................................................57
contents 4 datasheet part 2: flash device operations ............................................................ 59 9 device operations overview ............................................................................................ 61 9.1 flash and lpsdram bus operations................................................................................ 61 9.2 flash bus operations ........................................................................................................ .64 9.3 flash command definitions................................................................................................ 66 10 flash read operations ....................................................................................................... 69 10.1 flash asynchronous page-mode read .............................................................................. 69 10.2 flash synchronous burst-mode read................................................................................ 70 10.2.1 flash burst suspend ............................................................................................. 70 10.3 flash read configuration register..................................................................................... 70 10.3.1 flash read mode .................................................................................................. 71 10.3.2 flash latency count.............................................................................................. 72 10.3.3 flash burst sequence ........................................................................................... 73 10.3.4 flash clock edge................................................................................................... 74 10.3.5 flash burst wrap ................................................................................................... 74 10.3.6 flash burst length................................................................................................. 74 11 flash programming operations ...................................................................................... 75 11.1 flash word programming................................................................................................... 75 11.1.1 flash factory word programming......................................................................... 76 11.2 flash buffered programming.............................................................................................. 76 11.3 flash buffered enhanced factory programming................................................................ 77 11.3.1 flash buffered efp requirements and considerations ........................................ 78 11.3.2 flash buffered efp setup phase.......................................................................... 78 11.3.3 flash buffered efp program/verify phase ........................................................... 78 11.3.4 flash buffered efp exit phase ............................................................................. 79 11.4 flash program suspend ..................................................................................................... 7 9 11.5 flash program resume...................................................................................................... 8 0 11.6 flash program protection ................................................................................................... 80 12 flash erase operations ...................................................................................................... 81 12.1 flash block erase.......................................................................................................... ..... 81 12.2 flash erase suspend ........................................................................................................ .81 12.3 flash erase resume ......................................................................................................... .82 12.4 flash erase protection ..................................................................................................... .. 82 13 flash security modes .......................................................................................................... 83 13.1 flash block locking........................................................................................................ .... 83 13.1.1 flash lock block.................................................................................................... 83 13.1.2 flash unlock block ................................................................................................ 83 13.1.3 flash lock-down block ......................................................................................... 83 13.1.4 flash block lock status ........................................................................................ 84 13.1.5 flash block locking during suspend .................................................................... 84 13.2 flash one-time programmable protection registers ........................................................ 85 13.2.1 flash reading of the protection registers ............................................................ 86 13.2.2 flash programming of the protection registers .................................................... 87 13.2.3 flash locking the protection registers ................................................................. 87
datasheet intel? pxa27x processor family memory subsystem 5 contents 14 flash dual-operation considerations ..........................................................................89 14.1 flash partitioning ......................................................................................................... .......89 14.2 flash read-while-write command sequences .................................................................89 14.2.1 simultaneous flash operation details...................................................................90 14.2.2 flash write to flash asynchronous read transition.............................................90 14.2.3 flash write to flash synchronous read operation transition..............................90 14.2.4 flash write with clock active.................................................................................90 14.2.5 flash read during flash buffered programming ..................................................91 14.3 simultaneous flash operation restrictions........................................................................91 15 special flash read states .................................................................................................93 15.1 flash read status register ................................................................................................9 3 15.1.1 flash clear status register ...................................................................................94 15.2 flash read device identifier............................................................................................... 95 15.3 cfi query .................................................................................................................. .........96 part 3: lpsdram operations ............................................................... 97 16 lsdram register definition .............................................................................................99 16.1 mode register .............................................................................................................. ......99 16.2 lpsdram extended mode register ................................................................................ 100 17 lpsdram command and operation ........................................................................... 101 17.1 lpsdram no operation / lpsdram deselect............................................................... 101 17.2 lpsdram active............................................................................................................. .101 17.3 lpsdram read command ............................................................................................. 101 17.4 lpsdram write command ............................................................................................. 102 17.5 lpsdram power-down ...................................................................................................102 17.6 lpsdram deep power-down .........................................................................................103 17.7 lpsdram clock suspend ............................................................................................... 103 17.8 lpsdram precharge....................................................................................................... 103 17.9 lpsdram auto precharge .............................................................................................. 103 17.10 lpsdram concurrent auto precharge............................................................................ 103 17.11 lpsdram burst terminate.............................................................................................. 110 17.12 lpsdram auto refresh .................................................................................................. 110 17.13 lpsdram self refresh.................................................................................................... 11 1 appendix a flash flowcharts ................................................................................................. 113 appendix b common flash interface .................................................................................. 121 appendix c intel? pxa27x processor memory subsystem ram type id ...........133 appendix d additional information ...................................................................................... 135 appendix e ordering introduction ........................................................................................137
contents 6 datasheet revision history date revision description 07/04 -001 initial product document release.
intel? pxa27x processor family memory subsystem 7 part 1: electrical, mechanical, and thermal specifications (emts)
8 intel? pxa27x processor family memory subsystem
part 1: emts introduction intel? pxa27x processor family memory subsystem 9 introduction 1 this document contains information pertaining to the pxa27x processor memory subsystem products in the intel ? pxa27x processor family. the intel ? pxa27x processor family memory subsystem is a stacked device combining high- performance intel strataflash ? memory die with or without low-power sdram die on intel ? stacked package. the flash memory features 1.8 v low- power operations with flexible multi-partitions, dual operation read-while-write or read-while- erase, asynchronous and synchronous reads up to 52 mhz on 0.13 m etox? viii flash technology. the lpsdram memory features 1.8 v low-power operation up to 104 mhz. the pxa27x processor memory subsystem is stacked on top of intel ? pxa27x processor for an optimized small form-factor package solution for cellular and pda applications. 1.1 nomenclature 1.8 volt core vcc (memory subsystem die core) voltage range of 1.7 v C 1.9 v. 1.8 volt i/o vccq (memory subsystem die i/o) voltage range of 1.7 v C 1.9 v. asserted signal with logical voltage level v il , or enabled. block group of cells, bits, bytes or words within the flash memory array that get erased with one erase instruction. bottom parameter previously referred to as a bottom-boot flash, a device with flash parameter partition located at the lowest physical address of its memory map for processor system boot up. deasserted signal with logical voltage level v ih , or disabled. device a specific memory type or stacked flash + lpsdram memory density configuration combination within a memory subsystem product family. die individual flash or lpsdram die used in a stacked package memory subsystem device. high-z high impedance low-z signal is driven on the bus. main block any 64-kword flash array block. main partition a flash partition containing only main blocks. non-array reads flash reads which return flash device identifier, cfi query, protection register and status register information. parameter block any 16-kword flash array block. parameter partition a flash partition containing parameter and main blocks.
part 1: emts introduction 10 intel? pxa27x processor family memory subsystem partition a group of flash blocks that shares common status register read state. program an operation to write data to the flash array or lpsdram. write bus cycle operation at the inputs of the flash or lpsdram die, in which a command or data are sent to the flash array or lpsdram. 1.2 acronyms aps automatic power savings buffered efp buffered enhanced factory programming cfi common flash interface csp chip scale package cui command user interface mlc technology multi-level cell technology otp one-time programmable plr protection lock register pr protection register rcr read configuration register rfu reserved for future use (unused active signals in a package ballout) rww / rwe read-while-write / read-while-erase sr status register wsm write state machine 1.3 conventions a5 denotes one element of a signal group, in this case address bit 5. bit binary unit, valid range [0,1]. byte eight bits, valid range [0x00 - 0xff]. clear logical zero (0). dq[15:0] denotes a group of similarly named signals, such as data bus. f-ce# denotes chip enable of flash die, where f to denote flash specific signal suffix and ce# is the root signal name of the flash die. d to denote lpsdram type signal.
part 1: emts introduction intel pxa27x processor family memory subsystem 11 gbit 1,073,741,824 bits. kbit 1024 bits. kbyte 1024 bytes (8,192 bits). kword 1024 words (16,384 bits). mbit 1,048,576 bits. mbyte 1,048,576 bytes (8,388,608 bits). 0x hexadecimal number prefix. 0b binary number prefix. set logical one (1). sr.4 a flash status register bit, in this case status register bit 4 of sr[7:0]. vcc signal or voltage connection. v cc signal or voltage level. vss denotes a global power signal of the stacked device, vss is common to all memory dies within a stacked memory device. word two bytes or sixteen bits, valid range [0 x0000 - 0xffff].
part 1: emts introduction 12 intel? pxa27x processor family memory subsystem
part 1: emts device overview intel pxa27x processor family memory subsystem 13 device overview 2 the pxa27x processor memory subsystem device combines 128- or 256-mbit intel strataflash ? memory die with or without 256-mbit low-power sdram die on intel stacked package. the following section describes the pxa27x processor memory subsystem features, operation, and characteristics of the flash and lpsdram devices. 2.1 intel strataflash ? memory die the flash die provides read-while-write or read-while-erase capability with density upgrades of 256-mbit increments. the flash die provides high-performance at low voltage on a 16-bit data bus and individually erasable memory blocks sized for optimum code and data storage. the flash die contains one parameter partition and several main partitions. the flash memory arrays are grouped into multiple 8-mbit partition for 128-mbit flash die, or 16-mbit partitions for 256-mbit flash die. by dividing the flash memory into partitions, program or erase operations can take place simultaneously as read operation. although each partition has write, erase, and burst read capabilities, simultaneous operations are limited to write or erase in one partition while reading in the another partition. burst reads across partition boundaries are allow, but the burst reads are not allow to cross into a partition that is busy in programming or erasing mode, or across flash dies within the pxa27x processor memory subsystem. a new burst read operation must be initiated when crossing these bondaries. upon initial power up or return from reset, the flash defaults to asynchronous page-mode read. configuring the read configura tion register (rcr) enables flash synchronous burst-mode reads. in synchronous burst-mode, output data are synchronized with the memory bus clock signal. in addition to the enhanced architecture and interface, the flash die incorporates technology that enables fast factory program and erase operations . designed for low-voltage systems, the flash supports read operations with f-vcc at 1.8 volt, and erase and program operations with f-vpp at 1.8 v or 9.0 v. buffered enhanced factory programming (buffered efp) provides the fastest flash array programming performance with f-vpp at 9.0 volt, which increases factory throughput. with f-vpp at 1.8 v, f-v cc and f-vpp can be tied together for a simple, ultra-low power design. in addition to voltage flexibility, a dedicated f-vpp connection provides complete data protection when f-vpp is less than v pplk . a flash command user interface (cui) is the interface between the pxa27x processor and all internal operations of each selected flash die. an internal flash write state machine (wsm) automatically executes, for example, the algorithms and timings necessary for block erase and program. a status register indicates erase or program completion and any errors that may have occurred. an industry-standard flash command sequence invokes program and erase automation. each erase operation erases one block at a time. the erase suspend feature allows system interrupt to pause an erase cycle to read or program data in another block in another partition. program suspend allows system interrupt to pause programming to read other locations. the flash array is programmed in 16-bits increments.
part 1: emts device overview 14 intel? pxa27x processor family memory subsystem the flash offers power savings through automatic power savings (aps) mode and standby mode. the individual flash die automatically enters aps mode following read-cycle completion. standby is initiated when the pxa27x processor deselects the flash by deasserting f-ce# or by asserting f- rst#. combined, these features can significantly reduce power consumption. for security requirement, each flash die features 2048-bits of one-time protection (otp) register allows unique flash identification that can be used to increase system security. in addition, the individual flexible block lock feature provide s zero-latency block locking and unlocking. 2.2 device description the pxa27x processor memory subsystem device combines high-performance intel strataflash ? memory die with low-power sdram die for 16-bit and intel strataflash ? memory only dies for 32-bit operations on intel stacked package. table 1, ?pxa27x processor memory subsystem signals for 16-bit interface? and table 2, ?pxa27x processor memory subsystem signals for 32- bit interface? on page 17 provide the signal relationships between the intel ? pxa27x processor device (bottom package) signal names with the pxa27x processor memory subsystem (top package) device respectively for x16 or x32 bit interfaces. table 1. intel? pxa27x processor memory subsystem signals for 16-bit interface (sheet 1 of 4) ball# type ball name sdram flash pxa27x w18 input dqm<0> d-dm[1] ? dqm<0> p17 input dqm<1> d-dm[0] ? dqm<1> t17 input dqm<2> ? ? dqm<2> w17 input dqm<3> ? ? dqm<3> w1 input ncs<0> ? f-ce# ncs<0> v18 input nsdcs<0> d-cs# ? nsdcs<0> w20 input nwe we# we# nwe w19 input noe ? oe# noe u20 input nsdcas d-cas# adv# nsdcas y19 input nsdras d-ras# ? nsdras v19 input sdclk<3> ? f-clk sdclk<3> p19 input sdclk<1> r-clk ? sdclk<1> t18 input sdcke d-cke ? sdcke w15 input nf_wp<0> ? f-wp# ? n6 bidirectional md<15> dq0 dq15 md<15> m6 bidirectional md<14> dq1 dq14 md<14> r8 bidirectional md<13> dq3 dq13 md<13> r9 bidirectional md<12> dq2 dq12 md<12> r10 bidirectional md<11> dq5 dq11 md<11> t11 bidirectional md<10> dq4 dq10 md<10> t12 bidirectional md<9> dq7 dq9 md<9> r14 bidirectional md<8> dq6 dq8 md<8>
part 1: emts device overview intel? pxa27x processor family memory subsystem 15 v13 bidirectional md<7> dq9 dq7 md<7> t14 bidirectional md<6> dq8 dq6 md<6> m15 bidirectional md<5> dq11 dq5 md<5> m16 bidirectional md<4> dq10 dq4 md<4> v15 bidirectional md<3> dq13 dq3 md<3> p16 bidirectional md<2> dq12 dq2 md<2> m17 bidirectional md<1> dq15 dq1 md<1> u17 bidirectional md<0> dq14 dq0 md<0> v2 input ma<25> ? ? ma<25> w2 input ma<24> d-ba1 a23 ma<24> w4 input ma<23> d-ba0 a22 ma<23> y4 input ma<22> ? a21 ma<22> w5 input ma<21> ? a20 ma<21> t4 input ma<20> ? a19 ma<20> r4 input ma<19> ? a18 ma<19> p2 input ma<18> ? a17 ma<18> w6 input ma<17> ? a16 ma<17> t5 input ma<16> ? a15 ma<16> r5 input ma<15> ? a14 ma<15> v6 input ma<14> ? a13 ma<14> u6 input ma<13> a12 a12 ma<13> t6 input ma<12> a11 a11 ma<12> w7 input ma<11> a10 a10 ma<11> p4 input ma<10> a9 a9 ma<10> p5 input ma<9> a8 a8 ma<9> t7 input ma<8> a7 a7 ma<8> r6 input ma<7> a6 a6 ma<7> n5 input ma<6> a5 a5 ma<6> w8 input ma<5> a4 a4 ma<5> r7 input ma<4> a3 a3 ma<4> p6 input ma<3> a2 a2 ma<3> t8 input ma<2> a1 a1 ma<2> y3 input ma<1> a0 a0 2 ma<1> w3 input ma<0> ? ? ma<0> y8 input nf_rst ? f-rst# ? w10 supply f_vpp ? f-vpp ? table 1. intel? pxa27x processor memory subsystem signals for 16-bit interface (sheet 2 of 4) ball# type ball name sdram flash pxa27x
part 1: emts device overview 16 intel? pxa27x processor family memory subsystem n1/ t2/ v5/ v7/ v8/ v9/ v10/ v11/ v12/ v14/ v16/ v17/ r19/ n20/ p20/ r1/ y6/ y7/ y10/ y11/ y12/ y13/ y16/ y20/ pxa27x processor memory subsystem core supply vcc_mem d-vcc f-vcc vcc_mem u19/ y2/ n2/ n18/ p18/ t1/ u5/ u7/ u8/ u9/ u10/ u11/ u12/ u14/ u16/ w11/ y5/ y9/ y17 pxa27x processor memory subsystem i/o supply vss_mem vssq vssq vss_mem a18/ a19/ a20/ b20/ c20/ c15/ d19 supply vss vss vss vss table 1. intel? pxa27x processor memory subsystem signals for 16-bit interface (sheet 3 of 4) ball# type ball name sdram flash pxa27x
part 1: emts device overview intel? pxa27x processor family memory subsystem 17 w9/ w12/ w13/ w16/ y15/ y18 rfu rfu ? ? ? y14 input nf_wp<1> 1 ??? notes: 1. nf_wp<1> is reserved for a stacked data-core flash memory write protect pin (not yet available in current pxa27x processor configurations), in the top package. 2. address signals are shifted by one for 16-bit flash to align the pxa27x processor memory subsystem with the processor and system design requirements. table 2. intel? pxa27x processor memory subsystem signals for 32-bit interface (sheet 1 of 4) ball# type ball name flash die #1 flash die #2 pxa27x w1 input ncs<0> f-ce# f-ce# ncs<0> w20 input nwe we# we# nwe w19 input noe oe# oe# noe u20 input nsdcas adv# adv# nsdcas v19 input sdclk<3> f-clk f-clk sdclk<3> w15 input nf_wp<0> f-wp# f-wp# ? m5 bidirectional md<31> ? dq15 md<31> l5 bidirectional md<30> ? dq14 md<30> l6 bidirectional md<29> ? dq13 md<29> t9 bidirectional md<28> ? dq12 md<28> t10 bidirectional md<27> ? dq11 md<27> r11 bidirectional md<26> ? dq10 md<26> r12 bidirectional md<25> ? dq9 md<25> u13 bidirectional md<24> ? dq8 md<24> p15 bidirectional md<23> ? dq7 md<23> r15 bidirectional md<22> ? dq6 md<22> n15 bidirectional md<21> ? dq5 md<21> w14 bidirectional md<20> ? dq4 md<20> u15 bidirectional md<19> ? dq3 md<19> t16 bidirectional md<18> ? dq2 md<18> n16 bidirectional md<17> ? dq1 md<17> n17 bidirectional md<16> ? dq0 md<16> n6 bidirectional md<15> dq15 ? md<15> m6 bidirectional md<14> dq14 ? md<14> r8 bidirectional md<13> dq13 ? md<13> r9 bidirectional md<12> dq12 ? md<12> table 1. intel? pxa27x processor memory subsystem signals for 16-bit interface (sheet 4 of 4) ball# type ball name sdram flash pxa27x
part 1: emts device overview 18 intel? pxa27x processor family memory subsystem r10 bidirectional md<11> dq11 ? md<11> t11 bidirectional md<10> dq10 ? md<10> t12 bidirectional md<9> dq9 ? md<9> r14 bidirectional md<8> dq8 ? md<8> v13 bidirectional md<7> dq7 ? md<7> t14 bidirectional md<6> dq6 ? md<6> m15 bidirectional md<5> dq5 ? md<5> m16 bidirectional md<4> dq4 ? md<4> v15 bidirectional md<3> dq3 ? md<3> p16 bidirectional md<2> dq2 ? md<2> m17 bidirectional md<1> dq1 ? md<1> u17 bidirectional md<0> dq0 ? md<0> v2 input ma<25> a23 a23 ma<25> w2 input ma<24> a22 a22 ma<24> w4 input ma<23> a21 a21 ma<23> y4 input ma<22> a20 a20 ma<22> w5 input ma<21> a19 a19 ma<21> t4 input ma<20> a18 a18 ma<20> r4 input ma<19> a17 a17 ma<19> p2 input ma<18> a16 a16 ma<18> w6 input ma<17> a15 a15 ma<17> t5 input ma<16> a14 a14 ma<16> r5 input ma<15> a13 a13 ma<15> v6 input ma<14> a12 a12 ma<14> u6 input ma<13> a11 a11 ma<13> t6 input ma<12> a10 a10 ma<12> w7 input ma<11> a9 a9 ma<11> p4 input ma<10> a8 a8 ma<10> p5 input ma<9> a7 a7 ma<9> t7 input ma<8> a6 a6 ma<8> r6 input ma<7> a5 a5 ma<7> n5 input ma<6> a4 a4 ma<6> w8 input ma<5> a3 a3 ma<5> r7 input ma<4> a2 a2 ma<4> p6 input ma<3> a1 a1 ma<3> t8 input ma<2> a0 2 a0 2 ma<2> y3 input ma<1> ? ? ma<1> w3 input ma<0> ? ? ma<0> table 2. intel? pxa27x processor memory subsystem signals for 32-bit interface (sheet 2 of 4) ball# type ball name flash die #1 flash die #2 pxa27x
part 1: emts device overview intel? pxa27x processor family memory subsystem 19 y8 input nf_rst f-rst# f-rst# ? w10 supply f_vpp f-vpp f-vpp ? n1/ t2/ v5/ v7/ v8/ v9/ v10/ v11/ v12/ v14/ v16/ v17/ r19/ n20/ p20/ r1/ y6/ y7/ y10/ y11/ y12/ y13/ y16/ y20/ pxa27x processor memory subsystem core supply vcc_mem d-vcc f-vcc vcc_mem u19/ y2/ n2/ n18/ p18/ t1/ u5/ u7/ u8/ u9/ u10/ u11/ u12/ u14/ u16/ w11/ y5/ y9/ y17 pxa27x processor memory subsystem i/o supply vss_mem vssq vssq vss_mem a18/ a19/ a20/ b20/ c20/ c15/ d19 supply vss vss vss vss table 2. intel? pxa27x processor memory subsystem signals for 32-bit interface (sheet 3 of 4) ball# type ball name flash die #1 flash die #2 pxa27x
part 1: emts device overview 20 intel? pxa27x processor family memory subsystem 2.3 intel ? pxa27x processor memory subsystem block diagram note: pxa271 = pxa27x cpu + 256-mbit flash + 256-mbit lpsdram (x16 configuration) device w9/ w12/ w13/ w16/ y15/ y18 rfu rfu ? ? ? y14 input nf_wp<1> 1 ??? notes: 1. nf_wp<1> is reserved for a stacked data-core flash memory write protect pin (not yet available in current pxa27x processor configurations), in the top package. 2. address signals in the stacked datasheet are shifted by two for 32-bit flash to align the pxa27x processor memory subsystem with the processor and system design requirements. figure 1. intel ? pxa27x processor memory subsystem (x16) device block diagram 1 table 2. intel? pxa27x processor memory subsystem signals for 32-bit interface (sheet 4 of 4) ball# type ball name flash die #1 flash die #2 pxa27x sdclk0 ma[24:1] md[15:0] ncs0 nwe noe intel ? pxa27x processor note: connections shown for x16 operation. nsdcas sdcke1 sdclk1 dqm[1:0] nsdcs0 nsdras nreset_out lpsdram 256-mbit intel strataflash ? memory 256-mbit d-ras# adv# f-ce# oe# we# f-clk a[23:0] r-clk d-cke d-cas# d-dm[1:0] d-cs# d-ba[1:0] f-rst# dq[15:0] memory subsystem
part 1: emts device overview intel pxa27x processor family memory subsystem 21 notes: 1. pxa272 = pxa27x cpu + 128-mbit flash + 128-mbit flash (x32 configuration) device. 2. pxa273 = pxa27x cpu + 256-mbit flash + 256-mbit flash (x32 configuration) device. figure 2. intel ? pxa27x processor memory subsystem (x32) device block diagram 1,2 sdclk0 ma[25:2] md[31:0] ncs0 nwe noe intel ? pxa27x processor (x32) note: connections shown for x32 operation. nsdcas nreset_out intel strataflash ? memory die #2 128 or 256-mbit intel strataflash ? memory die #1 128 or 256-mbit dq[31:0] adv# f-ce# oe# we# f-clk a[23:0] f-rst#
part 1: emts device overview 22 intel? pxa27x processor family memory subsystem
part 1: emts package information intel pxa27x processor family memory subsystem 23 package information 3 this section provides the package mechanical specifications for the intel ? pxa27x processor with pxa27x processor memory subsystem device. the intel ? pxa27x processor with pxa27x processor memory subsystem device is provided in a 14 mm x 14 mm, 336-pin, 0.650 mm fs-csp molded matrix array package, as shown in figure 3 , figure 4 , and table 3, intel? pxa27x processor with memory subsystem dimensions on page 24 . 3.1 package mechanical information figure 3. intel ? pxa27x processor with memory subsystem mechanical details - top view top view - bottom package ball side down complete ink mark not shown a b c d e f g h j k l m n p r t u v w y 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 d e g f ball a1 corner
part 1: emts package information 24 intel? pxa27x processor family memory subsystem figure 4. intel ? pxa27x processor with memory subsystem mechanical details - side view table 3. intel ? pxa27x processor with memory subsystem dimensions dimension symbol min typical max pacakge height a 1.55 ball height a1 0.180 package body thickness a2 1.121 1.195 ball (lead) width b 0.350 0.4 0.450 bottom package body width d 13.9 14 14.1 bottom package body length e 13.9 14 14.1 top package body width f 10.9 11 11.1 top package body length g 12.9 13 13.1 pitch [e] 0.650 ball (lead) count n 336 seating plane coplanarity y 0.150 corner to ball a1 distance along d s1 0.825 corner to ball a1 distance along e s2 0.825 note: all mechanical dimensions are in milimeters (mm). seating plane a a2 a1 y
part 1: emts package information intel pxa27x processor family memory subsystem 25 figure 5. intel ? pxa27x processor with memory subsystem package marking level 1 name fpo # intel legal i pxa271fc0416 mcp fpo# intel m c 03 alt# flash pkg philippines alt top pkg. coo level 1 name fpo # intel legal i pxa271fc0416 mcp fpo# intel m c 03 alt# flash pkg philippines alt top pkg. coo
part 1: emts package information 26 intel? pxa27x processor family memory subsystem
part 1: emts ballout and signal descriptions intel pxa27x processor family memory subsystem 27 ballout and signal descriptions 4 this section provides the ballout diagra ms and signal descriptions for the intel ? pxa27x processor with memory subsystem device. 4.1 ballout diagrams figure 6. intel ? pxa27x processor with memory subsystem ball map, top left quarter 12345678910 a vcc_usb vcc_usb gpio<89> gpio<42> usbh_n<1> usbh_p<1> gpio<90> gpio<61> gpio<65> gpio<71> b gpio<118> gpio<119> gpio<88> gpio<43> gpio<115> uio vcc_core vcc_lcd vcc_core gpio<70> c vss_core usbc_n gpio<120> gpio< 116> gpio<114> vcc_usim gpio<91> gpio<63> gpio<64> gpio<69> d vcc_usb usbc_p gpio<44> gpio<39> gpio<41> vss_io gpio<58> gpio<59> vss_io gpio<68> e vcc_core gpio<117> gpio<35> vss_io gpio<109> gpio<1 6> vss_core gpio<62> gpio<66> vss_core f gpio<45> gpio<34> gpio<32> gpio<110> gpio<111> gpio<25> gpio<22> gpio <60> vss_core gpio<67> g gpio<112> gpio<92> gpio<17> gpio<36> gpio<37> gpio<30> h gpio<23> gpio<24> gpio<26> gpio<27> gpio<38> gpio<46> j vcc_io vss_io gpio<40> gpio<31> vss_core gpio<11> k gpio<28> gpio<29> vcc_core gpio<113> gpio<47> vss_core
part 1: emts ballout and signal descriptions 28 intel? pxa27x processor family memory subsystem figure 7. intel ? pxa27x processor with memory subsystem ball map, top right quarter 11 12 13 14 15 16 17 18 19 20 vcc_lcd vcc_core testclk gpio<9> gpio<0> nreset txtal_out vss vss vss a vcc_core gpio<14> vss_io tdi gpio<4> pwr_en txtal_in boot_sel nreset_o ut vss b gpio<86> gpio<75> tms ntrst vss gpio<3> nvdd_faul t nbatt_fau lt pwr_cap< 0> vss c gpio<87> gpio<76> gpio<77> tdo gpio<10> gpio<1> sys_en pwr_cap< 1> vss pwr_out d gpio<72> vss_io gpio<74> tck clk_req pwr_cap< 3> vcc_batt pwr_cap< 2> pxtal_in pxtal_out e vss_core gpio<73> vss_core gpio<19> gpio<97> gpio<94> gpio<96> vcc_pll vss_pll vss_io f vss_io gpio<100> gpio<99> gpio<98> gpio<93> gpio<95> g vss_core gpio<106> gpio<104> gpio<101> gpio<102> vcc_io h gpio<51> gpio<108> gpio<107> gpio<105> vcc_core gpio<103> j gpio<81> vss_bb gpio<50> gpio<52> gpio<53> gpio<54> k
part 1: emts ballout and signal descriptions intel pxa27x processor family memory subsystem 29 figure 8. intel ? pxa27x processor with memory subsystem ball map, bottom left quarter l vcc_io vss_io gpio<12> gpio<13> md<30> md<29> m gpio<49> gpio<18> vcc_sram rdnwr md<31> md<14> n vcc_mem vss_mem vcc_sram vss_core ma<6> md<15> p gpio<80> ma<18> gpio<79> ma<10> ma<9> ma<3> r vcc_mem vcc_core vcc_sram ma<19> ma<15> ma<7> ma<4> md<13> md<12> md<11> t vss_mem vcc_mem gpio<33> ma<20> ma<16> ma<12> ma<8> ma<2> md<28> md<27> u vcc_core vss_core vcc_sram vss_core vss_mem ma<13> vss_mem vss_mem vss_mem vss_mem v gpio<15> ma<25> vss_core gpio<78> vcc_mem ma<14> vcc_mem vcc_mem vcc_mem vcc_mem w ncs<0> ma<24> ma<0> ma<23> ma<21> ma<17> ma<11> ma<5> rfu f_vpp y vss_core vss_mem ma<1> ma<22> vss_mem vcc_mem vcc_mem nf_rst vss_mem vcc_mem 12345678910
part 1: emts ballout and signal descriptions 30 intel? pxa27x processor family memory subsystem figure 9. intel ? pxa27x processor with memory subsystem ball map, bottom right quarter note: rfu means reserved for future use. please contact your local intel representative for recommendations on what pcb designers can do with the rfus. gpio<85> gpio<55> gpio<57> gpio<48> vcc_core vcc_bb l md<5> md<4> md<1> gpio<56> gpio<83> gpio<84> m md<21> md<17> md<16> vss_mem gpio<82> vcc_mem n md<23> md<2> dqm<1> vss_mem sdclk<1> vcc_mem p md<26> md<25> vss_core md<8> md<22> vss_core nsdcs<1> gpio<21> vcc_mem vcc_core r md<10> md<9> vcc_core md<6> vcc_core md<18> dqm<2> sdcke sdclk<2> gpio<20> t vss_mem vss_mem md<24> vss_mem md<19> vss_mem md<0> vss_core vss_mem nsdcas u vcc_mem vcc_mem md<7> vcc_mem md<3> vcc_mem vcc_mem nsdcs<0> sdclk<3> sdclk<0> v vss_mem rfu rfu md<20> nf_wp<0> rfu dqm<3> dqm<0> noe nwe w vcc_mem vcc_mem vcc_mem nf_wp<1> rfu vcc_mem vss_mem rfu nsdras vcc_mem y 11 12 13 14 15 16 17 18 19 20
part 1: emts ballout and signal descriptions intel? pxa27x processor family memory subsystem 31 4.2 signal descriptions table 4 describes the active signals for the pxa27x processor memory subsystem. table 4. intel? pxa27x processor memory subsystem signal descriptions (s heet 1 of 3) symbol type name and function a[max:min] input address: global device signals. share inputs for all memory die addresses during read and write operations. for 16-bit bus operations, a[24:1] signal balls are used, while 32-bit bus operations, a[25:2] are used. this is due to the pxa27x processor addresses shift as compare to the flash and lpsdram die. flash die addressability: a[23:0] for 256-mbit die; a[22:0] for 128-mbit die. for 256-mbit lpsdram die: a[13:1] are the row and a[9:1] are the column addresses. ? lpsdram address inputs also provide the op-code during a mode register set or special mode register set command. ? a11 defines the auto precharge. during a lpsdram precharge command, a11 is sampled to determine if all banks are to be precharged (a11 = high). dq[max:0] input/ output data input/outputs: global device signals. inputs data and commands during write cycles, outputs data during read cycles. data signals float when the device or its output are deselected. data are internally latched during writes on the device. ? dq[15:0] are used for 16-bit bus operations. ? dq[31:0] are used for 32-bit bus operations. adv# input address valid: low-true input. during synchronous flash read operations, addresses are latched on the rising edge of adv#, or on the next valid f-clk edge, whichever occurs first. in asynchronous flash read operation, addresses are latched on the rising edge adv#, or are continuously flow-through when adv# is kept asserted. f-ce# input flash chip enable: low-true input. f-ce# low selects the associated flash memory die. f-ce# high deselects the associated flash die. when deasserted, the associated flash die is deselected, power is reduced to standby levels, data outputs are placed in high-z state. f-clk, r-clk input clock: synchronizes the selected memory die to the pxa27x memory bus clock in synchronous operations. ? f-clk is a flash signal. synchronizes the flash die to the pxa27x memory bus frequency in synchronous operations. ? r-clk is a lpsdram input signal. synchronizes the lpsdram die to the pxa27x memory bus clock. lpsdram is sampled on the positive edge of r-clk. r-clk also increments the internal burst counter and controls the output registers. oe# input output enable: low-true input. oe# low enables the output drivers of the selected flash die. oe# high places the flash output drivers of the selected die in high-z. f-rst# input flash reset: low-true input. f-rst# low resets internal operations and inhibits write operations. f-rst# high enables normal operation. exit from reset places the flash device in asynchronous read array mode. wait output device wait: flash die configurable low-true or high-true output. indicates data is valid in synchronous array or non-array sync flash reads. configuration register bit 10 (cr.10, wt) determines its polarity when asserted. with f-ce# and oe# at v il , wait?s active output is v ol or v oh . wait is high-z if f-ce# or oe# is v ih . ? in synchronous array or non-array flash read modes, wait indicates invalid data when asserted and valid data when deasserted. ? in asynchronous flash page read, and all flash write modes, wait is deasserted.
part 1: emts ballout and signal descriptions 32 intel? pxa27x processor family memory subsystem we# input write enable: global device signal. low-true input. ? for flash operation, we# low selects the associated memory die for write operation. we# high deselect the associated memory die, data are placed in high-z state. ? for lpsdram operation, we# is latched on the positive clock edge in conjunction with the d-ras# and d-cas# signals. the we# input is used to select the bank activate or precharge command and read or write command. f-wp# input flash write protect: low-true input. f-wp# low enables the lock-down flash mechanism. blocks in a lock-down state cannot be unlocked with the unlock command. f-wp# high overrides the lock-down function, enabling locked-down blocks to be unlocked with the unlock command. d-cke input lpsdram clock enable: high-true input ? d-cke low synchronously with clock, the internal clock is suspended from the next clock cycle. ? the state of the outputs and the burst address is halted. when all banks are in the idle state, d- cke is high, the lpdram enters into power-down and self refresh modes. ? d-cke is synchronous except after the device enters power-down and self refresh modes, where d-cke becomes asynchronous until exiting the same mode. the input buffers, including r-clk, are disabled during power-down and self refresh modes, providing low standby power. d-ba[1:0] input lpsdram bank select: low-true input. d-ba0 and d-ba1 defines to which bank the bank activate, read, write, or bank pre-charge command is being applied. the bank address d-ba0 and d-ba1 are used to latched in mode register set. d-ras# input lpsdram row address strobe: low-true input. ? the d-ras# signal defines the operation commands, with the d-cas# and we# signals. ? the d-ras# is latched at the rising edges of r-clk. when d-ras# and d-cs# are asserted and d-cas# is deasserted, either the bank activate command or the precharge command is selected by the we# signal. ? we# is deasserted, the bank activate command is selected and the bank designated by d-ba[1:0] is turned on to the active state. d-cas# input lpsdram column address strobe: low-true input. ? d-cas# signal defines the operation commands in conjunction with the d-ras# and we# signals and is latched at the rising edges of r-clk. ? d-ras# is deasserted and d-cs# is asserted, the column access is started by asserting d-cas#. read or write command then is selected by asserting we# low or high. d-cs# input lpsdram chip select: low-true input. d-cs# low selects the associated lpsdram memory die. all commands are masked when d-cs# high. d-cs# provides for external bank selection on systems with multiple banks. it is considered part of the command code. d-dm[1:0] input lpsdram data input/output mask: data input mask. ? d-dm[1:0] are byte selects. input data is masked when d-dm[1:0] are sampled high during a write cycle. d-dm1 masks dq[15-8], and d-dm0 masks dq[7-0]. ? the d-dm[1:0] latency for read is 2 clocks and for write is 0 clocks. f-vpp power flash erase/ program voltage: flash specific signal. valid f-vpp voltage on this ball allows flash block erase or program functions. flash memory array contents cannot be altered when f-vpp v pplk . flash block erase and program at invalid f-vpp voltage should not be attempted. f-vcc power flash core voltage level: flash specific signals. flash core source voltage. ? flash operations are inhibited when f-v cc v lko . operations at invalid f-vcc voltage should not be attempted. table 4. intel? pxa27x processor memory subsystem signal descriptions (sheet 2 of 3) symbol type name and function
part 1: emts ballout and signal descriptions intel? pxa27x processor family memory subsystem 33 vccq power output voltage level: global device signals. device input/output-driver source voltage within its operatng voltage range. d-vcc power lpsdram power supply: supplies power to the lpsdram die. ? d-vcc supplies power for lpsdram operation. f-vcc power flash power supply: supplies power to the flash die. ? f-vcc supplies power for flash operation. vss 1 power ground: global ground reference for device memory core type voltages. du - do not use: this ball must be left floating. this ball should not be connected to any power supplies, signals, or other balls. rfu 2 - reserved for future use: reserved by intel for future device functionality and enhancements. notes: 1. connect all vss to system ground. do not float any vss connections. 2. please contact your local intel representative for details. table 4. intel? pxa27x processor memory subsystem signal descriptions (s heet 3 of 3) symbol type name and function
part 1: emts ballout and signal descriptions 34 intel? pxa27x processor family memory subsystem
part 1: emts maximum ratings and operating conditions intel? pxa27x processor family memory subsystem 35 maximum ratings and operating conditions 5 5.1 absolute maximum ratings warning: stressing the device beyond the ?absolute maximum ratings? may cause permanent damage. these are stress ratings only. see table 5 . table 5. intel? pxa27x processor memory subsystem absolute maximum ratings parameter min max unit notes case temperature under bias ?25 +85 c storage temperature ?55 +125 voltage on any flash signals (except f-v cc , f-vpp) relative to vss ?0.5 +3.8 v 1 voltage on any lpsdram signals ?0.5 +2.6 1 f-vpp voltage ?0.2 +10 1,2 f-v cc and d-vcc voltage ?0.2 +2.45 1 vccq voltage ?0.2 +2.45 1 flash output short circuit current ? 100 ma 3 lpsdram output short circuit current ? 50 notes: 1. all specified voltages are relative to vss. minimum dc voltage is ?0.5 v on input/output pins and ?0.2 v on f-vcc, d-vcc, and f-vpp pins. during transitions, this level may undershoot to ?2.5 v for periods < 5 ns which, during transitions, may overshoot to f-v cc + 1.5 v and d-v cc + 1.5 v for periods < 5 ns. 2. maximum dc voltage on f-vpp may overshoot to +9.0 v for periods < 20 ns. 3. output shorted for no more than one second. no more than one output shorted at a time.
part 1: emts maximum ratings and operating conditions 36 intel? pxa27x processor family memory subsystem 5.2 operating conditions warning: operation beyond the operating conditions is not recommended and extended exposure beyond the operating conditions may adversely affect device reliability. note: f-v pp program voltage is normally v ppl . maximum f-v pp can be f-v pph 0.5 v for 1000 cycles on the main blocks and 2500 cycles on the parameter blocks during flash program or erase. table 6. memory subsystem operating conditions symbol parameter condition min max unit t c case operating temperature C25 +85 c f-v cc flash supply core voltage 1.7 2.0 v d-v cc lpsdram supply core voltage 1.7 1.9 v ccq i/o supply voltage option 1.71 1.9 v ppl flash progarmming voltage supply (logic level) 0.9 2.0 v pph 1 flash factory programming (elevated voltage) 8.5 9.5 t pph maximum hours at elevated voltage f-v pp = v pph 80hours flash block erase cycles flash main and parameter blocks f-v pp = f-v cc 100,000 cycles flash main blocks f-v pp = v pph 1000 flash parameter blocks f-v pp =v pph 2500
part 1: emts electrical specifications intel pxa27x processor family memory subsystem 37 electrical specifications 6 note: the pxa27x processor memory subsystem device power is the sum of all active and non-active die currents. 6.1 flash dc current characteristics the flash dc current characteristics shown in table 7 are for the individual flash die within the pxa27x processor memory subsystem device. table 7. flash dc current characteristics (sheet 1 of 2) sym parameter typ max unit test conditions notes i li input load current C 1 a f-v cc = f-v cc max v ccq = v ccq max v in = v ccq or v ss 1 i lo output leakage current C 1 a f-v cc = f-v cc max v ccq = v ccq max v in = v ih or v il 1 i ccs standby 50 110 a f-v cc = f-v cc max v ccq = v ccq max f-ce# = v ih f-rst# = v ih f-wp# = v ih 1,2 i ccaps automatic power saving (aps) 50 110 a f-v cc = f-v cc max v ccq = v ccq max f-ce# = v ih f-rst# = v ih 1,2 i ccr asynchronous single-word ?f = 5 mhz (1 f-clk) 13 15 ma 1-word read f-v cc = f-v cc max f-ce# = v il oe# = v ih inputs: v il or v ih 1 page-mode read ? f = 13 mhz (5 f-clk) 8 9 ma 4-word read 1 i ccr synchronous burst read ? f = 52 mhz, lc = 4 18 22 ma burst length = 8 f-v cc = f-v cc max f-ce# = v il oe# = v ih inputs: v il or v ih 1 21 25 ma burst length = 16 i ccw, i cce ? f-vpp program current, ? f-vpp erase current 35 50 ma f-v pp = v ppl , program/erase in progress 1,3,4,7 25 32 ma f-v pp = v pph , program/erase in progress 1,3,5,7 i ccws, i cces ? f-vpp program suspend current, ? f-vpp erase suspend current 50 110 a f-ce# = v il , suspend in progress 1,6,3 i pps, i ppws, i ppes f-vpp standby current, f-vpp program suspend current, f-vpp erase suspend current 0.2 5 a f-v pp = f-v ppl , suspend in progress 1,3 i ppr f-vpp read 2 15 a f-v pp f-v cc 1,3
part 1: emts electrical specifications 38 intel? pxa27x processor family memory subsystem 6.2 flash dc voltage characteristics i ppw f-vpp program current 0.05 0.10 ma f-v pp = v ppl , program in progress 1,3 822 f-v pp = v pph , program in progress 1,3 i ppe f-vpp erase current 0.05 0.10 ma f-v pp = v ppl , erase in progress 1,3 822 f-v pp = v pph , erase in progress 1,3 notes: 1. all currents are rms unless noted. typical values are at typical f-vcc and t c = +25 c. 2. i ccs is the average current measured over any 5 ms time interval 5 s after f-ce# is deasserted. 3. sampled, not 100% tested. 4. flash read + program current is the sum of i ccr + i ccw currents. 5. flash read + erase current is the sum of i ccr + i cce currents. 6. i cces is specified with the flash deselected. if the flash is read-while-erase suspend, the flash current is i cces + i ccr . 7. i ccw , i cce are measured over typical or max times specified in section 7.4, flash program and erase characteristics on page 51 . table 8. flash dc voltage characteristics sym parameter min max unit test condition notes v il input low voltage 0 0.4 v 1 v ih input high voltage v ccq C 0.4 v ccq v v ol output low voltage 0.1 v f-v cc = f-v cc min v ccq = v ccq min i oh = 100 a v oh output high voltage v ccq C 0.1 v v pplk f-v pp lock-out voltage 0.4 v 2 v lko f-v cc lock voltage 1.0 v v lkoq v ccq lock voltage 0.9 v notes: 1. v il can undershoot to C0.4 v and v ih can overshoot to v ccq + 0.4 v for durations of 20 ns. 2. f-v pp v pplk inhibits erase and program operations. do not use v ppl and v pph outside their valid ranges. table 7. flash dc current characteristics (sheet 2 of 2) sym parameter typ max unit test conditions notes
part 1: emts electrical specifications intel pxa27x processor family memory subsystem 39 6.3 lpsdram dc characteristics notice: dc characteristics of all die in the pxa27x processor memory subsystem need to be considered accordingly, depending on the device operation. table 9. lpsdram dc characteristics (sheet 1 of 2) parameter description test conditions min typ max unit notes d-v cc voltage range 1.7 1.9 v i cc1 (one bank active) operating current at min cycle time burst length = 1 i io = 0 ma t ck t ck_min 75ma i cc2p precharge standby current: power- down mode (all banks idle) d-cke = l, d-cs# = h t ck t ck_min 700 a i cc2n precharge standby current: non-power- down mode (all banks idle) d-cke = h, d-cs# = h t ck t ck_min 15ma i cc3p active standby current in power- down mode (all banks active) d-cke = l, t ck t ck_min 5ma i cc3n active standby current: non-power- down mode (all banks active) d-cke = h, t ck t ck_min 25ma3 i cc4 (4 banks active) operating current page burst mode i io = 0 ma t ck t ck_min 80ma i cc5 auto refresh current t rc > t rc_min 150ma2 i cc6 self refresh current address & data toggling at min cycle time 600 a4 i cc7 deep power-down current address & data toggling at min cycle time 10 a v oh output high voltage i oh = -100 ? v ccq C 0.15 Cv v ol output low voltage i ol = 100 ? , v ccqmin C0.1 0.2 v v ih input high voltage v ccq C 0.3 v ccq + 0.2 v
part 1: emts electrical specifications 40 intel? pxa27x processor family memory subsystem v il input low voltage -0.2 0.3 v i il input leakage current C0.2 v < v in < v ccq + 0.2 v C1.5 +1.5 a1 notes: 1. input leakage currents include high-z output leakage for bi-directional buffers with tri-state outputs. 2. input signals are toggled at max frequency to simulate pxa27x processor memory subsystem operating condition, where another device may be active. 3. no accesses in progress. 4. see below table 10, lpsdram self refresh current . table 10. lpsdram self refresh current parameter description test condition set temperature # of banks unit all banks refreshed bank 0 & 1 refreshed bank 0 refreshed i cc6 self refresh current (all banks refreshed) d-cke < 0.2 v t ck = infinity 85 c max 600 450 315 a 70 c max 525 375 295 45 c max 450 300 270 15 c max 375 250 250 note: other than i cc6 for all banks at 85c, the self refresh currents are verified during device characterization and not 100% tested. table 9. lpsdram dc characteristics (sheet 2 of 2)
part 1: emts ac characteristics intel? pxa27x processor family memory subsystem 41 ac characteristics 7 7.1 ac test conditions note: ac test inputs are driven at v ih for logic "1" and v il for logic "0." input/output timing begins and ends at v ccq /2. input rise and fall times (10% to 90%) < 5 ns. worst case speed occurs at f-v cc = f-v cc min . notes: 1. test configuration component value for worst case speed conditions. 2. c l includes jig capacitance. figure 10. intel? pxa27x processor memory subsystem ac input/output reference waveform input v ccq /2 v ccq /2 output v ccq 0v test points figure 1 1. intel? pxa27x processor memory subsystem transient equivalent te sting load circuit i/o output z o = 50 ohms c l = 30pf 50 ohms v ccq /2
part 1: emts ac characteristics 42 intel? pxa27x processor family memory subsystem 7.2 flash ac read specifications table 11. flash ac read specifications (sheet 1 of 2) number symbol parameter v cc range min max units notes asynchronous specifications r1 t avav read cycle time f-v cc = 1.8 v to 2.0 v 85 ns 1 f-v cc = 1.7 v to 2.0 v 88 ns r2 t avqv address to output valid f-v cc = 1.8 v to 2.0 v 85 ns f-v cc = 1.7 v to 2.0 v 88 ns r3 t elqv f-ce# low to output valid f-v cc = 1.8 v to 2.0 v 85 ns f-v cc = 1.7 v to 2.0 v 88 ns r4 t glqv oe# low to output valid 20 ns 1,2 r5 t phqv f-rst# high to output valid 150 ns 1 r6 t elqx f-ce# low to output in low-z 0 ns 1,3 r7 t glqx oe# low to output in low-z 0 ns 1,2,3 r8 t ehqz f-ce# high to output in high-z 17 ns 1,3 r9 t ghqz oe# high to output in high-z 17 ns r10 t oh output hold from first occurring address, f-ce#, or oe# change 0 ns r11 t ehel f-ce# pulse width high 14 ns 1 latching specifications r101 t avvh address setup to adv# high 7 ns 1 r102 t elvh f-ce# low to adv# high 10 ns r103 t vlqv adv# low to output valid f-v cc = 1.8 v to 2.0 v 85 ns f-v cc = 1.7 v to 2.0 v 88 ns r104 t vlvh adv# pulse width low 7 ns r105 t vhvl adv# pulse width high 7 ns r106 t vhax address hold from adv# high 7 ns 1,4 r108 t apa page address access 25 ns 1 r111 t phvh f-rst# high to adv# high 30 ns 1 clock specifications r200 f f-clk f-clk frequency 52 mhz 1,3 r201 t f-clk f-clk period 19.2 ns r202 t ch/cl f-clk high and low time 3.5 ns r203 t f-clk f-clk fall and rise time 3ns synchronous specifications r301 t avch/ t avcl address setup to f-clk 7 ns 1 r302 t vlch/ t vlcl adv# low setup to f-clk 7 ns r303 t elch/ t elcl f-ce# low setup to f-clk 7 ns
part 1: emts ac characteristics intel pxa27x processor family memory subsystem 43 r304 t chqv /t clqv f-clk to output valid C14ns r305 t chqx output hold from f-clk 3 ns 1,5 r306 t chax address hold from f-clk 7 ns 1,4,5 r311 t chvl f-clk valid to adv# setup 0 ns 1 notes: 1. see figure 10, pxa27x processor memory subsystem ac input/output reference waveform on page 41 for timing measurements and max allowable input slew rate. 2. oe# may be delayed by up to t elqv C t glqv after f-ce#s falling edge without impact to t elqv . 3. sampled, not 100% tested. 4. address hold in synchronous burst mode is t chax or t vhax , whichever timing specification is satisfied first. 5. applies only to subsequent synchronous reads. figure 12. flash asynchronous single-word read with adv# low table 11. flash ac read specifications (sheet 2 of 2) number symbol parameter v cc range min max units notes r5 r7 r6 r9 r4 r8 r3 r1 r2 r1 a ddress [a] adv# [v] f-ce# [e] oe# [g] data [d/q] f-rst# [p]
part 1: emts ac characteristics 44 intel? pxa27x processor family memory subsystem note: a[1:0] must be held constant. figure 13. flash asynchronous single-word read with adv# latch r10 r7 r6 r9 r4 r8 r3 r106 r101 r105 r105 r2 r1 a ddres s [max:min+2] [a] a[1:0] [a] adv# [v] f-ce# [e] oe# [g] data [d/q] figure 14. flash asynchronous page-mode read timing r108 r108 r108 r7 r6 r9 r4 r8 r3 r106 r101 r105 r105 r10 r10 r10 r10 r1 r1 r2 a d dres s [max:min +2] [a] a[1:0] [a] ad v# [v] f-ce# [e] oe# [g] data [d/q]
part 1: emts ac characteristics intel pxa27x processor family memory subsystem 45 note: this diagram illustrates the case where an n-word burst is initiated to the flash memory array and it is terminated by f-ce# deassertion after the first word in the burst. figure 15. flash synchronous single-word array or non-array read timing latency count r305 r304 r4 r9 r7 r8 r303 r102 r3 r104 r106 r101 r104 r105 r105 r2 r306 r301 f-clk [c] a ddress [a] ad v# [v] f-ce# [e] oe# [g] data [d/q] figure 16. flash synchronous burst-mode eight-word read timing latency count a q0 q1 q6 q7 r10 r304 r305 r304 r4 r7 r9 r8 r303 r3 r106 r102 r105 r105 r101 r2 r306 r302 r301 f-clk [c] a ddress [a] adv# [v] f-ce# [e] oe# [g] data [d/q]
part 1: emts ac characteristics 46 intel? pxa27x processor family memory subsystem note: f-clk can be stopped in either high or low state. figure 17. flash burst suspend timing q0 q1 q1 q2 r304 r304 r7 r6 r4 r9 r4 r3 r106 r101 r105 r105 r1 r1 r2 r305 r305 r304 f-clk [c] a ddress [a] ad v# [v] f-ce# [e] oe# [g] we# [w] data [d/q]
part 1: emts ac characteristics intel? pxa27x processor family memory subsystem 47 7.3 flash ac write specifications table 12. intel? pxa27x flash ac write specifications number symbol parameter min max unit notes w1 t phwl f-rst# high recovery to we# low 150 ? ns 1,2,3 w2 t elwl f-ce# setup to we# low 0 ? ns 1,2,3 w3 t wlwh we# write pulse width low 50 ? ns 1,2,4 w4 t dvwh data setup to we# high 50 ? ns 1,2 w5 t avwh address setup to we# high 50 ? ns 1,2 w6 t wheh f-ce# hold from we# high 0 ? ns 1,2 w7 t whdx data hold from we# high 0 ? ns 1,2 w8 t whax address hold from we# high 0 ? ns 1,2 w9 t whwl we# pulse width high 20 ? ns 1,2,5 w10 t vpwh f-vpp setup to we# high 200 ? ns 1,2,3,7 w11 t qvvl f-vpp hold from status read 0 ? ns w12 t qvbl f-wp# hold from status read 0 ? ns 1,2,3,7 w13 t bhwh f-wp# setup to we# high 200 ? ns w14 t whgl we# high to oe# low 0 ? ns 1,2,9 w16 t whqv we# high to read valid t avqv + 35 ? ns 1,2,3,6,10 write to asynchronous read specifications w18 t whav we# high to address valid 0 ? ns 1,2,3,6 write to synchronous read specifications w19 t whch/l we# high to flash clock valid 19 ? ns 1,2,3,6,10 w20 t whvh we# high to adv# high 19 ? ns write specifications with clock active w21 t vhwl adv# high to we# low ? 20 ns 1,2,3,11 w22 t chwl flash clock high to we# low ? 20 ns notes: 1. write timing characteristics during erase suspend are the same as write-only operations. 2. a write operation can be terminated with either f-ce# or we#. 3. sampled, not 100% tested. 4. write pulse width low (t wlwh or t eleh ) is defined from f-ce# or we# low (whichever occurs last) to f- ce# or we# high (whichever occurs first). 5. write pulse width high (t whwl or t ehel ) is defined from f-ce# or we# high (whichever occurs first) to f-ce# or we# low (whichever occurs last). 6. t whvh or t whch/l must be met when transitioning from a write cycle to a synchronous burst read. 7. f-vpp and f-wp# should be at a valid level until erase or program success is determined. 8. this specification is only applicable when transitioning from a write cycle to an asynchronous read. see spec w19 and w20 for synchronous read. 9. when doing a read status operation following any command that alters the status register, w14 is 20 ns. 10. add 10 ns if the write operations results in a rcr or block lock status change, for the subsequent read operation to reflect this change. 11. these specs are required only when the device is in a synchronous mode and clock is active during address setup phase.
part 1: emts ac characteristics 48 intel? pxa27x processor family memory subsystem figure 18. flash write to flash write timing w1 w7 w4 w7 w4 w3 w9 w3 w9 w3 w3 w6 w2 w6 w2 w8 w8 w5 w5 a ddress [a] ad v# [v] f-ce# [e] we# [w] oe# [g] data [d/q] f-rst# [p] figure 19. flash asynchronous read to flash write timing q d r5 w7 w4 r10 r7 r6 w6 w3 w3 w2 r9 r4 r8 r3 w8 w5 r1 r2 r1 a ddress [a] f-ce# [e] oe# [g] we# [w] data [d/q] f-rst# [p]
part 1: emts ac characteristics intel pxa27x processor family memory subsystem 49 figure 20. flash write to flash asynchronous read timing figure 21. flash synchronous read to flash write timing d q w1 r9 r 8 r4 r3 r2 w7 w4 w14 w18 w3 w3 r10 w6 w2 r1 r1 w8 w5 a ddress [a] f-ce# [e] we# [w] oe# [g] data [d/q] f-rst# [p] latency count q d d w7 r13 r305 r304 r7 w15 w9 w19 w8 w9 w3 w3 w2 r8 r4 w6 r11 r11 r303 r3 w20 r104 r104 r106 r102 r105 r105 w18 w5 r101 r2 r306 r302 r301 f-clk [c] a ddress [a] ad v# [v] f-ce# [e] oe# [g] we# [w] data [d/q]
part 1: emts ac characteristics 50 intel? pxa27x processor family memory subsystem figure 22. flash write to flash synchronous read timing latency count d q q w1 r304 r305 r304 r3 w7 w4 r4 w18 w3 w3 r11 r303 r11 w6 w2 r104 r106 r104 r306 w8 w5 r302 r301 r2 f-clk [c] a ddress [a] ad v# [v] f-ce# [e] we# [w] oe# [g] data [d/q] f-rst# [p]
part 1: emts ac characteristics intel? pxa27x processor family memory subsystem 51 7.4 flash program and erase characteristics 7.5 lpsdram die capacitance ta ble 13. intel? pxa27x flash program and erase characteristics number. symbol parameter v ppl v pph units notes min typ max min typ max conventional word programming w200 t prog/w program time single word ? 90 180 ? 85 170 s 1 single cell ? 30 60 ? 30 60 1 buffered programming w200 t prog/word program time single word ? 90 180 ? 85 170 s 1 w201 t prog/buffer one buffer (32-words) ? 440 880 ? 340 680 1 buffered enhanced factory programming w451 t befp/word program single word n/a n/a n/a n/a 10 n/a s 1,2 w452 t befp/setup buffered efp setup n/a n/a n/a 5 n/a n/a 1 erasing and suspending w500 t ers/buffer erase time 16-kword parameter ? 0.4 2.5 ? 0.4 2.5 s 1 w501 t ers/main block 64-kword main ? 1.2 4 ? 1.0 4 1 w600 t susp/prog susp suspend latency program suspend ? 20 25 ? 20 25 s 1 w601 t susp/erase susp erase suspend ? 20 25 ? 20 25 1 notes: 1. typical values measured at tc = +25 c and nominal voltages. excludes system overhead. sampled, but not 100% tested. 2. averaged programming time over entire flash arrays. table 14. lpsdram capacitance symbol parameter max unit condition c in input capacitance 5 pf v in = 0 v c out output capacitance 7 pf v out = 0 v note: sampled, not 100% tested. t c = 25 c, f = 1 mhz.
part 1: emts ac characteristics 52 intel? pxa27x processor family memory subsystem 7.6 lpsdram ac characteristics table 15. 256-mbit lpsdram ac characteristicsread-only operations symbol parameter test condition min max unit notes t rc clock cycle time cl = 3 r-clk = 104 mhz 9.5 ns 1,2 t ckh clock high level pulse width 3 ns 1,2 t ckl clock low level pulse width 3 ns 1,2 t t transition time 0.5 1.0 ns 1,2 t ckeh d-cke hold time 1 ns 1,2 t ckes d-cke setup time 2 ns 1,2 t ah address hold time 1 ns 1,2 t as address setup time 2 ns 1,2 t ih data input hold time 1 ns 1,2 t is data input setup time 2 ns 1,2 t cmh d-cs#, d-ras#, d-cas#, we#, d-dm hold time 1 ns 1,2 t cms d-cs#, d-ras#, d-cas#, we#, d-dm setup time 2 ns 1,2 t ac clock to valid output delay (positive edge of clock) cl = 3 C 7 ns 1,2 t oh data out hold time 2.5 ns 1,2 t lz clock to output in low-z 1 ns 1,2 t hz clock to output in high-z cl = 3 7 ns 1,2 t ras row active time (active to precharge command) 60 100k ns 1,2 t rc row cycle time (active to active command on same bank) 90 ns 1,2 t rcd row to column delay (active to read/write) 28.5 ns 1,2 t rp row precharge time 28.5 ns 1,2 t ref refresh period (4096 rows) 64 ms 1,2 t rfc auto refresh period 110 ns 1,2 t srex self refresh exit time (self refresh to active) 120 ns 1,2 notes: 1. the minimum number of clock cycles is determined by dividing the minimum time required by clock cycle time. 2. lpsdram ac specs are guaranteed only when normal output driver strength is used. see table 35, lpsdram configurable output driver strength on page 100 .
part 1: emts ac characteristics intel pxa27x processor family memory subsystem 53 table 16. 256-mbit lpsdram ac characteristicswrite operations 1,2 symbol parameter test condition min max unit t wr write recovery time 20 ns t rrd active bank a to active bank b command 20 ns t dal last data input to active delay t wr + t rp ns t cdl last data input to new read/write command 1 t ck t bdl last data input to burst terminate command 1 t ck t ccd read/write command to read/write command 1 t ck t dqw d-dm write mask latency 0 t ck t dqz d-dm data out mask latency 2 t ck t mrd load mode register command to active/refresh command 2 t ck t wr write recovery time t wr / t ck < 1 1 t ck 1 < t wr / t ck < 2 2 t phz data out to high z from precharge command cl = 3 3 t ck t ini initialization delay 200 s notes: 1. the minimum number of clock cycles is determined by dividing the minimum time required by clock cycle time. 2. lpsdram ac specs are guaranteed only when normal output driver strength is used. see table 35, lpsdram configurable output driver strength on page 100 .
part 1: emts ac characteristics 54 intel? pxa27x processor family memory subsystem
part 1: emts power and reset specifications intel pxa27x processor family memory subsystem 55 power and reset specifications 8 8.1 flash power-up and power-down power supply sequencing is not required if f- vcc, vccq, and f-vpp are connected together. if vccq and/or f-vpp are not connected to the f-vcc supply, then f-v cc should reach f-v cc min before applying v ccq and f-v pp . device inputs should not be driven before supply voltage equals f-v cc min . power supply transitions should only occur when f-rst# is low. this protects the device from accidental programming or erasure during power transitions. 8.2 flash output disable when oe# is deasserted, the flash outputs dq[max:0] are disabled and placed in hign-z. 8.3 flash standby when f-ce# is deasserted the flash is deselected and placed in standby, substantially reducing power consumption. in standby, the data outputs are placed in high-z, independent of the level placed on oe#. standby current, i ccs , is the average current measured over any 5 ms time interval, 5 s after f-ce# is deasserted. when the flash is deselected (while f-ce# is deasserted) during a program or erase operation, it continues to consume active power until the program or erase operation is completed. 8.4 flash reset when the pxa27x processor reset occurs with no flash memory reset, improper processor initialization may occur because the flash memory may be providing status information rather than array data. f-rst# should be controlled by the same low-true reset signal that resets the pxa27x processor. after initial power-up or reset, the flash defaults to asynchronous read array, and the status register is set to 0x80. a minimum delay is required before an initial read access or a write cycle can be initiated. after this wake - up interval passes, normal operation is restored. see table 17 and figure 23 on page 56 for details about the flash reset timing. note: if f-rst# is asserted during a program or erase operation, the operation is terminated and the memory contents at the aborted location (for a program) or block (for an erase) are no longer valid, because the data may have been only partially written or erased.
part 1: emts power and reset specifications 56 intel? pxa27x processor family memory subsystem table 17. flash reset timing 8.5 flash power supply decoupling flash memory device require careful power supply decoupling. three basic power supply current considerations are require: 1) standby current levels, 2) active current levels, and 3) transient peaks produced when f-ce# and oe# are asserted and deasserted. when the flash is accessed, many internal conditions change. transient current magnitudes depend on the device outputs capacitive and inductive loading. two-line control and correct decoupling capacitor selection suppress transient voltage peaks. because intel strataflash ? memory draws its power from f-vcc, f-vpp, and vccq, therefore each power connection should have a 0.1 f ceramic capacitor connected to a corresponding ground connection (e.g.,vccq to vss). high- frequency, inherently low-inductance capacitors should be placed as close as possible to package leads. it is recommended, for every eight devices used in the system, a 4.7 f electrolytic capacitor should be placed between power and ground close to the devices. the bulk capacitor is meant to overcome voltage droop caused by pcb trace inductance. nbr. symbol parameter min max unit notes p1 t plph f-rst# pulse width low 100 ns 1,2,3,5 p2 t plrh f-rst# low to device reset during erase 25 s 3,4,5 f-rst# low to device reset during program 25 3,4,5 p3 t vccph f-v cc power valid to f-rst# de-assertion (high) 60 1,3,5 notes: 1. the device may reset if t plph is < t plph min, but this is not guaranteed. 2. if f-rst# is tied to the f-v cc supply, the flash will not be ready until t vccph and after f-v cc f-v cc min . 3. if f-rst# is tied to any pin or signal with v ccq voltage levels, the f-rst# input voltage must not exceed f-v cc until f-v cc f-v cc min . 4. reset completes within t plph if f-rst# is asserted while no erase or program operation is executing. 5. sampled, but not 100% tested. figure 23. flash reset operation waveforms f-v cc f-rst# [p] v ih v il f-rst# [p] v ih v il f-rst# [p] v ih v il p2 p3 p2 p1 r5 r5 r5 0 v abor t complete abort complete f-v cc (a) reset during read mode (b) reset during program or block erase p1 < p2 (c) reset during program or block erase p1 > p2 (d) f-vcc power-up to f-rst# high
part 1: emts power and reset specifications intel pxa27x processor family memory subsystem 57 8.6 flash automatic power saving automatic power saving (aps) provides low power operation during a reads active state. during aps, i ccaps average current is measured over any 5 ms time interval, 5 s after f-ce# is deasserted. aps, the same time interval 5 s after the following events: 1. there is no internal read, program, or erase operations. 2. f-ce# is asserted. 3. the address lines are quiescent and at vss or vccq. oe# may also be driven during aps. 8.7 lpsdram power-up sequence and initialization the lpsdram must be powered up and initialized in a predefined manner. once power is applied to d-vcc and vccq simultaneously, and the clock is stable, the lpsdram requires a t ini delay prior to issuing any command other than the nop command. the nop command should be applied at least once during the t ini delay. after the t ini delay, a precharge command should be applied to precharge all banks. this must be followed by two back to back auto refresh cycles. after the auto refresh cycles are complete, the mode registers must be programmed. the mode register will power up in an unknown state. the mode register and the extended mode register should be loaded prior to issuing any operational commands.
part 1: emts power and reset specifications 58 intel? pxa27x processor family memory subsystem
pxa27x processor memory subsystem 59 part 2: flash device operations
60 pxa27x processor memory subsystem
part 2: flash device operations device operations overview intel pxa27x processor family memory subsystem 61 device operations overview 9 9.1 flash and lpsdram bus operations bus operations for the pxa27x processor memory subsystem device involve the control of flash and lpsdram inputs. the bus operations are shown from table 18 to table 20 . fully synchronous operations are performed by the flash or lpsdram to latch the commands at the positive edges of f-clk or r-clk respectively . table 18. flash + lpsdram bus operations (sheet 1 of 2) device mode f-rst# f-ce# oe# adv# f-vpp we# d-cke n-1 d-cke n d-cs# d-ras# d-cas# d-dm[1:0] d-ba[1:0] a11 address data notes flash die sync readhlll x h lpsdram outputs must be in high-z flash dq out 1,2,3,4, 15 async read hlll x h flash dq out 1,2,3,4, 15 write h l h l v ppl / v pph lflash dq in 1,2,4,15 output disable hlhx x h any lpsdram mode is allowed flash high-z 4,15 standby h h x x x x flash high-z 4,15 reset l x x x x x flash high-z 4,15 lpsdram die active flash outputs must be in high-z h h x l l h x v row address lpsdram dq out 5,6,7 read hhx l hl v v l col addr lpsdram dq out 5,6,7,13 with auto precharge h write lhxlhl v v l x lpsdram dq in 5,6,8 with auto precharge h burst stop l h h l h h x x x x lpsdram high-z 9 precharge one bank lhxllh x vl x lpsdram high-z 6 all banks x h auto refresh flash outputs must be in high-z hhhlll x x x x lpsdram high-z 6, 12 self refresh entry flash must be in high-z h h l l l l x x x x lpsdram high-z 6 self refresh exit any flash mode is allowed h lh lhh xx x x lpsdram high-z 6 xhxx
part 2: flash device operations device operations overview 62 intel? pxa27x processor family memory subsystem lpsdram die load mode register flash outputs must be in high-z lhxlll x operand code lpsdram high-z 6, 10,11 input/ output enable xh x l x lpsdram high-z 6, 9 input inhibit/ output high-z any flash mode is allowed x h x h x lpsdram high-z 6, 9 clock suspend entry any flash mode is allowed x hl hxx xx x x lpsdram high-z 6, 13 vlvv clock suspend exit flash outputs must be in high-z xlhxxxxx x x lpsdram high-z 6,13 power down entry any flash mode allowed x hl hxx xx x x lpsdram high-z 6, 14 flash outputs must be in high-z hlhh power down exit any flash mode is allowed x lh hxx xx x x lpsdram high-z 6,14 hlhh deep power down entry flash outputs must be in high-z lhllhh x x x x lpsdram high-z 6,14 deep power down exit xlhxxxxx x x lpsdram high-z 6,14 device deselect (nop) any flash mode is allowed x h x h x x x x x x lpsdram high-z 6 no operation (nop) flash outputs must be in high-z hhx lhh x x x x lpsdram high-z 6 notes: 1. oe# and we# should never be asserted simultaneously. 2. x can be v il or v ih for inputs. 3. flash cfi query and status register accesses use dq[7:0] only, all other reads use dq[15:0]. 4. all states and sequences not shown are illegal or reserved. 5. v = valid. 6. a[13:1] provide row address for lpsdram. a[9:1] provide column address for lpsdram. 7. select bank and column address, and start read. a11 high enables auto precharge. 8. select bank and column address, and start write. a11 high enables auto precharge. 9. activate or deactivate the data during writes with zero-clock delay and during reads with two-clock delay. d-dm0 corresponds to dq[7:0], d-dm1 corresponds to dq[15:8]. 10. a[11:1] define the dram operand code to the register 11. extended mode register is programmed by setting d-ba1 = h and d-ba0 = l. for mode register programming, set d-ba1 = d-ba0 = l 12. all banks must be precharged before issuing an auto-refresh command. 13. clock suspend mode occurs when column access or burst is in progress 14. power-down occurs when no accesses are in progress. 15. for x32 flash only stacked combination, the bus operations are equivalent to x16 flash die bus operations. table 18. flash + lpsdram bus operations (sheet 2 of 2) device mode f-rst# f-ce# oe# adv# f-vpp we# d-cke n-1 d-cke n d-cs# d-ras# d-cas# d-dm[1:0] d-ba[1:0] a11 address data notes
part 2: flash device operations device operations overview intel pxa27x processor family memory subsystem 63 table 19. lpsdram functional mode description: current state bank n , command to bank n current state d-cs# d-ras# d-cas# we# command action notes any h x x x no operation continue previous operation 1,2 l h h h no operation continue previous operation 1,2 idle l l h h active select and activate row 1,2 l l l h auto refresh auto refresh 1,2 l l l l load mode register mode register set 1,2 l l h l precharge nop 1,2 row active l h l h read select column & start read burst 1,2,4 l h l l write select column & start write burst 1,2,4 l l h l precharge deactivate row in bank (or banks) 1,2,3,4 read (without auto precharge) lhlh read truncate read & start new read burst 1,2,5 lhll write truncate read & start new write burst 1,2,5 l l h l prechard truncate read, start precharge 1,2 l h h l burst terminate burst terminate 1,2 write (without auto precharge) lhlh read truncate write & start new read burst 1,2,5 lhll write truncate write& start new write burst 1,2,5 l l h l precharge truncate write, start precharge 1,2 l h h l burst terminate burst terminate 1,2 notes: 1. the table applies when both d-cke n-1 and d-cke n are high. 2. all states and sequences not shown are illegal or reserved. 3. this command may or may not be bank specific. if all banks are being precharged, they must be in a valid state for precharging. 4. a command other than no operation (nop), should not be issued to the same bank while a read or write burst with auto precharge is enabled. 5. the new read or write command could be auto precharge enabled or auto precharge disabled.
part 2: flash device operations device operations overview 64 intel? pxa27x processor family memory subsystem 9.2 flash bus operations f-ce# low and f-rst# high enable device read operations. the flash device internally decodes upper address inputs to determine the accessed partition. adv# low opens the internal address latches. oe# low activates the outputs and gates selected data onto the i/o bus. in asynchronous mode, the addresses are latched when adv# goes high or continuously flows through if adv# is held low. in synchronous burst-mode, the addresses are latched by the first rising edge of adv#, or the next valid f-clk edge with adv# low (we# and f-rst# must be high, and f-ce# must be low). table 20. lpsdram functional mode description: current state bank n , command to bank m current state d-cs# d-ras# d-cas# we# command action notes any h x x x no operation continue previous operation 1,2 l h h h no operation continue previous operation 1,2 idle x x x x any any command allowed to bank m 1,2 row activating, active, or precharging l l h h active activate row 1,2 l h l h read start read burst 1,2 l h l l write start write burst 1,2 l l h l precharge precharge 1,2 read with auto precharge disabled l l h h active activate row 1,2 l h l h read start read burst 1,2 l h l l write start write burst 1,2 l l h l precharge precharge 1,2 write with auto precharge disabled l l h h active activate row 1,2 l h l h read start read burst 1,2 l h l l write start write burst 1,2 l l h l precharge precharge 1,2 read with auto precharge l l h h active activate row 1,2 l h l h read start read burst 1,2 l h l l write start write burst 1,2 l l h l precharge precharge 1,2 write with auto precharge l l h h active activate row 1,2 l h l h read start read burst 1,2 l h l l write start write burst 1,2 l l h l precharge precharge 1,2 notes: 1. the table applies when both d-cke n-1 and d-cke n are high. 2. all states and sequences not shown are illegal or reserved.
part 2: flash device operations device operations overview intel pxa27x processor family memory subsystem 65 table 21. flash command bus cycles mode command bus cycles first bus cycle second bus cycle oper addr 1 data 2 oper addr 1 data 2 read read array 1 write pna 0xff read device identifier 2 write pna 0x90 read pba+ia id cfi query 2 write pna 0x98 read pna+qa qd read status register 2 write pna 0x70 read pna srd clear status register 1 write x 0x50 program word program 2 write wa 0x40/ 0x10 write wa wd buffered program 3 > 2 write wa 0xe8 write wa n - 1 buffered enhanced factory program (buffered efp) 4 > 2 write wa 0x80 write wa 0xd0 erase block erase 2 write ba 0x20 write ba 0xd0 suspend program/erase suspend 1 write x 0xb0 program/erase resume 1 write x 0xd0 block locking/ unlocking lock block 2 write ba 0x60 write ba 0x01 unlock block 2 write ba 0x60 write ba 0xd0 lock-down block 2 write ba 0x60 write ba 0x2f protection program protection register 2 write pra 0xc0 write pra pd program lock register 2 write lra 0xc0 write lra lrd configuration program read configuration register 2 write rcd 0x60 write rcd 0x03 notes: 1. first command cycle address should be the same as the operations target address. pna = address within the partition. pba = partition base address. ia = identification code address offset. qa = cfi query address offset. ba = address within the block. wa = word address of memory location to be written. pra = protection register address. lra = lock register address. x = any valid address within the flash. 2. id = identifier data. qd = query data on dq[15:0]. srd = status register data. wd = word data. n = word count of data to be loaded into the write buffer. pd = protection register data. pd = protection register data. lrd = lock register data. rcd = read configuration register data on a[15:0]. a[max:16] can select any partition . 3. the second cycle of the buffered program command is the word count of the data to be loaded into the write buffer. this is followed by up to 32-words of data.then the confirm command (0xd0) is issued, triggering the array programming operation. 4. the confirm command (0xd0) is followed by the buffer data.
part 2: flash device operations device operations overview 66 intel? pxa27x processor family memory subsystem 9.3 flash command definitions table 22. flash command codes and definitions (sheet 1 of 2) mode code device mode description read 0xff read array places the addressed partition in read array mode. array data is output on dq[15:0]. 0x70 read status register places the addressed partition in read status register mode. the partition enters this mode after a program or erase command is issued. status register data is output on dq[7:0]. 0x90 read device id or configuration register places the addressed partition in read device identifier mode. subsequent reads from addresses within the partition outputs manufacturer/device codes, configuration register data, block lock status, or protection register data on dq[15:0]. 0x98 read query places the addressed partition in read query mode. subsequent reads from the partition addresses output common flash interface information on dq[7:0]. 0x50 clear status register the wsm can only set status register error bits. the clear status register command is used to clear the sr error bits. write 0x40 word program setup first cycle of a 2-cycle programming command; prepares the cui for a write operation. on the next write cycle, the address and data are latched and the wsm executes the programming algorithm at the addressed location. during program operations, the partition responds only to read status register and program suspend commands. f-ce# or oe# must be toggled to update the status register in asynchronous read. f-ce# or adv# must be toggled to update the status register data for synchronous non-array read. the read array command must be issued to read array data after programming has finished. 0x10 alternate word program setup equivalent to the word program setup command, 0x40. 0xe8 buffered program this command loads a variable number of bytes up to the buffer size of 32-words onto the program buffer. 0xd0 buffered program confirm the confirm command is issued after the data streaming for writing into the buffer is done. this instructs the wsm to perform the buffered program algorithm, writing the data from the buffer to the flash memory array. 0x80 buffered enhanced factory programming setup first cycle of a 2-cycle command; initiates buffered enhanced factory program mode (buffered efp). the cui then waits for the buffered efp confirm command, 0xd0, that initiates the buffered efp algorithm. all other commands are ignored when buffered efp mode begins. 0xd0 buffered efp confirm if the previous command was buffered efp setup (0x80), the cui latches the address and data, and prepares the flash for buffered efp mode. erase 0x20 block erase setup first cycle of a 2-cycle command; prepares the cui for a block-erase operation. the wsm performs the erase algorithm on the block addressed by the erase confirm command. if the next command is not the erase confirm (0xd0) command, the cui sets status register bits sr.4 and sr.5, and places the addressed partition in read status register mode. 0xd0 block erase confirm if the first command was block erase setup (0x20), the cui latches the address and data, and the wsm erases the addressed block. during block-erase operations, the partition responds only to read status register and erase suspend commands. f- ce# or oe# must be toggled to update the status register in asynchronous read. f- ce# or adv# must be toggled to update the status register data for synchronous non-array read. suspend 0xb0 program or erase suspend this command issued to any flash address initiates a suspend of the currently- executing program or block erase operation. the status register indicates successful suspend operation by setting either sr.2 (program suspended) or sr.6 (erase suspended), along with sr.7 (ready). the write state machine remains in the suspend mode regardless of control signal states (except for f-rst# asserted). 0xd0 suspend resume this command issued to any flash address resumes the suspended program or block- erase operation.
part 2: flash device operations device operations overview intel pxa27x processor family memory subsystem 67 block locking/ unlocking 0x60 lock block setup first cycle of a 2-cycle command; prepares the cui for block lock configuration changes. if the next command is not block lock (0x01), block unlock (0xd0), or block lock-down (0x2f), the cui sets status register bits sr.4 and sr.5, indicating a command sequence error. 0x01 lock block if the previous command was block lock setup (0x60), the addressed block is locked. 0xd0 unlock block if the previous command was block lock setup (0x60), the addressed block is unlocked. if the addressed block is in a lock-down state, the operation has no effect. 0x2f lock-down block if the previous command was block lock setup (0x60), the addressed block is locked down. protection 0xc0 program protection register setup first cycle of a 2-cycle command; prepares the flash for a protection register or lock register program operation. the second cycle latches the register address and data, and starts the programming algorithm. configu- ration 0x60 read configuration register setup first cycle of a 2-cycle command; prepares the cui for flash read configuration. if the set read configuration register command (0x03) is not the next command, the cui sets status register bits sr.4 and sr.5, indicating a command sequence error. 0x03 read configuration register if the previous command was read configuration register setup (0x60), the cui latches the address and writes a[15:0] to the read configuration register. following a configure read configuration register command, subsequent read operations access array data. table 22. flash command codes and definitions (sheet 2 of 2) mode code device mode description
part 2: flash device operations device operations overview 68 intel? pxa27x processor family memory subsystem
part 2: flash device operations flash read operations intel pxa27x processor family memory subsystem 69 flash read operations 10 the flash supports two read modes: asynchro nous page-mode and synchronous burst-mode. asynchronous page-mode is the default read mode after flash power-up or a reset. the read configuration register must be configured to enable synchronous burst reads of the flash memory array (see section 10.3, flash read configuration register on page 70 ). to perform a read operation, f-rst# and we# must be deasserted while f-ce# and oe# are asserted. f-ce# is the flash-select control. when asserted, it enables the flash memory. oe# is the data-output control. when asserted, the addressed flash memory data is driven onto the i/o bus. see section 10.3, flash read configuration register on page 70 for details on the available read modes, and section 15, special flash read states on page 93 for details regarding the available read states. the automatic power savings (aps) feature provides low power operation following reads during active mode. after data is read from the memory array and the address lines are quiescent, aps automatically places the flash into standby. in aps, flash current is reduced to i ccaps (see section 6.1, flash dc current characteristics on page 37 ). each partition of the flash can be in any of four read states: read array, read identifier, read status or read query. upon power-up, or after a reset, all partitions of the flash default to read array. to change a partitions read state, the appropriate read command must be written to the flash (see section 9.3, flash command definitions on page 66 ). 10.1 flash asynchronous page-mode read following a flash power-up or reset, asynchronous page-mode is the default flash read mode and all partitions are set to read array. however, to perform array reads after any other flash operation (e.g. write operation), the read array command must be issued in order to read from the flash memory array. note: asynchronous page-mode reads can only be performed when read configuration register bit rcr.15 is set (see section 10.3, flash read configuration register on page 70 ). to perform an asynchronous page-mode read, an address is driven onto a[max:min], and f-ce# and adv# are asserted. we# and f-rst# must already have been deasserted. adv# can be driven high to latch the address, or it must be held low throughout the read cycle. f-clk is not used for asynchronous page-mode reads, and is ignored. if only asynchronous reads are to be performed, f-clk should be tied to a valid v ih level, and adv# must be tied to ground. flash array data are driven onto dq[15:0] after an initial access time t avqv delay. (see section 7.2, flash ac read specifications on page 42 ). in asynchronous page-mode, four-data words are sensed simultaneously from the flash memory array and loaded into an internal page buffer. the buffer word corresponding to the initial address on a[max:min] is driven onto dq[15:0] af ter the initial access delay. address bits a[max:min+2] select the 4-word page. address bits a[min+1:min] determine which word of the 4-word page is output from the data buffer at any given time. note: amin for a 16-bit operations is a1 while a 32-bit operations, amin = a2 on the package ballout.
part 2: flash device operations flash read operations 70 intel? pxa27x processor family memory subsystem 10.2 flash synchronous burst-mode read read configuration register bits rcr[15:0] must be set before flash synchronous burst operation can be performed. synchronous burst mode can be performed for both array and non-array reads such as read id, read status or read query. (see section 10.3, flash read configuration register on page 70 for details). synchronous burst-mode outputs 4-, 8-, 16-, or continuous- words. to perform a synchronous burst- read, an initial address is driven onto a[max:min], and f-ce# and adv# are asserted. we# and f-rst# must already have been deasserted. adv# is asserted, and then deasserted to latch the address. alternately, adv# can remain asserted throughout the burst access, in which case the address is latched on the next valid f-clk edge while adv# is asserted. during synchronous array and non-array read modes, the first word is output from the data buffer on the next valid f-clk edge after the initial access latency delay (see section 10.3.2, flash latency count on page 72 ). subsequent data is output on valid f-clk edges following a minimum delay. however, for a synchronous non-array read, the same word of data will be output on successive clock edges until the burst length requirements are satisfied. 10.2.1 flash burst suspend the burst suspend feature of the flash can reduce or eliminate the initial access latency incurred when system software needs to suspend a burst sequence that is in progress in order to retrieve data from another device on the same system bus. the pxa27x processor can resume the burst sequence later. burst suspend provides maximum benefit in non-cache systems. burst accesses can be suspended during the initial access latency (before data is received) or after the flash has output data. when a burst access is suspended, internal array sensing continues and any previously latched internal data are retained. a burst sequence can be suspended and resumed without limit as long as flash operation conditions are met. burst suspend occurs when f-ce# is asserted, the current address has been latched (either adv# rising edge or valid f-clk edge), f-clk is halted, and oe# is deasserted. f-clk can be halted when it is at v ih or v il . to resume the burst access, oe# is reasserted, and f-clk is restarted. subsequent f-clk edges resume the burst sequence. 10.3 flash read configuration register the flash read configuration regi ster (rcr) is used to select the read mode (synchronous or asynchronous), and it defines the synchronous bu rst characteristics of the flash. to modify rcr settings, use the configure read configuration register command (see section 9.2, flash bus operations on page 64 ). rcr contents can be examined using the read device identifier command, and then reading from + 0x05 offset. see section 15.2, flash read device identifier on page 95 . the rcr is shown in table 23 on page 71 .
part 2: flash device operations flash read operations intel pxa27x processor family memory subsystem 71 10.3.1 flash read mode the flash read mode (rm) bit selects synchronous burst-mode or asynchronous page-mode operation for the flash. when the rm bit is set, asynchronous page-mode is selected (default). when rm is cleared, synchronous burst-mode is selected. table 23. flash read configuration register description read configuration register (rcr) read mode res latency count res data hold res burst seq f-clk edge res res burst wrap burst length rm r lc[2:0] r dh r bs ce r r bw bl[2:0] 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit name description 15 read mode (rm) 0 = synchronous burst-mode read 1 = asynchronous page-mode read (default) 14 reserved (r) reserved bits should be cleared (0) 13:11 latency count (lc[2:0]) 010 =code 2 011 =code 3 100 =code 4 101 =code 5 110 =code 6 111 =code 7 (default) ? other bit settings are reserved. 10 reserved (r) default to an active high (1) 9 data hold (dh) 0 =data held for a 1-clock data cycle 1 =data held for a 2-clock data cycle (default) 8 reserved (r) default to an active high (1) 7 burst sequence (bs) 0 =reserved 1 =linear (default) 6 clock edge (ce) 0 = falling edge 1 = rising edge (default) 5:4 reserved (r) reserved bits should be cleared (0) 3 burst wrap (bw) 0 =wrap; burst accesses wrap within burst length set by bl[2:0] 1 =no wrap; burst accesses do not wrap within burst length (default) 2:0 burst length (bl[2:0]) 001 =reserved 010 =8-word burst 011 =16-word burst 111 =reserved (default) ? other bit settings are reserved.
part 2: flash device operations flash read operations 72 intel? pxa27x processor family memory subsystem 10.3.2 flash latency count the latency count bits, lc[2:0], tell the flash how many clock cycles must elapse from the rising edge of adv# (or from the first valid clock edge after adv# is asserted) until the first data word is to be driven onto dq[15:0]. the input clock frequency is used to determine this value. table 24 on page 72 shows the data output latency for the different settings of lc[2:0]. refer to table 24, flash lc and frequency support on page 72 for latency code settings example. figure 24. flash first-access latency count table 24. flash lc and frequency support latency count settings frequency support (mhz) 2 28 3 40 4 or 5 52 note: lc is based on t avqv = 85 ns and t chqv = 14 ns. code 6 (reserved) code 5 code 4 code 3 code 2 code 1 (reserved) code 0 (reserved) code 7 (reserved) valid address valid output valid output valid output valid out put valid output valid output valid output valid output valid output valid output valid out put valid output valid output valid output valid output valid output valid out put valid output valid output valid output valid output valid out put valid output valid output valid output valid output valid output valid output valid output valid output valid output valid output valid output valid output valid output valid output address [a] adv# [v] data [d/q] f-clk [c] data [d/q] data [d/q] data [d/q] data [d/q] data [d/q] data [d/q] data [d/q]
part 2: flash device operations flash read operations intel pxa27x processor family memory subsystem 73 10.3.3 flash burst sequence the burst sequence (bs) bit selects linear-burst sequence (default). only linear-burst sequence is supported. table 25 shows the synchronous burst sequence for all burst lengths supported by pxa27x processor. figure 25. example of flash latency count setting data [d/q] address [a] f-clk [c] f-ce# [e] adv# [v] r103 valid output valid output high z t data 1st 0 2nd 3rd 4th valid address code 3 table 25. flash burst sequence word ordering start addr. (dec) burst wrap (rcr.3) burst addressing sequence (dec) 8-word burst (bl[2:0] = 0x010) 16-word burst (bl[2:0] = 0x011) 0 0 0-1-2-3-4-5-6-7 0-1-2-3-414-15 1 0 1-2-3-4-5-6-7-0 1-2-3-4-515-0 2 0 2-3-4-5-6-7-0-1 2-3-4-5-615-0-1 3 0 3-4-5-6-7-0-1-2 3-4-5-6-715-0-1-2 4 0 4-5-6-7-0-1-2-3 4-5-6-7-815-0-1-2-3 5 0 5-6-7-0-1-2-3-4 5-6-7-8-915-0-1-2-3-4 6 0 6-7-0-1-2-3-4-5 6-7-8-9-1015-0-1-2-3-4-5 7 0 7-0-1-2-3-4-5-6 7-8-9-1015-0-1-2-3-4-5-6 14 0 14-15-0-1-212-13 15 0 15-0-1-2-313-14 0 1 0-1-2-3-4-5-6-7 0-1-2-3-414-15 1 1 1-2-3-4-5-6-7-8 1-2-3-4-515-16 2 1 2-3-4-5-6-7-8-9 2-3-4-5-616-17 3 1 3-4-5-6-7-8-9-10 3-4-5-6-717-18 4 1 4-5-6-7-8-9-10-11 4-5-6-7-818-19 5 1 5-6-7-8-9-10-11-12 5-6-7-8-919-20 6 1 6-7-8-9-10-11-12-13 6-7-8-9-1020-21 7 1 7-8-9-10-11-12-13-14 7-8-9-10-1121-22 14 1 14-15-16-17-1828-29 15 1 15-16-17-18-1929-30
part 2: flash device operations flash read operations 74 intel? pxa27x processor family memory subsystem 10.3.4 flash clock edge the clock edge (ce) bit selects either a rising (default) or falling clock edge for f-clk. this clock edge is used at the start of a burst cycle, to output synchronous data, and to assert/deassert wa i t. 10.3.5 flash burst wrap the burst wrap (bw) bit determines whether 8-word, or 16-word burst length accesses wrap within the selected word-length boundaries or cross word-length boundaries. when bw is set, burst wrapping does not occur (default). when bw is cleared, burst wrapping occurs. 10.3.6 flash burst length the burst length bit (bl[2:0]) selects the linear burst length for all synchronous burst reads of the flash memory array. the burst lengths are 8-word and 16-word.
part 2: flash device operations flash programming operations intel pxa27x processor family memory subsystem 75 flash programming operations 11 the flash supports three programming methods: single-word programming (0x40/0x10), buffered programming (0xe8, 0xd0), and buffered enhanced factory programming (buffered efp) (0x80, 0xd0). see section 9.3, flash command definitions on page 66 for details on the various programming commands issued to the flash. to perform a write operation, both f-ce# and we# are asserted while f-rst# and oe# are deasserted. during a write operation, address and data are latched on the rising edge of we# or f-ce#, whichever occurs first. table 21, flash command bus cycles on page 65 shows the bus cycle sequence for each of the supported flash commands, while table 22, flash command codes and definitions on page 66 describes each command. see section 7.3, flash ac write specifications on page 47 for signal-timing details. warning: write operations with invalid f-v cc and/or f-v pp voltages can produce spurious results and should not be attempted. successful programming requires the addressed block to be unlocked. if the block is locked down, f-wp# must be deasserted and the block must be unlocked before attempting to program the block. attempting to program a locked block causes a program error (sr.4 and sr.1 are set) and termination of the operation. see section 13, flash security modes on page 83 for details on locking and unlocking blocks. 11.1 flash word programming word programming operations are initiated by writing the word program setup command to the flash (see section 9.2, flash bus operations on page 64 ). this is followed by a second write to the flash with the address and data to be programmed. the partition accessed during both write cycles outputs status register data when read. the partition accessed during the second cycle (the data cycle) of the program command sequence is the location where the data is written. see figure 52, flash word program flowchart on page 113 . programming can occur in only one partition at a time; all other partitions must be in a read state or in erase suspend. f-v pp must be above v pplk , and within the specified v ppl value. during programming, the flash write state machine (wsm) executes a sequence of internally- timed events that program the desired data bits at the addressed location, and verifies that the bits are sufficiently programmed. programming the flash memory array changes ones to zeros. flash array bits that are zeros can be changed to ones only by erasing the block. see section 12, flash erase operations on page 81 . the flash status register can be examined for programming progress and errors by reading any address within the partition that is being programmed. the partition remains in the read status register state until another command is written to that partition. issuing the read status register command to another partition address sets that partition to the read status register state, allowing programming progress to be monitored at that partitions address.
part 2: flash device operations flash programming operations 76 intel? pxa27x processor family memory subsystem status register bit sr.7 indicates the programming status while the sequence executes. commands that can be issued to the programming partition during programming are program suspend, read status register, read device identifier, cfi qu ery, and read array (this returns unknown data). when programming has finished, sr.4 (when set) indicates a programming failure. if sr.3 is set, the wsm could not perform the word programming operation because f-vpp was outside of its acceptable limits. if sr.1 is set, the word programming operation attempted to program a locked block, causing the operation to abort. before issuing a new command, the status register contents should be examined and then cleared using the clear status register command. any valid command can follow, when word programming has completed. 11.1.1 flash factory word programming factory word programming is similar to word programming in that it uses the same commands and programming algorithms. however, factory word programming enhances the programming performance with f-v pp = v pph . this can enable faster programming times during factory manufacturing processes. factory word programming is not intended for extended use. see section 5.2, operating conditions on page 36 for limitations when f-v pp = v pph . note: when f-v pp = v ppl , the flash draws programming current from the f-vcc supply. if f-vpp is driven by a logic signal, v ppl must remain above v ppl min to program the flash. when f-v pp = v pph , the flash draws programming current from the f-vpp supply. figure 26, example f-vpp supply connections on page 80 shows examples of flash power supply configurations. 11.2 flash buffered programming the flash features a 32-word buffer to enable optimum programming performance. for buffered programming, data is first written to an on-chip write buffer. then the buffer data is programmed into the flash memory array in buffer-size increments. this can improve system programming performance significantly over non-buffered programming. when the buffered programming setup command is issued. see section 9.3, flash command definitions on page 66 , status register information is updated and reflects the availability of the write buffer. sr.7 indicates buffer availability: if set, the buffer is available; if cleared, the write buffer is not available. to retry, issue the buffered programming setup command again, and re- check sr.7. when sr.7 is set, the buffer is ready for loading. see figure 54, flash buffer program flowchart on page 115 . on the next write, a word count is written to the flash at the buffer address. this tells the flash how many data words will be written to the buffer, up to the maximum size of the buffer. on the next write, a flash start address is given along with the first data to be written to the flash memory array. subsequent writes provide additional flash addresses and data. all data addresses must lie within the start address plus the word count. optimum programming performance and lower power usage are obtained by aligning the starting address at the beginning of a 32-word boundary (a[4:0] = 0x00). crossing a 32-word boundary during programming will result in doubling the total programming time due to refilling the buffer region.
part 2: flash device operations flash programming operations intel pxa27x processor family memory subsystem 77 after the last data is written to the buffer, the buffered programming confirm command must be issued to the original block address. the wsm begins to program buffer contents to the flash memory array. if a command other than the buffered programming confirm command is written to the flash, a command sequence error occurs and sr[7,5,4] are set. if an error occurs while writing to the array, the flash stops programming, and sr[7,4] are set, indicating a programming failure. reading from another partition is allowed while data is being programmed into the array from the write buffer. see section 14, flash dual-operation considerations on page 89 . when buffered programming has completed, additional buffer writes can be initiated by issuing another buffered programming setup command and repeating the buffered program sequence. buffered programming may be performed with f-v pp = v ppl or f-v pp = v pph . see section 5.2, operating conditions on page 36 for limitations when operating the flash with f-v pp = v pph . if an attempt is made to program past an erase-block boundary using the buffered program command, the flash aborts the operation. this generates a command sequence error, and sr[5,4] are set. if buffered programming is attempted while f-v pp v pplk , sr[4,3] are set. if any errors are detected that have set status register bits, the status register should be cleared using the clear status register command. 11.3 flash buffered enhanced factory programming buffered enhanced factory programing (buffered efp) is design to speed up flash programming for today's beat-rate-sensitive manufacturing environments. the enhanced programming algorithm used in buffered efp eliminates traditional programming elements that drive up overhead in flash programmer systems. buffered efp consists of three phases: setup, program/verify, and exit. see figure 55, flash buffered efp flowchart on page 116 . it uses a write buffer to spread mlc program performance across 32-words. verification occurs in the same phase as programming to accurately program the flash memory cell to the correct bit state. a single two-cycle command sequence programs the entire block of data. this enhancement eliminates three write cycles per buffer: two commands and the word count for each set of 32-words. host programmer bus cycles fill the flash write buffer followed by a status check. sr.0 indicates when data from the buffer has been programmed into sequential flash memory array locations. following the buffer-to-flash array programming sequence, the write state machine (wsm) increments internal addressing to automatically select the next 32-word array boundary. this aspect of buffered efp saves host programming equipment the address-bus setup overhead. with adequate continuity testing, programming equipment can rely on the wsms internal verification to ensure that the flash has programmed properly. this eliminates the external post- program verification and its associated overhead.
part 2: flash device operations flash programming operations 78 intel? pxa27x processor family memory subsystem 11.3.1 flash buffered efp requirements and considerations buffered efp requirements: ? case temperature: t c = 25 c, 5 c ? f-v cc within specified operating range. ? f-v pp driven to v pph . ? target block unlocked before issuing the buffered efp setup and confirm commands. ? the first-word address (wa0) for the block to be programmed must be held constant from the setup phase through all data streaming into the target block, until transition to the exit phase is desired. ? wa0 must align with the start of an array buffer boundary 1 . buffered efp considerations: ? for optimum performance, cycling must be limited below 100 erase cycles per block 2 . ? buffered efp programs one block at a time; all buffer data must fall within a single block 3 . ? buffered efp cannot be suspended. ? programming to the flash memory array can occur only when the buffer is full 4 . ? read operation while performing buffered efp is not supported. notes: 1. word buffer boundaries in the array are determined by a[4:0] (0x00 through 0x1f). the alignment start point is a[4:0] = 0x00. 2. some degradation in performance may occur if this limit is exceeded, but the flash will continue to work properly. 3. if the internal address counter increments beyond the block's maximum address, addressing wraps around to the beginning of the block. 4. if the number of words is less than 32, remaining locations must be filled with 0xffff. 11.3.2 flash buffered efp setup phase after receiving the buffered efp setup and confirm command sequence, sr.7 (ready) is cleared, indicating that the wsm is busy with buffered efp algorithm startup. a delay before checking sr.7 is required to allow the wsm enough time to perform all of its setups and checks (block- lock status, f-v pp level, etc.). if an error is detected, sr.4 is set and buffered efp operation terminates. if the block was found to be locked, sr.1 is also set. sr.3 is set if the error occurred due to an incorrect f-v pp level. note: reading from the flash after the buffered efp setup and confirm command sequence outputs status register data. do not issue the read status register command; it will be interpreted as data to be loaded into the buffer. 11.3.3 flash buffered efp program/verify phase after the buffered efp setup phase has completed, the host programming system must check sr[7,0] to determine the availability of the write buffer for data streaming. sr.7 cleared indicates the flash is busy and the buffered efp program/verify phase is activated. sr.0 indicates the write buffer is available.
part 2: flash device operations flash programming operations intel pxa27x processor family memory subsystem 79 two basic sequences repeat in this phase: loading of the write buffer, followed by buffer data programming to the array. for buffered efp, the count value for buffer loading is always the maximum buffer size of 32-words. during the buffer-loading sequence, data is stored to sequential buffer locations starting at address 0x00. programming of the buffer contents to the flash memory array starts as soon as the buffer is full. if the number of words is less than 32, the remaining buffer locations must be filled with 0xffff. caution: the buffer must be completely filled for programming to occur. supplying an address outside of the current block's range during a buffer-fill sequence causes the algorithm to exit immediately. any data previously loaded into the buffer during the fill cycle is not programmed into the array. the starting address for data entry must be buffer size aligned, if not the buffered efp algorithm will be aborted and the program fail (sr.4) flag will be set. data words from the write buffer are directed to sequential memory locations in the flash memory array; programming continues from where the previous buffer sequence ended. the host programming system must poll sr.0 to determine when the buffer program sequence completes. sr.0 cleared indicates that all buffer data has been transferred to the flash array; sr.0 set indicates that the buffer is not available yet for the next fill cycle. the host system may check full status for errors at any time, but it is only necessary on a block basis after buffered efp exit. after the buffer fill cycle, no write cycles should be issued to the flash until sr.0 = 0 and the flash is ready for the next buffer fill. note: any spurious writes are ignored after a buffer fill operation and when internal program is proceeding. the host programming system continues the buffered efp algorithm by providing the next group of data words to be written to the buffer. alternatively, it can terminate this phase by changing the block address to one outside of the current blocks range. the program/verify phase concludes when the programmer writes to a different block address; data supplied must be 0xffff. upon program/verify phase completion, the flash enters the buffered efp exit phase. 11.3.4 flash buffered efp exit phase when sr.7 is set, the flash has returned to normal operating conditions. a full status check should be performed on the partition being programmed at this time to ensure the entire block programmed successfully. when exiting the buffered efp algorithm with a block address change, the read mode of both the programmed and the addressed partition will not change. after buffered efp exit, any valid command can be issued to the flash. 11.4 flash program suspend issuing the program suspend command while programming suspends the programming operation. this allows data to be accessed from memory locations other than the one being programmed. the program suspend command can be issued to any flash address; the corresponding partition is not affected. a program operation can be suspended to perform reads only. additionally, a program operation that is running during an erase suspend can be suspended to perform a read operation. see figure 53, flash program suspend/resume flowchart on page 114 .
part 2: flash device operations flash programming operations 80 intel? pxa27x processor family memory subsystem when a programming operation is executing, issuing the program suspend command requests the wsm to suspend the programming algorithm at predetermined points. the partition that is suspended continues to output srd after the program suspend command is issued. programming is suspended when sr[7,2] are set. suspend latency is specified in section 7.4, flash program and erase characteristics on page 51 . to read data from blocks within the suspended partition, the read array command must be issued to that partition. read array, read status register, read device identifier, cfi query, and program resume are valid commands during a program suspend. a program operation does not need to be suspended in order to read data from a block in another partition that is not programming. if the other partition is already in a read array, read device identifier, or cfi query state, issuing a valid address returns corresponding read data. if the other partition is not in a read mode, one of the read commands must be issued to the partition before data can be read. during a program suspend, deasserting f-ce# places the flash in standby, reducing active current. f-vpp must remain at its programming level, and f-wp# must remain unchanged while in program suspend. if f-rst# is asserted, the flash is reset. 11.5 flash program resume the resume command instructs the flash to continue programming, and automatically clears status register bits sr[7,2]. this command can be written to any partition. when read at the partition thats programming, the flash outputs data corresponding to the partitions last state. if error bits are set, the status register should be cl eared before issuing the next instruction. f-rst# must remain deasserted. see figure 53, flash program suspend/resume flowchart on page 114 . 11.6 flash program protection when f-v pp = v il , absolute hardware write protection is provided for all flash blocks. if f-v pp is below v pplk , programming operations halt and sr.3 is set indicating a f-v pp -level error. block lock registers are not affected by the voltage level on f-v pp ; they may still be programmed and read, even if f-v pp v pplk . . figure 26. example f-vpp supply connections ? f-v pph fast programming ? absolute write protection with f-v pp v pplk f-v cc (note 1) f-vcc f-vpp f-v pp f-vcc f-vpp ? f-v ppl for in-system programming ? f-v pph fast factory programming f-v cc f-v pp ? f-v ppl for in-system programming ? absolute write protection via logic signal f-v cc f-vcc f-vpp prot# (logic signal) ? f-v ppl for in-system programming f-v cc f-vcc f-vpp 10k ?
part 2: flash device operations flash erase operations intel pxa27x processor family memory subsystem 81 flash erase operations 12 flash erasing is performed on an individual block basis. an entire block is erased each time an erase command sequence is issued, and only one block is erased at a time. when a block is erased, all bits within that block read as logical ones. the following sections describe block erase operations in detail. 12.1 flash block erase block erase operations are initiated by writing the block erase setup command to the address of the target block to be erased. see section 9.3, flash command definitions on page 66 . next, the block erase confirm command is written to the address of the block to be erased. erasing can occur in only one partition at a time; all other partitions must be in a read state. if the flash is placed in standby (f-ce# deasserted) during an erase operation, the flash continues to complete the erase operation before entering standby. note: f-v pp > v pplk and the block must be unlocked (see figure 56, flash block erase flowchart on page 117 ). during a block erase, the flash write state machine (wsm) executes a sequence of internally- timed events that conditions, erases, and verifies all bits within the block. erasing the flash memory array changes logical-zeros to logical-ones. memory array bits can be changed to zeros only by programming the block (see section 11, flash programming operations on page 75 ). the status register can be examined for block erase progress and errors by reading any address within the partition that is being erased. the partition remains in the read status register state until another command is written to that partition. issuing the read status register command to another partition address sets that partition to the read status register state, allowing erase progress to be monitored at that partitions address. sr.0 indicates whether the addressed partition or another partition is erasing. the partitions status register bit sr.7 is set upon erase completion. sr.7 indicates block erase status while the sequence executes. when the erase operation has finished, status register bit sr.5 indicates an erase failure if set. sr.3 set would indicate that the wsm could not perform the erase operation because f-v pp was outside of its acceptable limits. sr.1 set indicates that the erase operation attempted to erase a locked block, causing the operation to abort. before issuing a new command, the status register contents should be examined and then cleared using the clear status register command. any valid command can follow once the block erase operation has completed. 12.2 flash erase suspend issuing the erase suspend command while erasing suspends the block erase operation. this allows data to be accessed from memory locations other than the one being erased. the erase suspend command can be issued to any flash address; the corresponding partition is not affected. a block
part 2: flash device operations flash erase operations 82 intel? pxa27x processor family memory subsystem erase operation can be suspended to perform a word or buffer program operation, or a read operation within any block except the block that is erase suspended. see figure 53, flash program suspend/resume flowchart on page 114 . when a block erase operation is executing, issuing the erase suspend command requests the wsm to suspend the erase algorithm at predetermined points. the partition that is suspended continues to output srd after the erase suspend command is issued. block erase is suspended when sr[7,6] are set. suspend latency is specified in section 7.4, flash program and erase characteristics on page 51 . during erase suspend, a program command can be issued to any block other than the erase- suspended block. block erase cannot resume until program operations initiated during erase suspend complete. read array, read status register, read device identifier, cfi query, and erase resume are valid commands during erase suspend. additionally, clear status register, program, program suspend, block lock, block unlock, and block lock-down are valid commands during erase suspend. during an erase suspend, deasserting f-ce# places the flash in standby, reducing active current. f-v pp must remain at a valid level, and f-wp# must remain unchanged while in erase suspend. if f-rst# is asserted, the flash is reset. 12.3 flash erase resume the erase resume command instructs the flash to continue erasing, and automatically clears status register bits sr[7,6]. this command can be written to any partition. when read at the partition thats erasing, the flash outputs data corresponding to the partitions last state. if status register error bits are set, the status register should be cl eared before issuing the next instruction. f-rst# must remain deasserted (see figure 53, flash program suspend/resume flowchart on page 114 ). 12.4 flash erase protection when f-v pp = v il , absolute hardware erase protection is provided for all flash blocks. if f-v pp v pplk , erase operations halt and sr.3 is set indicating a f-v pp level error.
part 2: flash device operations flash security modes intel pxa27x processor family memory subsystem 83 flash security modes 13 the flash features security modes used to protect the code or data information stored in the flash memory array. the following sections describe each security mode in detail. 13.1 flash block locking individual instant block locking is used to protect user code and/or data within the flash memory array. all blocks power up in a locked state to protect array data from being altered during power transitions. any block can be locked or unlocked with no latency. locked blocks cannot be programmed or erased; they can only be read. software-controlled security is implemented using the block lock and block unlock commands. hardware-controlled security can be implemented using the block lock-down command along with asserting f-wp#. 13.1.1 flash lock block to lock a block, issue the lock block setup command. the next command must be the lock block command issued to the desired blocks address (see section 9.3, flash command definitions on page 66 and figure 58, flash block lock operations flowchart on page 119 ). if the set read configuration register command is issued after the block lock setup command, the flash configures the rcr instead. block lock and unlock operations are not affected by the voltage level on f-v pp . the block lock bits may be modified and/or read even if f-v pp v pplk . 13.1.2 flash unlock block the unlock block command is used to unlock blocks (see section 9.3, flash command definitions on page 66 ). unlocked blocks can be read, programmed, and erased. unlocked blocks return to a locked state when the flash is reset or powered down. if a block is in a lock-down state, wp# must be deasserted before it can be unlocked (see figure 27, flash block locking state diagram on page 84 ). 13.1.3 flash lock-down block a locked or unlocked block can be locked-down by writing the lock-down block command sequence (see section 9.3, flash command definitions on page 66 ). blocks in a lock-down state cannot be programmed or erased; they can only be read. however, unlike locked blocks, their locked state cannot be changed by software commands alone. a locked-down block can only be unlocked by issuing the unlock block command with f-wp# deasserted. to return an unlocked block to locked-down state, a lock-down command must be issued prior to changing f-wp# to v il . locked-down blocks revert to the locked state upon reset or power up the flash (see figure 27, flash block locking state diagram on page 84 ).
part 2: flash device operations flash security modes 84 intel? pxa27x processor family memory subsystem 13.1.4 flash block lock status the read device identifier command is used to determine a blocks lock status (see section 15.2, flash read device identifier on page 95 ). data bits dq[1:0] display the addressed blocks lock status; dq0 is the addressed blocks lock bit, while dq1 is the addressed blocks lock-down bit. 13.1.5 flash block locking during suspend block lock and unlock changes can be performed during an erase suspend. to change block locking during an erase operation, first issue the erase suspend command. monitor the status register until sr.7 and sr.6 are set, indicating the flash is suspended and ready to accept another command. next, write the desired lock command sequence to a block, which changes the lock state of that block. after completing block lock or unlock operations, resume the erase operation using the erase resume command. note: a lock block setup command followed by any command other than lock block, unlock block, or lock-down block produces a command sequence error and set status register bits sr.4 and sr.5. if a command sequence error occurs during an erase suspend, sr.4 and sr.5 remains set, even after the erase operation is resumed. unless the status register is cleared using the clear status register command before resuming the erase operation, possible erase errors may be masked by the command sequence error. if a block is locked or locked-down during an erase suspend of the same block, the lock status bits change immediately. however, the erase operation completes when it is resumed. block lock operations cannot occur during a program suspend. figure 27. flash block locking state diagram [x00] [x01] power-up/reset unlocked locked [011] [111] [110] locked- down 4,5 software locked [011] hardware locked 5 unlocked f-wp# hardware control notes: 1. [a,b,c] represents [f-wp#, d1, d0]. x = dont care. 2. d1 indicates block lock-down status. d1 = 0, lock-down has not been issued to this block. d1 = 1, lock-down has been issued to this block. 3. d0 indicates block lock status. d0 = 0, block is unlocked. d0 = 1, block is locked. 4. locked-down = hardware + software locked. 5. [011] states should be tracked by system software to determine difference between hardware locked and locked-down states. software block lock ( 0x60/0x01) or software block unlock (0x60/0xd0) software block lock- down (0x60/0x2f) f- w p# har dwar e control
part 2: flash device operations flash security modes intel pxa27x processor family memory subsystem 85 13.2 flash one-time programmable protection registers the flash contains seventeen protection registers (prs) that can be used to implement system security measures and/or flash identification. ea ch protection register can be individually locked. the first 128-bit protection register (pr0) is comprised of two 64-bit (8-word) segments. the lower 64-bit segment is pre-programmed at the factory with a unique 64-bit number. the remaining 64-bit segment, as well as the other sixteen 128-bit protection registers, are blank as default. users can program these registers as needed. when programmed, users can then lock the protection register(s) to prevent additional bit programming. see figure 28, flash one-time programmable protection register map on page 86 . the user-programmable protection registers contain one-time programmable (otp) bits; when programmed, register bits cannot be erased. each protection register can be accessed multiple times to program individual bits, as long as the register remains unlocked. each protection register has an associated lock register bit. when a lock register bit is programmed, the associated protection register can only be read; it can no longer be programmed. additionally, because the lock register bits themselves are otp, when programmed, lock register bits cannot be erased. therefore, when a protection register is locked, it cannot be unlocked
part 2: flash device operations flash security modes 86 intel? pxa27x processor family memory subsystem . 13.2.1 flash reading of the protection registers the protection registers can be read from within any partitions address space. to read the protection register, first issue the read flash identifier command at any partitions address to place that partition in the read device identifier state (see section 9.3, flash command definitions on page 66 ). next, perform a read operation at that partitions base address plus the address offset corresponding to the register to be read. table 28, flash die identifier information on page 96 shows the address offsets of the protection registers and lock registers. register data is read 16 bits at a time. note: if a program or erase operation occurs within the flash while it is reading a protection register, certain restrictions may apply. see table 26, simultaneous flash operation restrictions on page 92 for details. figure 28. flash one-time programmable protection register map 0x89 lock register 1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0x102 0x109 0x8a 0x91 128-bit protection register 16 (user-programmable) 128-bit protection register 1 (user-programmable) 0x88 0x85 64-bit segment (user-programmable) 0x84 0x81 0x80 lock register 0 64-bit segment (factory-programmed) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 128-bit protection register 0
part 2: flash device operations flash security modes intel pxa27x processor family memory subsystem 87 13.2.2 flash programming of the protection registers to program any of the protection registers, first issue the program protection register command at the parameter partitions base address plus the offset to the desired protection register (see section 9.3, flash command definitions on page 66 ). next, write the desired protection register data to the same protection register address (see figure 28, flash one-time programmable protection register map on page 86 ). the flash programs the 64-bit and 128-bit user-programmable protection register data 16 bits at a time (see figure 59, flash one-time programmable protection register programming flowchart on page 120 ). issuing the program protection register command outside of the protection registers address space causes a program error (sr.4 set). attempting to program a locked protection register causes a program error (sr.4 set) and a lock error (sr.1 set). note: if a program or erase operation occurs when programming a protection register, certain restrictions may apply. see table 26, simultaneous flash operation restrictions on page 92 for details. 13.2.3 flash locking the protection registers each protection register can be locked by programming its respective lock bit in the lock register. to lock a protection register, progra m the corresponding bit in the lock register by issuing the program lock register command, followed by the desired lock register data (see section 9.3, flash command definitions on page 66 ). the physical addresses of the lock registers are 0x80 for register 0 and 0x89 for register 1. these addresses are used when programming the lock registers. see table 28, flash die identifier information on page 96 . bit 0 of lock register 0 is already programmed at the factory, locking the lower, pre-programmed 64-bits region of the first 128-bit protection register containing the unique identification number of the flash. bit 1 of lock register 0 can be programmed by the user to lock the user- programmable, 64-bits region of the first 128-bi ts protection register. the other bits in lock register 0 are not used. lock register 1 controls the locking of the upper sixteen 128-bit protection registers. each of the 16 bits of lock register 1 correspond to each of the upper sixteen 128-bit protection registers. programming a bit in lock register 1 locks the corresponding 128-bit protection register. caution: after being locked, the protection registers cannot be unlocked.
part 2: flash device operations flash security modes 88 intel? pxa27x processor family memory subsystem
part 2: flash device operations flash dual-operation considerations intel pxa27x processor family memory subsystem 89 flash dual-operation considerations 14 the multi-partition architecture of the flash allows background programming (or erasing) to occur in one partition while data reads (or code execution) take place in another partition. 14.1 flash partitioning the flash memory array is divided into multiple 16-mbit partitions, which allows simultaneous read-while-write operations. simultaneous program and erase is not allowed. only one partition at a time can be in program or erase mode. the flash supports read-while-write operations with bus cycle granularity and not command granularity. in other words, it is not assumed that both bus cycles of a two cycle command (an erase command for example) will always occur as back to back bus cycles to the flash. in practice, code fetches (reads) may be interspersed between write cycles to the flash, and they will likely be directed to a different partition than the one being written. this is especially true when a processor is executing code from one partition that instructs the processor to program or erase in another partition. 14.2 flash read-while-write command sequences when issuing commands to the flash, a read operation can occur between 2-cycle write commands ( figure 29 , and figure 30 ). however, a write operation issued between a 2-cycle commands write sequence causes a command sequence error. (see figure 31, flash operating mode with illegal command sequence example on page 90 ) when reading from the same partition after issuing a setup command, status register data is returned, regardless of the read mode of the partition prior to issuing the setup command. figure 29. flash operating mode with correct command sequence example partition a partition a partition b 0x20 0xd0 0xff a ddress [a] we# [w] oe# [g] data [d/q]
part 2: flash device operations flash dual-operation considerations 90 intel? pxa27x processor family memory subsystem 14.2.1 simultaneous flash operation details the flash supports simultaneous read from one partition while programming or erasing in any other partition. certain features like the protection registers and query data have special requirements with respect to simultaneous operation capability. these will be detailed in the following sections. 14.2.2 flash write to flash asynchronous read transition the ac parameter w18 (t whav - we# high to address valid) is required when transitioning from a write cycle (we# going high) to perform an asynchronous read (only address valid is required). 14.2.3 flash write to flash synchronous read operation transition the flash ac parameters w19 (t whcv : we# high to clock valid) and w20 (t whvh : we# high to adv# high) are required when transitioning from a write cycle (we# going high) to perform a synchronous burst read. a delay from we# going high to a valid clock edge or adv# going high to latch a new address must be met. 14.2.4 flash write with clock active the flash ac parameters w21 (t vhwl : adv# high to we# low) and w22 (t chwl : clock high to we# low) are required during write operations when the flash is in a synchronous mode and the clock is active. a write bus cycle consists of two parts: figure 30. flash operating mode with correct command sequence example figure 31. flash operating mode with illegal command sequence example partition a partition b partition a 0x20 valid array data 0xd0 a ddress [a] we# [w] oe# [g] data [d/q] partition a partition b partition a partition a 0x20 0xff 0xd0 sr[7:0] a d d re ss [ a ] we# [w] oe# [g] data [d/q]
part 2: flash device operations flash dual-operation considerations intel pxa27x processor family memory subsystem 91 ? the processor provides an address to the flash. ? the processor then provides data to the flash. the flash in turn binds the received data with the received address. when operating synchronously (rcr.15 = 0), the address of a write cycle may be provided to the flash by the first active clock edge with adv# low, or rising edge of adv# as long as the applicable cycle separation conditions are met between each cycle. if neither a clock edge nor a rising adv# edge is used to provide a new address at the beginning of a write cycle (the clock is stopped and adv# is low), the address may also be provided to the flash by holding the address bus stable for the required amount of time (w5, t av w h ) before the rising we# edge. alternatively, the host may choose not to provide an address to the flash during subsequent write cycles (if adv# is high and only f-ce# or we# is toggled to separate the prior cycle from the current write cycle). in this case, the flash will use the most recently provided address from the host. for representation of these timings see: ? figure 20, flash write to flash asynchronous read timing on page 49 ? figure 21, flash synchronous read to flash write timing on page 49 ? figure 22, flash write to flash synchronous read timing on page 50 14.2.5 flash read during flash buffered programming the multi-partition architecture of the flash allows background programming (or erasing) to occur in one partition while data reads (or code execution) take place in another partition. to perform a read while buffered programming operation, first issue a buffered program set up command in a partition. when a read operation occurs in the same partition after issuing a setup command, status register data will be returned, regardless of the read mode of the partition prior to issuing the setup command. to read data from a block in other partition and the other partition already in read array mode, a new block address must be issued. however, if the other partition is not already in read array mode, issuing a read array command will cause the buffered program operation to abort and a command sequence error would be posted in the status register. simultaneous read-while-buffered efp is not supported. 14.3 simultaneous flash operation restrictions since the flash supports simultaneous read from one partition while programming or erasing in another partition, certain features like the protection registers and cfi query data have special requirements with respect to simultaneous operation capability. ( table 26 provides details on restrictions during simultaneous operations.)
part 2: flash device operations flash dual-operation considerations 92 intel? pxa27x processor family memory subsystem table 26. simultaneous flash operation restrictions protection register or cfi data parameter partition array data other partitions notes read (see notes) write/erase while programming or erasing in a main partition, the protection register or cfi data may be read from any other partition. reading the parameter partition array data is not allowed if the protection register or query data is being read from addresses within the parameter partition. (see notes) read write/erase while programming or erasing in a main partition, read operations are allowed in the parameter partition. accessing the protection registers or cfi data from parameter partition addresses is not allowed when reading array data from the parameter partition. read read write/erase while programming or erasing in a main partition, read operations are allowed in the parameter partition. accessing the protection registers or cfi data in a partition that is different from the one being programed/erased, and also different from the parameter partition is allowed. write no access allowed read while programming the protection register, reads are only allowed in the other main partitions. access to array data in the parameter partition is not allowed. programming of the protection register can only occur in the parameter partition, which means this partition is in read status. no access allowed write/erase read while programming or erasing the parameter partition, reads of the protection registers or cfi data are not allowed in any partition. reads in partitions other than the parameter partition are supported.
part 2: flash device operations special flash read states intel pxa27x processor family memory subsystem 93 special flash read states 15 the following sections describe non-array read states. non-array reads can be performed in asynchronous read or synchronous burst mode. a non-array read operation occurs as asynchronous single-word mode. when non-array reads are performed in asynchronous page mode only the first data is valid and all subsequent data are undefined. when a non-array read operation occurs as synchronous burst mode, the same word of data requested will be output on successive clock edges until the burst length requirements are satisfied. each partition can be in one of its read states independent of other partitions modes. see figure 12, flash asynchronous single-word read with adv# low on page 43 and figure 15, flash synchronous single-word array or non-array read timing on page 45 for details. 15.1 flash read status register the status of any partition is determined by reading the status register from the address of that particular partition. to read the status register, issue the read status register command within the desired partitions address range. status register information is available at the partition address to which the read status register, word program, or block erase command was issued. status register data is automatically made available following a word program, block erase, or block lock command sequence. reads from a partition after any of these command sequences outputs that partitions status until another valid command is written to that partition (e.g. read array command). the status register is read using single asynchronous-mode or synchronous burst mode reads. status register data is output on dq[7:0], while 0x00 is output on dq[15:8]. in asynchronous mode the falling edge of oe#, or f-ce# (whichever occurs first) updates and latches the status register contents. however, reading the status register in synchronous burst mode, f-ce# or adv# must be toggled to update status data. the status register read operations do not affect the read state of the other partitions. the flash write status bit (sr.7) provides overall st atus of the flash. the partition status bit (sr.0) indicates whether the addressed partition or some other partition is actively programming or erasing. status register bits sr[6:1] present stat us and error information about the program, erase, suspend, f-v pp , and block-locked operations.
part 2: flash device operations special flash read states 94 intel? pxa27x processor family memory subsystem always clear the status register prior to resuming erase operations to avoid status register ambiguity when issuing commands during erase suspend. if a command sequence error occurs during an erase-suspend state, the status register contains the command sequence error status (sr[7,5,4] are set). when the erase operation resumes and finishes, possible errors during the erase operation cannot be detected by the status register because it contains the previous error status. 15.1.1 flash clear status register the flash clear status register command clears the status register, leaving all partition read states unchanged. it functions independent of f-v pp . the write state machine (wsm) sets and clears sr[7,6,2,0], but it sets bits sr[5:3,1] without clearing them. the status register should be cleared before starting a command sequence to avoid any ambiguity. a flash reset also clears the status register. table 27. flash status register description status register (sr) default value = 0x80 flash write status erase suspend status erase status program status f-vpp status program suspend status block- locked status partition status dws ess es ps f-vpps pss bls pws 76543210 bit name description 7 flash write status (dws) 0 = flash is busy; program or erase cycle in progress; sr.0 valid. 1 = flash is ready; sr[6:1] are valid. 6 erase suspend status (ess) 0 = erase suspend not in effect. 1 = erase suspend in effect. 5 erase status (es) 0 = erase successful. 1 = erase fail or program sequence error when set with sr[4,7]. 4 program status (ps) 0 = program successful. 1 = program fail or program sequence error when set with sr[5,7] 3 f-vpp status (f-vpps) 0 = f-v pp within acceptable limits during program or erase operation. 1 = f-v pp v pplk during program or erase operation. 2 program suspend status (pss) 0 = program suspend not in effect. 1 = program suspend in effect. 1 block locked status (bls) 0 = block not locked during program or erase. 1 = block locked during program or erase; operation aborted. 0 partition write status (pws) dws pws 0 0 = program or erase operation in addressed partition. 0 1 = program or erase operation in other partition. 1 0 = no active program or erase operations. 1 1 = reserved. (for buffered efp operation, see section 11.3, flash buffered enhanced factory programming on page 77 )
part 2: flash device operations special flash read states intel pxa27x processor family memory subsystem 95 15.2 flash read device identifier the read device identifier command instructs the addressed partition to output manufacturer code, device identifier code, block-lock status, pr otection register data, or configuration register data when that partitions addresses are read (see section 9.3, flash command definitions on page 66 for details on issuing the read device identifier command). table 28, flash die identifier information on page 96 show the address offsets and data values for this flash. issuing a read device identifier command to a partition that is programming or erasing places that partition in the read identifier state while the partition continues to program or erase in the background.
part 2: flash device operations special flash read states 96 intel? pxa27x processor family memory subsystem 15.3 cfi query the cfi query command instructs the flash to output common flash interface (cfi) data when partition addresses are read. see section 9.3, flash command definitions on page 66 for details on issuing the cfi query command. appendix b, common flash interface on page 121 shows cfi information and address offsets within the cfi database. issuing the cfi query command to a partition that is programming or erasing places that partitions outputs in the cfi query state, while the partition continues to program or erase in the background. the cfi query command is subject to read restrictions dependent on parameter partition availability, as described in table 26, simultaneous flash operation restrictions on page 92 . table 28. flash die identifier information item address (1,2) data manufacturer code pba + 0x00 0089h flash id code pba + 0x01 8810 block lock configuration: bba + 0x02 lock bit: ? block is unlocked dq0 = 0b0 ? block is locked dq1 = 0b1 ? block is not locked-down dq0 = 0b0 ? block is locked-down dq1 = 0b1 configuration register pba + 0x05 configuration register data lock register 0 pba + 0x80 pr-lk0 64-bit factory-programmed protection register pba + 0x81C0x84 factory protection register data 64-bit user-programmable protection register pba + 0x85C0x88 user protection register data lock register 1 pba + 0x89 protection register data 16x128-bit user-programmable protection registers pba + 0x8aC0x109 pr-lk1 notes: 1. pba = partition base address. 2. bba = block base address.
intel? pxa27x processor family memory subsystem 97 part 3: lpsdram operations
98 intel? pxa27x processor family memory subsystem 16xxx
part 3: lpsdram operations lsdram register definition intel pxa27x processor family memory subsystem 99 lsdram register definition 16 16.1 mode register the mode register is used to define specific modes of operation of the lpsdram. this definition includes the selection of a burst length, burst type, a cas# latency, and a write burst mode. the mode register settings are illustrated in the table below. the mode register is programmed by the load mode register command and will retain the information until it is reprogrammed, the lpsdram loses power, or the lpsdram goes in deep power-down mode. the register should be loaded when all banks are idle, and subsequent operation should only be initiated after t mrd . addresses a[12:11, 9:8] must be set to 0 for all mode register programming. d-ba[1:0] should be set to (0,0) to differentiate from extended mode register programming. notes: 1. states not mentioned are undefined. 2. the sequential burst will wrap on reaching the last column of the burst length. note: cas# latency not mentioned are undefined. table 29. lpsdram setting for burst length burst length a3 a2 a1 a4 = 0 a4 = 1 1 1 000 2 2 001 4 4 010 8 8 011 full page reserved 1 1 1 table 30. lpsdram setting for burst type a4 burst type 0 sequential 1 interleaved table 31. lpsdram setting for cas# latency a7 a6 a5 cas# latency 001 1 010 2 011 3
part 3: lpsdram operations lsdram register definition 100 intel? pxa27x processor family memory subsystems 16.2 lpsdram extended mode register the extended mode register controls two power saving functions: temperature-compensated self refresh (tcsr), and partial-array self refresh (p asr). both these features can only be used when the lpsdram is under self refresh. in addi tion, the configurable output driver strength can be programmed through the extended mode register. the extended mode register is programmed by the load mode register command and will retain the information until it is reprogrammed, the lpsdram loses power, or the lpsdram goes in deep power down mode. the register should be loaded when all banks are idle, and subsequent operation should only be initiated after t mrd . to program the extended mode register, bank addresses d-ba1 = 1, and d-ba0 = 0 should be used. addresses a[12:6] should be set to '0'. table 32. lpsdram setting for write burst mode a10 write burst mode 0 programmed burst 1 single word burst table 33. lpsdram setting for partial-array self refresh a3 a2 a1 self-refresh coverage 000 four banks 0 0 1 two banks (bank 0 & bank 1) 0 1 0 one bank (bank 0) table 34. lpsdram setting for temperature-compensated self refresh a5 a4 maximum ambient temperature 11 85 c 00 70 c 01 45 c 10 15 c table 35. lpsdram configurable output driver strength a7 a6 strength output load (pf) 0 0 normal 30 01 half tbd 1 0 reserved na 1 1 reserved na note: lpsdram ac specs are guaranteed only when normal output driver strength is used.
part 3: lpsdram operations lpsdram command and operation intel pxa27x processor family memory subsystem 101 lpsdram command and operation 17 17.1 lpsdram no operation / lpsdram deselect the no operation / lpsdram deselect command is used on a lpsdram that is selected (d-cs# / r-ds# is low). it is also used to deselect the lpsdram by preventing new commands from being executed. operations already in progress are not affected. 17.2 lpsdram active the active command is used to activate a row in particular bank for a subsequent read or write access. the value of the bank d-ba[1:0] and the row address needs to be provided. the row remains active until a precharge command is issued to the bank. a precharge command must be issued before opening a different row in the same bank. more than one bank can be active at any time. a read or write command could be issued to that row, subject to the t rcd specification. t rcd (min) should be divided by the clock period and rounded up to the next whole number to determine the earliest clock edge after the active command on which the read/write can be entered. a subsequent active command to another row in the same bank can only be issued after the previous row has been closed. the minimum time interval between two successive active commands on the same bank is defined by t rc . the minimum time interval between two successive active commands on the different banks is defined by t rrd . this is illustrated in figure 34 on page 104 . 17.3 lpsdram read command read command is used to initiate a burst read to an active row. the value of d-ba[1:0] select the bank and address inputs select the starting column location. the value of a11 determines whether or not auto precharge is used. output data appears on the data bus, subject to the logic level on the d-dm[1:0] inputs two clocks earlier. d-dm[1:0] latency for read command is 2 clock cycles. the burst length is set in the mode register. the starting column and bank address is provided along with the auto precharge option. during read bursts, the starting valid data-out corresponding to the starting column address will be available after cas latency cycles after the read command. each subsequent data-out will be valid by the next positive edge of the clock. this is shown in figure 35, lpsdram example of cas# latency, cl = 2 on page 105 with a cas latency of 2. data from a read burst may be truncated by a subsequent read command. the first data from the new burst follows either the last element of a completed burst or the last desired element of a longer burst that is being truncated. the new read command can be issued as early as cl-1 cycles before the last desired element. this is shown in figure 36, consecutive lpsdram read bursts with cl = 2 on page 105 . figure 37 on page 105 shows random lpsdram access reads. these can be issued to the same or different banks.
part 3: lpsdram operations lpsdram command and operation 102 intel? pxa27x processor family memory subsystems a read burst can be terminated by a subsequent write command, and data from a fixed length read burst can be followed by a write command. the write command may be initiated on the clock edge immediately following the last data element from the read burst, provided the i/o contention could be avoided. d-dm[1:0] can be used to control i/o contention as shown in figure 38, lpsdram read to lpsdram write command on page 106 . d-dm[1:0] latency is 2 clocks for output buffers masking, so the d-dm[1:0] signal must be set high at least 2 clocks prior to the write command. d-dm[1:0] latency for write is zero clocks, so d-dm[1:0] must be set low before write command to ensure data written is not masked. a read burst may be followed by or truncated with a precharge command, which could be issued cl-1 cycles before the last desired element. this is shown in figure 39, lpsdram read command followed by precharge on page 106 . following precharge command, another command to the same bank cannot be issued until t rp is met. similarly burst terminate command can be used to stop a burst as shown in figure 40, lpsdram read followed by burst terminate on page 106 . 17.4 lpsdram write command the write command is used to initiate a burst write access to an active row. the value of d-ba[1:0] select the bank and address inputs select the starting column location. the value of a11 determines whether or not auto precharge is used. input data appearing on the data bus, is written to the memory array subject to the d-dm[1:0] input logic level appearing coincident with the data. d-dm[1:0] latency for write command is 0-clock cycle. the burst length is set in the mode register. the starting column and bank address is provided along with the auto precharge option. the first valid data-in is registered coincident with the write command. subsequent data elements will be registered on each successive positive clock edge. figure 39, lpsdram read command followed by precharge on page 106 shows 2 consecutive 4 word write bursts. a write burst may be followed by or truncated with a precharge command to the same bank. the precharge should be issued t wr after the clock edge after the last desired input data is entered. in addition, when truncating a write burst, the d-dm[1:0] signal must be used to mask input data for the clock edge coincident with the precharge command. this is shown in figure 42 and figure 43 on page 107 , where t wr corresponds to either 1 or 2 clock cycles, respectively. following the precharge command, a subsequent command cannot be issued to the same bank until t rp is met. write burst can be truncated with a burst te rminate command. while truncating, the input data being applied coincident to the burst terminate will be ignored. data for any writes may be truncated by a subsequent read command as shown in figure 44 on page 108 . once the read command is registered, the data inputs will be ignored. 17.5 lpsdram power-down power down occurs if d-cke is set low coincident with lpsdram deselect or nop command and when no accesses are in progress. if power down occurs when all banks are idle, it is precharge power-down. if power down occurs when one or more banks are active, it is referred to as active power down. the lpsdram cannot stay in this mode for longer than the refresh period (64 ms) without losing data. the power down state is exited by setting d-cke high while issuing a lpsdram deselect or nop command. this is shown in figure 45 on page 108 .
part 3: lpsdram operations lpsdram command and operation intel pxa27x processor family memory subsystem 103 17.6 lpsdram deep power-down the deep power-down (dpd) mode enables very low standby currents. all internal voltage generators inside the lpsdram are stopped and all memory data are lost in this mode. to enter the dpd mode, all banks must be precharged, prior to the dpd command. to exit this mode, the d-cke is taken high after the clock is stable. 17.7 lpsdram clock suspend this mode occurs when a column access or burst is in progress, and d-cke is set low. the internal clock gets suspended freezing the lpsdram logi c. any command or data present on the input pins at the time of suspended internal clock is ignored. the output data on the pins stays frozen. this mode is exited by setting d-cke high, which results in resumption of the operation. figure 46 on page 108 shown clock suspend during a write burst and figure 47 on page 109 shows a clock suspend during a read burst. 17.8 lpsdram precharge the precharge is used to deactivate an active row in a particular bank or active row in all banks. the banks will be available for row access after a specified time (t rp ) after the precharge command is issued. if one bank is to precharged, the particular bank address needs to be addressed. if all banks are to be precharged, a11 should be set high along with the precharge command. 17.9 lpsdram auto precharge auto precharge is accomplished when a11 is high, to enable auto precharge in conjunction with a specific read or write command. this precharges the row after the read or write burst is complete. auto precharge ensures that a precharge is initiated at the earliest valid stage within a burst. another command to the same bank must not be issued until the precharge time (t rp ) is completed. auto precharge does not apply in full-page burst mode. auto precharge is non- persistent. 17.10 lpsdram concurrent auto precharge if an access command with auto precharge enabled is being executed, it can be interrupted by another access command. ? figure 48 on page 109 shows a read with auto precharge to bank n, interrupted by a read (with or without auto precharge) to bank m. the read to bank m will interrupt the read to bank n, cas# latency later. the precharge to bank n will begin when the read to bank m is registered. ? figure 49 on page 109 shows a read with auto precharge to bank n, interrupted by a write (with or without auto precharge) to bank m. the precharge to bank n will begin when the write to bank m is registered. d-dm[1:0] should be set high 2 clock before the write command to prevent bus contention.
part 3: lpsdram operations lpsdram command and operation 104 intel? pxa27x processor family memory subsystems ? figure 50 on page 110 shows a write with auto precharge to bank n, interrupted by a read (with or without auto precharge) to bank m. the new command initiates bank n write recovery (t wr ) followed by precharge. the last valid data-in to bank n is 1 clock prior to the read to bank m. ? figure 51 on page 110 shows a write with auto precharge to bank n, interrupted by a write (with or without auto precharge) to bank m. the new command initiates bank n write recovery (t wr ) followed by precharge. the last valid data-in to bank n is 1 clock prior to the write to bank m. figure 32. lpsdram auto refresh cycles with d-cke high figure 33. lpsdram self refresh entry and exit mode figure 34. lpsdram active command and lpsdram read access command issued to 2 different banks t0 t1 t2 tn tm t rp t rfc t rfc command precharge nop auto refresh auto refresh active r-clk t0 t1 t2 tn tm t rp command precharge nop auto refresh nop auto refresh t srex > t ras r-clk d-cke t0 t1 t2 t3 t4 t5 t6 t7 command active nop read-ap nop active nop read-ap nop t rcd, bank 0 address bk 0/row bk 0/col a bk 1/row bk1/ col b t rrd data i/o dout - a dout-a+1 dout-a+2 t ras, bank 0 r-clk
part 3: lpsdram operations lpsdram command and operation intel pxa27x processor family memory subsystem 105 figure 35. lpsdram example of cas# latency, cl = 2 figure 36. consecutive lpsdram read bursts with cl = 2 note: new command should be issued cl-1 clock cycles before the last desired data. new command can be used to truncate previous read burst. figure 37. random lpsdram read access with cl = 2 t0 t1 t2 t3 read nop nop nop dou t thz tch tac tlz cl=2 cl=2 r-clk command data i/o r-clk t0 t1 t2 t3 t4 t5 t6 command read nop nop nop read nop nop address bk n /col a bk any/col b data i/o dout - a dout-a+1 dout-a+2 dout - a+3 dout - b cl - 1 r-clk t0 t1 t2 t3 t4 t5 t6 commandread readreadreadnop nop nop address bk any/col a bk any/col b bk any/col c bk any/col d data i/o dout - a dout - b dout - c dout - d
part 3: lpsdram operations lpsdram command and operation 106 intel? pxa27x processor family memory subsystems figure 38. lpsdram read to lpsdram write command note: data masking used to prevent i/o contention. figure 39. lpsdram read command followed by precharge note: command issued cl-1 clocks before last desired data-out element. figure 40. lpsdram read followed by burst terminate r-clk t0 t1 t2 t3 t4 command read nop nop nop write address bk n /col a bk any/col b data i/o dout - a dout-a+1 din - b d-dm r-clk t0 t1 t2 t3 t4 t5 t6 t7 command read nop nop nop precharge nop nop active address bk n /col a bk n/all bk/row data i/o dout - a dout-a+1 dout-a+2 dout - a+3 cl - 1 cl=2 t0 t1 t2 t3 t4 t5 t6 command read nop nop nop brst term nop nop address bk n /col a data i/o dout - a dout-a+1 dout-a+2 dout - a+3 cl - 1 cl=2 r-clk
part 3: lpsdram operations lpsdram command and operation intel pxa27x processor family memory subsystem 107 figure 41. random lpsdram write to 4-word bursts note: the commands can be to any active bank. figure 42. lpsdram write to precharge command where write recovery takes 1 clock cycle figure 43. lpsdram write to precharge command where write recovery takes 2 clock cycles t0 t1 t2 t3 t4 t5 t6 clk command write nop nop nop write nop nop address bk n /col a bk any/col b data i/o din - a din-a+1 din-a+2 din - a+3 din - b din - b+1 din - b+2 r-clk t0 t1 t2 t3 t4 t5 t6 clk dqm command write nop precharge nop nop active nop t rp address bk n /col a bk a/all bk any/col b t wr data i/o din - a din-a+1 r-clk d-dm r-clk d-dm t0 t1 t2 t3 t4 t5 t6 command write nop nop precharge nop nop active t rp address bk n /col a bk a/all bk any/col b t wr data i/o din - a din-a+1
part 3: lpsdram operations lpsdram command and operation 108 intel? pxa27x processor family memory subsystems figure 44. lpsdram write command followed by lpsdram read command note: the read and write command can be done to any bank. (cl = 2) figure 45. lpsdram precharge power-down mode note: all banks are idle with d-cke low. figure 46. lpsdram clock suspend during lpsdram write burst note: input data is ignored when internal clock is suspended. t0 t1 t2 t3 t4 t5 clk command write nop read nop nop nop address bk n /col a bk a ny /col b data i/o din - a din - a+1 dout - b dout - b+1 cl=2 r-clk t0 t1 t2 tn tn+1 clk cke two clk cycles command precharge nop nop nop active all banks a10 row single bank ba0, ba1 bank row data i/o high-z d-cke a11 d-ba[1:0] r-clk t0 t1 t2 t3 t4 t5 clk cke internal clock commandnopwrite nopnop address bk n /col a bk any/col b data i/o din - a din - a+1 din - a+2 d-cke r-clk
part 3: lpsdram operations lpsdram command and operation intel pxa27x processor family memory subsystem 109 figure 47. lpsdram clock suspend during lpsdram read burst (cl = 2) note: output data gets frozen while internal clock is suspended. figure 48. lpsdram read with auto precharge to bank n interrupted by read to bank m figure 49. lpsdram read with auto precharge to bank n interrupted by write to bank m t0 t1 t2 t3 t4 t5 t6 clk cke internal clock command read nop nop nop nop nop address bk n /col a data i/o dout - a dout-a+1 dout - a+2 dout - a+3 d-cke r-clk t0 t1 t2 t3 t4 t5 t6 bank n bank m command nop read-ap nop read-ap nop nop nop t rp , bank n bank n page active read burst interrupt burst, precharge idle bank m page active read burst address bk n /col a bk m/col b cl=2 data i/o dout - a dout - a+1 dout - b dout - b+1 r-clk t0 t1 t2 t3 t4 t5 t6 bank n bank m command nop read-ap nop nop write-ap nop nop t rp , bank n bank n page active read burst interrupt burst, precharge bank m page active write burst address bk n /col a bk m/col b cl=2 data i/o dout - a din - b din - b+1 din - b+2 r-clk d-dm
part 3: lpsdram operations lpsdram command and operation 110 intel? pxa27x processor family memory subsystems 17.11 lpsdram burst terminate this command is used to truncate bursts. the most recent command prior to the burst terminate command will be truncated. 17.12 lpsdram auto refresh this command is used during normal operation of the lpsdram. this command is non- persistent. all banks must be idle before issuing auto refresh command. this command can be issued after a minimum of t rp after the precharge command. the address bits are "don't care" during the auto refresh command. as an example, the 256-mbit lpsdram requires 4096 auto refresh cycles (4096 rows/bank) every 64 ms (t ref ). providing a distributed auto refresh command every 15.625 s will meet the refresh requirement and ensure that each row is refreshed. alternatively, 4096 refresh command cycles can be issued in a burst at a minimum cycle rate (t rfc ), once every 64 ms. figure 32 on page 104 shows auto refresh cycles. figure 50. lpsdram write with auto precharge to bank n interrupted by read to bank m figure 51. lpsdram write with auto precharge to bank n interrupted by write to bank m t0 t1 t2 t3 t4 t5 t6 clk bank n bank m command write-ap nop read-ap nop nop nop nop t wr , bank n t rp , bank n bank n active write burst interrupt burst, write recovery precharge bank m page active read burst (4 word) precharge address bk n /col a bk m/col b data i/o din -a din -a+1 dout - b dout - b+1 dout - b+2 r-clk t0 t1 t2 t3 t4 t5 t6 clk bank n bank m command write-ap nop write-ap nop nop nop nop t wr , bank n t rp , bank n bank n active write burst (4 word) interrupt burst, write recovery precharge t wr , bank m bank m page active write burst (4 word) wrtie recovery address bk n /col a bk m/col b data i/o din -a din -a+1 din - b din - b+1 din - b+2 din - b+3 r-clk
part 3: lpsdram operations lpsdram command and operation intel pxa27x processor family memory subsystem 111 17.13 lpsdram self refresh this state retains data in the lpsdram, even as the rest of the system is powered down. the self refresh command is initiated like the auto refresh command, except the d-cke is disabled (low). all banks must be idle before this command is issued. once the self refresh command is registered, all inputs become "don't care" except d-cke, which must remain low. the procedure for exiting self refresh mode requires a series of commands. first clock must be stable before d-cke going high. nop commands should be issued (minimum of 2 clocks) to meet the refresh exit time (t srex ) limitation. figure 33 on page 104 shows self refresh entry and exit mode.
part 3: lpsdram operations lpsdram command and operation 112 intel? pxa27x processor family memory subsystems
a. flash flowcharts intel pxa27x processor family memory subsystem 113 flash flowcharts a figure 52. flash word program flowchart program suspend loop start w rite 0x40, w or d address write data, w or d address read status register sr.7 = full status check (if desired) program complete suspend? 1 0 no yes word program procedure repeat for subsequent w ord program operations. full status register check can be done after each pr ogram, or after a sequence of program operations. w rite 0xff after the last operation to set to the read array state. comments bus operation command data = 0x40 addr = location to program write program setup data = data to program addr = location to program write data status register data read none check sr.7 1 = wsm ready 0 = wsm busy idle none (setup) (confirm) full status check procedure read status register program successful sr.3 = sr.1 = 0 0 sr.4 = 0 1 1 1 v pp range error device protect error program error if an error is detected, clear the status register before continuing operations - only the clear staus register command clears the status register error bits. idle idle bus operation none none command check sr.3: 1 = v pp error check sr.4: 1 = data program er ror comments idle none check sr.1: 1 = block locked; operation aborted
a. flash flowcharts 114 intel? pxa27x processor family memory subsystem figure 53. flash program suspend/resume flowchart read status register sr.7 = sr.2 = write 0xff susp partition read array data program completed done reading write 0xff pgm'd partition write 0xd0 any address program resumed read array data 0 no 0 yes 1 1 program suspend / resume procedure write program resume data = 0xd0 addr = suspended block (ba) bus operation command comments write program suspend data = 0xb0 addr = block to suspend (ba) standby check sr.7 1 = wsm ready 0 = wsm busy standby check sr.2 1 = program suspended 0 = program completed write read array data = 0xff addr = any address within the suspended partition read read array data from block other than the one being programmed read status r egister data addr = suspended block (ba) pgm_sus.wmf star t w rite 0xb0 any address program suspend read status program resume read array read array write 0x70 same partition write read status data = 0x70 addr = same partition if the suspended partition was placed in read array mode: write read status return partition to status mode: data = 0x70 addr = same partition w rite 0x70 same partition read status
a. flash flowcharts intel pxa27x processor family memory subsystem 115 figure 54. flash buffer program flowchart buffer programming procedure start get next target address issue buffer prog. cmd. 0xe8, word address read status register at word address write buffer available? sr.7 = 1 = yes device supports buffer writes? set timeout or loop counter timeout or count expired? write confirm 0xd0 and word address (note 5) yes no buffer program data, start word address x = 0 0 = no yes use single word programming abort buffer program? no x = n? write buffer data, word address x = x + 1 write to another block address buffer program aborted no yes yes write word count, word address suspend program loop read status register (note 7) is bp finished? sr.7 = full status check if desired program complete suspend program? 1=yes 0=no yes no issue read status register command no 1. word count value on d[7:0] is loaded into the word count register. count ranges for this device are n = 0x00 to 0x1f. 2. the device outputs the status register when read. 3. write buffer contents will be programmed at the issued word address. 4. align the start address on a write buffer boundary for maximum programming performance (i.e., a[4:0] of the start word address = 0x00). 5. the buffered programming confirm command must be issued to an address in the same block, for example, the original start word address, or the last address used during the loop that loaded the buffer data . 6. the status register indicates an improper command sequence if the buffer program command is aborted; use the clear status register command to clear error bits. 7. the status register can be read from any addresses within the programming partition. full status check can be done after all erase and write sequences complete. write 0xff after the last operation to place the partition in the read array state. bus operation idle read command none none write buffer prog. setup read none idle none comments check sr.7: 1 = wsm ready 0 = wsm busy status register data addr = note 7 data = 0xe8 addr = word address sr.7 = valid addr = word address check sr.7: 1 = write buffer available 0 = no write buffer available write (notes 5, 6) buffer prog. conf. data = 0xd0 addr = original word address write (notes 1, 2) none data = n-1 = word count n = 0 corresponds to count = 1 addr = word address write (notes 3, 4) none data = write buffer data addr = start word address write (note 3) none data = write buffer data addr = word address other partitions of the device can be read by addressing those partitions and driving oe# low. (any write commands are not allo wed during this period.) 0xff commands can be issued to read from an y block s in oth er partit io ns
a. flash flowcharts 116 intel? pxa27x processor family memory subsystem figure 55. flash buffered efp flowchart 2. write-buffer contents are programmed sequentially sequentially to the flash arr ay starting at the first word write data @ 1 st word address last data? write 0x ffff, address not within current block program done? read status reg. y no (sr.7=0) full status check procedure program complete read status reg. befp exited? yes (sr.7=1) start write 0x80 @ 1 st word address v pp applied, block unlocked write 0xd0 @ 1 st word address befp setup done? read status reg. exit n program & verify phase exit phase setup phase x = 32? initialize count: x = 0 increment count: x = x+1 y n check v pp , lock e rrors (s r[3,1]) yes (sr.7=0) comments bus state operation befp setup delay data stream ready? read status reg. no (sr[0]=1) repeat for subsequent blocks; after befp exit, a full status register check can determine if any program error occurred; see full status register check procedure in the word program flowchart. write 0xff to enter read array state. check sr.7: 0 = exit not completed 1 = exit completed check exit status read status register data = status reg. data address = 1st word addr befp exit standby if sr.7 is set, check: sr.3 set = v pp error sr.1 set = locked block error condition check standby check sr.7: 0 = befp ready 1 = befp not ready befp setup done? standby data = status reg. data address = 1 st word addr status register read data = 0xd0 @ 1 st word address befp confirm write data = 0x80 @ 1 st word address befp setup write (note 1) v pph applied to vpp unlock block write befp setup bus state comments operation no (sr.0=1) yes (sr.0=0) no (sr.7=1) yes (sr.0=0) befp program & verify comments bus state operation write (note 2) load buffer standby increment count standby initialize count data = data to program address = 1 st word addr. x = x+1 x = 0 standby buffer full? x = 32? yes = read sr.0 no = load next data word read standby status register data stream ready? data = status register data address = 1 st word addr. check sr.0: 0 = ready for data 1 = not ready for data read standby standby write status register program done? last data? exit prog & verify phase data = status reg. data address = 1 st word addr. check sr.0: 0 = program done 1 = program in progress no = fill buffer again yes = exit data = 0xffff @ addres s not in current block n otes: 1. first- word address to be programmed within the tar get block must be al i gned on a w r i te- buffer boundar y. address; wsm inter nally incr ements addressing.
a. flash flowcharts intel pxa27x processor family memory subsystem 117 figure 56. flash block erase flowchart start full erase status check procedure repeat for subsequent block erasures. full status register check can be done after each block er ase or after a sequence of block erasures. w rite 0xff after the last operation to enter read array mode. only the clear status register command clear s sr[1, 3, 4, 5]. if an error is detected, clear the status register before attempting an erase retr y or other err or recovery. no suspend erase 1 0 0 0 1 1,1 1 1 0 yes suspend erase loop 0 w rite 0x20, block address w rite 0xd0, block address read status register sr.7 = full erase status check (if desired) block erase complete read status register block erase successful sr.1 = block locked error block erase procedure bus operation command comments write block erase setup data = 0x20 addr = block to be erased (ba) write erase confirm data = 0xd0 addr = block to be erased (ba) read none status register data. idle none check sr.7: 1 = wsm ready 0 = wsm busy bus operation command comments sr.3 = v pp range error sr[4,5] = command sequence error sr.5 = block erase error idle none check sr.3: 1 = v pp range error idle none check sr[4,5]: both 1 = command sequence er ror idle none check sr.5: 1 = block erase error idle none check sr.1: 1 = attempted erase of locked block; er ase aborted. (block erase) (eras e confirm)
a. flash flowcharts 118 intel? pxa27x processor family memory subsystem figure 57. flash erase suspend/resume flowchart erase completed read ar r ay data 0 0 no read 1 program program loop read array data 1 start read status register sr.7 = sr.6 = erase resumed read or pr ogr am ? done write write idle idle write erase suspend read array or pr ogr am none none program resume data = 0xb0 addr = sam e parti tion addr ess as above data = 0xff or 0x40 addr = any addr ess wi thin the suspended partition check sr.7: 1 = w sm r eady 0 = w sm busy check sr.6: 1 = erase suspended 0 = erase completed data = 0xd0 addr = any addr ess bus operat ion command comments read none status register data. addr = same partition read or write none read ar r ay or pr ogr am data fr om /to block other than the one being er ased erase suspend / resume procedure if the suspended partition was placed in read array mode or a program loop: write 0xb0, any address (erase suspend) w rite 0x70, same partition (read status) write 0xd0, any address (e rase res ume) w rite 0x70, same partition (read status) write 0xff, erased partition (read a rray) write read status data = 0x70 addr = any par ti tion addr ess write read status r egister return partition to status mode: data = 0x70 addr = same partition yes
a. flash flowcharts intel pxa27x processor family memory subsystem 119 figure 58. flash block lock operations flowchart no start write 0x60, block address write 0x90 read block lock status locking change? lock change complete write either 0x01/0xd0/0x2f, block address write 0xff partition address yes write write write (optional) read (optional) idle write lock setup lock, unlock, or lock-down confirm read device id block lock status none read array data = 0x60 addr = block to lock/unlock/lock-down data = 0x01 (block lock) 0xd0 (block unlock) 0x2f (lock-down block) addr = block to lock/unlock/lock-down data = 0x90 addr = block address + offset 2 block lock status data addr = block address + offset 2 confirm locking change on d[1,0]. data = 0xff addr = block address bus operation command comments locking operations procedure (lock confirm) (read device id) (read array) optional (lock setup)
a. flash flowcharts 120 intel? pxa27x processor family memory subsystem figure 59. flash one-time programmable protection register programming flowchart full status check procedure progr am protection register oper ation addresses must be within the protection register address space. addresses outside this space will return an error. repeat for subsequent programming operations. full status register check can be done after each pr ogram, or after a sequence of program operations. w rite 0xff after the last operation to set read ar ray state. only the clear staus register command clears sr[1, 3, 4]. if an error is detected, clear the status register before attempting a program retry or other error recover y. 1 0 1 1 1 protection register programming procedure start w rite 0xc0, pr address write pr address & data read status register sr.7 = full status check (if desired) program complete read status register data program successful sr.3 = sr.4 = sr.1 = v pp range er ror program error register locked; program aborted idle idle bus operation none none command check sr.3: 1 = v pp range error check sr.4: 1 = programming error comments write write idle program pr setup protection program none data = 0xc0 addr = first location to program data = data to program addr = location to program check sr.7: 1 = w sm ready 0 = w sm busy bus operation command comments read none status register data. idle none check sr.1: 1 = block locked; operation aborted (program setup) (confirm data) 0 0 0
b. common flash interface intel? pxa27x processor family memory subsystem 121 common flash interface b the common flash interface (cfi) is part of an overall specification for multiple command-set and control-interface descriptions. this appendix describes the database structure containing the data returned by a read operation after issuing the cfi query command (see section 9.2, flash bus operations on page 64 ). system software can parse this database structure to obtain information about the flash, such as block size, density, bus width, and electrical specifications. the system software will then know which command set(s) to use to properly perform flash writes, block erases, reads and otherwise control the flash. b.1 query structure output the query database allows system software to obtain information for controlling the flash. this section describes the flash cfi-compliant interface that allows access to query data. query data are presented on the lowest-order data outputs (dq[7:0]) only. the numerical offset value is the address relative to the maximum bus width supported by the flash. for the pxa27x processor memory subsystem, the flash query table starting address is a 10h, which is a word address for x16 flash. for a word-wide (x16) flash, the first two query-structure bytes, ascii q and r, appear on the low byte at word addresses 10h and 11h. this cfi-compliant flash outputs 00h data on upper bytes. the flash outputs ascii q in the low byte (dq[7:0]) and 0x00 in the high byte (dq[15:8]). at query addresses containing two or more bytes of information, the least significant data byte is presented at the lower address, and the most significant data byte is presented at the higher address. in all of the following tables, addresses and data are represented in hexadecimal notation, so the h suffix has been dropped. in addition, since the upper byte of word-wide flash is always 0x00, the leading 00 has been dropped from the table notation and only the lower byte value is shown. any x16 flash outputs can be assumed to have 0x00 on the upper byte in this mode. table 36. summary of query structure output as a function of device and mode device hex offset hex code ascii value device addresses 00010 51 q 00011 52 r 00012 59 y
b. common flash interface 122 intel? pxa27x processor family memory subsystem table 37. example of query structure output of x16- flash b.2 query structure overview the query command causes the flash component to display the common flash interface (cfi) query structure or database. the structure sub-sections and address locations are summarized in table 38 . table 38. query structure notes: 1. refer to the query structure output section and offset 28h for the detailed definition of offset address as a function of flash bus width and mode. 2. ba = block address beginning location (i.e., 08000h is block 1s beginning location when the block size is 16-kword). 3. offset 15 defines p which points to the primary intel-specific extended query table. b.3 cfi query identification string the identification string provides verification that the component supports the common flash interface specification. it also indicates the specification version and supported vendor-specified command set(s). word addressing: byte addressing: offset hex code value offset hex code v alue a x Ca 0 d 15 C d 0 a x Ca 0 d 7 C d 0 00010h 0051 "q" 00010h 51 "q" 00011h 0052 "r" 00011h 52 "r" 00012h 0059 "y" 00012h 59 "y" 00013h p_id lo prvendor 00013h p_id lo prvendor 00014h p_id hi id # 00014h p_id lo id # 00015h p lo prvendor 00015h p_id hi id # 00016h p hi tbladr 00016h ... ... 00017h a _id lo a ltvendor 00017h 00018h a _id hi id # 00018h ... ... ... ... offset sub-section name description (1) 00001-fh reserved reserved f or vendor-specif ic inf ormation 00010h cfi query identif ication string command set id and vendor data of f set 0001bh system interf ace inf ormation device timing & voltage inf ormation 00027h device geometry def inition flash device layout
b. common flash interface intel? pxa27x processor family memory subsystem 123 table 39. cfi identification table 40. system interface information offset length description add. hex code value 10h 3 query-unique ascii string qry 10: --51 "q" 11: --52 "r" 12: --59 "y" 13h 2 primary vendor command set and control interface id code. 13: --01 16-bit id code for vendor-specified algorithms 14: --00 15h 2 extended query table primary algorithm address 15: --0a 16: --01 17h 2 alternate vendor command set and control interface id code. 17: --00 0000h means no second vendor-specified algorithm exists 18: --00 19h 2 secondary algorithm extended query table address. 19: --00 0000h means none exists 1a: --00 offset length description add. hex code value 1bh 1 1b: --17 1.7v 1ch 1 1c: --20 2.0v 1dh 1 1d: --85 8.5v 1eh 1 1e: --95 9.5v 1fh 1 n such that t yp ical sin g le word p ro g ram time-out = 2 n -sec 1f: --08 256s 20h 1 n such that t yp ical max. buffer write time-out = 2 n -sec 20: --09 512s 21h 1 n such that t yp ical block erase time-out = 2 n m-sec 21: --0a 1s 22h 1 n such that t yp ical full chi p erase time-out = 2 n m-sec 22: --00 na 23h 1 n such that maximum word p ro g ram time-out = 2 n times t yp ical 23: --01 512s 24h 1 n such that maximum buffer write time-out = 2 n times t yp ical 24: --01 1024s 25h 1 n such that maximum block erase time-out = 2 n times t yp ical 25: --02 4s 26h 1 n such that maximum chi p erase time-out = 2 n times t yp ical 26: --00 na v pp [programming] supply minimum program/erase voltage bits 0C3 bcd 100 mv bits 4C7 hex volts v pp [programming] supply maximum program/erase voltage bits 0C3 bcd 100 mv bits 4C7 hex volts v cc logic supply minimum program/erase voltage bits 0C3 bcd 100 mv bits 4C7 bcd volts v cc logic supply maximum program/erase voltage bits 0C3 bcd 100 mv bits 4C7 bcd volts
b. common flash interface 124 intel? pxa27x processor family memory subsystem b.4 flash geometry definition table 41. flash geometry definition offset length description code 27h 1 n such that device size = 2 n in number of bytes 27: see table below 76543210 28h 2 x64x32x16x828:--01x16 15 14 13 12 11 10 9 8 29:--00 2ah 2 n such that maximum number of bytes in write buffer = 2 n 2a: --06 64 2b: --00 2ch 1 2c: 2dh 4 erase block region 1 information 2d: bits 0C15 = y, y+1 = number of identical-size erase blocks 2e: bits 16C31 = z, region erase block(s) size are z x 256 bytes 2f: 30: 31h 4 erase block region 2 information 31: bits 0C15 = y, y+1 = number of identical-size erase blocks 32: bits 16C31 = z, region erase block(s) size are z x 256 bytes 33: 34: 35h 4 reserved for future erase block region information 35: 36: 37: 38: see table below see table below see table below see table below flash device interface code assignment: "n" such that n+1 specifies the bit field that represents the flash device width capabilities as described in the table: number of erase block regions (x) within device: 1. x = 0 means no erase blocking; the device erases in bulk 2. x specifies the number of device regions with one or more contiguous same-size erase blo cks. 3. symmetrically blocked partitions have one blocking region
b. common flash interface intel? pxa27x processor family memory subsystem 125 table 42. flash die geometry definition address Cb Cb 27: --18 --19 28: --01 --01 29: --00 --00 2a: --06 --06 2b: --00 --00 2c: --02 --02 2d: --03 --03 2e: --00 --00 2f: --80 --80 30: --00 --00 31: --7e --fe 32: --00 --00 33: --00 --00 34: --02 --02 35: --00 --00 36: --00 --00 37: --00 --00 38: --00 --00 128 mbit 256 mbit
b. common flash interface 126 intel? pxa27x processor family memory subsystem b.5 intel-specific extended query table table 43. primary vendor-specific extended query offset (1) length descri p tion hex p = 10ah (optional flash features and commands) add. code value (p+0)h 3 primary extended query table 10a --50 "p" (p+1)h unique ascii string pri 10b: --52 "r" (p+2)h 10c: --49 "i" (p+3)h 1 major version number, ascii 10d: --31 "1" (p+4)h 1 minor version number, ascii 10e: --33 "3" (p+5)h 4 optional feature and command support (1=yes, 0=no) 10f: --e6 (p+6)h bits 10C31 are reserved; undefined bits are 0. if bit 31 is 110: --03 (p+7)h 1 then another 31 bit field of o p tional features follows at 111: --00 (p+8)h the end of the bitC30 field. 112: --00 bit 0 chip erase supported bit 0 = 0 no bit 1 suspend erase supported bit 1 = 1 yes bit 2 suspend program supported bit 2 = 1 yes bit 3 legacy lock/unlock supported bit 3 = 0 no bit 4 queued erase supported bit 4 = 0 no bit 5 instant individual block locking supported bit 5 = 1 yes bit 6 protection bits supported bit 6 = 1 yes bit 7 pagemode read supported bit 7 = 1 yes bit 8 synchronous read supported bit 8 = 1 yes bit 9 simultaneous operations supported bit 9 = 1 yes (p+9)h 1 113: --01 bit 0 pro g ram su pp orted after erase sus p end bit 0 = 1 yes (p+a)h 2 block status register mask 114: --03 (p+b)h bits 2C15 are reserved; undefined bits are 0 115: --00 bit 0 block lock-bit status register active bit 0 = 1 yes bit 1 block lock-down bit status active bit 1 = 1 yes (p+c)h 1 116: --18 1.8v (p+d)h 1 117: --90 9.0v supported functions after suspend: read array, status, query other supported operations are: bits 1C7 reserved; undefined bits are 0 v cc logic supply highest performance program/erase voltage bits 0C3 bcd value in 100 mv bits 4C7 bcd value in volts v pp optimum program/erase supply voltage bits 0C3 bcd value in 100 mv bits 4C7 hex value in volts
b. common flash interface intel? pxa27x processor family memory subsystem 127 table 44. protection register information table 45. burst read information offset (1) length descri p tion hex p = 10ah (optional flash features and commands) add. code value (p+e)h 1 118: --02 2 (p+f)h 4 protection field 1: protection description 119: --80 80h (p+10)h this field describes user-available one time pro g rammable 11a: --00 00h (p+11)h ( otp ) protection re g ister b y tes. some are p re- p ro g rammed 11b: --03 8 byte (p+12)h 11c: --03 8 byte (p+13)h 10 protection field 2: protection description 11d: --89 89h (p+14)h 11e: --00 00h (p+15)h 11f: --00 00h (p+16)h 120: --00 00h (p+17)h 121: --00 0 (p+18)h bits 40C47 = n n = factory pgm'd groups (high byte) 122: --00 0 (p+19)h 123: --00 0 (p+1a)h 124: --10 16 (p+1b)h 125: --00 0 (p+1c)h 126: --04 16 bits 48C55 = n \ 2n = factory programmable bytes/group bits 56C63 = n n = user pgm'd groups (low byte) bits 64C71 = n n = user pg m'd g rou p s ( hi g h b y te ) bits 72C79 = n 2 n = user programmable bytes/group with device-unique serial numbers. others are user programmable. bits 0C15 point to the protection register lock byte, the sections first byte. the following bytes are factory pre-programmed and user-programmable. bits 0C7 = lock/bytes jedec-plane physical low address bits 8C15 = lock/bytes jedec-plane physical high address bits 16C23 = n such that 2 n = factory pre-programmed bytes bits 24C31 = n such that 2 n = user programmable bytes bits 0C31 point to the protection register physical lock-word address in the jedec-plane. following bytes are factory or user-programmable. bits 32C39 = n n = factory pgm'd groups (low byte) number of protection register fields in jedec id space. 00h, indicates that 256 protection fields are available offset (1) length descri p tion hex p = 10ah (optional flash features and commands) add. code value (p+1d)h 1 127: --03 8 byte (p+1e)h 1 128: --04 4 (p+1f)h 1 129: --01 4 (p+20)h 1 synchronous mode read capability configuration 2 12a: --02 8 (p+21)h 1 synchronous mode read capability configuration 3 12b: --03 16 (p+22)h 1 synchronous mode read capability configuration 4 12c: --07 cont page mode read capability bits 0C7 = n such that 2 n hex value represents the number of read-page bytes. see offset 28h for device word width to determine page-mode data output width. 00h indicates no read p a g e buffer. number of synchronous mode read configuration fields that follow. 00h indicates no burst capability. synchronous mode read capability configuration 1 bits 3C7 = reserved bits 0C2 n such that 2 n+1 hex value represents the maximum number of continuous synchronous reads when the device is configured for its maximum word width. a value of 07h indicates that the device is capable of continuous linear bursts that will output data until the internal burst counter reaches the end of the devices burstable address space. this fields 3-bit value can be written directly to the read configuration register bits 0C2 if the device is configured for its maximum word width. see offset 28h for word width to determine the burst data out p ut width.
b. common flash interface 128 intel? pxa27x processor family memory subsystem table 46. partition and erase-block region information offset (1) see table below p= 10ah descri p tion address bottom to p ( o p tional flash features and commands ) len bot top (p+23)h (p+23)h 1 12d: 12d: number of device hardware-partition regions within the device. x = 0: a single hardware partition device (no fields follow). x specifies the number of device partition regions containing one or more contiguous erase block regions.
b. common flash interface intel? pxa27x processor family memory subsystem 129 table 47. partition region 1 information (p +24)h (p +24)h n um ber of identical partitions w ithin the partition region 2 12e : 12e : (p +25)h (p +25)h 12f: 12f: (p +26)h (p +26)h 1 130: 130: (p +27)h (p +27)h 1 131: 131: (p +28)h (p +28)h 1 132: 132: (p +29)h (p +29)h 1 133: 133: (p +2a )h (p +2a )h p artition r egion 1 e rase b lock type 1 inform ation 4 134: 134: (p +2b )h (p +2b )h bits 0C15 = y, y+1 = # identical-size erase blks in a partition 135: 135: (p +2c )h (p +2c )h bits 16C31 = z, region erase block(s) size are z x 256 bytes 136: 136: (p + 2 d )h (p + 2 d )h 137: 137: (p+2e)h (p+2e)h p artition 1 (e rase b lock type 1) 2 138: 138: (p + 2 f )h (p + 2 f )h m inim um block erase cycles x 1000 139: 139: (p +30)h (p +30)h 1 13a : 13a : (p +31)h (p +31)h 1 13b : 13b : (p +32)h p artition r egion 1 e rase b lock type 2 inform ation 4 13c : (p +33)h bits 0C15 = y, y+1 = # identical-size erase blks in a partition 13d : (p +34)h bits 16C31 = z, region erase block(s) size are z x 256 bytes 13e : (p +35)h (bottom param eter device only) 13f: (p +36)h p artition 1 (e rase block type 2) 2 140: (p +37)h m inim um block erase cycles x 1000 141: (p + 3 8 )h 1 142: (p + 3 9 )h 1 143: n um ber of program or erase operations allow ed in a partition bits 0C3 = num ber of sim ultaneous p rogram operations bits 4C7 = num ber of sim ultaneous e rase operations s im ultaneous program or erase operations allowed in other p a rtitio n s w h ile a p a rtitio n in th is re g io n is in p ro g ra m m o d e bits 0C3 = num ber of sim ultaneous p rogram operations bits 4C7 = num ber of sim ultaneous e rase operations s im ultaneous program or erase operations allowed in other p a rtitio n s w h ile a p a rtitio n in th is re g io n is in e ra s e m o d e bits 0C3 = num ber of sim ultaneous p rogram operations bits 4C7 = num ber of sim ultaneous e rase operations types of erase block regions in this p artition r egion. x = 0 = no erase blocking; the p artition r egion erases in bulk x = num ber of erase block regions w / contiguous sam e-size erase blocks. s ym m etrically blocked partitions have one blocking region. p artition size = (t ype 1 blocks)x(type 1 block sizes) + (type 2 blocks)x(t ype 2 block sizes) + + (type n blocks)x(t ype n block sizes) p artition 1 (erase block type 1) bits per cell ; in te rn a l e c c bits 0C3 = bits per cell in erase region b it 4 = re s e rv e d for internal e c c used (1=yes, 0=no) b its 5 C 7 = re s e rv e fo r fu tu re u s e p artition 1 (erase block type 1) page m ode and synchronous m ode capab ilitie s d e fin e d in t a b le 1 0 . bit 0 = page-m ode host reads perm itted (1=yes, 0=no) bit 1 = synchronous host reads perm itted (1=yes, 0=no) bit 2 = synchronous host writes perm itted (1=yes, 0=no) b its 3 C 7 = re s e rv e d fo r fu tu re u s e p artition 1 (e rase block type 2) bits per cell bits 0C3 = bits per cell in erase region b it 4 = re s e rv e d for internal e c c used (1=yes, 0=no) b its 5 C 7 = re s e rv e fo r fu tu re u s e p artition 1 (e rase block type 2) pagem ode and synchronous m ode capab ilitie s d e fin e d in t a b le 1 0 bit 0 = page-m ode host reads perm itted (1=yes, 0=no) bit 1 = synchronous host reads perm itted (1=yes, 0=no) bit 2 = synchronous host writes perm itted (1=yes, 0=no) b its 3 C 7 = re s e rv e d fo r fu tu re u s e
b. common flash interface 130 intel? pxa27x processor family memory subsystem figure 60. partition region 2 information (p +3a )h (p +32)h n um ber of identical partitions within the partition region 2 144: 13c : (p+3b)h (p+33)h 145: 13d : (p + 3 c )h (p + 3 4 )h 1 146: 13e : (p + 3 d )h (p + 3 5 )h 1 147: 13f: (p+3e)h (p+36)h 1 148: 140: (p + 3 f )h (p + 3 7 )h 1 149: 141: (p +40)h (p +38)h p artition r egion 2 e rase b lock type 1 inform ation 4 14a : 142: (p +41)h (p +39)h bits 0C15 = y, y+1 = # identical-size erase blks in a partition 14b : 143: (p +42)h (p +3a )h bits 16C31 = z, region erase block(s) size are z x 256 bytes 14c : 144: (p +43)h (p +3b )h 14d : 145: (p +44)h (p +3c )h p artition 2 (e rase block type 1) 2 14e : 146: (p +45)h (p +3d )h m inim um block erase cycles x 1000 14f: 147: (p +46)h (p +3e )h 1 150: 148: (p +47)h (p +3f)h 1 151: 149: (p +40)h p artition r egion 2 e rase b lock type 2 inform ation 4 14a : (p +41)h bits 0C15 = y, y+1 = # identical-size erase blks in a partition 14b : (p +42)h bits 16C31 = z, region erase block(s) size are z x 256 bytes 14c : (p + 4 3 )h 14d : (p +44)h p artition 2 ( e rase block t yp e 2 ) 214e: (p +45)h m inim um block erase cycles x 1000 14f: (p + 4 6 )h 1 150: (p + 4 7 )h 1 151: n um ber of program or erase operations allowed in a partition bits 0C3 = num ber of sim ultaneous p rogram operations bits 4C7 = num ber of sim ultaneous e rase operations s im ultaneous program or erase operations allowed in other partitions w hile a partition in this region is in p rogram m ode bits 0C3 = num ber of sim ultaneous p rogram operations bits 4C7 = num ber of sim ultaneous e rase operations s im ultaneous program or erase operations allowed in other partitions w hile a partition in this region is in e rase m ode bits 0C3 = num ber of sim ultaneous p rogram operations bits 4C7 = num ber of sim ultaneous e rase operations types of erase block regions in this p artition r egion. x = 0 = no erase blocking; the p artition r egion erases in bulk x = num ber of erase block regions w / contiguous sam e-size erase blocks. s ym m etrically blocked partitions have one blocking region. p artition size = (type 1 blocks)x(type 1 block sizes) + (type 2 blocks)x(type 2 block sizes) + + (type n blocks)x(t ype n block sizes) p artition 2 (e rase block type 1) bits per cell bits 0C3 = bits per cell in erase region bit 4 = reserved fo r in te rn a l e c c u s e d (1 = y e s , 0 = n o ) b its 5 C 7 = re s e rv e fo r fu tu re u s e p artition 2 (erase block type 1) pagem ode and synchronous m ode capab ilitie s a s d e fin e d in t a b le 1 0 . bit 0 = page-m ode host reads perm itted (1=yes, 0=no) bit 1 = synchronous host reads perm itted (1=yes, 0=no) bit 2 = synchronous host writes perm itted (1=yes, 0=no) b its 3 C 7 = re s e rv e d fo r fu tu re u s e p artition 2 (e rase block type 2) bits per cell bits 0C3 = bits per cell in erase region bit 4 = reserved fo r in te rn a l e c c u s e d (1 = y e s , 0 = n o ) b its 5 C 7 = re s e rv e fo r fu tu re u s e p artition 2 (erase block type 2) pagem ode and synchronous m ode capab ilitie s a s d e fin e d in t a b le 1 0 . bit 0 = page-m ode host reads perm itted (1=yes, 0=no) bit 1 = synchronous host reads perm itted (1=yes, 0=no) bit 2 = synchronous host writes perm itted (1=yes, 0=no) b its 3 C 7 = re s e rv e d fo r fu tu re u s e
b. common flash interface intel? pxa27x processor family memory subsystem 131 table 48. flash die partition and erase block region information address Cb Cb 12d: --02 --02 12e: --01 --01 12f: --00 --00 130: --11 --11 131: --00 --00 132: --00 --00 133: --02 --02 134: --03 --03 135: --00 --00 136: --80 --80 137: --00 --00 138: --64 --64 139: --00 --00 13a: --02 --02 13b: --03 --03 13c: --06 --0e 13d: --00 --00 13e: --00 --00 13f: --02 --02 140: --64 --64 141: --00 --00 142: --02 --02 143: --03 --03 144: --0f --0f 145: --00 --00 146: --11 --11 147: --00 --00 148: --00 --00 149: --01 --01 14a: --07 --0f 14b: --00 --00 14c: --00 --00 14d: --02 --02 14e: --64 --64 14f: --00 --00 150: --02 --02 151: --03 --03 128 mbit 256 mbit
b. common flash interface 132 intel? pxa27x processor family memory subsystem
c. pxa27x processor memory subsystem ram type id intel pxa27x processor family memory subsystem 133 pxa27x processor memory subsystem ram type id c this field provides a means to identify a particular ram type via software during both the engineering sample and production phases. the following pxa27x processor memory subsystem product information will be hard-coded at address 0x76 in the cfi space. this methodology shall be used for all subsequent pxa27x processor memory subsystem products. note: all 16 bits of the data bus are used in this field.
c. pxa27x processor memory subsystem ram type id 134 intel? pxa27x processor family memory subsystem table 49. pxa27x processor memory subsystem ram type id field description cfi offset description notes 0x76 bits 15:0 correspond to the defined revision id field this field shall only be used in pxa27x processor memory subsystem products, and wil be located at offset 0x76 bits 15:13 = ram density ? 000b: no ram (default) ? 001b: 128-mbit ? 010b: 256-mbit ? 011b: 512-mbit ? 100b: 1-gbit ? 101b: 2-gbit ? 110b: 4-gbit ? 111b: reserved bit 15:13 describe the total ram density used in the pxa27x processor memory subsystem products. ? total ram density could be from a single monolithic die, or made up of multiple ram dies stacked to equate to a high density. bits 12:11 = ram type ? 00b: no ram (default) ? 01b: lpsdram ? 10b: lpddr ram ? 11b: reserved bit 12:11 describe the ram type used in the pxa27x processor memory subsystem products. ? valid ram type options: lpsdram or lpddr ram. ? ram types not listed are not available. bit 10 = bus width ? 00b: 16-bits (default) ? 01b: 32-bits ? 10b: reserved ? 11b: reserved bit 10 describe the bus width of the ram type used in the pxa27x processor memory subsystem products. bits 9:8 = number of banks ? 00b: no ram (default) ? 01b: 4 banks ? 10b: reserved ? 11b: reserved bit 9:8 describe the number of banks available in the ram used in the pxa27x processor memory subsystem products. bits 7:6 = number of rows ? 00b: no ram (default) ? 01b: 12 rows ? 10b: 13 rows ? 11b: 14 rows bit 7:6 describe the number of rows available in the ram used in the pxa27x processor memory subsystem products. 0x76 bit 5:4 = number of columns ? 00b: no ram (default) ? 01b: 7 columns ? 10b: 8 columns ? 11b: 9 columns bit 5:4 describe the number of columns available in the ram used in the pxa27x processor memory subsystem products. bits 3:2 = ram bus clock speed ? 00b: no ram (default) ? 01b: 104 mhz ? 10b: 133 mhz ? 11b: 266 mhz bit 3:2 describe the ram clock speed option available to used in the pxa27x processor memory subsystem products. bits 1:0 = reserved bit 1:0 is reserved for future use. the default setting is 0x00.
d. additional information intel pxa27x processor family memory subsystem 135 additional information d : order number document 280000 intel ? pxa27x family developers manual 280001 intel ? pxa27x family design guide 280003 intel ? pxa27x family electrical, mechanical, and thermal specification 280004 intel ? pxa27x family optimization guide notes: 1. please call the intel literature center at (800) 548-4725 to request intel documentation. international customers should contact their local intel or distribution sales office. 2. for the most current information on intel ? pxa27x processor or memory subsystem, refer to http:// developer.intel.com/design/pca/prodbref/253820.htm
d. additional information 136 intel? pxa27x processor family memory subsystem
e. ordering introduction intel pxa27x processor family memory subsystem 137 ordering introduction e figure 61. intel? pxa27x mcp product decoder product family member 271 = pxa27x cpu + 256-mbit flash + 256-mbit lpsdram (x16 configuration) package type lv = leaded rc = lead-free stepping speed 312 mhz 416 mhz 520 mhz r c pxa271 fc0 4 16 272 = pxa27x cpu + (2 x 128-mbit flash) x32 configuration 273 = pxa27x cpu + (2 x 256-mbit flash) x32 configuration intel xscale ? family flash included
e. ordering introduction 138 intel? pxa27x processor family memory subsystem

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