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not r ecommended for new data sheet no.pd94706 ir3081 xphase tm vr 10 control ic des cript ion the ir3 081 control ic co mbined with an ir xphase tm phase ic provide s a full feature d a nd flexible way to implement a complete vr 10 powe r solutio n . the ?control ? ic provide s overall sy ste m control a n d interfaces with any num be r of ?pha se ics? whi c h ea ch drive and monitor a sin g le p h a s e of a multiph a se conve r ter. th e x phase tm architectu re result s in a po wer su pply th at is smalle r, less expe nsiv e, and e a si er to desig n whil e providin g hi gher effici en cy than conve n tional ap pro a ch es. the ir30 81 i s intend ed for vrd or v r m / evrd 10 ap plicat io ns that use extern al vccvid/vtt circuits. feat ure s ? 6 bit vr 10 compatible vi d with 0.5% overall sy ste m accuracy ? 1 to x phase s operatio n wit h matchin g p hase ics ? programma bl e dynami c vid slew rate ? no di scha rge of output cap a citors du rin g dynamic vid step-d o wn (can be di sabl e d ) ? +/-30 0 mv diff erential rem o te sense ? programmabl e 150khz to 1mhz oscillat o r ? programma bl e vid offset and lo ad lin e output impe dan ce ? programma bl e softstart ? programma bl e hiccu p ove r -curre nt protecti on with delay to preve n t false trigge ring ? simplified powergoo d provides in dication of prope r o peratio n and avoids fal s e trigge rin g ? operates fro m 12v input wi th 9.1v un der-voltage l o ckout ? 6.8v/5ma bias re gulato r p r ovide s syste m referen c e voltage ? enable input ? small thermal l y enhan ced 28l mlpq p a ckag e package pinout n/ c 27 oc set 15 ii n 16 vd r p 17 fb 18 eaou t 19 bbf b 20 vbi as 21 vc c 22 lg n d 23 rmp o u t 24 e n able 28 ro s c 13 ss / d e l 25 vd a c 14 trm 4 12 trm 3 11 vosn s- 10 trm 2 9 trm 1 8 pw r g d 26 vi d 4 7 vi d 3 6 vi d 2 5 vi d 1 4 vi d 0 3 vi d 5 2 osc d s 1 ir3081 control ic page 1 of 39 10/ 01 /04 designs. replace with ir3081a
ir3081 ordering inforamation dev i c e o r d e r qu antit y ir308 1mt r 3000 p e r reel * ir3081 m 100 pie c e stri ps * sa mp le s only absolute maximum ratings operating ju nction te mpe r ature?? ? ??..150 o c storage te m peratu r e ran ge?? ??? ??.-6 5 o c to 150 o c esd rating ???? ?? ???? ?? ??? hbm cla ss 1 c je dec st anda rd pin # pin name v ma x v mi n i sour ce i sink 1 o s c d s 2 0 v - 0 . 3 v 1 m a 1 m a 2 - 7 v i d 0 - 5 2 0 v - 0 . 3 v 1 0 m a 1 0 m a 8, 9, 11,12 trm1 -4 do n o t con n e ct do n o t con n ec t do not connec t do not connec t 1 0 v o s n s - 0 . 5 v - 0 . 5 v 1 0 m a 1 0 m a 1 3 r o s c 2 0 v - 0 . 5 v 1 m a 1 m a 1 4 v d a c 2 0 v - 0 . 3 v 1 m a 1 m a 1 5 o c s e t 2 0 v - 0 . 3 v 1 m a 1 m a 1 6 i i n 2 0 v - 0 . 3 v 1 m a 1 m a 1 7 v d r p 2 0 v - 0 . 3 v 5 m a 5 m a 1 8 f b 2 0 v - 0 . 3 v 1 m a 1 m a 1 9 e a o u t 1 0 v - 0 . 3 v 1 0 m a 2 0 m a 2 0 b b f b 2 0 v - 0 . 3 v 1 m a 1 m a 2 1 v b i a s 2 0 v - 0 . 3 v 1 m a 1 m a 2 2 v c c 2 0 v - 0 . 3 v 1 m a 5 0 m a 2 3 l g n d n / a n / a 5 0 m a 1 m a 2 4 r m p o u t 2 0 v - 0 . 3 v 1 m a 1 m a 2 5 s s / d e l 2 0 v - 0 . 3 v 1 m a 1 m a 2 6 p w r g d 2 0 v - 0 . 3 v 1 m a 2 0 m a 2 7 n / c n / a n / a n / a n / a 2 8 e n a b l e 2 0 v - 0 . 3 v 1 m a 1 m a page 2 of 39 10/ 01 /04
ir3081 electrical specifications unle ss otherwise sp ecifie d, thes e spe c ification s appl y over: 9.5v ? ? ?
ir3081 par a mete r t e s t con d i t i o n m i n t y p m a x u n i t oscillator switchin g fre quen cy r rosc = 41.9k ? ? ? ?
ir3081 pin des c ription pin# pin symbo l pin descri ption 1 oscds apply a voltage gre a ter th an vbias to disa ble the o scill ator. use d durin g facto r y testing & trim ming. gro und or l eave ope n for normal operation. 2-7 vid0-5 inputs to vid d to a conve r ter 8, 9, 11,12 trm1 -4 used for p r e c ision p o st-pa c kage trimmi ng of the vdac voltage. do not ma ke any con n e c tion to these pin s . 10 vosns- remote se nse input. conn ect to gro und at the load. 13 rosc con n e c t a re sisto r to vosns- to progra m oscillator freque ncy an d fb, ocset, bbfb, and vdac bia s currents 14 vdac reg u lated vol t age pro g ram m ed by the vid inputs. current sen s ing and pwm operation a r e refere nced to this pin. co nne ct an external rc net work to vos n s- to program dynamic vid s l ew rate. 15 ocset program s the hiccup over-curre nt thre shold thro ugh an external re sisto r tied to vdac an d an internal curre n t source. ov er-cu r rent pro t ection can b e disa bled by con n e c ting th is pin to a dc voltage no greater than 6. 5v (do not flo a t this pin as improper operation will occur). 16 iin curre n t sense input from the phase ic(s ). to en su re prope r op era t ion bias to at least 25 0mv (don?t float this pin). 17 vdrp buffered iin signal. co nne ct an external rc n e two r k t o fb to program conve r ter output imped ance 18 fb inverting inpu t to the error amplifier. co nverter o u tpu t voltage is offset from the vdac voltag e throug h an external resi stor con n e c ted to the converter output voltage at the load an d an intern al curre n t sou r ce. 19 eaout output of the erro r amplifie r 20 bbfb input to the regulatio n det e ct co mpa r at or. con n e c t to conve r ter o u tput voltage and vdrp pin through resi sto r netwo rk to p r ogra m re cove ry from vid step-d o wn. con n e c t to ground to di sab l e body braki n g tm durin g transitio n to a lowe r vid co d e . 21 vbias 6.8v/5ma re gulated o u tpu t used a s a sys tem refe ren c e voltage for internal ci rcu i try and the pha s e ics. 22 vcc powe r for internal circuitry 23 lgnd local gro und and ic su bst r ate co nne cti on 24 rmpo ut oscillator out put voltage. used by pha s e ics to pro g ram pha s e delay 25 ss/del controls con v erter softsta rt, power g o od, and over-curre nt dela y timing. co nne ct an external capa citor to l g nd to prog ram the timing . an optional resi sto r ca n b e adde d in se ri es with the ca pacito r to red u ce the ove r -curre nt delay time. 26 pwrgd open colle ct or output that drives lo w du ring softsta rt and any external fault con d ition. co nne ct externa l pull-up. 27 n/c no internal conne ction 28 enable enable input. a logic low a pplied to this pin puts the i c into fault mode. page 5 of 39 10/ 01 /04
ir3081 syst em theory of operat ion xphase tm ar chitec ture the xphas e tm architectu re is de signe d for multipha se interle a ved buck convert e rs whi c h a r e used i n appl ication s requi rin g sm all si ze, de si gn flexibility, low voltage, high cu rrent and fa st tran sient respon se. the a r chitecture ca n control converters of any pha se number where flexibility fa cilitates the desi gn trade-off of multiphase converters. the scala b le architectu re can be ap plied to other appli c ation s which requi re hig h curre n t or mu ltiple output voltage s. as sho w n i n figure 1, th e xphase tm archite c ture co nsi s ts of a control i c a nd a scal able array of ph ase converte rs each usin g a single pha s e ic. the co ntrol ic com m unicates with the phase ics throug h a 5-wire anal o g bus, i.e. bias voltage, pha se timin g , avera ge cu rr ent, erro r am plifier o u tput, and vid volta ge. th e cont rol ic in co rpo r ates al l the system functio n s, i.e. vid, pwm ramp oscillato r, erro r ampli f ier, bias voltage, and faul t protection s etc. th e phase i c imp l ements th e functio n s req u i r ed by the co nverter of e a c h ph ase, i. e. the gate driv ers, p w m co mparator and latch, over-volta ge protection, an d curre n t sen s i ng and sha r in g. there is no unu sed o r re dund ant silicon with the xphase tm archite c ture co mpared to others su ch a s a 4 phase controlle r tha t can be con f igured for 2, 3, or 4 ph a s e o p e r ation. pcb layo u t is e a si er sin c e the 5 wire bu s eliminate s the need for p o int-to-point wirin g betwe en the control ic and ea ch pha s e. the criti c al ga te drive an d curre n t sen s e conn ectio n s are sho r t and local to the phas e ics. this improv es the pcb layout by lowering th e para s itic in du ctan ce of the gate drive ci rcuits a nd re d u cin g the noi se of the cu rrent sen s e sig nal. 0.1uf cin ccs rcs ccs rcs 0.1uf vout+ vout sense- vout- 12v vid3 vid0 vid2 vid4 vout sense+ power good vr hot enable vid1 vid5 phase fault iru3081 control ic >> bias voltage >> phase timing >> pwm control << current sense additional phases input/output iru3086 phase ic control bus cout current share current share iru3086 phase ic >> vid voltage phase fault phase fault phase hot phase hot figure 1. system block di agra m page 6 of 39 10/ 01 /04
ir3081 pwm con t ro l method the pwm blo ck diag ram of the xphase tm architectu re is sho w n in f i gure 2. fee d - forward volta ge mo de cont rol with trailing ed ge modulatio n is used. a high -gain wide -ba ndwi d th voltage type error amplifier in the co ntrol ic is use d for the voltag e cont rol loo p . an external rc circuit co nne ct ed to th e input voltag e and g r ou nd is used to progra m the slop e of the pwm ram p and to provide the feed-forward co ntrol at each ph ase. the pwm ramp slope will chang e with the in put voltage an d automatically comp en sate f o r chan ge s in the input volt age. th e inp u t voltage ca n ch ang e due to vari ations i n the sil v er box outp u t voltage or due to the wi re an d pcb - trace voltage drop rel a ted to ch ang e s in load curren t. + - 10 k + - sh ar e ad ju s t er ro r a m p lif ie r cur re nt sen se amp li fie r x34 x 0 .91 2 0mv + - + - + - 10 k sh ar e ad ju s t er ro r a m p lif ie r cur re nt sen se amp li fie r x34 2 0mv x 0 .91 + - + - + - + - + - da ci n p w mr mp bi as i n ra m p i n - ra m p i n + ga t e h sc o m p i s ha re cs in + ga t e l ea i n cs i n - sy st em re fe ren ce vo lt age enab le clo ck pul se gen er ato r body brak ing comp arat or ram p dis ch arg e cla mp pw m la tc h s res et domin ant ph as e ic r pw m c omp ar ato r r drp rp w m rm p rp hs 2 cs co m p + - rp hs 1 + - + - rcs rv f b + - cp w m rm p cs co m p cc s rp w m rm p rcs + - cp w m rm p + - + - cc s rp hs 2 rp hs 1 + - gn d vo u t bi as i n vd ac vb i a s da ci n p w mr mp ra m p i n + vo s n s- vo s n s+ v o sn s- i s ha re ra m p i n - ii n vd r p ea i n ga t e h sc o m p cs i n - cs in + ga t e l ea o u t rm p o ut vi n fb ir os c sy st em re fe ren ce vo lt age vda c body brak ing comp arat or ram p dis ch arg e cla mp enab le clo ck pul se gen er ato r v bia s r egu la tor if b vdr p amp 50% dut y cyc le ra m p g e ne ra t o r vva lley vpe ak e rro r am p r s res et domin ant pw m la tc h ph as e ic cout co nt rol i c pw m c omp ar ato r figure 2. pwm block di agra m freque nc y a nd phase ti ming contro l the o scill ator is located in the co ntrol i c an d its fre q uen cy is p r og ramma ble fro m 150 khz to 1mhz by an external resi sto r . the output of th e oscillato r i s a 5 0 % dut y cycl e tri a n g le waveform with p e a k and valley voltages of approximatel y 5v and 1v respe c tively. this si gnal i s used to p r ogra m both t he switchi ng freque ncy a n d pha se timing of the phase ics. t he pha s e i c i s p r og ramm e d by re si stor divider r phs1 and r phs2 conne cted bet wee n the vbias refere nce volta ge a nd the ph ase ic lg nd pi n. a co mp ara t or in the p h ase i c s dete c ts the cro ssi ng of the oscillator wav e form over th e voltage gen er ated by the resi sto r divid e r and tri gge rs a clo c k pul se that starts t he pwm cycle. the p eak an d valle y voltages track the vbias vo ltage red u cin g potenti a l phase ic timing errors. figure 3 sho w s the p hase timing for a n 8 pha se converte r. note th at bot h sl ope s of t he tria ngle waveform ca n be u s ed for pha se timing by swa ppin g the rmpin+ a nd rmpin? p i ns, as sho w n in figure 2. page 7 of 39 10/ 01 /04
ir3081 ramp (from control ic) clk1 vvalle y (1.00v) phase ic clock pulses vph ase1&8 (1.5v) vph ase3&6 (3.5v) vph ase2&7 (2.5v) vph ase4&5 (4.5v) vpeak (5.0 v) clk2 50% ramp duty cycle clk3 clk4 clk5 clk6 clk7 clk8 slope = 80mv / % dc slope = 1.6mv / ns @ 200khz slope = 8.0mv / ns @ 1mhz figure 3. 8 phase oscillator waveform s pwm oper ation the p w m co mparator i s lo cated in the phase ic. upo n re ceivin g a clo c k pul se, t he pwm latch is set; the p w m r m p voltage begi ns to increase; the low side driver i s turned off, and the high side dri v er is then turned on after the non- overlap time. when the p w m r mp voltage exceed s the error a m plifier? s out put voltage, the pwm latch is re set. this turns off the high sid e driver an d then turn s on the lo w sid e driver after th e non-overla p time; it activates the ramp di scha rge cla m p, which qui ckly discha rge s th e pw m r mp cap a cito r to t he vda c vol t age of th e control i c until the next clo ck p u lse. the pwm lat c h is reset dominant allo wi ng all pha se s to go to zero duty cycle wi thin a few tens of nano se cond s in respon se to a load step decrea s e. ph ase s can overlap and go to 100% d u ty cycle in re spo n se to a load ste p increa se with turn -on gate d by the clo c k pul se s. an erro r amplifie r outp u t volta ge g r eate r th an the co mm on mo de input range o f the pwm compa r ator re sults i n 10 0 % duty cycle reg a rdl e ss o f the voltage of the pwm ramp. thi s arrang ement guarantee s the erro r amp lifier is always in cont rol a nd ca n dema nd 0 to 100% duty cycle as req u ire d . i t also f a v o r s re sp on se t o a loa d st ep d e cr ea se w h ic h is a ppropri a te given the low o u tput t o inp u t voltag e ratio of most sy stems. the inducto r current will in cre a se mu ch more rapidly than de crea se in resp on se to load tran sie n ts. this control method is de sign ed to p r o v ide ?sin gle cycle tran sient re sp on se? where the ind u c tor current chang es in respon se to l oad tra n sie n t s within a si ngle switchin g cycle m a ximizing th e effectivene ss o f the powe r train a n d minimizi ng th e output cap a citor re quire ments. an a dditional advantage of the archit e c ture is that diff eren ce s i n grou nd o r inp u t voltage at the pha se s ha ve no effect on operation si nce the p w m ramp s are re feren c ed to v d ac. figure 4 depi cts pwm o p e r ating wavefo rms u nde r variou s co nditio n s. page 8 of 39 10/ 01 /04
ir3081 91% vd ac phase ic clock pulse vdac eain pwmrm p gatel gateh duty cycle decrease due to vin increase (feed-forwa rd) duty cy cle increa se due to load increas e s teady-state o peration steady-st ate operation duty cy cle decrea se due to l oad decreas e (body br aking) or f ault (vcc uv , ocp, vid =11111x) figure 4. pwm op eratin g wavefo rms body braking tm in a conventi onal syn c h r o nou s buck co nver ter, the minimum time requi red to redu ce the current in the indu ctor in respon se to a load step d e c re ase is; o min max slew v i i l t ) ( * the sl ew rate of the ind u ctor cu rrent can be sig n i ficantly incre a se d by turn ing off the synchrono us rectifier in respon se to a loa d step decrea s e. th e switch n o d e vo ltage is then fo rced t o de cr ea se until cond ucti on of th e synchro nou s re ctifier?s bo dy diode occu rs. t h is i n creases th e vo ltage a c ro ss the indu ctor from vout to vout + v bod y di ode . the minimu m time requi red to re du ce the cu rre nt in the inductor in re spo n s e to a loa d transi ent decrea s e i s n o w; bodydiode o min max slew v v i i l t ) ( * since th e vol t age d r op i n t he bo dy dio d e is often hi g her th an o u tp ut voltage, th e indu cto r cu rre nt sle w rat e can be increa sed by 2x or more. this patent pendi ng te ch nique i s refe rre d to a s ?b ody braki ng? and i s a c co mplish e d throug h the ?0% duty cy cl e co mpa r ato r ? lo cated i n th e ph a s e ic. if the error a m plifier?s outp u t voltage drop s bel ow 91% of the vdac voltage this co mpa r at or turn s off the low si de gat e driver. lossles s av erage indu ctor curre nt s e nsing inducto r current ca n be se nse d by conn ecting a serie s resi st or and a ca pa citor n e twork in pa rallel with th e i ndu ctor and mea s u r in g the voltage across the ca pacito r , as sh own in fig u re 5. the equati on of the sen s ing n e two r k i s , cs cs l l cs cs l c c sr sl r s i c sr s v s v 1 ) ( 1 1 ) ( ) ( usually the resi stor rcs a nd capa citor ccs a r e cho s en so that th e time con s tant of rcs a nd ccs eq ual s the tim e con s tant of th e ind u cto r wh ich i s th e ind u ctan ce l over the ind u ct or dcr (r l ). if the two time cons tants matc h, the voltage a c ro ss ccs is prop ortional to th e cu rrent thro ugh l, a nd th e se nse ci rcu i t can b e tre a t ed as if o n ly a se nse resi sto r with the value of r l was u s ed . the mi smat ch of the tim e const ants doe s not affect the m e a s u r eme n t of indu ctor dc current, but affects the a c compon ent of the indu ctor current. page 9 of 39 10/ 01 /04
ir3081 v l l r l i v l o r c cs cs c o cu rren t v s c c sense a m p csout figure 5. in ducto r cu rren t sensing an d current sen s e amplifier the advanta ge of sen s in g the indu cto r cu rre nt versu s high side or low si de sen s in g is th at actual out put curre n t being delive r ed to the load is obtaine d rather than pea k or sa m p led inform ation about the switch cu rre nts. the output voltag e ca n be po si tioned to m e et a load line based o n re al time inform ation. except for a sen s e resi stor i n seri es with th e indu cto r , this is the o n ly sen s e meth od that can suppo rt a sing le cy cl e tra n sient re sp on se . othe r method s provide no inform ation duri ng e i t her load in crease (lo w sid e sen s in g) o r load de crea se (high side sensi ng). an additional proble m associate d with pea k or valle y current mo de co ntrol for voltage posit ioning i s that they suffer from pea k-to -averag e erro rs. the s e e r rors will sh ow in many wa ys but one e x ample is th e effect of freque ncy variation. if the freq uen cy of a particul a r unit is 10 % low, the p eak to p e a k indu ctor curre n t will be 10 % large r and the output im peda nce of the c onverte r will drop by about 1 0 %. variation s in indu ctan ce, current sen s e amplifie r band width, p w m pro p d e l a y, any ad de d sl ope com pen sa tion, i n put voltage, and output v o ltage are all additio nal sou r ces of pe ak-to - ave r ag e errors. current sense amplifier a high sp eed differential cu rre nt sen s e a m plifier is lo cated in the p hase ic, as shown in figu re 5. its gain d e crea se s with in cre a si ng temp eratu r e a nd i s no minally 34 at 25oc an d 29 at 125o c (-1 470 p p m/oc). this red u cti on of ga i n tends to co m pen sate the 3850 ppm/o c increa se in i ndu ctor dcr. since in m o st de sign s th e phase ic j unctio n is hotter tha n th e indu ctor th ese t w o effe cts tend to ca ncel su ch th a t no additio n a l tempe r ature co mpen sati on of the load line i s re quire d. the cu rrent sen s e amplifi e r ca n a c cep t positive differ ential inp u t up to 1 00m v and ne gati v e up to -20 m v befo r e clippi ng. the output of the curre n t se nse amplifier i s su mmed with the da c volta ge and se nt to the co ntrol ic and other pha s e s throug h an o n -chip 1 0 k ? resi sto r co nn ected to the i s hare pi n. the ishare pins of all the phase s are tie d toget her and th e voltage o n the sha r e bu s re pre s ent s the averag e current thro ugh a ll the indu cto r s an d is use d by the control ic for voltage posit i oning a nd current limit prot ection. av erage cur r ent shar e l oop curre n t sh ari ng bet wee n p hases of the conve r ter i s a c hiev e d by th e avera ge cu rre nt sh are l o op in e a ch phase ic. the o u tput of the current sense am plifie r is compa r ed with the share bu s le ss a 20mv offset. if current in a pha se i s smalle r tha n the average current, the sh are a d ju st am plifier of the p hase will acti vate a cu rren t sou r ce that redu ce s the slope of i t s pwm ram p thereby in crea sing its d u ty cy cle and output curre n t. the cro ssover freq uen cy of the curre n t share loop can be prog ram m ed with a capa ci tor at th e scomp pin so t hat the sh are loop do es no t intera ct with the outp u t voltage loo p . page 1 0 of 39 10/ 01 /04
ir3081 ir3081 theory of operati o n block diagra m the block dia g ram of the ir30 81 is sho w n in figu re 6, and sp ecifi c features a r e discusse d in the followin g se ction s . error amp ifb 1.3v vid = 11111x vid c o n t r o l vid dac output vid step-down 6ua 50% duty cycle on 1.2v idischg 1.0v current source generator ramp generator 70ua ss/del discharge iocset oc comparator 6.8v vchg 4v softstart clamp 5.0v vbias regulator ichg vdrp amp rosc buffer amp 0.2v off 90mv 0.6v vcc uvlo comparator 9.1v + enable comparator start 8.9v + - stop - delay comparator discharge comparator over current fault latch r s set dominant + - + - + - + - + - + - + - + - + - + - + - + + - + - + - + - + - iin vid3 vid5 vosns- vdac ocset lgnd vid2 vid4 rmpout ss/del rosc vid1 pwrgd vdrp vbias vid0 fb enable vcc bbfb eaout irosc irosc vbias irosc irosc disable irosc irosc irosc irosc irosc irosc irosc irosc figure 6. ir3081 blo ck diagra m vid cont rol a 6-bit vid v o ltage comp a t ible with v r 10, a s sho w n in ta ble 1, is availa ble at the vda c pin. a detail ed blo c k diagram of th e vid cont rol circuitry can be found in figur e 7. th e vid pins re quire an exte rnal bi as volt age an d sho u ld n o t b e floated. th e vid inp u t compa r ators, with 0. 6v ref e ren c e, m oni tor the vid pi ns a nd cont rol the 6 bit digital-to -ana log conve r te r (dac) who s e output i s sent to the vdac buffer amplifie r. t he o u tput of the b u ffer amplifier i s th e vda c pin. the v d ac v o ltage i s p o st -pa c k age tri mmed to co mpen sate fo r the inp u t offsets of th e erro r amplifi e r to provide a 0.5% s y stem se t-poin t accu ra cy. t he a c tual v d ac voltage d oes not d e termine the system a c curacy and h a s a wide r tolera nce. page 1 1 of 39 10/ 01 /04
ir3081 the i r 30 81 can a c cept chang es in th e vid co de while op erati ng a nd va ry the da c volt age acco rdin gly. th e sin k /so u rce capability of the vdac bu ffe r amplifier is prog ram m ed by the same extern al resi stor th at sets the oscillator freq uen cy. the sl ew rate of the voltage at the vdac pin can be adj us te d by an external ca pa citor betwe en vdac pi n an d the vos n s- pin. a resi stor co nne cte d in se ri es with this cap a citor is re quire d to compe n s ate the vdac buffer amplifie r. di gital vid tra n sition s re sul t in a sm oot h an alog tra n sition of th e vda c volt age and conve r ter out put voltage minimizi ng in rush current s in the inp u t and o u tput capa citors an d overshoot of the output voltage. it is desi r able to prevent n egative indu ct or cu rrents i n re spo n se to a req u e s t for a lowe r vid cod e . neg a tive curren t transfo rm s th e bu ck co nverter i n to a b o o st conve r ter and tr a n sfe r s e n e r gy fro m the output cap a cito rs b a c k into the input voltage. this e n e r gy can ca use voltage spikes and d a mag e the silver box or othe r co mpone nts u n l e ss they are spe c ifical ly design ed t o handl e it. furthe rmo r e, p o we r is wa st ed du ring th e transfe r of e nergy from th e output back to the in put. the ir3 081 i n clu d e s ci rcu i try that turns off both con t rol and syn c hron ou s mo sfets in respon se to a lo wer vi d cod e so th at the load cu rre n t instead of the indu cto r di scharge s the output ca pa ci tors. a lower vid cod e is d e tected by the vid st ep-d o wn dete c t co mpa r ato r whi c h m onitors t he ?fa s t? output of the dac (plu s 7 m v for noi se immunity ) comp ared to the ?slo w? o u tput of the vdac pin. if a d y namic vid step do wn i s d e tected, the b ody brake lat c h i s set and the outp u t of the erro r amplifie r is pulled d o wn to 75% of the dac voltage by the vid body bra k e cla m p. thi s trigge rs the b ody braki n g tm function whi c h turn s off b o th high si de and lo w sid e drivers in the pha se ics. the conve r te r?s output vol t age ne ed s t o be m onito red an d comp ared to the v d ac volta ge to determi ne whe n to resume no rm al operation. unfortu nately , the voltage on t he fb pin can be pull e d down by its compe n satio n netwo rk durin g the su dden de crea se in the error amplifier?s ou tput voltage so an additio n a l pin bbfb i s p r ovide d . t he bbfb pin is conn ected to the co nv erter outpu t voltage an d vdrp pin with re sisto r s o f the sa me v a lue a s on th e fb pin and th erefo r e provide s an u n -corru p t ed re presen tation of co nverter outp u t voltage. the reg u lation d e tect comp arator compa r e s the bbfb to the vdac voltag e and re se ts t he bo dy bra k e latch rele asing the e r ror amplifier? s output an d al lowin g no rma l ope ration to re sume. bo dy braki n g tm duri ng a t r a n sition to a l o we r vid co de can b e disa bled by conne cting the bbfb pin to grou nd. e nabl e vid = 111 11x det ect t o er ror am p i ros c (f rom cur ren t so urc e g ener ato r) + - + - + - + - + - + - + - vo sn s - vi d 5 vi d 3 vi d 4 vi d 2 ea o u t vi d 1 vi d 0 vd ac bbf b 0 .6v vid inp ut comp ara tor s (1 o f 6 show n) - dig ita l t o ana log con ver ter + vda c b uffe r amp is ourc e is ink "fa st" vd ac "sl ow" vd ac vi d do wn bb cla mp 75 % 7m v r eset d omin ant s 1.7u s blan kin g r egu lat ion d ete ct c omp ara tor bod y bra ke lat ch r v id s tep -do wn d etec t c ompa rat or 80 0ns bl ank ing ib bfb figure 7. vid co ntrol blo ck diag ram page 1 2 of 39 10/ 01 /04
ir3081 processo r pins (0 = low, 1 = high ) processo r pins (0 = low, 1 = high ) vid4 vid3 vid2 vid1 vid0 vid5 vout (v) vid4 vid3 vid2 vid1 vid0 vid5 vout (v) 0 1 0 1 0 0 0.837 5 1 1 0 1 0 0 1.212 5 0 1 0 0 1 1 0.850 0 1 1 0 0 1 1 1.225 0 0 1 0 0 1 0 0.862 5 1 1 0 0 1 0 1.237 5 0 1 0 0 0 1 0.875 0 1 1 0 0 0 1 1.250 0 0 1 0 0 0 0 0.887 5 1 1 0 0 0 0 1.262 5 0 0 1 1 1 1 0.900 0 1 0 1 1 1 1 1.275 0 0 0 1 1 1 0 0.912 5 1 0 1 1 1 0 1.287 5 0 0 1 1 0 1 0.925 0 1 0 1 1 0 1 1.300 0 0 0 1 1 0 0 0.937 5 1 0 1 1 0 0 1.312 5 0 0 1 0 1 1 0.950 0 1 0 1 0 1 1 1.325 0 0 0 1 0 1 0 0.962 5 1 0 1 0 1 0 1.337 5 0 0 1 0 0 1 0.975 0 1 0 1 0 0 1 1.350 0 0 0 1 0 0 0 0.987 5 1 0 1 0 0 0 1.362 5 0 0 0 1 1 1 1.000 0 1 0 0 1 1 1 1.375 0 0 0 0 1 1 0 1.012 5 1 0 0 1 1 0 1.387 5 0 0 0 1 0 1 1.025 0 1 0 0 1 0 1 1.400 0 0 0 0 1 0 0 1.037 5 1 0 0 1 0 0 1.412 5 0 0 0 0 1 1 1.050 0 1 0 0 0 1 1 1.425 0 0 0 0 0 1 0 1.062 5 1 0 0 0 1 0 1.437 5 0 0 0 0 0 1 1.075 0 1 0 0 0 0 1 1.450 0 0 0 0 0 0 0 1.087 5 1 0 0 0 0 0 1.462 5 1 1 1 1 1 1 of f 4 0 1 1 1 1 1 1.475 0 1 1 1 1 1 0 of f 4 0 1 1 1 1 0 1.487 5 1 1 1 1 0 1 1.100 0 0 1 1 1 0 1 1.500 0 1 1 1 1 0 0 1.112 5 0 1 1 1 0 0 1.512 5 1 1 1 0 1 1 1.125 0 0 1 1 0 1 1 1.525 0 1 1 1 0 1 0 1.137 5 0 1 1 0 1 0 1.537 5 1 1 1 0 0 1 1.150 0 0 1 1 0 0 1 1.550 0 1 1 1 0 0 0 1.162 5 0 1 1 0 0 0 1.562 5 1 1 0 1 1 1 1.175 0 0 1 0 1 1 1 1.575 0 1 1 0 1 1 0 1.187 5 0 1 0 1 1 0 1.587 5 1 1 0 1 0 1 1.200 0 0 1 0 1 0 1 1.600 0 note: 3. output disabled (fault mode ) table 1. voltage identification (vid) adap tiv e voltage posi tioning adaptive voltage po sitioni ng i s n eed ed to red u ce the output volta g e deviatio n s durin g lo ad t r ansi ents an d the po we r dissipatio n of the load wh en it is drawi ng maximum curre n t. the circuitry relat ed to voltage positioni ng i s sho w n in figure 8. re sistor r fb i s conne cted bet wee n the e r ror amplifie r?s inve rting inp u t pin fb and the conve r te r?s output voltage. an i n ternal curre n t so urce wh ose value i s prog ra m m ed by the same external re si stor that p r o g rams th e oscillator freq uen cy pump s curre n t into t he fb pin. th e error amplif ier force s the conve r ter? s o u tput voltage lowe r to maintain a b a lan c e at its inputs. r fb is sele cted to prog ram th e desi r ed amo unt of fixed offset voltage belo w the dac voltage. the voltage a t the vdrp pi n is a b u ffere d versi on of t he share bu s and rep r e s en ts the sum of the dac volt age a nd the avera ge i ndu ctor curre n t of all the phases. th e vdrp pi n is conne cted to t he fb pin through the re si stor r drp . since the e r ror amplifie r will force th e lo op to maintai n fb to be e q ual to the v d ac refe ren c e voltage, an a dditiona l curre n t will fl ow into the fb pin e qual to (vdrp-v d ac) / r drp . when the l oad cu rre nt i n crea se s, th e ada ptive positio ning v o ltage in crea se s a c cordin gly. more cu rrent flo w s th rough th e fee dba ck re si sto r r fb , an d m a ke s the output voltag e lowe r prop ortional to th e load curren t. t he positio ning voltage can b e pro g rammed by th e resi sto r r drp so that the dro op i m peda nce p r o duces the de sire d co nvert e r output i m p edan ce. the offset an d slo pe of the conve r ter o u tput impeda nce are refere n c ed to an d therefo r e ind e p ende nt of the vdac voltag e. page 1 3 of 39 10/ 01 /04
ir3081 cs i n - cs i n + cs i n - v drp is ha re p h as e i c ea o u t p h as e i c c u r r ent s ens e a m p l if ie r is ha re is ha re is ha re is ha re . .. ... iin vd a c vd a c fb vd ac 10 k + - rfb + - r drp + - ifb 10 k + - vo er r o r a m p lif i e r c u r r ent s ens e a m p l if ie r c o n t r o l ic v drp a m p l if ie r cs i n + figure 8. adaptive voltage positio ning inductor dcr temper atu r e corr ectio n if the thermal compe n satio n of the inductor dcr pro v ided by the tempe r ature d epen dent gai n of the curre n t sen s e amplifier is n o t ade quate, a ne gative te m perature co efficient (nt c ) the r mi stor c an b e u s e d fo r a dditional correctio n . the thermist or sh ould b e place d clo s e to the indu ctor a nd con necte d in pa rallel with th e feedba ck resi stor, a s sho w n in fig u re 9. the re sisto r in se rie s with the the r mist o r is u s e d to redu ce the nonlin ea rity of the thermistor. a simila r n e two r k mu st be pl ace d o n the bbfb to en sure prope r op eration du rin g a tran sition t o a l o wer vid co de with body brakin g tm . ea o u t iiniin er r o r a m p lif ie r c ont r o l i c av p am p l i f i e r + - rfb if b rf b 2 vd a c rdrp + - rt vo fb v drp figure 9. temperature co mpen sation o f inductor dcr remote voltage sensing to re du ce th e effect of im peda nce in th e gro und pla ne, the vos n s- pi n is u s ed for remote sen s in g and con n e c ted dire ctly to the load. the v d ac voltag e is refe re nced to vosn s- to avoid ad ditio nal erro r term s o r delay rel a ted to a sep a rate diff erential am pl ifier. the ca pacito r con n e ct ing the v d ac and v o sns- pin s ensure that high sp eed transi ents a r e fed directly into t he error amplifier with out delay. page 1 4 of 39 10/ 01 /04
ir3081 soft sta r t, o v er-current fault dela y , and hicc up mode the ir3081 has a p r og ra mmable soft-start fun c tion to lim it the surge cu rre nt durin g the conve r ter sta r t-up. a cap a cito r co n necte d betwe en the ss/del and lg nd pins controls soft start as well as ove r -current prote c t i on delay and hiccup mode timi ng. a ch arge cu rre nt of 7 0ua and di sch a rge curre n t of 6ua cont rol the up slo pe and do wn slop e of the voltage at the ss/del pin resp ectively. figure 1 0 de picts the va ri ous op eratin g mode s as co ntrolle d by th e ss/del fun c tion. if there is n o fault, th e ss/del pin will be gi n to be cha r ged. the e r ror amplifie r output is cl a m ped lo w un til ss/del reache s 1.3v. the error amplifier will then regul ate the conve r te r?s output volt age to match the ss/del voltage le ss t he 1.3v offse t until it rea c he s th e l e vel dete r min ed by the vid input s. the ss/del voltage continu e s to increa se u n til it rises ab ove 3.91v and allo ws the pwrgd si gnal to be a s serte d . ss/del finally settles at 4v, indicating the e n d of the soft start. und e r voltag e lock out a nd vid=1 111 1x faults as well a s a low sign al on the enable inp u t immediatel y sets the fault latch ca usin g ss/del to begin to discha rge. th e ss/de l ca pacito r will co ntinue to discharg e do wn to 0.2v. if the fault has cleared the fault latch will be reset by the discharge comparator allowing a norm al soft start to occur. a delay is in cluded if a n over-cu r rent co ndition o c curs afte r a su ccessful soft start se que nce. this i s requi red si nce over-cu r rent con d ition s ca n o c cur as p a rt of normal operation du e to lo ad tran sient s o r vid tran sition s. if an over- current fault occurs during nor mal operation it will initiate the discharge of the capacitor at ss/del but will not set the fault latch immediately. if the ov er-current con d ition persi sts lo ng enou gh fo r the ss/del capa citor to discha rg e below the 90mv offset of the delay co mparator, the fault latch will be set pu lling the error amplifier? s output low inhibiting switchin g in th e pha se ics an d de -a ssertin g the p w rg d signal. the ss/del cap a citor will co ntinue to discha rge u n til it reache s 0.2v and the fault latch is reset allo win g a normal soft start to occur. if an over-cu r rent con d ition i s a gain encount ered du ring the soft sta r t cycl e the fa ult latch will b e set witho u t any delay an d hi ccu p mode will be gin. du ring hi ccup mo de th e cha r g e to di scharge curre n t ratio re sult s in a fixed 7. 9% hiccup m ode duty cycle reg a rdl e ss of at wha t point the over-cu r rent co ndition o c curs. ho weve r, the hiccu p fre quen cy is d e termin ed b y the load curre n t and over-current set val ue. the ove r -cu r rent d e lay can b e redu ced by addin g a re si sto r in serie s wit h the ss/de l capa citor. the d e lay comp arator? s offset voltage is re du ced b y the d r op in t he resi stor caused by the discha rge current. th e val ue of th e seri es re sist o r sho u ld be 1 0 k ? or less to avoid interf erenc e with the s o ft s t art func tion. if ss/del pin is pulled b e lo w 0.9v, the converte r ca n be disabled. under volta g e locko ut (uvlo ) the uv lo fu nction m onito rs the i r 30 8 1 ?s vcc sup p ly pin and e n su re s that ir30 81 ha s a high en oug h voltage to power the int e rnal circuit. the ir30 81? s uvlo is se t higher than the minimum operat ing voltage of co mpatible phase ics th us providing uvlo p r ote c tion for them as well. du ri ng power- up the fault latch is re set wh en vcc excee d s 9.1 v and the r e is no other f ault. if the vcc volt a ge drop s b e lo w 8.9v the faul t latch will b e set. fo r conve r ters u s ing a sep a rate 5v supply f o r g a te d r iver bias an external uvlo ci rcuit ca n be adde d to p r e v ent any operation unti l adequ ate voltage is p r e s e n t. a diode co nne ct ed bet ween the 5v supply and the ss/del pin provide s a s i mple 5v uvlo func tion. ov er current prote c tion (o cp) the current li mit threshold is set by a re sisto r conn ec ted betwe en t he ocset a nd vdac pin s . if the iin pin voltage, whi c h is p r o portion al to the avera ge curre n t plus da c voltage, exceed s the ocset voltage, the ove r -curre nt prote c tion is t r igge re d. vid = 1111 1 x fault vid cod e s of 1111 11 an d 1111 10 will set the fault latch an d di s abl e the error a m plifier. an 8 00n s delay is provide d to prevent a fault con d ition from oc cu rrin g durin g dyn a mic vid cha nge s. page 1 5 of 39 10/ 01 /04
ir3081 h iccu p o ver- cur rent p rote cti on n orm al o per atio n st art -up vc c vo ut pw rgd 3. 91v ss /del (1 2v) 8.9v uvlo p ower -do wn re -sta rt af ter oc p oc p th res hold ocp del ay (v out cha nge s du e to lo ad an d v id c han ges) en able 1. 3v ( vcc gat es f ault mo de) (en abl e ga tes f aul t mo de) io ut figure 10. operatin g wav e form s po w e r goo d outpu t the pwrg d pin is a n ope n-colle ctor o u t put and shou ld be pull ed u p to a voltage sou r ce thro u gh a resi stor. duri ng soft start, the pwrgd remain s low until the output vo ltage is in re gulatio n and ss/del is above 3.91v. th e pwrgd pi n become s lo w if the fault latch is set. a high leve l at t he pwrg d pin indi cate s that the conv erter i s in operation an d has n o fault, but does not ensu r e the output voltage is within the sp eci f ication. outp ut voltag e regul ation wit h in the de sig n limits can lo gically be a ssur ed h o wever, assu ming n o comp one nt failure in the system. load cu rren t indicator o u tpu t the vdrp p i n voltage re pre s ent s the av erag e current of the co nverter plu s the da c voltage. the loa d cu rrent informatio n can be ret r ieve d by a differential amplifier which su btra cts the vda c vo ltage from the vdrp vol t age. sy stem refe rence voltag e (vbias ) the ir3 081 sup p lie s a 6.8v/5ma pre c i s ion referen c e volt age fro m the vbias pin. the oscillator ram p a m plitude tracks the vbias voltage, whi c h should be used to progra m the p hase ic tri p po ints to minimi ze ph ase del ay erro rs. enable input pulling the enable pin b e low 0.6v sets the fault la tch. page 1 6 of 39 10/ 01 /04
ir3081 application information rcs + d bst c bst d bst rcs + c bst d bst rcs + c bst 20k r b i asi n rv cc r p h ase62 da c i n 19 bi as i n 20 rm p i n+ 1 rm p i n- 2 gat e h 14 v cch 15 cs i n - 17 ph s f lt 18 h o t set 3 v rho t 4 sc om p 6 eai n 7 pgn d 13 gat e l 12 lgn d 9 p w mrmp 8 is ha re 5 vc c 10 v ccl 11 cs i n + 16 ir3086 phase ic l o s cds 1 vi d 5 2 vi d 0 3 vi d 1 4 vi d 2 5 vi d 3 6 vi d 4 7 pw r g d 26 trm 1 8 trm 2 9 vos n s- 10 trm 3 11 trm 4 12 vd a c 14 ss/ d e l 25 ro s c 13 en able 28 rmp o ut 24 lgn d 23 vc c 22 vbi as 21 bbf b 20 eaou t 19 fb 18 v drp 17 iin 16 oc set 15 n/c 27 ir3081 control ic rcs - cs co m p rcs - l cv ccl da cin 19 bi asi n 20 rm p i n+ 1 rm p i n- 2 gat e h 14 v cch 15 cs in- 17 ph sf lt 18 h o t set 3 v rho t 4 sc om p 6 eai n 7 pgn d 13 gat e l 12 lgn d 9 pw m r m p 8 is ha re 5 vc c 10 v ccl 11 cs in+ 16 ir3086 phase ic ccp rfb 1 r p h ase32 rb b drp rp wm rm p cp wmrmp rs ha re cv cc rp wm rm p cin cs co m p rp wm rm p cin cs co m p ccs + cv ccl 20k r b i asi n vgat e cs co m p rg a t e 20k r b i asi n qgat e dg a t e rv da c cp wmrmp cv cc cv cc r p h ase11 rdrp rcp c ss/ d e l cin 10 ohm rv cc cfb r p h ase31 ccs - cp wmrmp cp wmrmp ro cs e t rv cc r p h ase42 r p h ase13 rp wm rm p ccs + r p h ase33 cv cc rp ha s e 2 1 20k r b i asi n r p h ase12 da c i n 19 bi as i n 20 rm p i n+ 1 rm p i n- 2 gat e h 14 v cch 15 cs i n - 17 ph s f lt 18 h o t set 3 v rho t 4 sc om p 6 eai n 7 pgn d 13 gat e l 12 lgn d 9 p w mrmp 8 is ha re 5 vc c 10 v ccl 11 cs i n + 16 ir3086 phase ic ccs - cv ccl cs co m p cin 20k r b i asi n r p h ase41 r p h ase23 rfb ro s c cdrp cv ccl cv cc da cin 19 bi asi n 20 rm p i n+ 1 rm p i n- 2 gat e h 14 v cch 15 cs in- 17 ph sf lt 18 h o t set 3 v rho t 4 sc o m p 6 ea i n 7 pgn d 13 gat e l 12 lg n d 9 p w mrmp 8 is ha re 5 vc c 10 v ccl 11 cs in+ 16 ir3086 phase ic cs co m p ccs - ccp 1 r p h ase43 rv cc rv cc rp wm rm p cp w m rmp da cin 19 bi asi n 20 rm p i n+ 1 rm p i n- 2 gat e h 14 v cch 15 cs in- 17 ph sf lt 18 h o t set 3 v rho t 4 sc om p 6 eai n 7 pgn d 13 gat e l 12 lgn d 9 pw m r m p 8 is ha re 5 vc c 10 v ccl 11 cs in+ 16 ir3086 phase ic l rv cc cp wmrmp r bbf b 20k r b i asi n cin 0. 1uf ccs - da cin 19 bi asi n 20 rm p i n+ 1 rm p i n- 2 gat e h 14 v cch 15 cs in- 17 ph sf lt 18 h o t set 3 v rho t 4 sc om p 6 eai n 7 pgn d 13 gat e l 12 lgn d 9 p w mrmp 8 is ha re 5 vc c 10 v ccl 11 cs in+ 16 ir3086 phase ic rp wm rm p rp ha s e 2 2 r p h ase52 r p h ase61 ccs + rcs - r p h ase63 rp ha s e 5 3 r ss/ d e l d bst ccs + rcs + 0. 1uf cv cc rcs - c bst cv ccl l cv da c cv cc cin ccs + rv cc l ccs + rcs - ccs - 1nf l rcs - r p h ase51 cv ccl ccs - rdrp 1 vr h o t p o w e r good vo u t sen se+ vo u t + ph ase f a u l t vo u t - vo u t sen se- vi d 0 vi d 5 en abl e vi d 1 vi d 3 vi d 4 12v vi d 2 cout distribution impedance d bst rcs + c bst d bst rcs + c bst figure 11. ir3081/ir308 6 six-phase v r m/evrd 1 0 converte r page 1 7 of 39 10/ 01 /04
ir3081 design procedures - ir3081 and ir3 086 chipset ir3081 external comp onents oscillator resistor ros c the oscillato r of ir308 1 g enerates a tri angle wavefo rm to syn c h r onize the p h a s e i c s, an d t he swit chin g freque ncy of the ea ch p hase conve r ter e qual s the oscillato r fr e quen cy, whi c h is set by th e extern al resistor r os c according t o the curve in f i gure 1 3 . soft sta r t c a pacitor c ss/ del and resistor r ss/del b e cau s e t h e cap a cit o r c ss / d e l prog ra ms fou r different time pa ra meters, i.e. soft s t art delay time, s o ft s t art time, over-cu r rent l a tch d e lay ti me, and po wer g ood dela y time, they sho u ld b e co nsid ere d tog e ther whil e choo sing c ss/del . the ss/del pin voltage control s the sl ew rate of th e conv erte r o u tput voltage, as sho w n in figu re 10. a fter the enable pin voltage ri se s above 0.6v, t here is a soft-start d e lay time t ssdel, af ter which the error amplifie r outp u t is releas ed to allow the soft s t art. the s o ft s t art time t ss rep r e s ent s the time during whi c h convert e r voltage ri ses fro m z e ro to v o. t ss can be p r o g r amme d by an external ca pacito r , whi c h is determi ne d by equation (1). o ss o ss chg del ss v t v t i c * 10 * 70 * 6 / ? = = 6 / / 10 * 70 3 . 1 * 3 . 1 * ? = = 6 / / 10 * 6 09 . 0 * 09 . 0 * ? = = 6 / / 10 * 70 ) 3 . 1 91 . 3 ( * ) 3 . 1 91 . 3 ( * ? ? ? = ? ? = 6 / 6 / / 10 * 6 10 * 6 09 . 0 * 09 . 0 ? ? ? ? = ? = 6 6 / / / / 10 * 70 ) 10 * 70 * 3 . 1 ( * ) 3 . 1 ( * ? ? ? = ? ? = vdac sle w rate progra mming capa citor c vdac and re sisto r r vdac the sl ew rat e of vdac d o wn -sl ope s r down can be programm ed by t he external ca pa citor c vdac a s defined in equation (7), whe r e i sink is the sin k current of vdac pin a s sh own in fi gure 15. the re sisto r r vdac is used to comp en sate vdac circuit and i s determ i ned by equa tion (8 ). t he sle w rate of v d ac up -sl o p e sr up i s pro portion a l page 1 8 of 39 10/ 01 /04
ir3081 to that of vdac do wn -sl o pe an d i s giv en by eq uation (9), whe r e i source is the sou r ce current of v d ac pin a s s h ow n in f i gu r e 15 . down sink vdac sr i c (7) 2 15 10 2 . 3 5 . 0 vdac vdac c r (8) vdac source up c i sr (9) ov er current setting res i stor r o c set the inductor dc resi stance is utilized t o sense the i nductor current. the copper wi re of inductor has a constant temperature coeffici ent of 3850 p p m/ c , and therefo r e the maximu m indu ctor d cr can b e ca lculate d from equation ( 1 0) , w h er e r l_max and r l_room are the inductor dcr at maximum temperature t l_max and room te mperature t_ room res p ec tively. )] ( 10 * 3850 1 [ _ 6 _ _ room max l room l max l t t r r (10) the cu rre nt sen s e amplifi e r g a in of i r 30 86 d e cre a se s with te mperature at the rate of 1470 ppm/ c, which comp en sate s part of the inducto r dcr i n crea se. the phase ic di e temperatu r e is only a cou p le of degre e s cel s iu s highe r than th e pcb tempe r ature due to the low therm a l impeda nce of mlpq packag e . the mi nimum curren t sense amplifier g a in at the maximum pha se ic temperature t ic_max is ca lculate d from equation (11). )] ( 10 * 1470 1 [ _ 6 _ _ room max ic room cs min cs t t g g (11) the total in p u t offset voltage (v cs_tofst ) of curre n t sen s e am plifier in pha se ics i s th e su m of in put offset (v cs_ofs t) o f the amplifier itself and th at cr eate d by the amplifier input bias currents flo w in g throug h the current sen s e r e si st o r s r cs+ and r cs- . cs csin cs csin ofst cs tofst cs r i r i v v _ _ (12) the over cu rrent limit is se t by the external re si stor r o c set as defined in equ a tion (1 3), wh ere i limit is the requi re d over current l i mit. i o c set, the bia s curre n t of ocset pin, cha nge s with switchi n g frequ en cy setting resi st or r os c and is d e termined by the curve in fi g u re 1 4 . k p is the ratio of indu ctor p eak cu rrent ove r averag e cu rrent in eac h pha se an d is cal c ulate d fro m equation (14). ocset min cs tofst cs p max l limit ocset i g v k r n i r / ] ) 1 ( [ _ _ _ (13) n i f v l v v v k o sw i o o i p / ) 2 /( ) ( (14) no load output voltag e setting resi stor r fb and adap tiv e voltage positio n ing resis t o r r drp a resi stor bet wee n fb pin and the conv erter out put i s u s ed to cre a te output vol t age offset v o_nl ofs t , which i s the differen c e b e t ween v dac voltage an d output voltag e at no lo ad con d it ion. a daptive volta ge po sitioni n g further lowe rs the co nverter voltag e by r o *i o, w here r o is the r e qu ir ed out put impeda nce of the conv erter. r fb is not on ly determine d by i fb , the current flowin g out of fb pin as sho w n in figure 14, bu t also affecte d by the adaptive volt age positio ni ng resi sto r r drp and total input off s et voltage of c u rr e n t s e ns e amp lifie rs . r fb and r drp are dete r min ed by (15 ) an d (16 ) re spe c tively. page 1 9 of 39 10/ 01 /04
ir3081 max l fb o tofst cs nlofst o max l fb r i r n v v r r _ _ _ _ ? ? ? ? ? = ? ? ? = _ _ (16) body braking tm rela ted resis t ors r bbfb and r bb drp the bo dy brakin g tm durin g dynami c vid can b e di sabl ed by co nne cting bbfb pin to ground. if the feature i s enabl ed, re si stors r bb fb and r bbdrp are n eed ed t o re store the feedba ck voltage of the error am plifier after dynami c vid step do wn. usually r bbfb and r bbdrp are cho s en to match r fb a nd r drp res p ec tively . ir3086 external comp onents pwm ram p resis t or r pw mr mp and capa citor c p w mr mp pwm ram p is generated b y conne cting the resi stor r pwmrmp betwee n a volta ge sou r ce an d pwmrmp pin as well as th e capa ci tor c pwmrmp between p w mrmp a nd l g nd. choo se the de sire d pwm ram p magnitud e v ramp and t he cap a cit o r c pwmrmp in the ran ge of 1 00pf an d 47 0pf, and the n cal c ulate th e resi sto r r p w mrmp from equation (17 ) . to achieve feed -forward volt ag e mode co ntro l, the re si stor r ramp shou ld be co nne cted to the i n put of the conve r ter. )] ln( ) [ln( * * * pwmrmp dac in dac in pwmrmp sw in o pwmrmp v v v v v c f v v r ? ? ? ? = + + = + ? + ? ? = 10/ 01 /04
ir3081 ov er temperatur e settin g resis t ors r ho tset1 and r ho tset2 the th re shol d voltage of vrho t com parato r i s pro portion al to t he di e temp e r ature t j (o c) of ph ase ic. dete rmin e the relatio n sh ip between th e die tem perature of pha se ic an d the temperature of the po we r conve r ter accordin g to the po wer l o ss, p c b layo ut and ai rflo w etc, a nd th en ca lculate hotset th resh old voltag e co rrespon d i ng to the allowed maxi mum tempe r ature fro m equation (2 0). 241 . 1 * 10 * 73 . 4 3 j hotset t v (20) there a r e t w o ways to set the ove r tem peratu r e thre shol d, central setting and l o cal setting. in the cent ral setting, only one re si stor divide r is use d , and the setting vo ltage is co nn ected to ho tset pins of all the phase ics. to redu ce the inf l uen ce of noi se on the a c cura cy of over te mperatu r e setting, a 0.1 u f cap a cito r sho u ld be pla c ed n e xt to hotset p i n of ea ch ph ase i c . in the local setting, a re sisto r div i der p e r pha se is n eede d, and the settin g voltage is con n e c ted to ho tset pin of ea ch p hase. the 0. 1uf d e coupli ng cap a cito r i s n o t ne ce ssary. use vbias as th e referen c e voltage. if r hots et1 is pre-sel e cted, r ho tset2 can be ca lculate d as fol l ows. hotset bias hotset hotset hotset v v v r r 1 2 (21) phase dela y timing resistors r phase1 and r phase2 the ph ase d e lay of the i n terleave d m u ltipha se con v erte r i s pro g ramm ed by the re sisto r divider con necte d at rmpin+ o r rmpin- dep endin g on wh ich slop e of the o scill ator ramp is u s ed for the p h a s e delay p r og ra mming of pha se ic, as sho w n in fig u re 3. if the up slop e is u s ed, rmpin+ pin of the p h a s e i c sho u ld be con n e c ted to rmpo ut pi n of the cont rol ic an d rmpin- pin sho u ld b e co nne cted to t he resi stor d i vi der. when rmpo ut v o ltage i s ab o v e the trip v o ltage at rmpin- pin, the pwm latch is set. gat e l beco m e s lo w, and gat e h become s high after the non-overl ap time. if d o w n s l o p e is us ed , rmpin - p i n o f th e p h a s e ic s h ou ld b e c o nn ec te d to r m pou t p i n o f the c o n t r o l ic and rmpin+ pi n sho u ld be co nne cted to t he re sisto r d i vider. whe n rmp o ut v o ltage i s bel ow th e tri p v o ltage at rmpin- pin, the pwm latch is set. gat e l beco m e s lo w, and gat e h become s high after the non-overl ap time. use vbias voltage a s the refere nce for t he re sisto r divider sin c e the oscillato r ramp m agn itude from co ntrol ic tracks vbias voltage. try to avoid both edge s of the oscilla tor ra mp for bette r noise immuni ty. determine the rati o of the progra mming resi st ors correspon di ng to the de sire d switchin g frequ en cie s and p h a s e n u mbe r s. if the re sisto r r phasex 1 is pre- sel e ct e d , t he re sist o r r phasex 2 is determine d as: phasex phasex phasex phasex ra r ra r 1 1 2 (22) combined o v er tempera t ure an d pha se delay setting re sistor s r phase1 , r phase2 and r phase3 the over te mperature se tting re si stor divider can b e combi ned with the p h a s e delay re si stor divide r t o save one resi sto r per p hase. cal c ulate th e hotset th reshold volta ge v ho tset co rre sp ondi ng to the all o we d maxim u m tempe r at ure from equation (2 0). if the o v er temperature setting volt age is lowe r than the pha se d e lay setting voltage, vbias*ra phasex , conne ct rmpin+ or rmpin- pin betwe en r p h asex 1 and r phasex 2, an d conn ect hotset pin betwe en r phasex 2 and r p h asex 3 . pre-selec t r phase x 1 , ) 1 ( * ) ( 1 2 phasex bias phasex hotset bias phasex phasex ra v r v v ra r (23) ) 1 ( * 1 3 phasex bias phasex hotset phasex ra v r v r (24) page 2 1 of 39 10/ 01 /04
ir3081 if the over te mperature se tting voltage i s hi ghe r tha n the ph ase d e lay setting voltage, vbias*ra phasex , co nne ct hotset pin betwe en r ph asex 1 and r p h asex 2 and conne ct rmpi n+ o r rmpin- between r p h asex 2 and r phasex3 respec tively. pre-s e lec t r p h asex 1 , hotset bias phasex bias phasex hotset phasex v v r v ra v r 1 2 ) ( (25) hotset bias phasex bias phasex phasex v v r v ra r 1 3 * (26) boo t str a p capacitor c bst dep endin g o n the duty cy cle an d gate drive current of the pha se ic, a 0.1uf t o 1uf cap a ci tor is n eed ed for the bootstrap ci rcuit. deco upling capa citor s for phase ic 0.1uf-1uf de cou p ling cap a citors a r e re quire d at vcc and vccl pins of ph ase ics. voltage loop comp ensation the adaptive voltage posi tioning (avp) is usually adopted in the computer applications to i m prove the transient respon se and redu ce th e p o we r lo ss at heavy load. l i ke cu rre n t mode control, the ad aptive voltage p o sitio n ing loo p introdu ce s extra zero to th e voltage l o o p and splits t he do uble po les of th e p o w er sta ge, which ma ke th e voltage loop compe n s ation mu ch easi e r. re sist o r s r fb and r drp a r e cho s e n a c cording to eq uation s (15 ) and (16 ) , a n d the sele ction of comp en sa tion types depe nd s on the output ca pacito r s u s e d in the converter. fo r the applicatio ns using elect r olytic, polymer or al- polymer ca p a citors an d runnin g at lower freq uen cy, type ii comp ensation sho w n in figu re 12(a ) is u s ual ly enough. while for the appli c ations using only cerami c capacit o rs and runni ng at hi gher frequency, ty pe iii compensation sho w n in fig u re 12 (b ) is p r eferred. for a ppli c atio ns whe r e av p is not requi red, the com pen sati on i s t he same a s f o r the reg u lar voltage mod e co ntrol. for co nverte r usi n g polymer, al -polym er, a nd ce ra mic ca pa citors, which hav e mu ch hig h e r es r ze ro freque ncy, type iii comp ensation is re quire d as sho w n in figu re 12(b ) with r drp and c drp remov e d. rc p cc p 1 eaou t cc p rf b rd rp vo+ v drp vd ac + - eaou t fbfb cfb cdrp rcp eao u t ccp 1 cc p rfb rd rp vo+ v drp vd ac fb + - eaou t rfb 1 (a) t y pe ii com pens atio n (b) t y pe iii compens ation figure 12. voltage loo p compen satio n netwo rk t y pe ii compensa tion fo r avp applic ations page 2 2 of 39 10/ 01 /04 determine th e com pen sati on at no loa d , the wo rst ca se condi tio n . cho o se the crossove r fre q uen cy fc bet wee n 1/10 and 1/5 of th e swit chin g freque ncy pe r pha se. assu me the time con s tant of the re si stor a nd ca pa citor across the output in du ctors mat c he s t hat of the ind u ctor, and de termine r cp and c cp fro m equatio ns (27 ) a nd (28 ) , whe r e l e and c e are t he e quivalen t indu ctan ce of output i n d u ctors and t he e quivalen t cap a cita nce of outp u t ca pacito r s r e spec tively.
ir3081 2 2 ) * * * 2 ( 1 * ) 2 ( c c o pwmrmp fb e e c cp r c f v v r c l f r + ? ? ? ? ? = ? ? = ? ? = ? ? = = = ? ? = ? + = ? ? ? ? ? = ? ? = + ? =
ir3081 k v v f c l r r o pwmrmp c e e fb cp 2 ) 2 ( s (37) cp c cp r f k c s 2 (38) cp c cp r k f c s 2 1 1 (39) fb c fb r f k c s 2 (40) fb c fb c k f r s 2 1 1 (41) current s h are loop compens a tion the crossove r fre que ncy of the cu rrent s hare loo p sh o u ld b e at lea s t one de cad e lowe r th an th at of the volta ge lo op in orde r to eli m inate the in teractio n b e twee n the two loop s. a ca p a citor fro m s c omp to g r o und i s usuall y enou gh for the sha r e loop com p ensation. ch oose the cro s sover freq u ency of current sha r e lo op (f ci ) based on the cro s sove r fre quen cy of voltage loop (f c), and dete r min e the c sco m p , 6 _ 10 * 05 . 1 * 2 * )] ( * * * 2 1 [ * * * * * * 65 . 0 ci o mi o o e ci le room cs o i pwmrmp scomp f v f i v c f r g i v r c s s (42) whe r e f mi is the pwm gai n in the curre n t share loop , ) ( * ) ( * * * dac i dac pwmrmp i pwmrmp sw pwmrmp pwmrmp mi v v v v v v f c r f ( 43) page 2 4 of 39 10/ 01 /04
ir3081 design e x ample 1 - vrm 10 2u conve r ter specifications input voltage : v i =12 v dac voltag e: v dac =1.35 v no lo ad out put voltage o ffset: v o_nlof st =20 mv output current: i o =105 a dc maximum output current: i oma x =120 a dc output imped ance: r o =0. 9 1 m ? ? ? ros c once the switching frequ ency i s cho s en, r os c ca n be d e termi ned fro m the cu rve in fig u re 1 3 . fo r swit chin g freque ncy of 400 khz pe r p hase, cho o se r os c =30.1k ? c ss/ del and resistor r ss/del bec a us e fast er ove r -cu r re nt prote c tion is requi re d, the soft sta r t ca pa citor c ss/del in series with the res i s t or r ss/del is used. cal c ulate the soft start cap a cito r fro m the requi re d soft start time. uf v t i c o ss chg del ss 1 . 0 10 * 20 35 . 1 10 * 2 10 * 70 3 3 6 / cal c ulate the soft start re si stor fro m the requi re d over current del ay time t ocdel , : k i c i t r dischg del ss dischg ocdel del ss 10 10 * 6 10 * 1 . 0 10 * 6 10 * 5 . 0 09 . 0 09 . 0 6 6 6 3 / / the s o ft s t art delay time is ms i i r c t chg chg del ss del ss ssdel 86 . 0 10 * 70 ) 10 * 70 * 10 * 10 3 . 1 ( 10 * 1 . 0 ) 3 . 1 ( 6 6 3 6 / / the po we r go od delay time is ms i v c t chg o del ss vccpg 8 . 1 10 * 70 ) 3 . 1 33 . 1 91 . 3 ( * 10 * 1 . 0 ) 3 . 1 91 . 3 ( * 6 6 / page 2 5 of 39 10/ 01 /04
ir3081 vdac sle w rate progra mming capa citor c vdac and re sisto r r vdac from fig u re 15, the sin k curre n t of vdac pin corresp ondi ng to 400khz (r os c =30.1 k ? nf sr i c down sink vdac 4 . 30 10 / 10 * 5 . 2 10 * 76 6 3 6 , choo se c vd ac =33n f cal c ulate the prog ram m ing resi stor. : 5 . 3 ) 10 * 33 ( 10 * 2 . 3 5 . 0 10 * 2 . 3 5 . 0 2 9 15 2 15 vdac vdac c r from fig u re 15, the sou r ce curre n t of vdac pin i s 11 0ua. the vdac up-slo pe sle w rate is us mv c i sr vdac source up / 3 . 3 10 * 33 10 * 110 9 6 ov er current setting res i stor r o c set the room te mperature is 25oc an d the target p c b t e mpe r at ure i s 1 00 o c . th e pha se ic di e tempe r atu r e is abo ut 1 oc high er tha n that of phase ic, and the indu ct or temp eratu r e is clo s e to pcb temperature. cal c ulate ind u ctor dc re si stan ce at 100 oc, : m t t r r room max l room l max l 61 . 0 )] 25 100 ( 10 * 3850 1 [ 10 * 47 . 0 )] ( 10 * 3850 1 [ 6 3 _ 6 _ _ the cu rrent sense amplifie r gain is 3 4 at 25oc, and its gain at 101o c is calculate d as, 2 . 30 )] 25 101 ( 10 * 1470 1 [ 34 )] ( 10 * 1470 1 [ 6 _ 6 _ _ room max ic room cs min cs t t g g set the over current limit at 135a. from fi gu re 1 4 , the bias curre n t of ocset pin (i o c set ) is 41ua with r os c =30.1 k ? n i f v l v v v k limit sw i o o i p ocset min cs tofst cs p max l limit ocset i g v k r n r r / ] ) 1 ( [ _ _ _ : k 3 . 13 ) 10 * 41 /( 2 . 30 ) 10 * 55 . 0 3 . 1 10 * 61 . 0 6 135 ( 6 3 3 no load output voltag e setting resi stor r fb and adap tiv e voltage positio n ing resis t o r r drp from fig u re 14, the bias current of fb pin is 41ua wit h r os c =30.1 k ? max l fb o tofst cs nlofst o max l fb r i r n v v r r : k r n g r r r o min cs max l fb drp 21 . 1 10 * 91 . 0 6 2 . 30 10 * 61 . 0 365 3 3 _ _ page 2 6 of 39 10/ 01 /04
ir3081 bod y braking related re sistors r bbfb and r bbdr p n/a. the bod y brakin g du ri ng dynami c vid is disa ble d . ir3086 external comp onents pwm ram p resis t or r pw mr mp and capa citor c p w mr mp set pwm ramp magnitude v pwmrmp =0.8v. choo se 220 pf for pwm ramp capa citor c pw mrmp , and calcul ate the resi st o r r pw mrmp , )] ln( ) [ln( pwmrmp dac in dac in pwmrmp sw in o pwmrmp v v v v v c f v v r ? ? ? ? ? ? ? = ? = ? ? ? ? ? ? ? = ? 1 . 16 )] 8 . 0 35 . 1 12 ln( ) 35 . 1 12 [ln( 10 * 220 10 * 400 12 33 . 1 12 3 , choo se r p w mrmp =16.2 k inductor cur r ent sen s ing capaci tor c cs+ and resi stors r cs+ a nd r cs- cho o s e c cs+ =47 n f, and calcul ate r cs+, ? = = = ? ? ? + + 0 . 10 10 * 47 ) 10 * 47 . 0 /( 10 * 220 9 3 9 the bia s cu rrents of csin+ and cs in- are 0.25 ua a nd 0.4ua re spec tively. cal c ulate resi sto r r cs- , ? = ? = ? = + ? 2 . 6 10 * 0 . 10 4 . 0 25 . 0 4 . 0 25 . 0 3 , choo se r cs- =6. 1 9 k ov er temperatur e settin g resis t ors r ho tset1 and r ho tset2 use ce ntral o v er-temp e rature setting a nd set the te mperatur e th resh old at 11 5 oc, whi c h co rre sp ond s to the ic die temperature of 116 oc. ca lculate the hotset thre shold voltage corre s p ondin g to the temperatu r e thre shold s . v t v j hotset 79 . 1 241 . 1 116 10 * 73 . 4 241 . 1 * 10 * 73 . 4 3 3 = + ? = + = ? ? ? = ? ? = ? ? = 57 . 3 79 . 1 8 . 6 79 . 1 10 * 10 3 1 2 phase dela y timing resistors r phase1 and r phase2 use ce ntral o v er-temp e rature setting a nd set the te mperatur e th resh old at 11 5 oc, whi c h co rre sp ond s to the ic die temperature of 116 oc. ca lculate the hotset thre shold voltage corre s p ondin g to the temperatu r e thre shold s . the p h a s e d e lay re si stor ratio s fo r p hases 1 to 6 at 4 0 0 k hz of switching frequ en cie s are ra phas e1 = 0 .628, ra phase2 =0. 415, ra phas e3 = 0 .202, ra phase4 = 0 .246, ra phase5 =0.44 1 an d ra phase6 =0.6 37 sta r ting f r om do wn- slop e. pre-sel e ct r phase11 =r phase21 =r phase31 =r phase41 =r ph ase51 = r pha se61 =10 k , ? = ? ? = ? ? = 9 . 16 10 * 10 628 . 0 1 628 . 0 1 3 11 1 1 12 r phase22 =7. 15k , r phas e32 =2. 5 5 k , r phase42 =3. 24k , p phase52 =7. 8 7 k , r phase62 = 17.4 k page 2 7 of 39 10/ 01 /04
ir3081 boo t str a p capacitor c bst cho o s e c bst =0. 1 u f deco upling capa citor s for phase ic and po w e r s t age cho o s e c vcc = 0 .1uf, c vccl =0.1uf voltage loop comp ensation type ii comp ensation i s u s ed fo r the co nverter with al-pol ymer o u tput ca pa citors. cho o se the cro s sover freque ncy fc=4 0khz, wh ich is 1/1 0 of the swit chin g freque ncy pe r phase, and d e termin e rcp and c cp . : k r c f v v r c l f r c c o ramp fb e e c cp 0 . 2 ) 10 * 7 * 10 * 560 * 10 * 40 * 2 ( 1 * ) 10 20 35 . 1 ( 8 . 0 365 ) 10 10 560 ( ) 6 / 10 220 ( ) 10 40 2 ( ) * * * 2 ( 1 * ) 2 ( 2 3 6 3 3 6 9 2 3 2 2 s s s s nf r c l c cp e e cp 71 10 0 . 2 ) 10 * 10 560 ( ) 6 / 10 220 ( 10 10 3 6 9 , choo se c cp =68 n f cho o s e c cp1 =47 p f to red u ce hi gh freq uen cy noise. current s h are loop compens a tion the cro s sove r frequ en cy of the current sha r e loo p f ci shoul d be at least one d e c ad e lower th an that of the voltage loop f c . choo se the cro s so ver frequ en cy of current sh are loo p f ci =4 kh z , a nd calculate c sco m p , 011 . 0 ) 35 . 1 12 ( * ) 35 . 1 8 . 0 12 ( 8 . 0 * 10 * 400 * 10 * 220 * 10 * 2 . 16 ) ( * ) ( * * * 3 12 3 dac i dac pwmrmp i pwmrmp sw pwmrmp pwmrmp mi v v v v v v f c r f 6 _ 10 * 05 . 1 * 2 * )] ( * * * 2 1 [ * * * * * * 65 . 0 ci o mi o o e ci le room cs o i pwmrmp scomp f v f i v c f r g i v r c s s 6 3 4 4 6 3 3 3 10 * 05 . 1 * 10 * 4 2 ) 10 * 1 . 9 * 105 33 . 1 ( 011 . 0 * ] 105 ) 10 * 1 . 9 * 105 33 . 1 ( * 10 * 10 * 560 * 10 * 4 * 2 1 [ * ) 6 10 * 47 . 0 ( * 34 * 105 * 12 * 10 * 2 . 16 * 65 . 0 s s nf 4 . 31 cho o s e c sc o m p =33nf. page 2 8 of 39 10/ 01 /04
ir3081 design example 2 - evrd 10 high frequency all-ce ramic converte r specifications input voltage : v i =12 v dac voltag e: v dac = 1 .3 v no lo ad out put voltage o ffset: v o_nlof st =20 mv output current: i o =105 a dc maximum output current: i oma x =120 a dc output imped ance: r o =0. 9 1 m ? ? ? ros c once the swi t ching f r equ e n cy is ch ose n , r os c can be dete r min ed from th e curve in fig u r e 1 3 data sheet. for swit chin g freq uen cy of 800 khz pe r pha se, choo se r os c =13.3 k ? c ss/ del and resistor r ss/del bec a us e fast er ove r -cu r re nt prote c tion is requi re d, the soft sta r t ca pa citor c ss/del in series with the res i s t or r ss/del is used. cal c ulate the soft start cap a cito r fro m the requi re d soft start time. uf v t i c o ss chg del ss 16 . 0 10 * 20 3 . 1 10 * 9 . 2 10 * 70 3 3 6 / , choo se c ss/ del =0.15uf cal c ulate the soft start re si stor fro m the requi re d over current del ay time t ocdel , : k i c i t r dischg del ss dischg ocdel del ss 1 10 * 6 10 * 15 . 0 10 * 6 10 * 1 . 2 09 . 0 09 . 0 6 6 6 3 / / the s o ft s t art delay time is ms i i r c t chg chg del ss del ss ssdel 6 . 2 10 * 70 ) 10 * 70 * 10 * 1 3 . 1 ( 10 * 15 . 0 ) 3 . 1 ( 6 6 3 6 / / the po we r go od delay time is ms i v c t chg o del ss vccpg 85 . 2 10 * 70 ) 3 . 1 28 . 1 91 . 3 ( * 10 * 15 . 0 ) 3 . 1 91 . 3 ( 6 6 / page 2 9 of 39 10/ 01 /04
ir3081 vdac sle w rate progra mming capa citor c vdac and re sisto r r vdac from figu re 15, the sin k curre n t of v d ac pin corresp ondi ng to 800 khz (r os c =13.3 k ? nf sr i c down sink vdac 68 10 / 10 * 5 . 2 10 * 170 6 3 6 cal c ulate the prog ram m ing resi stor. : 2 . 1 ) 10 * 68 ( 10 * 2 . 3 5 . 0 10 * 2 . 3 5 . 0 2 9 15 2 15 vdac vdac c r from fig u re 15, the sou r ce curre n t of vdac pin i s 25 0ua. the vdac up-slo pe sle w rate is us mv c i sr vdac source up / 7 . 3 10 * 68 10 * 250 9 6 ov er current setting res i stor r o c set the room te mperature is 25oc an d the target p c b t e mpe r at ure i s 1 00 o c . th e pha se ic di e tempe r atu r e is abo ut 1 oc high er tha n that of phase ic, and the indu ct or temp eratu r e is clo s e to pcb temperature. cal c ulate ind u ctor dc re si stan ce at 100 oc, : m t t r r room max l room l max l 64 . 0 )] 25 100 ( 10 * 3850 1 [ 10 * 5 . 0 )] ( 10 * 3850 1 [ 6 3 _ 6 _ _ the cu rrent sense amplifie r gain is 3 4 at 25oc, and its gain at 101o c is calculate d as, 2 . 30 )] 25 101 ( 10 * 1470 1 [ 34 )] ( 10 * 1470 1 [ 6 _ 6 _ _ room max ic room cs min cs t t g g set the over current limit at 135a. from fi gu re 1 4 , the bias curre n t of ocset pin (i o c set ) is 90ua with r os c =13.3 k ? n i f v l v v v k limit sw i o o i p ocset min cs tofst cs p max l limit ocset i g v k r n r r / ] ) 1 ( [ _ _ _ : k 34 . 6 ) 10 * 90 /( 2 . 30 * ) 10 * 55 . 0 32 . 1 10 * 64 . 0 6 135 ( 6 3 3 no load output voltag e setting resi stor r fb and adap tiv e voltage positio n ing resis t o r r drp from fig u re 14, the bias current of fb pin is 90ua wit h r os c =13.3 k ? max l fb o tofst cs nlofst o max l fb r i r n v v r r : 576 10 * 91 . 0 6 2 . 30 * 10 * 64 . 0 162 3 3 _ _ o min cs max l fb drp r n g r r r page 3 0 of 39 10/ 01 /04
ir3081 bod y braking related re sistors r bbfb and r bbdr p n/a. the bod y brakin g du ri ng dynami c vid is disa ble d . ir3086 external comp onents pwm ram p resis t or r pw mr mp and capa citor c p w mr mp set pwm ra mp magnitu d e v pwmrmp =0.75v. choo se 100pf fo r pwm ram p capa citor c p w mrmp , and ca lculate the resi st o r r pw mrmp , )] ln( ) [ln( * * * pwmrmp dac in dac in pwmrmp sw in o pwmrmp v v v v v c f v v r ? ? ? ? = ? = ? ? ? ? ? ? ? ? 2 . 18 )] 75 . 0 3 . 1 12 ln( ) 3 . 1 12 [ln( 12 10 * 100 3 10 * 800 12 28 . 1 = inductor cur r ent sen s ing capaci tor c cs+ and resi stors r cs+ a nd r cs- cho o se 47nf for cap a cito r c cs+, and cal c ulate r cs+, ? = = = ? ? ? + + 22 . 4 10 * 47 ) 10 * 5 . 0 /( 10 * 100 9 3 9 the bia s cu rrents of csin+ and cs in- are 0.25 ua a nd 0.4ua re spec tively. cal c ulate resi sto r r cs- , ? = ? = ? = + ? 61 . 2 10 * 22 . 4 4 . 0 25 . 0 4 . 0 25 . 0 3 combined o v er tempera t ure an d pha se delay setting re sistor s r phasex1 , r phasex2 and r phasex3 the over tem peratu r e setting re sisto r di vider is co mb ined wi th the pha se delay resi stor divide r. set the temperatu r e threshold at 115 o c , whi c h co rrespon d s to the ic di e te mpe r ature of 116 o c , and cal c ulate the hotse t thre shol d voltage co rre s po ndin g to the tempe r atu r e thre sh old s . v t v j hotset 79 . 1 241 . 1 116 10 * 73 . 4 241 . 1 10 * 73 . 4 3 3 = + ? = + ? = ? ? the p h a s e d e lay re si stor ratio s fo r p hases 1 to 6 at 8 0 0 k hz of switching frequ en cie s are ra phas e1 = 0 .665, ra phase2 =0. 432, ra phas e3 = 0 .198, ra phase4 = 0 .206, ra phase5 =0.40 1 an d ra phase6 =0.5 97 sta r ting f r om do wn- slop e. the over te mperature se tting voltage of phases 1, 2, 5, and 6 is lowe r tha n the pha se delay setting voltage, vbias*ra phasex . pre-selec t r phase11 =10 k , ? = ? ? ? ? ? = ? ? ? ? = 1 . 12 ) 665 . 0 1 ( 8 . 6 10 * 10 ) 79 . 1 8 . 6 665 . 0 ( ) 1 ( * ) ( 3 1 2 ? = ? ? = ? ? = 87 . 7 ) 665 . 0 1 ( * 8 . 6 10 * 1 . 12 79 . 1 ) 1 ( * 3 1 3 r phase21 = 10k , r phase22 =2. 9 4 k , r p h ase23 =4. 6 4 k r phase51 = 10k , r phase52 =2. 3 2 k , r p h ase53 =4. 4 2 k r phase61 = 10k , r phase62 =8. 2 5 k , r p h ase63 =6. 4 9 k page 3 1 of 39 10/ 01 /04
ir3081 the over tem peratu r e setting voltage of phase s 3 a n d 4 is highe r than the pha se delay setting voltage, vbias*ra phasex . pre-selec t r phasex1 =10 k ? hotset bias phase bias phase hotset phase v v r v ra v r : k v v r v ra r hotset bias phase bias phase phase 67 . 2 79 . 1 8 . 6 10 * 10 8 . 6 198 . 0 * 3 31 3 33 r phase41 = 10k ? ? ? khz r r g c r f le fb cs e drp c 146 ) 6 / 10 * 5 . 0 ( 162 34 ) 10 * 22 62 ( 2 576 2 3 6 1 s s q 63 180 ) 5 . 0 tan( 90 1 s t a c cho o s e : 110 162 3 2 3 2 1 fb fb r r cho o se the d e sired cro s so ver frequ en cy fc (=1 4 0 k hz) aroun d fc1 e s timated ab o v e, and cal c ul ate nf r f c fb c fb 2 . 5 110 10 * 140 4 1 4 1 3 1 s s , choo se c fb =5. 6 n f nf r c r r c drp fb fb fb drp 7 . 2 576 10 * 6 . 5 ) 110 162 ( ) ( 9 1 : k v v r c l f r o ramp fb e e c cp 65 . 1 10 * 20 3 . 1 75 . 0 * 162 ) 62 10 * 22 ( ) 6 / 10 * 100 ( ) 10 * 140 2 ( ) 2 ( 3 6 9 2 3 2 s s nf r c l c cp e e cp 27 10 65 . 1 ) 62 * 10 * 22 ( ) 6 / 10 * 100 ( 10 10 3 6 9 cho o s e c cp1 =47 p f to red u ce hi gh freq uen cy noise. current s h are loop compens a tion the cro s sove r frequ en cy of the current sha r e loo p f ci shoul d be at least one d e c ad e lower th an that of the voltage loop f c . choo se the cro s so ver frequ en cy of current sh are loo p f ci =3 . 5 kh z , a nd ca lculate c sco m p , page 3 2 of 39 10/ 01 /04
ir3081 011 . 0 ) 3 . 1 12 ( * ) 3 . 1 75 . 0 12 ( 75 . 0 * 10 * 800 * 10 * 100 * 10 * 2 . 18 ) ( * ) ( * * * 3 12 3 dac i dac pwmrmp i pwmrmp sw pwmrmp pwmrmp mi v v v v v v f c r f 6 _ 10 * 05 . 1 * 2 * )] ( * * * 2 1 [ * * * * * * 65 . 0 ci o mi o o e ci le room cs o i pwmrmp scomp f v f i v c f r g i v r c s s 6 4 4 6 3 3 10 * 05 . 1 * 3500 2 ) 10 * 1 . 9 * 105 33 . 1 ( 011 . 0 * ] 105 ) 10 * 1 . 9 * 105 33 . 1 ( * 62 * 10 * 22 * 3500 * 2 1 [ * ) 6 10 * 5 . 0 ( * 34 * 105 * 12 * 10 * 2 . 18 * 65 . 0 s s nf 6 . 20 cho o s e c sc o m p =22nf page 3 3 of 39 10/ 01 /04
ir3081 layout guidelines the followi ng layout guide lines a r e recommen ded t o redu ce the para s itic ind u ctan ce a nd resi stan ce of the pcb layout, therefore minimi zin g the noise couple d to the ic. x dedi cate at le ast one mid d l e layer for a g r oun d plan e l g nd. x con n e c t the grou nd tab u nder the cont rol ic to lg nd plan e throu gh a via. x place th e foll owin g critical comp one nts on the sa me l a yer a s cont rol ic a nd position them a s clo s e a s po ssible to the re spe c tive pins, r os c , r o c set , r vdac , c vda c , c vcc , c ss /del and r cc/del . avoid using any via for th e c o nn ec tio n . x place th e co mpen sation compon ents o n the sam e la yer a s cont rol ic a nd po sition them a s cl ose a s p o ssi b le to eaout, fb and vdrp pi n s . avoid usin g any via for the co nne ctio n. x use kelvin conne ction s fo r the remote voltage sen s e si g nal s, vo sns+ a nd v o sns-, a nd avoid cro s sin g over the fast tran si tion node s, i.e. switching n ode s, gate dri v e signal s an d bootst rap n ode s. x control bu s sign als, vda c , rmpo ut, iin, vbias, and e s p e ci a lly eaout, sho u ld n o t cross over th e fast transitio n nod es. page 3 4 of 39 10/ 01 /04
ir3081 pcb me tal a nd compon e n t placemen t ? ? ? ?
ir3081 solder resis t ? ? ? ? ? ?
ir3081 stencil de sign x the sten cil a pertu re s for t he lea d lan d s shoul d be approximatel y 80% of the are a of the lead la nd s. red u ci ng the amount of solder dep osit ed will mini mi ze the o c cu rrence of lead sho r ts. since for 0.5mm pitch devi c e s the lead s are only 0.25m m wide, t he sten cil ape rt ure s shoul d not be mad e narrower; openi ng s in stencil s < 0.25 mm wide a r e difficult to maintain rep eata b le sol der rel ease. x the sten cil le ad la nd a p e r ture s sho u ld t herefo r e be shorten ed i n le ngth by 80% and ce ntere d on the lea d land. x the la nd pa d ap ertu re sho u ld be striped with 0.25mm wid e op enin g s and sp aces to de po sit approximatel y 50% area of solder on th e cente r pad. if too much sold er is de p o sited on the center pa d the part will float and the le ad land s will be ope n. x the maximu m length and width of the land pad st encil a pertu re sho u ld be equal to the sold er resi st openi ng min u s an ann ular 0.2mm pull b a ck to de crea se t he i n ci de nce of sh ortin g the center l and to the lead lan d s wh en the part is pushed into t he sol der p a ste. page 3 7 of 39 10/ 01/04
ir3081 perform ance characte r istics fi g u r e 13 - o s ci l l at or fr e q u e ncy v e r s us r o sc 15 0 20 0 25 0 30 0 35 0 40 0 45 0 50 0 55 0 60 0 65 0 70 0 75 0 80 0 85 0 90 0 95 0 10 00 10 15 2 0 25 30 35 4 0 45 50 55 60 6 5 70 75 80 8 5 90 95 1 0 0 ro s c ( k o h m s ) o s c i l l a t or fr e q ue nc y ( k h z ) f i g u re 1 4 - if b , b b f b , & oc s e t b i a s c u rr e n ts v s r o s c 5 15 25 35 45 55 65 75 85 95 10 5 11 5 12 5 10 15 20 2 5 30 35 40 4 5 50 5 5 60 65 7 0 7 5 80 85 9 0 95 1 0 0 ro s c ( k o h m ) ua f i g u r e 1 5 - vd a c sou r c e & si nk c u r r e nt s v c r o sc ( i nc l u de s o c set bi as c u r r e n t ) 0 25 50 75 100 125 150 175 200 225 250 275 300 325 10 15 20 25 30 35 40 45 50 5 5 60 65 70 75 80 8 5 90 95 1 0 0 ro s c (k o h m ) ua is in k i s o urce f i g u r e 16 - b i as c u r r e n t a c cu r a c y ve r s u s r o sc ( i n c l u d e s t e m p er at ur e a n d i n put vol t a g e va r i at i o n) 0% 2% 4% 6% 8% 10 % 12 % 14 % 1 0 1 5 20 25 30 35 40 45 50 55 60 65 70 75 80 85 90 95 1 0 0 ro s c (k o h m ) + / - 3 s i gm a v a r i a t i on ( % ) f b , bb f b , o c se t bi a s c u r r ent v d a c s i nk c u r r ent v d a c s o u r c e cur rent page 3 8 of 39 10/ 01/04
ir3081 package information 28l mlpq (5 x 5 mm body ) ? data an d sp e c ificatio ns su bject to ch an ge witho u t no tice. this p r od uct has b een d e signed a nd qu alified for the con s um er m a rket. qualification standards ca n be found o n ir?s we b sit e . ir wo rl d h e adq u a r t ers: 233 kansas st., el segundo, calif orni a 90245, usa te l: (310) 252-7105 tac fax: (31 0 ) 252 -7 903 ww w.irf.co m page 3 9 of 39 10/ 01 /04

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