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hd404889/hd404899/hd404878/ hd404868 series low-voltage as microcomputers with on-chip lcd circuit ade-202-075d (o) rev. 5.0 feb. 2000 description the hd404889, hd404899, and hd404868 series comprise low-voltage, 4-bit single-chip microcomputers with a variety of on-chip supporting functions that include an lcd circuit, a/d converter, multifunctional timers, and large-current i/o pins. these devices are suitable for system and display panel control in a wide range of applications, including pagers, remote controllers, and home appliances equipped with an lcd display. the hd404878 series comprises low-voltage, 4-bit single-chip microcomputers with no on-chip a/d converter. each series is equipped with a 32.768 khz sub-resonator for realtime clock use, providing a time counting facility, and a variety of low-power modes to reduce current drain. the hd4074889, hd4074899, and hd4074869 are ztat? microcomputers with on-chip prom that drastically shortens development time and ensures a smooth transition from debugging to mass production. (the prom programming specifications are the same as for the 27256 type.) ztat tm : zero turn-around time. ztat tm is a trademark of hitachi, ltd. features 46 i/o pins (hd404889/hd404899/hd404878 series) 41 i/o pins (hd404868 series) large-current i/o pins (source: 10 ma max.):4 large-current i/o pins (sink: 15 ma max.): 8 (hd404889/hd404899/hd404878 series) 6 (hd404868 series) lcd segment multiplexed pins:16 analog input multiplexed pins: 6 (hd404889 and hd404899 series) 4 (hd404868 series)
hd404889/hd404899/hd404878/hd404868 series 2 ? four timer/counters 8-bit timer: 2 (hd404889/hd404899/hd404878 series) 1 (hd404868 series) 16-bit timer:1 (can also be used as two 8-bit timer) ? 8-bit input capture circuit (hd404889/hd404899/hd404878 series) ? two timer outputs (including pwm out-put) ? two event counter inputs (edge-programmable) (hd404889/hd404899/hd404878 series) one event counter input (edge-programmable) (hd404868 series) ? clock-synchronous 8-bit serial interface ? a/d converter 6 channels 8-bit (hd404889 series) 6 channels 10-bit (hd404899 series) 4 channels 10-bit (hd404868 series) ? lcd controller/driver (32 segments 4 commons) (hd404889/hd404899/hd404878 series) (24 segments 4 commons) (hd404868 series) ? on-chip oscillators ? main clock (ceramic resonator, crystal resonator, or external clock operation possible) ? sub-clock (32.768 khz crystal resonator) ? interrupts external: 3 (including one edge-programmable) internal : 6 (hd404889 and hd404899 series) : 5 (hd404878 and hd404868 series) ? subroutine stack up to 16 levels, including interrupts ? four low-power dissipation modes ? module standby (timers, serial interface, a/d converter) ? system clock division software switching (1/4 or 1/32) ? inputs for return from stop mode (wakeup): 4 ? instruction execution time min. 0.89 m s (f osc = 4.5 mhz) ? operation voltage 1.8 v to 5.5 v cautions about operation! ? electrical properties presented on the data sheet for the mask rom and ztat tm versions will surely and sufficiently satisfy the standard values. however, real capabilities, operation margin, noise margin, and other properties may vary depending on differences of manufacturing processes, internal wiring patterns, etc. therefore, it is requested for users to carry out an evaluation test for each product on an actual system under the same conditions to see its operation. ? memory register, data area, and stack area values are unstable immediately after power is turned on. they must be initialized before use.
hd404889/hd404899/hd404878/hd404868 series 3 ordering information hd404889 series type product name model name rom (words) ram (digits) package mask rom hd404888 hd404888h 8,192 1,344 80-pin plastic qfp (fp-80a) hd404888te 80-pin plastic tqfp (tfp-80c) hd4048812 hd4048812h 12,288 80-pin plastic qfp (fp-80a) hd4048812te 80-pin plastic tqfp (tfp-80c) hd404889 HD404889H 16,384 80-pin plastic qfp (fp-80a) hd404889te 80-pin plastic tqfp (tfp-80c) hcd404889 hcd404889 chip * 2 ztat tm hd4074889 hd4074889h 16,384 80-pin plastic qfp * 1 (fp-80a) hd4074889te 80-pin plastic tqfp * 1 (tfp-80c) notes: 1. ztat tm chip shipment is not supported. 2. the specifications of shipped chips differ from those of the package product. please contact our sales staff for details.
hd404889/hd404899/hd404878/hd404868 series 4 hd404899 series type product name model name rom (words) ram (digits) package mask rom hd404898 hd404898h 8,192 1,344 80-pin plastic qfp (fp-80a) hd404898te 80-pin plastic tqfp (tfp-80c) hd4048912 hd4048912h 12,288 80-pin plastic qfp (fp-80a) hd4048912te 80-pin plastic tqfp (tfp-80c) hd404899 hd404899h 16,384 80-pin plastic qfp (fp-80a) hd404899te 80-pin plastic tqfp (tfp-80c) hcd404899 hcd404899 chip * 2 ztat tm hd4074899 hd4074899h 16,384 80-pin plastic qfp * 1 (fp-80a) hd4074899te 80-pin plastic tqfp * 1 (tfp-80c) notes: 1. ztat tm chip shipment is not supported. 2. the specifications of shipped chips differ from those of the package product. please contact our sales staff for details. in planning stage. hd404878 series type product name model name rom (words) ram (digits) package mask rom hd404874 hd404874h 4,096 880 80-pin plastic qfp (fp-80a) hd404874te 80-pin plastic tqfp (tfp-80c) hd404878 hd404878h 8,192 80-pin plastic qfp (fp-80a) hd404878te 80-pin plastic tqfp (tfp-80c) hcd404878 hcd404878 chip * 2 ztat tm hd4074889 or hd4074899 is used. * 1 notes: 1. ztat tm chip shipment is not supported. 2. the specifications of shipped chips differ from those of the package product. please contact our sales staff for details. in planning stage.
hd404889/hd404899/hd404878/hd404868 series 5 hd404868 series type product name model name rom (words) ram (digits) package mask rom hd404864 hd404864h 4,096 408 64-pin plastic qfp (fp-64a) hd404864s 64-pin plastic dilp (dp-64s) hd404868 hd404868h 8,192 64-pin plastic qfp (fp-64a) hd404868s 64-pin plastic dilp (dp-64s) hcd404868 hcd404868 chip * 1 ztat tm hd4074869 hd4074869h 16,384 64-pin plastic qfp (fp-64a) hd4074869s 64-pin plastic dilp (dp-64s) note: 1. in planning stage
hd404889/hd404899/hd404878/hd404868 series 6 list of functions product name hd404888 hd4048812 hd404889 hcd404889 rom (words) 8,192 12,288 16,384 ram (digit) 1,344 i/o 46 (max) large-current i/o pins 4 (source, 10 ma max), 8 (sink, 15 ma max) lcd segment multiplexed pins 16 analog input multiplexed pins 6 timer/counter 16-bit timer: 1 (can also be used as two 8-bit timer), 8-bit timer: 2 input capture 8 bit 1 timer output 2 (pwm output possible) event input 2 (edge selection possible) serial interface 1 (8-bit synchronous) a/d converter 8 bits 6 channels lcd circuit max. 32 seg 4 com interrupt sources external 3 (edge selection possible for 1) internal 6 low-power modes 4 stop mode o watch mode o standby mode o subactive mode o module standby o system clock division software switching o main oscillator ceramic oscillation o crystal oscillation o sub-oscillator crystal oscillation o (32.768khz) minimum instruction execution time 0.89 m s(f osc =4.5mhz) operating voltage (v) 1.8 to 5.5 package 80-pin plastic qfp (fp-80a) 80-pin plastic tqfp (tfp-80c) chip guaranteed operation temperature( c) ?0 to +75 +75
hd404889/hd404899/hd404878/hd404868 series 7 product name hd4074889 hd404898 hd4048912 hd404899 rom (words) 16,384prom 8,192 12,288 16,384 ram (digit) 1,344 i/o 46 (max) large-current i/o pins 4 (source, 10 ma max), 8 (sink, 15 ma max) lcd segment multiplexed pins 16 analog input multiplexed pins 6 timer/counter 16-bit timer: 1 (can also be used as two 8-bit timer), 8-bit timer: 2 input capture 8 bit 1 timer output 2 (pwm output possible) event input 2 (edge selection possible) serial interface 1 (8-bit synchronous) a/d converter 8 bits 6 channels 10 bits 6 channels lcd circuit max. 32 seg 4 com interrupt sources external 3 (edge selection possible for 1) internal 6 low-power modes 4 stop mode o watch mode o standby mode o subactive mode o module standby o system clock division software switching o main oscillator ceramic oscillation o crystal oscillation o sub-oscillator crystal oscillation o (32.768khz) minimum instruction execution time 0.89 m s(f osc =4.5mhz) operating voltage (v) 2.0 to 5.5 1.8 to 5.5 package 80-pin plastic qfp (fp-80a) 80-pin plastic tqfp (tfp-80c) guaranteed operation temperature( c) ?0 to +75
hd404889/hd404899/hd404878/hd404868 series 8 product name hd40c4899 hd4074899 hd404874 hd404878 rom (words) 16,384 16,384prom 4,096 8,192 ram (digit) 1,344 880 i/o 46 (max) large-current i/o pins 4 (source, 10 ma max), 8 (sink, 15 ma max) lcd segment multiplexed pins 16 analog input multiplexed pins 6 timer/counter 16-bit timer: 1 (can also be used as two 8-bit timer), 8-bit timer: 2 input capture 8 bit 1 timer output 2 (pwm output possible) event input 2 (edge selection possible) serial interface 1 (8-bit synchronous) a/d converter 10 bits 6 channels lcd circuit max. 32 seg 4 com interrupt sources external 3 (edge selection possible for 1) internal 6 5 low-power modes 4 stop mode o watch mode o standby mode o subactive mode o module standby o system clock division software switching o main oscillator ceramic oscillation o crystal oscillation o sub-oscillator crystal oscillation o (32.768khz) minimum instruction execution time 0.89 m s(f osc =4.5mhz) operating voltage (v) 1.8 to 5.5 2.0 to 5.5 1.8 to 5.5 package chip 80-pin plastic qfp (fp-80a) 80-pin plastic tqfp (tfp-80c) guaranteed operation temperature( c) +75 ?0 to +75
hd404889/hd404899/hd404878/hd404868 series 9 product name hcd404878 hd404864 hd404868 hd4074869 rom (words) 8,192 4,096 8,192 16,384prom ram (digit) 880 408 i/o 46 (max) 41 (max) large-current i/o pins 4 (source, 10 ma max), 8 (sink, 15 ma max) 4 (source, 10 ma max), 6 (sink, 15 ma max) lcd segment multiplexed pins 16 analog input multiplexed pins 4 timer/counter 16-bit timer: 1 (can also be used as two 8-bit timer), 8-bit timer: 2 16-bit timer: 1 (can also be used as two 8-bit timer), 8-bit timer: 1 input capture 8 bit 1 timer output 2 (pwm output possible) event input 2 (edge selection possible) 1 (edge selection possible) serial interface 1 (8-bit synchronous) a/d converter 10 bits 4 channels lcd circuit max. 32 seg 4 com max. 24 seg 4 com interrupt sources external 3 (edge selection possible for 1) internal 5 low-power modes 4 stop mode o watch mode o standby mode o subactive mode o module standby o system clock division software switching o main oscillator ceramic oscillation o crystal oscillation o sub-oscillator crystal oscillation o (32.768khz) minimum instruction execution time 0.89 m s(f osc =4.5mhz) operating voltage (v) 1.8 to 5.5 2.0 to 5.5 package chip 64-pin plastic qfp (fp-64a) 64-pin plastic dilp (dp-64s) guaranteed operation temperature( c) +75 ?0 to +75
hd404889/hd404899/hd404878/hd404868 series 10 pin arrangement avcc r7 0 /an 0 r7 1 /an 1 r7 2 /an 2 r7 3 /an 3 r8 0 /an 4 r8 1 /an 5 avss test osc 1 ocs 2 gnd x2 x1 reset vcc d 0 / int 0 d 1 /int 1 d 2 d 3 d 4 d 5 d 6 d 7 d 8 d 9 d 10 d 11 r0 0 / wu 0 r0 1 / wu 1 r0 2 / wu 2 r0 3 / wu 3 r1 0 /evnb r1 1 /evnd r1 2 /buzz r1 3 /tob r2 0 /toc r2 1 / sck r2 2 /si/so r2 3 seg20 seg19 seg18 seg17 r6 3 /seg16 r6 2 /seg15 r6 1 /seg14 r6 0 /seg13 r5 3 /seg12 r5 2 /seg11 r5 1 /seg10 r5 0 /seg9 r4 3 /seg8 r4 2 /seg7 r4 1 /seg6 r4 0 /seg5 r3 3 /seg4 r3 2 /seg3 r3 1 /seg2 r3 0 /seg1 v 0 v 1 v 2 v 3 com4 com3 com2 com1 seg32 seg31 seg30 seg29 seg28 seg27 seg26 seg25 seg24 seg23 seg22 seg21 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 fp-80a tfp-80c (top view) hd404889/hd404899 series
hd404889/hd404899/hd404878/hd404868 series 11 nc r7 0 r7 1 r7 2 r7 3 r8 0 r8 1 nc test osc 1 osc 2 gnd x2 x1 reset vcc d 0 / int 0 d 1 /int 1 d 2 d 3 d 4 d 5 d 6 d 7 d 8 d 9 d 10 d 11 r0 0 / wu 0 r0 1 / wu 1 r0 2 / wu 2 r0 3 / wu 3 r1 0 /evnb r1 1 /evnd r1 2 /buzz r1 3 /tob r2 0 /toc r2 1 / sck r2 2 /si/so r2 3 seg20 seg19 seg18 seg17 r6 3 /seg16 r6 2 /seg15 r6 1 /seg14 r6 0 /seg13 r5 3 /seg12 r5 2 /seg11 r5 1 /seg10 r5 0 /seg9 r4 3 /seg8 r4 2 /seg7 r4 1 /seg6 r4 0 /seg5 r3 3 /seg4 r3 2 /seg3 r3 1 /seg2 r3 0 /seg1 v 0 v 1 v 2 v 3 com4 com3 com2 com1 seg32 seg31 seg30 seg29 seg28 seg27 seg26 seg25 seg24 seg23 seg22 seg21 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 fp-80a tfp-80c (top view) hd404878 series
hd404889/hd404899/hd404878/hd404868 series 12 hd404868 series r70/an0 r71/an1 r72/an2 r73/an3 test osc1 osc2 gnd x2 x1 reset vcc d0/ int 0 d1/int1 d2 d3 d4 d5 d6 d7 d8 d9 r00/ wu 0 r01/ wu 1 r02/ wu 2 r10/evnb r11 r12/buzz r13/tob r20/toc r21/ sck r22/si/so r62/seg15 r61/seg14 r60/seg13 r53/seg12 r52/seg11 r51/seg10 r50/seg9 r43/seg8 r42/seg7 r41/seg6 r40/seg5 r33/seg4 r32/seg3 r31/seg2 r30/seg1 r23 v1 v2 v3 com4 com3 com2 com1 seg24 seg23 seg22 seg21 seg20 seg19 seg18 seg17 r63/seg16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 fp-64a (top view) com1 com2 com3 com4 v3 v2 v1 r70/an0 r71/an1 r72/an2 r73/an3 test osc1 osc2 gnd x2 x1 reset vcc d0/ int 0 d1/int1 d2 d3 d4 d5 d6 d7 d8 d9 r00/ wu 0 r01/ wu 1 r02/ wu 2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 seg24 seg23 seg22 seg21 seg20 seg19 seg18 seg17 r63/seg16 r62/seg15 r61/seg14 r60/seg13 r53/seg12 r52/seg11 r51/seg10 r50/seg9 r43/seg8 r42/seg7 r41/seg6 r40/seg5 r33/seg4 r32/seg3 r31/seg2 r30/seg1 r23 r22/si/so r21/ sck r20/toc r13/tob r12/buzz r11 r10/evnb dp-64s (top view)
hd404889/hd404899/hd404878/hd404868 series 13 pad arrangement hcd404889, hcd404899 2 4 6 8 10 12 14 16 18 20 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 22 24 26 28 30 32 34 36 38 40 80 78 76 74 72 70 68 66 64 62 79 77 75 73 71 69 67 65 63 61 60 58 56 54 52 50 48 46 44 42 59 57 55 53 51 49 47 45 43 41 model name model name: hd404889 (hcd404889) hd404899 (hcd404899)
hd404889/hd404899/hd404878/hd404868 series 14 pad coordinates hcd404889, hcd404899 chip size (x y): coordinates: home point position: pad size (x y): chip thickness: 4.63 4.77 (mm) pad center chip center 90 90 ( m) 280 ( m) chip center (x=0,y=0) y x mold coodinates coodinates pad no. pad name x ( m m) y ( m m) pad no. pad name x ( m m) y ( m m) 1 av cc ?129 1779 41 r30/seg1 2129 ?787 2 r70/an0 ?129 1589 42 r31/seg2 2129 ?616 3 r71/an1 ?129 1417 43 r32/seg3 2129 ?445 4 r72/an2 ?129 1246 44 r33/seg4 2129 ?273 5 r73/an3 ?129 1074 45 r40/seg5 2129 ?102 6 r80/an4 ?129 903 46 r41/seg6 2129 ?73 7 r81/an5 ?129 732 47 r42/seg7 2129 ?59 8 av ss ?129 506 48 r43/seg8 2129 ?88 9 test ?129 103 49 r50/seg9 2129 ?17 10 osc1 ?129 ?8 50 r51/se10 2129 ?45 11 osc2 ?129 ?40 51 r52/seg11 2129 ?4 12 gnd ?129 ?34 52 r53/seg12 2129 98 13 x2 ?129 ?05 53 r60/seg13 2129 269 14 x1 ?129 ?76 54 r61/seg14 2129 440 15 resetn ?129 ?48 55 r62/seg15 2129 612 16 v cc ?129 ?119 56 r63/seg16 2129 783 17 d0/int0n ?129 ?290 57 seg17 2129 954 18 d1/int1 ?129 ?462 58 seg18 2129 1126 19 d2 ?129 ?633 59 seg19 2129 1297 20 d3 ?129 ?804 60 seg20 2129 1477 21 d4 ?677 ?199 61 seg21 1588 2199 22 d5 ?506 ?199 62 seg22 1407 2199 23 d6 ?335 ?199 63 seg23 1236 2199 24 d7 ?163 ?199 64 seg24 1064 2199 25 d8 ?92 ?199 65 seg25 893 2199 26 d9 ?21 ?199 66 seg26 722 2199 27 d10 ?49 ?199 67 seg27 550 2199 28 d11 ?78 ?199 68 seg28 379 2199 29 r00/wu0n ?07 ?199 69 seg29 208 2199 30 r01/wu1n ?35 ?199 70 seg30 36 2199 31 r02/wu2n 36 ?199 71 seg31 ?35 2199 32 r03/wu3n 208 ?199 72 seg32 ?07 2199 33 r10/evnb 379 ?199 73 com1 ?78 2199 34 r11/evnd 550 ?199 74 com2 ?49 2199 35 r12/buzz 722 ?199 75 com3 ?21 2199 36 r13/tob 893 ?199 76 com4 ?92 2199 37 r20/toc 1064 ?199 77 v3 ?163 2199 38 r21/sckn 1236 ?199 78 v2 ?335 2199 39 r22/si/so 1407 ?199 79 v1 ?506 2199 40 r23 1588 ?199 80 v0 ?677 2199
hd404889/hd404899/hd404878/hd404868 series 15 pad arrangement hcd404878 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 model name model name: hd404878 (hcd404878)
hd404889/hd404899/hd404878/hd404868 series 16 pad coordinates hcd404878 chip size (x y): coordinates: home point position: pad size (x y): chip thickness: 4.13 4.26 (mm) pad center chip center 90 90 ( m) 280 ( m) y chip center (x=0,y=0) x mold coodinates coodinates pad no. pad name x ( m m) y ( m m) pad no. pad name x ( m m) y ( m m) 1 r70 ?879 1446 40 r31/seg2 1879 ?405 2 r71 ?879 1280 41 r32/seg3 1879 ?239 3 r72 ?879 1114 42 r33/seg4 1879 ?072 4 r73 ?879 948 43 r40/seg5 1879 ?06 5 r80 ?879 781 44 r41/seg6 1879 ?40 6 r81 ?879 615 45 r42/seg7 1879 ?73 7 test ?879 449 46 r43/seg8 1879 ?07 8 osc1 ?879 282 47 r50/seg9 1879 ?41 9 osc2 ?879 116 48 r51/se10 1879 ?4 10 gnd ?879 ?3 49 r52/seg11 1879 92 11 x2 ?879 ?39 50 r53/seg12 1879 258 12 x1 ?879 ?06 51 r60/seg13 1879 425 13 resetn ?879 ?72 52 r61/seg14 1879 591 14 v cc ?879 ?38 53 r62/seg15 1879 757 15 d0/int0n ?879 ?05 54 r63/seg16 1879 924 16 d1/int1 ?879 ?071 55 seg17 1879 1087 17 d2 ?879 ?237 56 seg18 1879 1246 18 d3 ?879 ?404 57 seg19 1879 1405 19 d4 ?654 ?943 58 seg20 1879 1564 20 d5 ?488 ?943 59 seg21 1509 1943 21 d6 ?322 ?943 60 seg22 1351 1943 22 d7 ?155 ?943 61 seg23 1192 1943 23 d8 ?89 ?943 62 seg24 1033 1943 24 d9 ?23 ?943 63 seg25 874 1943 25 d10 ?56 ?943 64 seg26 716 1943 26 d11 ?90 ?943 65 seg27 557 1943 27 r00/wu0n ?24 ?943 66 seg28 398 1943 28 r01/wu1n ?58 ?943 67 seg29 239 1943 29 r02/wu2n 9 ?943 68 seg30 81 1943 30 r03/wu3n 175 ?943 69 seg31 ?8 1943 31 r10/evnb 341 ?943 70 seg32 ?37 1943 32 r11/evnd 508 ?943 71 com1 ?11 1943 33 r12/buzz 674 ?943 72 com2 ?70 1943 34 r13/tob 840 ?943 73 com3 ?28 1943 35 r20/toc 1007 ?943 74 com4 ?87 1943 36 r21/sckn 1173 ?943 75 v3 ?038 1943 37 r22/si/so 1339 ?943 76 v2 ?194 1943 38 r23 1506 ?943 77 v1 ?351 1943 39 r30/seg1 1879 ?571 78 v0 ?507 1943
hd404889/hd404899/hd404878/hd404868 series 17 pin description hd404889/hd404899/hd404878 series pin number item symbol fp-80a tfp-80c i/o function power supply v cc 16 apply the power supply voltage to this pin. gnd 12 connect to ground. test test 9 input not for use by the user application. connect to gnd potential. reset reset 15 input used to reset the mcu. oscillation osc 1 10 input internal oscillator input/output pins. connect a ceramic resonator, crystal resonator, or external osc 2 11 output oscillator circuit. x1 14 input realtime clock oscillator input/output pins. connect a 32.768 khz crystal. if 32.768 khz x2 13 output crystal oscillation is not used, fix the 1 pin to v cc and leave the 2 pin open. port d 0 ? 11 17?8 i/o i/o pins addressed bit by bit. d 0 to d 3 are large-current source pins (max. 10 ma), and d 4 to d 11 are large- current sink pins (max. 15 ma). r0 0 ?6 3 r7 0 ?8 1 29?6, 2? i/o i/o pins, addressed in 4-bit units. interrupt int 0 ,int 1 17,18 input external interrupt input pins wakeup wu 0 wu 3 29?2 input input pins used for transition from stop mode to active mode. serial interface sck 38 i/o serial interface clock i/o pin si 39 input serial interface receive data input pin so 39 output serial interface transmit data output pin timer tob,toc 36,37 output timer output pins evnb,evnd 33,34 input event count input pins lcd v 0 ? 3 80?7 lcd driver power supply pins. the on-chip power supply dividing resistor can be disconnected by software. power supply conditions are: v cc v 1 v 2 v 3 gnd. com1?om4 73?6 output lcd common signal pins seg1?eg32 41?2 output lcd segment signal pins a/d converter * 1 av cc 1 a/d converter power supply pin. connect as close as possible to the v cc pin so as to be at the same potential as v cc . av ss 8 ground pin for av cc . connect as close as possible to the gnd pin so as to be at the same potential as gnd. an 0 ?n 5 2? input a/d converter analog input pins buzzer output buzz 35 output timer overflow toggle output or divided system clock output pin other nc 1, 8 * 2 connect to ground potential. notes: 1. applies to hd404889 and hd404899 series. 2. applies to hd404878 series.
hd404889/hd404899/hd404878/hd404868 series 18 hd404868 series pin number item symbol fp-64a dp-64s i/o function power supply v cc 12 19 apply the power supply voltage to this pin. gnd 8 15 connect to ground. test test 5 12 input not for use by the user application. connect to gnd potential. reset reset 11 18 input used to reset the mcu. oscillation osc 1 6 13 input internal oscillator input/output pins. connect a ceramic resonator, crystal resonator, or external osc 2 7 14 output oscillator circuit. x1 10 17 input realtime clock oscillator input/output pins. connect a 32.768 khz crystal. if 32.768 khz x2 9 16 output crystal oscillation is not used, fix the 1 pin to v cc and leave the 2 pin open. port d 0 ? 9 13?2 20?9 i/o i/o pins addressed bit by bit. d 0 to d 3 are large- current source pins (max. 10 ma), and d 4 to d 9 are large-current sink pins (max. 15 ma). r0 0 ?0 2 r1 0 ?6 3 r7 0 ?7 3 23?5 26?9 1? 30?2 33?6 8?1 i/o i/o pins, addressed in 4-bit units. interrupt int 0 ,int 1 13,14 20, 21 input external interrupt input pins wakeup wu 0 wu 2 23?5 30?2 input input pins used for transition from stop mode to active mode. serial interface sck 31 38 i/o serial interface clock i/o pin si 32 39 input serial interface receive data input pin so 32 39 output serial interface transmit data output pin timer tob,toc 29, 30 36, 37 output timer output pins evnb 26 33 input event count input pins lcd v 1 ? 3 64?2 7? lcd driver power supply pins. the on-chip power supply dividing resistor can be disconnected by software. power supply conditions are: v cc v 1 v 2 v 3 gnd. com1?om4 58?1 1? output lcd common signal pins seg1?eg24 34?7 41?4 output lcd segment signal pins a/d converter an 0 ?n 3 1? 8?1 input a/d converter analog input pins buzzer output buzz 28 35 output timer overflow toggle output or divided system clock output pin
hd404889/hd404899/hd404878/hd404868 series 19 block diagramg int 0 int 1 tob evnb toc evnd sck si/so avcc an 0 an 1 an 2 an 3 an 4 an 5 avss seg1 to seg32 com1 to com4 v0 v1 v2 v3 buzz hmcs400 cpu hd404889/hd404899 series rom ram p-mos large- current buffer n-mos large- current buffer external interrupt control circuit 8-bit timer a 8-bit timer b 8-bit timer c 8-bit timer d synchronous serial interface a/d converter 8-bit 6 channels (hd404889 series) 10-bit 6 channels (hd404899 series) lcd circuit 32-segment 4 common buzzer output circuit reset test osc1 osc2 x1 x2 vcc gnd wu 0 wu 1 wu 2 wu 3 d port r0 port r1 port r2 port r3 port r4 port r5 port r6 port r7 port r8 port d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 d 8 d 9 d 10 d 11 r0 0 r0 1 r0 2 r0 3 r1 0 r1 1 r1 2 r1 3 r2 0 r2 1 r2 2 r2 3 r3 0 r3 1 r3 2 r3 3 r4 0 r4 1 r4 2 r4 3 r5 0 r5 1 r5 2 r5 3 r6 0 r6 1 r6 2 r6 3 r7 0 r7 1 r7 2 r7 3 r8 0 r8 1 : data bus : signal line
hd404889/hd404899/hd404878/hd404868 series 20 int 0 int 1 tob evnb toc evnd sck si/so seg1 to seg32 com1 to com4 v0 v1 v2 v3 buzz hmcs400 cpu rom ram p-mos large- current buffer n-mos large- current buffer external interrupt control circuit 8-bit timer a 8-bit timer b 8-bit timer c 8-bit timer d clock-synchronous 8-bit serial interface lcd circuit 32-segment 4 common buzzer output circuit reset test osc1 osc2 x1 x2 vcc gnd wu 0 wu 1 wu 2 wu 3 d port r0 port r1 port r2 port r3 port r4 port r5 port r6 port r7 port r8 port d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 d 8 d 9 d 10 d 11 r0 0 r0 1 r0 2 r0 3 r1 0 r1 1 r1 2 r1 3 r2 0 r2 1 r2 2 r2 3 r3 0 r3 1 r3 2 r3 3 r4 0 r4 1 r4 2 r4 3 r5 0 r5 1 r5 2 r5 3 r6 0 r6 1 r6 2 r6 3 r7 0 r7 1 r7 2 r7 3 r8 0 r8 1 : data bus : signal line hd404878 series
hd404889/hd404899/hd404878/hd404868 series 21 reset test osc 1 osc 2 x1 x2 v cc gnd wu 0 wu 1 wu 2 hmcs400 cpu rom ram 8-bit timer a 8-bit timer c 8-bit timer b d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 d 8 d 9 d port r0 0 r0 1 r0 2 r1 0 r1 1 r1 2 r1 3 r2 0 r2 1 r2 2 r2 3 r3 0 r3 1 r3 2 r3 3 toc evnb tob p-mos large- current buffer n-mos large- current buffer an 0 an 1 an 2 an 3 a/d converter 4 channels 10-bit external interrupt control circuit int 0 int 1 r6 0 r6 1 r6 2 r6 3 r7 0 r7 1 r7 2 r7 3 clock-synchronous 8-bit serial interface sck si/so lcd circuit 24-segment 4 common seg1 seg24 com1 com4 v 1 v 2 v 3 buzzer output circuit buzz r4 0 r4 1 r4 2 r4 3 r5 0 r5 1 r5 2 r5 3 ~ ~ ~~ r0 port r1 port r2 port r4 port r5 port r6 port r7 port r3 port hd404868 series
hd404889/hd404899/hd404878/hd404868 series 22 memory map rom memory map the rom memory map is shown in figure 1 and is described below. vector address area ($0000 to $000f): when an mcu reset or interrupt handling is performed, the program is executed from the vector address. a jmpl instruction should be used to branch to the start address of the reset routine or the interrupt routine. zero page subroutine area ($0000 to $003f):a branch can be made to a subroutine in the area $0000 to $003f with the cal instruction. pattern area ($0000 to $0fff): rom data in the area $0000 to $0fff can be referenced as pattern data with the p instruction. program area ($0000 to $0fff(hd404874, hd404864)), ($0000 to $1fff (hd404888, hd404898, hd404878, hd404868, hcd404878)), ($0000 to $2fff (hd4048812, hd4048912)), ($0000 to $3fff (hd404889, hd404899, hcd404889, hcd404899, hd4074899, hd4074889, hd4074869))
hd404889/hd404899/hd404878/hd404868 series 23 $0000 $000f $003f $0fff $1fff $3fff $2fff vector addresses (16 words) zero page subroutine area (64 words) hd404874/hd404864 pattern/program area (4,096 words) hd404888/hd404898/hd404878/ hd404868/hcd404878 pattern/program area (8,192 words) hd4048812/hd4048912 pattern/program area (12,288 words) hd404889/hd4074889/ hd404899/hd4074899/hd4074869/ hcd404889/hcd404899 pattern/program area (16,384 words) $0000 $0001 $0002 $0003 $0004 $0005 $0006 $0007 $0008 $0009 $000a $000b $000c $000d $000e $000f jmpl instruction (jump to reset routine) jmpl instruction (jump to wu 0 to wu 3 routine) jmpl instruction (jump to int 0 routine) jmpl instruction (jump to int 1 routine) jmpl instruction (jump to timer a routine) jmpl instruction (jump to timer b/timer d routine) jmpl instruction (jump to timer c routine) jmpl instruction (jump to a/d or serial interface routine) figure 1 rom memory map ram memory map the mcu has on-chip ram comprising a memory register area, lcd data area, data area, and stack area. in addition to these areas, an interrupt control bit area, special register area, and register flag area are mapped onto ram memory space as a ram-mapped register area.the ram memory map is shown in figure 2 and described below. memory register, lcd data area, data area, and stack area values are unstable immediately after power is turned on. they must be initialized before use.
hd404889/hd404899/hd404878/hd404868 series 24 speed select reg. miscellaneous reg. edge select reg. port mode reg.0 port mode reg.1 port mode reg.2 port mode reg.3 port mode reg.4 module standby reg.1 module standby reg.2 timer mode reg.a timer mode reg.b1 timer mode reg.b2 timer mode reg.c1 timer mode reg.c2 timer mode reg.d1 timer mode reg.d2 serial mode reg.1 serial mode reg.2 serial data reg.lower serial data reg.upper a/d mode reg. a/d data reg.lower a/d data reg.upper lcd control reg. lcd mode reg. buzzer mode reg. port d 0 ~ d 3 dcr port d 4 ~ d 7 dcr port d 8 ~ d 11 dcr port r0 dcr port r1 dcr port r2 dcr port r3 dcr port r4 dcr port r5 dcr port r6 dcr port r7 dcr port r8 dcr vreg. $000 $03f $040 $04f $050 $06f $070 $08f $090 $38f $390 $25f $260 $3bf $3c0 $3ff ram-mapped register area hd404889 series memory register (mr) area (16 digits) lcd data area (32 digits) data (464 digits) stack area (64 digits) interrupt control bit area not used w w w w w w w w w w w w w r/w r/w w w r/w r/w w w r/w r/w w w r/w r/w w r r w w w w w w w w w w w w w w w r/w timer-b timer-c timer-d not used register flag area not used not used not used not used $000 $001 $002 $003 $004 $005 $006 $007 $008 $009 $00a $00b $00c $00d $00e $00f $010 $011 $012 $013 $014 $015 $016 $017 $018 $019 $01a $01b $01c $01d $01e $01f $020 $021 $022 $023 $024 $025 $026 $027 $028 $029 $02a $02b $02c $02d $02e $02f $030 $031 $032 $033 $034 $035 $036 $037 $038 $039 $03a $03b $03c $03d $03e $03f timer read reg.b lower (trbl) r timer write reg.b lower (twbl) w timer read reg.b upper (trbu) r timer write reg.b upper (twbu) w timer read reg.c lower (trcl) r timer write reg.c lower (twcl) w timer read reg.c upper (trcu) r timer write reg.c upper (twcu) w timer read reg.d lower (trdl) r timer write reg.d lower (twdl) w timer read reg.d upper (trdu) r timer write reg.d upper (twdu) w $012 $013 $016 $017 $01a $01b * not used not used v = 0 (bank = 0) data (464 digits) v = 1 (bank = 1) data (304 digits) (ssr) (mis) (esr) (pmr0) (pmr1) (pmr2) (pmr3) (pmr4) (msr1) (msr2) (tma) (tmb1) (tmb2) (trbl/twbl) (trbu/twbu) (tmc1) (tmc2) (trcl/twcl) (trcu/twcu) (tmd1) (tmd2) (trdl/twdl) (trdu/twdu) (smr1) (smr2) (srl) (sru) (amr) (adrl) (adru) (lcr) (lmr) (bmr) (dcd0) (dcd1) (dcd2) (dcr0) (dcr1) (dcr2) (dcr3) (dcr4) (dcr5) (dcr6) (dcr7) (dcr8) (v) notes: r : read w : write r/w : read/write *two registers are mapped onto the same address ($012, $013, $016, $017, $01a, $01b). * figure 2 ram memory map
hd404889/hd404899/hd404878/hd404868 series 25 speed select reg. miscellaneous reg. edge select reg. port mode reg.0 port mode reg.1 port mode reg.2 port mode reg.3 port mode reg.4 module standby reg.1 module standby reg.2 timer mode reg.a timer mode reg.b1 timer mode reg.b2 timer mode reg.c1 timer mode reg.c2 timer mode reg.d1 timer mode reg.d2 serial mode reg.1 serial mode reg.2 serial data reg.lower serial data reg.upper a/d mode reg. a/d data reg.lower a/d data reg.middle a/d data reg.upper lcd control reg. lcd mode reg. buzzer mode reg. port d 0 ~ d 3 dcr port d 4 ~ d 7 dcr port d 8 ~ d 11 dcr port r0 dcr port r1 dcr port r2 dcr port r3 dcr port r4 dcr port r5 dcr port r6 dcr port r7 dcr port r8 dcr vreg. $000 $03f $040 $04f $050 $06f $070 $08f $090 $38f $390 $25f $260 $3bf $3c0 $3ff ram-mapped register area hd404899 series memory register (mr) area (16 digits) lcd data area (32 digits) data (464 digits) stack area (64 digits) interrupt control bit area not used w w w w w w w w w w w w w r/w r/w w w r/w r/w w w r/w r/w w w r/w r/w w r r r w w w w w w w w w w w w w w w r/w timer-b timer-c timer-d not used register flag area not used not used not used $000 $001 $002 $003 $004 $005 $006 $007 $008 $009 $00a $00b $00c $00d $00e $00f $010 $011 $012 $013 $014 $015 $016 $017 $018 $019 $01a $01b $01c $01d $01e $01f $020 $021 $022 $023 $024 $025 $026 $027 $028 $029 $02a $02b $02c $02d $02e $02f $030 $031 $032 $033 $034 $035 $036 $037 $038 $039 $03a $03b $03c $03d $03e $03f timer read reg.b lower (trbl) r timer write reg.b lower (twbl) w timer read reg.b upper (trbu) r timer write reg.b upper (twbu) w timer read reg.c lower (trcl) r timer write reg.c lower (twcl) w timer read reg.c upper (trcu) r timer write reg.c upper (twcu) w timer read reg.d lower (trdl) r timer write reg.d lower (twdl) w timer read reg.d upper (trdu) r timer write reg.d upper (twdu) w $012 $013 $016 $017 $01a $01b * not used not used v = 0 (bank = 0) data (464 digits) v = 1 (bank = 1) data (304 digits) (ssr) (mis) (esr) (pmr0) (pmr1) (pmr2) (pmr3) (pmr4) (msr1) (msr2) (tma) (tmb1) (tmb2) (trbl/twbl) (trbu/twbu) (tmc1) (tmc2) (trcl/twcl) (trcu/twcu) (tmd1) (tmd2) (trdl/twdl) (trdu/twdu) (smr1) (smr2) (srl) (sru) (amr) (adrl) (adrm) (adru) (lcr) (lmr) (bmr) (dcd0) (dcd1) (dcd2) (dcr0) (dcr1) (dcr2) (dcr3) (dcr4) (dcr5) (dcr6) (dcr7) (dcr8) (v) notes: r : read w : write r/w : read/write *two registers are mapped onto the same address ($012, $013, $016, $017, $01a, $01b). * figure 2 ram memory map (cont)
hd404889/hd404899/hd404878/hd404868 series 26 speed select reg. miscellaneous reg. edge select reg. port mode reg.0 port mode reg.1 port mode reg.2 port mode reg.3 port mode reg.4 module standby reg.1 module standby reg.2 timer mode reg.a timer mode reg.b1 timer mode reg.b2 timer mode reg.c1 timer mode reg.c2 timer mode reg.d1 timer mode reg.d2 serial mode reg.1 serial mode reg.2 serial data reg.lower serial data reg.upper lcd control reg. lcd mode reg. buzzer mode reg. port d 0 ~ d 3 dcr port d 4 ~ d 7 dcr port d 8 ~ d 11 dcr port r0 dcr port r1 dcr port r2 dcr port r3 dcr port r4 dcr port r5 dcr port r6 dcr port r7 dcr port r8 dcr $000 $03f $040 $04f $050 $06f $070 $08f $090 $38f $390 $3bf $3c0 $3ff ram-mapped register area hd404878 series memory register (mr) area (16 digits) lcd data area (32 digits) data (768 digits) stack area (64 digits) interrupt control bit area not used w w w w w w w w w w w w w r/w r/w w w r/w r/w w w r/w r/w w w r/w r/w w w w w w w w w w w w w w w w timer-b timer-c timer-d not used register flag area not used not used not used not used $000 $001 $002 $003 $004 $005 $006 $007 $008 $009 $00a $00b $00c $00d $00e $00f $010 $011 $012 $013 $014 $015 $016 $017 $018 $019 $01a $01b $01c $01d $01e $01f $020 $021 $022 $023 $024 $025 $026 $027 $028 $029 $02a $02b $02c $02d $02e $02f $030 $031 $032 $033 $034 $035 $036 $037 $038 $039 $03a $03b $03c $03d $03e $03f timer read reg.b lower (trbl) r timer write reg.b lower (twbl) w timer read reg.b upper (trbu) r timer write reg.b upper (twbu) w timer read reg.c lower (trcl) r timer write reg.c lower (twcl) w timer read reg.c upper (trcu) r timer write reg.c upper (twcu) w timer read reg.d lower (trdl) r timer write reg.d lower (twdl) w timer read reg.d upper (trdu) r timer write reg.d upper (twdu) w $012 $013 $016 $017 $01a $01b not used not used (ssr) (mis) (esr) (pmr0) (pmr1) (pmr2) (pmr3) (pmr4) (msr1) (msr2) (tma) (tmb1) (tmb2) (trbl/twbl) (trbu/twbu) (tmc1) (tmc2) (trcl/twcl) (trcu/twcu) (tmd1) (tmd2) (trdl/twdl) (trdu/twdu) (smr1) (smr2) (srl) (sru) (lcr) (lmr) (bmr) (dcd0) (dcd1) (dcd2) (dcr0) (dcr1) (dcr2) (dcr3) (dcr4) (dcr5) (dcr6) (dcr7) (dcr8) notes: r : read w : write r/w : read/write *two registers are mapped onto the same address ($012, $013, $016, $017, $01a, $01b). * figure 2 ram memory map (cont)
hd404889/hd404899/hd404878/hd404868 series 27 $030 $031 $032 $033 $034 $035 $036 $037 $038 $039 $03a $03b $03c $03d $03e $03f $000 $001 $002 $003 $004 $005 $006 $007 $008 $009 $00a $00b $00c $00d $00e $00f $010 $011 $012 $013 $014 $015 $016 $017 $018 $019 $01a $01b $01c $01d $01e $01f $020 $021 $022 $023 $024 $025 $026 $027 $028 $029 $02a $02b $02c $02d $02e $02f speed select reg. miscellaneous reg. edge select reg. port mode reg.0 port mode reg.1 port mode reg.2 port mode reg.3 port mode reg.4 module standby reg.1 module standby reg.2 timer mode reg.a timer mode reg.b1 timer mode reg.b2 timer b timer mode reg.c1 timer mode reg.c2 timer c lcd control reg. lcd mode reg. buzzer mode reg. port d 0 ? 3 dcr port d 4 ? 7 dcr port d 8 ? 9 dcr port r0 dcr port r1 dcr port r2 dcr port r3 dcr port r4 dcr port r5 dcr port r6 dcr port r7 dcr interrupt control bit area register flag area (ssr) (mis) (esr) (pmr0) (pmr1) (pmr2) (pmr3) (pmr4) (msr1) (msr2) (tma) (tmb1) (tmb2) (trbl/twbl) (trbu/twbu) (tmc1) (tmc2) (trcl/twcl) (trcu/twcu) (smr1) (smr2) (srl) (sru) (amr) (adrl) (adrm) (adru) (lcr) (lmr) (bmr) (dcd0) (dcd1) (dcd2) (dcr0) (dcr1) (dcr2) (dcr3) (dcr4) (dcr5) (dcr6) (dcr7) (twbl) (twbu) (twcl) (twcu) ram-mapped register area memory register (mr) area (16 digits) lcd data area (24 digits) data (304 digits) stack area (64 digits) serial mode reg.1 serial mode reg.2 serial mode reg.lower serial mode reg.upper a/d mode reg. a/d data reg.lower a/d data reg.middle a/d data reg.upper $012 $013 $016 $017 timer read reg.b lower timer read reg.b upper timer read reg.c lower timer read reg.c upper (trbl) (trbu) (trcl) (trcu) timer write reg.b lower timer write reg.b upper timer write reg.c lower timer write reg.c upper : read : write : read/write r w r/w *two registers are mapped onto the same address ($012, $013, $016, $017). notes: $000 $03f $040 $04f $050 $067 $068 $08f $090 $1bf $1c0 $3bf $3c0 $3ff not used not used r r r r w w w w w w w w w w w w w w w w w r/w r/w w w r/w r/w w w r/w r/w w r r r w w w w w w w w w w w w w w not used not used not used not used not used hd404868 series * figure 2 ram memory map (cont)
hd404889/hd404899/hd404878/hd404868 series 28 ram-mapped register area ($000 to $03f): ? interrupt control bit area ($000 to $003) this area consists of bits used for interrupt control. its configuration is shown in figure 3. individual bits can only be accessed by ram bit manipulation instructions (sem/semd, rem/remd, tm/tmd). there are restrictions on access to certain bits. the individual bits and instruction restrictions are shown in figure 4. ? special register area ($004 to $01f, $024 to $03f) this area comprises mode registers and data registers for external interrupts, the serial interface, timers, lcd, a/d converter, etc., and i/o pin data control registers. its configuration is shown in figures 2 and 5. these registers are of three kinds: write-only (w), read-only (r), and read/write (r/w). the sem/semd and rem/remd instructions can be used on the lcd control register (lcr: $02c) and the third bit of buzzer mode register (bmr3: $02e, 3), but ram bit manipulation instructions cannot be used on the other registers. ? register flag area ($020 to $023) this area consists of the dton and wdon flags and interrupt control bits. its configuration is shown in figure 3. individual bits can only be accessed by ram bit manipulation instructions (sem/semd, rem/remd, tm/tmd). there are restrictions on access to certain bits. the individual bits and instruction restrictions are shown in figure 4. memory register (mr) area ($040 to $04f): in this data area, the 16 memory register digits (mr(0) to mr(15)) can also be accessed by the register- register instructions lamr and xmra. the configuration of this area is shown in figure 6. lcd data area: $050 to $06f (hd404889/hd404899/hd404878 series) $050 to $067 (hd404868 series) this 32-digit data area stores data to be displayed on an lcd. data written in this area is automatically outputed to segments as display data. "1" data indicates "on" and "0" data "off" (see the section of the lcd circuit for details). data area: $090 to $38f (hd404889/hd404899/hd404878 series) $090 to $1bf (hd404868 series) for the 464 digits from $090 to $25f, the bank can be switched according to the value of the bank register (v: $03f) (figure 7). the bank register value must always be set when accessing the area from $090 to $25f. the data area from $260 to $38f can be addressed without a bank register setting. stack area ($3c0 to $3ff): this is the stack area used to save the contents of the program counter (pc), status flag (st), and carry flag (ca) when a subroutine call (cal or call instruction) or interrupt handling is performed. as four digits are used for one level, the area can be used as a subroutine stack with a maximum of 16 levels. the saved data and saved status information are shown in figure 6. the program counter is restored by the rtn and rtni instructions. the status and carry flags are restored by the rtni instruction, but are not affected by the rtn instruction. any part of the area not used for saving can be used as a data area.
hd404889/hd404899/hd404878/hd404868 series 29 bit 3 imwu * 1 ( wu 0 to wu 3 interrupt mask) im1 (int 1 interrupt mask) imtb (timer b interrupt mask) imad * 3 (a/d converter interrupt mask) ram address $000 $001 $002 $003 notes: 1. wu 0 to wu 2 interrupt mask in the hd404868 series 2. wu 0 to wu 2 interrupt request flag in the hd404868 series 3. applies to the hd404889, hd404899, and hd404868 series. 4. applies to the hd404889, hd404899, and hd404878 series. bit 2 ifwu * 2 ( wu 0 to wu 3 interrupt request flag) if1 (int 1 interrupt request flag) iftb (timer b interrupt request flag) ifad * 3 (a/d converter interrupt request flag) bit 1 rsp (stack pointer reset) im0 ( int 0 interrupt mask) imta (timer a interrupt mask) imtc (timer c interrupt mask) bit 0 ie (interrupt enable flag) if0 ( int 0 interrupt request flag) ifta (timer a interrupt request flag) iftc (timer c interrupt request flag) dton (dton flag) gef (gear enable flag) imtd * 4 (timer d interrupt mask) ims (serial interrupt mask) $020 $021 $022 $023 adsf * 3 (a/d start flag) not used iftd * 4 (timer d interrupt request flag) ifs (serial interrupt request flag) wdon (watchdog on flag) icef (input capture error flag) not used not used lson (low speed on flag) icsf (input capture status flag) not used not used if im ie sp : interrupt request flag : interrupt mask : interrupt enable flag : stack pointer figure 3 interrupt control bit and register flag area configuration
hd404889/hd404899/hd404878/hd404868 series 30 ie im lson if icsf icef gef rsp wdon adsf * dton not used sem/semd allowed not executed not executed allowed allowed not executed in active mode used in subactive mode not executed allowed allowed allowed not executed inhibited allowed not executed allowed allowed allowed allowed inhibited inhibited inhibited allowed allowed inhibited rem/remd tm/tmd bits in the interrupt control bit area and register flag area can be set and reset by the sem or semd instruction and the rem or remd instruction, and tested by the tm or tmd instruction. they are not affected by any other instructions. the following restrictions apply to individual bits. the wdon bit is reset only by stop mode clearance by means of an mcu reset. do not use the rem or remd instruction on the adsf bit during a/d conversion. the dton bit is always in the reset state in active mode. if the tm or tmd instruction is used on a bit for which its use is prohibited, or on a nonexistent bit, the status flag value will be undetermined. * applies to hd404889, hd404899, and hd404868 series. notes : figure 4 instruction restrictions
hd404889/hd404899/hd404878/hd404868 series 31 ram address hd404889 series bit 3 bit 2 bit 1 bit 0 $000 $003 $004 $005 $006 $007 $008 $009 $00a $00b $00c $00d $00e $00f $010 $011 $012 $013 $014 $015 $016 $017 $018 $019 $01a $01b $01c $01f $020 $023 $024 $025 $026 $027 $028 $029 $02a $02b $02c $02d $02e $02f $030 $031 $032 $033 $034 $035 $036 $037 $038 $039 $03a $03b $03c $03d $03e $03f ssr mis esr pmr0 pmr1 pmr2 pmr3 pmr4 msr1 msr2 tma tmb1 tmb2 trbl/twbl trbu/twbu tmc1 tmc2 trcl/twcl trcu/twcu tmd1 tmd2 trdl/twdl trdu/twdu smr1 smr2 srl sru amr adrl adru lcr lmr bmr dcd0 dcd1 dcd2 dcr0 dcr1 dcr2 dcr3 dcr4 dcr5 dcr6 dcr7 dcr8 v interrupt control bit area 32 khz oscillation stop setting 32 khz frequency division ratio selection system clock selection system clock frequency division ratio switching pull-up mos control interrupt frame period selection int1 edge detection selection d 1 /int 1 d 0 / int 0 r0 3 / wu 3 r1 3 /tob r0 2 / wu 2 r1 2 /buzz r0 1 / wu 1 r1 1 /evnd r0 0 / wu 0 r1 0 /evnb r2 2 /si/so r2 1 / sck r2 0 /toc r6/seg13~16 r5/seg9~12 r4/seg5~8 r3/seg1~4 timer d clock on/off timer c clock on/off timer b lock on/off a/d clock on/off serial clock on/off timer a clock source selection timer b clock source selection timer c clock source selection reload on/off reload on/off timer b output mode setting timer c output mode selection evnb edge detection selection evnd edge detection selection timer b register (lower) timer b register (upper) timer c register (lower) timer c register (upper) timer d register (lower) timer d register (upper) serial data register (lower) serial data register (upper) a/d data register (lower) a/d data register (upper) timer d clock source selection reload on/off input capture selection register flag area serial transfer clock speed selection r2 2 /si/so pmos control so idle h/l setting analog channel selection a/d conversion time power supply dividing resistor switch realtime clock mode display selection on-chip power supply switch display on/off input clock selection duty selection clock output on/off buzzer/clock selection buzzer/clock source selection portd 3 dcr portd 2 dcr portd 1 dcr portd 0 dcr portr0 3 dcr portr0 2 dcr portr0 1 dcr portr0 0 dcr portr1 3 dcr portr1 2 dcr portr1 1 dcr portr1 0 dcr portr2 3 dcr portr2 2 dcr portr2 1 dcr portr2 0 dcr portr3 3 dcr portr3 2 dcr portr3 1 dcr portr3 0 dcr portr4 3 dcr portr4 2 dcr portr4 1 dcr portr4 0 dcr portr5 3 dcr portr5 2 dcr portr5 1 dcr portr5 0 dcr portr6 3 dcr portr6 2 dcr portr6 1 dcr portr6 0 dcr portr7 3 dcr portr7 2 dcr portr7 1 dcr portr7 0 dcr portr8 1 dcr portr8 0 dcr portd 7 dcr portd 6 dcr pord 5 dcr portd 4 dcr portd 11 dcr portd 10 dcr portd 9 dcr portd 8 dcr bank setting not used not used not used not used not used not used not used not used not used not used not used not used not used not used not used not used not used timera/timer base not used not used not used figure 5 special function register area
hd404889/hd404899/hd404878/hd404868 series 32 ram address hd404899 series bit 3 bit 2 bit 1 bit 0 $000 $003 $004 $005 $006 $007 $008 $009 $00a $00b $00c $00d $00e $00f $010 $011 $012 $013 $014 $015 $016 $017 $018 $019 $01a $01b $01c $01f $020 $023 $024 $025 $026 $027 $028 $029 $02a $02b $02c $02d $02e $02f $030 $031 $032 $033 $034 $035 $036 $037 $038 $039 $03a $03b $03c $03d $03e $03f ssr mis esr pmr0 pmr1 pmr2 pmr3 pmr4 msr1 msr2 tma tmb1 tmb2 trbl/twbl trbu/twbu tmc1 tmc2 trcl/twcl trcu/twcu tmd1 tmd2 trdl/twdl trdu/twdu smr1 smr2 srl sru amr adrl adrm adru lcr lmr bmr dcd0 dcd1 dcd2 dcr0 dcr1 dcr2 dcr3 dcr4 dcr5 dcr6 dcr7 dcr8 v interrupt control bit area 32 khz oscillation stop setting 32 khz frequency division ratio selection system clock selection system clock frequency division ratio switching pull-up mos control interrupt frame period selection int1 edge detection selection d 1 /int 1 d 0 / int 0 r0 3 / wu 3 r1 3 /tob r0 2 / wu 2 r1 2 /buzz r0 1 / wu 1 r1 1 /evnd r0 0 / wu 0 r1 0 /evnb r2 2 /si/so r2 1 / sck r2 0 /toc r6/seg13~16 r5/seg9~12 r4/seg5~8 r3/seg1~4 timer d clock on/off timer c clock on/off timer b lock on/off a/d clock on/off serial clock on/off timer a clock source selection timer b clock source selection timer c clock source selection reload on/off reload on/off timer b output mode setting timer c output mode selection evnb edge detection selection evnd edge detection selection timer b register (lower) timer b register (upper) timer c register (lower) timer c register (upper) timer d register (lower) timer d register (upper) serial data register (lower) serial data register (upper) a/d data register (middle) a/d data register (upper) timer d clock source selection reload on/off input capture selection register flag area serial transfer clock speed selection r2 2 /si/so pmos control so idle h/l setting analog channel selection a/d conversion time power supply dividing resistor switch realtime clock mode display selection on-chip power supply switch display on/off input clock selection duty selection clock output on/off buzzer/clock selection buzzer/clock source selection portd 3 dcr portd 2 dcr portd 1 dcr portd 0 dcr portr0 3 dcr portr0 2 dcr portr0 1 dcr portr0 0 dcr portr1 3 dcr portr1 2 dcr portr1 1 dcr portr1 0 dcr portr2 3 dcr portr2 2 dcr portr2 1 dcr portr2 0 dcr portr3 3 dcr portr3 2 dcr portr3 1 dcr portr3 0 dcr portr4 3 dcr portr4 2 dcr portr4 1 dcr portr4 0 dcr portr5 3 dcr portr5 2 dcr portr5 1 dcr portr5 0 dcr portr6 3 dcr portr6 2 dcr portr6 1 dcr portr6 0 dcr portr7 3 dcr portr7 2 dcr portr7 1 dcr portr7 0 dcr portr8 1 dcr portr8 0 dcr portd 7 dcr portd 6 dcr pord 5 dcr portd 4 dcr portd 11 dcr portd 10 dcr portd 9 dcr portd 8 dcr bank setting not used not used not used not used a/d data register (lower) not used not used not used not used not used not used not used not used not used not used not used not used not used timera/timer base not used not used not used figure 5 special function register area (cont)
hd404889/hd404899/hd404878/hd404868 series 33 ram address hd404878 series bit 3 bit 2 bit 1 bit 0 $000 $003 $004 $005 $006 $007 $008 $009 $00a $00b $00c $00d $00e $00f $010 $011 $012 $013 $014 $015 $016 $017 $018 $019 $01a $01b $01c $01f $020 $023 $024 $025 $026 $027 $028 $029 $02a $02b $02c $02d $02e $02f $030 $031 $032 $033 $034 $035 $036 $037 $038 $039 $03a $03b $03c $03d $03e $03f ssr mis esr pmr0 pmr1 pmr2 pmr3 pmr4 msr1 msr2 tma tmb1 tmb2 trbl/twbl trbu/twbu tmc1 tmc2 trcl/twcl trcu/twcu tmd1 tmd2 trdl/twdl trdu/twdu smr1 smr2 srl sru lcr lmr bmr dcd0 dcd1 dcd2 dcr0 dcr1 dcr2 dcr3 dcr4 dcr5 dcr6 dcr7 dcr8 interrupt control bit area 32 khz oscillation stop setting 32 khz frequency division ratio selection system clock selection system clock frequency division ratio switching pull-up mos control interrupt frame period selection int1 edge detection selection d 1 /int 1 d 0 / int 0 r0 3 / wu 3 r1 3 /tob r0 2 / wu 2 r1 2 /buzz r0 1 / wu 1 r1 1 /evnd r0 0 / wu 0 r1 0 /evnb r2 2 /si/so r2 1 / sck r2 0 /toc r6/seg13~16 r5/seg9~12 r4/seg5~8 r3/seg1~4 timer d clock on/off timer c clock on/off timer b lock on/off serial clock on/off timer a clock source selection timer b clock source selection timer c clock source selection reload on/off reload on/off timer b output mode setting timer c output mode selection evnb edge detection selection evnd edge detection selection timer b register (lower) timer b register (upper) timer c register (lower) timer c register (upper) timer d register (lower) timer d register (upper) serial data register (lower) serial data register (upper) timer d clock source selection reload on/off input capture selection register flag area serial transfer clock speed selection r2 2 /si/so pmos control so idle h/l setting power supply dividing resistor switch realtime clock mode display selection on-chip power supply switch display on/off input clock selection duty selection clock output on/off buzzer/clock selection buzzer/clock source selection portd 3 dcr portd 2 dcr portd 1 dcr portd 0 dcr portr0 3 dcr portr0 2 dcr portr0 1 dcr portr0 0 dcr portr1 3 dcr portr1 2 dcr portr1 1 dcr portr1 0 dcr portr2 3 dcr portr2 2 dcr portr2 1 dcr portr2 0 dcr portr3 3 dcr portr3 2 dcr portr3 1 dcr portr3 0 dcr portr4 3 dcr portr4 2 dcr portr4 1 dcr portr4 0 dcr portr5 3 dcr portr5 2 dcr portr5 1 dcr portr5 0 dcr portr6 3 dcr portr6 2 dcr portr6 1 dcr portr6 0 dcr portr7 3 dcr portr7 2 dcr portr7 1 dcr portr7 0 dcr portr8 1 dcr portr8 0 dcr portd 7 dcr portd 6 dcr pord 5 dcr portd 4 dcr portd 11 dcr portd 10 dcr portd 9 dcr portd 8 dcr not used not used not used not used not used not used not used not used not used not used not used not used not used not used not used not used not used timera/timer base not used not used not used figure 5 special function register area (cont)
hd404889/hd404899/hd404878/hd404868 series 34 ram address hd404868 series bit 3 bit 2 bit 1 bit 0 $000 $003 $004 $005 $006 $007 $008 $009 $00a $00b $00c $00d $00e $00f $010 $011 $012 $013 $014 $015 $016 $017 $018 $019 $01a $01b $01c $01f $020 $023 $024 $025 $026 $027 $028 $029 $02a $02b $02c $02d $02e $02f $030 $031 $032 $033 $034 $035 $036 $037 $038 $039 $03a $03b $03c $03d $03e $03f ssr mis esr pmr0 pmr1 pmr2 pmr3 pmr4 msr1 msr2 tma tmb1 tmb2 trbl/twbl trbu/twbu tmc1 tmc2 trcl/twcl trcu/twcu smr1 smr2 srl sru amr adrl adrm adru lcr lmr bmr dcd0 dcd1 dcd2 dcr0 dcr1 dcr2 dcr3 dcr4 dcr5 dcr6 dcr7 interrupt control bit area 32 khz oscillation stop setting 32 khz frequency division ratio selection system clock selection system clock frequency division ratio switching pull-up mos control interrupt frame period selection int1 edge detection selection d 1 /int 1 d 0 / int 0 not used r1 3 /tob r0 2 / wu 2 r1 2 /buzz r0 1 / wu 1 not used r0 0 / wu 0 r1 0 /evnb r2 2 /si/so r2 1 / sck r2 0 /toc r6/seg13~16 r5/seg9~12 r4/seg5~8 r3/seg1~4 timer c clock on/off timer b lock on/off a/d clock on/off serial clock on/off timer a clock source selection timer b clock source selection timer c clock source selection reload on/off reload on/off timer c output mode selection evnb edge detection selection timer b register (lower) timer b register (upper) timer c register (lower) timer c register (upper) not used not used serial data register (lower) serial data register (upper) a/d data register (middle) a/d data register (upper) not used register flag area serial transfer clock speed selection r2 2 /si/so pmos control so idle h/l setting analog channel selection a/d conversion time power supply dividing resistor switch realtime clock mode display selection on-chip power supply switch display on/off input clock selection duty selection clock output on/off buzzer/clock selection buzzer/clock source selection portd 3 dcr portd 2 dcr portd 1 dcr portd 0 dcr not used portr0 2 dcr portr0 1 dcr portr0 0 dcr portr1 3 dcr portr1 2 dcr portr1 1 dcr portr1 0 dcr portr2 3 dcr portr2 2 dcr portr2 1 dcr portr2 0 dcr portr3 3 dcr portr3 2 dcr portr3 1 dcr portr3 0 dcr portr4 3 dcr portr4 2 dcr portr4 1 dcr portr4 0 dcr portr5 3 dcr portr5 2 dcr portr5 1 dcr portr5 0 dcr portr6 3 dcr portr6 2 dcr portr6 1 dcr portr6 0 dcr portr7 3 dcr portr7 2 dcr portr7 1 dcr portr7 0 dcr portd 7 dcr portd 6 dcr pord 5 dcr portd 4 dcr not used portd 9 dcr portd 8 dcr not used not used not used not used a/d data register (lower) not used not used not used not used not used not used not used not used timer b output mode selection not used not used not used not used not used timera/timer base not used not used not used figure 5 special function register area (cont)
hd404889/hd404899/hd404878/hd404868 series 35 mr (0) mr (1) mr (2) mr (3) mr (4) mr (5) mr (6) mr (7) mr (8) mr (9) mr (10) mr (11) mr (12) mr (13) mr (14) mr (15) $040 $041 $042 $043 $044 $045 $046 $047 $048 $049 $04a $04b $04c $04d $04e $04f level level level level level level level level level level level level level level level level st pc 10 ca pc 3 pc 13 pc 9 pc 6 pc 2 pc 12 pc 8 pc 5 pc 1 pc 11 pc 7 pc 4 pc 0 $3fc $3fd $3fe $3ff 1020 1021 1022 1023 bit 3 bit 2 bit 1 bit 0 $3ff 1,023 960 $3c0 (a) memory registers (b) stack area 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 pc 13 to pc 0 : program counter st : status flag ca : carry flag figure 6 configuration of memory registers and stack area, and stack position bit read/write initial value on reset bit name 3 not used 2 not used 1 not used 0 r/w 0 v0 v0 0 1 bank 0 is selected bank 1 is selected bank area selection bank register (v: $03f) note: after reset, the value in the bank register is 0, and therefore bank 0 is selected. applies to hd404889 and hd404899 series. figure 7 bank register (v)
hd404889/hd404899/hd404878/hd404868 series 36 functional description registers and flags the mcu has nine registers and two flags for cpu operations. they are shown in figure 8 and described below. accumulator b register w register x register y register spx register spy register carry flag status flag initial value: undefined, r/w initial value: undefined, r/w initial value: undefined, r/w initial value: undefined, r/w initial value: undefined, r/w initial value: undefined, r/w initial value: undefined, r/w initial value: undefined, r/w initial value: 1, no r/w program counter initial value: $0000, no r/w stack pointer initial value: $3ff, no r/w 30 (a) 30 (b) 10 (w) 30 (x) 30 (y) 30 (spx) 30 (spy) 0 (ca) 0 (st) 13 0 (pc) 50 (sp) 9 1111 figure 8 registers and flags accumulator (a) and b register (b): the accumulator and b register are 4-bit registers used to hold the result of an alu operation, and for data transfer to or from memory, an i/o area, or another register.
hd404889/hd404899/hd404878/hd404868 series 37 w register (w), x register (x) and y register (y): the w register is a 2-bit register, and the x and y registers are 4-bit registers, used for ram register indirect addressing. the y register is also used for d port addressing. spx register (spx) and spy register (spy): the spx and spy registers are 4-bit registers used as x register and y register auxiliary registers, respectively. carry flag (ca): this flag holds alu overflow when an arithmetic/logic instruction is executed. it is also affected by the sec, rec, rotl, and rotr instructions. the contents of the carry flag are saved to the stack when interrupt handling is performed, and are restored from the stack by the rtni instruction (but are not affected by the rtn instruction). status flag (st): this flag holds alu overflow when an arithmetic/logic or compare instruction is executed, and the result of an alu non-zero or bit test instruction. it is used as the branch condition for the br, brl, cal, and call instructions. the status flag is a latch-type flag, and does not change until the next arithmetic/logic, compare, or bit test instruction is executed. after a br, brl, cal, or call instruction, the status flag is set to 1 regardless of whether the instruction is executed or skipped. the contents of the status flag are saved to the stack when interrupt handling is performed, and are restored from the stack by the rtni instruction (but are not affected by the rtn instruction). program counter (pc): this is a 14-bit binary counter that holds rom address information. stack pointer (sp): the stack pointer is a 10-bit register that holds the address of the next save space in the stack area. the stack pointer is initialized to $3ff by an mcu reset. the stack pointer is decremented by 4 each time data is saved, and incremented by 4 each time data is restored. the upper 4 bits of the stack pointer are fixed at 1111, so that a maximum of 16 stack levels can be used. there are two ways in which the stack pointer is initialized to $3ff: by an mcu reset as mentioned above, or by resetting the rsp bit with the rem or remd instruction. reset an mcu reset is performed by driving the reset pin low. at power-on, and when subactive mode, watch mode, or stop mode is cleared, reset should be input for at least trc to provide the oscillation settling time for the oscillator.in other cases, the mcu is reset by inputting reset for at least two instruction cycles. table 1 shows the areas initialized by an mcu reset, and their initial values.
hd404889/hd404899/hd404878/hd404868 series 38 table 1 (1) initial values after mcu reset item abbr. initial value contents program counter (pc) $0000 program executed from rom start address status flag (st) 1 branching by conditional branch instruction enabled stack pointer (sp) $3ff stack level is 0 interrupt interrupt enable flag (ie) 0 all interrupts disabled flags/ mask interrupt request flag (if) 0 no interrupt requests interrupt mask (im) 1 interrupt requests masked i/o port data register (pdr) all bits 1 "1" level output possible data control registers (dcd0 to 2) all bits 0 output buffer off (high impedance) data control registers (dcr0 to 7, dcr80, dcr81) all bits 0 port mode register 0 (pmr0) --00 see port mode register 0 section port mode register 1 (pmr1) 0000 see port mode register 1 section port mode register 2 (pmr2) 0000 see port mode register 2 section port mode register 3 (pmr3) 0000 see port mode register 3 section port mode register 4 (pmr4) 0000 see port mode register 4 section edge detection select register (esr) --00 see edge detection select register section timers timer mode register a (tma) 0000 see timer mode register a section timer mode register b1 (tmb1) 0000 see timer mode register b1 section timer mode register b2 (tmb2) -000 see timer mode register b2 section timer mode register c1 (tmc1) 0000 see timer mode register c1 section timer mode register c2 (tmc2) -0-- see timer mode register c2 section timer mode register d1 (tmd1) 0000 see timer mode register d1 section timer mode register d2 (tmd2) -000 see timer mode register d2 section prescaler s (pss) $000 prescaler w (psw) $00 timer/counter a (tca) $00 timer/counter b (tcb) $00 timer/counter c (tcc) $00 timer/counter d (tcd) $00 timer write register b (twbu,l) $x0 timer write register c (twcu,l) $x0 timer write register d (twdu,l) $x0
hd404889/hd404899/hd404878/hd404868 series 39 table 1 (1) (cont) initial values after mcu reset item abbr. initial value contents serial serial mode register 1 (smr1) 0000 see serial mode register 1 section interface serial mode register 2 (smr2) -0x- see serial mode register 2 section serial data register (sru,l) $xx octal counter 000 a/d a/d mode register (amr) 0000 see a/d mode register section converter a/d data register (hd404889 series) (adru,l) $7f see a/d data register section a/d data register (hd404899 series) (adru,m,l) $1ff see a/d data register section lcd lcd control register (lcr) 0000 see lcd control register section lcd mode register (lmr) 0000 see lcd duty/clock control register section bit low speed on flag (lson) 0 see low-power mode section registers watchdog timer on flag (wdon) 0 see timer c section a/d start flag (adsf) 0 see a/d converter section direct transfer on flag (dton) 0 see low-power mode section input capture status flag (icsf) 0 see timer d section input capture error flag (icef) 0 see timer d section gear enable flag (gef) 0 see system clock gear function others miscellaneous register (mis) 0-00 see low-power mode and input/output sections system clock select register (ssr) 0000 see low-power mode and oscillator circuit sections module standby register 1 (msr1) -000 see timer section module standby register 2 (msr2) --00 see serial interface and a/d converter sections buzzer mode register (bmr) 0000 see buzzer mode register section notes: 1. the state of registers and flags other than those listed above after an mcu reset is shown in table 1 (2). 2. x: indicates invalid value, - indicates that the bit does not exist.
hd404889/hd404899/hd404878/hd404868 series 40 table 1 (2) initial values after mcu reset item abbr. after stop mode clearance by wu 0 to wu 3 input after other mcu reset carry flag (ca) retain value immediately prior to value immediately prior to mcu reset is not accumulator (a) entering stop mode guaranteed. must be initialized by program. b register (b) w register (w) x/spx register (x/spx) y/spy register (y/spy) ram interrupts there are a total of nine interrupt sources, comprising wakeup input ( wu 0 to wu 3 ), external interrupts ( int 0 , int 1 ), timer/counter (timer a, timer b, timer c, timer d) interrupts, a serial interface interrupt, and an a/d converter interrupt. each interrupt source is provided with an interrupt request flag, interrupt mask, and vector address, used for storing and controlling interrupt requests. in addition, an interrupt enable flag is provided to control interrupts as a whole. of the interrupt sources, timers b and d share the same vector address, and the a/d converter and serial interface also share the same vector address. software must therefore determine which of the interrupt sources is requesting an interrupt at the start of interrupt handling. interrupt control bits and interrupt handling: the interrupt control bits are mapped onto ram addresses $000 to $003 and $022 to $023, and can be accessed by ram bit manipulation instructions. however, the interrupt request flags (if) cannot be set by software. when the mcu is reset, the interrupt enable flag (ie) and interrupt request flags (if) are initialized to 0, and the interrupt masks (im) are initialized to 1. figure 9 shows a block diagram of the interrupt control circuit, table 2 shows interrupt priorities and vector addresses, and table 3 lists the conditions for executing interrupt handling for each of the nine kinds of interrupt source. when the interrupt request flag is set to 1 and the interrupt mask is cleared to 0, an interrupt is requested. if the interrupt enable flag is set to 1 at this time, interrupt handling is started. the vector address corresponding to the interrupt source is generated by the priority control circuit. the interrupt handling sequence is shown in figure 10, and the interrupt handling flowchart in figure 11. when an interrupt is accepted, execution of the previous instruction is completed in the first cycle. in the second cycle, the interrupt enable flag (ie) is reset. in the second and third cycles, the contents of the carry flag, status flag, and program counter are saved on the stack. in the third cycle, a jump is made to the vector address and instruction execution is resumed from that address.
hd404889/hd404899/hd404878/hd404868 series 41 in each vector address area, a jmpl instruction should be written that branches to the start address of the interrupt routine. in the interrupt routine, the interrupt request flag that caused interrupt handling must be reset by software. table 2 vector addresses and interrupt priorities interrupt source priority vector address reset $0000 wu 0 to wu 3 1 $0002 int 0 2 $0004 int 1 3 $0006 timer a 4 $0008 timer b, d 5 $000a timer c 6 $000c serial interface, a/d converter 7 $000e
hd404889/hd404899/hd404878/hd404868 series 42 $000,2 $000,3 ifwu imwu $001,0 $001,1 if0 im0 $001,2 $001,3 if1 im1 $002,0 $002,1 ifta imta $002,2 $002,3 iftb imtb $003,0 $003,1 iftc imtc $003,2 $003,3 ifad imad $000,0 i/e $023,2 $023,3 ifs ims $022,2 $022,3 iftd imtd ( wu 0 to wu 3 interrupt) ( int 0 interrupt) (int 1 interrupt) (timer a interrupt) (timer b interrupt) (timer c interrupt) (a/d interrupt) priority control circuit interrupt request vector address (timer d interrupt) (serial interrupt) figure 9 block diagram of interrupt control circuit
hd404889/hd404899/hd404878/hd404868 series 43 table 3 interrupt processing and activation conditions interrupt source interrupt control bit wu 0 to wu 3 int 0 int 1 timer a timer b or timer d timer c a/d or serial ie 11111 11 ifwu imwu 10000 00 if0 im0 * 1000 00 if1 im1 * * 1 00 00 ifta imta ***1000 iftb imtb +iftd imtd ****100 iftc imtc ***** 10 ifad imad +ifs ims ***** *1 note: * operation is not affected whether the value is 0 or 1. 1 2 3 4 5 6 instruction execution* interrupt acceptance save to stack ie reset execution of jmpl instruction at vector address save to stack vector address generated execution of instruction at start address of interrupt routine instruction cycle note: the stack is accessed and the ie reset after the instruction is executed, even if it is a 2c y cle instruction. figure 10 interrupt sequence
hd404889/hd404899/hd404878/hd404868 series 44 power on reset ="0"? yes no yes yes no no no no no no no yes yes yes yes yes yes reset mcu interrupt request? execute instruction pc ? (pc)+1 pc ? $0002 pc ? $0004 pc ? $0006 pc ? $0008 pc ? $000a pc ? $000c pc ? $000e ie="1"? accept interrupt ie ? "0" stack ? (pc) stack ? (ca) stack ? (st) wu 0 ~ wu 3 interrupt? int 0 interrupt? int 1 interrupt? timer a interrupt? timer b, timer d interrupt? timer c interrupt? ( a/d, serial interrupt ) figure 11 interrupt handling flowchart
hd404889/hd404899/hd404878/hd404868 series 45 interrupt enable flag (ie: $000,0): the interrupt enable flag controls interrupt enabling/disabling of all interrupt requests as shown in table 4. the interrupt enable flag is reset by interrupt handling and set by the rtni instruction. table 4 interrupt enable flag (ie: $000,0) interrupt enable flag(ie) interrupt enabling/disabling 0 interrupts disabled 1 interrupts enabled wakeup interrupt request flag (ifwu: $000,2): the wakeup interrupt request flag (ifwu) is set by the detection of a falling edge in wu 0 to wu 3 input in active mode, subactive mode,watch mode, or standby mode. in stop mode, when a falling edge is detected at the wakeup pin, the mcu waits for the oscillation settling time, then switches to active mode. the wakeup interrupt request flag (ifwu) is not set in this case. wakeup interrupt mask (imwu: $000,3): this bit masks an interrupt request by the wakeup interrupt request flag. bit read/write initial value on reset bit name 3 2 1 w 0 esr1 0 w 0 esr0 esr1 esr0 0 1 0 1 not detected falling edge detection rising edge detection both rising and falling edge detection int 1 edge detect edge detection select register (esr: $006) 0 1 figure 12 edge detection select register (esr)
hd404889/hd404899/hd404878/hd404868 series 46 external interrupt request flags (if0, if1: $001): if0 is set by a falling edge in the int 0 input, and if1 is set by a rising edge, falling edge, or both edges in the int 1 input (table 5). interrupt edge selection is performed by means of the edge detection select register (esr: $006) (figure 12). table 5 external interrupt request flags (if0, if1: $001) external interrupt request flags (if0, if1) interrupt request 0 no external interrupt request 1 external interrupt request generated external interrupt masks (im0, im1: $001): these bits mask interrupt requests by the external interrupt request flags (table 6). table 6 external interrupt mask (im: $001) external interrupt masks (im0, im1) interrupt request 0 external interrupt request enabled 1 external interrupt request masked (held pending) timer a interrupt request flag (ifta: $002,0): the timer a interrupt request flag is set by timer a overflow output (table 7). table 7 timer a interrupt request flag (ifta: $002,0) timer a interrupt request flag(ifta) interrupt request 0 no timer a interrupt request 1 timer a interrupt request generated timer a interrupt mask (imta: $002,1): this bit masks an interrupt request by the timer a interrupt request flag (table 8). table 8 timer a interrupt mask (imta: $002,1) timer a interrupt mask (imta) interrupt request 0 timer a interrupt request enabled 1 timer a interrupt request masked (held pending)
hd404889/hd404899/hd404878/hd404868 series 47 timer b interrupt request flag (iftb: $002,2): the timer b interrupt request flag is set by timer b overflow output (table 9). table 9 timer b interrupt request flag (iftb: $002,2) timer b interrupt request flag (iftb) interrupt request 0 no timer b interrupt request 1 timer b interrupt request generated timer b interrupt mask (imtb: $002,3): this bit masks an interrupt request by the timer b interrupt request flag (table 10). table 10 timer b interrupt mask (imtb: $002,3) timer b interrupt mask (imtb) interrupt request 0 timer b interrupt request enabled 1 timer b interrupt request masked (held pending) timer c interrupt request flag (iftc: $003,0): the timer c interrupt request flag is set by timer c overflow output (table 11). table 11 timer c interrupt request flag (iftc: $003,0) timer c interrupt request flag (iftc) interrupt request 0 no timer c interrupt request 1 timer c interrupt request generated (held pending) timer c interrupt mask (imtc: $003,1): this bit masks an interrupt request by the timer c interrupt request flag (table 12). table 12 timer c interrupt mask (imtc: $003,1) timer c interrupt mask (imtc) interrupt request 0 timer c interrupt request enabled 1 timer c interrupt request masked (held pending)
hd404889/hd404899/hd404878/hd404868 series 48 timer d interrupt request flag (iftd: $022,2): (applies to hd404889, hd404899, and hd404878 series) the timer d interrupt request flag is set by timer d overflow output, or by an evnd input edge when used as an input capture timer (table 13). table 13 timer d interrupt request flag (iftd: $022,2) timer d interrupt request flag (iftd) interrupt request 0 no timer d interrupt request 1 timer d interrupt request generated timer d interrupt mask (imtd: $022,3): (applies to hd404889, hd404899, and hd404878 series) this bit masks an interrupt request by the timer d interrupt request flag (table 14). table 14 timer d interrupt mask (imtd: $022,3) timer d interrupt mask (imtd) interrupt request 0 timer d interrupt request enabled 1 timer d interrupt request masked (held pending) serial interrupt request flag (ifs: $023,2): the serial interrupt request flag is set on completion of serial data transfer, or if data transfer is halted midway (table 15). table 15 serial interrupt request flag (ifs: $023,2) serial interrupt request flag (ifs) interrupt request 0 no serial interrupt request 1 serial interrupt request generated serial interrupt mask (ims: $023,3): this bit masks an interrupt request by the serial interrupt request flag (table 16). table 16 serial interrupt mask (ims: $023,3) serial interrupt mask (ims) interrupt request 0 serial interrupt request enabled 1 serial interrupt request masked (held pending)
hd404889/hd404899/hd404878/hd404868 series 49 a/d interrupt request flag (ifad: $003,2): (applies to hd404889, hd404899, and hd404868 series) the a/d interrupt request flag is set on completion of a/d conversion (table 17). table 17 a/d interrupt request flag (ifad: $003,2) a/d interrupt request flag (ifad) interrupt request 0 no a/d interrupt request 1 a/d interrupt request generated a/d interrupt mask (imad: $003,3): (applies to hd404889, hd404899, and hd404868 series) this bit masks an interrupt request by the a/d interrupt request flag (table 18). table 18 a/d interrupt mask (imad: $003,3) serial interrupt mask (imad) interrupt request 0 a/d interrupt request enabled 1 a/d interrupt request masked (held pending)
hd404889/hd404899/hd404878/hd404868 series 50 operating modes the five operating modes shown in table 19 can be used for the mcu. the function of each mode is shown in table 20, and the state transition diagram among each mode in figure 13. table 19 operating modes and clock status mode name active standby stop watch subactive* 2 activation method reset cancellation, interrupt request, wu 0 to wu 3 input in stop mode stop/sby instruction in subactive mode (when direct transfer is selected) sby instruction stop instruction when tma3 = 0 stop instruction when tma3 = 1 int 0 /timer a or wu 0 to wu 3 interrupt request in watch mode status system oscillator op op stopped stopped stopped subsystem oscillator op op op * 1 op op cancellation method reset input, stop/sby instruction reset input, interrupt request reset input, wu 0 to wu 3 input reset input, int 0 /timer a or wu 0 to wu 3 interrupt request reset input, stop/sby instruction notes: op: implies in operation. 1. operating or stopping the oscillator can be selected by setting bit 3 of the system clock select register (ssr: $004) 2. subactive mode is an optional function; specify it on the fnction option list.
hd404889/hd404899/hd404878/hd404868 series 51 table 20 operation in low-power dissipation modes function stop mode watch mode standby mode subactive mode* 3 cpu retained retained retained op ram retained retained retained op timer a stopped op op op timer b stopped stopped op op timer c stopped stopped op op timer d * 4 stopped stopped op op serial interface stopped * 1 stopped * 1 op op a/d * 5 stopped stopped op stopped lcd stopped op * 2 op op i/o retained retained retained op notes: op: implies in operation. 1. transmission/reception is activated if a clock is input in external clock mode. however, interrupts stop. 2. when a 32 khz clock source is used. 3. subactive mode is an optional function specified on the function option list. 4. applies to hd404889, hd404899, and hd404878 series. 5. applies to hd404889, hd404899, and hd404868 series.
hd404889/hd404899/hd404878/hd404868 series 52 reset by reset pin input or watchdog timer reset (tma3=0) (tma3=1) timer a, wu 0 to wu 3 or int 0 interrupt standby mode active mode sby instruction interrupt sby instruction interrupt stop instruction (tma3=1,lson=0) (tma3=1,lson=1) f osc : fx : fcyc : fw : f sub : cpu : clk : per : lson : dton : tma3 : main oscillator frequency sub-oscillator frequency (for realtime clock) f osc /32 or fosc/4 (selected by software) fx/8 fx/8 or fx/4 (selected by software) system clock clock for realtime clock peripheral function clock low speed on flag direct transfer on flag timer mode register a bit3 timer a, wu 0 ~ wu 3 or int 0 interrupt wu 0 to wu 3 stop instruction wu 0 to wu 3 stop instruction stop instruction stop mode (tma3=0,ssr3=0,lson=0) (tma3=0,ssr3=1,lson=0) subactive mode *4 *2 *3 *1 dton 1 0 don? care 0 transition condition stop/sby instruction stop/sby instruction stop/sby instruction stop/sby instruction lson 0 0 1 0 *1 *2 *3 *4 tma3 1 1 1 0 watch mode f osc fx cpu clk per : stop : stop : stop : stop : stop f osc fx cpu clk per : active : active : fcyc : fcyc : fcyc f osc fx cpu clk per : stop : active : stop : stop : stop f osc fx cpu clk per : active : active : stop : fcyc : fcyc f osc fx cpu clk per : stop : active : f sub : fw : f sub f osc fx cpu clk per : active : active : fcyc : fw : fcyc f osc fx cpu clk per : active : active : stop : fw : fcyc f osc fx cpu clk per : stop : active : stop : fw : stop f osc fx cpu clk per : stop : active : stop : fw : stop figure 13 mcu status transitions
hd404889/hd404899/hd404878/hd404868 series 53 active mode: in active mode all functions operate. in this mode, the mcu operates on clocks generated by the osc 1 and osc 2 oscillator circuits. standby mode: in standby mode the oscillators continue to operate but clocks relating to instruction execution halt. as a result, cpu operation stops, and registers, ram, and the d port/r port set for output retain their state immediately prior to entering standby mode. interrupts, timers, the serial interface, and other peripheral functions continue to operate. power consumption is lower than in active mode due to the halting of the cpu. the mcu is switched to standby mode by executing the sby instruction in active mode. standby mode is cleared by reset input or an interrupt request. when standby mode is cleared by reset input, an mcu reset is performed. when standby mode is cleared by an interrupt request, the mcu enters active mode and executes a instruction following the sby instruction. after executing the instruction, if the interrupt enable flag is set to 1, interrupt handling is executed; if the interrupt enable flag is cleared to 0, the interrupt request is held pending and normal instruction execution is continued. mcu operation flowchart is shown in figure 14.
hd404889/hd404899/hd404878/hd404868 series 54 stop mode system clock oscillator started system reset next instruction execution system clock oscillator started interrupts enabled ifwu imwu =1? if0 im0 = 1? if1 im1 = 1? ifta ? imta = 1? iftb ? imtb + iftd imtd = 1? iftc? imtc = 1? ifad imad + ifs ims = 1? if = 1, im = 0, ie = 1? no no yes yes yes yes* no no no no no no yes only when clearing from standby mode note: standby mode watch mode reset =0? yes* yes* yes* yes no no yes yes no reset =0? nop system clock oscillator started next instruction execution wu 0 to wu 3 = ? figure 14 mcu operation flowchart
hd404889/hd404899/hd404878/hd404868 series 55 stop mode: in stop mode, all mcu function stop except that states prior to entry into stop mode are retained. this mode thus has the lowest power consumption of all operating mode. in stop mode, the osc 1 and osc 2 oscillators stop. bit 3 (ssr3) of the system clock select register (ssr: $004) (figure 24) can be used to select the active (= 0) or stopped (= 1) state for the x1 and x2 oscillators. the mcu is switched to stop mode by executing a stop instruction while bit 3 (tma3) of timer mode register a (tma: $00f) is cleared to 0 in active mode. stop mode is cleared by reset or wu 0 to wu 3 input. when stop mode is cleared by reset , the reset signal should be input for at least the oscillation settling time (trc) (see "ac characteristics") shown in figure 15. then, the mcu is initialized and starts instruction execution from the start (address 0) of the program. when the mcu detects a falling edge at wu 0 to wu 3 in stop mode, it automatically waits for the oscillation settling time, then switches to active mode. after the transition to active mode, the mcu resumes program execution from the instruction following the stop instruction. if stop mode is cleared by wakeup input, ram data and registers retain their values prior to entering stop mode. stop mode oscillator internal clock reset stop instruction executed t res (at least oscillation settling time (t rc )) figure 15 timing chart for clearing stop mode by reset input note: if stop mode is cleared by wakeup input when an external clock is used as the system clock (osc1), the subclock should not be stopped in stop mode. watch mode: in watch mode, the realtime clock function (timer a) and lcd function using the x1 and x2 oscillators operate, but other functions stop. this mode thus has the second lowest power consumption after stop mode, and is useful for performing realtime clock display only. in watch mode, the osc 1 and osc 2 oscillators stop but the x1 and x2 oscillators continue to operate. the mcu is switched to watch mode by executing a stop instruction while tma3 = 1 in active mode, or by executing a stop/sby instruction in subactive mode.
hd404889/hd404899/hd404878/hd404868 series 56 watch mode is cleared by reset input or an int 0 ,timer a or wu 0 to wu 3 interrupt request. for reset input, refer to the section on stop mode. when watch mode is cleared by an int 0 ,timer a or wu 0 to wu 3 interrupt request, the mode transition depends on the value of the lson bit: the mcu enters active mode if lson = 0, and enters subactive mode if lson = 1. in the case of a transition to active mode, interrupt request generation is delayed to secure the oscillation settling time: the delay is the trc set time for the timer a interrupt, and, for the int 0 interrupt or wu 0 to wu 3 interrupt, tx (t + t rc < tx < 2t + t rc ) if bit 1 and 0 (mis1, mis0) of the miscellaneous register are set to 00, or tx (t rc < tx < t + t rc ) if mis1 and mis0 are set to 01 or 10 (figures 16 and 17). other operations when the transition is made are the same as when watch mode is cleared (figure 14). subactive mode: in subactive mode, the osc 1 and osc 2 oscillator circuits stop and the mcu operates on clocks generated by the x1 and x2 oscillator circuits. in this mode, functions other than the a/d converter operate, but since the operating clocks are slow, power consumption is the lowest after watch mode. a cpu instruction processing speed of 244 m s or 122 m s can be selected according to whether bit 2 (ssr2) of the system clock select register (ssr: $004) is set to 1 or cleared to 0. the value of the ssr2 bit should be changed (0 1 or 1 0) only in active mode. if the value is changed in subactive mode, the mcu may operate incorrectly. subactive mode is cleared by executing a stop/sby instruction. a transition is then made to either watch mode or active mode according to the value of the low speed on flag (lson: $020,0) and the direct transfer on flag (dton: $020,3). subactive mode is a function option, and should be specified in the function option list. interrupt frame: in watch mode and subactive mode, clk is supplied to the timer a, wu 0 to wu 3 , and int 0 acceptance circuits. prescaler w and timer a operate as time bases, and generate interrupt frame timing. either of two values can be selected for the interrupt frame period, t, by means of the miscellaneous register (mis: $005) (figure 17). in watch mode and subactive mode, the timing for generation of timer a, int 0 and wu 0 to wu 3 interrupts is synchronized with the interrupt frame. except for the case of an active mode transition, the interrupt strobe timing is used for interrupt request generation. timer a generates overflow and interrupt requests at the interrupt strobe timing.
hd404889/hd404899/hd404878/hd404868 series 57 watch mode oscillation stabilization period active mode active mode interrupt strobe int 0 interrupt request generation t ttt rc t x t: interrupt frame period t rc : oscillation stabilization period only in case of transition to active mode note: if the time from the fall of the int 0 or wu 0 to wu 3 signal until the interrupt is accepted and active mode is entered and is designated t x , then t x will be in the following range : t+t rc t x 2t+t rc (mis1, mis0=00) t rc t x t+t rc (mis1, mis0=01 or 10) figure 16 interrupt frame miscellaneous register (mis: $005) bit read/write reset bit name 3 w 0 mis3 21 w 0 mis1 0 w 0 mis0 interrupt frame period t( ms )*1 oscillation settling time t rc ( ms )*1 mis1 mis0 0 1 0 1 0 1 0.24414 3.90625 3.90625 0.12207(0.24414)* 2 7.8125 31.25 oscillator circuit condition external clock input ceramic resonator crystal resonator not used notes: 1. t and t rc values are for use of a 32.768 khz crystal oscillator at the x1-x2 pins. 2. this value applies only in case of direct transition operation. buffer control see section 3, input/output, and figure 33 figure 17 miscellaneous register (mis)
hd404889/hd404899/hd404878/hd404868 series 58 direct transition from subactive to active mode: a direct transition can be made from subactive mode to active mode by controlling the direct transfer on flag (dton: $020,3) and low speed on flag (lson: $020,0). the procedure is shown below. (a) set lson = 0 and dton = 1 in subactive mode. (b) execute a stop or sby instruction. (c) after the lapse of the mcu internal processing time and the oscillation settling time, the mcu automatically switches from subactive mode to active mode (figure 18). notes: 1. the dton flag ($020,3) can be set in only subactive mode. it is always in the reset state in active mode. 2. the condition for transition time t d from the subactive mode to active mode is as follows: t rc < t d < t + t rc . subactive mode stop/sby instruction execution mcu internal processing time oscillation stabilization time active mode (set lson =0, dton =1) interrupt strobe direct transition completion timing t t d t rc t: interrupt frame period t rc : oscillation settling time t d : direct transition time figure 18 direct transition timing mcu operation sequence: the mcu operates in accordance with the flowchart shown in figure 19. reset input is asynchronous input, and the mcu immediately enters the reset state upon reset input, regardless of its current state. in the low-power mode operation sequence, if a stop/sby instruction is executed while the ie flag is cleared and the interrupt flag is set, releasing the relevant interrupt mask, the stop/sby instruction is canceled (regarded as nop) and the next instruction is executed. therefore, when executing a stop/sby instruction, all interrupt flags must be cleared, or interrupts masked, beforehand.
hd404889/hd404899/hd404878/hd404868 series 59 yes yes yes yes no no no no if=1 im=0 ie=0 if=1 im=0 stop/sby instruction standby/watch mode stop mode wu 0 ~ wu 3 = hardware nop execution hardware nop execution clearing standby watch mode pc ? (pc)+1 pc ? (pc)+1 mcu operation cycle note: see figure 14, mcu operation flowchart, for if and im operation. interrupt handling routine instruction execution instruction execution clearing stop mode nop pc ? (pc)+2 figure 19 mcu operating sequence (low-power mode operation)
hd404889/hd404899/hd404878/hd404868 series 60 usage notes: in watch mode and subactive mode, an interrupt will not be detected correctly if the int 0 or wu 0 to wu 3 high or low-level period is shorter than the interrupt frame period. the mcu? edge sensing method is shown in figure 20. the mcu samples the i nt 0 and wu 0 to wu 3 signals at regular intervals, and if consecutive sampled values change from high to low, it determines that a falling edge has been generated. interrupt detection errors occur since this sampling is performed at the interrupt frame period. if the high- level period of the int 0 or wu 0 to wu 3 signal is within an interrupt frame, as shown in figure 21 (a), the signal will be low at point a and point b, with the result that the falling edge will not be recognized. similarly, if the low-level period of the int 0 or wu 0 to wu 3 signal is within an interrupt frame, as shown in figure 21 (b), the signal will be high at point a and point b, with the result that the falling edge will not be recognized. in watch mode and subactive mode, therefore, ensure that the high-level and low-level periods of the int 0 and wu 0 to wu 3 signals is at least as long as the interrupt frame period. int 0 or wu 0 to wu 3 sampling high low low figure 20 edge sensing method int 0 or wu 0 to wu 3 interrupt frame point a: low point b: low int 0 or wu 0 to wu 3 interrupt frame point a: high point b: high (a) high-level mode (b) low-level mode figure 21 sampling examples
hd404889/hd404899/hd404878/hd404868 series 61 internal oscillator circuit figure 22 shows the clock pulse generator circuit. as shown in table 21, a ceramic oscillator or crystal oscillator can be connected to osc1 and osc2, and a 32.768 khz crystal oscillator can be connected to x1 and x2. external clock operation is possible for the system oscillator. set bit 1 (ssr1) of the system clock select register (ssr: $004) according to the frequency of the oscillator connected to osc1 and osc2 (figure 24). note: if the setting of bit 1 in the system clock select register does not match the frequency of the system oscillator, the subsystem using 32.768 khz oscillation will not operate correctly. osc 1 x1 lson system clock selection circuit osc 2 system oscillator 1/4 or 1/32 division circuit* timing generation circuit f osc f cyc t cyc x2 sub system clock oscillator 1/8 or 1/4 division circuit* timing generator circuit f x f sub t subcyc 1/8 division circuit timing generation circuit f w t wcyc cpu per cpu ?om ?am ?registers, flags ?/o peripheral functions interrupts tma3 bit timer a interrupts time base clock selection circuit clk notes: the division ratio can be selected by setting bit 0 or bit 2 in the system clock select register (ssr:$004). figure 22 clock pulse generator circuit
hd404889/hd404899/hd404878/hd404868 series 62 system clock gear function the mcu has a built-in system clock gear function that allows the system clock divided by 4 or by 32 to be selected by software for the instruction execution time. efficient power consumption can be achieved by operating at the divided-by-4 rate when high-speed processing is needed, and at the divided-by-32 rate at the other times. figure 23 shows the system clock conversion method. system clock conversion from division-by-4 to division-by-32 is performed as follows. first, make the division-by-32 setting (ssr0 write), then set the gear enable flag (gef: $021,3). this flag is used to distinguish between gear conversion and a transition to standby mode. next, execute an sby instruction. when the gear enable flag is not set, standby mode is entered; when this flag is set, gear conversion mode is entered. in this case a transition is made to standby mode for the duration of the gear conversion, but after the synchronization time has elapsed, a transition is made automatically to active mode. as soon as the transition is made to active mode, the gear enable flag is reset. the same procedure is used for conversion from division-by-32 to division-by-4. clear all interrupts, then disable interrupts, before carrying out gear conversion. incorrect operation may result if an interrupt is generated during gear conversion.
hd404889/hd404899/hd404878/hd404868 series 63 division-by-32 setting (ssr0 = 1) set gear enable flag execute sby instruction execute next instruction synchronization time division-by-4 setting (ssr0 = 0) set gear enable flag execute sby instruction execute next instruction synchronization time figure 23 system clock division ratio conversion flowchart
hd404889/hd404899/hd404878/hd404868 series 64 system clock select register (ssr: $004) note: * if the subsystem clock is not used, this bit must be set to 1 following power-on and reset. if it is set to 0 (the initial value), malfunctioning may occur in the stop mode. bit read/write initial value on reset bit name 3 w 0 ssr3 * 2 w 0 ssr2 1 w 0 ssr1 0 w 0 ssr0 system clock division ratio switch 0 1 division-by-4 (f cyc - f osc /4) division-by-32 (f cyc - f osc /32) system clock division ratio switch 0 1 f osc =0.4?.0mhz f osc =1.6?.5mhz subsystem clock division ratio switch 0 1 f sub =fx/8 f sub =fx/4 subsystem clock stop setting 0 1 subsystem clock operates in stop mode subsystem clock stops in stop mode figure 24 system clock select register
hd404889/hd404899/hd404878/hd404868 series 65 table 21 oscillator circuit examples circuit structure circuit constants external clock operation external oscillator osc 1 osc 2 open ceramic oscillator (osc 1 , osc 2 ) osc 1 osc 2 c 1 c 2 r f gnd ceramic oscillator ceramic oscillator: csa4.00mg (murata) r f =1m w 20% c 1 =c 2 =30pf 20% crystal oscillator (osc 1 , osc 2 ) osc 1 osc 2 c 1 c 2 r f gnd crystal oscillator osc 1 osc 2 lc s c 0 r s r f =1m w 20% c 1 =c 2 =10?2pf 20% crystal: equivalent circuit at left c 0 =7pfmax. r s =100 w max. crystal oscillator (x1, x2) x1 x2 c 1 c 2 gnd crystal oscillator x1 x2 lc s c 0 r s crystal: 32.768 khz: mx38t (nihon denpa kogyo) c 1 =c 2 =20pf 20% r s =14k w c 0 =1.5pf notes: 1. with a crystal or ceramic oscillator, circuit constants will differ depending on the resonator, stray capacitance in the interconnecting circuit, and other factors. suitable constants should be determined in consultation with the resonator manufacturer. 2. make the connections between the osc 1 and osc 2 pins (x1 and x2 pins) and external components as short as possible, and ensure that no other lines cross these lines (see layout example in figure 25). 3. when 32.768 khz crystal oscillation is not used, fix the x1 pin at v cc and leave the x2 pin open.
hd404889/hd404899/hd404878/hd404868 series 66 reset x1 x2 gnd osc 2 osc 1 test gnd figure 25 typical layouts of crystal and ceramic oscillator
hd404889/hd404899/hd404878/hd404868 series 67 input/output the mcu has 46 input/output pins (d 0 to d 11 , r0 to r7, r8 0 , and r8 1 ) in the hd404889, hd404899, and hd404878 series, or 41 input/output pins (d 0 to d 9 , r0 0 , r0 1 , r0 2 , and r1 to r7) in the hd404868 series. the features of these pins are described below. ? the four pins d 0 to d 3 are source large-current (10 ma max.) i/o pins. ? the eight pins d 4 to d 11 are sink large-current (15 ma max.) i/o pins. ? i/o pins comprise pins (d 0 , d 1 , r 0 , r 1 , r2 0 to r2 2 , r3 to r7, r8 0 , and r8 1 ) that also have a peripheral function (timer, serial interface, etc.). with these pins, the peripheral function setting has priority over the d port or r port pin setting. when a peripheral function setting has been made for a pin, the pin function and input/output mode will be switched automatically in accordance with that setting. ? selection of input or output for i/o pins, or selection of the port or peripheral function for pins multiplexed as peripheral function pins, is performed by the program. ? all output of the peripheral function pins are cmos outputs. the so pin and r2 2 port pin can be designated as nmos open-drain output by the program. ? a reset clears peripheral function selection. and since the data control registers (dcd, dcr) are also reset, input/output pins go to the high-impedance state. ? each i/o pin has a built-in pull-up mos that can be turned on and off individually by the program. figure 26 shows the i/o buffer configuration, and table 22 shows i/o pin circuit configuration control by the program. table 23 shows the circuit configuration of each i/o pin. pull-up mos pull-up control signal buffer control signal output data input data v cc pmos nmos input control signal mis3 dcd, dcr pdr v cc figure 26 i/o pin circuit configuration
hd404889/hd404899/hd404878/hd404868 series 68 table 22 programmable i/o circuits mis3 (bit 3 of mis) 0 1 dcd,dcr 0 1 0 1 pdr 0 101 010 1 cmos buffer pmos on on nmos on on pull-up mos on on note: ?: off table 23 circuit configurations of i/o pins type circuit configuration pins i/o pins v cc v cc input control signal mis3 dcd, dcr pdr pull-up control signal buffer control signal output data input data d 0 -d 11 r0 0 -r0 3 r1 0 -r1 3 r2 0 , r2 1 , r2 3 r3 0 -r3 3 r4 0 -r4 3 r5 0 -r5 3 r6 0 -r6 3 r7 0 -r7 3 r8 0 -r8 1 v cc v cc input control signal mis3 dcr pdr pull-up control signal buffer control signal output data input data smr22 r2 2 perip- heral function pins i/o pins v cc v cc mis3 pdr pull-up control signal i/o control signal output data input data sck sck sck note: in a reset, since the i/o control registers are reset, input/output pins go to the high-impedance state and peripheral function selections are cleared.
hd404889/hd404899/hd404878/hd404868 series 69 table 23 circuit configurations of i/o pins (cont) type circuit configuration pins perip- heral function pins output pins v cc v cc mis3 pdr pull-up control signal pmos control signal output data smr22 so so v cc v cc mis3 pdr pull-up control signal output data tob, toc, buzz tob, toc, buzz input pins reset input data reset v cc mis3 pdr wu 0 wu 3 etc. wu 0 - wu 3 , int 0 , int 1 , evnb, evnd, si v cc mis3 pdr a/d input input control signal an 0 -an 5 * notes: in a reset, since the i/o control registers are reset, input/output pins go to the high-impedance state and peripheral function selections are cleared. * applies to hd404889, hd404899, and hd404868 series.
hd404889/hd404899/hd404878/hd404868 series 70 d port the d port consists of 12 i/o pins (10 i/o pins in the hd404868 series) that are addressed bit-by-bit. ports d 0 to d 3 are source large-current i/o pins, and ports d 4 to d 11 (ports d 4 to d 9 in the hd404868 series) are sink large-current i/o pins. the d port can be set and reset by the sed and red instructions or the sedd and redd instructions. output data is stored in the port data register (pdr) for each pin. the entire d port can be tested by the td or tdd instruction. the d port output buffer is turned on and off by the d port data control registers (dcd0 to dcd2: $030 to $032). the dcd registers are mapped onto memory addresses (figure 27). ports d 0 and d 1 are multiplexed as interrupt input pins int 0 and int 1 , respectively. setting as interrupt pins is performed by bits 0 and 1 (pmr00, pmr01) of port mode register 0 (pmr0: $008) (figure 28).
hd404889/hd404899/hd404878/hd404868 series 71 data control registers note: * applies to hd404889, hd404899, and hd404878 series (dcd0? : $030?032) (dcr0? : $034?03c) register name dcd0?cd2 dcr0?cr8 bit read/write reset bit name read/write reset bit name 3 w 0 dcd03?cd23 w 0 dcr03?cr73 2 w 0 dcd02?cd22 w 0 dcr02?cr72 1 w 0 dcd01?cd21 w 0 dcr01?cr81 0 w 0 dcd00?cd20 w 0 dcr00?cr80 all bits 0 1 cmos buffer off (high impedance) cmos buffer active cmos buffer control register name dcd0 dcd1 dcd2 dcr0 dcr1 dcr2 dcr3 dcr4 dcr5 dcr6 dcr7 dcr8 bit 3 d 3 d 7 d 11 * r0 3 * r1 3 r2 3 r3 3 r4 3 r5 3 r6 3 r7 3 bit 2 d 2 d 6 d 10 * r0 2 r1 2 r2 2 r3 2 r4 2 r5 2 r6 2 r7 2 bit 1 d 1 d 5 d 9 r0 1 r1 1 r2 1 r3 1 r4 1 r5 1 r6 1 r7 1 r8 1 * bit 0 d 0 d 4 d 8 r0 0 r1 0 r2 0 r3 0 r4 0 r5 0 r6 0 r7 0 r8 0 * correspondence between each bit of dcd and dcr and ports figure 27 data control registers (dcd, dcr)
hd404889/hd404899/hd404878/hd404868 series 72 r port the r port consists of 34 i/o pins (31 i/o pins in the hd404868 series) that are addressed in 4-bit units. input can be performed by means of the lar and lbr instructions, and output by means of the lra and lrb instructions. output data is stored in the port data register (pdr) for each pin. the r port output buffer is turned on and off by the r port data control registers (dcr0 to dcr8: $034 to $03c). the dcr registers are mapped onto memory addresses (figure 27). ports r0 0 to r0 3 are multiplexed as wakeup input pins wu 0 to wu 3 , respectively. setting of these pins as peripheral function pins is performed by port mode register 1 (pmr1: $009) (figure 29). ports r1 0 and r1 1 are multiplexed as peripheral function pins evnb and evnd, respectively. setting of these pins as peripheral function pins is performed by bits 0 and 1 (pmr20, pmr21) of port mode register 2 (pmr2: $00a) (figure 30). ports r1 2 to r1 3 and r2 0 are multiplexed as peripheral function pins buzz, tob, and toc, respectively. setting of these pins as peripheral function pins is performed by bits 2 and 3 (pmr22, pmr23) of port mode register 2 (pmr2: $00a) and bit 0 (pmr30) of port mode register 3 (pmr3: $00b)(figures 30 and 31). ports r2 1 and r2 2 are multiplexed as peripheral function pins sck and si/so, respectively. setting of these pins as peripheral function pins is performed by bits 1 to 3 (pmr31 to pmr33) of port mode register 3 (pmr3: $00b) (figure 31). ports r3 to r6 are multiplexed as peripheral function pins seg1 to seg16, respectively. setting of these pins as segment pins is performed every 4 pins in 4-bit units by port mode register 4 (pmr4: $00c) (figure 32). ports r7 0 to r7 3 and r8 0 to r8 1 also function as peripheral function pins an 0 to an 5 (hd404889, hd404899, and hd404868 series only). peripheral function pin setting of these pins is performed using bits 1 to 3 (amr 1 to amr 3 ) of the a/d mode register (amr :$028). (see figure 74 in a/d converter.)
hd404889/hd404899/hd404878/hd404868 series 73 port mode register 0 (pmr0: $008) bit read/write initial value on reset bit name 3 not used 2 not used 1 w 0 pmr01 0 w 0 pmr00 pmr00 0 1 d 0 / int 0 pin mode selection d 0 int 0 pmr01 0 1 d 1 /int 1 pin mode selection d 1 int 1 figure 28 port mode register 0 (pmr0: $008)
hd404889/hd404899/hd404878/hd404868 series 74 r0 0 / wu 0 pin mode selection r0 0 wu 0 bit read/write initial value on reset bit name 3 w 0 pmr13 * pmr13 0 1 r0 3 / wu 3 pin mode selection r0 3 wu 3 2 w 0 pmr12 pmr12 0 1 r0 2 / wu 2 pin mode selection r0 2 wu 2 1 w 0 pmr11 pmr11 0 1 r0 1 / wu 1 pin mode selection r0 1 wu 1 0 w 0 pmr10 pmr10 0 1 port mode register 1 (pmr1: $009) note: * applies to hd404889, hd404899, and hd404878 series figure 29 port mode register 1 (pmr1: $009)
hd404889/hd404899/hd404878/hd404868 series 75 r1 0 /evnb pin mode selection r1 0 evnb bit read/write initial value on reset bit name 3 w 0 pmr23 pmr23 0 1 r1 3 /tob pin mode selection r1 3 tob 2 w 0 pmr22 pmr22 0 1 r1 2 /buzz pin mode selection r1 2 buzz 1 w 0 pmr21 * pmr21 0 1 r1 1 /evnd pin mode selection r1 1 evnd 0 w 0 pmr20 pmr20 0 1 port mode register 2 (pmr2: $00a) note: * applies to hd404889, hd404899, and hd404878 series figure 30 port mode register 2 (pmr2: $00a)
hd404889/hd404899/hd404878/hd404868 series 76 r2 0 /toc pin mode selection r2 0 toc bit read/write initial value on reset bit name 3 w 0 pmr33 2 w 0 pmr32 pmr32 * 0 1 pmr33 0 1 r2 2 /si/so pin mode selection r2 2 si so 1 w 0 pmr31 pmr31 0 1 r2 1 / sck pin mode selection r2 1 sck 0 w 0 pmr30 pmr30 0 1 port mode register 3 (pmr3: $00b) * : don't care figure 31 port mode register 3 (pmr3: $00b)
hd404889/hd404899/hd404878/hd404868 series 77 r3/seg1 to seg4 pin mode selection r3 seg1? bit read/write initial value on reset bit name 3 w 0 pmr43 pmr43 0 1* r6/seg13 to seg16 pin mode selection r6 seg13?6 2 w 0 pmr42 pmr42 0 1* r5/seg9 to seg12 pin mode selection r5 seg9?2 1 w 0 pmr41 pmr41 0 1* r4/seg5 to seg8 pin mode selection r4 seg5? 0 w 0 pmr40 pmr40 0 1* port mode register 4 (pmr4: $00c) * : when use as a segment output pin, write its port data register (pdr) to '0' figure 32 port mode register 4 (pmr4: $00c) pull-up mos control program-controllable pull-ups mos are incorporated in all i/o pins. on/off control of all pull-ups mos is performed by bit 3 (mis3) of the miscellaneous register (mis: $005) and the port data register (pdr) for each pin, enabling the pull-up mos to be turned on or off independently for each pin (table 22, figure 33). except for analog input multiplexed pins, the pull-up mos on/off setting can be made independent of the setting as an on-chip supporting module pin.
hd404889/hd404899/hd404878/hd404868 series 78 bit read/write initial value on reset bit name 3 w 0 mis3 2 1 w 0 mis1 0 w 0 mis0 t rc selection (see figure 17 in the operating modes section) miscellaneous register (mis: $005) mis3 0 1 pull-up mos control all pull-ups mos off pull-up mos active figure 33 miscellaneous register (mis:$005) handling of i/o pins not used by user system if i/o pins that are not used by the user system are left floating, they may generate noise that can result in chip malfunctions. therefore, the pin potential must be fixed. in this case, pull the pins up to v cc with the built-in pull-up mos or with an external resistor of approximately 100 k w .
hd404889/hd404899/hd404878/hd404868 series 79 prescalers the mcu has the following two prescalers, s and w. the operating conditions for each prescaler are shown in table 24, and the output supply destinations in figure 34. timer a to d input clocks other than external events, serial transfer clocks other than external clocks, and the lcd circuit operating clock are selected from the prescaler outputs in accordance with the respective mode register. prescaler operation prescaler s (pss): prescaler s is an 11-bit counter that has the system clock as input. when the mcu is reset, prescaler s is reset to $000, then divides the system clock. prescaler s operation is stopped by a reset by the mcu, and in stop mode and watch mode. it does not stop in any other modes. prescaler w (psw): prescaler w is a counter that has a clock divided from the x1 input (32 khz crystal oscillation) as input. when the mcu is reset, prescaler w is reset to $00, then divides the input clock. prescaler w can also be reset by software. table 24 prescaler operating conditions prescaler input clock reset conditions stop conditions prescaler s system clock in active and standby modes, subsystem clock in subactive mode mcu reset, stop mode clearance mcu reset, stop mode, watch mode prescaler w clock obtained by division- by-8 of 32.768 khz oscillation by subsystem clock oscillator mcu reset, software* mcu reset, stop mode note: if bits tma3 to tma1 in timer mode register a (tma) are all set to 1, psw is cleared to $00.
hd404889/hd404899/hd404878/hd404868 series 80 prescaler w system clock prescaler s clock selector lcd controller driver circuit subsystem clock serial interface timer d timer c timer b timer a figure 34 prescaler output destinations
hd404889/hd404899/hd404878/hd404868 series 81 timers the mcu incorporates four timers, a to d, in the hd404889, hd404899, and hd404878 series, or three timers, a to c, in the hd404868 series. ? timer a: free-running timer ? timer b: multifunctional timer ? timer c: multifunctional timer ? timer d: multifunctional timer timer a is an 8-bit free-running timer. timers b, c, and d are 8-bit multifunctional timers; each one of their have the functions shown in table 25 and their operating mode can be set by the program. table 25 timer functions functios timer a timer b timer c timer d clock source prescaler s available available available available prescaler w available external event available available timer functions free-running available available available available time-base available event counter available available reload available available available watchdog available input capture available timer outputs toggle available available pwm available available note: ?implies not available timer a timer a functions timer a has the following functions. ? free-running timer ? realtime clock time base the block diagram of timer a is shown in figure 35.
hd404889/hd404899/hd404878/hd404868 series 82 1/4 1/2 32.768-khz oscillator system clock data bus clock line signal line prescaler w (psw) selector selector prescaler s (pss) selector internal data bus timer a interrupt request flag (ifta) clock overflow timer counter a (tca) timer mode register a (tma) 3 2 f 1/2 t wcyc f t wcyc per 2 4 8 32 128 512 1024 2048 ? ? ? ? ? ? ? ? 2 8 16 32 ? ? ? ? w w figure 35 timer a block diagram timer a operation free-running timer operation: the timer a input clock is selected by timer mode register a (tma: $00f). timer a is reset to $00 by an mcu reset, and counts up each time the input clock is input. when the input clock is input after the timer a value reaches $ff, overflow output is generated, and the timer a value becomes $00. the generated overflow output sets the timer a interrupt request flag (ifta: $002,0). timer a continues counting up after the count value returns to $00, so that an interrupt is generated regularly every 256 input clock cycles. realtime clock time base operation: timer a can be used as the realtime clock time base by setting bit 3 (tma3) of timer mode register a to 1. as the prescaler w output is input to timer/counter a, interrupts are generated with accurate timing using the 32.768 khz crystal oscillator as the basic clock. when timer a is used as the realtime clock time base, prescaler w and timer/counter a can be reset to $00 by the program.
hd404889/hd404899/hd404878/hd404868 series 83 timer a register timer a operation is set by means of the following register. timer mode register a (tma: $00f): timer mode register a (tma: $00f) is a 4-bit write-only register. timer a operation and input clock selection are set as shown in figure 36.
hd404889/hd404899/hd404878/hd404868 series 84 bit read/write initial value on reset bit name 3 w 0 tma3 2 w 0 tma2 1 w 0 tma1 0 w 0 tma0 tma3 0 1 tma2 0 1 1 0 tma1 0 1 1 0 1 0 0 1 tma0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 * source prescaler pss pss pss pss pss pss pss pss psw psw psw psw psw input clock period 2,048 t cyc 1,024 t cyc 512 t cyc 128 t cyc 32 t cyc 8 t cyc 4 t cyc 2 t cyc 32 t wcyc 16 t wcyc 8 t wcyc 2 t wcyc 1/2 t wcyc operating mode timer a mode time base mode timer mode register a (tma: $00f) not used psw, tca reset * : don't care notes: 1. t wcyc = 244.14 s (using 32.768 khz crystal oscillator) 2. timer/counter overflow output period (s) = input clock period (s) 256. 3. if psw and tca reset is selected during lcd, the lcd enters the halt state (power switch off). therefore, to provide continuous lcd the psw and tca reset interval must be minimized by the program. 4. the division ratio must not be changed while time base mode is being used, as this will result in an error in the overflow period. figure 36 timer mode register a (tma)
hd404889/hd404899/hd404878/hd404868 series 85 timer b timer b functions: timer b has the following functions. ? free-running/reload timer ? external event counter ? timer output operation (toggle output, pwm output) the block diagram of timer b is shown in figure 37. 3 1 2 3 4 4 4 timer b ineterrupt request flag (iftb) (tcbl) (tcbu) timer read register bu (trbu) internal data bus timer read register bl (trbl) timer counter b timer write register b (twbl) (twbu) free-runnning/reload control timer mode register b1 (tmb1) timer mode register b2 (tmb2) data bus clock line signal line selector overflow prescaler s (pss) system clock ? 2 ? 4 ? 8 ? 32 ? 128 ? 512 ? 2048 timer output control logic timer c clock source edge detection logic tob evnb per figure 37 timer b block diagram
hd404889/hd404899/hd404878/hd404868 series 86 timer b operation ? free-running/reload timer: free-running/reload timer operation, the input clock source, and the prescaler division ratio are selected by means of timer mode register b1 (tmb1). timer b is initialized to the value written to timer write register b (twbl, twbu) by software, and counts up by 1 each time the input clock is input. when the input clock is input after the timer b value reaches $ff, overflow output is generated. timer b is then set to the value in timer write register b if the reload timer function is selected, or to $00 if the free-running timer function is selected, and starts counting up again. overflow output sets the timer b interrupt request flag (iftb). this flag is reset by the program or by an mcu reset. for details, see figure 3, interrupt control bit and register flag area configuration, and table 1, initial values after mcu reset. ? external event counter operation: when external event input is designated for the input clock, timer b operates as an external event counter. when external event input is used, the r1 0 /evnb pin is designated as the evnb pin by port mode register 2 (pmr2). the external event detected edge for timer b can be designated as a falling edge, rising edge, or both falling and rising edges in the input signal by means of timer mode register b2 (tmb2). if both falling and rising edges are selected, the input signal falling and rising edge interval should be at least 2tcyc. timer b counts up by 1 each time a falling edge is detected in the signal input at the evnb pin. other operations are the same as for the free-running/reload timer function. ? timer output operation: with timer b, the r13/tob pin is designated as the tob pin by the setting of bit 3 of port mode register 2 (pmr2), and toggle waveform output or pwm waveform output can be selected by timer mode register b2 (tmb2). ? toggle output: with toggle output, the output level is changed upon input of the next clock pulse after the timer b value reaches $ff. use of this function in combination with the reload timer allows a clock signal with any period to be output, enabling it to be used as buzzer output. the output waveform is shown in figure 38 (1). ? pwm output: with pwm output, variable-duty pulses are output. the output waveform is as shown in figure 38 (2), according to the contents of timer mode register b1 (tmb1) and timer write register b (twbl, twbu). when the waveform is output with bit 3 (tmb13) of timer mode register b1 cleared to 0, the write to timer write register b to change the duty is effective from the next frame, whereas if the waveform is output with the tmb13 bit set to 1 (reload setting), the next frame is output immediately after the timer write register write. ? module standby: with timer b, the supply of the system clock to the timer/counter can be halted by setting bit 0 of module standby register 1 (msr1: $00d) to 1. in the module standby state, the mode register value is retained but the counter value is not guaranteed.
hd404889/hd404899/hd404878/hd404868 series 87 (1) toggle output waveform (timer b, timer c) (2) pwm output waveform (timer b, timer c) ( ) 256 clock periods 256 clock periods free-running timer (256 ?n) clock periods (256 ?n) clock periods reload timer t (n + 1) t 256 t t (256 ?n) tmb13 = 0 (free-running timer) tmb13 = 1 (reload timer) notes: t: counter input clock period the clock input source and division ratio are controlled by timer mode register b1 and timer mode register c1. n: value in timer write register b or timer write register c when n = 255 (= $ff), pwm output is always fixed at the timer low level.) figure 38 timer output waveforms
hd404889/hd404899/hd404878/hd404868 series 88 timer b registers timer b operation setting and timer b value reading/writing is controlled by the following registers. timer mode register b1 (tmb1: $010) timer mode register b2 (tmb2: $011) timer write register b (twbl: $012, twbu: $013) timer read register b (trbl: $012, trbu: $013) port mode register 2 (pmr2: $00a) module standby register 1 (msr1: $00d) ? timer mode register b1 (tmb1: $010): timer mode register b1 (tmb1) is a 4-bit write-only register, used to select free-running/reload timer operation and the input clock as shown in figure 39. timer mode register b1 (tmb1) is reset to $0 by an mcu reset: a modification of timer mode register b1 (tmb1) becomes effective after execution of two instructions following the timer mode register b1 (tmb1) write instruction. the program must provide for timer b initialization by writing to timer write register b (twbl, twbu) to be executed after the post- modification mode has become effective.
hd404889/hd404899/hd404878/hd404868 series 89 3 w 0 tmb13 2 w 0 tmb12 1 w 0 tmb11 0 w 0 tmb10 bit read/write initial value on reset bit name 0 1 tmb12 tmb11 tmb10 0 1 0 1 0 1 0 1 0 1 input clock period and input clock source 1 2,048 t cyc 512 t cyc 128 t cyc 32 t cyc 8 t cyc 4 t cyc 2 t cyc r1 0 /evnb (external event input) 0 tmb13 0 1 free-running/reload timer free-running timer reload timer timer mode register b1 (tmb1: $010) figure 39 timer mode register b1 (tmb1) ? timer mode register b2 (tmb2: $011): timer mode register b2 (tmb2) is a 3-bit write-only register, used to select the timer b output mode and evnb pin detected edge as shown in figure 40. timer mode register b2 (tmb2) is reset to $0 by an mcu reset.
hd404889/hd404899/hd404878/hd404868 series 90 tmb20 0 1 0 1 evnb pin detected edge not detected falling edge detection rising edge detection both rising and falling edge detection tmb22 0 1 timer b output waveform toggle output pwm output tmb21 0 1 timer mode register b2 (tmb2: $011) bit read/write initial value on reset bit name 3 2 w 0 tmb22 1 w 0 tmb21 0 w 0 tmb20 figure 40 timer mode register b2 (tmb2) ? timer write register b (twbl: $012, twbu:$013): timer write register b (twbl, twbu) is a write-only register composed of a lower digit (twbl) and an upper digit (twbu) (figures 41 and 42). the lower digit (twbl) of timer write register b is reset to $0 by an mcu reset, while the upper digit (twbu) is undetermined. timer b can be initialized by writing to timer write register b (twbl, twbu). to write the data, first write the lower digit (twbl). the lower digit write does not change the timer b value. next, write the upper digit (twbu). timer b is then initialized to the timer write register b (twbl, twbu) value. when writing to timer write register b (twbl, twbu) from the second time onward, if it is not necessary to change the lower digit (twbl) reload value, timer b initialization is completed by the upper digit write alone. 3 w 0 twbl3 2 w 0 twbl2 1 w 0 twbl1 0 w 0 twbl0 timer write register b (lower) (twbl: $012) bit read/write initial value on reset bit name figure 41 timer write register b (lower) (twbl)
hd404889/hd404899/hd404878/hd404868 series 91 3 w undetermined twbu3 2 w undetermined twbu2 1 w undetermined twbu1 0 w undetermined twbu0 timer write register b (upper) (twbu: $013) bit read/write initial value on reset bit name figure 42 timer write register b (upper) (twbu) ? timer read register b (trbl: $012, trbu: $013): timer read register b (trbl, trbu) is a read-only register composed of a lower digit (trbl) and an upper digit (trbu) from which the value of the upper digit of timer b is read directly (figures 43 and 44). first, read the upper digit (trbu) of timer read register b. the current value of the timer b upper digit is read and, at the same time, the value of the timer b lower digit is latched in the lower digit (trbl) of timer read register b. the timer b value is obtained when the upper digit (trbu) of timer read register b is read by reading the lower digit (trbl) of timer read register b. 3 r undetermined trbl3 2 r undetermined trbl2 1 r undetermined trbl1 0 r undetermined trbl0 timer read register b (lower) (trbl: $012) bit read/write initial value on reset bit name figure 43 timer read register b (lower) (trbl) bit read/write initial value on reset bit name 3 r undetermined trbu3 2 r undetermined trbu2 1 r undetermined trbu1 0 r undetermined trbu0 timer read register b (upper) (trbu: $013) figure 44 timer read register b (upper) (trbu)
hd404889/hd404899/hd404878/hd404868 series 92 ? port mode register 2 (pmr2: $00a): port mode register 2 (pmr2) is a write-only register used to set the function of the r1 0 /evnb and r1 3 /tob pins as shown in figure 45. port mode register 2 (pmr2) is reset to $0 by an mcu reset. r1 0 /evnb pin mode selection r1 0 evnb bit read/write initial value on reset bit name 3 w 0 pmr23 pmr23 0 1 r1 3 /tob pin mode selection r1 3 tob 2 w 0 pmr22 pmr22 0 1 r1 2 /buzz pin mode selection r1 2 buzz 1 w 0 pmr21 * pmr21 0 1 r1 1 /evnd pin mode selection r1 1 evnd 0 w 0 pmr20 pmr20 0 1 port mode register 2 (pmr2: $00a) note: * applies to hd404889, hd404899, and hd404878 series figure 45 port mode register 2 (pmr2: $00a) ? module standby register 1 (msr1: $00d): module standby register 1 (msr1) is a write-only register used to designate supply or stopping of the clock to timer b as shown in figure 46. module standby register 1 (msr1) is reset to $0 by an mcu reset.
hd404889/hd404899/hd404878/hd404868 series 93 timer b clock supply control supplied stopped bit read/write initial value on reset bit name 3 2 w 0 msr12 1 w 0 msr11 msr11 0 1 timer c clock supply control supplied stopped 0 w 0 msr10 msr10 0 1 msr12 0 1 timer d clock supply control supplied stopped module standby register 1 (msr1: $00d) figure 46 module standby register 1 (msr1)
hd404889/hd404899/hd404878/hd404868 series 94 timer c timer c functions:timer : c has the following functions. ? free-running/reload timer ? watchdog timer ? timer output operation (toggle output, pwm output) the block diagram of timer c is shown in figure 47.
hd404889/hd404899/hd404878/hd404868 series 95 (twcl) (twcu) 2 4 8 32 128 512 ? per 3 4 4 4 toc 2048 (tccl) (tccu) system reset signal watchdog on flag (wdon) timer output control logic timer b overflow system clock prescaler (pss) watchdog timer control logic timer c interrupt request flag (iftc) timer read register cl (trcl) timer read register cu (trcu) overflow timer counter c timer write register c timer mode register c1 (tmc1) timer output control timer mode register c2 (tmc2) selector free-running/reload control internal data bus data bus clock line signal line figure 47 timer c block diagram
hd404889/hd404899/hd404878/hd404868 series 96 timer c operation ? free-running/reload timer: free-running/reload timer operation, the input clock source, and the prescaler division ratio are selected by means of timer mode register c1 (tmc1). timer c is initialized to the value written to timer write register c (twcl, twcu) by software, and counts up by 1 each time the input clock is input. when the input clock is input after the timer c value reaches $ff, overflow output is generated. timer c is then set to the value in timer write register c (twcl, twcu) if the reload timer function is selected, or to $00 if the free-running timer function is selected, and starts counting up again. overflow output sets the timer c interrupt request flag (iftc). this flag is reset by the program or by an mcu reset. for details, see figure 3, interrupt control bit and register flag area configuration, and table 1, initial values after mcu reset. ? 16-bit timer operation: when timer b overflow flag is selected as the clock source, timer c can be used as a 16-bit timer that counts the timer b clock source pulses. in this case, since the timer b and timer c free-running/reload settings are independent, the settings should be made to suit the purpose. ? watchdog timer operation: by using the timer c overflow output, timer c can be used as a watchdog timer for detecting program runaway. the watchdog timer is enabled when the watchdog on flag (wdon) is set to 1, and generates an mcu reset when timer c overflows. usually, timer c initialization is performed by the program before the timer c value reaches $ff, so controlling program runaway. ? timer output operation: with timer c, the r2 0 /toc pin is designated as the toc pin by setting bit 0 of port mode register 3 (pmr3) to 1, and toggle waveform output or pwm waveform output can be selected by timer mode register c2 (tmc2). ? toggle output the operation is similar to that for timer b toggle output. ? pwm output the operation is similar to that for timer b pwm output. ? module standby: the operation is similar to that for timer b module standby.
hd404889/hd404899/hd404878/hd404868 series 97 timer c registers timer c operation setting and timer c value reading/writing is controlled by the following registers. timer mode register c1 (tmc1: $014) timer mode register c2 (tmc2: $015) timer write register c (twcl: $016, twcu: $017) timer read register c (trcl: $016, trcu: $017) port mode register 3 (pmr3: $00b) module standby register 1 (msr1: $00d) ? timer mode register c1 (tmc1: $014): timer mode register c1 (tmc1) is a 4-bit write-only register, used to select free-running/reload timer operation, the input clock, and the prescaler division ratio as shown in figure 48. timer mode register c1 (tmc1) is reset to $0 by an mcu reset. a modification of timer mode register c1 (tmc1) becomes effective after execution of two instructions following the timer mode register c1 (tmc1) write instruction. the program must provide for timer c initialization by writing to timer write register c (twcl, twcu) to be executed after the post- modification mode has become effective.
hd404889/hd404899/hd404878/hd404868 series 98 3 w 0 tmc13 2 w 0 tmc12 1 w 0 tmc11 0 w 0 tmc10 timer mode register c1 (tmc1: $014) tmc12 tmc11 tmc10 input clock period 2,048 t cyc 512 t cyc 128 t cyc 32 t cyc 8 t cyc 4 t cyc 2 t cyc timer b overflow 0 1 0 1 0 1 0 1 0 1 0 1 0 1 tmc13 0 1 bit read/write initial value on reset bit name free-running/reload timer free-running timer reload timer figure 48 timer mode register c1 (tmc1)
hd404889/hd404899/hd404878/hd404868 series 99 ? timer mode register c2 (tmc2: $015): timer mode register c2 (tmc2) is a 1-bit write-only register, used to select the timer c output mode as shown in figure 49. timer mode register c2 (tmc2) is reset to $0 by an mcu reset. 3 2 w 0 tmc22 tmc22 0 1 1 0 timer mode register c2 (tmc2: $015) bit read/write initial value on reset bit name timer c output waveform toggle output pwm output figure 49 timer mode register c2 (tmc2) ? timer write register c (twcl: $016, twcu: $017): timer write register c (twcl, twcu) is a write-only register composed of a lower digit (twcl) and an upper digit (twcu) (figures 50 and 51). timer write register c (twcl, twcu) operation is similar to that for timer write register b (twbl, twbu). timer write register c (lower) (twcl: $016) 3 w 0 twcl3 2 w 0 twcl2 1 w 0 twcl1 0 w 0 twcl0 bit read/write initial value on reset bit name figure 50 timer write register c (lower) (twcl)
hd404889/hd404899/hd404878/hd404868 series 100 timer write register c (upper) (twcu: $017) bit read/write initial value on reset bit name 3 w undetermined twcu3 2 w undetermined twcu2 1 w undetermined twcu1 0 w undetermined twcu0 figure 51 timer write register c (upper) (twcu) ? timer read register c (trcl: $016, trcu: $017): timer read register c (trcl, trcu) is a read-only register composed of a lower digit (trcl) and an upper digit (trcu) from which the value of the upper digit of timer c is read directly (figures 52 and 53). timer read register c (trcl, trcu) operation is similar to that for timer read register b (trbl, trbu). timer read register c (upper) (trcl: $016) bit read/write initial value on reset bit name 3 r undetermined trcl3 2 r undetermined trcl2 1 r undetermined trcl1 0 r undetermined trcl0 figure 52 timer read register c (lower) (trcl) timer read register c (upper) (trcu: $017) bit read/write initial value on reset bit name 3 r undetermined trcu3 2 r undetermined trcu2 1 r undetermined trcu1 0 r undetermined trcu0 figure 53 timer read register c (upper) (trcu)
hd404889/hd404899/hd404878/hd404868 series 101 ? port mode register 3 (pmr3: $00b): port mode register 3 (pmr3) is a write-only register used to set the function of the r2 0 /toc pin as shown in figure 54. port mode register 3 (pmr3) is reset to $0 by an mcu reset. r2 0 /toc pin mode selection r2 0 toc bit read/write initial value on reset bit name 3 w 0 pmr33 2 w 0 pmr32 pmr32 * 0 1 pmr33 0 1 r2 2 /si/so pin mode selection r2 2 si so 1 w 0 pmr31 pmr31 0 1 r2 1 / sck pin mode selection r2 1 sck 0 w 0 pmr30 pmr30 0 1 port mode register 3 (pmr3: $00b) * : don't care figure 54 port mode register 3 (pmr3) ? module standby register 1 (msr1: $00d): module standby register 1 (msr1) is a write-only register used to designate supply or stopping of the clock to timer c as shown in figure 46. module standby register 1 (msr1) is reset to $0 by an mcu reset.
hd404889/hd404899/hd404878/hd404868 series 102 timer d (hd404889/hd404899/hd404878 series) timer d functions : timer d has the following functions. ? free-running/reload timer ? external event counter ? input capture timer block diagrams of timer d in different operating modes are shown in figures 55-1 and 55-2.
hd404889/hd404899/hd404878/hd404868 series 103 (twdl) (twdu) ? 2 ? 4 ? 8 ? 32 ? 128 ? 512 ? 2048 2 3 4 4 4 ?er timer read register du (trdu) prescaler s (pss) selector edge detection logic evnd system clock edge detection control data bus clock line signal line timer mode register d2 (tmd2) timer write register d free-running/ reload control timer read register dl (trdl) timer d interrupt request flag (iftd) internal data bus overflow (tcdl) (tcdu) timer counter d timer mode register d1 (tmd1) figure 55-1 timer d block diagram (reload timer and event counter modes)
hd404889/hd404899/hd404878/hd404868 series 104 2 3 3 4 4 evnd input capture status flag (icsf) input capture error flag (icef) timer d interrupt request flag (iftd) read signal edge detection logic system clock prescaler s (pss) selector timer read register d timer counter d (trdl) (trdu) (tcdl) (tcdu) input capture timer control internal data bus timer mode register d2 (tmd2) data bus clock line signal line time mode register d1 (tmd1) ? 2 ? 4 ? 8 ? 32 ? 128 ? 512 ? 2048 ?er overflow figure 55-2 timer d block diagram (input capture timer mode)
hd404889/hd404899/hd404878/hd404868 series 105 timer d operation ? free-running/reload timer: free-running/reload timer operation, the input clock source, and the prescaler division ratio are selected by means of timer mode register d1 (tmd1). timer d is initialized to the value written to timer write register d (twdl, twdu) by software, and counts up by 1 each time the input clock is input. when the input clock is input after the timer d value reaches $ff, overflow output is generated. timer d is then set to the value in timer write register d (twdl, twdu) if the reload timer function is selected, or to $00 if the free-running timer function is selected, and starts counting up again. overflow output sets the timer d interrupt request flag (iftd). this flag is reset by the program or by an mcu reset. for details, see figure 3, interrupt control bit and register flag area configuration, and table 1, initial values after mcu reset. ? external event counter operation: when external event input is designated for the input clock, timer d operates as an external event counter. when external event input is used, the r1 1 /evnd pin is designated as the evnd pin by port mode register 2 (pmr2). the external event detected edge for timer d can be designated as a falling edge, rising edge, or both falling and rising edges in the input signal by means of timer mode register d2 (tmd2). if both falling and rising edges are selected, the input signal falling and rising edge interval should be at least 2tcyc. timer d counts up by 1 each time the edge selected by timer mode register d2 (tmd2) is detected. other operations are the same as for the free-running/reload timer function. ? input capture timer operation: the input capture timer function is used to measure the time between trigger input edges input at the evnd pin. the trigger input edge can be designated as a falling edge, rising edge, or both falling and rising edges by means of timer mode register d2 (tmd2). when a trigger input edge is detected at the evnd pin, the current timer d value is stored in timer read register d (trdl, trdu), and the timer d interrupt request flag (iftd) and input capture status flag (icsf) are set. at the same time, timer d is reset to $00 and continues counting up. if the next trigger input edge is input while the input capture status flag (icsf) is set, or if timer d overflows, the input capture error flag (icef) is set. the input capture status flag (icsf) and input capture error flag (icef) are reset to 0 by an mcu reset or by writing 0 to them. when timer d is set to operate as an input capture timer, it is reset to $00.
hd404889/hd404899/hd404878/hd404868 series 106 timer d registers: timer d operation setting and timer d value reading/writing is controlled by the following registers. timer mode register d1 (tmd1: $018) timer mode register d2 (tmd2: $019) timer write register d (twdl: $01a, twdu: $01b) timer read register d (trdl: $01a, trdu: $01b) port mode register 2 (pmr2: $00a) module standby register 1 (msr1: $00d) ? timer mode register d1 (tmd1: $018): timer mode register d1 (tmd1) is a 4-bit write-only register, used to select free-running/reload timer operation, the input clock, and the prescaler division ratio as shown in figure 56. timer mode register d1 (tmd1) is reset to $0 by an mcu reset. a modification of timer mode register d1 (tmd1) becomes effective after execution of two instructions following the timer mode register d1 (tmd1) write instruction. the program must provide for timer d initialization by writing to timer write register d (twdl, twdu) to be executed after the post-modification mode has become effective. when timer d is set to operate as an input capture timer, an internal clock should be set as the input clock.
hd404889/hd404899/hd404878/hd404868 series 107 3 w 0 tmd13 2 w 0 tmd12 1 w 0 tmd11 0 w 0 tmd10 bit read/write initial value on reset bit name 0 1 tmd12 tmd11 tmd10 0 1 0 1 0 1 0 1 0 1 input clock period and input clock source 1 2,048 t cyc 512 t cyc 128 t cyc 32 t cyc 8 t cyc 4 t cyc 2 t cyc r11/evnd (external event input) 0 tmd13 0 1 free-running/reload timer free-running timer reload timer timer mode register d1 (tmd1: $018) figure 56 timer mode register d1 (tmd1) ? timer mode register d2 (tmd2: $019): timer mode register d2 (tmd2) is a 3-bit write-only register, used to select the evnd pin detected edge and input capture operation as shown in figure 57. timer mode register d2 (tmd2) is reset to $0 by an mcu reset.
hd404889/hd404899/hd404878/hd404868 series 108 tmd21 tmd20 0 1 0 1 0 1 evnd pin detected edge not detected falling edge detection rising edge detection both rising and falling edge detection tmd22 0 1 input capture setting free-running/reload timer input capture timer bit read/write initial value on reset bit name 3 2 w 0 tmd22 1 w 0 tmd21 0 w 0 tmd20 timer mode register d2 (tmd2: $019) figure 57 timer mode register d2 (tmd2) ? timer write register d (twdl: $01a, twdu: $01b): timer write register d (twdl, twdu) is a write-only register composed of a lower digit (twdl) and an upper digit (twdu) (figures 58 and 59). timer write register d (twdl, twdu) operation is similar to that for timer write register b (twbl, twbu). bit read/write initial value on reset bit name 3 w 0 twdl3 2 w 0 twdl2 1 w 0 twdl1 0 w 0 twdl0 timer write register d (lower) (twdl: $01a) figure 58 timer write register d (lower) (twdl)
hd404889/hd404899/hd404878/hd404868 series 109 bit read/write initial value on reset bit name 3 w undetermined twdu3 2 w undetermined twdu2 1 w undetermined twdu1 0 w undetermined twdu0 timer write register d (upper) (twdu: $01b) figure 59 timer write register d (upper) (twdu) ? timer read register d (trdl: $01a, trdu: $01b): timer read register d (trdl, trdu) is a read-only register composed of a lower digit (trdl) and an upper digit (trdu) (figures 60 and 61). timer read register d (trdl, trdu) operation is similar to that for timer read register b (trbl, trbu). in the input capture timer operating mode, when the timer d value is read after trigger input, it does not matter whether the lower or upper digit is read first. bit read/write initial value on reset bit name 3 r undetermined trdl3 2 r undetermined trdl2 1 r undetermined trdl1 0 r undetermined trdl0 timer read register d (lower) (trdl: $01a) figure 60 timer read register d (lower) (trdl) bit read/write initial value on reset bit name 3 r undetermined trdu3 2 r undetermined trdu2 1 r undetermined trdu1 0 r undetermined trdu0 timer read register d (upper) (trdu: $01b) figure 61 timer read register d (upper) (trdu)
hd404889/hd404899/hd404878/hd404868 series 110 ? port mode register 2 (pmr2: $00a): port mode register 2 (pmr2) is a write-only register used to set the r1 1 /evnd pin function as shown in figure 45. port mode register 2 (pmr2) is reset to $0 by an mcu reset. ? module standby register 1 (msr1: $00d): module standby register 1 (msr1) is a write-only register used to designate supply or stopping of the clock to timer d as shown in figure 46. module standby register 1 (msr1) is reset to $0 by an mcu reset.
hd404889/hd404899/hd404878/hd404868 series 111 serial interface the serial interface serially transfers and receives 8-bit data, and includes the following features. ? multiple transmit clock sources ? external clock ? internal prescaler output clock ? system clock ? output level control in idle states five registers, an octal counter, and a multiplexer are also configured for the serial interface as follows. ? serial data register (srl: $026, sru: $027) ? serial mode register 1 (smr1: $024) ? serial mode register 2 (smr2: $025) ? port mode register 3 (pmr3: $00b) ? octal counter (oc) ? selector the block diagram of the serial interface is shown in figure 62.
hd404889/hd404899/hd404878/hd404868 series 112 2 8 32 128 si/so sck system clock per 512 2048 1/2 1/2 serial interrupt request flag (ifs) octal counter (oc) idle control logic i/o control logic clock transfer control data bus clock line signal line serial mode register 1 (smr1) serial mode register 2 (smr2) serial data register (srl/u) internal data bus selector selector prescalers (pss) 2 4 figure 62 serial interface block diagram
hd404889/hd404899/hd404878/hd404868 series 113 serial interface operation selecting and changing serial interface operating mode: the operating modes that can be selected for the serial interface are shown in table 26. the combination of port mode register 3 (pmr3) values should be selected from this table. when the serial interface operating mode is changed, the serial interface internal state must be initialized by writing to serial mode register 1 (smr1). note : the serial interface is initialized by writing to serial mode register 1 (smr1: $024). see serial mode register 1 for details. table 26 serial interface operating modes pmr3 serial interface operating mode bit3 bit2 bit1 0 * 1 clock continuous output mode 1 0 1 receive mode 1 1 1 transmit mode *: don't care serial interface pin setting: the r2 1 / sck pin and r2 2 /si/so pin are set by writing data to port mode register 3 (pmr3). see serial interface registers for details. serial clock source setting: the serial clock is set by writing data to serial mode register 1 (smr1). see serial interface registers for details. serial data setting: transmit serial data is set by writing data to the serial data register (srl, sru). receive serial data is obtained by reading the serial data register (srl, sru). serial data is shifted by means of the serial clock to perform input/output from/to an external device. the output level of the so pin is undetermined until the first data is output after a reset by the mcu, or until high/low control is performed in the idle state. transfer control: serial interface operation is started by an sts instruction. the octal counter is reset to 000 by the sts instruction, and is incremented by 1 on each rise of the serial clock. when 8 serial clock pulses have been input, or if data transmission/reception is suspended midway, the octal counter is reset to 000, the serial interrupt request flag (ifs) is set, and transfer is terminated. the serial clock is selected by means of serial mode register 1 (smr1). see figure 66.
hd404889/hd404899/hd404878/hd404868 series 114 serial interface operating states: the serial interface has the operating states shown in figure 63 in external clock mode and internal clock mode. sts instruction wait state serial clock wait state transfer state clock continuous output state (internal clock mode only) ? sts instruction wait state upon mcu reset ((00) and (10) in figure 63), the serial interface enters the sts instruction wait state. in the sts instruction wait state, the internal state of the serial interface is initialized. even if the serial clock is input at this time, the serial interface will not operate. when the sts instruction is executed ((01), (11)), the serial interface enters the serial clock wait state. ? serial clock wait state the serial clock wait state is the interval from sts instruction execution until the first serial clock falling edge. when the serial clock is input in the serial clock wait state ((02), (12)), the octal counter begins counting, the contents of the serial data register (srl) begin shifting, and the serial interface enters the transfer state. however, if clock continuous output mode is selected in internal clock mode, the serial interface enters the clock continuous output state ((17)) instead of the transfer state. if a write to serial mode register 1 (smr1) is performed in the serial clock wait state, the serial interface enters the sts instruction wait state ((04), (14)). ? transfer state the transfer state is the interval from the first serial clock falling edge until the eighth serial clock rising edge. in the transfer state, if an sts instruction is executed or if eight serial clocks have been input, the octal counter is cleared to 000, and the serial interface makes a state transition. if an sts instruction is executed ((05), (15)), the serial interface enters the serial clock wait state. after eight serial clocks have been input, the serial interface enters the serial clock wait state ((03)) when in external clock mode, and enters the sts instruction wait state ((13)) when in internal clock mode. in internal clock mode, the serial clock stops after output of eight clocks. if a write to serial mode register 1 (smr1) is performed in the transfer state ((06), (16)), the serial interface is initialized and enters the sts instruction wait state. when the serial interface switches from the transfer state to another state, the octal counter is reset to 000 and the serial interrupt request flag (ifs) is set. ? clock continuous output state (internal clock mode only) in the clock continuous output state, no receive or transmit operation is performed, and the serial clock is only output from the sck pin. it is therefore effective in internal clock mode. if the serial clock is input ((17)) when bit 3 (pmr33) of port mode register 3 (pmr3) is cleared to 0 and the serial interface is in the serial clock wait state, a transition is made to the clock continuous output state. if a write to serial mode register 1 (smr1) is performed in the clock continuous output state ((18)), the serial interface enters the sts instruction wait state.
hd404889/hd404899/hd404878/hd404868 series 115 sts instruction wait state (octal counter ="000", serial clock disabled) mcu reset (00) serial clock wait state (octal counter ="000") transfer state (octal counter "000") smr1 write (14) sts instruction (11) serial clock (12) serial clocks (03) sts instruction (05) (ifs ? "1") sts instruction (15) (ifs ? "1") external clock mode sts instruction wait state (octal counter ="000", serial clock disabled) serial clock wait state (octal counter ="000") transfer state (octal counter "000") smr1 write (04) sts instruction (01) serial clock (02) smr1 write (06) (ifs ? "1") 8 serial clocks (13) smr1 write (16) (ifs ? "1") mcu reset (10) serial clock (17) smr1 write (18) clock continuous output state (pmr33 ="0") internal clock mode ( ) refer to the text for details on the circled numbers in the figure. 8 figure 63 serial interface operating states
hd404889/hd404899/hd404878/hd404868 series 116 idle high/low control: when the serial interface is in the sts instruction wait state or the serial clock wait state (i.e. when idle), the output level of the so pin can be set arbitrarily by software. idle high/low control is performed by writing the output level to bit 1 (smr21) of serial mode register 2 (smr2). an example of idle high/low control is shown in figure 64. idle high/low control cannot be performed in the transfer state.
hd404889/hd404899/hd404878/hd404868 series 117 state sck pin (input) so pin ifs msb lsb undefined idle idle idle idle idle h/l setting dummy write to cause state transition port setting sts wait state serial clock wait state transfer state sts wait state serial clock wait state external clock setting idle h/l setting (flag reset by transfer completion processing) mcu reset pmr3 write smr1 write smr2 write srl, sru write sts instruction state sck pin (output) so pin ifs msb lsb undefined idle h/l setting port setting sts wait state serial clock wait state transfer state sts wait state (flag reset by transfer completion processing) mcu reset pmr3 write smr1 write smr2 write srl, sru write sts instruction (2) internal clock mode (1) external clock mode external clock setting transmit data write transmit data write idle h/l setting figure 64 examples of serial interface operation sequence
hd404889/hd404899/hd404878/hd404868 series 118 serial clock error detection (external clock mode): the serial interface will operate incorrectly in the transfer state if external noise results in unnecessary pulses being added to the serial clock. serial clock error detection in such cases is carried out as shown in figure 65. if more than eight serial clock pulses are input due to external noise while in the transfer state, at the eighth clock pulse (including any external noise pulses), the octal counter is cleared to 000 and the serial interrupt request flag (ifs) is set. at the same time, the serial interface exits the transfer state and enters the serial clock wait state, but returns to the transfer state at the next regular clock pulse falling edge. meanwhile, in the interrupt handling routine, transfer end processing is performed, the serial interrupt request flag is reset, and a dummy write is performed into serial mode register 1 (smr1). the serial interface then returns to the sts wait state, and the serial interrupt request flag (ifs) is set again. it is therefore possible to detect a serial clock error by testing the serial interrupt request flag after the dummy write to serial mode register 1. usage notes: ? initialization after register modification if a port mode register 3 (pmr3) write is performed in the serial clock wait state or transfer state, a serial mode register 1 (smr1) write should be performed again to initialize the serial interface. ? serial interrupt request flag (ifs:$023, 2) setting if a serial mode register 1 (smr1) write or sts instruction is executed during the first low-level interval of the serial clock in the transfer state, the serial interrupt request flag (ifs) will not be set. to ensure that the serial interrupt request flag (ifs) is properly set in this case, programming is required to make sure that the sck pin is in the 1 state (by executing an input instruction for the r2 port) before executing a serial mode register 1 (smr1) write or an sts instruction.
hd404889/hd404899/hd404878/hd404868 series 119 transfer end (ifs ? "1") disable interrupts ifs ? "0" smr1 write ifs=1? normal termination serial clock error processing (1) serial clock error detection flowchart serial clock wait state transfer state serial clock wait state transfer state (noise) state sck pin (input) smr1 write ifs 1234567 8 (2) serial clock error detection sequence flag set by octal counter reaching 000 flag reset by transfer end processing yes no because the serial interface returns to the transfer state, a write to smr1 resets ifs. figure 65 example of serial clock error detection
hd404889/hd404899/hd404878/hd404868 series 120 serial interface registers serial interface operation setting and serial data reading/writing is controlled by the following registers. serial mode register 1 (smr1: $024) serial mode register 2 (smr2: $025) serial data register (srl: $026, sru: $027) port mode register 3 (pmr3: $00b) module standby register 2 (msr2: $00e) serial mode register 1 (smr1: $024): serial mode register 1 (smr1) has the following functions. see figure 66. ? serial clock selection ? prescaler division ratio selection ? serial interface initialization the serial mode register 1 (smr1) is a 4-bit write-only register, and is reset to $0 by an mcu reset. a write to serial mode register 1 (smr1) halts the supply of the serial clock to the serial data register (srl, sru) and the octal counter, and resets the octal counter to 000. therefore, if serial mode register 1 (smr1) is written to during serial interface operation, data transmission/reception will be suspended and the serial interrupt request flag (ifs) will be set. a modification of serial mode register 1 (smr1) becomes effective after execution of two instructions following the serial mode register 1 (smr1) write instruction. the program must therefore provide for the sts instruction to be executed two cycles after the instruction that writes to serial mode register 1 (smr1).
hd404889/hd404899/hd404878/hd404868 series 121 serial mode register 1 (smr1: $024) smr13 smr12 smr11 smr10 sck pin serial clock source serial clock (pss division ratio 2 or 4) serial clock cycle 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 1 0 output output output output output output output input output output output output output output output input pss pss pss pss pss pss system clock external clock pss pss pss system clock external clock pss pss pss ( per /2048) 2 ( per /512) 2 ( per /128) 2 ( per /32) 2 ( per /8) 2 ( per /2) 2 per ( per /2048) 4 ( per /512) 4 ( per /128) 4 ( per /32) 4 ( per /8) 4 ( per /2) 4 per 4096 tcyc 1024 tcyc 256 tcyc 64 tcyc 16 tcyc 4 tcyc tcyc 8192 tcyc 2048 tcyc 512 tcyc 128 tcyc 32 tcyc 8 tcyc tcyc bit read/write initial value on reset bit name 3 w 0 smr13 2 w 0 smr12 1 w 0 smr11 0 w 0 smr10 figure 66 serial mode register 1 (smr1) serial mode register 2 (smr2: $025): serial mode register 2 (smr2) has the following functions. see figure 67. ? r2 2 /si/so pin pmos control ? idle high/low control serial mode register 2 (smr2) is a 2-bit write-only register. the register value cannot be modified in the transfer state. bit 2 (smr22) of serial mode register 2 (smr2) controls the on/off status of the r2 2 /si/so pin pmos. the bit 2 (smr22) only is reset to 0 by an mcu reset.
hd404889/hd404899/hd404878/hd404868 series 122 bit 1 (smr21) of serial mode register 2 (smr2) performs so pin high/low control in the idle state. the so pin changes at the same time as the high/low write. smr21 0 1 r2 2 /si/so pin output buffer control pmos active pmos off (nmos open-drain output) smr22 0 1 idle high/low control so pin set to low-level output in idle state so pin set to high-level output in idle state serial mode register 2 (smr2: $025) bit read/write initial value on reset bit name 3 2 w 0 smr22 1 w undeternined smr21 0 figure 67 serial mode register 2 (smr2) serial data register (srl: $026, sru: $027): the serial data register (srl, sru) has the following functions. see figures 68 and 69. ? transmit data write and shift operations ? receive data shift and read operations the data written to the serial data register (srl, sru) is output lsb-first from the so pin in synchronization with the falling edge of the serial clock. external data input lsb-first from the si pin is latched in synchronization with the rising edge of the serial clock. figure 70 shows the serial clock and data input/output timing chart. writing and reading of the serial data register (srl, sru) must be performed only after data transmission/reception is completed. the data contents are not guaranteed if a read or write is performed during data transmission or reception.
hd404889/hd404899/hd404878/hd404868 series 123 serial data register (lower) (srl: $026) 3 r/w undetermined sr3 2 sr2 1 sr1 0 sr0 r/w r/w r/w undetermined undetermined undetermined bit read/write initial value on reset bit name figure 68 serial data register (srl) serial data register (upper) (sru: $027) 3 r/w undetermined sr7 2 sr6 1 sr5 0 sr4 r/w r/w r/w undetermined undetermined undetermined bit read/write initial value on reset bit name figure 69 serial data register (sru) 12345678 serial clock serial output data serial input data latch timing lsb msb figure 70 serial interface input/output timing chart
hd404889/hd404899/hd404878/hd404868 series 124 port mode register 3 (pmr3: $00b): port mode register 3 (pmr3) has the following functions. see figure 71. ? r2 1 / sck pin selection ? r2 2 /si/so pin selection port mode register 3 (pmr3) is a 4-bit write-only register used to select serial interface pin settings as shown in figure 71. it is reset to $0 by an mcu reset. r2 0 /toc pin mode selection pmr30 r2 1 / sck pin mode selection pmr31 0 1 r2 0 toc 0 1 r2 1 sck pmr33 pmr32 0 1 * 0 1 r2 2 /si/so pin mode selection r2 2 si so * : don't care port mode register 3 (pmr3: $00b) bit read/write initial value on reset bit name 3 w 0 pmr33 2 w 0 pmr32 1 w 0 pmr31 0 w 0 pmr30 figure 71 port mode register 3 (pmr3)
hd404889/hd404899/hd404878/hd404868 series 125 module standby register 2 (msr2: $00e): module standby register 2 (msr2) is a write-only register used to designate supply or stopping of the clock to the serial interface as shown in figure 72. module standby register 2 (msr2) is reset to $0 by an mcu reset. serial clock supply control supplied stopped msr20 a/d clock supply control supplied stopped msr21 0 1 0 1 module standby register 2 (msr2: $00e) bit read/write initial value on reset bit name 3 2 1 w 0 msr21 0 w 0 msr20 figure 72 module standby register 2 (msr2)
hd404889/hd404899/hd404878/hd404868 series 126 a/d converter hd404889 series the mcu has a built-in successive approximation type a/d converter using a resistance ladder method, capable of digital conversion of six analog inputs with an 8-bit resolution. the a/d converter block diagram is shown in figure 73. the a/d converter comprises the following four registers. ? a/d mode register (amr: $028) ? a/d start flag (adsf: $020,2) ? a/d data register (adrl: $02a, adru: $02b) ? module standby register 2 (msr2: $00e) note : address $029 is a reserved register, and should not be read or written to. interrupt flag (ifad) encoder a/d data register (adru, adrl) internal data bus selector conversion time control a/d start flag (adsf) comp reference voltage reference voltage control r7 0 /an 0 r7 1 /an 1 r7 2 /an 2 r7 3 /an 3 r8 0 /an 4 r8 1 /an 5 + a/d control logic a/d mode register (amr) av cc av ss d/a 3 operating mode signal (set to 1 in stop, watch, and subactive modes, and during module standby) figure 73 a/d converter block diagram
hd404889/hd404899/hd404878/hd404868 series 127 a/d mode register (amr: $028): the a/d mode register is a 4-bit write-only register that shows the a/d converter speed setting and information on the analog input pin specification. the a/d conversion time is selected by bit 0, and the channel by bits 1, 2, and 3 (figure 74). a/d start flag (adsf: $020,2): a/d conversion is started by writing 1 to the a/d start flag. when conversion ends, the converted data is placed in the a/d data register and the a/d start flag is cleared at the same time. (figure 75). bit read/write initial value on reset bit name 3 w 0 amr3 2 w 0 amr2 1 w 0 amr1 0 w 0 amr0 analog input channel selection no selection an0 an1 an2 an3 an4 an5 amr1 * 0 1 0 1 0 1 amr2 0 1 0 1 amr3 0 1 amr0 0 1 a/d conversion time 65 t cyc 125 t cyc a/d mode register (amr: $028) * : don't care figure 74 a/d mode register (amr)
hd404889/hd404899/hd404878/hd404868 series 128 bit read/write initial value on reset bit name 3 r/w 0 dton 2 r/w 0 adsf 1 r/w 0 wdon 0 r/w 0 lson a/d start flag (adsf: $020,2) 1 0 dton (see low-power mode section) wdon (see timer section) lson (see low-power mode section) a/d start flag (adsf) a/d conversion starts indicates end of a/d conversion figure 75 a/d start flag (adsf) a/d data register (adrl: $02a, adru: $02b): the a/d data register is a read-only register consisting of a lower and upper 4 bits. this register is not cleared by a reset. also, data read during a/d conversion is not guaranteed. at the end of a/d conversion, the resulting 8-bit data is stored in this register, and is held until the next conversion operation starts (figures 76, 77, and 78). msb lsb bit7 bit0 conversion result adru : $02b adrl : $02a 3 2 1 0 3 2 1 0 figure 76 a/d data register
hd404889/hd404899/hd404878/hd404868 series 129 bit read/write initial value on reset bit name 3 r 1 adrl3 2 r 1 adrl2 1 r 1 adrl1 0 r 1 adrl0 a/d data register-lower (adrl: $02a) figure 77 a/d data register-lower (adrl) bit read/write initial value on reset bit name 3 r 0 adru3 2 r 1 adru2 1 r 1 adru1 0 r 1 adru0 a/d data register-upper (adru: $02b) figure 78 a/d data register-upper (adru) module standby register 2 (msr2: $00e): writing 1 to bit 1 of module standby register 2 stops the supply of the system clock to the a/d module and cuts the current (i ad ) flowing in the ladder resistor. usage notes: ? use the sem or semd instruction to write to the a/d start flag (adsf). ? do not write to the adsf during a/d conversion. ? data in the a/d data register is undetermined during a/d conversion. ? as the a/d converter operates on a clock from osc, it stops in stop mode, watch mode, and subactive mode. the current flowing in the a/d converter ladder resistor is also cut in these low-power modes to reduce power consumption. ? when an analog input pin is selected by the a/d mode register, the pull-up mos for that pin is disabled.
hd404889/hd404899/hd404878/hd404868 series 130 a/d converter hd404899/hd404868 series the mcu has a built-in successive approximation type a/d converter using a resistance ladder method, capable of digital conversion of six analog inputs (four analog inputs in the hd404868 series) with a 10-bit resolution. the a/d converter block diagram is shown in figures 79-1 and 79-2. the a/d converter comprises the following four registers. ? a/d mode register (amr: $028) ? a/d start flag (adsf: $020,2) ? a/d data register (adrl: $029, adrm: $02a, adru: $02b) ? module standby register 2 (msr2: $00e) interrupt flag (ifad) encoder a/d data register (adru, adrm, adrl) internal data bus selector conversion time control a/d start flag (adsf) comp reference voltage reference voltage control r7 0 /an 0 r7 1 /an 1 r7 2 /an 2 r7 3 /an 3 r8 0 /an 4 r8 1 /an 5 + a/d control logic a/d mode register (amr) av cc av ss d/a 3 operating mode signal (set to 1 in stop, watch, and subactive modes, and during module standby) figure 79-1 a/d converter block diagram (hd404899 series)
hd404889/hd404899/hd404878/hd404868 series 131 interrupt flag (ifad) encoder a/d data register (adru, adrm, adrl) internal data bus selector conversion time control a/d start flag (adsf) comp reference voltage reference voltage control r7 0 /an 0 r7 1 /an 1 r7 2 /an 2 r7 3 /an 3 + a/d control logic a/d mode register (amr) v cc gnd d/a 3 operating mode signal (set to 1 in stop, watch, and subactive modes, and during module standby) figure 79-2 a/d converter block diagram (hd404868 series)
hd404889/hd404899/hd404878/hd404868 series 132 a/d mode register (amr: $028): the a/d mode register is a 4-bit write-only register that shows the a/d converter speed setting and information on the analog input pin specification. the a/d conversion time is selected by bit 0, and the channel by bits 1, 2, and 3 (figure 80). a/d start flag (adsf: $020,2): a/d conversion is started by writing 1 to the a/d start flag. when conversion ends, the converted data is placed in the a/d data register and the a/d start flag is cleared at the same time. (figure 81). bit read/write initial value on reset bit name 3 w 0 amr3 2 w 0 amr2 1 w 0 amr1 0 w 0 amr0 analog input channel selection no selection an0 an1 an2 an3 an4 * an5 * amr1 * 0 1 0 1 0 1 amr2 0 1 0 1 amr3 0 1 amr0 0 1 a/d conversion time 65 t cyc 125 t cyc a/d mode register (amr: $028) note: * applies to hd404899 series. figure 80 a/d mode register (amr)
hd404889/hd404899/hd404878/hd404868 series 133 bit read/write initial value on reset bit name 3 r/w 0 dton 2 r/w 0 adsf 1 r/w 0 wdon 0 r/w 0 lson a/d start flag (adsf: $020,2) 1 0 dton (see low-power mode section) wdon (see timer section) lson (see low-power mode section) a/d start flag (adsf) a/d conversion starts indicates end of a/d conversion figure 81 a/d start flag (adsf) a/d data register (adrl: $029, adrm: $02a, adru: $02b): the a/d data register is a read-only register consisting of a middle and upper 4 bits. this register is not cleared by a reset. also, data read during a/d conversion is not guaranteed. at the end of a/d conversion, the resulting 10-bit data is stored in this register, and is held until the next conversion operation starts (figures 82, 83, 84 and 85). msb lsb bit9 bit0 conversion result adru : $02b adrm : $02a 3 2 1 0 3 2 1 0 adrl : $029 32 figure 82 a/d data register
hd404889/hd404899/hd404878/hd404868 series 134 bit read/write initial value on reset bit name 3 r 1 adrl3 2 r 1 adrl2 1 not used 0 not used a/d data register-lower (adrl: $029) figure 83 a/d data register-lower (adrl) bit read/write initial value on reset bit name 3 r 1 adrm3 2 r 1 adrm2 1 r 1 adrm1 0 r 1 adrm0 a/d data register-middle (adrm: $02a) figure 84 a/d data register-middle (adrm) bit read/write initial value on reset bit name 3 r 0 adru3 2 r 1 adru2 1 r 1 adru1 0 r 1 adru0 a/d data register-upper (adru: $02b) figure 85 a/d data register-upper (adru) module standby register 2 (msr2: $00e): writing 1 to bit 1 of module standby register 2 stops the supply of the system clock to the a/d module and cuts the current (i ad ) flowing in the ladder resistor. usage notes: ? use the sem or semd instruction to write to the a/d start flag (adsf). ? do not write to the adsf during a/d conversion. ? data in the a/d data register is undetermined during a/d conversion.
hd404889/hd404899/hd404878/hd404868 series 135 ? as the a/d converter operates on a clock from osc, it stops in stop mode, watch mode, and subactive mode. the current flowing in the a/d converter ladder resistor is also cut in these low-power modes to reduce power consumption. ? when an analog input pin is selected by the a/d mode register, the pull-up mos for that pin is disabled.
hd404889/hd404899/hd404878/hd404868 series 136 lcd circuit the mcu incorporates a controller and driver that drive four common signal pins and 32 segment pins (24 segment pins in the hd404868 series). the controller unit consists of a ram unit that stores the display data, a display control register (lcr), and a duty/clock control register (lmr) (figures 86-1 and 86-2). the lcd circuit allows four different duties and lcd clocks to be controlled by the program, and also incorporates dual-port ram, enabling display data to be transferred to the segment signal pins automatically without program processing. if the 32 khz oscillator clock is designated as the lcd clock source, lcd display is also possible in watch mode in which the system clock stops.
hd404889/hd404899/hd404878/hd404868 series 137 common signal output circuit segment signal output circuit internal lcd power supply switch 32 2 duty selection selector lcd display control register (lcr) dual-port display ram (32 digits) lcd display mode register (lmr) 2 com1 com2 com3 com4 v 1 v 2 v 3 seg17 to seg32 lcd input clocks display data 2 display control port mode register 4 (pmr4) 4 pin control seg1 to seg4 seg9 to seg12 seg5 to seg8 clock v cc lcd power supply control circuit internal data bus data bus clock line signal line v 0 seg13 to seg16 pin function switching circuit note: figure 86-1 lcd circuit block diagram (hd404889/hd404899/hd404878 series)
hd404889/hd404899/hd404878/hd404868 series 138 common signal output circuit segment signal output circuit internal lcd power supply switch 24 2 duty selection selector lcd display control register (lcr) dual-port display ram (24 digits) lcd display mode register (lmr) 2 com1 com2 com3 com4 v 1 v 2 v 3 seg17 to seg24 lcd input clocks display data 2 display control port mode register 4 (pmr4) 4 pin control seg1 to seg4 seg9 to seg12 seg5 to seg8 clock v cc lcd power supply control circuit internal data bus data bus clock line signal line seg13 to seg16 pin function switching circuit note: figure 86-2 lcd circuit block diagram (hd404868 series)
hd404889/hd404899/hd404878/hd404868 series 139 lcd data area and segment data: $050 to $06f (hd404889/hd404899/hd404878 series) $050 to $067 (hd404868 series) figures 87-1 and 87-2 show the lcd ram area configuration. each bit of the storage area corresponds to one of four duties. when data is written to the area corresponding to a particular duty, it is automatically output to the segment as display data. $050 $051 $052 $053 $054 $055 $056 $057 $058 $059 $05a $05b $05c $05d $05e $05f bit3 bit2 bit1 bit0 seg1 seg2 seg3 seg4 seg5 seg6 seg7 seg8 seg9 seg10 seg11 seg12 seg13 seg14 seg15 seg16 seg1 seg2 seg3 seg4 seg5 seg6 seg7 seg8 seg9 seg10 seg11 seg12 seg13 seg14 seg15 seg16 seg1 seg2 seg3 seg4 seg5 seg6 seg7 seg8 seg9 seg10 seg11 seg12 seg13 seg14 seg15 seg16 seg1 seg2 seg3 seg4 seg5 seg6 seg7 seg8 seg9 seg10 seg11 seg12 seg13 seg14 seg15 seg16 com4 com3 com2 com1 seg17 seg18 seg19 seg20 seg21 seg22 seg23 seg24 seg25 seg26 seg27 seg28 seg29 seg30 seg31 seg32 com4 com3 $060 $061 $062 $063 $064 $065 $066 $067 $068 $069 $06a $06b $06c $06d $06e $06f bit3 bit2 bit1 bit0 com2 com1 seg17 seg18 seg19 seg20 seg21 seg22 seg23 seg24 seg25 seg26 seg27 seg28 seg29 seg30 seg31 seg32 seg17 seg18 seg19 seg20 seg21 seg22 seg23 seg24 seg25 seg26 seg27 seg28 seg29 seg30 seg31 seg32 seg17 seg18 seg19 seg20 seg21 seg22 seg23 seg24 seg25 seg26 seg27 seg28 seg29 seg30 seg31 seg32 figure 87-1 lcd ram area configuration (using dual-port ram) (hd404889/hd404899/hd404878 series) $050 $051 $052 $053 $054 $055 $056 $057 $058 $059 $05a $05b $05c $05d $05e $05f bit3 bit2 bit1 bit0 seg1 seg2 seg3 seg4 seg5 seg6 seg7 seg8 seg9 seg10 seg11 seg12 seg13 seg14 seg15 seg16 seg1 seg2 seg3 seg4 seg5 seg6 seg7 seg8 seg9 seg10 seg11 seg12 seg13 seg14 seg15 seg16 seg1 seg2 seg3 seg4 seg5 seg6 seg7 seg8 seg9 seg10 seg11 seg12 seg13 seg14 seg15 seg16 seg1 seg2 seg3 seg4 seg5 seg6 seg7 seg8 seg9 seg10 seg11 seg12 seg13 seg14 seg15 seg16 com4 com3 com2 com1 seg17 seg18 seg19 seg20 seg21 seg22 seg23 seg24 com4 com3 $060 $061 $062 $063 $064 $065 $066 $067 bit3 bit2 bit1 bit0 com2 com1 seg17 seg18 seg19 seg20 seg21 seg22 seg23 seg24 seg17 seg18 seg19 seg20 seg21 seg22 seg23 seg24 seg17 seg18 seg19 seg20 seg21 seg22 seg23 seg24 figure 87-2 lcd ram area configuration (using dual-port ram) (hd404868 series)
hd404889/hd404899/hd404878/hd404868 series 140 lcd control register (lcr: $02c): the lcd control register is a 4-bit write-only register that controls lcd blanking, the on/off state of the lcd power switch, display in watch mode and subactive mode, and disconnection of the lcd power supply dividing resistor, as shown in figure 88. individual bit in this register can be set and reset by bit manipulation instructions. ? display on/off control off: segment signals are in the off state, regardless of lcd ram data. on: lcd ram data is output as segment signals. ? built-in power switch on/off control off: the built-in lcd power switch is off. on: the built-in lcd power switch is on. if v0 and v1 are shorted externally, v1 goes to the v cc level. ? lcd display in watch mode and subactive mode off: in watch mode and subactive mode, all common and segment pins are fixed at gnd potential. the built-in lcd power switch is off. on: in watch mode and subactive mode, lcd ram data is output as segment signals. ? lcd power supply dividing resistor switch on/off control off: the built-in lcd power supply dividing resistor is disconnected. on: the built-in lcd power supply dividing resistor is connected.
hd404889/hd404899/hd404878/hd404868 series 141 bit read/write initial value on reset bit name 3 w 0 lcr3 2 w 0 lcr2 1 w 0 lcr1 0 w 0 lcr0 0 1 lcr0 lcd control register (lcr: $02c) 0 1 built-in lcd power switch on/off control off on lcr1 0 1 watch mode/subactive mode lcd display off on lcr2 0 1 lcd power supply dividing resistor on off lcr3 lcd on/off control off on figure 88 lcd control register (lcr)
hd404889/hd404899/hd404878/hd404868 series 142 lcd duty/clock control register (lmr: $02d): the lcd duty/clock control register is a 4-bit write-only register used to set four kinds of display duty ratio and lcd reference clock (figure 89). table 27 shows the lcd frame frequencies for each duty setting. bit read/write initial value on reset bit name 3 w 0 lmr3 2 w 0 lmr2 1 w 0 lmr1 0 w 0 lmr0 lcd duty/clock control register (lmr: $02d) lmr1 lmr0 0 1 0 1 0 1 duty factor 1/4 1/3 1/2 1 (static drive) lmr3 0 1 lmr2 0 1 0 1 lcd circuit clock cl0=32.768khz duty/128 cl1=32.768khz duty/256 cl2= per duty/256 when tma3 = 0, cl3 = per duty/2048 when tma3 = 1, cl3 = 32.768 khz duty/512 figure 89 lcd duty/clock control register (lmr)
hd404889/hd404899/hd404878/hd404868 series 143 table 27 lcd frame frequencies for each duty setting frame period duty lmr3 lmr2 fosc=400khz fosc=800khz fosc=2.0mhz fosc=4.0mhz division by 4 division by 32 division by 4 division by 32 division by 4 division by 32 division by 4 division by 32 0 0 cl0 256hz 1 cl1 128hz static 0 cl2 390.6hz 48.8hz 781.3hz 97.7hz 1953hz 244.1hz 3906hz 488.3hz 1 1 cl3* 48.8hz 6.1hz 97.7hz 12.2hz 244.1hz 30.5hz 488.3hz 61.0hz 64hz 0 0 cl0 128hz 1 cl1 64hz 1/2 0 cl2 195.3hz 24.4hz 390.6hz 48.8hz 976.6hz 122.1hz 1953hz 244.1hz 1 1 cl3* 24.4hz 3.1hz 48.8hz 6.1hz 122.1hz 15.3hz 244.1hz 30.5hz 32hz 0 0 cl0 85.3hz 1 cl1 42.7hz 1/3 0 cl2 130.1hz 16.3hz 260.2hz 32.5hz 650hz 81.3hz 1301hz 162.6hz 1 1 cl3* 16.3hz 2.0hz 32.5hz 4.1hz 81.3hz 10.2hz 162.6hz 20.3hz 21.3hz 0 0 cl0 64hz 1 cl1 32hz 1/4 0 cl2 97.7hz 12.2hz 195.3hz 24.4hz 488.3hz 61.0hz 976.6hz 122.1hz 1 1 cl3* 12.2hz 1.5hz 24.4hz 3.1hz 61.0hz 7.6hz 122.1hz 15.3hz 16hz
hd404889/hd404899/hd404878/hd404868 series 144 port mode register 4 (pmr4: $00c): port mode register 4 (pmr4) is a 4-bit write-only register that enables the r3 to r6 port pins to be switched to seg1 to seg16 pin functions in 4-port units (figure 90). 0 1 * r3 seg1? r3/seg1 to seg4 pin mode selection pmr40 0 1 * r4 seg5? 0 1 * r5 seg9?2 r4/seg5 to seg8 pin mode selection pmr41 r5/seg9 to seg12 pin mode selection pmr42 0 1 * r6 seg13?6 r6/seg13 to seg16 pin mode selection pmr43 bit read/write initial value on reset bit name 3 w 0 pmr43 2 w 0 pmr42 1 w 0 pmr41 0 w 0 pmr40 port mode register 4 (pmr4: $00c) note: * when use as a segment output pin, write its port data resister (pdr) to "0" figure 90 port mode register 4 (pmr4: $00c)
hd404889/hd404899/hd404878/hd404868 series 145 lcd drive voltage (v lcd ): example of lcd drive power supply wiring are shown in figures 91-1 and 91-2. the lcd drive voltage (v lcd ) should be within the following range. 2.2 v lcd v cc (v) if the lcd drive voltage is applied from off-chip, connect the v0 pin to v cc and turn the lcd power switch (lcd control register) off. (hd404889/hd404899/hd404878 series) when the power supply voltage is used as the lcd drive voltage, the v0 and v1 pins should be shorted. (hd404889/hd404899/hd404878 series) v cc v cc v 0 v 1 v 2 v 3 gnd com1 seg1 to seg32 static drive (power supply voltage used for v lcd ) 4-digit lcd 1 32 v cc v cc v 0 v 1 v 2 v 3 gnd com1 com2 seg1 to seg32 2 8-digit lcd 1/2 duty, 1/2 bias drive (power supply voltage used for v lcd ) v cc v 0 v 1 v 2 v 3 gnd com1 to com3 seg1 to seg32 v cc 1/3 duty, 1/3 bias drive (external power supply used for v lcd ) 3 32 10-digit signed lcd v cc v 0 v 1 v 2 v 3 gnd com1 to com4 seg1 to seg32 v cc 1/4 duty, 1/3 bias drive (external power supply used for v lcd ) 4 32 16-digit lcd v lcd v lcd 32 figure 91-1 examples of lcd wiring (hd404889/hd404899/hd404878 series)
hd404889/hd404899/hd404878/hd404868 series 146 v cc v cc v 1 v 2 v 3 gnd com1 seg1 to seg24 static drive (power supply voltage used for v lcd ) 3-digit lcd 1 24 v cc v cc v 1 v 2 v 3 gnd com1 com2 seg1 to seg24 2 6-digit lcd 8-digit lcd 1/2 duty, 1/2 bias drive (power supply voltage used for v lcd ) v cc v 1 v 2 v 3 gnd com1 to com3 seg1 to seg24 v cc 1/3 duty, 1/3 bias drive (external power supply used for v lcd ) 3 24 v cc v 1 v 2 v 3 gnd com1 to com4 seg1 to seg24 v cc 1/4 duty, 1/3 bias drive (external power supply used for v lcd ) 4 24 12-digit lcd v lcd v lcd 24 figure 91-2 examples of lcd wiring (hd404868 series) large lcd panel drive: if the capacitance of the driven lcd is large, the value of the divided resistance should be reduced by dividing the resistance in parallel with the built-in divided resistor (see figures 92-1 and 92-2). as an lcd has a matrix structure, the path of the charge/discharge current flowing to the load capacitance is complicated. moreover, the current varies depending on the illumination state, so that it is not possible to determine the resistance values simply from the lcd load capacitance. the resistance values must therefore be determined experimentally in accordance with the power consumption requirement of the equipment, including the lcd. (adding capacitors c with a value of 0.1 to 0.3 m f is also effective). a value of 1 k w to 10 k w is normally set for r.
hd404889/hd404899/hd404878/hd404868 series 147 v0(v cc ) v1 v2 v3 gnd r r r c r c c r r v0(v cc ) v1 v2 v3 gnd figure 92-1 large lcd panel drive (using power supply voltage for v lcd ) (hd404889/hd404899/hd404878 series) v1 v2 v3 gnd r r r c r c c r r v1 v2 v3 gnd figure 92-2 large lcd panel drive (using power supply voltage for v lcd ) (hd404868 series) usage notes when r3 0 /seg1 to r6 0 /seg16 pins are used as segment output pins, write their port data register (pdr) to ??
hd404889/hd404899/hd404878/hd404868 series 148 buzzer output circuit buzzer output circuit functions: the buzzer output circuit has the following functions. ? timer overflow toggle output ? system clock divided clock pulse output the block diagram of the buzzer output circuit is shown in figure 93. buzzer output circuit operation ? timer overflow toggle output operation the timer overflow toggle output operation setting is made by bits 1 and 2 of the buzzer mode register (bmr) and bit 2 of port mode register 2 (pmr2). by clearing bit 2 of the buzzer mode register (bmr) to 0, selecting timer b or timer c overflow by bit 1, and setting bit 2 of port mode register 2 (pmr2) to 1, a toggle waveform is output from the buzz pin with overflow as the trigger. ? system clock divided clock pulse output the system clock divided clock pulse output operation setting is made by bits 0 to 3 of the buzzer mode register (bmr) and bit 2 of port mode register 2 (pmr2). bit 2 of the buzzer mode register (bmr) is set to 1, the system clock division ratio is selected by bits 0 and 1, and bit 2 of port mode register 2 (pmr2) is set to 1. clock pulses are output by setting bit 3 of the buzzer mode register (bmr) to 1. if bit 3 of the buzzer mode register (bmr) is cleared to 0, the buzz pin goes low. the clock pulse width is fixed without regard to the timing set by bit 3 of the buzzer mode register (bmr), and careful coordination with software is necessary with regard to the number of output pulses. after a clock pulse modification is made, clock pulses should not be output until 4tcyc after the modifying instruction. only a bit manipulation instruction can be used on bit 3 of the buzzer mode register (bmr). buzzer output circuit registers buzzer output circuit operation setting is performed by the following registers. buzzer mode register (bmr: $02e) port mode register 2 (pmr2: $00a) buzzer mode register (bmr: $02e): the buzzer mode register (bmr) is a 4-bit write-only register used to set toggle output by timer overflow and system clock divided clock pulse output as shown in figure 94. bit 3 of the buzzer mode register (bmr) can only accessed by a bit manipulation instruction. the buzzer mode register (bmr) is reset to $0 by an mcu reset.
hd404889/hd404899/hd404878/hd404868 series 149 port mode register 2 (pmr2: $00a): port mode register 2 (pmr2) is a 4-bit write-only register used to switch the r1 2 /buzz pin function as shown in figure 30. port mode register 2 (pmr2) is reset to $0 by an mcu reset. buzz timer b overflow per 1/2 (toggle) synchro- nization circuit buzzer mode register selector internal data bus data bus clock line signal line 1/2 1/3 1/4 selector selector timer c overflow figure 93 buzzer output circuit
hd404889/hd404899/hd404878/hd404868 series 150 bit read/write initial value on reset bit name 3 w 0 bmr3 2 w 0 bmr2 1 w 0 bmr1 0 w 0 bmr0 buzzer mode register (bmr: $02e) bmr2 0 1 bmr1 bmr0 buzz pin output 0 * division by 2 of timer b overflow division by 2 of timer c overflow 1 * 0 ?er clock 0 1 ?er/2clock 0 ?er/3clock ?er/4clock 1 1 0 stopped (low level) output 1 clock output control (enabled when bmr2 = 1, bit manipulation instruction) * : don't care figure 94 buzzer mode register (bmr)
hd404889/hd404899/hd404878/hd404868 series 151 ztat tm microcomputer with built-in programmable rom 1. precautions for use of ztat tm microcomputer with built-in programmable rom (1) precautions for writing to programmable rom built in ztat tm microcomputer in the ztat tm microcomputer with built-in plastic mold one-time programmable rom, incomplete electrical connection between the prom writer and socket adapter causes writing errors and, makes the computer unoperatable. to enhance the writing efficiency, attention should be paid to the following points: (a) make sure that the socket adapter is firmly fixed to the prom writer and connected electrically with each other (neither opened nor shorted), before starting the writing process. (b) to secure the electrical connection between the contact pin and ic lead, make sure that there is no foreign substance on the contact pin of the socket adapter, which may cause improper electrical connection. (c) when inserting the ic, be careful to protect the ic lead from bending in order to secure the electrical connection between the contact pin and ic lead. if the lead is bent, correct the bending and insert it again. (d) if any trouble is noticed during a blank check to be performed to prevent erroneous writing due to improper electrical connection, carry out the writing process again according to above steps (a), (b), and (c). (e) during the writing process, do not touch the socket adapter and ic to prevent erroneous writing. (f) to write continuously in the ic, follow steps (a), (b), (c), (d) and (e). (g) if a writing error recurs, or the rate of writing errors occur frequently, stop writing and check the prom writer, socket adapter, etc. for defects. (h) if any problem is noticed in the written program or in the program after being left at a high temperature, consult our technical staff. (2) precautions when new prom writer, socket adapter or ic is used when a new prom writer, socket adapter or ic is employed, breakdown of the ic may occur or its writing may become impossible because the noise, overshoot, timing or other electrical characteristics may be inconsistent with the assured ic writing characteristics. to avoid such troubles, check the following points before starting the writing process. (a) to ensure stable writing operation, check that the v cc of the power supplied to the prom writer, power source current capacity of v pp , and current consumption at the time of writing to ic are provided with sufficient margin. (b) to prevent breakdown of the ic, check that the power source voltage between gnd-v cc and gnd- v pp , and overshoot or undershoot of the power source at the connecting terminal of the socket adapter are within the ratings. particularly, if the overshoot or undershoot exceeds the maximum rating, the p-n connection may be damaged, leading to permanent breakdown. if overshoot or undershoot occurs, recheck the power source damping resistance of capacity. (c) to prevent breakdown of the ic and for stable writing and reading operation, insert the ic into the socket adapter and check the power noise between the gnd-v cc and gnd-v pp near the ic connecting
hd404889/hd404899/hd404878/hd404868 series 152 terminal. if power source noise is noticed, insert an appropriate capacitor between the gnd power sources depending on the noise generated. in case of high frequency noise , insert a capacitor of low inductance. (d) for stable writing and reading operation, insert the ic into the socket adapter and check the input waveform, timing and noise near the r/w, cs, address and data terminals. particularly, since recent ics have increased in speed, caution should be exercised against the noise to the power source or address due to crosstalk from the output data terminal. to avoid these problems, inserting a low inductance capacitor between the gnd and power source or inserting a damping resistance to the output data terminal is effective. (e) particularly, when a multiple prom writer is used, perform above items (a), (b), (c), and (d) assuming all ics inserted into the socket adapter. (f) in the case of a multiple prom writer, when an unacceptable result is noticed during a blank check performed to prevent erroneous writing due to improper electrical connection of the power source, etc., rewriting is impossible unless every writing process can be stopped. therefore, the potential increases due to erroneous writing because of improper connection. be sure to check the electrical connection between the prom writer and socket adapter and ic. (g) if any abnormality is noticed while checking a written program, consult our technical staff. 2. programming of built-in programmable rom the mcu can stop its function as an mcu in prom mode for programming the built-in prom. prom mode is set by driving the reset , m 0 , and m 1 pins low (or by driving the reset and m 0 pins low in the hd4074869), and driving the test pin to the v pp level. writing and reading specifications of the prom are the same as those for the commercial eprom27256. using a socket adapter for specific use of each product, programming is possible with a general-purpose prom writer. since an instruction of the hmcs400 series is 10 bits long, a conversion circuit is incorporated to adapt the general-purpose prom writer. this circuit splits each instruction into five lower bits and five higher bits to write from or read to two addresses. this enables use of a general-purpose prom. for instance, to write to a 16kword of built-in prom writer with a general-purpose prom, specify 32kbyte address ($0000-$7fff). an example of prom memory map is shown in figure 95. notes: 1. when programming with a prom writer, set up each rom size to the address given in table 30. if it is programmed erroneously to an address given in table 30 or later, check of writing of prom may become impossible. particularly, caution should be exercised in the case of a plastic package since reprogramming is impossible with it. set the data in unused addresses to $ff. 2. if the indexes of the prom writer socket, socket adapter and product are not aligned precisely, the product may break down due to overcurrent. be sure to check that they are properly set to the writer before starting the writing process.
hd404889/hd404899/hd404878/hd404868 series 153 3. two levels of program voltages (v pp ) are available for the prom: 12.5v and 21v. our product employs a v pp of 12.5v. if a voltage of 21v is applied, permanent breakdown of the product will result. the v pp of 12.5v is obtained for the prom writer by setting it according to the intel 27258 specifications. table 28 socket adapters package model name manufacturer fp-80a please ask hitachi service section. tfp-80c please ask hitachi service section. fp-64a please ask hitachi service section. dp-64s please ask hitachi service section. writing/verification programming of the built-in program rom employs a high speed programming method. with this method, high speed writing is effected without voltage stress to the device or without damaging the reliability of the written data. a basic programming flow chart is shown in figure 96 and a timing chart in figure 97. for precautions for prom writing procedure, refer to section 2, "characteristics of ztat tm microcomputer's built-in programmable rom and precautions for its applications." table 29 selection of mode mode ce oe v pp o 0 to o 4 writing ?ow ?igh v pp data input verification ?igh ?ow v pp data output prohibition of programming ?igh ?igh v pp high impedance table 30 prom writer program address rom size address 8k $0000~$3fff 12k $0000~$5fff 16k $0000~$7fff
hd404889/hd404899/hd404878/hd404868 series 154 programmable rom (hd4074889, hd4074899, hd4074869) the hd4074889, hd4074899, and hd4074869 are a ztat tm microcomputers with built-in prom that can be programmed in prom mode. prom mode pin description hd4074889, hd4074899 pin no. mcu mode prom mode pin no. mcu mode prom mode fp-80a tfp-80c pin name i/o pin name i/o fp-80a tfp-80c pin name i/o pin name i/o 1av cc ? cc ?1r3 0 /seg1 i/o a 1 i 2r7 0 /an0 i/o v cc ?2r3 1 /seg2 i/o a 2 i 3r7 1 /an1 i/o v cc ?3r3 2 /seg3 i/o a 3 i 4r7 2 /an2 i/o 44 r3 3 /seg4 i/o a 4 i 5r7 3 /an3 i/o 45 r4 0 /seg5 i/o o 0 i/o 6r8 0 /an4 i/o 46 r4 1 /seg6 i/o o 1 i/o 7r8 1 /an5 i/o 47 r4 2 /seg7 i/o o 2 i/o 8av ss gnd 48 r4 3 /seg8 i/o o 3 i/o 9 test i v pp ?9r5 0 /seg9 i/o o 4 i/o 10 osc1 i v cc ?0r5 1 /seg10 i/o o 4 i/o 11 osc2 o 51 r5 2 /seg11 i/o o 3 i/o 12 gnd gnd 52 r5 3 /seg12 i/o o 2 i/o 13 x2 o 53 r6 0 /seg13 i/o o 1 i/o 14 x1 i gnd 54 r6 1 /seg14 i/o o 0 i/o 15 reset i reset i55r6 2 /seg15 i/o 16 v cc ? cc ?6r6 3 /seg16 i/o 17 d 0 / int 0 i/o a 0 i 57 seg17 o 18 d 1 /int 1 i/o 58 seg18 o 19 d 2 i/o a 5 i 59 seg19 o 20 d 3 i/o a 6 i 60 seg20 o 21 d 4 i/o a 7 i 61 seg21 o 22 d 5 i/o a 8 i 62 seg22 o 23 d 6 i/o a 9 i 63 seg23 o 24 d 7 i/o a 10 i 64 seg24 o 25 d 8 i/o a 11 i 65 seg25 o 26 d 9 i/o a 12 i 66 seg26 o 27 d 10 i/o a 13 i 67 seg27 o 28 d 11 i/o a 14 i 68 seg28 o 29 r0 0 / wu 0 i/o v cc 69 seg29 o 30 r0 1 / wu 1 i/o 70 seg30 o 31 r0 2 / wu 2 i/o 71 seg31 o 32 r0 3 / wu 3 i/o 72 seg32 o 33 r1 0 /evnb i/o 73 com1 o 34 r1 1 /evnd i/o m0 i 74 com2 o 35 r1 2 /buzz i/o m1 i 75 com3 o 36 r1 3 /tob i/o ce i 76 com4 o 37 r2 0 /toc i/o 77 v3 38 r2 1 / sck i/o oe i78v2 39 r2 2 /si/so i/o xm0 o 79 v1 v cc 40 r2 3 i/o xm1 o 80 v0 v cc
hd404889/hd404899/hd404878/hd404868 series 155 hd4074869 pin no. mcu mode prom mode pin no. mcu mode prom mode fp-64a dp-64s pin name i/o pin name i/o fp-64a dp-64s pin name i/o pin name i/o 18r7 0 /an0 i/o v cc 3340r2 3 i/o a 14 i 29r7 1 /an1 i/o v cc 3441r3 0 /seg1 i/o a 1 i 310r7 2 /an2 i/o 35 42 r3 1 /seg2 i/o a 2 i 411r7 3 /an3 i/o 36 43 r3 2 /seg3 i/o a 3 i 5 12 test i v pp 3744r3 3 /seg4 i/o a 4 i 6 13 osc1 i v cc 3845r4 0 /seg5 i/o o 0 i/o 7 14 osc2 o 39 46 r4 1 /seg6 i/o o 1 i/o 8 15 gnd gnd 40 47 r4 2 /seg7 i/o o 2 i/o 9 16 x2 o 41 48 r4 3 /seg8 i/o o 3 i/o 10 17 x1 i gnd 42 49 r5 0 /seg9 i/o o 4 i/o 11 18 reset i reset i 4350r5 1 /seg10 i/o o 4 i/o 12 19 v cc v cc 4451r5 2 /seg11 i/o o 3 i/o 13 20 d 0 / int 0 i/o a 0 i 4552r5 3 /seg12 i/o o 2 i/o 14 21 d 1 /int 1 i/o 46 53 r6 0 /seg13 i/o o 1 i/o 15 22 d 2 i/o a 5 i 4754r6 1 /seg14 i/o o 0 i/o 16 23 d 3 i/o a 6 i 4855r6 2 /seg15 i/o 17 24 d 4 i/o a 7 i 4956r6 3 /seg16 i/o 18 25 d 5 i/o a 8 i 50 57 seg17 o 19 26 d 6 i/o a 9 i 51 58 seg18 o 20 27 d 7 i/o a 10 i 52 59 seg19 o 21 28 d 8 i/o a 11 i 53 60 seg20 o 22 29 d 9 i/o a 12 i 54 61 seg21 o 23 30 r0 0 / wu 0 i/o v cc 55 62 seg22 o 24 31 r0 1 / wu 1 i/o 56 63 seg23 o 25 32 r0 2 / wu 2 i/o 57 64 seg24 o 26 33 r1 0 /evnb i/o 58 1 com1 o 27 34 r1 1 i/o a 13 i 59 2 com2 o 28 35 r1 2 /buzz i/o m0 i 60 3 com3 o 29 36 r1 3 /tob i/o ce i 61 4 com4 o 30 37 r2 0 /toc i/o xm1 o 62 5 v 3 31 38 r2 1 / sckn i/o oe i636v 2 32 39 r2 2 /si/so i/o xm0 o 64 7 v 1 v cc notes: 1. i/o: i/o pin, i: input-only pin, o: output-only pin 2. as there are two each of pins o 0 to o 4 , the respective pairs should be shorted. 3. unused data pins (o 5 to o 7 ) on the prom programmer side should be handled as shown below on the socket. v cc o 5 , o 6 , o 7 4. pin a 9 should be handled as shown below on the socket. v cc hd4074889 hd4074899 hd4074869 writer side a 9
hd404889/hd404899/hd404878/hd404868 series 156 2. pin functions in prom mode v pp : applies the on-chip prom programming voltage (12.5 v 0.3 v). ce : inputs a control signal to set the on-chip prom to the write/verify enabled state. oe : inputs a data output control signal during verification. a 0 to a 14 : on-chip prom address input pins. o 0 to o 4 : on-chip prom data bus i/o pins. as there are two each of pins o 0 to o 4 , the respective pairs should be shorted. m 0 , m 1 , reset , test: prom mode setting pins. prom mode is set by driving the m 0 , m 1 , and reset pins low (or by driving the m 0 , and reset pins low in the hd4074869), and driving the test pin to the v pp level. other pins: v cc , av cc , r7 0 /an 0 , r7 1 /an 1 , osc 1 , v 0 , and v 1 should be connected to v cc potential. gnd, av ss , and x1 should be connected to gnd potential. other pins should be left open.
hd404889/hd404899/hd404878/hd404868 series 157 $0000 1 11 1 11 vector address zero-page subroutine (64 words) pattern (4,096 words) program (16,384 words) $0001 $001f $0080 $007f $2000 $1fff $0020 $7fff bit 4 bit 8 bit 3 bit 7 bit 2 bit 6 bit 1 bit 5 bit 0 bit 9 upper three bits are not to be used (fill them with 111) upper 5 bits lower 5 bits $0000 $000f $0010 $003f $0040 $3fff $0000 $0001 $0002 $0003 $0004 $0005 $0006 $0007 $0008 $0009 $000a $000b $000c $000d $000e $000f jmpl instruction (jump to reset routine) jmpl instruction (jump to wu 0 to wu 3 jmpl instruction (jump to int 1 routine) jmpl instruction (jump to timer a routine) jmpl instruction (jump to int 0 routine) jmpl instruction (jump to timer b, timer d routine) jmpl instruction (jump to timer c routine) . . . . . . . . . jmpl instruction (jump to a/d, serial routine) $0fff $1000 figure 95 memory map in prom mode
hd404889/hd404899/hd404878/hd404868 series 158 start set prog./verify mode v pp =12.5 0.3v, v cc =6.0 0.25v address=0 n=0 n+1 ? n program t pw = 1ms 5% verify go program t opw = 3nms last address? yes no nogo set read mode v cc =5.0 0.5v, v pp =v cc 0.6v read all address go end address + 1 ? address yes n hd404889/hd404899/hd404878/hd404868 series 159 programming electrical characteristics dc characteristics (v cc = 6v 0.25v, v pp = 12.5v 0.3v, v ss = 0v, t a = 25 c 5 c, unless otherwise specified) item symbol test conditions min typ max unit input high voltage o 0 to o 4 ,a 0 to a 14 , oe , ce v ih 2.2 v cc +0.3 v input low voltage o 0 to o 4 ,a 0 to a 14 , oe , ce v il ?.3 0.8 v output high voltage o 0 to o 4 v oh i oh =?00 m a 2.4 v output low voltage o 0 to o 4 v ol i ol =1.6ma 0.4 v input leakage current o 0 to o 4 ,a 0 to a 14 , oe , ce ? i il v in =5.25v/0.5v 2 m a v cc current i cc 30ma v pp current i pp 40ma ac characteristics (v cc = 6v 0.25v, v pp = 12.5v 0.3v, t a = 25 c 5 c, unless otherwise specified) item symbol test conditions min typ max unit address setup time t as 2 m s oe setup time t oes 2 m s data setup time t ds 2 m s address hold time t ah 0 m s data hold time t dh 2 m s data output disable time t df see figure 89 130 ns v pp setup time t vps 2 m s program pulse width t pw 0.95 1.0 1.05 ms ce pulse width during overprogramming t opw 2.85 78.75 ms v cc setup time t vcs 2 m s data output delay time t oe 0 500 ns notes: input pulse level: 0.8 v to 2.2 v input rise/fall times: 20ns input timing reference levels: 1.0 v, 2.0 v output timing reference levels: 0.8 v, 2.0 v
hd404889/hd404899/hd404878/hd404868 series 160 write verify address data v pp v cc v cc v pp v cc gnd ce oe data in stable data out valid t as t ds t dh t df t ah t pw t oes t oe t opw t vps t vcs figure 97 prom write/verify timing
hd404889/hd404899/hd404878/hd404868 series 161 notes on prom programming principles of programming/erasure: a memory cell in a ztat microcomputer is the same as an eprom cell; it is programmed by applying a high voltage between its control gate and drain to inject hot electrons into its floating gate. these electrons are stable, surrounded by an energy barrier formed by an sio 2 film. the change in threshold voltage of a memory cell with a charged floating gate makes the corresponding bit appear as 0; a cell whose floating gate is not charged appears as a 1 bit (figure 98). the charge in a memory cell may decrease with time. this decrease is usually due to one of the following causes: ? ultraviolet light excites electrons, allowing them to escape. this effect is the basis of the erasure principle. ? heat excites trapped electrons, allowing them to escape. ? high voltages between the control gate and drain may erase electrons. if the oxide film covering a floating gate is defective, the electron erasure rate will be greater. however, electron erasure does not often occur because defective devices are detected and removed at the testing stage. control gate floating gate drain sio 2 source nn ++ control gate floating gate drain sio 2 source nn ++ erasure (1) write (0) figure 98 cross-sections of a prom cell prom programming: prom memory cells must be programmed under specific voltage and timing conditions. the higher the programming voltage v pp and the longer the programming pulse t pw is applied, the more electrons are injected into the floating gates. however, if v pp exceeds specifications, the pn junctions may be permanently damaged. pay particular attention to overshooting in the prom programmer. in addition, note that negative voltage noise will produce a parasitic transistor effect that may reduce breakdown voltages. the ztat microcomputer is electrically connected to the prom programmer by a socket adapter. therefore, note the following points: ? check that the socket adapter is firmly mounted on the prom programmer. ? do not touch the socket adapter or the lsi during the programming. touching them may affect the quality of the contacts, which will cause programming errors.
hd404889/hd404899/hd404878/hd404868 series 162 prom reliability after programming: in general, semiconductor devices retain their reliability, provided that some initial defects can be excluded. these initial defects can be detected and rejected by screening. baking devices under high-temperature conditions is one method of screening that can rapidly eliminate data-hold defects in memory cells. (refer to the previous principles of programming/erasure section.) ztat microcomputer devices are extremely reliable because they have been subjected to such a screening method during the wafer fabrication process, but hitachi recommends that each device be exposed to 150 c at one atmosphere for at least 48 hours after it is programmed, to ensure its best performance. the recommended screening procedure is shown in figure 99. note: if programming errors occur continuously during prom programming, suspend programming and check for problems in the prom programmer or socket adapter. if programming verification indicates errors in programming or after high-temperature exposure, please inform hitachi. note: exposure time is measured from when the temperature in the heater reaches 150 c. programming, verification exposure to high temperature, without power 150 c 10 c, 48 h +8 h 0 h * program read check v = 4.5 v or 5.5 v cc figure 99 recommended screening procedure
hd404889/hd404899/hd404878/hd404868 series 163 addressing modes ram addressing modes the mcu has three ram addressing modes, as shown in figure 100 and described below. register indirect addressing mode: the contents of the w, x, and y registers (10 bits in total) are used as a ram address. direct addressing mode: a direct addressing instruction consists of two words. the first word contains the opcode, and the contents of the second word (10 bits) are used as a ram address. memory register addressing mode: the memory registers (mr), which are located in 16 addresses from $040 to $04f, are accessed with the lamr and xmra instructions. ap 9 ap 0 w 1 y 0 w register x register y register ram address register indirect addressing ap 9 ap 0 ram address direct addressing d 9 d 0 2nd word of instruction opcode 1st word of instruction ap 9 ap 0 ram address memory register addressing m 3 opcode instruction 000100 ap 8 ap 7 ap ap 5 ap 4 6 ap 3 ap 2 ap 1 ap ap ap ap ap ap ap ap 87654321 d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 ap 8 ap 7 ap 6 ap 5 ap 4 ap 3 ap 2 ap 1 w 0 x 3 x 2 x 1 x 0 y 3 y 2 y 1 m 2 m 1 m 0 figure 100 ram addressing modes
hd404889/hd404899/hd404878/hd404868 series 164 rom addressing modes and the p instruction the mcu has four rom addressing modes, as shown in figure 101 and described below. direct addressing mode: a program can branch to any address in the rom memory space by executing the jmpl, brl, or call instruction. each of these instructions replaces the 14 program counter bits (pc 13 ?c 0 ) with 14-bit immediate data. current page addressing mode: the mcu has 64 pages of rom with 256 words per page. a program can branch to any address in the current page by executing the br instruction. this instruction replaces the eight low-order bits of the program counter (pc 7 ?c 0 ) with eight-bit immediate data. if the br instruction is on a page boundary (address 256n + 255), executing that instruction transfers the pc contents to the next physical page, as shown in figure 103. this means that the execution of the br instruction on a page boundary will make the program branch to the next page. note that the hmcs400-series cross assembler has an automatic paging feature for rom pages. zero-page addressing mode: a program can branch to the zero-page subroutine area located at $0000 $003f by executing the cal instruction. when the cal instruction is executed, 6 bits of immediate data are placed in the six low-order bits of the program counter (pc 5 ?c 0 ), and 0s are placed in the eight high- order bits (pc 13 ?c 6 ). table data addressing mode: a program can branch to an address determined by the contents of four-bit immediate data, the accumulator, and the b register by executing the tbr instruction. p instruction: rom data addressed in table data addressing mode can be referenced with the p instruction as shown in figure 102. if bit 8 of the rom data is 1, eight bits of rom data are written to the accumulator and the b register. if bit 9 is 1, eight bits of rom data are written to the r1 and r2 port output registers. if both bits 8 and 9 are 1, rom data is written to the accumulator and the b register, and also to the r1 and r2 port output registers at the same time. the p instruction has no effect on the program counter.
hd404889/hd404899/hd404878/hd404868 series 165 d 9 d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 2nd word of instruction opcode 1st word of instruction [jmpl] [brl] [call] pc 9 pc 8 pc 7 pc 6 pc 5 pc 4 pc 3 pc 2 pc 1 pc 0 pc pc pc pc 10 11 12 13 program counter direct addressing zero page addressing d 5 d 4 d 3 d 2 d 1 d 0 instruction [cal] opcode pc 98 pc 76 pc 54 pc 3 pc 1 pc 0 pc pc 10 11 12 13 program counter 00 00 0 0 0 0 pc pc pc pc pc pc 2 b 1 b 0 a 3 a 2 a 1 a 0 accumulator program counter table data addressing pc 9 pc 8 pc 7 pc 6 pc 5 pc 4 pc 3 pc 2 pc 1 pc 0 pc pc pc 10 11 12 13 b 2 b 3 b register p 3 p 0 [tbr] instruction opcode 0 0 p 2 p 1 pc opcode b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 instruction pc 90 pc pc pc 11 12 13 program counter current page addressing [br] pc 10 7 pc 6 pc 5 pc 4 pc 3 pc 2 pc 1 pc pc 8 pc p 0 p 1 p 2 p 3 figure 101 rom addressing modes
hd404889/hd404899/hd404878/hd404868 series 166 b 1 b 0 a 3 a 2 a 1 a 0 accumulator referenced rom address address designation ra 9 ra 8 ra 7 ra 6 ra 5 ra 4 ra 3 ra 2 ra 1 ra 0 ra ra ra 10 11 12 13 b 2 b 3 b register 0 0 p 3 p 0 [p] instruction opcode p 2 p 1 ra ro 9 ro 0 ro 8 ro 7 ro 6 ro 5 ro 4 ro 3 ro 2 ro 1 bbbb aa a a 3210 3210 if ro = 1 8 accumulator, b register rom data pattern output ro 9 rom data r2 3 r2 2 r2 1 r2 0 r1 3 r1 2 r1 1 r1 0 if ro = 1 9 output registers r1, r2 ro 0 ro 8 ro 7 ro 6 ro 5 ro 4 ro 3 ro 2 ro 1 figure 102 p instruction br aaa aaa nop 256 (n ?1) + 255 256n br aaa br bbb 256n + 254 256n + 255 256 (n + 1) bbb nop figure 103 branching when the branch destination is on a page boundary
hd404889/hd404899/hd404878/hd404868 series 167 instruction set the mcu series has 101 instructions, classified into the following 10 groups: ? immediate instructions ? register-to-register instructions ? ram addressing instructions ? ram register instructions ? arithmetic instructions ? compare instructions ? ram bit manipulation instructions ? rom addressing instructions ? input/output instructions ? control instructions the functions of these instructions are listed in tables 31 to 40, and an opcode map is shown in table 41. table 31 immediate instructions operation mnemonic operation code function status words/ cycles load a from immediate lai i 100011i 3 i 2 i 1 i 0 i a 1/1 load b from immediate lbi i 100000i 3 i 2 i 1 i 0 i b 1/1 load memory from immediate lmid i,d 011010i 3 i 2 i 1 i 0 d 9 d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 i m 2/2 load memory from immediate, increment y lmiiy i 101001i 3 i 2 i 1 i 0 i m, y + 1 y nz 1/1
hd404889/hd404899/hd404878/hd404868 series 168 table 32 register-register instructions operation mnemonic operation code function status words/ cycles load a from b lab 0001001000 b a 1/1 load b from a lba 0011001000 a b 1/1 load a from w law 0100000000 0000000000 w a 2/2* load a from y lay 0010101111 y a 1/1 load a from spx laspx 0001101000 spx a 1/1 load a from spy laspy 0001011000 spy a 1/1 load a from mr lamr m 100111m 3 m 2 m 1 m 0 mr (m) a 1/1 exchange mr and a xmra m 101111m 3 m 2 m 1 m 0 mr (m) a 1/1 note: the assembler automatically provides an operand for the second word of the law instruction. table 33 ram address instructions operation mnemonic operation code function status words/ cycles load w from immediate lwi i 00111100i 1 i 0 i w 1/1 load x from immediate lxi i 100010i 3 i 2 i 1 i 0 i x 1/1 load y from immediate lyi i 100001i 3 i 2 i 1 i 0 i y 1/1 load w from a lwa 0100010000 0000000000 a w 2/2* load x from a lxa 0011101000 a x 1/1 load y from a lya 0011011000 a y 1/1 increment y iy 0001011100 y + 1 y nz 1/1 decrement y dy 0011011111 y 1 y nb 1/1 add a to y ayy 0001010100 y + a y ovf 1/1 subtract a from y syy 0011010100 y a y nb 1/1 exchange x and spx xspx 0000000001 x spx 1/1 exchange y and spy xspy 0000000010 y spy 1/1 exchange x and spx, y and spy xspxy 0000000011 x spx,y spy 1/1 note: the assembler automatically provides an operand for the second word of the lwa instruction.
hd404889/hd404899/hd404878/hd404868 series 169 table 34 ram register instructions operation mnemonic operation code function status words/ cycles load a from memory lam 0010010000 m a 1/1 lamx 0010010001 m a x spx lamy 0010010010 m a y spy lamxy 0010010011 m a x spx, y spy load a from memory lamd d 0110010000 d 9 d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 m a 2/2 load b from memory lbm 0001000000 m b 1/1 lbmx 0001000001 m b x spx lbmy 0001000010 m b y spy lbmxy 0001000011 m b x spx, y spy load memory from a lma 0010010100 a m 1/1 lmax 0010010101 a m x spx lmay 0010010110 a m y spy lmaxy 0010010111 a m x spx, y spy load memory from a lmad d 0110010100 d 9 d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 a m 2/2 load memory from a, increment y lmaiy 0001010000 a m, y + 1 y nz 1/1 lmaiyx 0001010001 a m, y + 1 y x spx load memory from a, decrement y lmady 0011010000 a m, y ?1 y nb 1/1 lmadyx 0011010001 a m, y ?1 y x spx
hd404889/hd404899/hd404878/hd404868 series 170 table 34 ram register instructions (cont) operation mnemonic operation code function status words/ cycles exchange memory and a xma 0010000000 m a 1/1 xmax 0010000001 m a x spx xmay 0010000010 m a y spy xmaxy 0010000011 m a x spx, y spy exchange memory and a xmad d 0110000000 d 9 d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 m a 2/2 exchange memory and b xmb 0011000000 m b 1/1 xmbx 0011000001 m b x spx xmby 0011000010 m b y spy xmbxy 0011000011 m b x spx, y spy
hd404889/hd404899/hd404878/hd404868 series 171 table 35 arithmetic instructions operation mnemonic operation code function status words/ cycles add immediate to a ai i 101000i 3 i 2 i 1 i 0 a + i a ovf 1/1 increment b ib 0001001100 b + 1 b nz 1/1 decrement b db 0011001111 b 1 b nb 1/1 decimal adjust for addition daa 0010100110 1/1 decimal adjust for subtraction das 0010101010 1/1 negate a nega 0001100000 a + 1 a 1/1 complement b comb 0101000000 b b 1/1 rotate right a with carry rotr 0010100000 1/1 rotate left a with carry rotl 0010100001 1/1 set carry sec 0011101111 1 ca 1/1 reset carry rec 0011101100 0 ca 1/1 test carry tc 0001101111 ca 1/1 add a to memory am 0000001000 m + a a ovf 1/1 add a to memory amd d 0100001000 d 9 d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 m + a a ovf 2/2 add a to memory with carry amc 0000011000 m + a + ca a ovf ca ovf 1/1 add a to memory with carry amcd d 0100011000 d 9 d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 m + a + ca a ovf ca ovf 2/2 subtract a from memory with carry smc 0010011000 m a ca a nb ca nb 1/1 subtract a from memory with carry smcd d 0110011000 d 9 d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 m ?a ? ca a nb ca nb 2/2 or a and b or 0101000100 a b a 1/1 and memory with a anm 0010011100 a m a nz 1/1 and memory with a anmd d 0110011100 d 9 d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 a m a nz 2/2 or memory with a orm 0000001100 a m a nz 1/1 or memory with a ormd d 0100001100 d 9 d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 a m a nz 2/2 eor memory with a eorm 0000011100 a m a nz 1/1 eor memory with a eormd d 0100011100 d 9 d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 a m a nz 2/2
hd404889/hd404899/hd404878/hd404868 series 172 table 36 compare instructions operation mnemonic operation code function status words/ cycles immediate not equal to memory inem i 000010i 3 i 2 i 1 i 0 i m nz 1/1 immediate not equal to memory inemd i,d 010010i 3 i 2 i 1 i 0 d 9 d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 i m nz 2/2 a not equal to memory anem 0000000100 a m nz 1/1 a not equal to memory anemd d 0100000100 d 9 d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 a m nz 2/2 b not equal to memory bnem 0001000100 b m nz 1/1 y not equal to immediate ynei i 000111i 3 i 2 i 1 i 0 y i nz 1/1 immediate less than or equal to memory ilem i 000011i 3 i 2 i 1 i 0 i m nb 1/1 immediate less than or equal to memory ilemd i,d 010011i 3 i 2 i 1 i 0 d 9 d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 i m nb 2/2 a less than or equal to memory alem 0000010100 a m nb 1/1 a less than or equal to memory alemd d 0100010100 d 9 d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 a m nb 2/2 b less than or equal to memory blem 0011000100 b m nb 1/1 a less than or equal to immediate alei i 101011i 3 i 2 i 1 i 0 a i nb 1/1 table 37 ram bit manipulation instructions operation mnemonic operation code function status words/ cycles set memory bit sem n 00100001n 1 n 0 i m (n) 1/1 set memory bit semd n,d 01100001n 1 n 0 d 9 d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 i m (n) 2/2 reset memory bit rem n 00100010n 1 n 0 0 m (n) 1/1 reset memory bit remd n,d 01100010n 1 n 0 d 9 d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 m (n) 2/2 test memory bit tm n 00100011n 1 n 0 m (n) 1/1 test memory bit tm n,d 01100011n 1 n 0 d 9 d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 m (n) 2/2
hd404889/hd404899/hd404878/hd404868 series 173 table 38 rom address instructions operation mnemonic operation code function status words/ cycles branch on status 1 br b 1 1 b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 1 1/1 long branch on status 1 brl u 010111p 3 p 2 p 1 p 0 d 9 d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 1 2/2 long jump unconditionally jmpl u 010101p 3 p 2 p 1 p 0 d 9 d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 2/2 subroutine jump on status 1 cal a 0111a 5 a 4 a 3 a 2 a 1 a 0 1 1/2 long subroutine jump on status 1 call u 010110p 3 p 2 p 1 p 0 d 9 d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 1 2/2 table branch tbr p 001011p 3 p 2 p 1 p 0 1 1/1 return from subroutine rtn 0000010000 1/3 return from interrupt rtni 0000010001 1 ie, carry restored st 1/1 table 39 input/output instructions operation mnemonic operation code function status words/ cycles set discrete i/o latch sed 0011100100 1 d (y) 1/1 set discrete i/o latch direct sedd m 101110m 3 m 2 m 1 m 0 1 d (m) 1/1 reset discrete i/o latch red 0001100100 0 d (y) 1/1 reset discrete i/o latch direct redd m 100110m 3 m 2 m 1 m 0 0 d (m) 1/1 test discrete i/o latch td 0011100000 d (y) 1/1 test discrete i/o latch direct tdd m 101010m 3 m 2 m 1 m 0 d (m) 1/1 load a from r-port register lar m 100101m 3 m 2 m 1 m 0 r (m) a 1/1 load b from r-port register lbr m 100100m 3 m 2 m 1 m 0 r (m) b 1/1 load r-port register from a lra m 101101m 3 m 2 m 1 m 0 a r (m) 1/1 load r-port register from b lrb m 101100m 3 m 2 m 1 m 0 b r (m) 1/1 pattern generation p p 011011p 3 p 2 p 1 p 0 1/2
hd404889/hd404899/hd404878/hd404868 series 174 table 40 control instructions operation mnemonic operation code function status words/ cycles no operation nop 0000000000 1/1 start serial sts 0101001000 1/1 standby mode/watch mode* sby 0101001100 1/1 stop mode/watch mode stop 0101001101 1/1 note: only after a transition from subactive mode.
hd404889/hd404899/hd404878/hd404868 series 175 table 41 opcode map r8 l h r9 0 1 2 3 4 5 6 7 8 9 a b c d e f 0 1 2 3 4 5 6 7 8 9 a b c d e f lbi i(4) lyi i(4) lxi i(4) lai i(4) lbr m(4) lar m(4) redd m(4) lamr m(4) ai i(4) lmiiy i(4) tdd m(4) alei i(4) lrb m(4) lra m(4) sedd m(4) xmra m(4) 0 0 1 1-word/2-cycle instruction 1-word/3-cycle instruction ram direct address instruction (2-word/2-cycle) 2-word/2-cycle instruction 0123456789abcdef nop xspx xspy xspxy anem am orm lbm(xy) bnem lab ib lmaiy(x) ayy laspy iy rtn rtni alem amc eorm nega red laspx tc inem i(4) ilem i(4) ynei i(4) xma(xy) lam(xy) sem n(2) lma(xy) rem n(2) smc tm n(2) anm rotr daa das lay rotl db dy sec lba lya rec lxa blem syy sed xmb(xy) lmady(x) td lwi i(2) tbr p(4)
hd404889/hd404899/hd404878/hd404868 series 176 table 41 opcode map (cont) r8 l h r9 0 1 2 3 4 5 6 7 8 9 a b c d e f 0 1 2 3 4 5 6 7 8 9 a b c d e f 1 0 1 1-word/2-cycle instruction 1-word/3-cycle instruction ram direct address instruction (2-word/2-cycle) 2-word/2-cycle instruction 0123456789abcdef law anemd amd ormd lwa alemd amcd eormd comb or sts sby stop inemd i(4) ilemd i(4) jmpl p(4) call p(4) brl p(4) xmad lamd semd n(2) lmad remd n(2) smcd tmd n(2) anmd lmid i(4) cal a(6) br b(8) p p(4)
hd404889/hd404899/hd404878/hd404868 series 177 absolute maximum ratings item symbol value unit notes power supply voltage v cc ?.3 to +7.0 v programming voltage v pp ?.3 to +14.0 v 1 pin voltage v t ?.3 to v cc +0.3 v allowable input current (total) l 0 100 ma 2 allowable output current (total) l 0 50 ma 3 allowable input current (per pin) l 0 4 ma 4,5 30 ma 4,6 allowable output current (per pin) ? 0 4 ma 7,8 20 ma 7,9 operating temperature topr ?0 to +75 c10 storage temperature tstg ?5 to +125 c11 notes: permanent damage may occur if these maximum ratings are exceeded. normal operation must be under the conditions stated in the electrical characteristics tables. if these conditions are exceeded, the lsi may malfunction or its reliability may be affected. 1. applies to the hd4074889, hd4074899, and hd4074869 test (v pp ) pin. 2. the allowable input current (total) is the sum of all currents flowing from i/o pins to ground at the same time. 3. the allowable output current (total) is the sum of all currents flowing from v cc to i/o pins. 4. the allowable input current (per pin) is the maximum current allowed to flow from any one i/o pin to ground. 5. applies to pins d 0 to d 3 and r0 to r8. 6. applies to pins d 4 to d 11 . 7. the allowable output current (per pin) is the maximum current allowed to flow from v cc to any one i/o pin. 8. applies to pins d 4 to d 11 and r0 to r8. 9. applies to pins d 0 to d 3 . 10. the operating temperature indicates the temperature range in which power can be supplied to the lsi (voltage vcc shown in the electrical characteristics tables can be applied). 11. in the case of chips, the storage specification differs from that of the package products. please consult your hitachi sales representative for details.
hd404889/hd404899/hd404878/hd404868 series 178 electrical characteristics dc characteristics (hd404888, hd4048812, hd404889, hd404898, hd4048912, hd404899, hd404874, hd404878, hd404864, hd404868: v cc =1.8v to 5.5v, gnd=0v, t a =?0 c to +75 c; hcd404889, hcd404899, hcd404878: v cc =1.8v to 5.5v, gnd=0v, ta=+75 c; hd4074889, hd4074899, hd4074869: v cc =2.0v to 5.5v, gnd=0v, t a =?0 c to +75 c, unless otherwise specified) item symbol pins min. typ. max. unit test conditions notes input high voltage v ih reset , sck , si, int 0 ,int 1 , wu 0 to wu 3 , evnb, evnd 0.90v cc ? cc +0.3 v osc 1 v cc ?.3 v cc +0.3 v external clock operation input low voltage v il reset , sck , si, int 0 ,int 1 , wu 0 to wu 3 , evnb, evnd ?.3 0.10v cc v osc 1 ?.3 0.3 v external clock operation output high voltage v oh sck ,so, buzz, tob, toc v cc ?.5 v i oh =0.3ma output low voltage v ol sck ,so, buzz, tob, toc 0.4 v i ol =0.4ma i/o leakage current | i il | reset , sck , si, int 0 , int 1 , wu 0 to wu 3 , evnb, evnd, osc 1 , tob, toc, so, buzz 1 m av in =0v to v cc 1 active mode l cc1 v cc 3.0 5.0 ma v cc =5v, f osc =4mhz 2 current dissipation l cc2 0.4 1.0 ma v cc =3v, f osc =800khz 2 standby mode current dissipation l sby1 v cc 1.0 2.0 ma v cc =5v, f osc =4mhz, lcd on 3 l sby2 0.3 0.6 ma v cc =3v, f osc =800khz lcd on 3 subactive mode current dissipation l sub v cc (hd404888, hd4048812, hd404889, hcd404889, hd404898, hd4048912, hd404899, hcd404899, hd404874, hd404878, hcd404878, hd404864, hd404868) ?560 m av cc = 3v, lcd on, 32 khz oscillator used 4,5 v cc (hd4074889, hd4074899, hd4074869) 70 120 m a 4,5
hd404889/hd404899/hd404878/hd404868 series 179 item symbol pins min. typ. max. unit test conditions notes watch mode current dissipation l wtc1 v cc ?530 m av cc = 3 v, lcd on, 32 khz oscillator used 4,5 l wtc2 v cc ?8 m av cc = 3 v, lcd off, 32 khz oscillator used 5 stop mode current dissipation l stop v cc 5 m av cc = 3 v, no 32 khz oscillator 5 stop mode retention voltage v stop v cc 1.5 v no 32 khz oscillator 6 notes: 1. excludes output buffer current. 2. power supply current when the mcu is in the reset state and there are no i/o currents. test conditions mcu state ? reset state pin states ? reset , test: at ground 3. power supply current when the on-chip timers are operating and there are no i/o currents. test conditions mcu state ? i/o: same as reset state ? standby mode ? f cyc = f osc /4 pin states ? reset : at v cc ? test: at ground ? d 0 to d 11 , r 0 to r 8 : at v cc 4. applies when the lcd power supply dividing resistor is connected. 5. power supply current when there are no i/o currents. test conditions pin states ? reset : at v cc ? test: at ground ? d 0 to d 11 , r 0 to r 8 : at v cc 6. voltage needed to retain ram data.
hd404889/hd404899/hd404878/hd404868 series 180 i/o characteristics for standard pins (hd404888, hd4048812, hd404889, hd404898, hd4048912, hd404899, hd404874, hd404878, hd404864, hd404868: v cc =1.8v to 5.5v, gnd=0v, t a =?0 c to +75 c; hcd404889, hcd404899, hcd404878: v cc =1.8v to 5.5v, gnd=0v, ta=+75 c; hd4074889, hd4074899, hd4074869: v cc =2.0v to 5.5v, gnd=0v, t a =?0 c to +75 c, unless otherwise specified) item symbol pins min. typ. max. unit test conditions notes input high voltage v ih r0 to r8 0.7v cc ? cc +0.3 v 1 r0 to r7 2 input low voltage v il r0 to r8 ?.3 0.3v cc v1 r0 to r7 2 output high voltage v oh r0 to r8 v cc ?.5 v i oh =0.3ma 1 r0 to r7 2 output low voltage v ol r0 to r8 0.4 v i ol =0.4ma 1 r0 to r7 2 i/o leakage current | i il | r0 to r8 1 m av in =0v to v cc 1, 3 r0 to r7 2, 3 mos pull-up current ? pu r0 to r8 10 50 150 m av cc =3v, v in =0v 1 r0 to r7 2 notes: 1. applies to the hd404889, hd404899, and hd404878 series. 2. applies to the hd404868 series. 3. excludes the current flowing in the output buffer.
hd404889/hd404899/hd404878/hd404868 series 181 i/o characteristics for high-current pins (hd404888, hd4048812, hd404889, hd404898, hd4048912, hd404899, hd404874, hd404878, hd404864, hd404868: v cc =1.8v to 5.5v, gnd=0v, t a =?0 c to +75 c; hcd404889, hcd404899, hcd404878: v cc =1.8v to 5.5v, gnd=0v, ta=+75 c; hd4074889, hd4074899, hd4074869: v cc =2.0v to 5.5v, gnd=0v, t a =?0 c to +75 c, unless otherwise specified) item symbol pins min. typ. max. unit test conditions notes input high voltage v ih d 0 to d 11 0.7v cc ? cc +0.3 v 1 d 0 to d 9 2 input low voltage v il d 0 to d 11 ?.3 0.3v cc v1 d 0 to d 9 2 output high voltage v oh d 4 to d 11 v cc ?.5 v i oh =0.3ma 1 d 4 to d 9 2 d 0 to d 3 v cc ?.0 v i oh =10ma, v cc =4.5 to 5.5v output low voltage v ol d 0 to d 3 0.4 v i ol =0.4ma d 4 to d 11 2.0 v i ol =15ma 1 d 4 to d 9 v cc =4.5v to 5.5v 2 i/o leakage current | i il |d 0 to d 11 1 m av in =0v to v cc 1, 3 d 0 to d 9 2, 3 mos pull-up current ? pu d 0 to d 11 10 50 150 m av cc =3v, v in =0v 1 d 0 to d 9 2 notes: 1. applies to the hd404889, hd404899, and hd404878 series. 2. applies to the hd404868 series. 3. excludes the current flowing in the output buffer.
hd404889/hd404899/hd404878/hd404868 series 182 lcd circuit characteristics (hd404888, hd4048812, hd404889, hd404898, hd4048912, hd404899, hd404874, hd404878, hd404864, hd404868: v cc =1.8v to 5.5v, gnd=0v, t a = ?0 c to +75 c; hcd404889, hcd404899, hcd404878: v cc =1.8v to 5.5v, gnd=0v, ta=+75 c; hd4074889, hd4074899, hd4074869: v cc =2.0v to 5.5v, gnd=0v, t a =?0 c to +75 c, unless otherwise specified) item symbol pins min. typ. max. unit test conditions notes segment driver voltage drop v ds seg1 to seg32 0.6 v i d =3 m a v 1 =2.7 to 5.5v 1, 2 seg1 to seg24 1, 3 common driver voltage drop v dc com1 to com4 0.3 v i d =3 m a v 1 =2.7 to 5.5v 1 lcd power supply dividing resistance r w 50 300 900 k w v 1 -gnd lcd voltage v lcd v 1 2.2 v cc v 4, 5 notes: 1. the voltage drop from power supply pins v 1 , v 2 , v 3 , and gnd to each segment pin or each common pin. 2. applies to the hd404889, hd404899, and hd404878 series. 3. applies to the hd404868 series. 4. in the hd404889, hd404899, and hd404878 series, when v lcd is supplied by the internal power supply, v 0 and v 1 should be shorted. when v lcd is supplied by an external power supply, the relationship v cc v lcd 2.2 v should be maintained. in this case, the v 0 pin should be fixed at v cc . 5. in the hd404868 series, when v lcd is supplied by an external power supply, the relationship v cc v lcd 2.2 v should be maintained.
hd404889/hd404899/hd404878/hd404868 series 183 a/d converter characteristics (hd404888, hd4048812, hd404889: v cc =1.8v to 5.5v, gnd=0v, t a =?0 c to +75 c; hcd404889: v cc =1.8v to 5.5v, gnd=0v, ta=+75 c; hd4074889: v cc =2.0v to 5.5v, gnd=0v, t a =?0 c to +75 c, unless otherwise specified) item symbol pins min. typ. max. unit test conditions notes analog power supply voltage av cc av cc v cc ?.3 v cc v cc +0.3 v 1 analog input voltage av in an 0 to an 5 av ss ?v cc v av cc -av ss current i ad 500 m av cc =av cc =5.0v analog input capacitance ca in an 0 to an 5 ?5pf resolution 8 bit number of inputs 0 6 channel absolute accuracy 2.0 lsb v cc =av cc =2.7v to 5.5v 3.0 lsb v cc =av cc =1.8v to 2.7v 2 conversion time 65 125 t cyc input impedance an 0 to an 5 1m w notes: 1. connect to the v cc pin when the a/d converter is not used. the av cc setting ranges are 1.8 v av cc 5.5v (hd404888, hd4048812, hd404889, hcd404889) and 2.0v av cc 5.5v (hd4074889) 2. the conversion time is 125tcyc.
hd404889/hd404899/hd404878/hd404868 series 184 (hd404898, hd4048912, hd404899: v cc =1.8v to 5.5v, gnd=0v, t a =?0 c to +75 c; hcd404899: v cc =1.8v to 5.5v, gnd=0v, ta=+75 c; hd4074899: v cc =2.0v to 5.5v, gnd=0v, t a =?0 c to +75 c, unless otherwise specified) item symbol pins min. typ. max. unit test conditions notes analog power supply voltage av cc av cc v cc ?.3 v cc v cc +0.3 v 1 analog input voltage av in an 0 to an 5 av ss ?v cc v av cc -av ss current i ad 500 m av cc =av cc =5.0v analog input capacitance ca in an 0 to an 5 ?5pf resolution 10 bit number of inputs 0 6 channel conversion time 125 t cyc v cc = av cc = 1.8 v to less than 2.0 v 2 65 125 t cyc v cc =av cc =2.0 v to 5.5v absolute accuracy 4.0 lsb input impedance an 0 to an 5 1m w notes: 1. connect to the v cc pin when the a/d converter is not used. the av cc setting ranges are 1.8 v av cc 5.5v (hd404898, hd4048912, hd404899, hcd404899) and 2.0v av cc 5.5v (hd4074899) 2. applies to hd404898, hd4048912, hd404899, and hcd404899. (hd404864, hd404868: v cc =1.8v to 5.5v, gnd=0v, t a =?0 c to +75 c; hd4074869: v cc =2.0v to 5.5v, gnd=0v, t a =?0 c to +75 c) item symbol pins min. typ. max. unit test conditions notes analog input voltage av in an 0 to an 3 gnd v cc v analog input capacitance ca in an 0 to an 3 ?5pf resolution 10 bit number of inputs 0 4 channel absolute accuracy 4.0 lsb conversion time 125 t cyc v cc = 1.8 v to less than 2.0 v 1 65 125 t cyc v cc = 2.0 v to 5.5v input impedance an 0 to an 3 1m w note: 1. applies to hd404864 and hd404868.
hd404889/hd404899/hd404878/hd404868 series 185 ac characteristics (hd404888, hd4048812, hd404889, hd404898, hd4048912, hd404899, hd404874, hd404878, hd404864, hd404868: v cc =1.8v to 5.5v, gnd=0v, t a =?0 c to +75 c;, hcd404889, hcd404899, hcd404878: v cc =1.8v to 5.5v, gnd=0v, ta=+75 c; hd4074889, hd4074899, hd4074869: v cc =2.0v to 5.5v, gnd=0v, t a =?0 c to +75 c, unless otherwise specified) item symbol pins min. typ. max. unit test conditions notes clock oscillation f osc osc 1 , osc 2 0.4 4.5 mhz division by 4 1 frequency x1,x2 32.768 khz instruction cycle time t cyc 0.89 10 m s division by 4 t subcyc 244.14 m s 32 khz oscillator used, division by 8 122.07 m s 32 khz oscillator used, division by 4 oscillation settling time(external clock and ceramic oscillator) t rc osc 1 , osc 2 7.5 ms 2 oscillation settling t rc osc 1 , osc 2 30 ms v cc =2.0 to 5.5v 2 time(crystal oscillator) x1,x2 2 s t a =?0 to +60 c2 external clock high- level width t cph osc 1 105 ns f osc =4mhz 3 external clock low- level width t cpl osc 1 105 ns f osc =4mhz 3 external clock rise time t cpr osc 1 20 ns f osc =4mhz 3 external clock fall time t cpf osc 1 20 ns f osc =4mhz 3 int 0 to int 1 , evnb,evnd, wu 0 to wu 3 high-level width t ih int 0 to int 1 , evnb,evnd, wu 0 to wu 3 2t cyc /t subcyc 4 int 0 to int 1 , evnb,evnd, wu 0 to wu 3 low-level width t il int 0 to int 1 , evnb,evnd, wu 0 to wu 3 2t cyc /t subcyc 4 reset low-level width t rstl reset 2t cyc 5 reset rise time t rstr reset 20 ms 5 input capacitance c in all input pins except test 15 pf f=1mhz,v in =0v test (hd404888, hd4048812, hd404889, hcd404889, hd404899, hd404898, hd4048912, hcd404899, hd404874, hd404878, hcd404878, hd404864, hd404868) 15 pf test (hd4074889, hd4074899, hd4074869) 40 pf
hd404889/hd404899/hd404878/hd404868 series 186 notes: 1. when the subsystem oscillator (32.768 khz crystal oscillation) is used, use within the range 0.4 mhz f osc 1.0 mhz or 1.6 mhz f osc 4.5 mhz. the ssr1 bit of the system clock select register (ssr) should be set to 0 and 1, respectively. 2. the oscillation settling time is defined as follows: (1) the time required for the oscillation to settle after v cc has reached min. at power-on. (2) the time required for the oscillation to settle after reset input has gone low when stop mode is cleared. to ensure enough time for the oscillation to settle at power-on hold the reset input low for at least time t rc . the oscillation settling time will depend on the circuit constants and stray capacitance. the resonator should be determined in consultation with the resonator manufacturer. with regard to the system clock (osc 1 , osc 2 ), bits mis1 and mis0 in the miscellaneous register (mis) should be set according to the oscillation settling time of the resonator used. 3. see figure 104. 4. see figure 105. 5. see figure 106. serial interface timing characteristics (hd404888, hd4048812, hd404889, hd404898, hd4048912, hd404899, hd404874, hd404878, hd404864, hd404868: v cc =1.8v to 5.5v, gnd=0v, t a =?0 c to +75 c;, hcd404889, hcd404899, hcd404878: v cc =1.8v to 5.5v, gnd=0v, ta=+75 c; hd4074889, hd4074899, hd4074869: v cc =2.0v to 5.5v, gnd=0v, t a =?0 c to +75 c, unless otherwise specified) item symbol pins min. typ. max. unit test conditions notes serial clock cycle time t scyc sck 1t cyc see load in figure 108 1 serial clock high-level width t sckh sck 0.4 t scyc see load in figure 108 1 serial clock low-level width t sckl sck 0.4 t scyc see load in figure 108 1 serial clock rise time t sc kr sck 100 ns see load in figure 108 1 serial clock fall time t sckf sck 100 ns see load in figure 108 1 serial output data delay time t dso so 300 ns see load in figure 108 1 serial input data setup time t ssi si 200 ns 1 serial input data hold time t hsi si 200 ns 1
hd404889/hd404899/hd404878/hd404868 series 187 during serial clock input item symbol pins min. typ. max. unit test conditions notes serial clock cycle time t scyc sck 1t cyc 1 serial clock high-level width t sckh sck 0.4 t scyc 1 serial clock low-level width t sckl sck 0.4 t scyc 1 serial clock rise time t sc kr sck 100 ns 1 serial clock fall time t sckf sck 100 ns 1 serial output data delay time t dso so 300 ns see load in figure 108 1 serial input data setup time t ssi si 200 ns 1 serial input data hold time t hsi si 200 ns 1 note: 1. see figure 107. 1/f cp 0.3v v cc -0.3v t cpl t cph t cpr t cpf osc 1 figure 104 external clock input waveform 0.9v cc 0.1v cc t ih t il int 0 , int 1 , evnb, evnd, wu 0 to wu 3 figure 105 interrupt timing
hd404889/hd404899/hd404878/hd404868 series 188 0.9v cc 0.1v cc t rstl t rstr reset figure 106 reset timing sck so si t sck f v cc ?.5v(0.9v cc )* 0.4v(0.1v cc )* t scyc t sckr t sckl t dos t t sckh t hsi t ssi v cc ?.5v 0.4v 0.9v cc 0.1v cc note : v cc ?.5v and 0.4v are the voltages during serial clock output. 0.9 v cc and 0.1 v cc are the voltages during serial clock input. figure 107 serial interface timing
hd404889/hd404899/hd404878/hd404868 series 189 v cc test point r 1 =2.6k r=12k c=30pf 1s2074(h) or equivalent figure 108 timing load circuit
hd404889/hd404899/hd404878/hd404868 series 190 package dimensions hitachi code jedec eiaj weight (reference value) fp-80a conforms 1.2 g unit: mm *dimension including the plating thickness base material dimension 60 0 ?8 0.10 0.12 m 17.2 0.3 41 61 80 1 20 40 21 17.2 0.3 *0.32 0.08 0.65 3.05 max 1.6 0.8 0.3 14 2.70 *0.17 0.05 0.10 +0.15 ?.10 0.83 0.30 0.06 0.15 0.04 hitachi code jedec eiaj weight (reference value) tfp-80c conforms 0.4 g unit: mm *dimension including the plating thickness base material dimension 0.10 m 0.10 0.5 0.1 0 ?8 1.20 max 14.0 0.2 0.5 12 14.0 0.2 60 41 120 80 61 21 40 *0.17 0.05 1.0 *0.22 0.05 0.10 0.10 1.00 1.25 0.20 0.04 0.15 0.04
hd404889/hd404899/hd404878/hd404868 series 191 hitachi code jedec eiaj weight (reference value) fp-64a conforms 1.2 g unit: mm *dimension including the plating thickness base material dimension 0.10 0.15 m 17.2 0.3 48 33 49 64 1 16 32 17 17.2 0.3 0.35 0.06 0.8 3.05 max 14 2.70 0 e 8 1.6 0.8 0.3 *0.17 0.05 0.10 +0.15 e0.10 1.0 *0.37 0.08 0.15 0.04 hitachi code jedec eiaj weight (reference value) dp-64s ? conforms 8.8 g unit: mm 0.25 + 0.11 e 0.05 0 e 15 1.78 0.25 0.48 0.10 0.51 min 2.54 min 5.08 max 19.05 57.6 58.5 max 1.0 1 33 32 64 17.0 18.6 max 1.46 max
hd404889/hd404899/hd404878/hd404868 series 192 note on rom ordering please note the following when ordering hd404888, hd4048812, hd404898 or hd4048912 rom. when ordering rom, please fill the "not used" areas below with all-1 data, to give the same amount of data as for the 16-kwords version (hd404889, hd404899). the program that converts rom data to mask drawing data is the same as that used for the 16-kwords version, and therefore the same amount of data is necessary. this applies both to orders using eprom and orders using data transmission. vector addresses program and pattern area (8,192 words) vector addresses zero page subroutine area (64 words) zero page subroutine area (64 words) program and pattern area (12,288 words) not used not used 8-kword rom version: hd404888, hd404898 write all-1 data to addresses $2000 to $3fff. 12-kword rom version: hd4048812, hd4048912 write all-1 data to addresses $3000 to $3fff. $0000 $000f $0010 $003f $0040 $1fff $2000 $3fff $3fff $0000 $000f $0010 $003f $0040 $2fff $3000 note : write all-1 data in shaded areas.
hd404889/hd404899/hd404878/hd404868 series 193 note on rom ordering please note the following when ordering hd404874 or hd404864 rom. when ordering rom, please fill the "not used" areas below with all-1 data, to give the same amount of data as for the 8-kwords version (hd404878, hd404868). the program that converts rom data to mask drawing data is the same as that used for the 8-kwords version, and therefore the same amount of data is necessary. this applies both to orders using eprom and orders using data transmission. vector addresses program and pattern area (4,096 words) zero page subroutine area (64 words) not used 4-kword rom version: hd404874, hd404864 write all-1 data to addresses $1000 to $1fff. $0000 $000f $0010 $003f $0040 $0fff $1000 $1fff note : write all-1 data in shaded areas.
hd404889/hd404899/hd404878/hd404868 series 194 option list hd404888, hd4048812, hd404889, hcd404889 please check off the appropriate applications and enter the necessary information. date of order year month day customer department name rom code name lsi number (hitachi entry) 1. rom size q hd404888 8 kwords q hd4048812 12 kwords q hd404889 16 kwords q hcd404889 16 kwords 2. function options * q 32 khz cpu operation, realtime clock time base * q no 32 khz cpu operation, realtime clock time base q no 32 khz cpu operation, no realtime clock time base note: when an asterisked item is selected, "crystal resonator" is necessary for subsystem oscillator (x1 x2). 3. rom code data organization for a microcomputer with eprom mounted (including a ztat microcomputer), specify the combined upper/lower type. q combined lower/upper type both the lower 5 data bits (l) and the upper 5 data bits (u) are written to a single eprom in the order lululu... q separate lower/upper type the lower 5 data bits (l) and upper 5 data bits (u) are written to separate eproms respectively. 4. system oscillator (osc1-osc2) q ceramic oscillator f = mhz q crystal oscillator f = mhz q external clock f = mhz
hd404889/hd404899/hd404878/hd404868 series 195 5. subsystem oscillator (x1 x2) 6. stop mode 7. package q not used q yes (used) q fp-80a q crystal resonator f = 32.768 khz q no (not used) q tfp-80c q chip note: the specifications of shipped chips differ from those of the package product. please contact our sales staff for details.
hd404889/hd404899/hd404878/hd404868 series 196 option list hd404898, hd4048912, hd404899, hcd404899 please check off the appropriate applications and enter the necessary information. date of order year month day customer department name rom code name lsi number (hitachi entry) 1. rom size q hd404898 8 kwords q hd4048912 12 kwords q hd404899 16 kwords q hcd404899 16 kwords 2. function options * q 32 khz cpu operation, realtime clock time base * q no 32 khz cpu operation, realtime clock time base q no 32 khz cpu operation, no realtime clock time base note: when an asterisked item is selected, "crystal resonator" is necessary for subsystem oscillator (x1 x2). 3. rom code data organization for a microcomputer with eprom mounted (including a ztat microcomputer), specify the combined upper/lower type. q combined lower/upper type both the lower 5 data bits (l) and the upper 5 data bits (u) are written to a single eprom in the order lululu... q separate lower/upper type the lower 5 data bits (l) and upper 5 data bits (u) are written to separate eproms respectively. 4. system oscillator (osc1-osc2) q ceramic oscillator f = mhz q crystal oscillator f = mhz q external clock f = mhz
hd404889/hd404899/hd404878/hd404868 series 197 5. subsystem oscillator (x1 x2) 6. stop mode 7. package q not used q yes (used) q fp-80a q crystal resonator f = 32.768 khz q no (not used) q tfp-80c q chip note: the specifications of shipped chips differ from those of the package product. please contact our sales staff for details.
hd404889/hd404899/hd404878/hd404868 series 198 option list hd404874, hd404878, hcd404878 please check off the appropriate applications and enter the necessary information. date of order year month day customer department name rom code name lsi number (hitachi entry) 1. rom size q hd404874 4 kwords q hd404878 8 kwords q hcd404878 8 kwords 2. function options * q 32 khz cpu operation, realtime clock time base * q no 32 khz cpu operation, realtime clock time base q no 32 khz cpu operation, no realtime clock time base note: when an asterisked item is selected, "crystal resonator" is necessary for subsystem oscillator (x1 x2). 3. rom code data organization for a microcomputer with eprom mounted (including a ztat microcomputer), specify the combined upper/lower type. q combined lower/upper type both the lower 5 data bits (l) and the upper 5 data bits (u) are written to a single eprom in the order lululu... q separate lower/upper type the lower 5 data bits (l) and upper 5 data bits (u) are written to separate eproms respectively. 4. system oscillator (osc1-osc2) q ceramic oscillator f = mhz q crystal oscillator f = mhz q external clock f = mhz 5. subsystem oscillator (x1 x2) 6. stop mode 7. package q not used q yes (used) q fp-80a q crystal resonator f = 32.768 khz q no (not used) q tfp-80c q chip note: the specifications of shipped chips differ from those of the package product. please contact our sales staff for details.
hd404889/hd404899/hd404878/hd404868 series 199 option list hd404864, hd404868 please check off the appropriate applications and enter the necessary information. date of order year month day customer department name rom code name lsi number (hitachi entry) 1. rom size q hd404864 4 kwords q hd404868 8 kwords 2. function options * q 32 khz cpu operation, realtime clock time base * q no 32 khz cpu operation, realtime clock time base q no 32 khz cpu operation, no realtime clock time base note: when an asterisked item is selected, "crystal resonator" is necessary for subsystem oscillator (x1 x2). 3. rom code data organization for a microcomputer with eprom mounted (including a ztat microcomputer), specify the combined upper/lower type. q combined lower/upper type both the lower 5 data bits (l) and the upper 5 data bits (u) are written to a single eprom in the order lululu... q separate lower/upper type the lower 5 data bits (l) and upper 5 data bits (u) are written to separate eproms respectively. 4. system oscillator (osc1-osc2) q ceramic oscillator f = mhz q crystal oscillator f = mhz q external clock f = mhz 5. subsystem oscillator (x1 x2) 6. stop mode 7. package q not used q yes (used) q fp-64a q crystal resonator f = 32.768 khz q no (not used) q dp-64s
hd404889/hd404899/hd404878/hd404868 series 200 cautions 1. hitachi neither warrants nor grants licenses of any rights of hitachi? or any third party? patent, copyright, trademark, or other intellectual property rights for information contained in this document. hitachi bears no responsibility for problems that may arise with third party? rights, including intellectual property rights, in connection with use of the information contained in this document. 2. products and product specifications may be subject to change without notice. confirm that you have received the latest product standards or specifications before final design, purchase or use. 3. hitachi makes every attempt to ensure that its products are of high quality and reliability. however, contact hitachi? sales office before using the product in an application that demands especially high quality and reliability or where its failure or malfunction may directly threaten human life or cause risk of bodily injury, such as aerospace, aeronautics, nuclear power, combustion control, transportation, traffic, safety equipment or medical equipment for life support. 4. design your application so that the product is used within the ranges guaranteed by hitachi particularly for maximum rating, operating supply voltage range, heat radiation characteristics, installation conditions and other characteristics. hitachi bears no responsibility for failure or damage when used beyond the guaranteed ranges. even within the guaranteed ranges, consider normally foreseeable failure rates or failure modes in semiconductor devices and employ systemic measures such as fail- safes, so that the equipment incorporating hitachi product does not cause bodily injury, fire or other consequential damage due to operation of the hitachi product. 5. this product is not designed to be radiation resistant. 6. no one is permitted to reproduce or duplicate, in any form, the whole or part of this document without written approval from hitachi. 7. contact hitachi? sales office for any questions regarding this document or hitachi semiconductor products. hitachi, ltd. semiconductor & integrated circuits. nippon bldg., 2-6-2, ohte-machi, chiyoda-ku, tokyo 100-0004, japan tel: tokyo (03) 3270-2111 fax: (03) 3270-5109 copyright ?hitachi, ltd., 1998. all rights reserved. printed in japan. hitachi asia pte. ltd. 16 collyer quay #20-00 hitachi tower singapore 049318 tel: 535-2100 fax: 535-1533 url northamerica : http:semiconductor.hitachi.com/ europe : http://www.hitachi-eu.com/hel/ecg asia (singapore) : http://www.has.hitachi.com.sg/grp3/sicd/index.htm asia (taiwan) : http://www.hitachi.com.tw/e/product/sicd_frame.htm asia (hongkong) : http://www.hitachi.com.hk/eng/bo/grp3/index.htm japan : http://www.hitachi.co.jp/sicd/index.htm hitachi asia ltd. taipei branch office 3f, hung kuo building. no.167, tun-hwa north road, taipei (105) tel: <886> (2) 2718-3666 fax: <886> (2) 2718-8180 hitachi asia (hong kong) ltd. group iii (electronic components) 7/f., north tower, world finance centre, harbour city, canton road, tsim sha tsui, kowloon, hong kong tel: <852> (2) 735 9218 fax: <852> (2) 730 0281 telex: 40815 hitec hx hitachi europe ltd. electronic components group. whitebrook park lower cookham road maidenhead berkshire sl6 8ya, united kingdom tel: <44> (1628) 585000 fax: <44> (1628) 778322 hitachi europe gmbh electronic components group dornacher stra? 3 d-85622 feldkirchen, munich germany tel: <49> (89) 9 9180-0 fax: <49> (89) 9 29 30 00 hitachi semiconductor (america) inc. 179 east tasman drive, san jose,ca 95134 tel: <1> (408) 433-1990 fax: <1>(408) 433-0223 for further information write to:

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