april 2008 rev 2 1/8 8 ESDA18-1F2 transil?, transient voltage suppressor features stand-off voltage 16v unidirectional device low clamping factor v cl /v br fast response time very thin package: 0.65 mm complies with the following standards iec 61000-4-2 level 4 ? 15 kv (air discharge) ? 8 kv (contact discharge) description the ESDA18-1F2 is a single line transil diode designed specifically for the protection of integrated circuits into portable equipment and miniaturized electronics devices subject to esd and eos transient overvoltages. figure 1. pin configuration (bump side) tm: transil is a trademark of stmicroelectronics. flip chip (4 bumps) b 1 2 k k a a a ka www.st.com
characteristics ESDA18-1F2 2/8 1 characteristics table 1. absolute ratings (limiting value, per diode) symbol parameter and test conditions value unit p pp peak pulse power dissipation 10 / 1000 s pulse t j initial = t amb 100 w peak pulse power dissipation 8 / 20 s pulse 700 i fsm non repetitive surge peak forward current t p =10 ms t j initial = t amb 8a t j maximum operating junction temperature 125 c t stg storage temperature range - 65 to + 175 c table 2. electrical characteristics (t amb = 25 c) symbol parameter v br breakdown voltage i rm leakage current v rm stand-off voltage v cl clamping voltage r d dynamic impedance i pp peak pulse current c capacitance order number v br i r i rm v rm v cl i pp (1) 1. 8 / 20 s pulse waveform. v f (2) 2. a dc current is not recommended for more than 5 sec. even if transil failure m ode is short circuit the bumps could exceed melting temperature and the component disassembled from the board. tc min. max. max. max. max. max. typ. i f = 850 ma v r =0 v vvmaav v a v 10 -4 /c pf ESDA18-1F2 16 18 1 0.5 10 20 1 1.3 8.5 230 v i v cl v br v rm i f v f i rm i pp slope: 1/r d
ESDA18-1F2 characteristics 3/8 figure 2. relative variation of peak pulse power versus initial junction temperature figure 3. peak pulse power versus exponential pulse duration 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 0 25 50 75 100 125 150 p [t initial] / p [t initial=25c) pp j pp j t (c) j 10 100 1000 10000 1 10 100 1000 p (w) pp t (s) p t initial=25c j figure 4. clamping voltage versus peak pulse current (typical values, exponential waveform) figure 5. forward voltage drop versus peak forward current (typical values) 0.1 1.0 10.0 100.0 10 12 14 16 18 20 22 24 26 28 30 i (a) pp v (v) cl 8/20s t initial=25c j 1.e-03 1.e-02 1.e-01 1.e+00 1.e+01 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 i (a) fm v (v) fm t =25c j t =125c j figure 6. junction capacitance versus reverse voltage applied (typical values) figure 7. relative variation of leakage current versus junction temperature (typical values) 0 50 100 150 200 250 300 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 c(pf) f=1mhz v =30mv t =25c osc rms j v (v) r 1 10 100 25 50 75 100 125 i [t ] / i [t =25c] rj rj t (c) j v =10v r
application information ESDA18-1F2 4/8 2 application information one major point is that the ESDA18-1F2 has to ensure the safety during reverse battery operation. indeed, during this operation the device must clamp the dc reverse voltage below 1.3 v @ 0.85 a (max current). thus reverse battery operation has been simulated by inverting the polatrity of the transil (please see figures 8 and 9) figure 8. reverse battery operation setup figure 9. reverse battery operation results a short calculation based on reverse battery operation results figures clearly show that in such real phone application the ESDA18-1F2 clamp the dc voltage below 1.3 v. typically the ESDA18-1F2 can clamp the dc voltage @ 0.9 v @ 0.76 a dc current: ptc 1 nf 4.7 k equivalent mobile phone impedance ESDA18-1F2 v v mains i v dc 2v max ---------------------- - 21.4 3.14 ----------------- 0.9v ? = i dc 2i max -------------------- - 21.2 3.14 ----------------- 0.76a ? =
ESDA18-1F2 ordering information scheme 5/8 3 ordering information scheme figure 10. ordering information scheme 4 packing information in order to meet environmental requirements, st offers these devices in ecopack ? packages. these packages have a lead-free second level interconnect. the category of second level interconnect is marked on the inner box label, in compliance with jedec standard jesd97. the maximum ratings related to soldering conditions are also marked on the inner box label. ecopack is an st trademark. ecopack specifications are available at www.st.com . figure 11. flip chip package dimensions esda 18 - 1 fx esd array number of line package breakdown voltage 18 = 18 volts max. 1 = signle line f = flip chip x = 2: lead-free, pitch = 500 m, bump = 315 m 0.92 mm 30 m 0.92 mm 30 m 315 m 50 500 m 50 225 m 225 m 500 m 50 650 m 65
packing information ESDA18-1F2 6/8 figure 14. flip chip tape and reel specification note: more packing information is av ailable in the application notes: an1235: ?flip chip: package description and recommendations for use? an1751: "emi filters: recommendations and measurements" figure 12. footprint recommendations figure 13. marking copper pad diameter: 250 m recommended, 300m max solder stencil opening: 330 m solder mask opening recommendation: 340 m min for 315 m copper pad diameter x y x w z w e dot, st logo xx = marking yww = datecode (y = year ww = week) z = manufacturing location dot identifying pin a1 location user direction of unreeling all dimensions in mm 4 0.1 1.0 1.0 8 0.3 4 0.1 1.75 0.1 3.5 0.1 ? 1.5 0.1 0.73 0.05 xxx yww st e xxx yww st e xxx yww st e
ESDA18-1F2 ordering information 7/8 5 ordering information 6 revision history table 3. ordering information order code marking package weight base qty delivery mode ESDA18-1F2 ee flip chip 1.25 mg 5000 tape and reel 7? table 4. document revision history date revision changes 09-may-2005 1 first issue. 18-apr-2008 2 updated ecopack statement. updated figure 11 , figure 13 , and figure 14 . reformatted to current standards.
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