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december 2007 rev 1 1/11 11 sta510f 44-v, 5.5-a, quad power half bridge features ! minimum input output pulse width distortion ! 150 mw rdson complementary dmos output stage ! cmos compatible logic inputs ! thermal protection ! thermal warning output ! under-voltage protection ! no power-on, power- off sequence required description sta510f is a monolithic, quad, half-bridge stage in multipower bcd technology. the device can be used as dual bridge or reconfigured, by connecting config pin to vdd pin, as single bridge with double current capability, and as half bridge (binary mode) with half current capability. the device is particularly designed to make the output stage of a stereo all-digital high-efficiency (ffx) amplifier capable of delivering 100 w + 100 w output power into 8- ? loads with thd = 10% and v cc = 39 v. in single btl configuration the device can deliver 200 w into a 4- ? load with thd = 10% and v cc = 39 v. the device is fully compatible with the ddx ? driver device. the input pins have a threshold proportional to v l pin voltage. figure 1. typical application powerso36 with exposed pad (or slug) up table 1. device summary order code operating temp. range package packing sta510f 0 to 70 c powerso36 (slug up) tube sta510f sta330 output filter output filter psu speaker speaker in a in b out a out b pwm out 1a pwm out 2a pwm out 1b pwm out 2b in 1a in 2a in1b in 2b out 1a out 1b out 2a out 2b vcc speaker speaker in a in b out a out b vcc gnd www.st.com
pin description sta510f 2/11 1 pin description figure 2. pin connection (top view) table 2. pin list pin name description 1 gnd-sub substrate ground 2, 3 out2b output half bridge 2b 4 vcc2b positive supply 5 gnd2b negative supply 6 gnd2a negative supply 7 vcc2a positive supply 8, 9 out2a output half bridge 2a 10, 11 out1b output half bridge 1b 12 vcc1b positive supply 13 gnd1b negative supply 14 gnd1a negative supply 15 vcc1a positive supply 16, 17 out1a output half bridge 1a gnd-sub out2b out2b v cc 2b gnd1b v cc 1a gnd1a out1a out1a gnd-reg v dd v dd config v ss v ss v cc sign v cc sign 18 16 17 15 6 5 4 3 2 21 22 31 32 33 35 34 36 20 1 19 n.c. gnd-clean d01au1273 out1b v cc 1b out1b pwrdn fault tri-state 9 8 7 28 29 30 out2a th_war 10 27 gnd2b out2a v cc 2a in1a in2b in1b 14 12 11 23 25 26 gnd2a in2a 13 24 v l
sta510f pin description 3/11 18 nc not connected 19 gnd-clean logical ground 20 gnd-reg ground for regulator vdd 21, 22 vdd 5v regulator referred to ground 23 v l high logical state setting voltage 24 config configuration 25 pwrdn stand-by 26 tri-state hi-z 27 fault fault pin advisor 28 th-war thermal warning advisor 29 in1a input of half bridge 1a 30 in1b input of half bridge 1b 31 in2a input of half bridge 2a 32 in2b input of half bridge 2b 33, 34 vss 5-v regulator referred to +vcc 35, 36 vccsign signal positive supply table 3. pin logical value device status fault (1) 1. the pin is open collector. to have the high logic value, it needs a pull-up resistor. 0 fault detected (short circuit, or thermal) 1 normal operation tri-state 0 all power stages in hi-z state 1 normal operation pwrdn 0 low-power mode 1 normal operation thwar (1) 0 temperature of the ic =130 c 1 normal operation config (2) 2. config = 1 means connect pin 24 (config) to pins 21, 22 (vdd). 0 normal operation 1 out1a = out1b, out2a = out2b (if in1a = in1b and in2a = in2b) table 2. pin list (continued) pin name description
electrical specifications sta510f 4/11 2 electrical specifications 2.1 absolute maximum ratings 2.2 thermal data 2.3 electrical specifications unless otherwise stated, the results in ta bl e 6 below are given for the conditions: v l =3.3v, vcc = 37 v and t = 25 c unless otherwise specified. table 4. absolute maximum ratings symbol parameter value unit v cc dc supply voltage (pin 4, 7, 12, 15) 44 v v max maximum voltage on pins 23 to 32 5.5 v esd max esd on pins (hbm) 1000 v t op operating temperature range 0 to 70 c t stg , t j storage and junction temperature -40 to 150 c table 5. thermal data symbol parameter min typ max unit t j-case thermal resistance junction to case (thermal pad) 1 2.5 c/w t jsd thermal shut-down junction temperature 150 c t warn thermal warning temperature 130 c t hsd thermal shut-down hysteresis 25 c table 6. electrical specifications symbol parameter condition min typ max unit r dson power pchannel/nchannel mosfet rdson id = 1 a 150 200 m ? i dss power pchannel/nchannel leakage current 100 a g n power pchannel rdson matching id = 1 a 95 % g p power nchannel rdson matching id = 1 a 95 % dt_s low current dead time (static) see test circuit figure 3 10 20 ns dt_d high current dead time (dynamic) l=22 h, c = 470nf, r l = 8 ?, id = 4.5 a, see test circuit figure 4 50 ns
sta510f electrical specifications 5/11 t d on turn-on delay time resistive load 100 ns t d off turn-off delay time resistive load 100 ns t r rise time resistive load, as figure 4 25 ns t f fall time resistive load, as figure 4 25 ns v cc supply voltage operating voltage 10 40 v v in-high high level input voltage v l /2 +300 mv v v in-low low level input voltage v l /2 - 300m v v i in-h high level input current pin voltage = v l 1 a i in-l low level input current pin voltage = 0.3v 1 a i pwrdn-h high level pwrdn pin input current v l = 3.3v 35 a v low low logical state voltage (pins pwrdn, tristate) (see ta bl e 7 ) v l = 3.3v 0.8 v v high high logical state voltage (pins pwrdn, tristate) (see ta bl e 7 ) v l = 3.3v 1.7 v i vcc- pwrdn supply current from vcc in power down pwrdn = 0 3 ma i fault output current pins fault -th-warn when fault conditions vpin = 3.3v 1 ma i vcc-hiz supply current from vcc in tri- state pin tri-state = 0 22 ma i vcc supply current from vcc in operation both channel switching) input pulse width duty cycle = 50%, switching frequency =384khz, no lc filters; 70 ma i out-sh overcurrent protection threshold isc (short circuit current limit) (note 2) 5.579a v uv undervoltage protection threshold 7v t pw_min output minimum pulse width no load 25 40 ns table 6. electrical specifications (continued) symbol parameter condition min typ max unit
electrical specifications sta510f 6/11 figure 3. test circuit for low current dead time figure 4. test circuit for high current dead time table 7. v low , v high threshold variation with v l v l v low max v high min unit 2.7 0.7 1.5 v 3.3 0.8 1.7 v 5 0.85 1.85 v table 8. logic truth table tri-stateinxainxbq1q2q3q4output mode 0 x x off off off off hi-z 1 0 0 off off on on dump 1 0 1 off on on off negative 1 1 0 onoffoffonpositive 1 1 1 ononoffoffnot used low current dead time = max(dtr,dtf) outxy vcc (3/4)vcc (1/2)vcc (1/4)vcc t dtf dtr duty cycle = 50% inxy outxy gnd +vcc m58 m57 r 8 ? + - v67 = vdc = vcc/2 d03au1458 high current dead time for bridge application = abs(dtout(a)-dtin(a))+abs(dtout(b)-dtin(b)) +v cc rload=8 ? q2 outxb dtout(b) dtin(b) dtout(a) c71 470nf c70 470nf c69 470nf iout=4.5a iout=4.5a q4 q1 q3 m64 inxb m63 d00au1162 m58 inxa m57 dtin(a) duty cycle=a duty cycle=b duty cycle a and b: fixed to have dc output current of 4.5a in the direction shown in figure l68 22 l67 22 outxa
sta510f electrical specifications 7/11 figure 5. typical quad half-bridge configuration giving 200 w per channel into 4 ? speakers, 10% thd, v cc =39v figure 6. typical driving configuration with sta330 out1b out2a out1a out2b vcc 3v3 3v3 in 2b in 2a in 1b in 1a eapd th_w pwm input c202 330p c202 330p c6 100n c6 100n r103 20 r103 20 4 ohm 4 ohm r2 10k r2 10k + c1 1000u + c1 1000u l201 15u l201 15u c2 100n c2 100n c201 330p c201 330p c104 10n c104 10n r202 20 r202 20 sta510f sta510f gnd sub 1 out2b 2 out2b 3 vcc2b 4 gnd2b 5 gnd2a 6 vcc2a 7 out2a 8 out2a 9 out1b 10 out1b 11 vcc1b 12 gnd1b 13 gnd1a 14 vcc1a 15 out1a 16 out1a 17 nc 18 gndclean 19 gndreg 20 vdd 21 vdd 22 ibias 23 config 24 pwrdn 25 tristate 26 fault 27 th_warn 28 in1a 29 in1b 30 in2a 31 in2b 32 vss 33 vss 34 vccsig 35 vccsig 36 l101 15u l101 15u c4 100n c4 100n r104 20 r104 20 l202 15u l202 15u c7 100n c7 100n c203 10n c203 10n c107 330n c107 330n l102 15u l102 15u c3 1u c3 1u c8 100n c8 100n r201 20 r201 20 c204 10n c204 10n c9 100n c9 100n c105 1u c105 1u 4 ohm 4 ohm r203 20 r203 20 c102 330p c102 330p c207 330n c207 330n c101 330p c101 330p r101 20 r101 20 c106 1u c106 1u r102 20 r102 20 c205 1u c205 1u c103 10n c103 10n c5 1u c5 1u c10 100n c10 100n c11 100n c11 100n r204 20 r204 20 r1 10k r1 10k c206 1u c206 1u
package information sta510f 8/11 3 package information in order to meet environmental requirements, st offers these devices in ecopack ? packages. these packages have a lead-free second level interconnect. the category of second level interconnect is marked on the package and on the inner box label, in compliance with jedec standard jesd97. the maximum ratings related to soldering conditions are also marked on the inner box label. ecopack is an st trademark. ecopack specifications are available at: http://www.st.com. figure 7. powerso36 package dimensions outline and mechanical data m. mm inch min. typ. max. min. typ. max. a 3.25 3.43 0.128 0.135 a2 3.1 3.2 0.122 0.126 a4 0.8 1 0.031 0.039 a5 0.2 0.008 a1 0.030 -0.040 0.0011 -0.0015 b 0.22 0.38 0.008 0.015 c 0.23 0.32 0.009 0.012 d 15.8 16 0.622 0.630 d1 9.4 9.8 0.37 0.38 d2 1 0.039 e 13.9 14.5 0.547 0.57 e1 10.9 11.1 0.429 0.437 e2 2.9 0.114 e3 5.8 6.2 0.228 0.244 e4 2.9 3.2 0.114 1.259 e0.65 0.026 e3 11.05 0.435 g 0 0.075 0 0.003 h 15.5 15.9 0.61 0.625 h 1.1 0.043 l 0.8 1.1 0.031 0.043 n 10? 10? s8?8? (1) ?d and e1? do not include mold flash or protusions. mold flash or protusions shall not exceed 0.15mm (0.006?) (2) no intrusion allowed inwards the leads. di powerso36 (slug up) 7183931 d outline and mechanical data (exposed pad (slug) up) powers036
sta510f trademarks and other acknowledgements 9/11 4 trademarks and other acknowledgements ffx is a stmicroelectronics proprietary digital modulation technology. ddx is a registered trademark of apogee technology, inc. ecopack is a registered trademark of stmicroelectronics.
revision history sta510f 10/11 5 revision history table 9. document revision history date revision changes 13-dec-2007 1 initial release.
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