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publication release date: april 13, 2005 - i - revision 2.1 w83194br-645 data sheet winbond clock generator for sis 645/650 chipset
w83194br-645 - ii - table of contents- 1. general description ..........................................................................................................1 2. features ....................................................................................................................... ...........1 3. pin configuration .............................................................................................................. ..2 4. block diagram .................................................................................................................. .....2 5. pin description................................................................................................................ ......3 5.1 crystal i/o .................................................................................................................... ....3 5.2 cpu, zclk, sdram, pci clock outputs .......................................................................3 5.3 i2c control interface........................................................................................................4 5.4 fixed frequency outputs ................................................................................................4 5.5 power management pins.................................................................................................5 5.6 power pins..................................................................................................................... ..5 6. frequency selection by hardware or software .................................................7 7. i 2 c control and status registers ................................................................................9 7.1 register 4: frequency select register (default = 0) .......................................................9 7.2 register 5: cpu, sdram clock register (1 = enable, 0 = stopped).............................9 7.3 register 6 pci clock register (1 = enable, 0 = stopped) ............................................11 7.4 register 7 48 mhz, zclk, ref clock regist er (1 = enable, 0 = stopped)..................11 7.5 register 8: agp control register (1 = enable, 0 = stopped) ............. ............. .............11 7.6 register 9: watchdog control register .........................................................................13 7.7 register 10: watchdog timer register .........................................................................13 7.8 register 11: m/n program register...............................................................................14 7.9 register 12: m/n program register...............................................................................14 7.10 register 13: spread spectrum programming register .................................................14 7.11 register 14: divisor and step-less enable contro l register.........................................15 7.12 register 15: cpu_zclk skew control register...........................................................15 7.13 register 16: cpu_agp_skew.....................................................................................15 7.14 register 17: skew control register...............................................................................16 7.15 register 18: winbond chip id register (read only) ....................................................16 7.16 register 19: winbond chip id register (read only) ....................................................16 7.17 ratio selection table.....................................................................................................17 8. access interface ............................................................................................................... 19 8.1 block write protocol ......................................................................................................19 8.2 block read protocol ......................................................................................................19 8.3 byte write protocol ........................................................................................................19 8.4 byte read protocol ........................................................................................................19 9. ordering information......................................................................................................20 10. how to read the top marking.......................................................................................20 11. package drawing and dimensions...............................................................................21 12. revision history ............................................................................................................... ..22
w83194br-645 publication release date: april 13, 2005 - 1 - revision 2.1 1. general description the w83194br-645 is a clock synthesizer for sis645/650 chipset. w83194br-645 provides all clocks required for high-speed intel pentium 4, and also provides 32 different frequencies of cpu clocks frequency setting. all clocks are externally selectable with smooth transitions. the w83194br- 645 makes sdram in synchronous or asynchronous frequency with cpu clocks. the w83194br-645 provides step-less frequency programming by controlling the vco freq. and the programmable agp, pci clock output divisor ratio. a watchdog timer is quipped and when time out, register9 bit5 will be set to 1 for warning. spread spectrum built in at 0.5% or 0.25% to reduce emi. programmable stopping individual clock outputs and frequency selection through i 2 c interface the w83194br-645 accepts a 14.318 mhz reference crystal as its input and runs on a 3.3v supply. high drive pci clock outputs typically provide greater than 1v /ns slew rate into 30 pf loads. the fixed frequency outputs as ref, 24 mhz, and 48 mhz provide better than 0.5v /ns slew rate. 2. features ? supports intel pentium 4 cpu with i 2 c. ? 2 pairs of differential cpu clocks ? 2 zclk for sis 645/650 chipset ? 2 agp clocks ? 1 sdram output clock for chipset ? 8 pci synchronous clocks ? 1 24/48 mhz, 1 48 mhz ? 3 ref clocks ? skew --- cpu to sdram < 1 ns, pci to pci < 500 ps, agp to agp < 175 ps ? smooth frequency switch with selections from 66 to 200 mhz ? i 2 c 2-wire serial interface and i 2 c read back ? flexible spread spectrum to reduce emi ? programmable registers to enable/stop each output and select modes (mode as tri-state or normal) ? packaged in 48-pin ssop
w83194br-645 - 2 - 3. pin configuration 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 vddr fs0&/ref0 xin xout gnd fs3&/pciclk_f0 fs4&/pciclk_f1 pciclk2 pciclk3 pciclk4 pciclk5 gnd vddpci 48mhz sdata* sdclk* vddsd sdram cpuclkt_1 vddc cpuclkc_1 vdda 24_48mhz/ multisel* vddagp gnd vdd48 gnd pci_stop#* agpclk0 gnd fs1&/ref1 agpclk1 &: pull-down 120k * : pull-up 120k # :input active low vddpci vddz gnd pd#*/vtt_pwgd zclk1 iref gnd gnd cpu_stop#* cpuclkt_0 cpuclkc_0 gnd pciclk1 pciclk0 zclk0 fs2&/ref2 4. block diagram pll2 mux control logic & config register divider 1/2 stop xtal osc pll1 spread spectrum stop m/n/ratio s.s.p rom driver vcoclk 48mhz 24_48mhz ref0:2 cpuclk_t 0:2 cpuclk_c 0:2 agpclk 0:1 pciclk_f0:1 pciclk_0:5 rref xin xout *sdata *sdclk fs<4:0> pd#* cpu_stop#* pci_stop#* multisel0* vtt_pwgd latch & por i2c interface 8 2 3 3 3 zclk 0:1 2 sdram
w83194br-645 publication release date: april 13, 2005 - 3 - revision 2.1 5. pin description buffer type symbol description in input in tp120k latched input at power up, internal 120 k ? pull up. in td120k latched input at power up, internal 120 k ? pull down. out output od open drain i/o bi-directional pin i/od bi-directional pin, open drain. # active low * internal 120 k ? pull-up & internal 120 k ? pull-down 5.1 crystal i/o pin pin name type description 6 xin in crystal input with internal loading capacitors (18pf) and feedback resistors. 7 xout out crystal output at 14.318 mhz nominally with internal loading capacitors (18pf). 5.2 cpu, zclk, sdram, pci clock outputs pin pin name type description 40, 39, 44, 43 cpuclkt_0 cpuclkc_0, cpuclkt_1 cpuclkc_1, out true cpu clock output and complementary cpu clock output. this pin will be stopped by cpu_stop# 47 sdram out sdram clock output, which have syn. or asyn. frequencies as cpu clocks. the clock phase is the same as cpuclkt_0 and cpuclkt_1. pciclk_f0 out pci free running clock during normal operation. 14 fs3& in td120k latched input for fs3 at initial power up for h/w selecting the output frequency. internal 120k ? pull-down pciclk_f1 out pci free running clock during normal operation. 15 fs4& in td120k latched input for fs4 at initial power up for h/w selecting the output frequency. internal 120k ? pull-down 16, 17, 20, 21, 22, 23 pciclk [0:5] out low skew (< 500ps) pci clock outputs.
w83194br-645 - 4 - 31, 30 agpclk [0:1] out agp clock outputs for agp. 9, 10 zclk [0:1] out z clock outputs for chipset. 5.3 i2c control interface pin pin name type description 34 sdata* i/o serial data of i 2 c 2-wire control inte rface, internal 120k ? pull- up. 35 sdclk* in serial clock of i 2 c 2-wire control interface, internal 120k ? pull- up. 5.4 fixed frequency outputs pin pin name type description 38 iref in deciding the reference current for the cpuclk pairs. the pin was connected to the precision resistor tied to ground to decide the appropriate current. there are two modes to select different current via power on trapping the pin 26 (multisel0). the table is show as follows. ref0 out 3.3v, 14.318 mhz reference clock output. 2 fs0& in td120k latched input for fs0 at initial power up for h/w selecting the output frequency. internal 120k ? pull-down. ref1 out 3.3v, 14.318 mhz reference clock output. 3 fs1& in td120k latched input for fs1 at initial power up for h/w selecting the output frequency, internal 120k ? pull-down. ref2 out 3.3v, 14.318 mhz reference clock output. 4 fs2& in td120k latched input for fs2 at initial power up for h/w selecting the output frequency. internal 120k ? pull-down. 24_48 mhz out 24 mhz or 48 mhz selected by register. 26 multisel0* in tp120k multisel0 at initial power up for h/w selecting the current multiplier for cpu outputs. internal 120k ? pull-up. 27 48 mhz out 48 mhz output for usb.
w83194br-645 publication release date: april 13, 2005 - 5 - revision 2.1 5.5 power management pins pin pin name type description pd#* in power down pin, if pd# = 0, all clocks are stopped. 33 vtt_pwgd in power good input signal comes from acpi with high active. this 3.3v input is level sensitive strobe used to determine fs [4:0] and multisel input are valid and is ready to sample. this pin is high active. 45 cpu_stop#* in cpu clock stop control pin, this pin is low active. internal 120k ? pull-up. 12 pci_stop#* in pci clock stop control pin, this pin is low active. internal 120k ? pull-up. 5.6 power pins pin pin name description 1 vddr power supply for ref0: 2 3.3v. 11 vddz power supply for zclk 3.3v. 36 vdda power supply for core logic. 3.3v 42 vddc power supply for cpuclk 3.3v. 29 vddagp power supply for agp outputs. 13,19 vddpci power supply for pci outputs. 48 vddsd power supply for sdram 3.3v. 28 vdd48 power supply for 48/24 mhz outputs. 5, 8, 18, 24, 25, 32, 37, 41, 46 gnd circuit ground.
w83194br-645 - 6 - hardware multsel [1:0] selects function multsel1 byte 8 bit 0 multsel0 pin 26 board target trace/term z reference r, iref = vdd/(3*rr) output current voh @ z 0 0 50 ? rr = 221 1% iref = 5.00 ma ioh = 4*iref 1.0v @ 50 0 0 60 ? rr = 221 1% iref = 5.00 ma ioh = 4*iref 1.2v @ 60 0 1 50 ? rr = 221 1% iref = 5.00 ma ioh = 5*iref 1.25v @ 50 0 1 60 ? rr = 221 1% iref = 5.00 ma ioh = 5*iref 1.5v @ 60 1 0 50 ? rr = 221 1% iref = 5.00 ma ioh = 6*iref 1.5v @ 50 1 0 60 ? rr = 221 1% iref = 5.00 ma ioh = 6*iref 1.8v @ 60 1 1 50 ? rr = 221 1% iref = 5.00 ma ioh = 7*iref 1.75v @ 50 1 1 60 ? rr = 221 1% iref = 5.00 ma ioh = 7*iref 2.1v @ 50 0 0 50 ? rr = 475 1% iref = 2.32 ma ioh = 4*iref 0.47v @ 50 0 0 60 ? rr = 475 1% iref = 2.32 ma ioh = 4*iref 0.56v @ 50 0 1 50 ? rr = 475 1% iref = 2.32 ma ioh = 5*iref 0.58v @ 50 0 1 60 ? rr = 475 1% iref = 2.32 ma ioh = 5*iref 0.7v @ 60 1 0 50 ? rr = 475 1% iref = 2.32 ma ioh = 6*iref 0.7v @ 50 1 0 60 ? rr = 475 1% iref = 2.32 ma ioh = 6*iref 0.84v @ 60 1 1 50 ? rr = 475 1% iref = 2.32 ma ioh = 7*iref 0.81v @ 50 1 0 60 ? rr = 475 1% iref = 2.32 ma ioh = 6*iref 0.97v @ 60
w83194br-645 publication release date: april 13, 2005 - 7 - revision 2.1 6. frequency selection by hardware or software this frequency table is used at power on latched fs [4:0] value or software programming at ssel [4:0] (register 4 bit 4 ~ 7, 2). fs4 fs3 fs2 fs1 fs0 cpu (mhz) sdram (mhz) zclk (mhz) agp (mhz) pci (mhz)
w83194br-645 - 8 - 0 0 0 0 0 66.67 66.67 66.67 66.67 33.33 0 0 0 0 1 100.00 100.00 66.67 66.67 33.33 0 0 0 1 0 100.00 200.00 66.67 66.67 33.33 0 0 0 1 1 100.00 133.33 66.67 66.67 33.33 0 0 1 0 0 100.00 150.00 60.00 60.00 30.00 0 0 1 0 1 100.00 125.00 62.50 62.50 31.25 0 0 1 1 0 108.00 162.1 64.8 64.8 32.4 0 0 1 1 1 100.00 133.33 80.00 66.67 33.33 0 1 0 0 0 100.00 200.00 66.67 66.67 33.33 0 1 0 0 1 100.00 166.67 62.50 62.50 31.25 0 1 0 1 0 100.00 166.67 71.43 83.33 41.67 0 1 0 1 1 80.00 133.33 66.67 66.67 33.33 0 1 1 0 0 80.00 133.33 66.67 66.67 33.33 0 1 1 0 1 95.00 95.00 63.33 63.33 31.67 0 1 1 1 0 95.00 126.67 63.33 63.33 31.67 0 1 1 1 1 66.67 66.67 50.00 50.00 25.00 1 0 0 0 0 105.00 140.00 70.00 70.00 35.00 1 0 0 0 1 100.90 100.90 67.27 67.27 33.63 1 0 0 1 0 108.00 144.00 72.00 72.00 36.00 1 0 0 1 1 100.90 134.53 67.27 67.27 33.63 1 0 1 0 0 112.00 149.33 74.67 74.67 37.33 1 0 1 0 1 133.33 100.00 66.67 66.67 33.33 1 0 1 1 0 133.33 133.33 66.67 66.67 33.33 1 0 1 1 1 133.33 166.67 66.67 66.67 33.33 1 1 0 0 0 100.00 133.00 80.00 66.67 33.33 1 1 0 0 1 100.00 100.00 80.00 66.67 33.33 1 1 0 1 0 100.00 166.67 83.33 62.50 31.25 1 1 0 1 1 133.33 166.67 83.33 66.67 33.33 1 1 1 0 0 100.00 133.00 100.00 66.67 33.33 1 1 1 0 1 100.00 100.00 100.00 66.67 33.33 1 1 1 1 0 100.00 166.67 100.00 62.50 31.25 1 1 1 1 1 130.4 163.0 93.2 65.2 32.6
w83194br-645 publication release date: april 13, 2005 - 9 - revision 2.1 7. i 2 c control and status registers the register 0~3 are reserved for external clock buffer (the register no. is increased by 1 if use byte data read/write protocol) 7.1 register 4: frequency select register (default = 0) bit name pwd description 7 ssel [3] 0 6 ssel [2] 0 5 ssel [1] 0 4 ssel [0] 0 frequency selection by software via i 2 c 3 en_ssel 0 enable software program fs [4:0]. 0 = select frequency by hardware. 1= select frequency by software i 2 c - bit 4: 7, 2. 2 ssel [4] 0 frequency selection bit 4 1 en_spsp 0 enable spread spectrum in the frequency table. 0 = normal 1 = spread spectrum enabled 0 en_safe_freq 0 enable reload safe frequency when the watchdog is timeout. 0 = reload the fs [4:0] latched pins when watchdog time out. 1 = reload the safe frequency bit defined at register 9 bit 4~0. 7.2 register 5: cpu, sdram clock register (1 = enable, 0 = stopped) bit pin no. pwd description 7 47 1 sdram 6 44, 43 1 cpuclkt/c1 5 40, 39 1 cpuclkt/c0 4 15 x fs [4] read back. 3 14 x fs [3] read back 2 4 x fs [2] read back 1 3 x fs [1] read back 0 2 x fs [0] read back
w83194br-645 - 10 -
w83194br-645 publication release date: april 13, 2005 - 11 - revision 2.1 7.3 register 6 pci clock register (1 = enable, 0 = stopped) bit pin no. pwd description 7 15 1 pciclk_f1 6 14 1 pciclk_f0 5 23 1 pciclk 5 4 22 1 pciclk 4 3 21 1 pciclk 3 2 20 1 pciclk 2 1 17 1 pciclk 1 0 16 1 pciclk 0 7.4 register 7 48 mhz, zclk, ref clock register (1 = enable, 0 = stopped) bit pin no. pwd description 7 27 1 48 mhz 6 26 1 24_48 mhz 5 sel_24 1 24/48 mhz frequency control 1: 24 mhz. 0: 48 mhz. 4 10 1 zclk1 3 9 1 zclk0 2 4 1 ref2 1 3 1 ref1 0 2 1 ref0 7.5 register 8: agp control register (1 = enable, 0 = stopped) bit pin no. pwd description 7 1 cpuclkt/c0 stop control: 0: cpuclk0 free run 1: cpuclk0 can stopped by cpu_stop# 6 1 cpuclkt/c1 stop control: 0: cpuclk1 free run 1: cpuclk1 can stopped by cpu_stop# 5 0 pci_f0 stop control: 0: pci_f0 free run
w83194br-645 - 12 - 1: pci_f0 can stopped by pci_stop#
w83194br-645 publication release date: april 13, 2005 - 13 - revision 2.1 register 8: agp control register (1 = enable, 0 = stopped), continued bit pin no. pwd description 4 0 pci_f1 stop control: 0: pci_f1 free run 1: pci_f1 can stopped by pci_stop# 3 30 1 agp_1 2 31 1 agp_0 1 multisel0 1 multisel0 trapping pin data read back 0 multisel1 0 multisel1 (iref output control) 7.6 register 9: watchdog control register bit name pwd description 7 reserved 0 reserved 6 en_wd 0 enable watchdog timer if set to 1. set to 0, disable watchdog timer. read this bit will return a counting state. if timer continues down count, this bit will return 1. otherwise, this bit will return 0. 5 wd_timeout 0 watchdog timeout status. if the watchdog is started and timer down counts to zero, this bit will be set to 1. clear this bit to logic 0, if set to 1, when the watchdog is restart in the next time. this bit is read only. 4 saf_freq [4] 0 3 saf_freq [3] 0 2 saf_freq [2] 0 1 saf_freq [1] 0 0 saf_freq [0] 0 watchdog safe frequency bits. these bits will be reloaded into fs [4:0], if the watchdog is timeout and enable reload safe frequency bits. 7.7 register 10: watchdog timer register bit name pwd description 7 wd_time [7] 0 6 wd_time [6] 0 5 wd_time [5] 0 4 wd_time [4] 0 3 wd_time [3] 1 2 wd_time [2] 0 1 wd_time [1] 0 watchdog timeout time. the bit resolution is 250 ms. the default time is 8*250 ms = 2.0 seconds. if the watchdog timer is start, this register will be down count. read this register will return a down count value.
w83194br-645 - 14 - 0 wd_time [0] 0 7.8 register 11: m/n program register bit name pwd description 7 n_div [8] 1 programmable n divisor value. bit 7~0 are defined in the register 12. 6 test2 0 test bit 2. winbond test bit, do not change them. 5 test1 1 test bit 1. winbond test bit, do not change them. 4 m_div [4] 0 3 m_div [3] 1 2 m_div [2] 0 1 m_div [1] 1 0 m_div [0] 1 programmable m divisor value. 7.9 register 12: m/n program register bit name pwd description 7 n_div [7] 0 6 n_div [6] 0 5 n_div [5] 1 4 n_div [4] 0 3 n_div [3] 1 2 n_div [2] 1 1 n_div [1] 1 0 n_div [0] 1 programmable n divisor value bit 7~0. the bit 8 is defined in register 11. 7.10 register 13: spread spectrum programming register bit name pwd description 7 sp_up [3] 0 spread spectrum up counter bit 3. 6 sp_up [2] 0 spread spectrum up counter bit 2. 5 sp_up [1] 0 spread spectrum up counter bit 1. 4 sp_up [0] 1 spread spectrum up counter bit 0 3 sp_down [3] 1 spread spectrum down counter bit 3 2 sp_down [2] 1 spread spectrum down counter bit 2 1 sp_down [1] 1 spread spectrum down counter bit 1
w83194br-645 publication release date: april 13, 2005 - 15 - revision 2.1 0 sp_down [0] 1 spread spectrum down counter bit 0 7.11 register 14: divisor and step-less enable control register bit name pwd description 7 en_mn_prog 0 0: use frequency table 1: use m/n register to program frequency the equation is vco freq. = 14.318mhz * (n+4)/ m . when the watchdog timer is timeout, this will be clear. in this time, the frequency is set to hardware default latched or safe frequency set by en_sfae_freq (register 9 bit 0). 6 ratio_sel [4] 1 5 ratio_sel [3] 0 4 ratio_sel [2] 0 3 ratio_sel [1] 1 2 ratio_sel [0] 1 cpu, pci, agp, sdram, and zclk ratio selection. the ratio is shown as following table. 1 test0 0 0 reserved 0 test bit 0. winbond test bit, do not change them. 7.12 register 15: cpu_zclk skew control register bit name pwd description 7 cpu_zclk_skew [2] 1 cpu to zclk skew control 6 reserved 0 reserved 5 reserved 1 4 reserved 0 3 reserved 0 2 reserved 1 1 reserved 1 0 reserved 1 reserved 7.13 register 16: cpu_agp_skew bit name pwd description 7 reserved 0 6 reserved 0 reserved for winbond internal use, do not change them 5 reserved 0 reserved for winbond internal use, do not change them 4 cpu_stop 1 cpu_stop pin read back
w83194br-645 - 16 - 3 pci_stop 1 cpu_stop pin read back 2 cpu_agp_skew [2] 1 1 cpu_agp_skew [1] 0 0 cpu_agp_skew [0] 0 cpu to agp skew. 7.14 register 17: skew control register bit name pwd description 7 cpu_zclk_skew [1] 0 6 cpu_zclk_skew [0] 0 cpu to agp skew 5 cpu_sdram_skew [2] 1 4 cpu_sdram_skew [1] 0 3 cpu_sdram_skew [0] 0 cpu to sdram skew 2 cpu_pci_skew [2] 1 1 cpu_pci_skew [1] 0 0 cpu_pci_skew [0] 0 cpu to pci skew 7.15 register 18: winbond chip id register (read only) bit name pwd description 7 chpi_id [7] 0 winbond chip id. w83194br-645 is 0x77. 6 chpi_id [6] 1 winbond chip id. 5 chpi_id [5] 1 winbond chip id. 4 chpi_id [4] 1 winbond chip id. 3 chpi_id [3] 0 winbond chip id. 2 chpi_id [2] 1 winbond chip id. 1 chpi_id [1] 1 winbond chip id. 0 chpi_id [0] 1 winbond chip id. 7.16 register 19: winbond chip id register (read only) bit name pwd description 7 sub_id [3] 0 winbond sub-chip id. the sub-chip id of w83194br-645 is defined as 0001b. 6 sub_id [2] 0 winbond sub-chip id. 5 sub_id [1] 0 winbond sub-chip id. 4 sub_id [0] 1 winbond sub-chip id.
w83194br-645 publication release date: april 13, 2005 - 17 - revision 2.1 3 ver_id [3] 0 winbond version id. the version id of w83194br-645 is 0001b. 2 ver_id [2] 0 winbond version id. 1 ver_id [1] 0 winbond version id. 0 ver_id [0] 1 winbond version id. 7.17 ratio selection table table of cpu, pci, agp, sdram, and zclk clock selection. reg14 reg14 reg14 reg14 reg14 bit6 bit5 bit4 bit3 bit2 cpu sdram zclk agp pci ssel4 ssel3 ssel2 ssel1 ssel0 ratio ratio ratio ratio ratio 0 0 0 0 0 3 3 6 6 12 0 0 0 0 1 3 4 6 6 12 0 0 0 1 0 4 2 6 6 12 0 0 0 1 1 4 3 4 6 12 0 0 1 0 0 4 3 5 6 12 0 0 1 0 1 4 3 6 6 12 0 0 1 1 0 4 4 4 6 12 0 0 1 1 1 4 4 5 6 12 0 1 0 0 0 4 4 6 6 12 0 1 0 0 1 5 3 5 8 16 0 1 0 1 0 5 3 6 8 16 0 1 0 1 1 5 3 6 6 12 0 1 1 0 0 5 3 7 6 12 0 1 1 0 1 5 3 8 8 16 0 1 1 1 0 5 4 7 10 20 0 1 1 1 1 5 4 8 8 16 1 0 0 0 0 5 4 8 10 20 1 0 0 0 1 5 4 10 10 20 1 0 0 1 0 6 4 10 10 20 1 0 0 1 1 6 6 6 6 12 1 0 1 0 0 6 6 8 8 16
w83194br-645 - 18 -
w83194br-645 publication release date: april 13, 2005 - 19 - revision 2.1 8. access interface the w83194br-645 provides i 2 c serial bus for microprocessor to read/write internal registers. in the w83194br-645 is provided block read/block write and byte-data read/write protocol. the i 2 c address is defined at 0xd2. block read and block write protocol 8.1 block write protocol 8.2 block read protocol ## in block mode, the command code must filled 8?h00 8.3 byte write protocol 8.4 byte read protocol
w83194br-645 - 20 - 9. ordering information part number package type production flow w83194br-645 48-pin ssop commercial, 0 c to +70 c 10. how to read the top marking 1st line: winbond logo and the type number: w83194br-645 2nd line: tracking code 2 8051234 2 : wafers manufactured in winbond fab 2 8051234 : wafer production series lot number 3rd line: tracking code 942 g e d 242 : packages made in '2002, week 42 g : assembly house id; o means ose, g means gr e : internal use code d : ic revision all the trade marks of products and companies mentioned in this data sheet belong to their respective owners. w83194br-645 28051234 242ged
w83194br-645 publication release date: april 13, 2005 - 21 - revision 2.1 11. package drawing and dimensions
w83194br-645 - 22 - 12. revision history version date page description n.a. all of the versions before 0.50 are for internal use. 1.0 01/08/02 n.a. change version and version on web site to 1.0 2.0 02/24/03 all update new form 2.1 4/13/2005 22 add disclaimer important notice winbond products are not designed, intended, authorized or warranted for use as components in systems or equipment intended for surgical implantation, atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, or for other applications intended to support or sustain life. further more, winbond products are not intended for applications wherein failure of winbond products could result or lead to a situation wherein personal injury, death or severe property or environmental damage could occur. winbond customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify winbond for any damages resulting from such improper use or sales. headquarters no. 4, creation rd. iii, science-based industrial park, hsinchu, taiwan tel: 886-3-5770066 fax: 886-3-5665577 http://www.winbond.com.tw/ taipei office tel: 886-2-8177-7168 fax: 886-2-8751-3579 winbond electronics corporation america 2727 north first street, san jose, ca 95134, u.s.a. tel: 1-408-9436666 fax: 1-408-5441798 winbond electronics (h.k.) ltd. no. 378 kwun tong rd., kowloon, hong kong fax: 852-27552064 unit 9-15, 22f, millennium city, tel: 852-27513100 please note that all data and specifications are subject to change without notice. all the trade marks of products and companies mentioned in this data sheet belong to their respective owners. winbond electronics (shanghai) ltd. 200336 china fax: 86-21-62365998 27f, 2299 yan an w. rd. shanghai, tel: 86-21-62365999 winbond electronics corporation japan shinyokohama kohoku-ku, yokohama, 222-0033 fax: 81-45-4781800 7f daini-ueno bldg, 3-7-18 tel: 81-45-4781881 9f, no.480, rueiguang rd., neihu district, taipei, 114, taiwan, r.o.c.

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