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the information in this document is subject to change without notice. before using this document, please confirm that this is the latest version. not all products and/or types are available in every country. please check with nec electronics sales representative for availability and additional information. document no. m15874ej6v0ds00 (6th edition) date published november 2005 ns cp (k) printed in japan mos integrated circuit pd4632312a-x 32m-bit cmos mobile specified ram 2m-word by 16-bit extended temperature operation preliminary data sheet the mark shows major revised points. 2001, 2005 description the pd4632312a-x is a high speed, low power, 33,554,432 bits (2,097,152 words by 16 bits) cmos mobile specified ram featuring low po wer static ram compatible f unction and pin configuration. the pd4632312a-x is fabricated with advanced cmos te chnology using one-transistor memory cell. features ? 2,097,152 words by 16 bits organization ? fast access time: 60, 65, 75, 85 ns (max.) ? fast page access time: 18, 25, 30 ns (max.) ? byte data control: /lb (i/o0 to i/o7), /ub (i/o8 to i/o15) ? low voltage operation: 2. 7 to 3.1 v (-b60x, -b65x) 2.7 to 3.1 v (chip), 1.65 to 2.1 v (i/o) (-be75x, -be85x) ? operating ambient temperature: t a = ?25 to +85 c ? output enable input for easy application ? chip enable input: /cs pin ? standby mode input: mode pin ? standby mode1: normal standby (memory cell data hold valid) ? standby mode2: density of memo ry cell data hold is variable pd4632312a access operating supply operating supply current time voltage ambient at operating at standby a (max.) ns (max.) v temperature ma (max.) density of data hold chip i/o c 32m bits 16m bits 8m bits 4m bits 0m bit -b60x note , -b65x note 60, 65 2.7 to 3.1 ? ?25 to +85 50 100 70 60 50 30 -be75x note , -be85x note 75, 85 2.7 to 3.1 1.65 to 2.1 45 note under development
preliminary data sheet m15874ej6v0ds 2 pd4632312a-x ordering information pd4632312a-x is mainly shipping by wafer. please consult with our sales offices fo r package samples and ordering information.
preliminary data sheet m15874ej6v0ds 3 pd4632312a-x pin configuration the following are pin configurations of package sample. /xxx indicates active low signal. 48-pin tape fbga (8 x 6) [ -b60x ] [ -b65x ] a b c d e f g h 1 2 3 4 5 6 bottom view 6 5 4 3 2 1 top view 1 2 3 4 5 6 6 5 4 3 2 1 a /lb /oe a0 a1 a2 mode a mode a2 a1 a0 /oe /lb b i/o8 /ub a3 a4 /cs i/o0 b i/o0 /cs a4 a3 /ub i/o8 c i/o9 i/o10 a5 a6 i/o1 i/o2 c i/o2 i/o1 a6 a5 i/o10 i/o9 d gnd i/o11 a17 a7 i/o3 v cc dv cc i/o3 a7 a17 i/o11 gnd e v cc i/o12 nc a16 i/o4 gnd e gnd i/o4 a16 nc i/o12 v cc f i/o14 i/o13 a14 a15 i/o5 i/o6 f i/o6 i/o5 a15 a14 i/o13 i/o14 g i/o15 a19 a12 a13 /we i/o7 g i/o7 /we a13 a12 a19 i/o15 h a18 a8 a9 a10 a11 a20 h a20 a11 a10 a9 a8 a18 note some signals can be applied because this pin is not internally connected. remark refer to package drawing for the index mark. a0 to a20 : address inputs i/o0 to i/o15 : data inputs / outputs /cs : chip select mode : standby mode /we : write enable /oe : output enable /lb, /ub : byte data select v cc : power supply gnd : ground nc note : no connection
preliminary data sheet m15874ej6v0ds 4 pd4632312a-x 48-pin tape fbga (8 x 6) [ -be75x ] [ -be85x ] a b c d e f g h 1 2 3 4 5 6 bottom view 6 5 4 3 2 1 top view 1 2 3 4 5 6 6 5 4 3 2 1 a /lb /oe a0 a1 a2 mode a mode a2 a1 a0 /oe /lb b i/o8 /ub a3 a4 /cs i/o0 b i/o0 /cs a4 a3 /ub i/o8 c i/o9 i/o10 a5 a6 i/o1 i/o2 c i/o2 i/o1 a6 a5 i/o10 i/o9 d gnd i/o11 a17 a7 i/o3 v cc dv cc i/o3 a7 a17 i/o11 gnd e v cc q i/o12 nc a16 i/o4 gnd e gnd i/o4 a16 nc i/o12 v cc q f i/o14 i/o13 a14 a15 i/o5 i/o6 f i/o6 i/o5 a15 a14 i/o13 i/o14 g i/o15 a19 a12 a13 /we i/o7 g i/o7 /we a13 a12 a19 i/o15 h a18 a8 a9 a10 a11 a20 h a20 a11 a10 a9 a8 a18 note some signals can be applied because this pin is not internally connected. remark refer to package drawing for the index mark. a0 to a20 : address inputs i/o0 to i/o15 : data inputs / outputs /cs : chip select mode : standby mode /we : write enable /oe : output enable /lb, /ub : byte data select v cc : power supply v cc q : input / output power supply gnd : ground nc note : no connection
preliminary data sheet m15874ej6v0ds 5 pd4632312a-x block diagram a0 a20 i/o8 to i/o15 /we /oe /ub /lb i/o0 to i/o7 v cc v cc q gnd mode refresh counter refresh control standby mode control address buffer address buffer row decoder memory cell array 33,554,432 bits input data controller sense amplifier / switching circuit column decoder output data controller /cs remark v cc q is the input / output power supply for -be75x and -be85x.
preliminary data sheet m15874ej6v0ds 6 pd4632312a-x truth table /cs mode /oe /we /lb /ub mode i/o supply i/o0 to i/o7 i/o8 to i/o15 current h h not selected (standby mode 1) high-z high-z i sb1 h h h not selected (standby mode 1) high-z high-z l not selected (standby mode 2) note high-z high-z i sb2 l h h h output disable high-z high-z i cca l h l l word read d out d out l h lower byte read d out high-z h l upper byte read high-z d out h l l l word write d in d in l h lower byte write d in high-z h l upper byte write high-z d in note mode pin must be fixed to high le vel except standby mode 2. (refer to 2.3 standby mode status transition ). remark : v ih or v il , h: v ih , l: v il
preliminary data sheet m15874ej6v0ds 7 pd4632312a-x contents 1. initia lizatio n ............................................................................................................. ....................................................... 8 2. partia l refr esh ............................................................................................................ ................................................... 9 2.1 standby mode .............................................................................................................. ............................................. 9 2.2 density switch ing ......................................................................................................... ............................................. 9 2.3 standby mode st atus trans ition ............................................................................................ ................................... 9 2.4 addresses for which pa rtial refresh is suppor ted .......................................................................... ....................... 10 3. page read operat ion........................................................................................................ ........................................... 11 3.1 features of page read o peratio n ........................................................................................... ............................... 11 3.2 p age lengt h............................................................................................................... ............................................. 11 3.3 page-corres ponding addr esses .............................................................................................. ............................... 11 3.4 page star t addr ess ........................................................................................................ ......................................... 11 3.5 page directi on............................................................................................................ ............................................. 11 3.6 interrupt during page read o peratio n ...................................................................................... .............................. 11 3.7 when page read is not used ................................................................................................ ................................... 11 4. mode regi ster se ttings ..................................................................................................... ........................................... 12 4.1 mode register setting method.............................................................................................. .................................. 12 4.2 cautions for setting mode regist er ........................................................................................ ................................ 13 5. electrical specific ations.................................................................................................. .............................................. 14 6. timi ng char ts.............................................................................................................. ................................................. 19 7. package drawin g ............................................................................................................ ............................................. 29 8. recommended sol dering c onditi ons ........................................................................................... ................................ 30 9. revisi on histo ry ........................................................................................................... ................................................ 31
preliminary data sheet m15874ej6v0ds 8 pd4632312a-x 1. initialization initialize the pd4632312a-x at power application using the follo wing sequence to stabilize internal circuits. (1) following power application, make mode high level after fixing mode to low level for the period of t vhmh . make /cs high level before making mode high level. (2) /cs and mode are fixed to high level for the period of t mhcl . normal operation is possible after t he completion of initialization. figure1-1. initialization timing chart /cs (input) v cc mode (input) t mhcl initialization t chmh t vhmh v cc (min.) normal operation cautions 1. make mode low level when starting the power supply. 2. t vhmh is specified from when the power supply voltage reaches the prescr ibed minimum value (v cc (min.)). initialization timing parameter symbol min. max. unit power application to mode low level hold t vhmh 50 s /cs high level to mode high level t chmh 0 ns following power application mode high level hold to /cs low level t mhcl 200 s
preliminary data sheet m15874ej6v0ds 9 pd4632312a-x 2. partial refresh 2.1 standby mode in addition to the regular standby m ode (standby mode 1) with a 32m bits density, standby mode 2, which performs partial refresh, is also provided. 2.2 density switching in standby mode 2, the densities that can be selected for performing refresh are 16m bits, 8m bits, 4m bits, and 0m bit. the density for performing refresh can be set with the mode register. once the refresh density has been set in the mode register, these settings are retained until they are set again, while applying the power supply. however, the mode register setting will become undefined if the power is turned off, so set the mode register again after power application. (for how to perform mode register settings, refer to section 4. mode register settings .) 2.3 standby mode status transition in standby mode 1, mode and /cs are high level, or mode, /lb and /ub are hi gh level. in standby mode 2, mode is low level. in standby mode 2, if 0m bit is set as the density, it is necessary to perform initialization the same way as after applying power, in order to return to normal operation from standby mode 2. when the densit y has been set to 16m bits, 8m bits, or 4m bits in standby mode 2, it is not necessary to perform initializat ion to return to normal operation from standby mode 2. for the timing charts, refer to figure 6-14. standby mode 2 (data hold: 16m bits / 8m bits / 4m bits) entry / exit timing chart , figure 6-15. standby mode 2 (data not held) entry / exit timing chart .
preliminary data sheet m15874ej6v0ds 10 pd4632312a-x figure 2-1. standby mode state machine power on active mode = v ih mode = v il mode = v il /cs = v il , mode = v ih standby mode 1 standby mode 2 (16m bits / 8m bits / 4m bits) /cs = v il initial state initialization standby mode 2 (data not held) /cs = v il , mode = v ih mode = v il mode = v il mode = v ih , /cs = v ih or /lb, /ub = v ih 2.4 addresses for which part ial refresh is supported data hold density correspondence address 16m bits 000000h to 0fffffh 8m bits 000000h to 07ffffh 4m bits 000000h to 03ffffh
preliminary data sheet m15874ej6v0ds 11 pd4632312a-x 3. page read operation 3.1 features of page read operation features 8 words mode page length 8 words page read-corresponding addresses a2, a1, a0 page read start address don?t care page direction don?t care interrupt during page read operation enabled note note an interrupt is output when /cs = h or in case a3 or a higher address changes. 3.2 page length 8 words is supported as the page lengths. 3.3 page-corresponding addresses the page read-enabled addresses are a2, a1, and a0. fi x addresses other than a2, a1, and a0 during page read operation. 3.4 page start address since random page read is supported, any address (a2, a1, a0) can be used as the page read start address. 3.5 page direction since random page read is possible, there is not restriction on the page direction. 3.6 interrupt during page read operation when generating an interrupt during page read, either make /cs high leve l or change a3 and higher addresses. 3.7 when page read is not used since random page read is support ed, even when not using page read, r andom access is possible as usual.
preliminary data sheet m15874ej6v0ds 12 pd4632312a-x 4. mode register settings the partial refresh density can be set using the mode register. sinc e the initial value of t he mode register at power application is undefined, be sure to set t he mode register after init ialization at power applicat ion. when setting the density of partial refresh, data befor e entering the partial refres h mode is not guaranteed. (this is the same for re-setup.) however, since partial refresh mode is not entered unless mode = l when partial refr esh is not used, it is not necessary to set the mode register. moreover, when using page read without using partial refres h, it is not necessary to set the mode register. 4.1 mode register setting method the mode register setting mode can be entered by successively writing two specific data a fter two continuous reads of the highest address (1fffffh). the mode register setting is a c ontinuous four-cycle operati on (two read cycles and two write cycles). commands are written to the command register. the command register is used to latch the addresses and data required for executing commands, and it does not have an exclusive memory area. for the timing chart and flow chart, refer to figure 6-12. mode register setting timing chart , figure 6-13. mode register setting flow chart . table 4-1. shows the commands and command sequences. table 4-1. command sequence command sequence 1st bus cycle 2nd bus cy cle 3rd bus cycle 4th bus cycle (read cycle) (read cycle) (write cycle) (write cycle) partial refresh density address data addr ess data address data address data 16m bits 1fffffh ? 1fffffh ? 1fffffh 00h 1fffffh 04h 8m bits 1fffffh ? 1fffffh ? 1fffffh 00h 1fffffh 05h 4m bits 1fffffh ? 1fffffh ? 1fffffh 00h 1fffffh 06h 0m bit 1fffffh ? 1fffffh ? 1fffffh 00h 1fffffh 07h 4th bus cycle (write cycle) i/o 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 mode register setting 0 0 0 0 0 0 0 0 0 0 0 0 0 pl pd page length 1 8 words i/o1 i/o0 density partial refresh 0 0 16m bits density 0 1 8m bits 1 0 4m bits 1 1 0m bit
preliminary data sheet m15874ej6v0ds 13 pd4632312a-x 4.2 cautions for setting mode register since, for the mode register setting, the internal counter status is judged by toggling /cs and /oe, toggle /cs at every cycle during entry (read cycle twice, write cycle twice), and toggle /oe like /cs at the first and second read cycles. if incorrect addresses or data are writt en, or if addresses or data are written in the incorrect order, the setting of the mode register are not performed correctly. when the highest address (1fffffh) is read consecutively three or more times, the mode register setting entries are cancelled. once the refresh density has been set in the mode register, these settings are retained until they are set again, while applying the power supply. however, the mode register setting will become undefined if the power is turned off, so set the mode register again after power application. for the timing chart and flow chart, refer to figure 6-12. mode register setting timing chart , figure 6-13. mode register setting flow chart .
preliminary data sheet m15874ej6v0ds 14 pd4632312a-x 5. electrical specifications absolute maximum ratings parameter symbol condition rating unit -b60x, -b65x -be75x, -be85x supply voltage v cc ?0.5 note to +4.0 ?0.5 note to +4.0 v input / output supply voltage v cc q ? ?0.5 note to +4.0 v input / output voltage v t ?0.5 note to v cc + 0.4 (4.0 v max.) ?0.5 note to v cc q + 0.4 (4.0 v max.) v operating ambient temperature t a ?25 to +85 ?25 to +85 c storage temperature t stg ?55 to +125 ?55 to +125 c note ?1.0 v (min.) (pulse width: 30 ns) caution exposing the device to stress above those listed in absolute maximum rating could cause permanent damage. the device is not meant to be operated under condi tions outside the limits described in the operational section of this specification. exposur e to absolute maximu m rating conditions for extended periods may a ffect device reliability. recommended operating conditions parameter symbol condition -b60x , -b65x -be75x, -be85x unit min. max. min. max. supply voltage v cc 2.7 3.1 2.7 3.1 v input / output supply voltage v cc q ? ? 1.65 2.1 v high level input voltage v ih 0.8v cc v cc +0.3 0.8v cc q v cc q+0.3 v low level input voltage v il ?0.3 note 0.2v cc ?0.3 note 0.2v cc q v operating ambient temperature t a ?25 +85 ?25 +85 c note ?0.5 v (min.) (pulse width: 30 ns) capacitance (t a = 25 c, f = 1 mhz) parameter symbol test condition min. typ. max. unit input capacitance c in v in = 0 v 8 pf input / output capacitance c i/o v i/o = 0 v 10 pf remarks 1. v in : input voltage, v i/o : input / output voltage 2. these parameters ar e not 100% tested.
preliminary data sheet m15874ej6v0ds 15 pd4632312a-x dc characteristics (recommended operating c onditions unless otherwise noted) (1/2) parameter symbol test conditi on density of -b60x, -b65x unit data hold min. typ. max. input leakage current i li v in = 0 v to v cc ?1.0 +1.0 a i/o leakage current i lo v i/o = 0 v to v cc , /cs = v ih or ?1.0 +1.0 a /we = v il or /oe = v ih operating supply current i cca /cs = v il , minimum cycle time, i i/o = 0 ma 50 ma standby supply current i sb1 /cs v cc ? 0.2 v, mode v cc ? 0.2 v 32m bits 100 a i sb2 /cs v cc ? 0.2 v, mode 0.2 v 16m bits 70 8m bits 60 4m bits 50 0m bit 30 high level output voltage v oh i oh = ?0.5 ma 0.8v cc v low level output voltage v ol i ol = 1 ma 0.2v cc v remark v in : input voltage, v i/o : input / output voltage dc characteristics (recommended operating c onditions unless otherwise noted) (2/2) parameter symbol test condition density of -be75x, -be85x unit data hold min. typ. max. input leakage current i li v in = 0 v to v cc q ?1.0 +1.0 a i/o leakage current i lo v i/o = 0 v to v cc q, /cs = v ih or ?1.0 +1.0 a /we = v il or /oe = v ih operating supply current i cca /cs = v il , minimum cycle time, i i/o = 0 ma 45 ma standby supply current i sb1 /cs v cc q ? 0.2 v, mode v cc q ? 0.2 v 32m bits 100 a i sb2 /cs v cc q ? 0.2 v, mode 0.2 v 16m bits 70 8m bits 60 4m bits 50 0m bit 30 high level output voltage v oh i oh = ?0.5 ma 0.8v cc q v low level output voltage v ol i ol = 1 ma 0.2v cc q v remark v in : input voltage, v i/o : input / output voltage
preliminary data sheet m15874ej6v0ds 16 pd4632312a-x ac characteristics (recommended operati ng conditions unless otherwise noted) ac test conditions [ -b60x, -b65x ] input waveform (rise and fall time 5 ns) test points 0.2vcc 0.8vcc vcc / 2 vcc / 2 vcc gnd 5ns output waveform test points vcc / 2 vcc / 2 [ -be75x, -be85x ] input waveform (rise and fall time 5 ns) test points 0.2vccq 0.8vccq vccq / 2 vccq / 2 vccq gnd 5ns output waveform test points vccq / 2 vccq / 2 output load ac characteristics directed with the note should be measured wi th the output load shown in figure 5-1, figure 5-2 . figure 5-1. figure 5-2. [ -b60x, -b65x ] [ -be75x, -be85x ] c l : 30 pf c l : 30 pf 5 pf (t clz , t olz , t blz , t chz , t ohz , t bhz ) 5 pf (t clz , t olz , t blz , t chz , t ohz , t bhz ) i/o (output) 50 ? z o = 50 ? c l v cc / 2 i/o (output) 50 ? z o = 50 ? c l v cc q / 2 remark c l includes capacitance of the pr obe and jig, and stray capacitance.
preliminary data sheet m15874ej6v0ds 17 pd4632312a-x read cycle parameter symbol -b60x -b65x -be75x -be85x unit note min. max. min. max. min. max. min. max. read cycle time t rc 65 65 75 85 ns 1 address access time t aa 60 65 75 85 ns /cs access time t acs 63 65 75 85 ns /oe to output valid t oe 45 45 50 55 ns /lb, /ub to output valid t ba 63 65 75 85 ns output hold from address change t oh 5 5 5 5 ns page read cycle time t prc 18 18 25 30 ns page access time t paa 18 18 25 30 ns /cs to output in low impedance t clz 10 10 10 10 ns 2 /oe to output in low impedance t olz 5 5 5 5 ns /lb, /ub to output in low impedance t blz 5 5 5 5 ns /cs to output in high impedance t chz 25 25 25 25 ns /oe to output in high impedance t ohz 25 25 25 25 ns /lb, /ub to output in high impedance t bhz 25 25 25 25 ns address set to /oe low level t aso 0 0 0 0 ns /oe high level to address hold t ohah ?5 ?5 ?5 ?5 ns /cs high level to address hold t chah 0 0 0 0 ns 3 /lb, /ub high level to address hold t bhah 0 0 0 0 ns 3, 4 /cs low level to /oe low level t clol 0 10,000 0 10,000 0 10,000 0 10,000 ns 5 /oe low level to /cs high level t olch 45 45 50 55 ns /cs high level pulse width t cp 10 10 10 10 ns /lb, /ub high level pulse width t bp 10 10 10 10 ns /oe high level pulse width t op 2 10,000 2 10,000 2 10,000 2 10,000 ns 5 notes 1. output load: 30 pf 2. output load: 5 pf 3. when t aso | t chah |, | t bhah |, t chah and t bhah (min.) are ?15 ns. t chah , t bhah t aso /lb, /ub, /cs (input) address (input) /oe (input) 4. t bhah is specified from when both /lb and /ub become high level. 5. t clol and t op (max.) are applied while /cs is being hold at low level.
preliminary data sheet m15874ej6v0ds 18 pd4632312a-x write cycle parameter symbol -b60x -b65x -be75x -be85x unit note min. max. min. max. min. max. min. max. write cycle time t wc 65 65 75 85 ns /cs to end of write t cw 55 55 60 70 ns address valid to end of write t aw 55 55 60 70 ns /lb, /ub to end of write t bw 55 55 60 70 ns write pulse width t wp 50 50 55 60 ns write recovery time t wr 0 0 0 0 ns /cs pulse width t cp 10 10 10 10 ns /lb, /ub high level pulse width t bp 10 10 10 10 ns /we high level pulse width t whp 10 10 10 10 ns address setup time t as 0 0 0 0 ns /oe high level to address hold t ohah ?5 ?5 ?5 ?5 ns /cs high level to address hold t chah 0 0 0 0 ns 1 /lb, /ub high level to address hold t bhah 0 0 0 0 ns 1, 2 data valid to end of write t dw 30 30 35 35 ns data hold time t dh 0 0 0 0 ns /oe high level to /we set t oes 0 10,000 0 10,000 0 10,000 0 10,000 ns 3 /we high level to /oe set t oeh 10 10,000 10 10,000 10 10,000 10 10,000 ns notes 1. when t as | t chah |, | t bhah | and t cp 18 ns, t chah and t bhah (min.) are ?15 ns. t chah , t bhah t as /lb, /ub, /cs (input) address (input) /we (input) 2. t bhah is specified from when both /lb and /ub become high level. 3. t oes and t oeh (max.) are applied while /cs is being hold at low level.
preliminary data sheet m15874ej6v0ds 19 pd4632312a-x 6. timing charts figure 6-1. read cycle timing chart 1 (/cs controlled) /cs (input) address (input) data out q2 i/o (output) high-z high-z high-z t rc /oe (input) l l data out q1 t rc t acs t acs t cp a1 a2 a3 t cp t clz t clz t chz t chz t chah t chah /lb, /ub (input) remark in read cycle, mode and /we should be fixed to high level. figure 6-2. read cycle timing chart 2 (/oe controlled) /cs (input) address (input) data out q2 i/o (output) high-z high-z high-z t rc /oe (input) t aso data out q1 t oe t rc t aa t aso t oe t aso t op t op a1 a2 a3 t ohz t olz t ohz t olz t ohah t ohah t aa /lb, /ub (input) t bhah t bhah l remark in read cycle, mode and /we should be fixed to high level.
preliminary data sheet m15874ej6v0ds 20 pd4632312a-x figure 6-3. read cycle timing chart 3 (/cs, /oe controlled) /cs (input) address (input) data out q2 i/o (output) high-z high-z high-z t rc /oe (input) data out q1 t rc t acs t aa t olch a1 a2 a3 t clz t oe t ohz t chz t ohah t chah /lb, /ub (input) t clol t olz t ohz t ohah t aso t olz t oe t bhah t bhah remark in read cycle, mode and /we should be fixed to high level. figure 6-4. read cycle timing chart 4 (address controlled) /cs (input) address (input) data out q2 i/o (output) t rc /oe (input) data out q1 t aa a1 a2 a3 t rc t aa t oh t oh t oh /lb, /ub (input) l l l remark in read cycle, mode and /we should be fixed to high level.
preliminary data sheet m15874ej6v0ds 21 pd4632312a-x figure 6-5. read cycle timing chart 5 (/lb, /ub controlled) /cs (input) address (input) i/o (output) high-z high-z high-z t rc /oe (input) t rc a1 a2 a3 t bhah t bhah /lb, /ub (input) t ba t bhz data out q1 t blz t ba t bhz data out q2 t blz t bp t bp l l remark in read cycle, mode and /we should be fixed to high level. figure 6-6. page read cycle timing chart i/o (output) address (a3 to a20) (input) page address (a0 to a2) (input) /cs (input) /oe (input) t prc t prc t prc t rc t paa t oh t paa t oh t paa t oh t aa t oe t oh a n+1 a n+2 a n+3 a n+7 q n q n+1 q n+2 q n+3 q n+7 t chz t ohz a n t paa t oh t prc t paa t oh t prc t paa t oh t prc t paa t oh q n+4 q n+5 q n+6 a n+4 a n+5 a n+6 t prc high-z remarks 1. in read cycle, mode and /we should be fixed to high level. 2. /lb and /ub are low level.
preliminary data sheet m15874ej6v0ds 22 pd4632312a-x figure 6-7. write cycle timing chart 1 (/cs controlled) t wc t as t wc t as t as a1 a2 a3 t cw t cw t wr t wr t cp t cp /cs (input) address (input) /we (input) /lb, /ub (input) data in d2 data in d1 t dw t dh t dw t dh /oe (input) t aso t ohah t oes t oeh i/o (input) high-z high-z high-z l l cautions 1. during address transition, at least one of pins /cs and /we, or both of /lb and /ub pins should be inactivated. 2. do not input data to the i/o pins while they are in the output state. 3. in write cycle, mode and /oe should be fixed to high level. remark write operation is done during the overlap time of a low level /cs, /we, /lb and/or /ub.
preliminary data sheet m15874ej6v0ds 23 pd4632312a-x figure 6-8. write cycle timing chart 2 (/we controlled) data in d2 t wc t as data in d1 t wc t as t whp a1 a2 a3 t cw t wr t cw t dw t dh t dw t dh t wp t wp /oe (input) t cp t aso t ohah t oes t oeh t bhah t bhah t wr t cp t chah t chah /cs (input) address (input) i/o (input) high-z high-z high-z /we (input) /lb, /ub (input) cautions 1. during address transition, at least one of pins /cs and /we, or both of /lb and /ub pins should be inactivated. 2. do not input data to the i/o pins while they are in the output state. 3. in write cycle, mode and /oe should be fixed to high level. remark write operation is done during the overlap time of a low level /cs, /we, /lb and/or /ub.
preliminary data sheet m15874ej6v0ds 24 pd4632312a-x figure 6-9. write cycle timing chart 3 (/we controlled) t wc t as t wc t as t aso a1 a2 a3 t wr t wr /oe (input) t ohah t oes t oeh t whp t aw t aw t dw t dh t dw t dh t wp t wp t bhah t bhah /cs (input) address (input) data in d2 i/o (input) high-z high-z high-z /we (input) data in d1 /lb, /ub (input) l cautions 1. during address transition, at least one of pins /cs and /we, or both of /lb and /ub pins should be inactivated. 2. do not input data to the i/o pins while they are in the output state. 3. in write cycle, mode and /oe should be fixed to high level. remark write operation is done during the overlap time of a low level /cs, /we, /lb and/or /ub.
preliminary data sheet m15874ej6v0ds 25 pd4632312a-x figure 6-10. write cycle timing chart 4 (/lb, /ub controlled) t wc t as t wc t as a1 a2 a3 t wr t wr t dw t dh t dw t dh t bw t bw t bp t bp t aso /oe (input) t ohah t oes t oeh /cs (input) address (input) data in d2 i/o (input) high-z high-z high-z /we (input) data in d1 /lb, /ub (input) l cautions 1. during address transition, at least one of pins /cs and /we, or both of /lb and /ub pins should be inactivated. 2. do not input data to the i/o pins while they are in the output state. 3. in write cycle, mode and /oe should be fixed to high level. remark write operation is done during the overlap time of a low level /cs, /we, /lb and/or /ub.
preliminary data sheet m15874ej6v0ds 26 pd4632312a-x figure 6-11. write cycle timing chart 5 (/lb, /ub independent controlled) t wc t as t wc t as a1 a2 a3 t wr t wr t dw t dh t dw t dh t bw t bw t aso /oe (input) t ohah t oes t oeh t bp /cs (input) address (input) data in d2 i/o0 to i/o7 (input) high-z high-z high-z high-z /we (input) data in d1 /lb (input) /ub (input) i/o8 to i/o15 (input) l cautions 1. during address transition, at least one of pins /cs and /we, or both of /lb and /ub pins should be inactivated. 2. do not input data to the i/o pins while they are in the output state. 3. in write cycle, mode and /oe should be fixed to high level. remark write operation is done during the overlap time of a low level /cs, /we, /lb and/or /ub.
preliminary data sheet m15874ej6v0ds 27 pd4632312a-x figure 6-12. mode register setting timing chart /lb, /ub (input) /we (input) /cs (input) address (input) /oe (input) i/o (input) t rc t rc t wc t wc 1fffffh t wp t wr t wp t wr t dw t dh t dw t dh 1fffffh 1fffffh 1fffffh xxxxh xxxxh mode register setting high-z high-z high-z figure 6-13. mode register setting flow chart start end address= 1fffffh read with toggled the /cs, /oe address = 1fffffh write data = 00h? no mode register setting exit fail address = 1fffffh write data = xxh? no note note xxh = 04h, 05h, 06h, 07h no no no no address= 1fffffh read with toggled the /cs, /oe
preliminary data sheet m15874ej6v0ds 28 pd4632312a-x figure 6-14. standby mode 2 (data hold: 16m bits / 8m bits / 4m bits) entry / exit timing chart /cs (input) t chml t mhcl1 mode (input) standby mode 1 standby mode 2 (data hold: 16m bits / 8m bits / 4m bits) figure 6-15. standby mode 2 (data not held) entry / exit timing chart /cs (input) t chml t mhcl2 mode (input) standby mode 1 standby mode 2 (data not held) standby mode 2 entry / exit timing parameter symbol min. max. unit note standby mode 2 entry t chml 0 ns /cs high level to mode low level standby mode 2 exit to normal operation t mhcl1 30 ns 1 mode high level to /cs low level standby mode 2 exit to normal operation t mhcl2 200 s 2 mode high level to /cs low level notes 1. this is the time it takes to retu rn to normal operation from standby mode 2 (data hold: 16m bits / 8m bits / 4m bits). 2. this is the time it takes to return to normal operation from standby mode 2 (data not held).
preliminary data sheet m15874ej6v0ds 29 pd4632312a-x 7. package drawing the following is a package drawing of package sample. s wb s wa 6 5 4 3 2 1 a b a b c d e f g h s y s y1 m s b x ab s 48-pin tape fbga (8x6) item millimeters d e 8.0 0.1 6.0 0.1 w a 0.2 0.94 0.10 b x 0.08 y 0.1 e 0.75 a1 0.24 0.05 a2 0.70 0.40 0.05 index mark index mark a a2 a1 ze zd y1 0.2 zd 1.125 ze 1.375 p48f9-75-bc2 e e d
preliminary data sheet m15874ej6v0ds 30 pd4632312a-x 8. recommended soldering conditions please consult with our sales offi ces for soldering conditions of the pd4632312a-x package sample. type of surface mount device pd4632312af9-bc2: 48-pin tape fbga (8 x 6)
preliminary data sheet m15874ej6v0ds 31 pd4632312a-x 9. revision history edition/ page type of location description date this previous revision (previous edition this edition) edition edition 6th edition/ throughout throughout modification part number the part numbers have been uncarried. nov. 2005 ? ?note? has been added to -b65x.
preliminary data sheet m15874ej6v0ds 32 pd4632312a-x [memo]
preliminary data sheet m15874ej6v0ds 33 pd4632312a-x [memo]
preliminary data sheet m15874ej6v0ds 34 pd4632312a-x [memo]
preliminary data sheet m15874ej6v0ds 35 pd4632312a-x 1 2 3 4 voltage application waveform at input pin waveform distortion due to input noise or a reflected wave may cause malfunction. if the input of the cmos device stays in the area between v il (max) and v ih (min) due to noise, etc., the device may malfunction. take care to prevent chattering noise from entering the device when the input level is fixed, and also in the transition period when the input level passes through the area between v il (max) and v ih (min). handling of unused input pins unconnected cmos device inputs can be cause of malfunction. if an input pin is unconnected, it is possible that an internal input level may be generated due to noise, etc., causing malfunction. cmos devices behave differently than bipolar or nmos devices. input levels of cmos devices must be fixed high or low by using pull-up or pull-down circuitry. each unused pin should be connected to v dd or gnd via a resistor if there is a possibility that it will be an output pin. all handling related to unused pins must be judged separately for each device and according to related specifications governing the device. precaution against esd a strong electric field, when exposed to a mos device, can cause destruction of the gate oxide and ultimately degrade the device operation. steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it when it has occurred. environmental control must be adequate. when it is dry, a humidifier should be used. it is recommended to avoid using insulators that easily build up static electricity. semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. all test and measurement tools including work benches and floors should be grounded. the operator should be grounded using a wrist strap. semiconductor devices must not be touched with bare hands. similar precautions need to be taken for pw boards with mounted semiconductor devices. status before initialization power-on does not necessarily define the initial status of a mos device. immediately after the power source is turned on, devices with reset functions have not yet been initialized. hence, power-on does not guarantee output pin levels, i/o settings or contents of registers. a device is not initialized until the reset signal is received. a reset operation must be executed immediately after power-on for devices with reset functions. power on/off sequence in the case of a device that uses different power supplies for the internal operation and external interface, as a rule, switch on the external power supply after switching on the internal power supply. when switching the power supply off, as a rule, switch off the external power supply and then the internal power supply. use of the reverse power on/off sequences may result in the application of an overvoltage to the internal elements of the device, causing malfunction and degradation of internal elements due to the passage of an abnormal current. the correct power on/off sequence must be judged separately for each device and according to related specifications governing the device. input of signal during power off state do not input signals or an i/o pull-up power supply while the device is not powered. the current injection that results from input of such a signal or i/o pull-up power supply may cause malfunction and the abnormal current that passes in the device at this time may cause degradation of internal elements. input of signals during the power off state must be judged separately for each device and according to related specifications governing the device. notes for cmos devices 5 6
pd4632312a-x the information in this document is current as of november, 2005. the information is subject to change without notice. for actual design-in, refer to the latest publications of nec electronics data sheets or data books, etc., for the most up-to-date specifications of nec electronics products. not all products and/or types are available in every country. please check with an nec electronics sales representative for availability and additional information. no part of this document may be copied or reproduced in any form or by any means without the prior written consent of nec electronics. nec electronics assumes no responsibility for any errors that may appear in this document. nec electronics does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of nec electronics products listed in this document or any other liability arising from the use of such products. no license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of nec electronics or others. descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. the incorporation of these circuits, software and information in the design of a customer's equipment shall be done under the full responsibility of the customer. nec electronics assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. while nec electronics endeavors to enhance the quality, reliability and safety of nec electronics products, customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. to minimize risks of damage to property or injury (including death) to persons arising from defects in nec electronics products, customers must incorporate sufficient safety measures in their design, such as redundancy, fire-containment and anti-failure features. nec electronics products are classified into the following three quality grades: "standard", "special" and "specific". the "specific" quality grade applies only to nec electronics products developed based on a customer- designated "quality assurance program" for a specific application. the recommended applications of an nec electronics product depend on its quality grade, as indicated below. customers must check the quality grade of each nec electronics product before using it in a particular application. the quality grade of nec electronics products is "standard" unless otherwise expressly specified in nec electronics data sheets or data books, etc. if customers wish to use nec electronics products in applications not intended by nec electronics, they must contact an nec electronics sales representative in advance to determine nec electronics' willingness to support a given application. (note) ? ? ? ? ? ? m8e 02. 11-1 (1) (2) "nec electronics" as used in this statement means nec electronics corporation and also includes its majority-owned subsidiaries. "nec electronics products" means any product developed or manufactured by or for nec electronics (as defined above). computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots. transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support). aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems and medical equipment for life support, etc. "standard": "special": "specific":

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