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?2008 silicon storage technology, inc. s71327-01-000 4/08 1 the sst logo and superflash are registered trademarks of silicon storage technology, inc. these specifications are subject to change without notice. advance information features: ? single voltage read and write operations ? 2.7-3.6v ? serial interface architecture ? spi compatible: mode 0 and mode 3 ? high speed clock frequency ? 66 mhz max ? superior reliability ? endurance: 100,000 cycles (typical) ? greater than 100 years data retention ? low power consumption: ? active read current: 10 ma (typical) ? standby current: 5 a (typical) ? flexible erase capability ? uniform 4 kbyte sectors ? uniform 32 kbyte overlay blocks ? uniform 64 kbyte overlay blocks ? fast erase and byte-program: ? chip-erase time: 35 ms (typical) ? sector-/block-erase time: 18 ms (typical) ? byte-program time: 7 s (typical) ? auto address increment (aai) word programming ? decrease total chip programming time over byte-program operations ? end-of-write detection ? software polling the busy bit in status register ? busy status readout on so pin ? hold pin (hold#) ? suspends a serial sequence to the memory without deselecting the device ? write protection (wp#) ? enables/disables the lock-down function of the status register ? software write protection ? write protection through block-protection bits in status register ? temperature range ? commercial: 0c to +70c ? industrial: -40c to +85c ? packages available ? 8-lead soic (200 mils) ? 16-lead soic (300 mils) ? all non-pb (lead-free) devices are rohs compliant product description the sst 25 series serial flash family features a four-wire, spi-compatible interface that allows for a low pin-count package which occupies less board space and ultimately lowers total system costs. sst25vf032b spi serial flash memories are manufactured with sst?s proprietary, high- performance cmos superflash technology. the split-gate cell design and thick-oxide tunneling injector attain better reliability and manufacturability compared with alternate approaches. the sst25vf032b devices significantly improve perfor- mance and reliability, while lowering power consumption. the devices write (program or erase) with a single power supply of 2.7-3.6v for sst25vf032b. the total energy consumed is a function of the applied voltage, current, and time of application. since for any given voltage range, the superflash technology uses less current to program and has a shorter erase time, the total energy consumed during any erase or program operation is less than alternative flash memory technologies. the sst25vf032b device is offered in both 8-lead soic (200 mils) and 16-lead soic ( 300 mils) packages. see fig- ures 2 and 3 for pin assignments. 32 mbit spi serial flash sst25vf032b sst25vf032b32mb serial peripheral interface (spi) flash memory
2 advance information 32 mbit spi serial flash sst25vf032b ?2008 silicon storage technology, inc. s71327-01-000 4/08 figure 1: functional block diagram 1327 b1.0 i/o buffers and data latches superflash memory x - decoder control logic address buffers and latches ce# y - decoder sck si so wp# hold# serial interface note: 1. in aai mode, the so pin can act as a ry/by# pin w hen configured as a ready/bus y status pin. see ?end-of- write detection? on page 12 for details
advance information 32 mbit spi serial flash sst25vf032b 3 ?2008 silicon storage technology, inc. s71327-01-000 4/08 pin description figure 2: pin assignments for 8-lead soic figure 3: pin assignments for 16-lead soic 1 2 3 4 8 7 6 5 ce# so wp# v ss v dd hold# sck si top view 1327 8-soic p1.0 notes: 1. in aai mode, the so pin can act as a ry/by# pin when configured as a ready/bus y status pin. see ?end-of- write detection? on page 12 for details. sck si nc nc nc nc v ss wp# hold# v dd nc nc nc nc ce# so 1327 16-soic p1.0 notes: 1. in aai mode, the so pin can act as a ry/by# pin when configured as a ready/busy status pin. see ?end-of- write detection? on page 12 for details.
4 advance information 32 mbit spi serial flash sst25vf032b ?2008 silicon storage technology, inc. s71327-01-000 4/08 table 1: pin description symbol pin name functions sck serial clock to provide the timing of the serial interface. commands, addresses, or input data are latched on the rising edge of the clock input, while output data is shifted out on the falling edge of the clock input. si serial data input to transfer commands, addresses, or data serially into the device. inputs are latched on the rising edge of the serial clock. so serial data output to transfer data serially out of the device. data is shifted out on the falling edge of the serial clock. ry/by# ready / busy pin flash busy status pin in aai mo de if so is configured as a hardware ry/by# pin. ce# chip enable the device is enabled by a high to low transition on ce#. ce# must remain low for the duration of any command sequence. wp# write protect the write protect (wp#) pin is used to enable/disable bpl bit in the status register. hold# hold to temporarily stop serial communication with spi flash memory without resetting the device. v dd power supply to provide power supply voltage: 2.7-3.6v v ss ground t1.0 1327
advance information 32 mbit spi serial flash sst25vf032b 5 ?2008 silicon storage technology, inc. s71327-01-000 4/08 memory organization the sst25vf032b superflash memory array is orga- nized in uniform 4 kbyte erasable sectors with 32 kbyte overlay blocks and 64 kbyte overlay erasable blocks. device operation the sst25vf032b is accessed through the spi (serial peripheral interface) bus compatible protocol. the spi bus consist of four control lines; chip enable (ce#) is used to select the device, and data is accessed through the serial data input (si), serial data output (so), and serial clock (sck). the sst25vf032b supports both mode 0 (0,0) and mode 3 (1,1) of spi bus operations. the difference between the two modes, as shown in figure 4, is the state of the sck signal when the bus master is in stand-by mode and no data is being transferred. the sck signal is low for mode 0 and sck signal is high for mode 3. for both modes, the serial data in (si) is sampled at the rising edge of the sck clock signal and the serial data output (so) is driven after the falling edge of the sck clock signal. figure 4: spi protocol 1327 f04.0 mode 3 sck si so ce# mode 3 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 mode 0 mode 0 high impedance msb msb don't care
6 advance information 32 mbit spi serial flash sst25vf032b ?2008 silicon storage technology, inc. s71327-01-000 4/08 hold operation the hold# pin is used to pause a serial sequence using the spi flash memory, but without resetting the clocking sequence. to activate the hold# mode, ce# must be in active low state. the hold# mode begins when the sck active low state coincides with the falling edge of the hold# signal. the hold mode ends when the hold# signal?s rising edge coincides wi th the sck active low state. if the falling edge of the hold# signal does not coincide with the sck active low state, then the device enters hold mode when the sck next reaches the active low state. similarly, if the rising edge of the hold# signal does not coincide with the sck active low state, then the device exits from hold mode when the sck next reaches the active low state. see figure 5 for hold condition waveform. once the device enters hold mode, so will be in high- impedance state while si and sck can be v il or v ih. if ce# is driven high during a hold condition, the device returns to standby mode. as long as hold# signal is low, the memory remains in the hold condition. to resume communication with the device, hold# must be driven active high, and ce# must be driven active low. see figure 5 for hold timing. figure 5: hold condition waveform write protection sst25vf032b provides software write protection. the write protect pin (wp#) enables or disables the lock-down function of the status regist er. the block-protection bits (bp3, bp2, bp1, bp0, and bpl) in the status register pro- vide write protection to the memory array and the status register. see table 4 for the block-protection description. write protect pin (wp#) the write protect (wp#) pin enables the lock-down func- tion of the bpl bit (bit 7) in the status register. when wp# is driven low, the execution of the write-status-register (wrsr) instruction is determined by the value of the bpl bit (see table 2). when wp# is high, the lock-down func- tion of the bpl bit is disabled. active hold active hold active 1327 f05.0 sck hold# table 2: conditions to execute write-status- register (wrsr) instruction wp# bpl execute wrsr instruction l 1 not allowed l0allowed hxallowed t2.0 1327
advance information 32 mbit spi serial flash sst25vf032b 7 ?2008 silicon storage technology, inc. s71327-01-000 4/08 status register the software status register provides status on whether the flash memory array is available for any read or write oper- ation, whether the device is write enabled, and the state of the memory write protection. during an internal erase or program operation, the status register may be read only to determine the completion of an operation in progress. table 3 describes the function of each bit in the software status register. busy the busy bit determines whether there is an internal erase or program operation in progress. a ?1? for the busy bit indi- cates the device is busy with an operation in progress. a ?0? indicates the device is ready for the next valid operation. write enable latch (wel) the write-enable-latch bit indicates the status of the inter- nal memory write enable latch. if the write-enable-latch bit is set to ?1?, it indicates the device is write enabled. if the bit is set to ?0? (reset), it in dicates the device is not write enabled and does not accept any memory write (program/ erase) commands. the write-enable-latch bit is automati- cally reset under the following conditions: ? power-up ? write-disable (wrdi) instruction completion ? byte-program instruction completion ? auto address increment (aai) programming is completed or reached its highest unprotected memory address ? sector-erase instruction completion ? block-erase instruction completion ? chip-erase instruction completion ? write-status-register instructions auto address increment (aai) the auto address increment programming-status bit pro- vides status on whether the device is in aai programming mode or byte-program mode. the default at power up is byte-program mode. table 3: software status register bit name function default at power-up read/write 0 busy 1 = internal write operation is in progress 0 = no internal write operation is in progress 0r 1 wel 1 = device is memory write enabled 0 = device is not memory write enabled 0r 2 bp0 indicate current level of block write protection (see table 4) 1 r/w 3 bp1 indicate current level of block write protection (see table 4) 1 r/w 4 bp2 indicate current level of block write protection (see table 4) 1 r/w 5 bp3 indicate current level of block write protection (see table 4) 0 r/w 6 aai auto address increment programming status 1 = aai programming mode 0 = byte-program mode 0r 7 bpl 1 = bp3, bp2, bp1, bp0 are read-only bits 0 = bp3, bp2, bp1, bp 0 are readable/writable 0r/w t3.0 1327
8 advance information 32 mbit spi serial flash sst25vf032b ?2008 silicon storage technology, inc. s71327-01-000 4/08 block protection (bp3,bp2, bp1, bp0) the block-protection (bp3, bp2, bp1, bp0) bits define the size of the memory area, as shown in table 4, to be soft- ware protected against any memory write (program or erase) operation. the write-status-register (wrsr) instruction is used to program the bp3, bp2, bp1 and bp0 bits as long as wp# is high or the block-protect-lock (bpl) bit is 0. chip-erase can only be executed if block- protection bits are all 0. after power-up, bp3, bp2, bp1 and bp0 are set to the defaults specified in table 4. block protection lock-down (bpl) wp# pin driven low (v il ), enables the block-protection- lock-down (bpl) bit. when bpl is set to 1, it prevents any further alteration of the bpl, bp3, bp2, bp1, and bp0 bits. when the wp# pin is driven high (v ih ), the bpl bit has no effect and its value is ?don?t care?. after power-up, the bpl bit is reset to 0. table 4: software status register block protection for sst25vf032b 1 1. x = don?t care (reserved) default is ?0 protection level status register bit 2 2. default at power-up for bp2, bp1, and bp0 is ?111?. (all blocks protected) protected memory address bp3 bp2 bp1 bp0 32 mbit none x 0 0 0 none upper 1/64 x 0 0 1 3f0000h-3fffffh upper 1/32 x 0 1 0 3e0000h-3fffffh upper 1/16 x 0 1 1 3c0000h-3fffffh upper 1/8 x 1 0 0 380000h-3fffffh upper 1/4 x 1 0 1 300000h-3fffffh upper 1/2 x 1 1 0 200000h-3fffffh all blocks x 1 1 1 000000h-3fffffh t4.0 1327
advance information 32 mbit spi serial flash sst25vf032b 9 ?2008 silicon storage technology, inc. s71327-01-000 4/08 instructions instructions are used to read, write (erase and program), and configure the sst25vf032b. the instruction bus cycles are 8 bits each for commands (op code), data, and addresses. the write-enable (wren) instruction must be executed prior any byte-program, auto address increment (aai) programming, sector-erase, block-erase, write-sta- tus-register, or chip-erase instructions. the complete list of instructions is provided in table 5. all instructions are synchronized off a high to low transition of ce#. inputs will be accept ed on the rising edge of sck starting with the most significant bit. ce# must be driven low before an instruction is entered and must be driven high after the last bit of the instruction has been shifted in (except for read, read-id, and read-status-register instructions). any low to high transition on ce#, before receiving the last bit of an instruction bus cycle, will termi- nate the instruction in progress and return the device to standby mode. instruction commands (op code), addresses, and data are all input from the most significant bit (msb) first. table 5: device operation instructions instruction descript ion op code cycle 1 1. one bus cycle is eight clock periods. address cycle(s) 2 2. address bits above the most significant bit can be either v il or v ih . dummy cycle(s) data cycle(s) maximum frequency read read memory 0000 0011b (03h) 3 0 1 to 25 mhz high-speed read r ead memory at higher speed 0 000 1011b (0bh) 3 1 1 to 66 mhz 4 kbyte sector-erase 3 3. 4kbyte sector erase addresses: use a ms -a 12, remaining addresses are don?t care but must be set either at v il or v ih. erase 4 kbyte of memory array 0010 0000b (20h) 3 0 0 66 mhz 32 kbyte block-erase 4 4. 32kbyte block erase addresses: use a ms -a 15, remaining addresses are don?t care but must be set either at v il or v ih. erase 32kbyte block of memory array 0101 0010b (52h) 3 0 0 66 mhz 64 kbyte block-erase 5 5. 64kbyte block erase addresses: use a ms -a 16, remaining addresses are don?t care but must be set either at v il or v ih. erase 64 kbyte block of memory array 1101 1000b (d8h) 3 0 0 66 mhz chip-erase erase full memory array 0110 0000b (60h) or 1100 0111b (c7h) 00066 mhz byte-program to program one data byte 0000 0010b (02h) 3 0 1 66 mhz aai-word-program 6 6. to continue programming to the next sequential address location, enter the 8-bit command, adh, followed by 2 bytes of data to be programmed. data byte 0 will be programmed into the initial address [a 23 -a 1 ] with a 0 =0, data byte 1 will be programmed into the initial address [a 23 -a 1 ] with a 0 = 1. auto address increment programming 1010 1101b (adh) 3 0 2 to 66 mhz rdsr 7 7. the read-status-register is continuous with ongoing clock cycles until terminated by a low to high transition on ce#. read-status-register 0000 0101b (05h) 0 0 1 to 66 mhz ewsr enable-write-status-register 0101 0000b (50h) 0 0 0 66 mhz wrsr write-status-register 0000 0001b (01h) 0 0 1 66 mhz wren write-enable 0000 0110b (06h) 0 0 0 66 mhz wrdi write-disable 0000 0100b (04h) 0 0 0 66 mhz rdid 8 8. manufacturer?s id is read with a 0 = 0, and device id is read with a 0 = 1. all other address bits are 00h. the manufacturer?s id and device id output stream is continuous until te rminated by a low-to-high transition on ce#. read-id 1001 0000b (90h) or 1010 1011b (abh) 301 to 66 mhz jedec-id jedec id read 1001 1111b (9fh) 0 0 3 to 66 mhz ebsy enable so as an output ry/by# status during aai programming 0111 0000b (70h) 0 0 0 66 mhz dbsy disable so as an output ry/by# status during aai programming 1000 0000b (80h) 0 0 0 66 mhz t5.0 1327
10 advance information 32 mbit spi serial flash sst25vf032b ?2008 silicon storage technology, inc. s71327-01-000 4/08 read (25 mhz) the read instruction, 03h, supports up to 25 mhz read. the device outputs the data starting from the specified address location. the data output stream is continuous through all addresses until terminated by a low to high tran- sition on ce#. the internal address pointer will automati- cally increment until the highest memory address is reached. once the highest memory address is reached, the address pointer will auto matically increment to the beginning (wrap-around) of the address space. for exam- ple, once the data from address location 3fffffh has been read, the next output will be from address location 000000h. the read instruction is initiate d by executing an 8-bit com- mand, 03h, followed by address bits [a 23 -a 0 ]. ce# must remain active low for the duration of the read cycle. see figure 6 for the read sequence. figure 6: read sequence high-speed-read (66 mhz) the high-speed-read instruction supporting up to 66 mhz read is initiated by executing an 8-bit command, 0bh, fol- lowed by address bits [a 23 -a 0 ] and a dummy byte. ce# must remain active low for the duration of the high-speed- read cycle. see figure 7 for the high-speed-read sequence. following a dummy cycle, the high-speed-read instruc- tion outputs the data starting from the specified address location. the data output stream is continuous through all addresses until terminated by a low to high transition on ce#. the internal address po inter will automatically incre- ment until the highest memory address is reached. once the highest memory address is reached, the address pointer will automatically incr ement to the beginning (wrap- around) of the address space. for example, once the data from address location 3fffffh has been read, the next output will be from address location 000000h. figure 7: high-speed-read sequence 1327 f06.0 ce# so si sck add. 012345678 add. add. 03 high impedance 15 16 23 24 31 32 39 40 70 47 48 55 56 63 64 n+2 n+3 n+4 n n+1 d out msb msb msb mode 0 mode 3 d out d out d out d out 1327 f07.0 ce# so si sck add. 012345678 add. add. 0b high impedance 15 16 23 24 31 32 39 40 47 48 55 56 63 64 n+2 n+3 n+4 n n+1 x msb mode 0 mode 3 d out d out d out d out 80 71 72 d out
advance information 32 mbit spi serial flash sst25vf032b 11 ?2008 silicon storage technology, inc. s71327-01-000 4/08 byte-program the byte-program instruction programs the bits in the selected byte to the desired data. the selected byte must be in the erased state (ffh) when initiating a program operation. a byte-program instruction applied to a pro- tected memory area will be ignored. prior to any write operation, the write-enable (wren) instruction must be executed. ce# must remain active low for the duration of the byte-program instruction. the byte- program instruction is initiated by executing an 8-bit com- mand, 02h, followed by address bits [a 23 -a 0 ]. following the address, the data is input in order from msb (bit 7) to lsb (bit 0). ce# must be driven high before the instruction is executed. the user may poll the busy bit in the software status register or wait t bp for the completion of the internal self-timed byte-program operation. see figure 8 for the byte-program sequence. figure 8: byte-program sequence 1327 f08.0 ce# so si sck add. 012345678 add. add. d in 02 high impedance 15 16 23 24 31 32 39 msb lsb mode 3 mode 0
12 advance information 32 mbit spi serial flash sst25vf032b ?2008 silicon storage technology, inc. s71327-01-000 4/08 auto address increment (aai) word-program the aai program instruction allo ws multiple bytes of data to be programmed without re-issuing the next sequential address location. this feature decreases total program- ming time when multiple bytes or entire memory array is to be programmed. an aai word program instruction pointing to a protected memory area will be ignored. the selected address range must be in the erased state (ffh) when ini- tiating an aai word program operation. while within aai word programming sequence, the only valid instructions are aai word (adh), rdsr (0 5h), or wrdi (04h). users have three options to determine the completion of each aai word program cycle: hardware detection by reading the serial output, software detection by polling the busy bit in the software status register or wait t bp. refer to end- of-write detection section for details. prior to any write operation, the write-enable (wren) instruction must be executed. the aai word program instruction is initiated by executing an 8-bit command, adh, followed by address bits [a 23 -a 0 ]. following the addresses, two bytes of data is input sequentially, each one from msb (bit 7) to lsb (bit 0). the first byte of data (d0) will be programmed into the initial address [a 23 -a 1 ] with a 0 = 0, the second byte of data (d1) will be programmed into the initial address [a 23 -a 1 ] with a 0 = 1. ce# must be driven high before the aai word program instruction is executed. the user must check the busy status before entering the next valid command. once the device indicates it is no longer busy, data for the next two sequential addresses may be programmed and so on. when the last desired byte had been entered, check the busy status using the hardware method or the rdsr instruction and execute the write-disable (wrdi) instruct ion, 04h, to terminate aai. check the busy status after wrdi to determine if the device is ready for any command. see figures 11 and 12 for aai word programming sequence. there is no wrap mode during aai programming; once the highest unprotected memory address is reached, the device will exit aai operatio n and reset the write-enable- latch bit (wel = 0) and the aai bit (aai = 0). end-of-write detection there are three methods to determine completion of a pro- gram cycle during aai word programming: hardware detection by reading the serial output, software detection by polling the busy bit in the software status register or wait t bp. the hardware end-of-write detection method is described in the section below. hardware end-of-write detection the hardware end-of-write detection method eliminates the overhead of polling the busy bit in the software status register during an aai word program operation. the 8-bit command, 70h, configures the serial output (so) pin to indicate flash busy status during aai word programming, as shown in figure 9. the 8-bit command, 70h, must be executed prior to executing an aai word-program instruc- tion. once an internal programming operation begins, asserting ce# will immediately drive the status of the inter- nal flash status on the so pin. a ?0? indicates the device is busy and a ?1? indicates the device is ready for the next instruction. de-asserting ce# will return the so pin to tri- state. the 8-bit command, 80h, prevents the serial output (so) pin from outputting busy status during aai-word-program operation and re-configures so as an output pin. the device can only accept the 80h command when the device is not in aai mode. once so is an output pin, in aai mode the device can accept both rdsr instruction for polling and software status register data outputs through the so pin. this is shown in figure 10. figure 9: enable so as hardware ry/by# during aai programming figure 10: disable so as hardware ry/by# during aai programming ce# so si sck 01234567 70 high impedance mode 0 mode 3 1327 f09.0 msb ce# so si sck 01234567 80 high impedance mode 0 mode 3 1327 f10.0 msb
advance information 32 mbit spi serial flash sst25vf032b 13 ?2008 silicon storage technology, inc. s71327-01-000 4/08 figure 11: auto address increment (aai) word-program sequence with hardware end-of-write detection figure 12: auto address increment (aai) word-program sequence with software end-of-write detection ce# si sck so d out 1378 aai.hw.1 last 2 data bytes wdri to exit aai mode wait t bp or poll software status register to load any command check for flash busy status to load next valid 1 command load aai command, address, 2 bytes data note: 1. valid commands during aai programming: aai command or wrdi command 2. user must configure the so pin to output flash busy status during aai programming 078 32 47 15 16 23 24 31 0 40 39 7 8 15 16 23 7 8 15 16 23 70 15 78 00 aaa ad d0 ad mode 3 mode 0 d1 d2 d3 ad d n-1 d n wrdi rdsr 078 32 47 15 16 23 24 31 0 40 39 7 8 15 16 23 7 8 15 16 23 70 15 78 00 ce# si sck so d out mode 3 mode 0 1378 aai.sw.1 wait t bp or poll software status register to load any command note: 1. valid commands during aai programming: aai command or wrdi command wait t bp or poll software status register to load next valid 1 command last 2 data bytes wdri to exit aai mode load aai command, address, 2 bytes data aaa ad d0 ad d1 d2 d3 ad d n-1 d n wrdi rdsr
14 advance information 32 mbit spi serial flash sst25vf032b ?2008 silicon storage technology, inc. s71327-01-000 4/08 sector-erase the sector-erase instruction clears all bits in the selected 4 kbyte sector to ffh. a sector-erase instruction applied to a protected memory area will be ignored. prior to any write operation, the write-enable (wren) instruction must be executed. ce# must remain active low for the duration of any command sequence. the sector-erase instruction is initiated by executing an 8-bit command, 20h, followed by address bits [a 23 -a 0 ]. address bits [a ms -a 12 ] (a ms = most significant address) are used to determine the sector address (sa x ), remaining address bits can be v il or v ih. ce# must be driven high before the instruction is executed. poll the busy bit in the software status register or wait t se for the completion of the internal self-timed sector-erase cycle. see figure 13 for the sector-erase sequence. figure 13: sector-erase sequence 1327 f13.0 ce# so si sck add. 012345678 add. 20 high impedance 15 16 23 24 31 add. mode 3 mode 0
advance information 32 mbit spi serial flash sst25vf032b 15 ?2008 silicon storage technology, inc. s71327-01-000 4/08 32-kbyte and 64-kbyte block-erase the 32-kbyte block-erase instruction clears all bits in the selected 32 kbyte block to ffh. a block-erase instruction applied to a protected memo ry area will be ignored. the 64-kbyte block-erase instruction clears all bits in the selected 64 kbyte block to ffh. a block-erase instruction applied to a protected memory area will be ignored. prior to any write operation, the write-enable (wren) instruction must be executed. ce# must remain active low for the duration of any command sequence. the 32-kbyte block- erase instruction is initiated by executing an 8-bit com- mand, 52h, followed by address bits [a 23 -a 0 ]. address bits [a ms -a 15 ] (a ms = most significant address) are used to determine block address (ba x ), remaining address bits can be v il or v ih. ce# must be driven high before the instruction is executed. the 64-kbyte block-erase instruction is initi- ated by executing an 8-bit command d8h, followed by address bits [a 23 -a 0 ]. address bits [a ms -a 15 ] are used to determine block address (ba x ), remaining address bits can be v il or v ih. ce# must be driven high before the instruction is executed. poll the busy bit in the software status register or wait t be for the completion of the internal self-timed 32- kbyte block-erase or 64-kbyte block-erase cycles. see figure 14 for the 32-kbyte block-erase sequence and fig- ure 15 for the 64-kbyte block-erase sequence. figure 14: 32-kbyte block-erase sequence figure 15: 64-kbyte block-erase sequence ce# so si sck addr 012345678 addr addr 52 high impedance 15 16 23 24 31 mode 0 mode 3 1327 32kbkler.0 msb msb ce# so si sck addr 012345678 addr addr d8 high impedance 15 16 23 24 31 mode 0 mode 3 1327 63kblker.0 msb msb
16 advance information 32 mbit spi serial flash sst25vf032b ?2008 silicon storage technology, inc. s71327-01-000 4/08 chip-erase the chip-erase instruction clear s all bits in the device to ffh. a chip-erase instruction will be ignored if any of the memory area is protected. prior to any write operation, the write-enable (wren) instruction must be executed. ce# must remain active low for the duration of the chip-erase instruction sequence. initiate the chip-erase instruction by executing an 8-bit command, 60h or c7h. ce# must be driven high before the instruction is executed. poll the busy bit in the software status register or wait t ce for the comple- tion of the internal self-timed chip-erase cycle. see figure 16 for the chip-erase sequence. figure 16: chip-erase sequence read-status-register (rdsr) the read-status-register (rdsr) instruction allows read- ing of the status register. the status register may be read at any time even during a write (program/erase) operation. when a write operation is in progress, the busy bit may be checked before sending any new commands to assure that the new commands are properly received by the device. ce# must be driven low before the rdsr instruction is entered and remain low until the status data is read. read- status-register is continu ous with ongoing clock cycles until it is terminated by a low to high transition of the ce#. see figure 17 for the rdsr instruction sequence. figure 17: read-status-register (rdsr) sequence ce# so si sck 01234567 60 or c7 high impedance mode 0 mode 3 1327 f16.0 msb 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 1327 f17.0 mode 3 sck si so ce# bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 05 mode 0 high impedance status register out msb msb
advance information 32 mbit spi serial flash sst25vf032b 17 ?2008 silicon storage technology, inc. s71327-01-000 4/08 write-enable (wren) the write-enable (wren) instruction sets the write- enable-latch bit in the status register to ?1? allowing write operations to occur. the wren instruction must be exe- cuted prior to any write (program/erase) operation. the wren instruction may also be used to allow execution of the write-status-register (wrsr) instruction; however, the write-enable-latch bit in the status register will be cleared upon the rising edge ce# of the wrsr instruction. ce# must be driven high before the wren instruction is executed. figure 18: write enable (wren) sequence write-disable (wrdi) the write-disable (wrdi) instruction resets the write- enable-latch bit and aai bit to ?0,? therefore, preventing any new write operations. the wrdi instruction will not termi- nate any programming operation in progress. any program operation in progress may continue up to t bp after execut- ing the wrdi instruction. ce# must be driven high before the wrdi instruction is executed. figure 19: write disable (wrdi) sequence enable-write-status-register (ewsr) the enable-write-status-register (ewsr) instruction arms the write-status-register (wrsr) instruction and opens the status register for alteration. the write-status- register instruction must be executed immediately after the execution of the enable-write-status-register instruction. this two-step instruction sequence of the ewsr instruc- tion followed by the wrsr instruction works like software data protection (sdp) command structure which prevents any accidental alteration of the status register values. ce# must be driven low before the ewsr instruction is entered and must be driven high before the ewsr instruction is executed. ce# so si sck 01234567 06 high impedance mode 0 mode 3 1327 f18.0 msb ce# so si sck 01234567 04 high impedance mode 0 mode 3 1327 f19.0 msb
18 advance information 32 mbit spi serial flash sst25vf032b ?2008 silicon storage technology, inc. s71327-01-000 4/08 write-status-register (wrsr) the write-status-register instruction writes new values to the bp3, bp2, bp1, bp0, and bpl bits of the status regis- ter. ce# must be driven low before the command sequence of the wrsr instruction is entered and driven high before the wrsr instruction is executed. see figure 20 for ewsr or wren and wrsr instruction sequences. executing the write-status-register instruction will be ignored when wp# is low and bpl bit is set to ?1?. when the wp# is low, the bpl bit can only be set from ?0? to ?1? to lock-down the status register, but cannot be reset from ?1? to ?0?. when wp# is high, the lock-down function of the bpl bit is disabled and the bpl, bp0, and bp1 and bp2 bits in the status register can all be changed. as long as bpl bit is set to ?0? or wp# pin is driven high (v ih ) prior to the low-to- high transition of the ce# pin at the end of the wrsr instruction, the bits in the status register can all be altered by the wrsr instruction. in this case, a single wrsr instruction can set the bpl bit to ?1? to lock down the status register as well as altering the bp0, bp1, and bp2 bits at the same time. see table 2 for a summary description of wp# and bpl functions. figure 20: enable-write-status-register (ewsr) or write-enable (wren) and write-status-register (wrsr) sequence 1327 f20.0 mode 3 high impedance mode 0 status register in 76543210 msb msb msb 01 mode 3 sck si so ce# mode 0 50 or 06 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
advance information 32 mbit spi serial flash sst25vf032b 19 ?2008 silicon storage technology, inc. s71327-01-000 4/08 read-id (rdid) the read-id instruction (rdid) identifies the device as sst25vf032b and manufacturer as sst. the device information can be read from executing an 8-bit command, 90h or abh, followed by address bits [a 23 -a 0 ]. following the read-id instruction, the manufacturer?s id is located in address 00000h and the device id is located in address 00001h. once the device is in read-id mode, the manu- facturer?s and device id output data toggles between address 00000h and 00001h until terminated by a low to high transition on ce#. refer to tables 6 and 7 for device identification data. figure 21: read-id sequence 1327 f21.0 ce# so si sck 00 012345678 00 add 1 90 or ab high impedance 15 16 23 24 31 32 39 40 47 48 55 56 63 bf device id bf device id note: the manufacturer's and device id output stream is continuous until terminated by a low to high transition on ce#. 1. 00h will output the manfacturer's id first and 01h will output device id first before toggling between the two. high impedance mode 3 mode 0 msb msb msb table 6: product identification address data manufacturer?s id 00000h bfh device id sst25vf032b 00001h 4ah t6.0 1327
20 advance information 32 mbit spi serial flash sst25vf032b ?2008 silicon storage technology, inc. s71327-01-000 4/08 jedec read-id the jedec read-id instruction identifies the device as sst25vf032b and the manufacturer as sst. the device information can be read from executing the 8-bit command, 9fh. following the jedec read-id instruction, the 8-bit manufacturer?s id, bfh, is output from the device. after that, a 24-bit device id is shifted out on the so pin. byte 1, bfh, identifies the manufacturer as sst. byte 2, 25h, iden- tifies the memory type as spi serial flash. byte 3, 4ah, identifies the device as sst25vf032b. the instruction sequence is shown in figure 22. the jedec read id instruction is terminated by a low to high transition on ce# at any time during data output. figure 22: jedec read-id sequence 25 4a 1327 f22.0 ce# so si sck 012345678 high impedance 15 16 14 28 29 30 31 bf mode 3 mode 0 msb msb 9 10111213 1718 32 34 9f 19 20 21 22 23 33 24 25 26 27 table 7: jedec read-id data manufacturer?s id device id memory type memory capacity byte1 byte 2 byte 3 bfh 25h 4ah t7.0 1327
advance information 32 mbit spi serial flash sst25vf032b 21 ?2008 silicon storage technology, inc. s71327-01-000 4/08 electrical specifications absolute maximum stress ratings applied conditions greater than thos e listed under ?absolute maximum stress ratings? may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these conditions or conditions greater t han those defined in the operational sections of this data sheet is not implied. expo sure to absolute maximum stress rating conditions may affect device reliability. temperature under bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55c to +125c storage temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65c to +150c d. c. voltage on any pin to ground potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0. 5v to v dd +0.5v transient voltage (<20 ns) on any pin to ground potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -2.0v to v dd +2.0v package power dissipation capability (t a = 25c) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0w surface mount solder reflow temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260c for 10 seconds output short circuit current 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 ma 1. output shorted for no more than one second. no more than one output shorted at a time. o perating r ange range ambient temp v dd commercial 0c to +70c 2.7-3.6v industrial -40c to +85c 2.7-3.6v ac c onditions of t est input rise/fall time . . . . . . . . . . . . . . . 5 ns output load . . . . . . . . . . . . . . . . . . . . . c l = 30 pf see figure 27 table 8: dc operating characteristics (vdd = 2.7-3.6v) symbol parameter limits test conditions min max units i ddr read current 10 ma ce# = 0.1 v dd /0.9 v dd @25 mhz, so = open i ddr2 read current 20 ma ce# = 0.1 v dd /0.9 v dd @66 mhz, so = open i ddw program and erase current 30 ma ce# = v dd i sb standby current 20 a ce# = v dd , v in = v dd or v ss i li input leakage current 1 a v in = gnd to v dd , v dd = v dd max i lo output leakage current 1 a v out = gnd to v dd , v dd = v dd max v il input low voltage 0.8 v v dd = v dd min v ih input high voltage 0.7 v dd vv dd = v dd max v ol output low voltage 0.2 v i ol = 100 a, v dd = v dd min v ol2 output low voltage 0.4 v i ol = 1.6 ma, v dd = v dd min v oh output high voltage v dd -0.2 v i oh = -100 a, v dd = v dd min t8.0 1327 table 9: recommended system power-up timings symbol parameter minimum units t pu-read 1 1. this parameter is measured only for init ial qualification and after a design or proc ess change that could affect this paramet er. v dd min to read operation 100 s t pu-write 1 v dd min to write operation 100 s t9.0 1327
22 advance information 32 mbit spi serial flash sst25vf032b ?2008 silicon storage technology, inc. s71327-01-000 4/08 table 10: capacitance (t a = 25c, f = 1 mhz, other pins open) parameter description test condition maximum c out 1 output pin capacitance v out = 0v 12 pf c in 1 input capacitance v in = 0v 6 pf t10.0 1327 1. this parameter is measured only for init ial qualification and after a design or proc ess change that could affect this paramet er. table 11: reliability characteristics symbol parameter minimum spec ification units test method n end 1 1. this parameter is measured only for init ial qualification and after a design or proc ess change that could affect this paramet er. endurance 10,000 cycles jedec standard a117 t dr 1 data retention 100 years jedec standard a103 i lt h 1 latch up 100 + i dd ma jedec standard 78 t11.0 1327 table 12: ac operating characteristics 25 mhz 66 mhz symbol parameter min max min max units f clk 1 1. maximum clock frequency for read instruction, 03h, is 25 mhz serial clock frequency 25 66 mhz t sckh serial clock high time 18 6.5 ns t sckl serial clock low time 18 6.5 ns t sckr 2 2. maximum rise and fall time may be limited by t sckh and t sckl requirements serial clock rise time (slew rate) 0.1 0.1 v/ns t sckf serial clock fall time (slew rate) 0.1 0.1 v/ns t ces 3 3. relative to sck. ce# active setup time 10 5 ns t ceh 3 ce# active hold time 10 5 ns t chs 3 ce# not active setup time 10 5 ns t chh 3 ce# not active hold time 10 5 ns t cph ce# high time 100 50 ns t chz ce# high to high-z output 15 7 ns t clz sck low to low-z output 0 0 ns t ds data in setup time 5 2 ns t dh data in hold time 5 4 ns t hls hold# low setup time 10 5 ns t hhs hold# high setup time 10 5 ns t hlh hold# low hold time 10 5 ns t hhh hold# high hold time 10 5 ns t hz hold# low to high-z output 20 7 ns t lz hold# high to low-z output 15 7 ns t oh output hold from sck change 0 0 ns t v output valid from sck 15 6 ns t se sector-erase 25 25 ms t be block-erase 25 25 ms t sce chip-erase 50 50 ms t bp 4 4. tbp of aai-word programming is also 10 s maximum time. byte-program 10 10 s t12.0 1327
advance information 32 mbit spi serial flash sst25vf032b 23 ?2008 silicon storage technology, inc. s71327-01-000 4/08 figure 23: serial input timing diagram figure 24: serial output timing diagram high-z high-z ce# so si sck msb lsb t ds t dh t chh t ces t ceh t chs t sckr t sckf t cph 1327 f23.0 1327 f24.0 ce# si so sck msb t clz t v t sckh t chz t oh t sckl lsb
24 advance information 32 mbit spi serial flash sst25vf032b ?2008 silicon storage technology, inc. s71327-01-000 4/08 figure 25: hold timing diagram figure 26: power-up timing diagram t hz t lz t hhh t hls t hhs 1327 f25.0 hold# ce# sck so si t hlh time v dd min v dd max v dd device fully accessible t pu-read t pu-write chip selection is not allowed. all commands are rejected by the device. 1327 f26.0
advance information 32 mbit spi serial flash sst25vf032b 25 ?2008 silicon storage technology, inc. s71327-01-000 4/08 figure 27: ac input/output reference waveforms 1327 ioref.0 reference points output input v ht v lt v ht v lt v iht v ilt ac test inputs are driven at v iht (0.9v dd ) for a logic ?1? and v ilt (0.1v dd ) for a logic ?0?. measurement reference points for inputs and outputs are v ht (0.6v dd ) and v lt (0.4v dd ). input rise and fall times (10% ? 90%) are <5 ns. note: v ht - v high te s t v lt - v low te s t v iht - v input high test v ilt - v input low test
26 advance information 32 mbit spi serial flash sst25vf032b ?2008 silicon storage technology, inc. s71327-01-000 4/08 product ordering information valid combinations for sst25vf032b sst25vf032b-66-4c-s2af SST25VF032B-66-4C-SCF sst25vf032b-66-4i-s2af sst25vf032b-66-4i-scf note: valid combinations are those products in mass producti on or will be in mass production. consult your sst sales representative to confirm availability of valid combinat ions and to determine availability of new combinations. sst 25 vf 032 b - 66 - 4c - s2a f xx x xxxx x- xx -xx - xxx x environmental attribute f 1 = non-pb / non-sn contact (lead) finish: nickel plating with gold top (outer) layer package modifier a = 8 leads or contacts c = 16 leads package type s = soic s2 = soic 200 mil body width temperature range c = commercial = 0c to +70c i = industrial = -40c to +85c minimum endurance 4 = 10,000 cycles operating frequency 66 = 66 mhz device density 032 = 32 mbit voltage v = 2.7-3.6v product series 25 = serial peripheral interface flash memory 1. environmental suffix ?f? denotes non-pb/non-sn solder. sst non-pb/non-sn solder devi ces are ?rohs compliant?.
advance information 32 mbit spi serial flash sst25vf032b 27 ?2008 silicon storage technology, inc. s71327-01-000 4/08 packaging diagrams figure 28: 16-lead plastic small outline integrated circuit (soic) sst package code sc 16.soic-sc-ill.3 note: 1. complies with jedec publication 95 ms-013 aa dimensions (except as noted), although some dimensions may be more string ent. ? = jedec min is 10.10; sst min (10.08) is less stringent ? = jedec min is 0.40; sst min (0.38) is less stringent 2. all linear dimensions are in metric (min/max). 3. coplanarity: 0.1 (.05) mm. 4. maximum allowable mold flash is 0.15mm at the package ends, and 0.25mm between leads. .33 .51 10.08 ? 10.50 1.27 bsc .10 .30 2.35 2.65 .23 .32 .38 ? 1.27 .020x45? 7? 4 places 7? 4 places 10.00 10.65 7.40 7.60 pin #1 identifier
28 advance information 32 mbit spi serial flash sst25vf032b ?2008 silicon storage technology, inc. s71327-01-000 4/08 figure 29: 8-lead small outline integrated ci rcuit (soic) 200 mil body width (5.2mm x 8mm) sst package code: s2a table 13: revision history number description date 00 ? initial release of data sheet oct 2006 01 ? changed clock frequency from 50 mhz to 66 mhz globally ? revised table 12 ac operating characteristics ? revised product ordering information and valid combinations on page 26 ? revised figure 11 and figure 12 ? changed iddr2 from max 15 ma to max 20 ma in table 8 ? changed tdh from min 5 ns to min 4 ns (66mhz) in table 12 mar 2008 2.16 1.75 08-soic-eiaj-s2a-3 note: 1. all linear dimensions are in millimeters (max/min). 2. coplanarity: 0.1 mm 3. maximum allowable mold flash is 0.15 mm at the package ends and 0.25 mm between leads. top view side view end view 5.40 5.15 8.10 7.70 5.40 5.15 pin #1 identifier 0.50 0.35 1.27 bsc 0.25 0.05 0.25 0.19 0.80 0.50 0? 8? 1mm silicon storage technology, inc. ? 1171 sonora court ? sunnyvale, ca 94086 ? telephone 408-735-9110 ? fax 408-735-9036 www.superflash.com or www.sst.com

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