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1 (12) da9180.001 8 march, 2004 mas9180 am receiver ic ? single band receiver ic ? high sensitivity ? very low power consumption ? wide supply voltage range ? power down control ? control for agc on ? high selectivity by crystal filter ? fast startup feature description the mas9180 am-receiver chip is a highly sensitive, simple to us e am receiver specially intended to receive time signals in the frequency range from 40 khz to 100 khz. only a few external components are required for time signal receiver. the circuit has preamplifier, wide range automatic gain control, demodulator and output comparator built in. the output signal can be processed directly by an additional digital circuitry to extract the data from the received signal. the control for agc (automatic gain control) can be used to switch agc on or off if necessary. mas9180 has differential input and two options for compensating shunt capacitances of different crystals (see ordering information on page 12). features applications ? single band receiver ic ? highly sensitive am receiver, 0.4 v rms typ. ? wide supply voltage range from 1.1 v to 5 v ? very low power consumption ? power down control ? fast startup ? only a few external components necessary ? control for agc on ? wide frequency range from 40 khz to 100 khz ? high selectivity by qu artz crysta l filter ? single band time signal receiver wwvb (usa), jjy (japan), dcf77 (germany), msf (uk) and bpc (china) block diagram agc amplifier power supply/biasing demodulator & comparator rfp rfm vdd vss pdn agc dec out qop qi qom aon this is preliminary information on a new product under development. micro analog systems oy reserves the right to make any changes without notice.
2 (12) da9180.001 8 march, 2004 mas9180 pad layout pdn aon rfim rfip dec vss agc qi vdd qop out 1456 m 1474 m qom mas9180ax, x = 1 or 5 die size = 1.47 x 1.46 mm; round pad ? 80 m note: because the substrate of the die is internally connected to vdd, the die has to be connected to vdd or left floating. please make sure that vdd is the first pad to be bonded. pick-and-place and all component assembly are recommended to be performed in esd protected area. note: coordinates are pad center points where origin has been located in bottom-left corner of the silicon die. pad identification na me x-coordinate y- coordinate note power supply voltage vdd 174 m 1262 m positive quartz filter output for crystal qop 174 m 1057 m negative quartz filter output for crystal qom 174 m 854 m 4 quartz filter input for crystal and external compensation capacitor qi 174 m 648 m agc capacitor agc 174 m 444 m receiver output out 175 m 240 m 1 demodulator capacitor dec 1295 m 225 m agc on control aon 1295 m 425 m 2 power down pdn 1295 m 624 m 3 positive receiver input rfip 1295 m 825 m 5 negative receiver input rfim 1295 m 1039 m 5 power supply ground vss 1282 m 1200 m notes: 1) out = vss when carrier amplitude at maximum; out = vdd when carrier amplitude is reduced (modulated) - the output is a current source/sink with |i out | > 5 a - at power down the output is pulled to vss (pull down switch) 2) aon = vss means agc off (hold current gain level); aon = vdd means agc on (working) - internal pull-up with current < 1 a which is switched off at power down 3) pdn = vss means re ceiver on; pdn = vdd means receiver off fast start-up is triggered when the receiver is after power down (pdn=vdd) controlled to power up (pdn=vss) i.e. at the fa lling edge of pdn signal. 4) external crystal compensation capacitor pin qom is connected only in mas9190a5 version. it is left unconnected in mas9180a1 version which has internal compensation capacitor. 5) receiver inputs rfip and rfim have both 600 k ? biasing mosfet-transistors towards ground
3 (12) da9180.001 8 march, 2004 absolute maximum ratings parameter symbol conditions min max unit supply voltage v dd -v ss -0.3 6 v input voltage v in v ss -0.3 v dd +0.3 v power dissipation p max 100 mw operating temperature t op -40 +85 o c storage temperature t st -55 +150 o c electrical characteristics operating conditions: vdd = 1.4v, temperature = 25c parameter symbol conditions min typ max unit operating voltage v dd 1.10 5 v current consumption i dd vdd=1.4 v, vin=0.4 vrms vdd=1.4 v, vin=20 mvrms vdd=3.6 v, vin=0.4 vrms vdd=3.6 v, vin=20 mvrms 49 36 50 38 75 50 a stand-by current i ddoff 0.1 a input frequency range f in 40 100 khz minimum input voltage v in min 0.4 1 vrms maximum input voltage v in max 20 mvrms receiver input resistance receiver input capacitance r rfi c rfi f=40 khz..77.5 khz 330 4.5 k ? pf input levels |l in |<0.5 a v il v ih 0.8 v dd 0.2 v dd v output current v ol <0.2 v dd ;v oh >0.8 v dd |i out | 5 a output pulse t 100ms 1 vrms v in 20 mvrms 50 140 ms t 200ms 1 vrms v in 20 mvrms 150 230 ms t 500ms 1 vrms v in 20 mvrms 400 500 600 ms t 800ms 1 vrms v in 20 mvrms 700 800 900 ms startup time t start fast start-up, vin=0.4 vrms fast start-up, vin=20 mvrms 1.3 3.5 s output delay time t delay 50 100 ms
4 (12) da9180.001 8 march, 2004 typical application agc amplifier power supply/biasing demodulator & comparator rfp rfm vdd vss pdn agc dec out qop qi qom aon + 1.4 v receiver output c agc 10 f c dec 47 nf note 2 note 1 ferrite antenna note 4 optional control for agc on/hold note 3 power down / fast startup control figure 1 application circuit of internal compensation capacitance version mas9180a1. agc amplifier power supply/biasing demodulator & comparator rfp rfm vdd vss pdn agc dec out qop qi qom aon + 1.4 v receiver output c agc 10 f c dec 47 nf note 2 note 1 ferrite antenna c c_ext =c 0 note 4 optional control for agc on/hold note 3 power down / fast startup control figure 2 application circuit of external compensation capacitance version mas9180a5.
5 (12) da9180.001 8 march, 2004 typical application (continued) agc amplifier power supply/biasing demodulator & comparator rfp rfm vdd vss pdn agc dec out qop qi qom aon + 1.4 v receiver output c agc 10 f c dec 47 nf note 3 power down / fast startup control note 2 note 1 note 4 optional control for agc on/hold ferrite antenna antenna frequency selection figure 3 dual band application circuit of external compensation capacitance version mas9180a5. note 1: crystals the crystal as well as ferrite antenna frequencies are chosen according to the time-signal system (table 1). the crystal shunt capacitance c 0 should be matched as well as possible with the internal shunt capacitance compensation capacitor c c of mas9180. mas9180a5 has also opti on for external crystal compensation capacitor. the external compensation capacitor should be matched as well as possible with crystal shunt capacitance. see compensation capacitance options on table 2. table 1 time-signal system frequencies time-signal system locati on antenna frequency recomm ended crystal frequency dcf77 germany 77.5 khz 77.503 khz msf united kingdom 60 khz 60.003 khz wwvb usa 60 khz 60.003 khz jjy japan 40 khz and 60 khz 40.003 khz and 60.003 khz bpc china 68.5 khz 68.505 khz table 2 compensation capacitance options device c c crystal description mas9180a1 0.75 pf for low c 0 crystal mas9180a5 c c_ext for any crystals, external compensation capacitor it should be noted that grounded crystal package has reduced shunt capacitance. this value is about 85% of floating crystal shunt capacitance. for example crystal with 1 pf floating package shunt capacitance can have 0.85 pf grounded package shunt capacitance. pcb traces of crystal and external compensation capacitance should be kept at minimum to minimize additional parasitic capacitance which can cause capacitance mismatching.
6 (12) da9180.001 8 march, 2004 typical application (continued) in dual band receiver configuration the crystals can be connected in parallel thus external compensation capacitor value c c_ext must be sum of two crystals? shunt capacitances. instead of parallel crystal connection it is also possible to connect other crystal from qop pin and the other crystal from qom pin to common qi pin (figure 3). in this circuit configuration no external compensation capacitor is required since the crystals compensate each other. the se nsitivity of dual band receiver configuratio n will be lower than th at of single band receiver configuration since the noise band width of crystal filter with two parallel crystals is double. note 2: agc capacitor the agc and dec capacitors must have low leakage currents due to very small signal currents through the capacitors. the insulation resistance of these capacitors should be at minimum 100 m ? . also probes with at least 100 m ? impedance should be used for voltage probing of agc and dec pins. dec capacitor can be low leakage chip capacitor. note 3: power down / fast startup control both power down and fast startup are controlled using the pdn pin. the device is in power down (turned off) if pdn = vdd and in power up (turned on) if pdn = vss. fast startup is triggered automatically by the falling edge of pdn signal, i.e., controlling device from power down to power up. the vdd must be high before falling edge of pdn to guarantee proper operation of fast startup circuitry. the startup time without proper fast startup control can be several minutes but with fast startup it is shortened typically to few seconds. note 4: optional control for agc on/hold aon control pin has internal pull up which turns agc circuit on all the time if aon pin is left unconnected. optionally aon control can be used to hold and release agc circuit. stepper motor drive etc. can produce disturbing amount of noise which can shift the input amplifier gain to unoptimal level. this can be avoided by controlling agc hold (aon=vss) during stepper motor drive periods and releasing agc (aon=vdd) when motors are not driven.
7 (12) da9180.001 8 march, 2004 mas9180 samples in sbdil 20 package top marking definitions: yyww = year week xxxxx.x = lot number z=sample version number nc 1 vdd 2 nc 3 qop 4 q om 5 nc 6 qi 7 agc 8 nc 9 out 10 20 vss 19 nc 18 rfim 17 rfip 16 nc 15 nc 14 pdn 13 aon 12 dec 11 nc 9180az yyww xxxxx.x pin description pin name pin type function note nc 1 vdd 2 p positive power supply nc 3 qop 4 ao positive quartz filter output for crystal qom 5 negative quartz filter output for external compensation capacitor or second crystal 5 nc 6 1 qi 7 ai quartz filter input for crystal and external compensation capacitor agc 8 ao agc capacitor nc 9 out 10 do receiver output 2 nc 11 dec 12 ao demodulator capacitor aon 13 di agc on control 3 pdn 14 di power down input 4 nc 15 nc 16 rfip 17 ai positive receiver input 6 rfim 18 ai negative receiver input 6 nc 19 vss 20 g power supply ground a = analog, d = digital, p = power, g = ground, i = input, o = output, nc = not connected notes: 1) pin 6 between qom and qi must be connected to vss to eliminate dil package leadframe parasitic capacitances disturbing the crystal filter performance. all other nc (not connected) pins are also recommended to be connected to vss to minimize noise coupling. 2) out = vss when carrier amplitude at maximum; out = vdd when carrier amplitude is reduced (modulated) - the output is a current source/sink with |i out | > 5 a - at power down the output is pulled to vss (pull down switch) 3) aon = vss means agc off (hold current gain level); aon = vdd means agc on (working) - internal pull-up with current < 1 a which is switched off at power down 4) pdn = vss means re ceiver on; pdn = vdd means receiver off - fast start-up is triggered when the receiver is after power down (pdn=vdd) controlled to power up (pdn=vss) i.e. at the fa lling edge of pdn signal. 5) external crystal compensation capacitor pin qom is connected only in mas9190a5 version. it is left unconnected in mas9180a1 version which has internal compensation capacitor. 6) receiver inputs rfip and rfim have both 600 k ? biasing mosfet-transistors towards ground
8 (12) da9180.001 8 march, 2004 pin configuration & top marking for plastic tssop-16 package qop vdd qom nc qi agc nc out nc vss rfim rfip nc pdn aon dec 9180az yyww top marking definitions: z = version number yyww = year week pin description pin name pin type function note vdd 1 p positive power supply qop 2 ao positive quartz filter output for crystal qom 3 ao negative quartz filter output for external compensation capacitor or second crystal 5 nc 4 1 qi 5 ai quartz filter input for crystal and external compensation capacitor agc 6 ao agc capacitor nc 7 out 8 do receiver output 2 dec 9 ao demodulator capacitor aon 10 di agc on control 3 pdn 11 di power down input 4 nc 12 rfip 13 ai positive receiver input 6 nc 14 rfim 15 ai negative receiver input 6 vss 16 g power supply ground a = analog, d = digital, p = power, g = ground, i = input, o = output, nc = not connected notes: 1) pin 4 between quartz crystal filter pins must be connected to vss to eliminate package leadframe parasitic capacitances disturbing the crystal filter performance. all other nc (not connected) pins are also recommended to be connected to vss to minimize noise coupling. 2) out = vss when carrier amplitude at maximum; out = vdd when carrier amplitude is reduced (modulated) - the output is a current source/sink with |i out | > 5 a - at power down the output is pulled to vss (pull down switch) 3) aon = vss means agc off (hold current gain level); aon = vdd means agc on (working) - internal pull-up (to agc on) with current < 1 a which is switched off at power down 4) pdn = vss means rece iver on; pdn = vdd means receiver off - fast start-up is triggered when the receiver is after power down (pdn=vdd) controlled to power up (pdn=vss) i.e. at the fa lling edge of pdn signal. 5) external crystal compensation capacitor pin qom is connected only in mas9190a5 version. it is left unconnected in mas9180a1 version which has internal compensation capacitor. 6) receiver inputs rfip and rfim have both 600 k ? biasing mosfet-transistors towards ground
9 (12) da9180.001 8 march, 2004 package (tssop16) outlines dimension min max unit a 6.40 bsc mm b 4.30 4.50 mm c 5.00 bsc mm d 0.05 0.15 mm e 1.10 mm f 0.19 0.30 mm g 0.65 bsc mm h 0.18 0.28 mm i 0.09 0.20 mm i1 0.09 0.16 mm j 0.19 0.30 mm j1 0.19 0.25 mm k 0 8 l 0.24 0.26 mm m (the length of a terminal for soldering to a substrate) 0.50 0.75 mm n 1.00 ref mm o 12 p 12 dimensions do not include mold flash, protrusions, or gate burrs. all dimensions are in accordance with jedec standard mo-153. b a c pin 1 d seating plane e h g f b b detail a l k m n p o detail a ii1 j j1 section b-b
10 (12) da9180.001 8 march, 2004 soldering information resistance to soldering heat according to rsh test iec 68-2-58/20 2*220 c maximum temperature 240 c maximum number of reflow cycles 2 reflow profile thermal profile parameters stated in jesd22-a113 should not be exceeded. http://www.jedec.org seating plane co-planarity max 0.08 mm lead finish solder plate 7.62 - 25.4 m, material sn 85% pb 15% embossed tape specifications dimension min max unit a 0 6.50 6.70 mm b 0 5.20 5.40 mm d 0 1.50 +0.10 / -0.00 mm d 1 1.50 mm e 1 1.65 1.85 mm f 1 7.20 7.30 mm k 0 1.20 1.40 mm p 11.90 12.10 mm p 0 4.0 mm p 2 1.95 2.05 mm s 1 0.6 mm t 0.25 0.35 mm w 11.70 12.30 mm p 0 p p 2 a 0 d 1 d 0 a a section a - a e 1 f 1 w tape feed direction b 0 t k 0 s 1 tape feed direction pin 1 designator
11 (12) da9180.001 8 march, 2004 reel specifications dimension min max unit a 330 mm b 1.5 mm c 12.80 13.50 mm d 20.2 mm n 50 mm w 1 (measured at hub) 12.4 14.4 mm w 2 (measured at hub) 18.4 mm trailer 160 mm leader 390, of which minimum 160 mm of empty carrier tape sealed with cover tape mm weight 1500 g d a b c n w 1 w 2 tape slot for tape start components trailer leader carrier tape cover tape start end 2000 components on each reel reel material: conductive, plastic antistatic or static dissipative carrier tape material: conductive cover ta p e material: static dissi p ative
12 (12) da9180.001 8 march, 2004 ordering information product code product description ca pacitance option mas9180a1tc00 single band am-receiver ic with differential input ews-tested wafer, thickness 400 m. c c = 0.75 pf mas9180a5tc00 single band am-receiver ic with differential input ews-tested wafer, thickness 400 m. external compensation capacitor MAS9180A1UA06 single band am-receiver ic with differential input tssop-16, tape & reel c c = 0.75 pf contact micro analog systems oy for other wafer thickness options. offered in north america by evox rifa, inc. 300 tri-state international, suite 375 lincolnshire, il 60069 usa tel: 1 847 948 9511 fax: 1 847 948 9320 email: service@evoxrifa.com web: http://www.evoxrifa.com/n_america micro analog systems oy contacts micro analog systems oy kamreerintie 2, p.o. box 51 fin-02771 espoo, finland http://www.mas-oy.com tel. (09) 80 521 tel. int. +358 9 80 521 telefax +358 9 805 3213 e-mail: info@mas-oy.com notice micro analog systems oy reserves the right to make changes to the products contained in this data sheet in order to improve the design or performance and to supply the best possible products. micro analog systems oy assumes no responsibility for the use of any circ uits shown in this data sheet, conveys no license under any patent or other rights unless otherwise specified in this data sheet, and make s no claim that the circuits are free from patent infringement. applications for any devices shown in this data sheet are for illustration only and micro analog systems oy makes no claim or warranty that such applications will be suitable for the use specified without further testing or modification.

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