View UPD70F3187GDA1-64-LML_6888695.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

user?s manual v850e/ph2 tm 32-bit single-chip microcontroller hardware pd70f3187 document no. u16580ee2v0ud00 date published june 2006 ? nec electronics corporation 2006 printed in germany
2 user?s manual u16580ee2v0ud00 1 2 3 4 voltage application waveform at input pin waveform distortion due to input noise or a reflected wave may cause malfunction. if the input of the cmos device stays in the area between v il (max) and v ih (min) due to noise, etc., the device may malfunction. take care to prevent chattering noise from entering the device when the input level is fixed, and also in the transition period when the input level passes through the area between v il (max) and v ih (min). handling of unused input pins unconnected cmos device inputs can be cause of malfunction. if an input pin is unconnected, it is possible that an internal input level may be generated due to noise, etc., causing malfunction. cmos devices behave differently than bipolar or nmos devices. input levels of cmos devices must be fixed high or low by using pull-up or pull-down circuitry. each unused pin should be connected to v dd or gnd via a resistor if there is a possibility that it will be an output pin. all handling related to unused pins must be judged separately for each device and according to related specifications governing the device. precaution against esd a strong electric field, when exposed to a mos device, can cause destruction of the gate oxide and ultimately degrade the device operation. steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it when it has occurred. environmental control must be adequate. when it is dry, a humidifier should be used. it is recommended to avoid using insulators that easily build up static electricity. semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. all test and measurement tools including work benches and floors should be grounded. the operator should be grounded using a wrist strap. semiconductor devices must not be touched with bare hands. similar precautions need to be taken for pw boards with mounted semiconductor devices. status before initialization power-on does not necessarily define the initial status of a mos device. immediately after the power source is turned on, devices with reset functions have not yet been initialized. hence, power-on does not guarantee output pin levels, i/o settings or contents of registers. a device is not initialized until the reset signal is received. a reset operation must be executed immediately after power-on for devices with reset functions. input of signal during power off state do not input signals or an i/o pull-up power supply while the device is not powered. the current injection that results from input of such a signal or i/o pull-up power supply may cause malfunction and the abnormal current that passes in the device at this time may cause degradation of internal elements. input of signals during the power off state must be judged separately for each device and according to related specifications governing the device. notes for cmos devices 5 all (other) product, brand, or trade names used in this pamphlet are the trademarks or registered trademarks of their respective owners. product specifications are subject to change without notice. to ensure that you have the latest product data, please contact your local nec electronics sales office.
3 user?s manual u16580ee2v0ud00 the information in this document is current as of june, 2006. the information is subject to change without notice. for actual design-in, refer to the latest publications of nec electronics data sheets or data books, etc., for the most up-to-date specifications of nec electronics products. not all products and/or types are available in every country. please check with an nec electronics sales representative for availability and additional information. no part of this document may be copied or reproduced in any form or by any means without the prior written consent of nec electronics. nec electronics assumes no responsibility for any errors that may appear in this document. nec electronics does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of nec electronics products listed in this document or any other liability arising from the use of such products. no license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of nec electronics or others. descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. the incorporation of these circuits, software and information in the design of a customer's equipment shall be done under the full responsibility of the customer. nec electroni cs assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. while nec electronics endeavors to enhance the quality, reliability and safety of nec electronics products, customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. to minimize risks of damage to property or injury (including death) to persons arising from defects in nec electronics products, customers must incorporate sufficient safety measures in their design, such as redundancy, fire-containment and anti-failure features. nec electronics products are classified into the following three quality grades: "standard", "special" and "specific". the "specific" quality grade applies only to nec electronics products developed based on a customer- designated "quality assurance program" for a specific application. the recommended applications of an nec electronics product depend on its quality grade, as indicated below. customers must check the quality grade of each nec electronics product before using it in a particular application. the quality grade of nec electronics products is "standard" unless otherwise expressly specified in nec electronics data sheets or data books, etc. if customers wish to use nec electronics products in applications not intended by nec electronics, they must contact an nec electronics sales representative in advance to determine nec electronics' willingness to support a given application. (note) ? ? ? ? ? ? m8e 02. 11-1 (1) (2) "nec electronics" as used in this statement means nec electronics corporation and also includes its majority-owned subsidiaries. "nec electronics products" means any product developed or manufactured by or for nec electronics (as defined above). computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots. transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support). aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems and medical equipment for life support, etc. "standard": "special": "specific":
4 user?s manual u16580ee2v0ud00 nec electronics corporation 1753, shimonumabe, nakahara-ku, kawasaki, kanagawa 211-8668, japan tel: 044-435-5111 http://www.necel.com/ [america] nec electronics america, inc. 2880 scott blvd. santa clara, ca 95050-2554, u.s.a. tel: 408-588-6000 800-366-9782 http://www.am.necel.com/ [asia & oceania] nec electronics (china) co., ltd 7th floor, quantum plaza, no. 27 zhichunlu haidian district, beijing 100083, p.r.china tel: 010-8235-1155 http://www.cn.necel.com/ nec electronics shanghai ltd. room 2509-2510, bank of china tower, 200 yincheng road central, pudong new area, shanghai p.r. china p.c:200120 tel: 021-5888-5400 http://www.cn.necel.com/ nec electronics hong kong ltd. 12/f., cityplaza 4, 12 taikoo wan road, hong kong tel: 2886-9318 http://www.hk.necel.com/ seoul branch 11f., samik lavied?or bldg., 720-2, yeoksam-dong, kangnam-ku, seoul, 135-080, korea tel: 02-558-3737 nec electronics taiwan ltd. 7f, no. 363 fu shing north road taipei, taiwan, r. o. c. tel: 02-8175-9600 nec electronics singapore pte. ltd. 238a thomson road, #12-08 novena square, singapore 307684 tel: 6253-8311 http://www.sg.necel.com/ for further information, please contact: g06.6-1a [europe] nec electronics (europe) gmbh arcadiastrasse 10 40472 dsseldorf, germany tel: 0211-65030 http://www.eu.necel.com/ hanover office podbielski strasse 166 b 30177 hanover tel: 0 511 33 40 2-0 munich office werner-eckert-strasse 9 81829 mnchen tel: 0 89 92 10 03-0 stuttgart office industriestrasse 3 70565 stuttgart tel: 0 711 99 01 0-0 united kingdom branch cygnus house, sunrise parkway linford wood, milton keynes mk14 6np, u.k. tel: 01908-691-133 succursale fran?aise 9, rue paul dautier, b.p. 52180 78142 velizy-villacoublay cdex france tel: 01-3067-5800 sucursal en espa?a juan esplandiu, 15 28007 madrid, spain tel: 091-504-2787 tyskland filial t?by centrum entrance s (7th floor) 18322 t?by, sweden tel: 08 638 72 00 filiale italiana via fabio filzi, 25/a 20124 milano, italy tel: 02-667541 branch the netherlands steijgerweg 6 5616 hs eindhoven the netherlands tel: 040 265 40 10
5 user?s manual u16580ee2v0ud00 preface readers this manual is intended for users who want to understand the functions of the v850e/ph2 (phoenix-f). purpose this manual presents the hardware manual of v850e/ph2. organization this system specification describes the following sections: ? pin function ? cpu function ? internal peripheral function ? flash memory legend symbols and notation are used as follows: weight in data notation : left is high-o rder column, right is low order column active low notation : xxx (pin or signal name is over-scored) or /xxx (slash before signal name) memory map address: : high order at high stage and low order at low stage note : explanation of (note) in the text caution : item deserving extra attention remark : supplementary explanation to the text numeric notation : binary... xxxx or xxx b decimal... xxxx hexadecimal... xxxx h or 0x xxxx prefixes representing powers of 2 (address space, memory capacity) k (kilo): 2 10 = 1024 m (mega): 2 20 = 1024 2 = 1,048,576 g (giga): 2 30 = 1024 3 = 1,073,741,824
6 user?s manual u16580ee2v0ud00
7 user?s manual u16580ee2v0ud00 table of contents preface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 chapter 1 introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 1.1 outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 1.2 device features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 1.3 applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 1.4 ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 1.5 pin configuration (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 1.6 function blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 1.6.1 internal block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 1.6.2 on-chip units. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 chapter 2 pin functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 2.1 list of pin functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 2.2 pin status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 2.3 description of pin functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 2.4 pin i/o circuits and recommended connection of unused pins . . . . . . . . . . . . . . . 70 2.5 noise suppression . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 chapter 3 cpu functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 3.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 3.2 cpu register set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 8 3.2.1 program register set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 3.2.2 system register set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 3.2.3 floating point arithmetic unit register set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 3.3 operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 8 3.3.1 operating modes outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 3.3.2 operation mode specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 3.4 address space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 3.4.1 cpu address space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 3.4.2 images . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 3.4.3 wrap-around of cpu address space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 3.4.4 memory map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 3.4.5 areas . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 3.4.6 peripheral i/o registers list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 3.4.7 programmable peripheral i/o area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 3.4.8 specific registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 3.4.9 system wait control register (vswc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 3.4.10 dma wait control registers 0 and 1 (dmawc0, dmawc1) . . . . . . . . . . . . . . . 130 3.4.11 cautions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 chapter 4 bus control function. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 4.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 4.2 bus control pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3 4.3 memory block function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 4.3.1 chip select control function. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 4.4 bus cycle type control function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 4.4.1 bus cycle type configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 4.5 bus access. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .139 4.5.1 number of access clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 4.5.2 bus sizing function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 4.5.3 endian control function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 4.5.4 bus width . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 4.6 wait function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 4.6.1 programmable wait function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
8 user?s manual u16580ee2v0ud00 4.7 idle state insertion function. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 4.8 bus priority order . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 7 4.9 boundary operation conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 4.9.1 program space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 4.9.2 data space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 chapter 5 memory access control function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 5.1 sram, external rom, external i/o interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 5.1.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 5.1.2 sram connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170 5.1.3 sram, external rom, external i/o access . . . . . . . . . . . . . . . . . . . . . . . . . . . 172 chapter 6 dma functions (dma controller) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181 6.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181 6.2 control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 2 6.3 dma channel priorities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188 6.4 dma operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 8 6.4.1 dma transfer of a/d converter result registers (adc0, adc1) . . . . . . . . . . . . 188 6.4.2 dma transfer of pwm timer reload (tmr0, tmr1) . . . . . . . . . . . . . . . . . . . . . 192 6.4.3 dma transfer of serial interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196 6.4.4 forcible termination of dma transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204 6.5 dma interrupt function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205 chapter 7 interrupt/exception processing function . . . . . . . . . . . . . . . . . . . . . . . . . 207 7.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207 7.2 non-maskable interrupt. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212 7.2.1 operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213 7.2.2 restore . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215 7.2.3 non-maskable interrupt status flag (np). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216 7.2.4 edge detection function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216 7.3 maskable interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217 7.3.1 operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217 7.3.2 restore . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219 7.3.3 priorities of maskable interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220 7.3.4 interrupt control register (picn) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224 7.3.5 interrupt mask registers 0 to 6 (imr0 to imr6) . . . . . . . . . . . . . . . . . . . . . . . . 228 7.3.6 in-service priority register (ispr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230 7.3.7 maskable interrupt status flag (id) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231 7.3.8 interrupt trigger mode selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232 7.4 software exception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237 7.4.1 operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237 7.4.2 restore . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238 7.4.3 exception status flag (ep) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239 7.5 exception trap . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 40 7.5.1 illegal opcode definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240 7.6 periods in which cpu does not acknowledge interrupts. . . . . . . . . . . . . . . . . . . . 242 chapter 8 clock generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243 8.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243 8.2 configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .243 8.3 power save control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244 8.3.1 overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244 8.3.2 halt mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245
9 user?s manual u16580ee2v0ud00 chapter 9 16-bit timer/event counter p . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247 9.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247 9.2 function outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 7 9.3 configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248 9.4 control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 2 9.5 operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 262 9.5.1 anytime rewrite and reload . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 262 9.5.2 interval timer mode (tpnmd2 to tpnmd0 = 000b) . . . . . . . . . . . . . . . . . . . . . 267 9.5.3 external event count mode (tpnmd2 to tpnmd0 = 001b) . . . . . . . . . . . . . . . 270 9.5.4 external trigger pulse output mode (tpnmd2 to tpnmd0 = 010b) . . . . . . . . . 274 9.5.5 one-shot pulse mode (tpnmd2 to tpnmd0 = 011b) . . . . . . . . . . . . . . . . . . . 277 9.5.6 pwm mode (tpnmd2 to tpnmd0 = 100b) . . . . . . . . . . . . . . . . . . . . . . . . . . . 280 9.5.7 free-running mode (tpnmd2 to tpnmd0 = 101b) . . . . . . . . . . . . . . . . . . . . . 285 9.5.8 pulse width measurement mode (tpnmd2 to tpnmd0 = 110b) . . . . . . . . . . . 291 9.5.9 counter synchronous operation function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 298 chapter 10 16-bit inverter timer/counter r. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 299 10.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 299 10.2 configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .300 10.3 control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 10 10.4 basic operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 29 10.4.1 basic counter operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 329 10.4.2 compare register rewrite operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 331 10.4.3 list of outputs in each mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 344 10.5 match interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 350 10.5.1 compare match interrupt related cautions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 352 10.6 flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 354 10.6.1 up count flags. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 354 10.6.2 normal phase/inverted phase simultaneous active detection flag . . . . . . . . . . 355 10.6.3 reload hold flag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 356 10.7 interrupt thinning out function. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 357 10.7.1 operation of interrupt thinning out function. . . . . . . . . . . . . . . . . . . . . . . . . . . . 358 10.7.2 operation examples when peak interrupts and valley interrupts occur alternately . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 360 10.7.3 interrupt thinning out function during counter saw tooth wave operation . . . . . 361 10.8 a/d conversion trigger function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 362 10.8.1 a/d conversion trigger operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 363 10.9 error interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .366 10.9.1 error interrupt and error signal output functions . . . . . . . . . . . . . . . . . . . . . . . . 366 10.10 operation in each mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 370 10.10.1 interval timer mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 370 10.10.2 external event count mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 374 10.10.3 external trigger pulse output mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 380 10.10.4 one-shot pulse mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 384 10.10.5 pwm mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 388 10.10.6 free-running mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 394 10.10.7 pulse width measurement mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400 10.10.8 triangular wave pwm mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 402 10.10.9 high-accuracy t-pwm mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 405 10.10.10 pwm mode with dead time. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 434
10 user?s manual u16580ee2v0ud00 chapter 11 16-bit timer/event counter t . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 443 11.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 443 11.2 function outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 443 11.3 configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .444 11.4 control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 51 11.5 basic operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 466 11.5.1 basic counter operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 466 11.5.2 method for writing to compare register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 469 11.6 operation in each mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 473 11.6.1 interval timer mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 473 11.6.2 external event count mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 476 11.6.3 external trigger pulse output mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 481 11.6.4 one-shot pulse mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 484 11.6.5 pwm mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 487 11.6.6 free-running mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 491 11.6.7 pulse width measurement mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 496 11.6.8 triangular wave pwm mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 497 11.6.9 encoder count function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 499 11.6.10 offset trigger generation mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 517 chapter 12 16-bit 2-phase encoder input up/down counter/general purpose timer (tmenc10) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 519 12.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 519 12.2 function outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 519 12.3 basic configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 521 12.4 control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 29 12.5 operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 538 12.5.1 basic operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 538 12.5.2 operation in general-purpose timer mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 539 12.5.3 operation in udc mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 542 12.6 supplementary description of internal operation . . . . . . . . . . . . . . . . . . . . . . . . . . 550 12.6.1 clearing of count value in udc mode b . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 550 12.6.2 clearing of count value upon occurrence of compare match . . . . . . . . . . . . . . 551 12.6.3 transfer operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 551 12.6.4 interrupt signal output upon compare match . . . . . . . . . . . . . . . . . . . . . . . . . . 552 12.6.5 tm1ubd flag (bit 0 of status register) operation . . . . . . . . . . . . . . . . . . . . . 552 chapter 13 auxiliary frequency output function (afo) . . . . . . . . . . . . . . . . . . . . . . . 553 13.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 553 13.2 configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .553 13.3 control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 54 13.4 operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 556 13.4.1 auxiliary frequency output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 556 13.4.2 auxiliary frequency generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 556 13.4.3 interval timer function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 556 chapter 14 a/d converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 557 14.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 557 14.2 configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .558 14.3 control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 60 14.4 operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 569 14.4.1 basic operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 569 14.4.2 operation mode and trigger mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 570 14.5 operation in a/d trigger mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 575 14.5.1 select mode operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 575 14.5.2 scan mode operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 578 14.6 operation in timer trigger mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 580 14.6.1 select mode operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 580
11 user?s manual u16580ee2v0ud00 14.6.2 scan mode operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 584 14.7 operation in external trigger mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 586 14.7.1 select mode operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 586 14.7.2 scan mode operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 590 14.8 precautions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .592 chapter 15 asynchronous serial interface c (uartc) . . . . . . . . . . . . . . . . . . . . . . . . 593 15.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 593 15.2 configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .594 15.3 control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 96 15.4 interrupt requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 9 15.5 operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 610 15.5.1 data format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 610 15.5.2 sbf transmission/reception format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 612 15.5.3 sbf transmit operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 614 15.5.4 sbf receive operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 615 15.5.5 uart transmit operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 616 15.5.6 continuous transmit operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 617 15.5.7 uart receive operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 619 15.5.8 receive error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 620 15.5.9 parity types and operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 621 15.5.10 receive data noise filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 622 15.6 dedicated baud rate generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 623 15.6.1 baud rate generator configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 623 15.6.2 baud rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 624 15.6.3 baud rate error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 624 15.6.4 baud rate setting example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 625 15.6.5 allowable baud rate range during reception . . . . . . . . . . . . . . . . . . . . . . . . . . . 626 15.6.6 baud rate during continuous transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . 628 chapter 16 clocked serial interface b (csib) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 629 16.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 629 16.2 configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .629 16.3 control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 33 16.4 operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 639 16.4.1 single transfer mode (master mode, transmission/reception mode) . . . . . . . . 639 16.4.2 single transfer mode (master mode, transmission mode) . . . . . . . . . . . . . . . . 640 16.4.3 single transfer mode (master mode, reception mode) . . . . . . . . . . . . . . . . . . . 641 16.4.4 continuous mode (master mode, transmission/reception mode) . . . . . . . . . . . 642 16.4.5 continuous mode (master mode, transmission mode) . . . . . . . . . . . . . . . . . . . 643 16.4.6 continuous mode (master mode, reception mode) . . . . . . . . . . . . . . . . . . . . . 644 16.4.7 continuous reception mode (error). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 645 16.4.8 continuous mode (slave mode, transmission/reception mode) . . . . . . . . . . . . 646 16.4.9 continuous mode (slave mode, reception mode) . . . . . . . . . . . . . . . . . . . . . . . 647 16.4.10 clock timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 648 16.5 output pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 650 16.6 operation flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 651 16.7 baud rate generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 657 16.7.1 configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 657 16.7.2 control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 658 16.7.3 baud rate generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 660
12 user?s manual u16580ee2v0ud00 chapter 17 clocked serial interface 3 (csi3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 661 17.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 661 17.2 configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .662 17.3 control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 64 17.4 dedicated baud rate generator 3n (brg3n) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 677 17.5 operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 679 17.5.1 operation modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 679 17.5.2 function of csi data buffer register (csibufn) . . . . . . . . . . . . . . . . . . . . . . . . 680 17.5.3 data transfer direction specification function . . . . . . . . . . . . . . . . . . . . . . . . . . 681 17.5.4 transfer data length changing function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 683 17.5.5 function to select serial clock and data phase . . . . . . . . . . . . . . . . . . . . . . . . . 684 17.5.6 master mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 685 17.5.7 slave mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 686 17.5.8 transfer clock selection function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 687 17.5.9 single mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 687 17.5.10 consecutive mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 689 17.5.11 transmission mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 691 17.5.12 reception mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 691 17.5.13 transmission/reception mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 691 17.5.14 delay control of transmission/reception completion interrupt (intc3n) . . . . . . 692 17.5.15 transfer wait function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 693 17.5.16 output pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 696 17.5.17 csibufn overflow interrupt signal (intc3novf) . . . . . . . . . . . . . . . . . . . . . . 697 17.6 operating procedures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 698 17.6.1 single mode (master mode, transmission mode) . . . . . . . . . . . . . . . . . . . . . . . 698 17.6.2 single mode (master mode, reception mode). . . . . . . . . . . . . . . . . . . . . . . . . . 700 17.6.3 single mode (master mode, transmission/reception mode) . . . . . . . . . . . . . . . 702 17.6.4 single mode (slave mode, transmission mode) . . . . . . . . . . . . . . . . . . . . . . . . 704 17.6.5 single mode (slave mode, reception mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . 706 17.6.6 single mode (slave mode, transmission/reception mode) . . . . . . . . . . . . . . . . 708 17.6.7 consecutive mode (master mode, transmission mode) . . . . . . . . . . . . . . . . . . 710 17.6.8 consecutive mode (master mode, reception mode) . . . . . . . . . . . . . . . . . . . . . 712 17.6.9 consecutive mode (master mode, transmission/reception mode) . . . . . . . . . . 714 17.6.10 consecutive mode (slave mode, transmission mode) . . . . . . . . . . . . . . . . . . . 716 17.6.11 consecutive mode (slave mode, reception mode) . . . . . . . . . . . . . . . . . . . . . . 718 17.6.12 consecutive mode (in slave mode and transmission/reception mode) . . . . . . 720 17.7 cautions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 722 chapter 18 afcan controller. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 723 18.1 outline description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 3 18.1.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 723 18.1.2 implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 723 18.1.3 overview of functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 724 18.1.4 configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 725 18.2 can protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .726 18.2.1 frame format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 726 18.2.2 frame types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 727 18.2.3 data frame and remote frame. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 728 18.2.4 error frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 736 18.2.5 overload frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 737 18.3 functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 738 18.3.1 determining bus priority . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 738 18.3.2 bit stuffing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 738 18.3.3 multi masters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 739 18.3.4 multi cast. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 739 18.3.5 can sleep mode/can stop mode function. . . . . . . . . . . . . . . . . . . . . . . . . . . . 739 18.3.6 error control function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 739 18.3.7 baud rate control function. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 745
13 user?s manual u16580ee2v0ud00 18.4 connection with target system. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 749 18.5 internal registers of can controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 750 18.5.1 can controller configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 750 18.5.2 register access type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 752 18.5.3 register bit configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 755 18.6 control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 59 18.6.1 can global control register (cngmctrl) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 759 18.6.2 can global clock selection register (cngmcs) . . . . . . . . . . . . . . . . . . . . . . . . 761 18.6.3 can global automatic block transmission control register (cngmabt) . . . . . . 762 18.6.4 can global configuration register (cngmconf) . . . . . . . . . . . . . . . . . . . . . . . 764 18.6.5 can global automatic block transmission delay register (cngmabtd) . . . . . 765 18.6.6 can module mask contro l registers (cnmaskml, cnmaskmh) . . . . . . . . . . 766 18.6.7 can module control register (cnctrl) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 770 18.6.8 can module last error code register (cnlec) . . . . . . . . . . . . . . . . . . . . . . . . . 774 18.6.9 can module information register (cninfo) . . . . . . . . . . . . . . . . . . . . . . . . . . . 775 18.6.10 can module error counter register (cnerc) . . . . . . . . . . . . . . . . . . . . . . . . . . 776 18.6.11 can module interrupt enable register (cnie) . . . . . . . . . . . . . . . . . . . . . . . . . . 777 18.6.12 can module interrupt status register (cnints) . . . . . . . . . . . . . . . . . . . . . . . . 779 18.6.13 can module bit rate prescaler register (cnbrp) . . . . . . . . . . . . . . . . . . . . . . . 781 18.6.14 can module bit rate register (cnbtr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 782 18.6.15 can module last in-pointer register (cnlipt) . . . . . . . . . . . . . . . . . . . . . . . . . 784 18.6.16 can module receive history list register (cnrgpt) . . . . . . . . . . . . . . . . . . . . . 785 18.6.17 can module last out-pointer register (cnlopt) . . . . . . . . . . . . . . . . . . . . . . . 787 18.6.18 can module transmit history list register (cntgpt) . . . . . . . . . . . . . . . . . . . . 788 18.6.19 can module time stamp register (cnts) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 790 18.6.20 can message data byte register (cnmdataxm) (x = 0 to 7), (cnmdatazm) (z = 01, 23, 45, 67) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 792 18.6.21 can message data length register m (cnmdlcm) . . . . . . . . . . . . . . . . . . . . . 794 18.6.22 can message configuration register (cnmconfm) . . . . . . . . . . . . . . . . . . . . 795 18.6.23 can message id register m (cnmidlm, cnmidhm). . . . . . . . . . . . . . . . . . . . 797 18.6.24 can message control register m (cnmctrlm) . . . . . . . . . . . . . . . . . . . . . . . 798 18.7 bit set/clear function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 801 18.8 can controller initializ ation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 803 18.8.1 initialization of can module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 803 18.8.2 initialization of message buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 803 18.8.3 redefinition of message buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 803 18.8.4 transition from initialization mode to operation mode . . . . . . . . . . . . . . . . . . . 805 18.8.5 resetting error counter cnerc of can module . . . . . . . . . . . . . . . . . . . . . . . 805 18.9 message reception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 806 18.9.1 message reception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 806 18.9.2 receive history list function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 807 18.9.3 mask function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 809 18.9.4 multi buffer receive block function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 811 18.9.5 remote frame reception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 812 18.10 message transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 813 18.10.1 message transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 813 18.10.2 transmit history list function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 815 18.10.3 automatic block transmission (abt). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 816 18.10.4 transmission abort process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 818 18.10.5 remote frame transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 819 18.11 power save modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 820 18.11.1 can sleep mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 820 18.11.2 can stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 822 18.11.3 example of using power saving modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 823 18.12 interrupt function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 824 18.12.1 interrupts generated by can module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 824
14 user?s manual u16580ee2v0ud00 18.13 diagnosis functions and special operational modes . . . . . . . . . . . . . . . . . . . . . . . 825 18.13.1 receive-only mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 825 18.13.2 single-shot mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 826 18.13.3 self-test mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 827 18.14 time stamp function. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 828 18.15 baud rate settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 9 18.15.1 representative examples of baud rate settings . . . . . . . . . . . . . . . . . . . . . . . . 833 18.16 operation of can controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 837 chapter 19 random number generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 861 19.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 861 19.2 configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .861 19.3 operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 862 19.3.1 access timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 862 chapter 20 port functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 863 20.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 863 20.2 port configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 4 20.2.1 function of each port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 865 20.2.2 port types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 866 20.2.3 peripheral registers of i/o ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 889 20.2.4 peripheral registers of valid edge control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 892 20.3 port pin functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 3 20.3.1 port 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 893 20.3.2 port 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 894 20.3.3 port 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 898 20.3.4 port 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 902 20.3.5 port 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 906 20.3.6 port 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 909 20.3.7 port 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 914 20.3.8 port 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 920 20.3.9 port 8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 924 20.3.10 port 9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 8 20.3.11 port 10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 932 20.3.12 port al . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 935 20.3.13 port ah . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 939 20.3.14 port dl . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 941 20.3.15 port dh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 945 20.3.16 port cs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 949 20.3.17 port ct . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 951 20.3.18 port cm. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 953 20.3.19 port cd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 956 20.4 noise elimination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 59 chapter 21 reset function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 963 21.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 963 21.2 configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .963 21.3 operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 964 chapter 22 internal ram parity check function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 965 22.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 965 22.2 operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 965 22.3 control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 66
15 user?s manual u16580ee2v0ud00 chapter 23 on-chip debug function (ocd) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 969 23.1 function overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 969 23.1.1 on-chip debug unit type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 969 23.1.2 debug function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 969 23.2 connection with n-wire type emulator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 971 23.2.1 kel connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 971 23.3 precautions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .975 chapter 24 flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 977 24.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 977 24.2 memory configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 978 24.3 functional outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 9 24.4 rewriting by dedicated flash programmer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 982 24.4.1 programming environment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 982 24.4.2 communication mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 983 24.4.3 flash memory control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 986 24.4.4 selection of communication mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 987 24.4.5 communication commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 988 24.4.6 pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 989 24.5 rewriting by self programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 994 24.5.1 overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 994 24.5.2 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 995 chapter 25 electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 997 25.1 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 997 25.2 general characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 998 25.2.1 capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 998 25.2.2 operating conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 998 25.2.3 oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 999 25.3 dc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000 25.4 ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1001 25.4.1 external asynchronous memory access read timing . . . . . . . . . . . . . . . . . . . 1002 25.4.2 external asynchronous memory access write timing . . . . . . . . . . . . . . . . . . . 1004 25.4.3 reset timing (power up/down sequence) . . . . . . . . . . . . . . . . . . . . . . . . . . 1006 25.4.4 interrupt timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1007 25.5 peripheral characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1008 25.5.1 timer characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1008 25.5.2 serial interface characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1011 25.5.3 a/d converter characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1020 25.6 flash programming characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1021 chapter 26 package drawings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1023 chapter 27 recommended soldering conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . 1025 appendix a index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 7 appendix b revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1037
16 user?s manual u16580ee2v0ud00
17 user?s manual u16580ee2v0ud00 list of figures figure 1-1: pin configuration 208-pin plastic lqfp ...................................................................... 36 figure 1-2: pin configuration 256-pin plastic bga (21 21) ........................................................ 37 figure 1-3: internal block diagram .............................................................................................. .. 41 figure 2-1: pin i/o circuits .................................................................................................... ........ 73 figure 2-2: noise removal time control register (1/2) .............................................................. 75 figure 3-1: cpu register set .................................................................................................... .... 78 figure 3-2: program counter (pc) ............................................................................................... 79 figure 3-3: interrupt status saving registers (eipc, eipsw) ..................................................... 81 figure 3-4: nmi status saving registers (fepc, fepsw) ............... ................ ................ ........... 82 figure 3-5: interrupt source register (ecr) ............................................................................... 82 figure 3-6: program status word (psw) .................................................................................... 83 figure 3-7: callt execution status saving registers (ctpc, ctpsw) .................................... 84 figure 3-8: exception/debug tr ap status saving registers (dbpc , dbpsw) ........... ............ ..... 85 figure 3-9: callt base pointer (ctbp) ...................................................................................... 85 figure 3-10: floating point arithmetic control register (ect) ....................................................... 86 figure 3-11: floating point arithmetic status register (efg) ........................................................ 87 figure 3-12: cpu address space .................................................................................................. .89 figure 3-13: address space image ................................................................................................ .90 figure 3-14: program space ...................................................................................................... ..... 91 figure 3-15: data space......................................................................................................... ......... 91 figure 3-16: memory map ......................................................................................................... ...... 92 figure 3-17: internal rom / internal flash memory area................................................................ 93 figure 3-18: on-chip peripheral i/o area ....................................................................................... 9 4 figure 3-19: programmable peripheral i/o area (outline) ............................................................ 109 figure 3-20: programmable peripheral area control register bpc ............................................. 110 figure 3-21: processor command register (prcmd).................................................................. 128 figure 3-22: system status register format phs ...................................................................... 129 figure 4-1: memory block function ............................................................................................. 13 4 figure 4-2: chip area select control registers 0, 1 (1/2) ......................................................... 135 figure 4-3: bus cycle configuration registers 0, 1 (bct0, bct1) ........................................... 138 figure 4-4: bus size configuration register (bsc) .................................................................... 140 figure 4-5: big endian addresses within word ........................................................................... 141 figure 4-6: little endian addresses within word ......................................................................... 141 figure 4-7: endian configuration register (bec) ....................................................................... 142 figure 4-8: data wait control registers 0, 1 (dwc0, dwc1) format ..................................... 162 figure 4-9: address wait control register (awc) ..................................................................... 163 figure 4-10: bus cycle control register (bcc) ........................................................................... 165 figure 4-11: bus clock dividing control register (dvc) .............................................................. 166 figure 5-1: examples of connection to sram (1/2).................................................................... 170 figure 5-2: sram, external rom, external i/o access timing (1/8).......................................... 172 figure 6-1: dma transfer memory start address registers 0 to 7 (mar0 to mar7) ................ 182 figure 6-2: dma transfer sfr start address registers 2, 3 (sar2, sar3) ............................. 183 figure 6-3: dma transfer count registers 0 to 7 (dtcr0 to dtcr7) ...................................... 184 figure 6-4: dma mode control register (dmamc) .................................................................... 185 figure 6-5: dma status register (dmas) .................................................................................. 185 figure 6-6: dma data size control register (dmdsc) ............................................................. 186 figure 6-7: dma trigger factor registers 4 to 7 (dtfr4 to dtfr7) ........................................ 187 figure 6-8: initialization of dma transfer for a/d conversion result.......................................... 189 figure 6-9: operation of dma channel 0/1 ................................................................................. 190 figure 6-10: dma channel 0 and 1 trigger signal timing ............................................................ 191 figure 6-11: initialization of dma transfer for tmrn compare registers .................................... 193 figure 6-12: operation of dma channel 2/3 ................................................................................. 194 figure 6-13: dma channel 2 and 3 trigger signal timing ............................................................ 195 figure 6-14: initialization of dma transfer for serial data reception ........................................... 197 figure 6-15: operation of dma channel 4/5 ................................................................................. 198
18 user?s manual u16580ee2v0ud00 figure 6-16: dma channel 4 and 5 trigger signal timing ............................................................ 199 figure 6-17: initialization of dma transfer for serial data transmission ...................................... 201 figure 6-18: dma channel 6 and 7 trigger signal timing ............................................................ 202 figure 6-19: operation of dma channel 6/7 ................................................................................. 203 figure 6-20: cpu and dma controller processing of dma transfer termination (example)....... 204 figure 6-21: correlation between serial i/o interface interrupts and dma completion interrupts 206 figure 7-1: processing configuration of non-maskable interrupt................................................ 213 figure 7-2: acknowledging non-maskable interrupt request ..................................................... 214 figure 7-3: reti instruction processing ...................................................................................... 215 figure 7-4: non-maskable interrupt status flag (np) ................................................................ 216 figure 7-5: nmi edge detection specification: interrupt mode register 0 (intm0) .................. 216 figure 7-6: maskable interrupt processing .................................................................................. 218 figure 7-7: reti instruction processing ...................................................................................... 219 figure 7-8: example of processing in which another interrupt request is issued while an interrupt is being processed (1/2) ............................................................... 221 figure 7-9: example of processing interrupt requests simultaneously generated.................... 223 figure 7-10: interrupt control register (picn) .............................................................................. 224 figure 7-11: interrupt mask registers 0 to 2 (imr0 to imr2) ....................................................... 228 figure 7-12: interrupt mask registers 3 to 6 (imr3 to imr6) ....................................................... 229 figure 7-13: interrupt service priority register (ispr) ................................................................. 230 figure 7-14: maskable interrupt status flag (id) ............................................................................ 231 figure 7-15: interrupt mode register 0 (intm0) .......................................................................... 233 figure 7-16: interrupt mode register 1 (intm1) .......................................................................... 234 figure 7-17: interrupt mode register 2 (intm2) .......................................................................... 235 figure 7-18: interrupt mode register 3 (intm3) .......................................................................... 236 figure 7-19: software exception processing................................................................................. 237 figure 7-20: reti instruction processing ...................................................................................... 23 8 figure 7-21: exception status flag (ep) ...................................................................................... 23 9 figure 7-22: illegal opcode..................................................................................................... ....... 240 figure 7-23: exception trap processing........................................................................................ 24 1 figure 7-24: restore processing from exception trap.................................................................. 241 figure 8-1: clock generator ..................................................................................................... ... 243 figure 8-2: power save mode state transition diagram ............................................................ 244 figure 9-1: block diagram of timer p.......................................................................................... 24 8 figure 9-2: tmpn capture/compare register 0 (tpnccr0) ..................................................... 249 figure 9-3: tmpn capture/compare register 1 (tpnccr1) ..................................................... 250 figure 9-4: tmpn counter register (tpncnt) .......................................................................... 251 figure 9-5: tmpn control register 0 (tpnctl0) ...................................................................... 252 figure 9-6: tmpn control register 1 (tpnctl1) (1/2)............................................................... 253 figure 9-7: tmpn i/o control register 0 (tpnioc0) .................................................................. 255 figure 9-8: tmpn i/o control register 1 (tpnioc1) .................................................................. 256 figure 9-9: tmpn i/o control register 2 (tpnioc2) .................................................................. 257 figure 9-10: tmpn option register 0 (tpnopt0) ........................................................................ 258 figure 9-11: tmpn input control register 0 (tpic0) .................................................................. 259 figure 9-12: tmp input control register 1 (tpic1) .................................................................... 260 figure 9-13: tmp input control register 1 (tpic1) .................................................................... 261 figure 9-14: basic operation flow for anytime write.................................................................... 263 figure 9-15: timing diagram for anytime write............................................................................. 264 figure 9-16: basic operation flow for reload (batch rewrite) ..................................................... 265 figure 9-17: timing chart for reload ............................................................................................ 266 figure 9-18: flowchart of basic operation in interval timer mode................................................ 267 figure 9-19: basic operation timing in interval timer mode (1/2) ................................................ 268 figure 9-20: flowchart of basic operation in external event count mode.................................... 271 figure 9-21: basic operation timing in external event count mode (1/2) .................................... 272 figure 9-22: flowchart of basic operation in external trigger pulse output mode ...................... 275 figure 9-23: basic operation timing in external trigger pulse output mode ............................... 276 figure 9-24: flowchart of basic operation in one-shot pulse mode ............................................ 278 figure 9-25: timing of basic operation in one-shot pulse mode ................................................. 279
19 user?s manual u16580ee2v0ud00 figure 9-26: flowchart of basic operation in pwm mode (1/2) .................................................... 281 figure 9-27: basic operation timing in pwm mode (1/2) ............................................................. 283 figure 9-28: flowchart of basic operation in free-running mode................................................ 286 figure 9-29: basic operation timing in free-running mode (tpnccs1 = 0, tpnccs0 = 0) ...... 287 figure 9-30: basic operation timing in free-running mode (tpnccs1 = 1, tpnccs0 = 1) ...... 288 figure 9-31: basic operation timing in free-running mode (tpnccs1 = 1, tpnccs0 = 0) ...... 289 figure 9-32: basic operation timing in free-running mode (tpnccs1 = 0, tpnccs0 = 1) ...... 290 figure 9-33: flowchart of pulse period measurement .................................................................. 292 figure 9-34: basic operation timing of pulse period measurement............................................. 293 figure 9-35: flowchart of alternating pulse width and pulse space measurement ..................... 294 figure 9-36: basic operation timing of alternating pulse width and pulse space measurement 295 figure 9-37: flowchart of simultaneous pulse wi dth and pulse space measurement................. 296 figure 9-38: basic operation timi ng of simultaneous pulse width and pulse space measurement ................................................................................ 297 figure 10-1: timer rn block diagram ........................................................................................... 30 1 figure 10-2: tmrn capture/compare register 0 (trnccr0) ..................................................... 302 figure 10-3: tmrn capture/compare register 1 (trnccr1) ..................................................... 303 figure 10-4: tmrn capture/compare register 2 (trnccr2) ..................................................... 304 figure 10-5: tmrn capture/compare register 3 (trnccr3) ..................................................... 305 figure 10-6: tmrn compare register 4 (trnccr4) ................................................................... 306 figure 10-7: tmrn compare register 5 (trnccr5) ................................................................... 307 figure 10-8: tmrn counter read register (trncnt) ................................................................ 308 figure 10-9: tmrn sub-counter read register (trnsbc) ......................................................... 308 figure 10-10: tmrn dead time setting register 0 (trndtc0) .................................................... 309 figure 10-11: tmrn dead time setting register 1 (trndtc1) .................................................... 309 figure 10-12: tmrn control register 0 (trnctl0) (1/2) .............................................................. 310 figure 10-13: tmrn control register 1 (trnctl1) (1/2) ............................................................... 312 figure 10-14: tmrn i/o control register 0 (trnioc0) ................................................................. 314 figure 10-15: tmr1 i/o control register 1 (tr1ioc1) ................................................................. 315 figure 10-16: tmr1 i/o control register 2 (tr1ioc2) ................................................................. 316 figure 10-17: tmrn i/o control register 3 (trnioc3) ................................................................. 317 figure 10-18: tmrn i/o control register 4 (trnioc4) ................................................................. 318 figure 10-19: tmrn option register 0 (trnopt0) (1/2)................................................................ 319 figure 10-20: tmrn option register 1 (trnopt1) (1/2)................................................................ 321 figure 10-21: tmrn option register 2 (trnopt2) (1/2)................................................................ 323 figure 10-22: tmrn option register 3 (trnopt3) (1/2)................................................................ 325 figure 10-23: tmrn option register 6 (trnopt6) ....................................................................... 327 figure 10-24: tmrn option register 7 (trnopt7) ....................................................................... 328 figure 10-25: anytime rewrite timing ............................................................................................ 333 figure 10-26: basic operation flow during batch rewrite .............................................................. 338 figure 10-27: batch rewrite timing (1/2) ........................................................................................ 339 figure 10-28: torn7 pin output timing 1 ...................................................................................... 346 figure 10-29: interrupt signal output example (1/2) ....................................................................... 350 figure 10-30: up count flags timings (1/2) ................................................................................... 354 figure 10-31: normal phase/inverted phase simultaneous active detection flag timing ............. 355 figure 10-32: reload hold flag timings ......................................................................................... 3 56 figure 10-33: interrupt thinning out operations (1/2) .................................................................... 358 figure 10-34: examples when peak interrupts and valley interrupts occur alternately (1/2)......... 360 figure 10-35: a/d conversion trigger output controller................................................................. 362 figure 10-36: a/d conversion trigger timings (1/2) ....................................................................... 364 figure 10-37: error interrupt (inttrner) and error signal (trner) output controller................. 366 figure 10-38: error interrupt and error signal output controller in pwm mode ............................. 367 figure 10-39: error interrupt and error signal output controller in triangular wave pwm mode.... 368 figure 10-40: error interrupt and error signal output controller in high-accuracy t-pwm mode / pwm mode with dead time ................................ 369 figure 10-41: basic operation flow in interval timer mode............................................................ 370 figure 10-42: basic timing in interval timer mode (1/2)................................................................. 372 figure 10-43: basic operation timing in external event count mode (1/4) .................................... 376
20 user?s manual u16580ee2v0ud00 figure 10-44: basic operation flow in external trigger pulse output mode .................................. 382 figure 10-45: basic operation timing in external trigger pulse output mode ............................... 383 figure 10-46: basic operation flow in one-shot pulse mode ........................................................ 386 figure 10-47: basic operation timing in one-shot pulse mode ..................................................... 387 figure 10-48: basic operation mode in pwm mode (1/2) ............................................................... 390 figure 10-49: basic operation timing in pwm mode (1/2) ............................................................. 392 figure 10-50: basic operation flow in free-running mode............................................................ 394 figure 10-51: basic operation timing in free-running mode (compare function) ....................... 397 figure 10-52: basic operation timing in free-running mode (capture function) ......................... 398 figure 10-53: basic operation timing in free-running mode (compare/capture function).......... 399 figure 10-54: basic operation timing in pulse width measurement mode .................................... 400 figure 10-55: basic operation timing in triangular wave pwm mode .......................................... 404 figure 10-56: high-accuracy t-pwm mode block diagram............................................................ 405 figure 10-57: counter operation in high-accuracy t-pwm mode.................................................. 409 figure 10-58: sub-counter operation in high-accuracy t-pwm mode .......................................... 409 figure 10-59: timer output example when trnce = 1 is set (initial) (high-accuracy t-pwm mode).................................................................................. 410 figure 10-60: timer output example during operation (high-accuracy t-pwm mode) ................ 411 figure 10-61: torn1 pin output example when performing additional pulse control.................. 412 figure 10-62: torn1 pin output example when addi tional pulse control is not performed ........ 413 figure 10-63: timings of timer output in high-accuracy t-pwm mode (1/3)................................. 414 figure 10-64: timer output change after compare register updating timings (1/3) .................... 418 figure 10-65: compare register value after trough reload timing (1/3)...................................... 421 figure 10-66: compare register value after trough reload (trndtc1 < trndtc0) (1/3) ......... 424 figure 10-67: compare register value after trough reload (1/3) ................................................. 427 figure 10-68: output waveform example when dead time is set ................................................ 430 figure 10-69: dead time control in high-accuracy t-pwm mode ................................................. 431 figure 10-70: operation example setting is out of range ............................................................. 432 figure 10-71: error interrupt operation example ............................................................................ 433 figure 10-72: block diagram in pwm mode with dead time......................................................... 434 figure 10-73: output waveform example in pwm mode with dead time...................................... 436 figure 10-74: timer output example when trnce = 1 is set (initial) (pwm mode with dead time) ................................................................................... 439 figure 10-75: output waveform example in pwm mode with dead time...................................... 440 figure 10-76: error interrupt (inttrner) in pwm mode with dead time...................................... 441 figure 11-1: block diagram of timer t.......................................................................................... 4 46 figure 11-2: tmtn capture/compare register 0 (ttnccr0) ...................................................... 447 figure 11-3: tmtn capture/compare register 1 (ttnccr1) ...................................................... 448 figure 11-4: tmtn counter write buffer register (ttntcw) ...................................................... 450 figure 11-5: tmtn counter read buffer register (ttncnt) ....................................................... 450 figure 11-6: tmtn control register 0 (ttnctl0) (1/2) ................................................................ 451 figure 11-7: tmtn control register 1 (ttnctl1) (1/2) ................................................................ 453 figure 11-8: tmtn control register 2 (ttnctl2) (1/2) ................................................................ 455 figure 11-9: tmtn i/o control register 0 (ttnioc0) .................................................................. 457 figure 11-10: tmtn i/o control register 1 (ttnioc1) .................................................................. 458 figure 11-11: tmtn i/o control register 2 (ttnioc2) .................................................................. 459 figure 11-12: tmtn i/o control register 3 (ttnioc3) (1/2)........................................................... 460 figure 11-13: tmtn option register 0 (ttnopt0) ........................................................................ 462 figure 11-14: tmtn option register 1 (ttnopt1) (1/2)................................................................. 463 figure 11-15: tmtn option register 2 (ttnopt2) ......................................................................... 465 figure 11-16: basic operation flow for anytime rewrite ................................................................ 469 figure 11-17: basic anytime rewrite operation timing .................................................................. 470 figure 11-18: basic operation flow for reload (batch rewrite) ..................................................... 471 figure 11-19: basic reload operation timing................................................................................. 472 figure 11-20: basic operation flow in interval timer mode............................................................ 473 figure 11-21: basic timing in interval timer mode (1/2)................................................................. 474 figure 11-22: basic operation timing in external event count mode (1/4) .................................... 477 figure 11-23: basic operation flow in external trigger pulse output mode .................................. 482
21 user?s manual u16580ee2v0ud00 figure 11-24: basic operation timing in external trigger pulse output mode ............................... 483 figure 11-25: basic operation flow in one-shot pulse mode ........................................................ 485 figure 11-26: basic operation timing in one-shot pulse mode ..................................................... 486 figure 11-27: basic operation mode in pwm mode (1/2) ............................................................... 487 figure 11-28: basic operation timing in pwm mode (1/2) ............................................................. 489 figure 11-29: basic operation flow in free-running mode............................................................ 491 figure 11-30: basic operation timing in free-running mode (compare function) ....................... 493 figure 11-31: basic operation timing in free-running mode (capture function) ......................... 494 figure 11-32: basic operation timing in free-running mode (compare/capture function).......... 495 figure 11-33: basic operation timing in pulse width measurement mode .................................... 496 figure 11-34: basic operation timing in triangular wave pwm mode .......................................... 498 figure 11-35: encoder count function up/down coun t selection specificati on timings (1/6) ...... 501 figure 11-36: counter clearing to 0000h through encoder clear input (pin tecrtn) timings (1/4) ............................................................................................................. 508 figure 11-37: counter hold through bit ttnecc timings (1/5) ...................................................... 512 figure 11-38: basic timing in offset trigger generation mode ...................................................... 517 figure 12-1: block diagram of timer enc10 (tmenc10) ............................................................ 522 figure 12-2: timer enc10 (tmenc10) ........................................................................................ 523 figure 12-3: compare register 100 (cm100) .............................................................................. 525 figure 12-4: compare register 101 (cm101) .............................................................................. 526 figure 12-5: capture/compare register 100 (cc100) ................................................................. 527 figure 12-6: capture/compare register 101 (cc101) ................................................................. 528 figure 12-7: timer unit mode register 10 (tum10) ................................................................... 529 figure 12-8: timer control register 10 (tmc10) (1/2) ................................................................. 530 figure 12-9: capture/compare control register 10(ccr10) ....................................................... 532 figure 12-10: signal edge selection register 10 ( sesa10) (1/2) .... ............ ............. ............. ...... 533 figure 12-11: prescaler mode register 10 (prm10) ..................................................................... 535 figure 12-12: status register 10 (status10) ............................................................................. 537 figure 12-13: tmenc10 block diagram (during pwm output operation) ..................................... 540 figure 12-14: pwm signal output example (when alvt10 bit = 0 is set).................................... 541 figure 12-15: mode 1 (when rising edge is specified as valid edge of tiud1 pin) ..................... 543 figure 12-16: mode 1 (when rising edge is specified as valid edge of tiud1 pin): in case of simultaneous tiud1, tcud1 pin edge timing....................................... 543 figure 12-17: mode 2 (when rising edge is specified as valid edge of tiud1, tcud1 pins) ..... 544 figure 12-18: mode 3 (when rising edge is specified as valid edge of tiud1 pin) ..................... 545 figure 12-19: mode 3 (when rising edge is specified as valid edge of tiud1 pin): in case of simultaneous tiud1, tcud1 pin edge timing....................................... 545 figure 12-20: mode 4 ............................................................................................................ .......... 546 figure 12-21: example of tmenc10 operation when interval operation and transfer operation are combined ........................................................................................... 547 figure 12-22: example of tm1operation in udc mo de .................................................................. 548 figure 12-23: clear operation upon match with cm100 during tmenc10 up count operation ... 550 figure 12-24: clear operation upon match with cm101 during tmenc10 down count operation .............................................................................................. 550 figure 12-25: count value clear operation upon compare match................................................. 551 figure 12-26: internal operation during transfer operation ........................................................... 551 figure 12-27: interrupt output upon compare match (cm101 with operation mode set to general-purpose timer mode and count clock set to f xx /8) ......................... 552 figure 12-28: tm1ubdn flag operation ......................................................................................... 552 figure 13-1: block diagram of au xiliary frequency output function ............................................ 553 figure 13-2: prescaler mode register 2 (prsm2) ...................................................................... 554 figure 13-3: prescaler compare register 2 (prscm2) .............................................................. 555 figure 14-1: block diagram of a/d converter (adcn) .................................................................. 559 figure 14-2: a/d converter n mode register 0 (admn0) ............................................................ 560 figure 14-3: a/d converter n mode register 1 (admn1) (1/2) ..................................................... 561 figure 14-4: a/d converter n mode register 2 (admn2) ............................................................ 563 figure 14-5: a/d converter n trigger source select register (adtrseln) ............................... 564
22 user?s manual u16580ee2v0ud00 figure 14-6: a/d conversion result registers n0 to n9, n0h to n9h (adcrn0 to adcrn9, adcrn0h to adcrn9h) ..................................................... 565 figure 14-7: relationship between analog input voltage and a/d conversion results ............... 567 figure 14-8: a/d conversion result registers n0 to n9, n0h to n9h (adcrn0 to adcrn9, adcrn0h to adcrn9h) ..................................................... 568 figure 14-9: select mode operation timing: 1-buffer mode (anin1)............................................ 572 figure 14-10: select mode operation timing: 4-buffer mode (anin2)............................................ 573 figure 14-11: scan mode operation timing: 4-channel scan (ani0 to ani3)................................ 574 figure 14-12: example of 1-buffer mode operation (a/d trigger select: 1 buffer)......................... 575 figure 14-13: example of 4-buffer mode operation (a/d trigger select: 4 buffers)....................... 577 figure 14-14: example of scan mode operation (a/d trigger scan).............................................. 579 figure 14-15: example of 1-buffer mode operation (timer trigger select: 1 buffer) (anin1) ........ 581 figure 14-16: example of 4-buffer mode operation (timer trigger select: 4 buffers) (anin3) ...... 583 figure 14-17: example of scan mode operation (timer trigger scan) (anin0 to anin4) .............. 585 figure 14-18: example of 1-buffer mode operation (external trigger select: 1 buffer) (anin1) .... 587 figure 14-19: example of 4-buffer mode operation (external trigger select: 4 buffers) (anin2) .. 589 figure 14-20: example of scan mode operation (external trigger scan) (anin0 to anin3) .......... 591 figure 15-1: block diagram of asynchronous serial interface n ................................................... 595 figure 15-2: uartcn control register 0 (ucnctl0) (1/2) ........................................................ 596 figure 15-3: uartcn control register 1 (ucnctl1) ................................................................. 598 figure 15-4: uartcn control register 2 (ucnctl2) ................................................................. 599 figure 15-5: uartcn option control register 0 (ucnopt0) (1/2) ............................................. 600 figure 15-6: uartcn option control register 1 (ucnopt1) ..................................................... 602 figure 15-7: uartcn status register (ucnstr) (1/2) .............................................................. 604 figure 15-8: uartcn status register 1 (ucnstr1) .................................................................. 606 figure 15-9: uartcn receive data register (ucnrx, ucnrxl) .............................................. 607 figure 15-10: uartcn transmit data register (ucntx, ucntxl) .............................................. 608 figure 15-11: uartc transmit/receive data format (1/2)............................................................ 610 figure 15-12: lin transmission manipulation outline..................................................................... 612 figure 15-13: lin reception manipulation outline .......................................................................... 613 figure 15-14: sbf transmission timing ......................................................................................... 61 4 figure 15-15: sbf reception timing.............................................................................................. .615 figure 15-16: uart transmission ................................................................................................. .616 figure 15-17: continuous transmission processing flow............................................................... 617 figure 15-18: continuous transfer operation timing ..................................................................... 618 figure 15-19: uart reception timing............................................................................................ 6 19 figure 15-20: noise filter circuit .............................................................................................. ....... 622 figure 15-21: configuration of baud rate generator ...................................................................... 623 figure 15-22: allowable baud rate range during reception......................................................... 626 figure 15-23: transfer rate during continuous transfer ............................................................... 628 figure 16-1: block diagram of csibn............................................................................................ 6 30 figure 16-2: csibn receive data register (cbnrx, cbnrxl) ................................................... 631 figure 16-3: csibn transmit data register (cbntx, cbntxl) ................................................... 632 figure 16-4: csibn control register 0 (cbnctl0) (1/2) ............................................................. 633 figure 16-5: csibn control register 1 (cbnctl1) ..................................................................... 635 figure 16-6: csibn control register 2 (cbnctl2) ...................................................................... 636 figure 16-7: effect of transfer data length setting ...................................................................... 637 figure 16-8: csibn status register (cbnstr) ........................................................................... 638 figure 16-9: single transfer mode (master mode, transmission/reception mode) ..................... 639 figure 16-10: single transfer mode (master mode, transmission mode) ...................................... 640 figure 16-11: single transfer mode (master mode, reception mode)............................................ 641 figure 16-12: continuous mode (master mode, transmission/reception mode) ........................... 642 figure 16-13: continuous mode (master mode, transmission mode)............................................. 643 figure 16-14: continuous mode (master mode, reception mode).................................................. 644 figure 16-15: continuous reception mode (error).......................................................................... 645 figure 16-16: continuous mode (slave mode, transmission/reception mode) ............................. 646 figure 16-17: continuous mode (slave mode, reception mode).................................................... 647 figure 16-18: csibn clock timing (1/2) .......................................................................................... 648
23 user?s manual u16580ee2v0ud00 figure 16-19: operation flow of single transmission..................................................................... 651 figure 16-20: operation flow of single reception (master)............................................................ 652 figure 16-21: operation flow of single reception (slave) ............................................................. 653 figure 16-22: operation flow of continuous transmission............................................................. 654 figure 16-23: operation flow of continuous reception (master) ................................................... 655 figure 16-24: operation flow of continuous reception (slave) ..................................................... 656 figure 16-25: block diagram of baud rate generators 0 and 1 (brg0, brg1) ............................ 657 figure 16-26: block diagram of csibn baud rate generators....................................................... 657 figure 16-27: prescaler mode registers 0 and 1 (prsm0, prsm1) ............................................ 658 figure 16-28: prescaler compare registers 0 and 1 (prscm0, prscm1) ................................. 659 figure 17-1: block diagram of clocked serial interface 3n (csi3n).............................................. 663 figure 17-2: clocked serial interface mode register 3n (csim3n) (1/2) .................................... 664 figure 17-3: clocked serial interface clock select register 3n (csic3n) (1/3) .......................... 666 figure 17-4: receive data buffer register 3n (sirb3n, sirb3nl, sirb3nh) ............................ 669 figure 17-5: chip select csi buffer register 3n (sfcs3n, sfcs3nl) ........................................ 670 figure 17-6: transmit data csi buffer register 3n (sfdb3n, sfdb3nl, sfdb3nh) ................ 671 figure 17-7: csibuf status register 3n (sfa3n)(1/3) ............................................................... 672 figure 17-8: transfer data length select register 3n (csil3n) ................................................. 675 figure 17-9: transfer data number specification register 3n (sfn3n) ..................................... 676 figure 17-10: transfer clock of csi3n ........................................................................................... .677 figure 17-11: function of csi data buffer register n (csibufn)................................................... 680 figure 17-12: data transfer direction specification (msb first) ...................................................... 681 figure 17-13: data transfer direction specification (lsb first) ....................................................... 682 figure 17-14: transfer data length changing function ................................................................. 683 figure 17-15: clock timing...................................................................................................... ........ 684 figure 17-16: master mode ....................................................................................................... ...... 685 figure 17-17: slave mode ........................................................................................................ ....... 686 figure 17-18: single mode ....................................................................................................... ....... 688 figure 17-19: consecutive mode.................................................................................................. ... 690 figure 17-20: delay control of transmission/reception completion interrupt (intc3n):............... 692 figure 17-21: transfer wait function (1/3)...................................................................................... 693 figure 17-22: single mode (master mode, transmission mode)..................................................... 698 figure 17-23: single mode (master mode, reception mode) .......................................................... 700 figure 17-24: single mode (master mode, transmission/reception mode).................................... 702 figure 17-25: single mode (slave mode, transmission mode)....................................................... 704 figure 17-26: single mode (slave mode, reception mode) ............................................................ 706 figure 17-27: single mode (slave mode, transmission/reception mode)...................................... 708 figure 17-28: consecutive mode (master mode, transmission mode) ........................................... 710 figure 17-29: consecutive mode (master mode, reception mode) ................................................ 712 figure 17-30: consecutive mode (master mode, transmission/reception mode).......................... 714 figure 17-31: consecutive mode (slave mode, transmission mode) ............................................. 716 figure 17-32: consecutive mode (slave mode, reception mode) .................................................. 718 figure 17-33: consecutive mode (slave mode, transmission/reception mode)............................ 720 figure 18-1: block diagram of can module.................................................................................. 725 figure 18-2: composition of layers.............................................................................................. .726 figure 18-3: data frame ......................................................................................................... ...... 728 figure 18-4: remote frame ....................................................................................................... ... 729 figure 18-5: start of frame (sof)............................................................................................... .. 730 figure 18-6: arbitration field (in standard format mode) ............................................................. 731 figure 18-7: arbitration field (in extended format mode)............................................................. 731 figure 18-8: control field ...................................................................................................... ........ 732 figure 18-9: data field ......................................................................................................... ......... 733 figure 18-10: crc field ......................................................................................................... ......... 733 figure 18-11: ack field ......................................................................................................... ......... 734 figure 18-12: end of frame (eof) ................................................................................................ .. 734 figure 18-13: interframe space (error active node) ....................................................................... 735 figure 18-14: interframe space (error passive node) .................................................................... 735 figure 18-15: error frame ....................................................................................................... ........ 736
24 user?s manual u16580ee2v0ud00 figure 18-16: overload frame.................................................................................................... ..... 737 figure 18-17: recovery operation from bus-off state through normal recovery sequence ......... 744 figure 18-18: segment setting ................................................................................................... ..... 745 figure 18-19: configuration of data bit time defined by can specification .................................. 746 figure 18-20: hard-synchronization at recognition of dominant level during bus idle.................. 747 figure 18-21: re-synchronization................................................................................................ .... 748 figure 18-22: connection to can bus............................................................................................. 749 figure 18-23: can global control register (cngmctrl) (1/2) ..................................................... 759 figure 18-24: can global clock selection register (cngmcs) .................................................... 761 figure 18-25: can global automatic block transmission control register (cngmabt) (1/2) ...... 762 figure 18-26: can global configuration register (cngmconf) ................................................. 764 figure 18-27: can global automatic block transmission delay register (cngmabtd) ............ 765 figure 18-28: can module n mask 1 registers l, h (cnmask1l, cn mask1h) ........ ............. .... 766 figure 18-29: can module n mask 2 registers l. h (cnmask2l, cnmask2h) ................ .......... 767 figure 18-30: can module n mask 3 registers (cnmask3l, cnmask3h)) ................................. 768 figure 18-31: can module n mask 4 registers (cnmask4l, cnmask4h)) ................................. 769 figure 18-32: can module n control register (cnctrl) (1/4) ...................................................... 770 figure 18-33: can module n last error code register (cnlec) .................................................. 774 figure 18-34: can module n information register (cninfo) ........................................................ 775 figure 18-35: can module n error counter register (cnerc) ..................................................... 776 figure 18-36: can module n interrupt enable register (cnie) (1/2) .............................................. 777 figure 18-37: can module n interrupt status register (cnints) (1/2)........................................... 779 figure 18-38: can module n bit rate prescaler register (cnbrp) ............................................... 781 figure 18-39: can module n bit rate register (cnbtr) (1/2) ....................................................... 782 figure 18-40: can module n last in-pointer register (cnlipt) .................................................... 784 figure 18-41: can module n receive history list register (cnrgpt) (1/2).................................. 785 figure 18-42: can module n last out-pointer register (cnlopt) ............................................... 787 figure 18-43: can module n transmit history list register (cntgpt) (1/2) ................................. 788 figure 18-44: can module time stamp register (cnts) (1/2) ...................................................... 790 figure 18-45: can message data byte register (1/2).................................................................... 792 figure 18-46: can message data length register m (cnmdlcm) .............................................. 794 figure 18-47: can message configuration register (cnmconfm) ............................................. 795 figure 18-48: can message id register m (cnmidlm, cnmidhm) ............................................. 797 figure 18-49: can message control register m (cnmctrlm) (1/3)............................................. 798 figure 18-50: example of bit setting/clearing operations .............................................................. 801 figure 18-51: 16-bit data during write operation .......................................................................... 802 figure 18-52: setting transmission request (trq) to transmit message buffer after redefining ......................................................................................................... 804 figure 18-53: transition to operation modes .................................................................................. 805 figure 18-54: receive history list.............................................................................................. ..... 808 figure 18-55: mask function identifier examples (1/2) ................................................................... 809 figure 18-56: message processing example .................................................................................. 813 figure 18-57: transmit history list............................................................................................. ..... 816 figure 18-58: can module terminal connection in receive-only mode........................................ 825 figure 18-59: can module terminal connection in self-test mode............................................... 827 figure 18-60: timing diagram of capture signal tsout ............................................................... 828 figure 18-61: initialization.................................................................................................... ............ 837 figure 18-62: re-initialization ................................................................................................. ......... 838 figure 18-63: message buffer initialization..................................................................................... .839 figure 18-64: message buffer redefinition ..................................................................................... 84 0 figure 18-65: message buffer redefinition during transmission .................................................... 841 figure 18-66: message transmit processing .................................................................................. 842 figure 18-67: message transmit processing (normal operation mode with abt) ......................... 843 figure 18-68: transmission via interrupt (using cnlopt register)................................................. 844 figure 18-69: transmit via interrupt (using cntgpt register)........................................................ 845 figure 18-70: transmission via software polling............................................................................. 846 figure 18-71: transmission abort processing (exc ept normal operation mode with abt)............ 847
25 user?s manual u16580ee2v0ud00 figure 18-72: transmission abort proc essing except for abt transmission (normal operation mode with abt) .......................................................................... 848 figure 18-73: abt transmission abort processing (normal operation mode with abt)................ 849 figure 18-74: abt transmission request abort processing (normal operation mode with abt) .......................................................................... 850 figure 18-75: reception via interrupt (using cnlipt register) ...................................................... 851 figure 18-76: reception via interrupt (using cnrgpt register).................................................... 852 figure 18-77: reception via softwa re polling.................................................................................. 85 3 figure 18-78: setting can sleep mode/stop mode......................................................................... 854 figure 18-79: clear can sleep/stop mode..................................................................................... 855 figure 18-80: bus-off recovery .................................................................................................. .... 856 figure 18-81: normal shutdown process ........................................................................................ 857 figure 18-82: forced shutdown process ........................................................................................ 857 figure 18-83: error handling .................................................................................................... ....... 858 figure 18-84: setting cpu standby (from can sleep mode) ......................................................... 859 figure 18-85: setting cpu standby (from can stop mode) ........................................................... 860 figure 19-1: random number register (rng) ............................................................................. 861 figure 20-1: port configuration ................................................................................................. .... 864 figure 20-2: port type 1 ........................................................................................................ ........ 866 figure 20-3: port type 1s ....................................................................................................... ...... 867 figure 20-4: port type 1e ....................................................................................................... ...... 868 figure 20-5: port type 2 ........................................................................................................ ........ 869 figure 20-6: port type 2a ....................................................................................................... ...... 870 figure 20-7: port type 2c ....................................................................................................... ...... 871 figure 20-8: port type 3 ........................................................................................................ ........ 872 figure 20-9: port type 4 ........................................................................................................ ........ 873 figure 20-10: port type 4c ...................................................................................................... ....... 874 figure 20-11: port type 5 ....................................................................................................... ......... 875 figure 20-12: port type 6 ....................................................................................................... ......... 876 figure 20-13: port type 7 ....................................................................................................... ......... 877 figure 20-14: port type 8 ....................................................................................................... ......... 878 figure 20-15: port type 9 ....................................................................................................... ......... 879 figure 20-16: port type 10 ...................................................................................................... ........ 880 figure 20-17: port type 11 ...................................................................................................... ........ 881 figure 20-18: port type 12 ...................................................................................................... ........ 882 figure 20-19: port type 13 ...................................................................................................... ........ 884 figure 20-20: port type 14 ...................................................................................................... ........ 886 figure 20-21: port type 15 ...................................................................................................... ........ 887 figure 20-22: port type 15a ..................................................................................................... ...... 888 figure 20-23: port register 0 (p0) ............................................................................................ ..... 893 figure 20-24: port register 1 (p1) ............................................................................................ ..... 895 figure 20-25: port mode register 1 (pm1) .................................................................................... 89 5 figure 20-26: port mode control register 1 (pmc1) (1/2) ............................................................. 896 figure 20-27: port register 2 (p2) ............................................................................................ ..... 899 figure 20-28: port mode register 2 (pm2) .................................................................................... 89 9 figure 20-29: port mode control register 2 (pmc2) (1/2) ............................................................. 900 figure 20-30: port register 3 (p3) ............................................................................................ ..... 903 figure 20-31: port mode register 3 (pm3) .................................................................................... 90 3 figure 20-32: port mode control register 3 (pmc3) (1/2) ............................................................. 904 figure 20-33: port register 4 (p4) ............................................................................................ ..... 907 figure 20-34: port mode register 4 (pm4) .................................................................................... 90 7 figure 20-35: port mode control register 4 (pmc4) ...................................................................... 908 figure 20-36: port register 5 (p5) ............................................................................................ ..... 910 figure 20-37: port mode register 5 (pm5) .................................................................................... 91 0 figure 20-38: port mode control register 5 (pmc5)) .................................................................... 911 figure 20-39: port emergency shut off control register 5 (pesc5) ............................................ 912 figure 20-40: port emergency shut off status register 5 (esost5)) .......................................... 913 figure 20-41: port register 6 (p6) ............................................................................................ ..... 915
26 user?s manual u16580ee2v0ud00 figure 20-42: port mode register 6 (pm6) .................................................................................... 91 5 figure 20-43: port mode control register 6 (pmc6) (1/2) ............................................................. 916 figure 20-44: port emergency shut off control register 6 (pesc6) ........... ............. ............. ....... 918 figure 20-45: port emergency shut off status register 6 (esost6)) .......................................... 919 figure 20-46: port register 7 (p7) ............................................................................................ ..... 921 figure 20-47: port mode register 7 (pm7) .................................................................................... 92 1 figure 20-48: port mode control register 7 (pmc7) (1/2) ............................................................. 922 figure 20-49: port register 8 (p8) ............................................................................................ ..... 925 figure 20-50: port mode register 8 (pm8) .................................................................................... 92 5 figure 20-51: port mode control register 8 (pmc8) (1/2) ............................................................. 926 figure 20-52: port register 9 (p9) ............................................................................................ ..... 929 figure 20-53: port mode register 9 (pm9) .................................................................................... 92 9 figure 20-54: port mode control register 9 (pmc9) (1/2) ............................................................. 930 figure 20-55: port register 10 (p10) .......................................................................................... ... 933 figure 20-56: port mode register 10 (pm10) ................................................................................ 933 figure 20-57: port mode control register 10 (pmc10) .................................................................. 934 figure 20-58: port register al(pal) ......................................................................................... .. 936 figure 20-59: port mode register al(pmal) .............................................................................. 937 figure 20-60: port mode control register al (pmcal) .............................................................. 938 figure 20-61: port register ah (pah) .......................................................................................... .939 figure 20-62: port mode register ah (pmah) ............................................................................... 940 figure 20-63: port mode control register ah (pmcah) ............................................................... 940 figure 20-64: port register dl(pdl) ......................................................................................... .. 942 figure 20-65: port mode register dl(pmdl) .............................................................................. 943 figure 20-66: port mode control register dl (pmcdl) ............................................................. 944 figure 20-67: port register dh(pdh) ......................................................................................... 946 figure 20-68: port mode register dh(pmdh) ............................................................................ 947 figure 20-69: port mode control register dh (pmcdh) ............................................................ 948 figure 20-70: port register cs (pcs) .......................................................................................... .949 figure 20-71: port mode register cs (pmcs) ............................................................................... 950 figure 20-72: port mode control register cs (pmccs) ............................................................... 950 figure 20-73: port register ct (pct) .......................................................................................... .951 figure 20-74: port mode register ct (pmct) ............................................................................... 952 figure 20-75: port mode control register ct (pmcct) ............................................................... 952 figure 20-76: port register cm (pcm) .......................................................................................... 953 figure 20-77: port mode register cm (pmcm) .............................................................................. 954 figure 20-78: port mode control register cm (pmccm) .............................................................. 955 figure 20-79: port register cd (pcd) .......................................................................................... 956 figure 20-80: port mode register cd (pmcd) .............................................................................. 957 figure 20-81: port mode control register cd (pmccd) .............................................................. 958 figure 20-82: noise elimination control register (nrc) (1/2) ....................................................... 961 figure 21-1: reset timing ....................................................................................................... ...... 964 figure 22-1: internal ram parity error status register (ramerr) ............................................ 966 figure 22-2: internal ram parity error address register (rampadd) ...................................... 967 figure 23-1: connecting n-wire type emulator (ie-v850e1-cd-nw (n-wire card)) .................. 971 figure 23-2: pin configuration of emulator connector (on target system side) .......................... 972 figure 23-3: example of recommended emulator connection of v850e/ph2............................. 974 figure 24-1: flash memory mapping ............................................................................................. 97 8 figure 24-2: environment required for writing programs to flash memory ................................. 982 figure 24-3: communication with dedicated flash programmer (uartc0) ................................ 983 figure 24-4: communication with dedicated flash programmer (csib0) .................................... 983 figure 24-5: communication with dedicated flash programmer (csib0 + hs) ........................... 984 figure 24-6: procedure for manipulating flash memory................................................................ 986 figure 24-7: selection of communication mode............................................................................ 987 figure 24-8: communication commands ...................................................................................... 988 figure 24-9: flmd0 pin connection example .............................................................................. 989 figure 24-10: flmd1 pin connection example .............................................................................. 990 figure 24-11: conflict of signals (serial interface input pin) ........................................................... 991
27 user?s manual u16580ee2v0ud00 figure 24-12: malfunction of other device ...................................................................................... 9 92 figure 24-13: conflict of signals (reset pin) ................................................................................ 993 figure 24-14: concept of self programming ................................................................................... 994 figure 24-15: rewriting entire memory area (boot swap).............................................................. 995 figure 25-1: oscillator recommendat ions .................................................................................... 999 figure 25-2: ac test input/output waveform ............................................................................. 1001 figure 25-3: ac test load condition .......................................................................................... 100 1 figure 25-4: external asynchronous memory access read timing............................................ 1003 figure 25-5: external asynchronous memory access write timing............................................ 1005 figure 25-6: reset timing ....................................................................................................... .... 1006 figure 25-7: interrupt timing ................................................................................................... .... 1007 figure 25-8: timer p characteristics ........................................................................................... 1 008 figure 25-9: timer r characteristics ........................................................................................... 1 009 figure 25-10: timer t characteristics ........................................................................................... 1010 figure 25-11: csib timing in master mode (ckp, dap bits = 00b or 11b).................................. 1012 figure 25-12: csib timing in master mode (ckp, dap bits = 01b or 10b).................................. 1012 figure 25-13: csib timing in slave mode (ckp, dap bits = 00b or 11b).................................... 1013 figure 25-14: csib timing in slave mode (ckp, dap bits = 01b or 10b).................................... 1013 figure 25-15: csi3 timing in master mode (ckp, dap bits = 00b or 11b) .................................. 1015 figure 25-16: csi3 timing in master mode (ckp, dap bits = 01b or 10b) .................................. 1015 figure 25-17: csi3 timing in slave mode (ckp, dap bits = 00b or 11b) .................................... 1016 figure 25-18: csi3 timing in slave mode (ckp, dap bits = 01b or 10b) .................................... 1016 figure 25-19: csi3 chip select timing (master mo de only) (csit = 0, cswe = 0, csmd = 0) .. 1017 figure 25-20: csi3 chip select timing (master mo de only) (csit = 0, cswe = 1, csmd = 0) .. 1017 figure 25-21: csi3 chip select timing (master mo de only) (csit = 0, cswe = 1, csmd = 1) .. 1018 figure 25-22: csi3 chip select timing (master mo de only) (csit = 1, cswe = 0, csmd = 0) .. 1018 figure 25-23: csi3 chip select timing (master mo de only) (csit = 1, cswe = 1, csmd = 0) .. 1019 figure 25-24: csi3 chip select timing (master mo de only) (csit = 1, cswe = 1, csmd = 1) .. 1019 figure 25-25: serial write operation characteristics .................................................................... 1022 figure 26-1: 208-pin plastic qfp (fine pitch) (28 x 28).............................................................. 1023 figure 26-2: 256-pin plastic bga (fine pitch) (21 x 21) ............................................................. 1024
28 user?s manual u16580ee2v0ud00
29 user?s manual u16580ee2v0ud00 list of tables table 1-1: 256-pin plastic bga .................................................................................................. ..... 38 table 2-1: port pins ............................................................................................................ ............. 45 table 2-2: non-port pins ........................................................................................................ ......... 50 table 2-3: pin status in reset and standby mode.......................................................................... 55 table 2-4: i/o circuit types.................................................................................................... ......... 70 table 2-5: noise suppression timing............................................................................................. .74 table 3-1: program registers.................................................................................................... ...... 79 table 3-2: system register numbers.............................................................................................. 80 table 3-3: saturated operation results ......................................................................................... 84 table 3-4: floating point arithmetic unit registers ......................................................................... 86 table 3-5: peripheral i/o registers ............................................................................................. .... 95 table 3-6: programmable peripheral i/o registers....................................................................... 111 table 4-1: number of bus access clocks ..................................................................................... 139 table 4-2: bus priority order ................................................................................................... ...... 167 table 6-1: timer tmr address mapping for dma transfer .......................................................... 192 table 6-2: dma configuration of serial data reception ............................................................... 196 table 6-3: dma configuration of serial data transmission .......................................................... 200 table 6-4: relations between dma trigger factors and dma completion interrupts.................. 205 table 7-1: interrupt/exception source list .................................................................................... 20 7 table 7-2: addresses and bits of interrupt control registers ....................................................... 225 table 8-1: operation status in halt mode................................................................................... 245 table 8-2: operation after releasing halt mode by interrupt request signal ........................... 246 table 9-1: configuration of tmp0 to tmp8 ................................................................................... 248 table 10-1: timer r configuration ............................................................................................... ... 300 table 10-2: tmrn count clock and count delay ........................................................................... 311 table 10-3: list of timer outputs in each mode (1/2)..................................................................... 344 table 10-4: list of interrupts in each mode (1/2) ............................................................................ 347 table 10-5: list of a/d conversion triggers, peak interrupts and valley interrupts in each mode 349 table 10-1: positive phase operation condition list ...................................................................... 417 table 10-2: negative phase operation condition list..................................................................... 417 table 10-3: compare register value after trough reload (trndtc0 < trndtc1) ..................... 418 table 10-4: compare register value after trough reload............................................................. 421 table 10-5: compare register value after trough reload (trndtc1 < trndtc0) ..................... 423 table 10-6: compare register value after trough reload............................................................. 427 table 11-1: timer t configuration............................................................................................... .... 444 table 11-2: list of timer t registers ........................................................................................... ... 445 table 11-3: capture/compare functions in each mode ................................................................. 447 table 11-4: capture/compare functions in each mode ................................................................. 449 table 11-5: tmtn count clock and count delay............................................................................ 452 table 11-6: counter clear operation ............................................................................................. .467 table 11-7: capture/compare rewrite methods in each mode ...................................................... 472 table 12-1: timer enc10 configuration list................................................................................... 521 table 12-2: timer enc10 (tmenc10) clear conditions ................................................................ 524 table 12-3: capture trigger signal to 16-bit capture register....................................................... 540 table 12-4: list of count operations in udc mode ........................................................................ 542 table 13-1: afo configuration .................................................................................................. ..... 553 table 14-1: assignment of a/d conversion result registers to analog input pins ........................ 566 table 14-2: relationship between operation mode and trigger mode........................................... 570 table 14-3: correspondence between anal og input pins and adcrnm register (a/d trigger select: 1 buffer) ....................................................................................... 575 table 14-4: correspondence between anal og input pins and adcrnm register (a/d trigger select: 4 buffers) ..................................................................................... 576 table 14-5: correspondence between anal og input pins and adcrnm register (a/d trigger scan)........................................................................................................ 578
30 user?s manual u16580ee2v0ud00 table 14-6: correspondence between anal og input pins and adcrnm register (1-buffer mode (timer trigger select: 1 buffer)).......................................................... 581 table 14-7: correspondence between anal og input pins and adcrnm register (4-buffer mode (timer trigger select: 4 buffers)) ........................................................ 582 table 14-8: correspondence between anal og input pins and adcrnm register (scan mode (timer trigger scan))............................................................................... 584 table 14-9: correspondence between anal og input pins and adcrnm register (external trigger select: 1 buffer) ................................................................................ 586 table 14-10: correspondence between a nalog input pins and adcrnm register (external trigger select: 4 buffers)) ............................................................................. 588 table 14-11: correspondence between a nalog input pins and adcrnm register (external trigger scan) ................................................................................................ 590 table 15-1: relation between uartcn register settings and data format ................................. 603 table 15-2: default priorities of uartcn interrupts....................................................................... 609 table 15-3: reception error causes ............................................................................................. .620 table 15-4: baud rate generator setting data............................................................................... 625 table 15-5: maximum/minimum allowable baud rate error ........................................................... 627 table 16-1: csibn configuration................................................................................................. .... 629 table 17-1: operation modes ..................................................................................................... ..... 679 table 17-2: conditions under which data can be transferred in slave mode.............................. 686 table 17-3: default output level of sck3n pin ............................................................................. 696 table 17-4: default output level of so3n pin ................................................................................ 696 table 17-5: default output level of scs3n0 to scs3n3 pins ........................................................ 697 table 18-1: can channel offsets ................................................................................................. .. 723 table 18-2: overview of functions ............................................................................................... ... 724 table 18-3: frame types ......................................................................................................... ....... 727 table 18-4: rtr frame settings.................................................................................................. ... 731 table 18-5: frame format setting (ide bit) and number of identifier (id) bits .............................. 731 table 18-6: data length setting................................................................................................. ..... 732 table 18-7: operation in error status........................................................................................... ... 736 table 18-8: definition error frame fields...................................................................................... .736 table 18-9: definition of overload frame fields ............................................................................. 737 table 18-10: determining bus priority........................................................................................... .... 738 table 18-11: bit stuffing ....................................................................................................... ............. 738 table 18-12: error types........................................................................................................ ........... 739 table 18-13: output timing of error frame....................................................................................... 740 table 18-14: types of error states.............................................................................................. ...... 741 table 18-15: error counter...................................................................................................... .......... 742 table 18-16: segment setting .................................................................................................... ....... 745 table 18-17: configuration of data bit time defined by can specification ..................................... 746 table 18-18: list of can controller registers................................................................................... 750 table 18-19: can global register access types............................................................................. 752 table 18-20: can module register access types ........................................................................... 753 table 18-21: message buffer access types ..................................................................................... 754 table 18-22: bit configuration of can global registers................................................................... 755 table 18-23: bit configuration of can module registers ................................................................. 756 table 18-24: bit configuration of message buffer registers............................................................. 758 table 18-25: message reception.................................................................................................. .... 806 table 18-26: message transmission............................................................................................... .. 814 table 18-27: transmission abort................................................................................................. ...... 819 table 18-28: list of can module interrupt sources .......................................................................... 824 table 18-29: settable bit rate combinations.................................................................................... 8 30 table 18-30: representative exam ples of baud rate settings (f canmod = 8 mhz) ......................... 833 table 18-31: representative exam ples of baud rate settings (f canmod = 16 mhz) ....................... 835 table 20-1: port type and function overview ................................................................................ 865 table 20-2: peripheral registers of i/o ports................................................................................. 8 89 table 20-3: peripheral registers of valid edge control ................................................................. 892 table 20-4: alternate function pins and port types of port 0 ........................................................ 893
31 user?s manual u16580ee2v0ud00 table 20-5: alternate function pins and port types of port 1 ........................................................ 894 table 20-6: alternate function pins and port types of port 2 ........................................................ 898 table 20-7: alternate function pins and port types of port 3 ........................................................ 902 table 20-8: alternate function pins and port types of port 4 ........................................................ 906 table 20-9: alternate function pins and port types of port 5 ........................................................ 909 table 20-10: alternate function pins and port types of port 6 ........................................................ 914 table 20-11: alternate function pins and port types of port 7 ........................................................ 920 table 20-12: alternate function pins and port types of port 8 ........................................................ 924 table 20-13: alternate function pins and port types of port 9 ........................................................ 928 table 20-14: alternate function pins and port types of port 10 ...................................................... 932 table 20-15: alternate function pins and port types of port al ...................................................... 935 table 20-16: alternate function pins and port types of port ah ..................................................... 939 table 20-17: alternate function pins and port types of port dl...................................................... 941 table 20-18: alternate function pins and port types of port dh ..................................................... 945 table 20-19: alternate function pins and port types of port cs ..................................................... 949 table 20-20: alternate function pins and port types of port ct...................................................... 951 table 20-21: alternate function pins and port types of port cm..................................................... 953 table 20-22: alternate function pins and port types of port cd ..................................................... 956 table 20-23: noise elimination.................................................................................................. ........ 959 table 23-1: pin functions of connector for ie-v850e1-cd-nw (on target system side) ............. 973 table 24-1: rewrite method ...................................................................................................... ...... 979 table 24-2: basic functions ..................................................................................................... ....... 980 table 24-3: protection functions................................................................................................ ..... 981 table 24-4: signal connections of dedicated flash programmer (pg-fp4) .................................. 985 table 24-5: communication commands ......................................................................................... 988 table 24-6: relationship between flmd0 and flmd1 pins and operation mode when reset is released............................................................................................... 990 table 24-7: pins used by serial interfaces ..................................................................................... 9 91 table 25-1: absolute maximum ratings.......................................................................................... 99 7 table 25-2: capacitance ........................................................................................................ ......... 998 table 25-3: operating conditions ............................................................................................... .... 998 table 25-4: oscillator characteristics ......................................................................................... .... 999 table 25-5: dc characteristics.................................................................................................. .... 1000 table 25-6: external asynchronous memory access read timing .............................................. 1002 table 25-7: external asynchronous memory access write timing .............................................. 1004 table 25-8: reset timing ....................................................................................................... ...... 1006 table 25-9: interrupt timing ................................................................................................... ...... 1007 table 25-10: timer p characteristics ........................................................................................... .. 1008 table 25-11: timer r characteristics ........................................................................................... .. 1009 table 25-12: timer t characteristics ........................................................................................... .. 1010 table 25-13: csib characteristics (master mode) .......................................................................... 1011 table 25-14: csib characteristics (slave mode) ............................................................................ 1011 table 25-15: csi3 characteristics (master mode) .......................................................................... 1014 table 25-16: csi3 characteristics (slave mode) ............................................................................ 1014 table 25-17: a/d converter characteristics ................................................................................... 10 20 table 25-18: flash memory basic characteristics .......................................................................... 1021 table 25-19: flash memory programming characteristics ............................................................. 1021 table 25-20: serial write operation characteristics ....................................................................... 1022 table 27-1: soldering conditions ................................................................................................ .. 1025
32 user?s manual u16580ee2v0ud00
33 user?s manual u16580ee2v0ud00 chapter 1 introduction the v850e/ph2 (phoenix-f note ) is a product of the nec electronics single-chip microcontrollers ?v850 series??. this chapter gives a short outline of the v850e/ph2 microcontroller. 1.1 outline the v850e/ph2 is a 32-bit single-chip microcontroller that realizes high-precision inverter control of a motor due to high-speed operation. it uses the v850e1 cpu (nu85efc) of the v850 series including single-precision floating point unit, and has on-chip rom, ram, bus interface, dma controller, a real- time pulse unit including 3-phase pwm timer for inve rter control, various serial interfaces including afcan, and peripheral facilities such as a/d conv erters, as well as an on-chip debug interface. (1) v850e1 cpu the v850e1 cpu (nu85efc) supports a risc instruction set that enhances the performance of the v850 cpu, which is the cpu core integrated in the v850 series, and has added instructions supporting high-level languages, such as c-language switch statement processing, table look-up branching, stack frame creation/deletion, and data conversion. this enhances the performance of both data processing and control. it is possible to use the software resources of the v850 cpu integrated system since the instruction codes of the v850e1 are upwardly compatible at the object code level with those of the v850 cpu. in addition, the v850e1 cpu (nu85efc) incorporates a single-precision floa ting point unit, which supports high speed floating point arithmetic operations. (2) external memory interface function the v850e/ph2 microcontroller features n on-chip external memory interface including separately configured address (22 bits) and data (32 bits) buses. sram and rom can be connected. (3) on-chip flash memory the v850e/ph2 microcontroller has a quickly accessible flash memory on-chip, that can shorten system development time since it is possible to rewrite a program with the v850e/ph2 microcontroller mounted in an ap plication system. moreov er, it can greatly im prove maintain ability after system ships. (4) a full range of development environment products a development environment system that includes an optimized c compiler, debugger, in-circuit emulator, simulator, system performance analyser, and other elements is also available. note: phoenix-f is the european name of the v850e/ph2 microcontroller.
34 chapter 1 introduction user?s manual u16580ee2v0ud00 1.2 device features ? number of instructions: 96 ? instruction execution time: 15.625 ns (@ = 64 mhz) ? general-purpose registers: 32 bits 32 ? instruction set: v850e1 cpu (nu85efc) (compatible with v850 plus additional powerful instructions for reducing code and increasing execution speed) single-precision floating point arithmetic operation signed multiplication (16 bits 16 bits 32 bits or 32 bits 32 bits 64 bits): 1 to 2 clocks saturated operation instructions (with overflow/underflow detection function) 32-bit shift instructions: 1 clock bit manipulation instructions load/store instructions with long/short format signed load instructions ? memory space: 64 mb linear address space (common program/data) chip select output function: 4 spaces memory block division function: 2, 4, or 8 mb/block programmable wait function idle state insertion function ? external bus interface: 32-bit data bus (address/data separated) 22-bit address bus 4 programmable chip select areas 32-/16-/8-bit bus sizing function external wait function ? internal memory: flash rom: 512 kb ram: 32 kb ? interrupts/exceptions: external interrupts: 14 (including nmi) internal interrupts: 85 sources exceptions: 1 source 8 programmable interrupt priority levels ? memory access controller: sram controller ? dma controller: 8 channels transfer mode: single transfer transfer units: 8 bits or 16 bits (depending on peripheral) maximum transfer count: 256 (2 8 ) transfer target: internal ram ? i/o transfer request: on-chip peripheral i/o dma transfer termination interrupt ? i/o lines: input ports: 5 i/o ports: 137
35 chapter 1 introduction user?s manual u16580ee2v0ud00 ? timer: 16-bit timer for 3-phase pwm inverter control: 2 channels 16-bit up/down counter for 4-quadrant encoding: 1 channel 16-bit general purpose timers: 9 channels 16-bit general purpose time rs with encoding capability: 2 channels ? serial interfaces: asynchronous serial interface (uartc): 2 channels clocked serial interface (csib): 2 channels queued clocked serial interface (csi3): 2 channels fcan interface (afcan): 2 channels ? a/d converters: 10-bit resolution 2 10 channels ? random number generator: automatic seed generation fips/maurer test passing ? clock generator: 16 mhz clock oscillator 4 fold pll synthesizer for internal system clock ? power save modes: halt mode ? auxiliary frequency output: pr ogrammable by user software ? supply voltage: 1.5 v (internal power supply, clock generator) 3.3 v (external i/o pins, a/d converter) ? package 208-pin plastic lqfp (fine pitch) (28 28) 256-pin plastic bga (21 21) ? cmos technology 1.3 applications the v850e/ph2 microcontrolle r is ideally suited for au tomotive applications, like electrical power steering and electric car control. it is also an excellent choice for other applications where a combination of general-purpose inverter control functions and can network support is required. 1.4 ordering information part number package pd70f3187gd-64-lml 208-pin plastic lqfp (fine pitch) (28 28) pd70f3187gd(a1)-64-lml 208-pin plastic lqfp (fine pitch) (28 28) pd70f3187gd(a2)-64-lml 208-pin plastic lqfp (fine pitch) (28 28) pd70f3187f1(a2)-64-jn4 256-pin plastic bga (21 21)
36 chapter 1 introduction user?s manual u16580ee2v0ud00 1.5 pin configuration (top view) ? 208-pin plastic lqfp (fine pitch) (28 28) pd70f3187gd-64-lml pd70f3187gd(a1)-64-lml pd70f3187gd(a2)-64-lml figure 1-1: pin configuration 208-pin plastic lqfp 66 p50/tor00 13 ani07 9 ani03 61 p100/tclr0/ticc00/top81 188 pdh7/d23 141 pa l9/a9 97 v ss32 112 p92/sck3 1 63 p102/tiud0/to0 29 av ss1 60 p75/tecrt1/afo 187 pdh6/d22 42 p13/tip11/tevtp0/t op11 140 pal8/a8 71 v ss31 113 p91/so31 59 p74/tit11/tevtt0/tot11/tenct11 41 v ss30 186 pdh5/d21 39 p12/tip10/ttrgp0/t op10 139 pal7/a7 114 p90/si31 116 p84/scs301/intp7 58 p73/tit10/ttrgt0/tot10/tenct10 138 pal6/a6 38 p11/tip01/ttrgp1/t op01 185 pdh4/d20 88 ddo 118 p86/scs303/ ssb0 17 av dd 170 v dd14 115 p83/scs300/intp6 57 p72/tecrt0/intp12 184 pdh3/d19 37 p10/tip00/tevtp1/t op00 137 pal5/a5 87 ddi 131 pal2/a2 117 p85/scs302/intp8 84 dck 194 v dd15 109 p82/sck3 0 56 p71/tit01/ttrgt1/tot01/tenct01 183 pdh2/d18 34 p04/intp3/adtrg1 136 pal4/a4 86 dms 19 ani19 23 ani15 27 ani11 130 pal1/a1 135 mode0/flmd0 133 v dd13 110 p81/so30 204 pcm7 35 v dd10 55 p70/tit00/tevtt1/tot00/tenct00 33 p03/intp2/adtrg0 182 pdh1/d17 132 pal3/a3 6 ani00 85 drst 52 p25/tip61/ttrgp7/t op61 14 ani08 10 ani04 129 pal0/a0 199 v dd37 177 pdl14/d14 89 v dd12 4 mode1/flmd1 111 p80/si30 203 pcm6 54 p27/tip71/tevtp6/top71 181 pdh0/d16 32 p02/intp1/eso1 51 p24/tip60/tevtp7/t op60 176 pdl13/d13 198 pdh15/d31 3 mode2 64 v dd11 101 p37/fctxd1 201 pcm1 53 p26/tip70/ttrgp6/top70 31 p01/intp0/eso0 178 pdl15/d15 205 pct4/rd 50 p23/tip51/tevtp4/t op51 175 pdl12/d12 197 pdh14/d30 83 reset 100 p36/fcrxd1 2 pcm0/wait 1 pcd5/ben3 30 p00/nmi 49 p22/tip50/ttrgp4/t op50 174 pdl11/d11 196 pdh13/d29 99 p35/fctxd0 202 pct5/wr 104 p32/rxdc1/intp5 208 pcd4/ben2 48 p21/tip41/ttrgp5/t op41 193 pdh12/d28 173 pdl10/d10 98 p34/fcrxd0 103 p31/txdc0 207 pcd3/ben1 79 cv ss 5 av ss0 47 p20/tip40/tevtp5/t op40 172 pdl9/d9 192 pdh11/d27 105 p33/txdc1 26 ani12 22 ani16 102 p30/rxdc0/intp4 206 pcd2/ben0 46 p17/tip31/tevtp2/t op31 171 pdl8/d8 191 pdh10/d26 15 ani09 11 ani05 7 ani01 95 p67/tor17/trtevt1 158 pcs4/cs4 144 v dd34 45 p16/tip30/ttrgp2/t op30 190 pdh9/d25 168 pdl7/d7 195 v ss15 18 av ref1 165 pdl4/d4 179 v dd36 94 p66/tor16 147 pcs3/cs3 119 v dd33 44 p15/tip21/ttrgp3/t op21 167 pdl6/d6 134 v ss13 162 pdl3/d3 163 v dd35 93 p65/tor15 169 v ss14 146 pcs1/cs1 43 p14/tip20/tevtp3/t op20 96 v dd32 90 v ss12 166 pdl5/d5 161 pdl2/d2 92 p64/tor14/tir13 128 pcs0/cs0 70 v dd31 157 pah5/a21 65 v ss11 160 pdl1/d1 81 x1 91 p63/tor13/tir12 40 v dd30 76 p60/tor10/ttrgr1 156 pah4/a20 36 v ss10 159 pdl0/d0 78 p62/tor12/tir11 21 ani17 25 ani13 75 p57/tor07 155 pah3/a19 80 x2 106 p45/sckb1 77 p61/tor11/tir10 8 ani02 12 ani06 74 p56/tor06 154 pah2/a18 107 p44/sob1 73 p55/tor05 153 pah1/a17 108 p43/sib1 125 p40/sib0 72 p54/tor04 152 pah0/a16 180 v ss36 127 p42/sckb0 124 p96/scs313/ ssb1 69 p53/tor03 151 pa l15/a15 164 v ss35 126 p41/sob0 148 pal12/a12 82 cv dd 200 v ss37 123 p95/scs312/intp1 1 68 p52/tor02 150 pal14/a14 143 pal11/a11 145 v ss34 16 av ref0 122 p94/scs311/intp10 67 p51/tor01 149 pal13/a13 28 ani10 24 ani14 20 ani18 62 p101/tcud0/ticc01 189 pdh8/d24 142 pal10/a10 120 v ss33 121 p93/scs310/intp9
37 chapter 1 introduction user?s manual u16580ee2v0ud00 ? 256-pin plastic bga (21 21) pd70f3187f1(a2)-jn4 figure 1-2: pin configuration 256-pin plastic bga (21 21) top view bottom view index mark index mark abcdefghjklmnprtuvwy ywvutrpnmlkjhgfedcba 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
38 chapter 1 introduction user?s manual u16580ee2v0ud00 table 1-1: 256-pin plastic bga (1/2) pin no pin name pin no pin name pin no pin name pin no pin name a1 nc b1 nc c1 av ss0 d1 av ss0 a2 nc b2 nc c2 mode1 d2 av ss0 a3 pct4/rd b3 pcd5/ben3 c3 mode2 d3 av ss0 a4 pct5/wr b4 pcd2/ben0 c4 pcd4/ben2 d4 pcm0/wait a5 pdh15/d31 b5 pcm6 c5 pcm7 d5 pcd3/ben1 a6 pdh13/d29 b6 pcm1 c6 v ss37 d6 v dd37 a7 pdh11/d27 b7 pdh14/d30 c7 v ss37 d7 v dd37 a8 pdh9/d25 b8 pdh12/d28 c8 v ss15 d8 v dd15 a9 pdh8/d24 b9 pdh10/d26 c9 v ss15 d9 v dd15 a10 pdh6/d22 b10 pdh7/d23 c10 pdh4/d20 d10 pdh2/d18 a11 pdh3/d19 b11 pdh5/d21 c11 v ss36 d11 v dd36 a12 pdh0/d16 b12 pdh1/d17 c12 v ss36 d12 v dd36 a13 pdl15/d15 b13 pdl13/d13 c13 pdl11/d11 d13 pdl10/d10 a14 pdl14/d14 b14 pdl12/d12 c14 v ss14 d14 v dd14 a15 pdl9/d9 b15 pdl8/d8 c15 pdl7/d7 d15 pdl6/d6 a16 pdl5/d5 b16 pdl4/d4 c16 v ss35 d16 v dd35 a17 pdl1/d1 b17 pdl3/d3 c17 v ss35 d17 v dd35 a18 pdl0/d0 b18 pcs4/cs4 c18 pdl2/d2 d18 pah4/a20 a19 nc b19 nc c19 pah5/a21 d19 pah3/a19 a20 nc b20 nc c20 nc d20 pal14/a14 e1 ani00 f1 ani03 g1 ani07 h1 ani18 e2 ani02 f2 ani06 g2 ani09 h2 ani19 e3 ani01 f3 ani05 g3 ani08 h3 av dd e4 av ss0 f4 ani04 g4 av ref0 h4 av ref1 e17 pah0/a16 f17 pal12/a12 g17 v dd34 h17 v dd34 e18 pah2/a18 f18 pal15/a15 g18 v ss34 h18 v ss34 e19 pah1/a17 f19 pal1 3/a13 g19 pcs1/cs1 h19 pal10/a10 e20 pcs3/cs3 f20 pal11/a11 g20 pal9/a9 h20 pal6/a6 j1 ani17 k1 ani13 l1 av ss1 m1 p01/intp0/eso0 j2 ani14 k2 ani10 l2 av ss1 m2 p00/nmi j3 ani15 k3 ani11 l3 av ss1 m3 v ss10 j4 ani16 k4 ani12 l4 av ss1 m4 v dd10 j17 pal5/a5 k17 v dd13 l17 v dd13 m17 p95/scs312/intp11 j18 pal8/a8 k18 v ss13 l18 v ss13 m18 pal0/a0 j19 pal7/a7 k19 pal4/a4 l19 pal3/a3 m19 pcs0/cs0 j20 mode0 k20 pal2/a2 l2 0 pal1/a1 m20 p42/sckb0
39 chapter 1 introduction user?s manual u16580ee2v0ud00 n1 p02/intp1/eso1 p1 p04/intp3/ adtrg1 r1 p11/tip01/ ttrgp1/top01 t1 p13/tip11/tevtp0/ top11 n2 p03/intp2/ adtrg0 p2 p10/tip00/ tevtp1/top00 r2 p12/tip10/ ttrgp0/top10 t2 p14/tip20/tevtp3/ top20 n3 v ss10 p3 v ss30 r3 v ss30 t3 p16/tip30/ttrgp2/ top30 n4 v dd10 p4 v dd30 r4 v dd30 t4 p21/tip41/ttrgp5/ top41 n17 v dd33 p17 v dd33 r17 p83/scs300/intp6 t17 p80/si30 n18 v ss33 p18 v ss33 r18 p86/scs303/ssb0 t18 p84/scs301/intp7 n19 p41/sob0 p19 p96/scs313/ssb1 r19 p93/scs310/intp9 t19 p90/si31 n20 p40/sib0 p20 p94/scs311/ intp10 r20 p85/scs302/intp8 t20 p91/so31 u1 p15/tip21/ ttrgp3/top21 v1 p20/tip40/ tevtp5/top40 w1 nc y1 nc u2 p17/tip31/ tevtp2/top31 v2 p23/tip51/ tevtp4/top51 w2 p26 y2 nc u3 p22/tip50/ ttrgp4/top50 v3 p24/tip60/ tevtp7/top60 w3 p27/tip71/ tevtp6/top71 y3 p72/tecrt0/ intp12 u4 p25/tip61/ ttrgp7/top61 v4 p70/tit00/tevtt1/ tot00/tenct00 w4 p73/tit10/ttrgt0/ tot10/tenct10 y4 p100/tclr1/ ticc10/top81 u5 p71/tit01/ttrgt1/ tot01/tenct01 v5 p74/tit11/tevtt0/ tot11/tenct11 w5 p101/tcud1/ ticc11 y5 p50/tor00 u6 p75 v6 p102/tiud1/to1 w6 p51/tor01 y6 p52/tor02 u7 v dd11 v7 v ss11 w7 p53/tor03 y7 p54/tor04 u8 v dd31 v8 v ss31 w8 p55/tor05 y8 p56/tor06 u9 p62/tor12/tir11 v9 p61/tor11/tir1 0 w9 p57/tor07 y9 p60/tor10/ttrgr1 u10 v ss31 v10 v ss31 w10 v ss31 y10 v ss31 u11 dck v11 reset w11 x2 y11 cv ss u12 v dd12 v12 v ss12 w12 x1 y12 cv dd u13 v dd12 v13 v ss12 w13 dms y13 drst u14 v dd32 v14 v ss32 w14 ddo y14 ddi u15 v dd32 v15 v ss32 w15 p65/tor15 y15 p63/tor13/tir12 u16 p32/rxdc1/intp5 v16 p67/tor17/ tevtr1 w16 p66/tor16 y16 p64/tor14/tir13 u17 p81/so30 v17 p31/txdc0 w17 p34/fcrxd0 y17 p35/fctxd0 u18 p82/sck30 v18 p30/rxdc0/intp4 w18 p36/fcrxd1 y18 p37/fctxd1 u19 p44/sob1 v19 p43/sib1 w19 p33/txdc1 y19 nc u20 p92/sck31 v20 p45/sckb1 w20 nc y20 nc table 1-1: 256-pin plastic bga (2/2) pin no pin name pin no pin name pin no pin name pin no pin name
40 chapter 1 introduction user?s manual u16580ee2v0ud00 pin identification a0 to a21: address bus adtrg0, adtrg1: a/d trigger input afo: auxiliary frequency output ani00 to ani09, ani10 to ani19: analog input av dd : analog power supply av ref0 , av ref1 : analog reference voltage av ss0 , av ss1 : analog ground ben0 to ben3 : byte enable cs0 , cs1 , cs3 , cs4 : chip select cv dd : power supply for oscillator cv ss : oscillator ground d0 to d31: data bus dck: debug clock input ddi: debug data input ddo: debug data output dms: debug mode select drst : debug reset eso0, eso1: emer gency shut-off fcrxd0, fcrxd1: fcan receive data input fctxd0, fctxd1: fcan transmit data output intp0 to intp12: external interrupt request mode0 to mode2: mode nmi: non-maskable interrupt request nc: not connected p00 to p04: port 0 p10 to p17: port 1 p20 to p27: port 2 p30 to p37: port 3 p40 to p45: port 4 p50 to p57: port 5 p60 to p67: port 6 p70 to p75: port 7 p80 to p86: port 8 p90 to p96: port 9 p100 to p102: port 10 pal0 to pal15: port al pah0 to pah5: port ah pcd2 to pcd5: port cd pcm0, pcm1, pcm6, pcm7: port cm pcs0, pcs1, pcs3, pcs4: port cs pct4, pct5: port ct pdl0 to pdl15: port dh pdh0 to pdh15: port dl rd : read strobe reset : reset rxdc0, rxdc1: receive data input sck30 , sck31 , sckb0 , sckb1 : serial clock scs300 to scs303, scs310 to scs313: serial chip select si30, si31, sib0, sib1: serial data input so30, so31, sob0, sob1: serial data output ssb0, ssb1: serial slave select input tclr1: timer clear tcud1: timer control pulse input tecrt0, tecrt1: timer external clear tenct00, tenct01, tenct10, tenct11: timer encoder input tevtp0 to tevtp7, tevtr1, tevtt0, tevtt1: timer event input ticc10, ticc11 tip00, tip01, tip10, tip11, tip20, tip21, tip30, tip31, tip40, tip41, tip50, tip51, tip60, tip61, tip70, tip71, tir10 to tir13, tit00, tit01, tit10, tit11: timer input tiud1: timer count pulse input to1, top00, top01, top10, top11, top20, top21, top30, top31, top40, top41, top50, top51, top60, top61, top70, top71, top81, tor00 to tor07, tor10 to tor17, tot00, tot01, tot10, tot11: timer output ttrgp0 to ttrgp7, ttrgr1, ttrgt0, ttrgt1: timer trigger input txdc0, txdc1: transmit data output v dd10 to v dd15 : power supply for cpu v dd30 to v dd37 : i/o buffers power supply v ss10 to v ss15 : cpu ground v ss30 to v ss37 : i/o buffers ground wait : wait wr : write strobe x1, x2: crystal
41 chapter 1 introduction user?s manual u16580ee2v0ud00 1.6 function blocks 1.6.1 internal block diagram figure 1-3: internal block diagram a/d converter 0 fcan1 fcrxd1 fctxd1 uartc0 txdc0 rxdc0 csib0 brg0 sib0 sob0 ssb0 sckb0 csib1 brg1 sib1 sob1 ssb1 sckb1 fcan0 fcrxd0 fctxd0 uartc1 txdc1 rxdc1 csi31 csc310 to csc313 si31 so31 sck31 csi30 csc300 to csc303 si30 so30 sck30 adtrg0 ani00 to ani09 av dd av ss 0 av ref 0 a/d converter 1 adtrg1 ani10 to ani19 av dd av ss 1 av ref 1 clock generator & system control moden reset x2 x1 v dd1 v ss1 v dd3 v ss3 cv dd cv ss rom bcu cpu rng brg2 afo ports pdl0 to pdl15 pdh0 to pdh15 pal0 to p al15 pah0 to p ah5 p00 to p04 p10 to p17 p20 to p27 p30 to p37 p40 to p45 p50 to p57 p60 to p67 p70 to p75 p80 to p86 p90 to p96 p100 to p102 pcs0, pcs1, pcs3, pcs4 pcm0, pcm1, pcm6, pcm7 pct4, pct5 pcd2 to pcd5 intc nmi intp0 to intp12 rpu tmr: 2ch tmenc10:1ch tmp: 9ch tmt: 2ch tor00 to tor07 tor10 to tor17 eso0, eso1 top00 to top70 top01 1 to top8 tip00 to tip70 tip01 to tip71 tevtp0 to tevtp8 ttrgp0 to ttrgp8 tenct00, tenct01, tecrt0 tenct10, tenct11, tecrt1 tit00, tit01 tit10, tit11 tevtt0, ttrgt0, tevtt1 ttrgt1 ttrgr1 tir10 to tir13 tot00, tot01 tot10, tot11 to1 tclr1 tcud1,tiud1 ticc10 ticc11 dcu dck, dms ddi, ddo drst alu multiplier 32 x 32 64 floating point unit ram dmac memc sram rom instruction queue d0 to d31 cs0 cs1 , cs3 cs4 , be0 be3 to a0 to a21 wait rd wr 32-bit barrel shifter pc system registers general registers 32-bit x 32 512 kb 32 kb
42 chapter 1 introduction user?s manual u16580ee2v0ud00 1.6.2 on-chip units (1) cpu the cpu uses five-stage pipeline control to enable single-clock execution of address calculations, arithmetic logic operations, data transfers, and almost all other instruction processing. other dedicated on-chip hardware, such as a multiplier (16 bits 16 bits 32 bits or 32 bits 32 bits 64 bits) and a barrel shifter (32 bits), help accelerate processing of complex instructions. (2) bus control unit (bcu) the bcu starts the required external bus cycle ba sed on the physical address obtained by the cpu. when an instruction is fetched from external memory area and the cpu does not send a bus cycle start request, the bcu genera tes a prefetch address and prefetches the instruction code. the prefetched instruction code is stored in an instruction queue in the cpu. the bcu controls a memory controller (memc) and dma controller (dmac) and performs external memory access and dma transfer. (a) memory controller (memc) the memc controls sram, rom, and vari ous i/o for external memory expansion. ? sram, external rom, external i/o interface supports access to sram, external rom, and external i/o. (b) dma controller (dmac) the dmac performs data transfers b/w internal on-chip ram and peripheral i/o. for this purpose eight dma channels are provided for particular transfer functions of serial i/o interfaces, real-time pulse unit (tmr), and a/d converter. (3) rom there is on-chip flash memory (512 kb) in the v850e/ph2 provided. on an instruction fetch, the rom can be accessed by the cpu in one clock. when single-chip mode 0 or flash memory progra mming mode is set, rom is mapped starting from address 00000000h. when single-chip mode 1 is set, it is mapped starting from address 00100000h. rom cannot be accessed if rom-less mode is set. (4) ram on-chip ram is mapped starting from address 03ff0000h. it can be accessed by the cpu in one clock on an instruction fetch or data access. (5) interrupt controller (intc) the intc services hardware interrupt requests from on-chip peripheral i/o and external sources (nmi, intp0 to intp12). eight levels of interrupt priorities can be specified for these interrupt requests, and multiple-interrupt servicing control can be performed for interrupt sources
43 chapter 1 introduction user?s manual u16580ee2v0ud00 (6) clock generator (cg) the cg provides a frequency that is 4 times the input clock (f x ) (using the on-chip pll) as the internal system clock (f cpu ). as the input clock, connect an exte rnal crystal or resonator to pins x1 and x2 or input an external clock from the x1 pin. (7) real-time pulse unit (rpu) the rpu incorporates a 2-channel 16-bit timer (tmr) for 3/6-phase sine wave pwm inverter control, an 1-channel 16-bit up/down counter (tmenc10) and a 2-channel 16-bit up/down counter (tmt) that can be used for 2-phase encoder input or as a general-purpose timer, a 9-channel 16-bit general-purpose timer unit (tmp). the rpu can measure pulse interval or frequency and can output programmable pulses. (8) serial interface (sio) the serial interfaces consist of 2 channels asynchronous serial interface c (uartc), 2 channels clocked serial interface b (csib), 2 channels clocked serial interface 3 (csi3), and 2 channels fcan interface (afcan). the uartc performs data transfer using pins txdcn and rxdcn (n = 0, 1). the csib performs data transfer using pins sobn, sibn, sckbn , ssin, and sson (n = 0, 1). the csi3 performs data transfer using pins so3n, si3n, sck3n , scs3n0 to scs3 (n = 0, 1). the afcan performs data transfer using pins fctxdn and fcrxdn (n = 0, 1). (9) baud rate generator (brg) the baud rate generator comprises 3 channels of 8-bit counters and comparators that can be used for clock supply of serial interfaces (csib) , auxiliary frequency output (afo) or interval timer. (10) a/d converter (adc) the two units of high-speed, high-resolution 10-bit a/d converter include 10 analog input pins for each unit. conversion is performed using the successive approximation method. (11) random number generator (rng) for encryption purpose a random number generator is provided. (12) debug control unit (dcu) on-chip debugging can be performed via a debug control unit (n-wire interface).
44 chapter 1 introduction user?s manual u16580ee2v0ud00 (13) ports as shown below, the following ports have general-purpose port functions and control pin functions. port i/o control function port 0 5-bit input nmi input, external interrup t input, a/d converter external trigger input, emergency shut-off input port 1 8-bit i/o real-time pulse unit i/o port 2 8-bit i/o real-time pulse unit i/o port 3 8-bit i/o serial interfac e i/o, external interrupt input port 4 6-bit i/o serial interface i/o port 5 8-bit i/o real-time pulse unit i/o port 6 8-bit i/o real-time pulse unit i/o port 7 6-bit i/o real-time pulse unit i/o, external interrupt input port 8 7-bit i/o serial interfac e i/o, external interrupt input port 9 7-bit i/o serial interfac e i/o, external interrupt input port 10 3-bit i/o real-time pulse unit i/o port al 16-bit i/o external address bus port ah 6-bit i/o external address bus port dl 16-bit i/o external data bus port dh 16-bit i/o external data bus port cd 4-bit i/o external bus interface control signal output port cm 4-bit i/o wait insertion signal input port cs 4-bit i/o external bus interface control signal output port ct 2-bit i/o external bus interface control signal output
45 user?s manual u16580ee2v0ud00 chapter 2 pin functions 2.1 list of pin functions the names and functions of the v850e/ph2 microcontroller pins are listed below. these pins can be divided into port pins and non-port pins according to their functions. (1) port pins table 2-1: port pins (1/5) pin name i/o function alternate function p00 i port 0 5-bit input-only port nmi p01 intp0, eso0 p02 intp1, eso1 p03 intp2, adtrg0 p04 intp3, adtrg1 p10 i/o port 1 8-bit i/o port input or output direction can be specified in 1-bit units tip00, tevtp1, top00 p11 tip01, ttrgp1, top01 p12 tip10, ttrgp0, top10 p13 tip11, tevtp0, top11 p14 tip20, tevtp3, top20 p15 tip21, ttrgp3, top21 p16 tip30, ttrgp2, top30 p17 tip31, tevtp2, top31 p20 i/o port 2 8-bit i/o port input or output direction can be specified in 1-bit units tip40, tevtp5, top40 p21 tip41, ttrgp5, top41 p22 tip50, ttrgp4, top50 p23 tip51, tevtp4, top51 p24 tip60, tevtp7, top60 p25 tip61, ttrgp7, top61 p26 tip70, ttrgp6, top70 p27 tip71, tevtp6, top71 p30 i/o port 3 8-bit i/o port input or output direction can be specified in 1-bit units rxdc0, intp4 p31 txdc0 p32 rxdc1, intp5 p33 txdc1 p34 fcrxd0 p35 fctxd0 p36 fcrxd1 p37 fctxd1
46 chapter 2 pin functions user?s manual u16580ee2v0ud00 p40 i/o port 4 6-bit i/o port input or output direction can be specified in 1-bit units sib0 p41 sob0 p42 sckb0 p43 sib1 p44 sob1 p45 sckb1 p50 i/o port 5 8-bit i/o port input or output direction can be specified in 1-bit units tor00 p51 tor01 p52 tor02 p53 tor03 p54 tor04 p55 tor05 p56 tor06 p57 tor07 p60 i/o port 6 8-bit i/o port input or output direction can be specified in 1-bit units tor10, ttrgr1 p61 tor11, tir10 p62 tor12, tir11 p63 tor13, tir12 p64 tor14, tir13 p65 tor15 p66 tor16 p67 tor17, tevtr1 p70 i/o port 7 6-bit i/o port input or output direction can be specified in 1-bit units tit00, tevtt1, tot00, tenct00 p71 tit01, ttrgt1, tot01, tenct01 p72 tecrt0, intp12 p73 tit10, ttrgt0, tot10, tenct10 p74 tit11, tevtt0, tot11, tenct11 p75 tecrt1, afo p80 i/o port 8 7-bit i/o port input or output direction can be specified in 1-bit units si30 p81 so30 p82 sck30 p83 scs300, intp6 p84 scs301, intp7 p85 scs302, intp8 p86 scs303, ssb0 table 2-1: port pins (2/5) pin name i/o function alternate function
47 chapter 2 pin functions user?s manual u16580ee2v0ud00 p90 i/o port 9 7-bit i/o port input or output direction can be specified in 1-bit units si31 p91 so31 p92 sck31 p93 scs310, intp9 p94 scs311, intp10 p95 scs312, intp11 p96 scs313, ssb1 p100 i/o port 10 3-bit i/o port input or output direction can be specified in 1-bit units tclr1, ticc10, top81 p101 tcud1, ticc11 p102 tiud1, to1 pal0 i/o port al 16-bit i/o port input or output direction can be specified in 1-bit units a0 pa l 1 a 1 pa l 2 a 2 pa l 3 a 3 pa l 4 a 4 pa l 5 a 5 pa l 6 a 6 pa l 7 a 7 pa l 8 a 8 pa l 9 a 9 pal10 a10 pal11 a11 pal12 a12 pal13 a13 pal14 a14 pal15 a15 pah0 i/o port ah 6-bit i/o port input or output direction can be specified in 1-bit units a16 pa h 1 a 1 7 pa h 2 a 1 8 pa h 3 a 1 9 pa h 4 a 2 0 pa h 5 a 2 1 table 2-1: port pins (3/5) pin name i/o function alternate function
48 chapter 2 pin functions user?s manual u16580ee2v0ud00 pdl0 i/o port dl 16-bit i/o port input or output direction can be specified in 1-bit units d0 pdl1 d1 pdl2 d2 pdl3 d3 pdl4 d4 pdl5 d5 pdl6 d6 pdl7 d7 pdl8 d8 pdl9 d9 pdl10 d10 pdl11 d11 pdl12 d12 pdl13 d13 pdl14 d14 pdl15 d15 pdh0 i/o port dh 16-bit i/o port input or output direction can be specified in 1-bit units d16 pdh1 d17 pdh2 d18 pdh3 d19 pdh4 d20 pdh5 d21 pdh6 d22 pdh7 d23 pdh8 d24 pdh9 d25 pdh10 d26 pdh11 d27 pdh12 d28 pdh13 d29 pdh14 d30 pdh15 d31 pcd2 i/o port cd 4-bit i/o port input or output direction can be specified in 1-bit units ben0 pcd3 ben1 pcd4 ben2 pcd5 ben3 pcm0 i/o port cm 4-bit i/o port input or output direction can be specified in 1-bit units wait pcm1 pcm6 pcm7 table 2-1: port pins (4/5) pin name i/o function alternate function
49 chapter 2 pin functions user?s manual u16580ee2v0ud00 pcs0 i/o port cs 4-bit i/o port input or output direction can be specified in 1-bit units cs0 pcs1 cs1 pcs3 cs3 pcs4 cs4 pct4 i/o port ct 2-bit i/o port input or output direction can be specified in 1-bit units rd pct5 wr table 2-1: port pins (5/5) pin name i/o function alternate function
50 chapter 2 pin functions user?s manual u16580ee2v0ud00 (2) non-port pins table 2-2: non-port pins (1/5) pin name i/o function alternate function a0 to a15 o 22-bit external address bus pal0 to pal15 a16 to a21 pah0 to pah5 adtrg0 i a/d conversion start trigger (adc0) p03, intp2 adtrg1 i a/d conversion start trigger (adc1) p04, intp3 afo o auxiliary frequency output p75, tecrt1 ani00 to ani09 i analog input channels (adc0) ? ani10 to ani19 i analog input channels (adc1) ? av dd ? positive power supply (3.3 v) (adc0, adc1) ? av ref0 i reference voltage input (adc0) ? av ref1 i reference voltage input (adc1) ? av ss0 ? power supply ground (adc0) ? av ss1 ? power supply ground (adc1) ? ben0 o external byte enable output pcd2 ben1 pcd3 ben2 pcd4 ben3 pcd5 cs0 o chip select signal output pcs0 cs1 pcs1 cs3 pcs3 cs4 pcs4 cv dd ? oscillator power supply (1.5 v) ? cv ss ? oscillator power supply ground ? d0 to d15 i/o 32-bit external data bus pdl0 to pdl15 d16 to d31 pdh0 to pdh15 dck i n-wire interface clock ? ddi i n-wire data input and reset mode selection ? ddo o n-wire data output ? dms i n-wire mode select ? drst i n-wire interface reset ? eso0 i emergency shut off input (tmr0) intp0, p01 eso1 i emergency shut off input (tmr1) intp1, p02 fcrxd0 i receive input (afcan0) p34 fcrxd1 i receive input (afcan1) p36 fctxd0 o transmit output (afcan0) p35 fctxd1 o transmit output (afcan1) p37 flmd0 i flash programming mode selection mode0 flmd1 mode1
51 chapter 2 pin functions user?s manual u16580ee2v0ud00 intp0 i external maskable interrupt request input p01, eso0 intp1 p02, eso1 intp2 p03, adtrg0 intp3 p04, adtrg1 intp4 p30, rxdc0 intp5 p32, rxdc1 intp6 p83, scs300 intp7 p84, scs301 intp8 p85, scs302 intp9 p93, scs310 intp10 p94, scs311 intp11 p95, scs312 intp12 p72, tecrt0 mode0 i device operating mode selection flmd0 mode1 flmd1 mode2 ? nmi i non-maskable interrupt request input p00 rd o read strobe signal output pct4 reset i system reset input ? rxdc0 i receive input (uartc0) p30, intp4 rxdc1 i receive input (uartc1) p32, intp5 sck30 i/o serial shift cl ock i/o (csi30) p82 sck31 i/o serial shift cl ock i/o (csi31) p92 sckb0 i/o serial shift cl ock i/o (csib0) p42 sckb1 i/o serial shift cl ock i/o (csib1) p45 scs300 o serial peripheral chip select (csi30) p83, intp7 scs301 p84, intp8 scs302 p85, intp9 scs303 p86, ssb0 scs310 o serial peripheral chip select (csi31) p93, intp10 scs311 p94, intp10 scs312 p95, intp11 scs313 p96, ssb1 si30 i serial data input (csi30) p80 si31 i serial data input (csi31) p90 sib0 i serial data input (csib0) p40 sib1 i serial data input (csib1) p43 so30 o serial data output (csi30) p81 so31 o serial data output (csi31) p91 sob0 o serial data output (csib0) p41 sob1 o serial data output (csib1) p44 table 2-2: non-port pins (2/5) pin name i/o function alternate function
52 chapter 2 pin functions user?s manual u16580ee2v0ud00 ssb0 i serial slave select input (csib0) p86, scs303 ssb1 i serial slave select input (csib1) p96, scs313 tclr1 i timer clear input (itenc0) p100, ticc10, top81 tcud1 i count up/down direction control input (itenc0) p101, ticc11 tecrt0 i timer clear input (tmt0) p72, intp12 tecrt1 i timer clear input (tmt1) p75, afo tenct00 i timer encoder input (tmt 0) p70, tit00, tevtt1, tot00 tenct01 i p71, tit01, ttrgt1, tot01 tenct10 i timer encoder input (tmt 1) p73, tit10, ttrgt0, tot10 tenct11 i p74, tit11, tevtt0, tot11 tevtp0 i timer event input (tmp0) p13, tip11, top11 tevtp1 i timer event input (tmp1) p10, tip00, top00 tevtp2 i timer event input (tmp2) p17, tip31, top31 tevtp3 i timer event input (tmp3) p14, tip20, top20 tevtp4 i timer event input (tmp4) p23, tip51, top51 tevtp5 i timer event input (tmp5) p20, tip40, top40 tevtp6 i timer event input (tmp6) p27, tip71, top71 tevtp7 i timer event input (tmp7) p24, tip60, top60 tevtr1 i timer event input (tmr1) p67, tor17 tevtt0 i timer event input (tmt 0) p74,tit11, tot11, tenct11 tevtt1 i timer event input (tmt 1) p70, tit00, tot00, tenct00 ticc10 i itenc0 capture trigger input p100, tclr1, top81 ticc11 p101, tcud1 tip00 i capture trigger input (tmp0) p10, tevtp1, top00 tip01 p11, ttrgp1, top01 tip10 i capture trigger input (tmp1) p12, ttrgp0, top10 tip11 p13, tevtp0, top11 tip20 i capture trigger input (tmp2) p14, tevtp3, top20 tip21 p15, ttrgp3, top21 tip30 i capture trigger input (tmp3) p16, ttrgp2, top30 tip31 p17, tevtp2, top31 tip40 i capture trigger input (tmp4) p20, tevtp5, top40 tip41 p21, ttrgp5, top41 tip50 i capture trigger input (tmp5) p22, ttrgp4, top50 tip51 p23, tevtp4, top51 tip60 i capture trigger input (tmp6) p24, tevtp7, top60 tip61 p25, ttrgp7, top61 tip70 i capture trigger input (tmp7) p26, ttrgp6, top70 tip71 p27, tevtp6, top71 table 2-2: non-port pins (3/5) pin name i/o function alternate function
53 chapter 2 pin functions user?s manual u16580ee2v0ud00 tir10 i capture trigger in put (tmr1) p61, tor11 tir11 p62, tor12 tir12 p63, tor13 tir13 p64, tor14 tit00 i capture trigger input (tmt 0) p70, tevtt1, tot00, tenct00 tit01 p71, ttrgt1, tot01, tenct01 tit10 i capture trigger input (tmt 0) p73, ttrgt0, tot10, tenct10 tit11 p74,tevtt0, tot11, tenct11 tiud1 i external count clock input (itenc0) p102, to1 to1 o pulse signal output (itenc0) p102, tiud1 top00 o pulse signal output (tmp0) p10, tip00, tevtp1 top01 p11, tip01, ttrgp1 top10 o pulse signal output (tmp1) p12, tip10, ttrgp0 top11 p13, tip11, tevtp0 top20 o pulse signal output (tmp2) p14, tip20, tevtp3 top21 p15, tip21, ttrgp3 top30 o pulse signal output (tmp3) p16, tip30, ttrgp2 top31 p17, tip31, tevtp2 top40 o pulse signal output (tmp4) p20, tip40, tevtp5 top41 p21, tip41, ttrgp5 top50 o pulse signal output (tmp5) p22, tip50, ttrgp4 top51 p23, tip51, tevtp4 top60 o pulse signal output (tmp6) p24, tip60, tevtp7 top61 p25, tip61, ttrgp7 top70 o pulse signal output (tmp7) p26, tip70, ttrgp6 top71 p27, tip71, tevtp6 top81 o pulse signal output (tmp8) p100, tclr1, ticc10 tor00 o pulse signal output (tmr0) p50 tor01 p51 tor02 p52 tor03 p53 tor04 p54 tor05 p55 tor06 p56 tor07 p57 table 2-2: non-port pins (4/5) pin name i/o function alternate function
54 chapter 2 pin functions user?s manual u16580ee2v0ud00 tor10 o pulse signal output (tmr1) p60, ttrgr1 tor11 p61, tir10 tor12 p62, tir11 tor13 p63, tir12 tor14 p64, tir13 tor15 p65 tor16 p66 tor17 p67, tevtr1 tot00 o pulse signal output (tmt 0) p70, tit00, tevtt1, tenct00 tot01 p71, tit01, ttrgt1, tenct01 tot10 o pulse signal output (tmt 1) p73, tit10, ttrgt0, tenct10 tot11 p74,tit11, tevtt0, tenct11 ttrgp0 i timer trigger input (tmp0) p12, tip10, top10 ttrgp1 timer trigger input (tmp1) p11, tip01, top01 ttrgp2 timer trigger input (tmp2) p16, tip30, top30 ttrgp3 timer trigger input (tmp3) p15, tip21, top21 ttrgp4 timer trigger input (tmp4) p22, tip50, top50 ttrgp5 timer trigger input (tmp5) p21, tip41, top41 ttrgp6 timer trigger input (tmp6) p26, tip70, top70 ttrgp7 timer trigger input (tmp7) p25, tip61, top61 ttrgr1 i timer trigger input (tmr1) p60, tor10 ttrgt0 i timer trigger input (tmt 0) p73, tit10, tot10, tenct10 ttrgt1 i timer trigger input (tmt 1) p71, tit01, tot01, tenct01 txdc0 o transmit output (uartc0) p31 txdc1 o transmit output (uartc1) p33 v dd10 to v dd15 ? positive power supply for internal cpu (1.5 v) ? v dd30 to v dd37 ? positive power supply for peripheral interface (3.3 v) ? v ss10 to v ss15 ? power supply ground for internal cpu ? v ss30 to v ss37 ? power supply ground for peripheral interface ? wait i external wait control signal input pcm0 wr o write strobe signal output pct5 x1 i crystal connection ? x2 ? ? table 2-2: non-port pins (5/5) pin name i/o function alternate function
55 chapter 2 pin functions user?s manual u16580ee2v0ud00 2.2 pin status remark: hi-z: high impedance ?: input data is not sampled : no function selected at reset table 2-3: pin status in reset and standby mode pin operating status during reset after reset release halt mode single-chip mode 0 single-chip mode 1 rom-less mode a0 to a15 (pal0 to pal15) hi-z hi-z operating operating a16 to a21 (pah0 to pah5) hi-z hi-z operating operating d0 to d15 (pdl0 to pdl15) hi-z hi-z operating operating d16 to d31 (pdh0 to pdh15) hi-z hi-z operating operating ben0 to ben3 (pcd2 to pcd5) hi-z hi-z operating operating cs0 (pcs0) hi-z hi-z operating operating cs1 (pcs1) hi-z hi-z operating operating cs3 (pcs3) hi-z hi-z operating operating cs4 (pcs4) hi-z hi-z operating operating rd (pct4) hi-z hi-z operating operating wr (pct5) hi-z hi-z operating operating wait (pcm0) hi-z hi-z operating operating bclk (pcm1) hi-z hi-z hi-z operating stst (pcm6) hi-z hi-z hi-z operating stnxt (pcm7) hi-z hi-z hi-z operating dck operating operating operating operating ddi operating operating operating operating ddo operating operating operating operating dms operating operating operating operating drst operating operating operating operating intp0 to intp3 (p01 to p04) ? input input operating intp4 (p30) ? input input operating intp5 (p32) ? input input operating intp6 to intp8 (p83 to p85) ? input input operating intp9 to intp11 (p93 to p95) ? input input operating nmi (p00) ? input input operating peripheral input pin other than above hi-z hi-z hi-z operating peripheral output pin other than above operating port input pin other than above hi-z hi-z hi-z ? port output pin other than above hold
56 chapter 2 pin functions user?s manual u16580ee2v0ud00 2.3 description of pin functions (1) p00 to p04 (port 0) ? input port 0 is an 8-bit input-only port in which all pins are fixed for input. besides functioning as a port, in control mode, p00 to p04 operate as nmi input, external interrupt request signal, real-time pulse unit (rpu) emergen cy shut off signal input, and a/d converter (adc) external trigger input. normally, if function pins also serve as ports, one mode or the other is selected using a port mode control register. however, there is no such register for p00 to p04. therefore, the input port cannot be switched with the nmi input pin, external interrupt request input pin, rpu emergency shut off signal input pin, and a/d converter (adc) external trigger input pin. read the status of each pin by reading the port. (a) port mode p00 to p04 are input-only. (b) control mode p00 to p04 also serve as nmi, intp0 to intp3, eso0, eso1, adtrg0, and adtrg1 pins, but the control function cannot be disabled. (i) nmi (non-maskable interrupt request) ? input this is non-maskable interrupt request input. (ii) intp0 to intp3 (interrupt request from peripherals) ? input these are external interrupt request input pins. (iii) eso0, eso1 (emergen cy shut off) ? input these pins input timer tmr0 and timer tmr1 emergency shut off signals. (iv) adtrg0, adtrg1 (a/d trigger input) ? input these are a/d converter external trigger input pins.
57 chapter 2 pin functions user?s manual u16580ee2v0ud00 (2) p10 to p17 (port 1) ? input/output port 1 is an 8-bit i/o port in which input or output can be set for each port pin individually. besides functioning as an i/o port, in control mode, p10 to p17 operate as rpu input or output. the operation mode can be specified by the port 1 mode control register (pmc1) to port or control mode for each port pin individually. (a) port mode p10 to p17 can be set to input or output in 1-bit units using the port 1 mode register (pm1). (b) control mode p10 to p17 can be set to port or control mode in 1-bit units using the pmc1 register. (i) tip00, tip01, tip10, tip11, tip20, tip21, tip30, tip31 (timer capture input) ? input these are timer tmp0 to tmp3 capture trigger input pins. (ii) tevtp0, tevtp1, tevtp2, tevt p3 (timer event input) ? input these are timer tmp0 to tmp3 external event counter input pins. (iii) ttrgp0, ttrgp1, ttrgp2, ttrgp3 (timer trigger) ? input these are timer tmp0 to tmp3 external trigger input pins. (iv) top00, top01, top10, top11, top20, top21, top30, top31 (timer output) ? output these pins output timer tmp0 to tmp3 pulse signals. (3) p20 to p27 (port 2) ? input/output port 2 is an 8-bit i/o port in which input or output can be set for each port pin individually. besides functioning as an i/o port, in control mode, p20 to p27 operate as rpu input or output. the operation mode can be specified by the port 2 mode control register (pmc2) to port or control mode for each port pin individually. (a) port mode p20 to p27 can be set to input or output in 1-bit units using the port 2 mode register (pm2). (b) control mode p20 to p27 can be set to port or control mode in 1-bit units using the pmc2 register. (i) tip40, tip41, tip50, tip51, tip60, tip61, tip70, tip71 (timer capture input) ? input these are timer tmp4 to tmp7 capture trigger input pins. (ii) tevtp4, tevtp5, tevtp6, tevt p7 (timer event input) ? input these are timer tmp4 to tmp7 external event counter input pins. (iii) ttrgp4, ttrgp5, ttrgp6, ttrgp7 (timer trigger) ? input these are timer tmp4 to tmp7 external trigger input pins. (iv) top40, top41, top50, top51, top60, top61, top70, toip71 (timer output) ? out- put these pins output timer tmp4 to tmp7 pulse signals.
58 chapter 2 pin functions user?s manual u16580ee2v0ud00 (4) p30 to p37 (port 3) ? input/output port 3 is an 8-bit i/o port in which input or output can be set for each port pin individually. besides functioning as an i/o port, in control mode, p30 to p37 operate as serial interface (uartc0, uartc1, afcan0, afcan1). additionally external interrupt request signal inputs are available in port input mode. the operation mode can be specified by the port 3 mode control register (pmc3) to port or control mode for each port pin individually. (a) port mode p30 to p37 can be set to input or output in 1-bit units using the port 3 mode register (pm3). (i) intp4, intp5 (interrupt request from peripherals) ? input these are external interrupt request input pins, which are simultaneously enabled in port input mode. (b) control mode p30 to p37 can be set to port or control mode in 1-bit units using the pmc3 register. (i) txdc0, txdc1 (transmit data) ? output these pins output serial transmit data of uartc0 and uartc1. (ii) rxdc0, rxdc1 (receive data) ? input these pins input serial receive data of uartc0 and uartc1. (iii) fctxd0, fctxd1 (transmit data for controller area network) ? output these pins output afcan0 and afcan1 serial transmit data. (iv) fcrxd 0, fcrxd1 (receive data for controller area network) ? input these pins input afcan0 and afcan1 serial receive data. (5) p40 to p45 (port 10) ? input/output port 4 is a 6-bit i/o port in which input or output can be set for each port pin individually. besides functioning as an i/o port, in control mode, p40 to p45 operate as serial interface (csib0, csib1). the operation mode can be specified by the port 4 mode control register (pmc4) to port or control mode for each port pin individually. (a) port mode p40 to p45 can be set to input or output in 1-bit units using the port 4 mode register (pm4). (b) control mode p40 to p45 can be set to port or control mode in 1-bit units using the pmc4 register. (i) sob0, sob1 (serial output) ? output these pins output csib0 and csib1 serial transmit data. (ii) sib0, sib1 (serial input) ? input these pins input csib0 and csib1 serial receive data. (iii) sckb0 , sckb1 (serial clock) ? i/o these are the csib0 and csib1 serial clock i/o pins.
59 chapter 2 pin functions user?s manual u16580ee2v0ud00 (6) p50 to p57 (port 5) ? input/output port 5 is an 8-bit i/o port in which input or output can be set for each port pin individually. besides functioning as an i/o port, in control mode, p50 to p57 operate as rpu input or output. the operation mode can be specified by the port 5 mode control register (pmc5) to port or control mode for each port pin individually. (a) port mode p50 to p57 can be set to input or output in 1-bit units using the port 5 mode register (pm5). (b) control mode p50 to p57 can be set to port or control mode in 1-bit units using the pmc5 register. (i) tor00, tor01, tor02, tor03, tor04 (timer output) ? output these pins output timer tmr0 pulse signals. (7) p60 to p67 (port 6) ? input/output port 6 is an 8-bit i/o port in which input or output can be set for each port pin individually. besides functioning as an i/o port, in control mode, p60 to p67 operate as rpu input or output. the operation mode can be specified by the port 6 mode control register (pmc6) to port or control mode for each port pin individually. (a) port mode p60 to p67 can be set to input or output in 1-bit units using the port 6 mode register (pm6). (b) control mode p60 to p67 can be set to port or control mode in 1-bit units using the pmc6 register. (i) tir10, tir11, tir12, tir13 (timer capture input) ? input these are timer tmr1 capture trigger input pins. (ii) tevtr1 (timer event input) ? input this is a timer tmr1 external event counter input pin. (iii) ttrgr1 (timer trigger) ? input this is a timer tmr1 external trigger input pin. (iv) tor10, tor11, tor12, tor13, tor14 (timer output) ? output these pins output timer tmr1 pulse signals.
60 chapter 2 pin functions user?s manual u16580ee2v0ud00 (8) p70 to p75 (port 7) ? input/output port 7 is a 6-bit i/o port in which input or output can be set for each port pin individually. besides functioning as an i/o port, in control mode, p70 to p75 operate as rpu input or output, and auxiliary frequency output. additi onally an external interrupt r equest signal input is available in port input mode. the operation mode can be specified by the port 7 mode control register (pmc7) to port or control mode for each port pin individually. (a) port mode p70 to p75 can be set to input or output in 1-bit units using the port 7 mode register (pm7). (i) intp12 (interrupt request from peripherals) ? input this is an external interrupt request input pi n, which is simultaneously enabled in port input mode. (b) control mode p70 to p75 can be set to port or control mode in 1-bit units using the pmc7 register. (i) tit00, tit01, tit10, tit11 (timer capture input) ? input these are timer tmt0 and tmt1 capture trigger input pins. (ii) tevtt0, tevtt1 (timer event input) ? input these are timer tmt0 and tmt1 external event counter input pins. (iii) ttrgt0, ttrgt1 (timer trigger) ? input these are timer tmt0 and tmt1 external trigger input pins. (iv) tecrt0, tecrt1 (timer clear) ? input these are timer tmt0 and tmt1 external clear input pins. (v) tenct00, tenct01, tenct10, tenct11 (timer encoder input ? input these are timer tmt0 and tmt1 encoder input pins. (vi) tot00, tot01, tot10, tot11 (timer output) ? output these pins output timer tmt0 and tmt1 pulse signals. (vii)afo (auxiliary frequency) ? output this is an auxiliary freq uency output signal pin of baudrate generator bgr2.
61 chapter 2 pin functions user?s manual u16580ee2v0ud00 (9) p80 to p86 (port 8) ? input/output port 8 is a 7-bit i/o port in which input or output can be set for each port pin individually. besides functioning as an i/o port, in control mode, p80 to p86 operate as serial interface (csi30, csib0). additionally external interrupt request signal inputs are available in port input mode. the operation mode can be specified by the port 8 mode control register (pmc8) to port or control mode for each port pin individually. (a) port mode p80 to p86 can be set to input or output in 1-bit units using the port 8 mode register (pm8). (i) intp6, intp7, intp8 (interrupt request from peripherals) ? input these are external interrupt request input pins, which are simultaneously enabled in port input mode. (b) control mode p80 to p86 can be set to port or control mode in 1-bit units using the pmc8 register. (i) so30 (serial output) ? output this pin outputs csi30 serial transmit data. (ii) si30 (serial input) ? input this pin inputs csi30 serial receive data. (iii) sck30 (serial clock) ? i/o this is the csi30 serial clock i/o pin. (iv) scs300 to scs303 (serial chip select) ? output these pins output csi30 serial chip select signals. (v) ssb0 (serial slave select signal) ? input this pin inputs csib0 slave select signal.
62 chapter 2 pin functions user?s manual u16580ee2v0ud00 (10) p90 to p96 (port 9) ? input/output port 9 is a 7-bit i/o port in which input or output can be set for each port pin individually. besides functioning as an i/o port, in control mode, p90 to p96 operate as serial interface (csi31, csib1). additionally external interrupt request signal inputs are available in port input mode. the operation mode can be specified by the port 9 mode control register (pmc9) to port or control mode for each port pin individually. (a) port mode p90 to p96 can be set to input or output in 1-bit units using the port 9 mode register (pm9). (i) intp9, intp10, intp11 (interrupt request from peripherals) ? input these are external interrupt request input pins, which are simultaneously enabled in port input mode. (b) control mode p90 to p96 can be set to port or control mode in 1-bit units using the pmc9 register. (i) so31 (serial output) ? output this pin outputs csi31 serial transmit data. (ii) si31 (serial input) ? input this pin inputs csi31 serial receive data. (iii) sck31 (serial clock) ? i/o this is the csi31 serial clock i/o pin. (iv) scs310 to scs313 (serial chip select) ? output these pins output csi31 serial chip select signals. (v) ssb1 (serial slave select input) ? input this pin inputs csib1 slave select signal.
63 chapter 2 pin functions user?s manual u16580ee2v0ud00 (11) p100 to p102 (port 10) ? input/output port 10 is a 3-bit i/o port in which input or output can be set for each port pin individually. besides functioning as an i/o port, in control mode, p100 to p102 operate as rpu input or output the operation mode can be specified by the port 10 mode control register (pmc10) to port or control mode for each port pin individually. (a) port mode p100 to p102 can be set to input or output in 1-bit units using the port 10 mode register (pm10). (b) control mode p100 to p102 can be set to port or control mode in 1-bit units using the pmc4 register. (i) tiud1 (timer count pulse input) ? input this is an external count clock input pin to the up/down counter (tmenc10). (ii) tcud1 (timer control pulse input) ? input this is an input count operation switching signal to the up/down counter (tmenc10). (iii) tclr1 (timer clear) ? input this is a clear signal input pin to the up/down counter (tmenc10). (iv) ticc10, ticc11 (timer capture input) ? input these are timer tmenc10 external capture trigger input pins. (v) to1 (timer output) ? output this pin outputs timer tmenc10 pulse signals. (vi) top80 (timer output) ? output this pin outputs timer tmp8 pulse signals. (12) pal0 to pal15 (port al) ? i/o port al is an 8-bit or a 16-bit i/o port in which input or output can be set for each port pin individually. besides functioning as a port, in control mode, t hese pins operate as the address bus (a0 to a15) when memory is expanded externally. the operation mode can be specified by the port al mode control register (pmcal) to port or control mode for each port pin individually. (a) port mode pal0 to pal15 can be set to input or output in 1-bit units using the port al mode register (pmal). (b) control mode pal0 to pal15 can be set to port or control mode in 1-bit units using the pmcal register. (i) a0 to a15 (address bus) ? 3-state output these are the address output pins of the lower 16 bits of the 22-bit address bus when the external memory is accessed.
64 chapter 2 pin functions user?s manual u16580ee2v0ud00 (13) pah0 to pah5 (port ah) ? i/o port ah is a 6-bit i/o port in which input or output can be set for each port pin individually. besides functioning as a port, in control mode, these pins operate as the address bus (a16 to a21) when memory is expanded externally. the operation mode can be specified by the port ah mode control register (pmcah) to port or control mode for each port pin individually. (a) port mode pah0 to pah5 can be set to input or output in 1-bit units using the port ah mode register (pmah). (b) control mode pah0 to pah6 can be set to port or control mode in 1-bit units using the pmcah register. (i) a16 to a21 (address bus) ? 3-state output these are the address output pins of the higher 6 bits of the 22-bit address bus when the external memory is accessed. (14) pdl0 to pdl15 (port dl) ? i/o port dl is an 8-bit or a 16-bit i/o port in which input or output can be set for each port pin individually. besides functioning as a port, in control mode, these pins operate as the data bus (d0 to d15) when memory is expanded externally. the operation mode can be specified by the port dl mode control register (pmcdl) to port or control mode for each port pin individually. (a) port mode pdl0 to pdl15 can be set to input or output in 1-bi t units using the port dl mode register (pmdl). (b) control mode pdl0 to pdl15 can be set to port or control mode in 1-bit units using the pmcdl register. (i) d0 to d15 (address bus) ? 3-state i/o these are the data i/o pins of the lower 16 bits of the 32-bit data bus when the external memory is accessed.
65 chapter 2 pin functions user?s manual u16580ee2v0ud00 (15) pdh0 to pdh15 (port dh) ? i/o port dh is an 8-bit or a 16-bit i/o port in which input or output can be set for each port pin individually. besides functioning as a port, in control mode, these pins operate as the data bus (d16 to d31) when memory is expanded externally. the operation mode can be specified by the port dh mode control register (pmcdh) to port or control mode for each port pin individually. (a) port mode pdh0 to pdh15 can be set to input or output in 1-bit units using the port dh mode register (pmdh). (b) control mode pdh0 to pdh15 can be set to port or control mode in 1-bit units using the pmcdh register. (i) d16 to d31 (address bus) ? 3-state i/o these are the data i/o pins of the higher 16 bits of the 32-bit data bus when the external memory is accessed. (16) pcd2 to pcd5 (port cd) ? i/o port cd is a 4-bit i/o port in which input or output can be set for each port pin individually. besides functioning as a port, in control mode, t hese pins operate as control signal outputs when memory is expanded externally. the operation mode can be specified by the port cd mode control register (pmccd) to port or control mode for each port pin individually. (a) port mode pcd2 to pcd5 can be set to input or output in 1-bit units using the port cd mode register (pmcd). (b) control mode pcd2 to pcd5 can be set to port or control mode in 1-bit units using the pmccd register. (i) ben0 to ben3 (byte enable) ? 3-state output these are the byte enable control signal pins, which indicate the validity of the corresponding byte on the 32-bit data bus.
66 chapter 2 pin functions user?s manual u16580ee2v0ud00 (17) pcm0, pcm1, pcm6, pcm7 (port cm) ? i/o port cm is a 4-bit i/o port in which input or output can be set for each port pin individually. besides functioning as a port, in control mode, these pins operate as control signal input when memory is expanded externally. the operation mode can be specified by the port cm mode control register (pmccm) to port or control mode for each port pin individually. (a) port mode pcm0, pcm1, pcm6, and pcm7 can be set to input or output in 1-bit units using the port cm mode register (pmcm). (b) control mode pcm0 can be set to port or control mode in 1-bit units using the pmccm register. (i) wait (wait) ? input this is the control signal input pin at which an external data wait is inserted into the bus cycle. the wait signal can be input asynchronously, and is sampled at the falling edge of the bclk signal. when the setup or hold time is terminated within the sampling timing, wait insertion may not be executed. (18) pcs0, pcs1, pcs3, pcs4 (port cs) ? i/o port cs is a 4-bit i/o port in which input or output can be set for each port pin individually. besides functioning as a port, in control mode, these pins operate as control signal outputs when memory is expanded externally. the operation mode can be specified by the port cs mode control register (pmccs) to port or control mode for each port pin individually. (a) port mode pcs0, pcs1, pcs3, and pcs4 can be set to input or output in 1-bit units using the port cs mode register (pmcs). (b) control mode pcs0, pcs1, pcs3, and pcs4 can be set to port or control mode in 1-bit units using the pmccs register. (i) cs0 , cs1 , cs3 , cs4 (chip select) ? 3-state output these are the chip select signal output pins for the external memory or peripheral i/o extension areas. the csn signal is assigned to the memory block n (n = 0, 1, 3, 4). it becomes active while the bus cycle that ac cesses the corresponding memory block is activated. in the idle state (ti), it becomes inactive. (19) pct4, pct5 (port ct) ? i/o port ct is a 2-bit i/o port in which input or output can be set for each port pin individually. besides functioning as a port, in control mode, these pins operate as control signal outputs when memory is expanded externally. the operation mode can be specified by the port ct mode control register (pmcct) to port or control mode for each port pin individually. (a) port mode
67 chapter 2 pin functions user?s manual u16580ee2v0ud00 pct4 and pct5 can be set to input or output in 1-bit units using the port ct mode register (pmct). (b) control mode pct4 and pct5 can be set to port or control mode in 1-bit units using the pmcct register. (i) rd (read strobe) ? 3-state output this is a strobe signal output pin that shows whether the bus cycle currently being executed is a read cycle for the external memory or peripheral i/o extension area. in the idle state (ti), it becomes inactive. (ii) wr (write strobe) ? 3-state output this is a strobe signal output pin that shows whether the bus cycle currently being executed is a write cycle for the external memory or peripheral i/o extension area.
68 chapter 2 pin functions user?s manual u16580ee2v0ud00 (20) dck (debug clock) ? input this pin inputs a debug clock. at the rising edge of the dck signal, the dms and ddi signals are sampled, and data is output from the ddo pin at the falling edge of the dck signal. keep this pin high when the debug function is not used. (21) ddi (debug data input) ? input this pin inputs debug data, which is sampled at the rising edge of the dck signal when the debug serial interface is in the shift state. data is input with the lsb first. keep this pin high when the debug function is not used. (22) ddo (debug data output) ? output this pin outputs debug data at the falling edge of the dck signal when the debug serial interface is in the shift state. data is output with the lsb first. (23) dms (debug mode select) ? input this input pin selects a debug mode. depending on the level of the dms signal, the state machine of the debug serial interface changes. this pin is sampled at the rising edge of the dck signal. keep this pin high when the debug function is not used. (24) drst (debug reset) ? input this pin inputs a debug reset signal that is a negative-logic signal to initialize the dcu asynchronously. when this signal goes low, the dcu is reset/invalidated. keep this pin low when the debug function is not used. (25) mode0 to mode2 (mode) ? input these are input pins used to specify the operating mode. (26) flmd0, flmd1 (flash programming mode) these are input pins used to specify the flash programming mode. (27) reset (reset) ? input reset is a signal that is input asynchronously and that has a constant low level width regardless of the operating clock?s status. when this signal is input, a system reset is executed as the first priority ahead of all other operations. in addition to being used for ordinary initialization/ start operations, this pin can also be used to release a standby mode (halt). (28) x1, x2 (crystal) these pins are used to connect the resonator that generates the system clock. (29) ani00 to ani09, ani10 to ani19 (analog input) ? input these are analog input pins of the corresponding a/d converter (adc0, adc1). (30) av ref0 , av ref1 (analog reference voltage) ? input these are reference voltage supply pins for the corresponding a/d converter (adc0, adc1). (31) av dd (analog power supply) this is the positive power supply pin for the a/d converters.
69 chapter 2 pin functions user?s manual u16580ee2v0ud00 (32) av ss (analog ground) this is the analog ground pin for the a/d converters. (33) cv dd (power supply for clock generator) this is the positive power supply pin for the clock generator. (34) cv ss (ground for clock oscillator) this is the ground pin for the clock generator. (35) v dd10 to v dd15 (power supply) these are the positive power supply pins for the internal cpu. (36) v dd30 to v dd37 (power supply) these are the positive power supply pins for the peripheral interface. (37) v ss10 to v ss15 (ground) these are the ground pins for the internal cpu. (38) v ss30 to v ss37 (ground) these are the ground pins for the peripheral interface.
70 chapter 2 pin functions user?s manual u16580ee2v0ud00 2.4 pin i/o circuits and recommended connection of unused pins table 2-4: i/o circuit types (1/3) terminal i/o circuit type recommended termination p00/nmi 2 connect independently to v ss3 via a resistor p01/intp0/eso0 p02/intp1/eso1 p03intp2/adtrg0 p04intp3/adtrg1 p10/tip00/tevtp1/top00 5-k input : connect independently to v dd3 or v ss3 via a resistor output: leave open p11/tip01/ttrgp1/top01 p12/tip10/ttrgp0/top10 p13/tip11/tevtp0/top11 p14/tip20/tevtp3/top20 p15/tip21/ttrgp3/top21 p16/tip30/ttrgp2/top30 p17/tip31/tevtp2/top31 p20/tip40/tevtp5/top40 p21/tip41/ttrgp5/top41 p22/tip50/ttrgp4/top50 p23/tip51/tevtp4/top51 p24/tip60/tevtp7/top60 p25/tip61/ttrgp7/top61 p26/tip70/ttrgp6/top70 p27/tip71/tevtp6/top71 p30/rxdc0/intp4 p31/txdc0 p32/rxdc1/intp5 p33/txdc1 p34/fcrxd0 p35/fctxd0 p36/fcrxd1 p37/fctxd1 p40/sib0 p41/sob0 p42/sckb0 p43/sib1 p44/sob1 p45/sckb1 p50/tor00 to p57/tor07
71 chapter 2 pin functions user?s manual u16580ee2v0ud00 p60/tor10/ttrgr1 5-k input: connect independently to v dd3 or v ss3 via a resistor output: leave open p61/tor11/tir10 p62/tor12/tir11 p63/tor13/tir12 p64/tor14/tir13 p65/tor15 p66/tor16 p67/tor17/tevtr1 p70/tit00/tevtt1 /tot00/tenct00 p71/tit01/ttrgt1/tot01/tenct01 p72/tecrt0/intp12 p73/tit10/ttrgt0/tot10/tenct10 p74/tit11/tevtt0 /tot11/tenct11 p75/tecrt1/afo p80/si30 p81/so30 p82/sck30 p83/scs300/intp6 p84/scs301/intp7 p85/scs302/intp8 p86/scs303/ssb0 p90/si31 p91/so31 p92/sck31 p93/scs310/intp9 p94/scs311/intp10 p95/scs312/intp11 p96/scs313/ssb1 p100/tclr1/ticc10/top80 p101/tcud1/ticc11 p102/tiud1/to1 pah0/a16 to pah5/a21 5 input: connect independently to v dd3 or v ss3 via a resistor output: leave open pal0/a0 to pal15/a15 pdh0/d16 to pdh15/d31 pdl0/d0 to pdl15/d15 pcs0/cs0 pcs1/cs1 pcs3/cs3 pcs4/cs4 pcd2/ben0 to pcd5/ben3 table 2-4: i/o circuit types (2/3) terminal i/o circuit type recommended termination
72 chapter 2 pin functions user?s manual u16580ee2v0ud00 pct4/rd 5 input: connect independently to v dd3 or v ss3 via a resistor output: leave open pct5/wr pcm0/wait pcm1 pcm6 pcm7 reset 2 pin must be used in the intended way x1 ? x2 ? mode0/flmd0 2 mode1/flmd1 2 mode2 2 dck 1 connect independently to v dd3 via a resistor drst 2-i leave open (on-chip pull-down resistor dms 1 connect independently to v dd3 via a resistor ddi ddo 3 leave open (always level output during reset) ani00 to ani09 7 connect independently to av dd or av ss via a resistor ani10 to ani19 av ref0 ? connect independently to av ss via a resistor av ref1 av dd ? pin must be used in the intended way av ss0 av ss1 v dd10 to v dd15 v ss10 to v ss15 v dd30 to v dd37 v ss30 to v ss37 cv dd cv ss table 2-4: i/o circuit types (3/3) terminal i/o circuit type recommended termination
73 chapter 2 pin functions user?s manual u16580ee2v0ud00 figure 2-1: pin i/o circuits p-ch n-ch in v dd type 1 type 5 type 2 type 5-k type 2-i type 7 type 3 schmitt trigger input with hysteresis characteristics in schmitt trigger input with hysteresis characteristics in p-ch n-ch out v dd v dd p-ch n-ch in/out data output disable input enable v dd p-ch n-ch in/out data output disable input enable p-ch n-ch in comparator (threshold voltage) v ref
74 chapter 2 pin functions user?s manual u16580ee2v0ud00 2.5 noise suppression the v850e/ph2 has a digital or analog delay circuits for noise suppression on all edge sensitive inputs. the digital delay circuit suppresses input pulses shorter than the internally generated edge detection signal to assure the hold time for these signals. the noise suppression is only effective on alternate pin functions, and it is not effective when the port input function is selected. table 2-5: noise suppression timing pin function noise removal time clock source nmi 4 to 5 clocks f xx /16 or f xx /64 (set by ncr0 bit of nrc register) intp0, intp1, eso0, eso1 analog delay (60ns to 200ns) intp2 to intp11, adtrg0, adtrg1 4 to 5 clocks f xx /16 or f xx /64 (set by ncr1 bit of nrc register) intp12, ticc00, ticc01, tclr0, tcud0, tiud0, tit00, tit01, tit10, tit11, tecrt0, tecrt1, tevtt0, tevtt1, ttrgt0, ttrgt1, tenct00, tenct01, tenct10, tenct11 4 to 5 clocks f xx /16 or f xx /64 (set by ncr2 bit of nrc register) tip00, tip01, tip10, tip11, tevtp0, tevtp1, ttrgp0, ttrgp1 4 to 5 clocks f xx /16 or f xx /64 (set by ncr3 bit of nrc register) tip20, tip21, tip30, tip31, tevtp2, tevtp3, ttrgp2, ttrgp3 4 to 5 clocks f xx /16 or f xx /64 (set by ncr4 bit of nrc register) tip40, tip41, tip50, tip51, tevtp4, tevtp5, ttrgp4, ttrgp5 4 to 5 clocks f xx /16 or f xx /64 (set by ncr5 bit of nrc register) tip60, tip61, tip70, tip71, tevtp6, tevtp7, ttrgp6, ttrgp7 4 to 5 clocks f xx /16 or f xx /64 (set by ncr6 bit of nrc register) tir10 to tir13, tevtr1, ttrgr1 4 to 5 clocks f xx /16 or f xx /64 (set by ncr7 bit of nrc register)
75 chapter 2 pin functions user?s manual u16580ee2v0ud00 (1) noise removal time control register (nrc) the nrc register specifies the noise removal clock setting for different edge sensitive inputs. this register can be read or written in 8-bit or 1-bit units. reset input clears this register to 00h. figure 2-2: noise removal time control register (1/2) after reset: 00h r/ w address: fffff7a0h 76543210 nrc ncr7 ncr6 ncr5 ncr4 ncr3 ncr2 ncr1 ncr0 ncr7 noise removal clock setting for input pins tir10 to tir13, tevtr1, ttrgr1 0f xx /16 1f xx /64 ncr6 noise removal clock setting for input pins tip60, tip61, tip70, tip71, tevtp6, tevtp7, ttrgp6, ttrgp7 0f xx /16 1f xx /64 ncr5 noise removal clock setting for input pins tip40, tip41, tip50, tip51, tevtp4, tevtp5, ttrgp4, ttrgp5 0f xx /16 1f xx /64 ncr4 noise removal clock setting for input pins tip20, tip21, tip30, tip31, tevtp2, tevtp3, ttrgp2, ttrgp3 0f xx /16 1f xx /64 ncr3 noise removal clock setting for input pins tip00, tip01, tip10, tip11, tevtp0, tevtp1, ttrgp0, ttrgp1 0f xx /16 1f xx /64 ncr2 noise removal clock setting for input pins intp12, ticc00, ticc01, tclr0, tcud0, tiud0, tit00, ti t01, tit10, tit11, te crt0, tecrt1, tevtt0, tevtt1, ttrgt0, ttrgt1, tenct00, tenct01, tenct10, tenct11 0f xx /16 1f xx /64
76 chapter 2 pin functions user?s manual u16580ee2v0ud00 figure 2-2: noise removal time control register (2/2) ncr1 noise removal clock setting for input pins intp2 to intp11, adtrg0, adtrg1 0f xx /16 1f xx /64 ncr0 noise removal clock setting for nmi input pin 0f xx /16 1f xx /64
77 user?s manual u16580ee2v0ud00 chapter 3 cpu functions the cpu of the v850e/ph2 microcontroller is based on the risc architecture and executes most instructions in one clock cycle by using a 5-stage pipeline control. 3.1 features ? number of instructions: 96 ? minimum instruction execution time: 15.6 ns (@ 64 mhz operation) ? memory space program space: 64 mb linear data space: 4 gb linear ? general-purpose registers: 32 bits 32 ? internal 32-bit architecture ? 5-stage pipeline control ? multiply/divide instructions (32 bits 32 bits 64 bits in 1 to 2 clocks) ? saturated operation instructions ? floating point arithmetic unit (single precision, 32 bits, ieee754-85 standard) ? 32-bit shift instruction: 1 clock ? load/store instruction with long/short format ? four types of bit manipulation instructions - set1 - clr1 -not1 -tst1
78 chapter 3 cpu functions user?s manual u16580ee2v0ud00 3.2 cpu register set the cpu registers of the v850e/ph2 can be classified into three categories: a general-purpose pro- gram register set, a dedicated system register set and a dedicated floating point arithmetic register set. all the registers have 32-bit width. in addition, the v850e/ph2 contains special system control registers that should be initialized before cpu operation, and a specific register controlling its clock. for detailed description of v850e1 core, refer to v850e1 core architecture manual and the addendum for floating point arithmetic. figure 3-1: cpu register set r2 r6 r7 r8 r9 r10 r11 r12 r13 r14 r15 r16 r17 r18 r19 r20 r21 r22 r23 r24 r25 r26 r27 r28 r29 r0 (zero register) r1 (assembler-reserved register) r3 (stack pointer (sp)) r4 (global pointer (gp)) r5 (text pointer (tp)) r30 (element pointer (ep)) r31 (link pointer (lp)) pc (program counter) psw (program status word) ecr (interrrupt source register) fepc fepsw (status saving register during nmi) (status saving register during nmi) eipc eipsw (status saving register during interrupt) efg (flag register) ect (control register) (status saving register during interrupt) 31 0 31 0 31 0 31 0 ctbp (callt base pointer) dbpc dbpsw (status saving register during exception/debug trap) (status saving register during exception/debug trap) ctpc ctpsw (status saving register during callt execution) (status saving register during callt execution) (1) program register set (2) system register set (3) floating point arithmetic register set
79 chapter 3 cpu functions user?s manual u16580ee2v0ud00 3.2.1 program register set the program register set includes general-purpose registers and a program counter. (1) general-purpose registers (r0 to r31) thirty-two general-purpose registers, r0 to r31, are available. all of these registers can be used as a data variable or address variable. however, r0 and r30 are implicitly used by instructions and care must be exercised when using these registers. r0 always holds 0 and is used for operations that use 0 or offset 0 addressing. r30 is used as a base pointer when performing memory access with the sld and sst short instructions. also, r1, r3 to r5, and r31 are implicitly used by the assembler and c compiler. therefore, before using these registers, their contents must be saved so that they are not lost, and they must be restored to the registers after use. there are cases when r2 is used by the real-time os. if r2 is not used by the real-time os, r2 can be used as a variable register. (2) program counter (pc) this register holds the address of the instruction under execution. the lower 26 bits of this register are valid, and bits 31 to 26 are fixed to 0. if a carry occurs from bit 25 to bit 26, it is ignored. bit 0 is fixed to 0, and branching to an odd address cannot be performed. figure 3-2: program counter (pc) table 3-1: program registers name usage operation r0 zero register always holds 0 r1 assembler-reserved register working register for generating 32-bit immediate r2 address/data variable register (when r2 is not used by the real-time os to be used) r3 stack pointer used to generate stack frame when function is called r4 global pointer used to access global variable in data area r5 text pointer register to indi cate the start of the text ar ea (area for placing program code) r6 to r29 address/data variable register r30 element pointer base pointer when memory is accessed r31 link pointer used by compiler when calling function 31 26 25 10 after reset 00000000h pc fixed to 0 instruction address under execution 0
80 chapter 3 cpu functions user?s manual u16580ee2v0ud00 3.2.2 system register set system registers control the status of the cpu and hold interrupt information. read from and write to system registers are performed by setting the system register numbers shown below with the system register load/store instructions (ldsr, stsr instructions). notes: 1. since only one set of registers is available, the contents of these registers must be saved by the program when multiple interrupt servicing is enabled. 2. since only one set of registers is available, the contents of these registers must be saved by the program when callt instructions nesting is used. caution: even if bit 0 of eipc, fepc, or ctpc is set to (1) by the ldsr instruction, bit 0 is ignored during return with the reti instruction following interrupt servicing (because bit 0 of pc is fixed to 0). if setting a value to eipc, fepc, and ctpc, set an even number (bit 0 = 0). table 3-2: system register numbers system register operand specification enabled for instruction no. name function ldsr stsr 0eipc pc value at interrupt handler entry note 1 ye s ye s 1 eipsw psw value at interrupt handler entry note 1 ye s ye s 2 fepc pc value at nmi handler entry yes yes 3 fepsw psw value at nmi handler entry yes yes 4 ecr exception cause register no yes 5 psw program status word yes yes 6 to 15 - reserved numbers for future function expansion (the operation is not guaranteed if accessed.) no no 16 ctpc pc value at callt subroutine entry note 2 ye s ye s 17 ctpsw psw value at callt subroutine entry note 2 ye s ye s 18 dbpc pc value at exception/debug trap entry yes yes 19 dbpsw psw value at except ion/debug trap entry yes yes 20 ctbp callt base pointer yes yes 21 to 31 - reserved numbers for future function expansion (the operation is not guaranteed if accessed.) no no
81 chapter 3 cpu functions user?s manual u16580ee2v0ud00 (1) interrupt status saving registers (eipc, eipsw) there are two context saving registers, eipc and eipsw. upon occurrence of a software exception or a maskable interrupt, the content of the program counter (pc) is saved to eipc and the content of the program status word (psw) is saved to eipsw (upon occurrence of a non-maskable interrupt (nmi), the contents are saved to the nmi status saving registers (fepc, fepsw)). the address of the next instruction following the instruction executed when a software exception or maskable interrupt occurs is saved to eipc, except for the divh instruction (see chapter 7 ?interrupt/exception processing function? on page 207). since there is only one set of interrupt status savi ng registers, the contents of these registers must be saved by the program when multip le interrupt servic ing is enabled. bits 31 to 26 of eipc and bits 31 to 8 of eipsw are reserved (fixed to 0) for future function expansion. figure 3-3: interrupt status saving registers (eipc, eipsw) the values of eipc and eipsw are restored to pc and psw during execution of a reti instruction. 31 26 25 0 after reset 0xxxxxxxh (x: undefined) eipc 000000 (pc contents) 31 87 0 after reset 000000xxh (x: undefined) eipsw 000000000000000000000000 (psw contents)
82 chapter 3 cpu functions user?s manual u16580ee2v0ud00 (2) nmi status saving registers (fepc, fepsw) there are two nmi stat us saving registers, fepc and fepsw. upon occurrence of a non-maskable interrupt (nmi), the content of the program counter (pc) is saved to fepc and the conten t of the program status word (psw) is saved to fepsw. the address of the next instruction following the instruction executed when a non-maskable interrupt occurs is saved to fepc, except for the divh instruction. bits 31 to 26 of fepc and bits 31 to 8 of fepsw are reserved (fixed to 0) for future function expansion. figure 3-4: nmi status saving registers (fepc, fepsw) the values of fepc and fepsw are restored to pc and psw during execution of a reti instruction. (3) exception cause register (ecr) upon occurrence of an interrupt or an exception, the exception cause register (ecr) holds the source of the interrupt or the exception. the value held by ecr is an exception code, coded for each interrupt source. this register is a read-only register, and thus data cannot be written to it using the ldsr instruction. figure 3-5: interrupt source register (ecr) the list of exception codes is tabulated in table 7-1, ?interrupt/exception source list,? on page 207 . 31 26 25 0 after reset 0xxxxxxxh (x: undefined) fepc 000000 (pc contents) 31 87 0 after reset 000000xxh (x: undefined) fepsw 000000000000000000000000 (psw contents) 31 16 15 0 after reset 00000000h ecr fecc eicc bit position bit name description 31 to 16 fecc non-maskable interrupt (nmi) exception code 15 to 0 eicc exception, maskable interrupt exception code
83 chapter 3 cpu functions user?s manual u16580ee2v0ud00 (4) program status word (psw) the program status word (psw) is a collection of flags that indicate the program status (instruction execution result) and the cpu status. when the contents of this register are changed using the ldsr instruction, the new contents become valid immediately following completion of the ldsr instruction execution. however, if the id flag is set to 1, interrupt request acknowledgement during ldsr instruction execution is prohibited. bits 31 to 8 are reserved (fixed to 0) for future function expansion. figure 3-6: program status word (psw) note: during saturated operation, the saturated operation results are determined by the contents of the ov flag and s flag. the sat flag is set to 1 only when the ov flag is set to 1 during saturated operation. this is explained on the following table. 31 2625 8765 4 3210 after reset 00000020h psw rfu np ep id sat cy ov s z bit position bit name description 31 to 8 rfu reserved field. fixed to 0. 7 np indicates that non-maskable interrupt (nmi) servicing is in progress. this flag is set to 1 when a nmi request is acknowledged, and disables multiple interrupts. 0: nmi servicing not in progress 1: nmi servicing in progress 6 ep indicates that exception processing is in progress. this flag is set to 1 when an exception occurs. moreover, interrupt requests can be acknowledged even when this bit is set. 0: exception processing not in progress 1: exception processing in progress 5 id indicates whether maskable interrupt request acknowledgment is enabled. 0: interrupt enabled 1: interrupt disabled 4 sat note indicates that the result of executing a saturated operation instruction has overflowed and that the calculation result is saturated. si nce this is a cumulative flag, it is set to 1 when the result of a saturated operation inst ruction becomes saturated, and it is not cleared to 0 even if the operation results of successive instructions do not become saturated. this flag is neither set nor cl eared when arithmetic operation instructions are executed. 0: not saturated 1: saturated 3 cy indicates whether carry or borrow o ccurred as the result of an operation. 0: no carry or borrow occurred 1: carry or borrow occurred 2 ov note indicates whether overflow occurred during an operation. 0: no overflow occurred 1: overflow occurred. 1 s note indicates whether the result of an operation is negative. 0: operation result is positive or 0. 1: operation result is negative. 0 z indicates whether operation result is 0. 0: operation result is not 0. 1: operation result is 0.
84 chapter 3 cpu functions user?s manual u16580ee2v0ud00 table 3-3: saturated operation results (5) callt execution status saving registers (ctpc, ctpsw) there are two callt execution status saving registers, ctpc and ctpsw. when the callt instruction is executed, the contents of the program counter (pc) are saved to ctpc, and the program status word (psw) contents are saved to ctpsw. the contents saved to ctpc consist of the address of the next instruction after the callt instruction. bits 31 to 26 ctpc and bits 31 to 8 of ctpsw are reserved (fixed to 0) for future function expansion. figure 3-7: callt execution status saving registers (ctpc, ctpsw) the values of ctpc and ctpsw are restored to pc and psw during execution of the ctret instruction. operation result status flag status saturated operation result sat ov s maximum positive value exceeded 1 1 0 7fffffffh maximum negative value exceeded 1 1 1 80000000h positive (maximum value not exceeded) holds value before operation 0 0 actual operation result negative (maximum value not exceeded) 1 31 26 25 0 after reset 0xxxxxxxh (x: undefined) ctpc 000000 (pc contents) 31 87 0 after reset 000000xxh (x: undefined) ctpsw 000000000000000000000000 (psw contents)
85 chapter 3 cpu functions user?s manual u16580ee2v0ud00 (6) exception/debug trap status saving registers (dbpc, dbpsw) there are two exception/debu g trap status saving registers, dbpc and dbpsw. upon occurrence of an exception trap or debug trap, the contents of the program counter (pc) are saved to dbpc, and the program status wo rd (psw) contents are saved to dbpsw. the contents saved to dbpc consist of the address of the next instruction after the instruction executed when an exception trap or debug trap occurs. bits 31 to 26 of dbpc and bits 31 to 8 of dbpsw are reserved (fixed to 0) for future function expansion. figure 3-8: exception/debug trap status saving registers (dbpc, dbpsw) the values of dbpc and dbpsw are restored to pc and psw during execution of the dbret instruction. (7) callt base pointer (ctbp) the callt base pointer (ctbp) is used to specify callt table start address and generate target addresses (bit 0 is fixed to 0). bits 31 to 26 are reserved (fixed to 0) for future function expansion. figure 3-9: callt base pointer (ctbp) 31 26 25 0 after reset 0xxxxxxxh (x: undefined) dbpc 000000 (pc contents) 31 87 0 after reset 000000xxh (x: undefined) dbpsw 000000000000000000000000 (psw contents) 31 26 25 10 after reset 0xxxxxxxh (x: undefined) ctbp 000000 (base address) 0
86 chapter 3 cpu functions user?s manual u16580ee2v0ud00 3.2.3 floating point arithmetic unit register set the floating point arithmetic unit is provided with one flag register and one control register. (1) floating point arithmetic control register (ect) this register is used for controlling the setting conditions of the tr flag: tr is a logical or between all the invalid operations the fpu can detect and each bit of ect is a mask bit for each condition. figure 3-10: floating point arithmetic control register (ect) table 3-4: floating point arithmetic unit registers name usage operation ect control register sets the operation of the efg register efg flag register holds the status of the fpu 31 1312111098765 4 3210 after reset 00000000h ect rfu itztvtutpt000 0 000 0 bit position bit name description 31 to 13 rfu reserved field. fixed to 0. 12 it enables invalid operation detection in the tr value calculation 0: iv is set when an invalid operation is detected 1: iv and tr are set when an invalid operation is detected 11 zt enables zero divide operation detection in the tr value calculation 0: zd is set when a zero divide operation is detected 1: zd and tr are set when a zero divide operation is detected 10 vt enables overflow detection in the tr value calculation 0: vf is set when an overflow is detected 1: vf and tr are set when an overflow is detected 9 ut enables underflow detection in the tr value calculation 0: ud is set when an underflow is detected 1: ud and tr are set when an underflow is detected 8 pt enables accuracy fail detection in the tr value calculation 0: pr is set when an accuracy fail is detected 1: pr and tr are set when an accuracy fail is detected 7 to 0 0 reserved field. fixed to 0.
87 chapter 3 cpu functions user?s manual u16580ee2v0ud00 (2) floating point arithmetic status register (efg) figure 3-11: floating point arithmetic status register (efg) 31 141312111098765 4 3210 after reset 00000000h efg rfu ro iv zd vf ud pr 0 0 0 tr 0 ov s z bit position bit name description 31 to 14 rfu reserved field. fixed to 0. 13 ro running operation: indicates whether the floating point arithmetic unit is running 0: operation in progress 1: fpu idle 12 iv invalid operation: indicates that an invalid operation has been requested. 0: normal operation 1: invalid operation detected 11 zd zero divide: indicates whether a division by 0 has been detected. 0: normal operation 1: division by 0 detected 10 vf overflow: indicates that the result of executing a floating point operation has overflowed. 0: no overflow generated 1: overflow generated 9 ud undervalue: indicates that the result of executing a floating point operation has underflowed. 0: no underflow generated 1: underflow generated 8 pr precision error: indicates t hat an accuracy failure occurred. 0: no accuracy failure occurred 1: accuracy failure occurred 7 to 5 0 reserved field. fixed to 0. 4 tr this flag summarizes the state of the fpu: 0: normal state 1: abnormal condition detected: one of the bits 13 to 8 is set. the setting conditions of this flag depends on the ect register value. 3 0 reserved field. fixed to 0. 2 ov indicates whether an overflow occurred during floating point to integer conversion 0: no overflow generated 1: overflow generated 1 s indicates whether floating point operation result is negative. 0: operation result is not negative. 1: operation result is negative. 0 z indicates whether floating point operation result is 0. 0: operation result is not 0. 1: operation result is 0.
88 chapter 3 cpu functions user?s manual u16580ee2v0ud00 3.3 operating modes the v850e/ph2 has the following operating modes. 3.3.1 operating modes outline (1) normal operating mode (a) single-chip modes 0, 1 access to the internal rom is enabled. in single-chip mode 0, after the system reset is released, each pin related to the bus interface enters the port mode, program execution branches to the reset entry address of the internal rom, and instruction processing starts. by sett ing the pmcdh, pmcdl, pmccs, pmcct, and pmccm registers to control mode by instruction, an external device can be connected to the external mem- ory area. in single-chip mode 1, after the system reset is released, each pin related to the bus interface enters the control mode, program execution branches to the external device?s (memory) reset entry address, and instruction processing starts. the internal rom area is mapped from address 100000h. (b) rom-less mode after the system reset is released, each pin related to the bus interface enters the control mode, program execution branches to the external device?s (memory) reset entry address, and instruction processing starts. fetching of instructions and data access for internal rom becomes impossible. in rom-less mode the data bus width is 32 bits. (2) flash memory programming mode in this mode the internal flash memory can be written or erased with an external flash writer, using the csib0 or uartc0 as serial interface. 3.3.2 operation mode specification the operation mode is specified according to the status of pins mode0 to mode2. in an application system fix the specification of these pins and do not change them during operation. operation is not guaranteed if these pins are changed during operation. remark: l: low-level input h: high-level input mode2 mode1 mode0 mode remark l l l single chip mode 0 internal rom area is allocated from address 00000000h. l l h flash memory programming mode csib0/iuartc0 selected by mode0 pin toggling. l h l rom-less mode external 32-bit data bus l h h single chip mode 1 internal rom area is allocated from address 00100000h. external 32-bit data bus other value than above setting prohibited
89 chapter 3 cpu functions user?s manual u16580ee2v0ud00 3.4 address space 3.4.1 cpu address space the cpu of the v850e/ph2 uses a 32-bit architecture and supports up to 4 gb of linear address space (data space) during operand addressing (data acce ss). when addressing instructions, a linear address space (program space) of up to 64 mb is supported. however, both the program and data spaces include areas whose use is prohibited. for details, refer to figure 3-13, ?address space image,? on page 90. figure 3-12 shows the cpu address space. figure 3-12: cpu address space ffffffffh 04000000h 03ffffffh 00000000h data area (4 gb linear) program area (64 mb linear) cpu address space
90 chapter 3 cpu functions user?s manual u16580ee2v0ud00 3.4.2 images when addressing an instruction address, up to 64 mb of linear address space (program space) and internal ram area are supported. for operand addressing (data access), up to 4 gb of linear address space (data area) is supported. on this 4 gb address space, however, 256 mb physi cal address spaces can be seen as an image. therefore, whatever the values of bits 31 to 29 of an address may be, a physical address space of the same 256 mb is accessed. figure 3-13: address space image ffffffffh f0000000h efffffffh 00000000h internal rom image image image internal ram peripheral i/o external memory physical address space fffffffh 0000000h image image e0000000h dfffffffh 20000000h 1fffffffh 10000000h 0fffffffh cpu address space
91 chapter 3 cpu functions user?s manual u16580ee2v0ud00 3.4.3 wrap-around of cpu address space (1) program space of the 32 bits of the program counter (pc), the higher 6 bits are fixed to 0 and only the lower 26 bits are valid. even if a carry or borrow occurs from bit 25 to bit 26 as a result of branch address calculation, the higher 6 bits ignore this and remain 0. therefore, the lower-limit address of the program space, 00000000h, and the upper-limit address, 03ffffffh, are contiguous addresses, and the program space is wrapped around at the boundary of these addresses. caution: no instructions can be fetched from the 4 kb area of 03fff000h to 03ffffffh because this area is a peripheral i/o area. therefore, do not execute any branch operation instructions in which the destination address will reside in any part of this area. figure 3-14: program space (2) data space the result of an operand address calculation that exceeds 32 bits is truncated to 32 bits. therefore, the lower-limit address of the data space, address 00000000h, and the upper-limit address, ffffffffh, are contiguous addresses, and the data space is wrapped around at the boundary of these addresses. figure 3-15: data space 03fffffeh 03ffffffh 00000000h 00000001h program space program space (+) direction (?) direction fffffffeh ffffffffh 00000000h 00000001h data space data space (+) direction (?) direction
92 chapter 3 cpu functions user?s manual u16580ee2v0ud00 3.4.4 memory map areas are reserved in v850e/ph2 as shown in figure 3-16. each mode is specified by the mode0 to mode2 pins. figure 3-16: memory map notes: 1. by setting the pmcal, pmcah, pmcdl, pmcdh, pmccs, pmcct, and pmccd port mode control registers to control mode, this area can be used as external memory area. 2. accessing addresses 3fff000h to 3ffffffh is prohibited. specify addresses ffff000h to fffffffh to access the on-chip peripheral i/o. 3. the operation is not guaranteed if an access-prohibited area is accessed. xfffffffh on-chip peripheral i/o area internal ram area on-chip peripheral i/o area internal ram area on-chip peripheral i/o area internal ram area access prohibited note 1 external memory area internal rom area external memory area internal rom area external memory area single-chip mode 0 single-chip mode 1 romless mode program area (64 mb) 1 mb 1 mb 4 kb x0200000h x01fffffh x0100000h x00fffffh x0000000h 32 kb xffff000h xfffefffh xfff0000h xffeffffh on-chip peripheral i/o area mirror note 2 x3ff0000h x3feffffh access prohibited note 3 xfff8000h xfff7fffh x3ff8000h x3ff7fffh internal ram area mirror x3fff000h x3ffefffh x4000000h x3ffffffh access prohibited note 2 on-chip peripheral i/o area mirror note 2 access prohibited note 3 internal ram area mirror on-chip peripheral i/o area mirror note 2 access prohibited note 3 internal ram area mirror access prohibited note 1 access prohibited note 1 access prohibited note 1
93 chapter 3 cpu functions user?s manual u16580ee2v0ud00 3.4.5 areas (1) internal rom area (a) memory map 1 mb of internal rom area, addresses 00000h to fffffh, is reserved. 512 kb are provided at addresses 000000h to 07ffffh as physical internal rom (flash memory). up to 1 mb of internal rom/internal flash memory area is reserved. 512 kb are provided in the following addresses as physical internal rom (flash memory). ? in single-chip mode 0: addresses 000000h to 07ffffh (addresses 080000h to 0fffffh are undefined) ? in single-chip mode 1: addresses 0100000h to 017ffffh (addresses 0180000h to 01fffffh are undefined) figure 3-17: internal rom / internal flash memory area (b) interrupt/exception table the v850e/ph2 increases the interrupt response speed by assigning handler addresses corre- sponding to each interrupt/exception. this group of handler addresses is called an interrupt/exception table. this table is located in the internal rom area. when an interrupt/exception request is acknowledged, execution jumps to the handler address and the program written in that memory is executed. for detailed list of the interrupt/exception sources and the corresponding handler addresses, please refer to table 7-1, ?interrupt/exception source list,? on page 207 . (2) internal ram area an area of 60 kb from fff0000h to fffefffh is reserved for the internal ram area. 32 kb are provided at addresses fff0000h to fff7fffh as physical internal ram. the 32 kb area of 3ff0000h to 3ff7fffh can be seen as an image of fff0000h to fff7fffh. undefined undefined internal flash memory area internal flash memory area single-chip mode 0 single-chip mode 1 0fffffh 080000h 000000h 07ffffh 1fffffh 180000h 100000h 17ffffh
94 chapter 3 cpu functions user?s manual u16580ee2v0ud00 (3) on-chip peripheral i/o area (sfr area) a 4 kb area from ffff000h to fffffffh is provided as the on-chip peripheral i/o area. an image of addresses ffff000h to fffffffh can be seen at addresses 3fff000h to 3ffffffh note . note: addresses 3fff000h to 3ffffffh are access-proh ibited. to access the on-chip peripheral i/o, specify addresses ffff000h to fffffffh. figure 3-18: on-chip peripheral i/o area peripheral i/o registers assigned with functions such as on-chip peripheral i/o operation mode specification and state monitoring are mapped to the on-chip peripheral i/o area. program fetches are not allowed in this area. cautions: 1. for registers in which byte access is possible, if half-word access is executed, the higher 8 bits become undefined during a read operation, and the lower 8 bits of data are written to the register during a write operation. do not access an 8-bit register in half-word units. 2. addresses that are not defined as registers are reserved for future expansion. if these addresses are accessed, the operation is undefined and not guaranteed. fffffffh ffff000h on-chip peripheral i/o area (4 kb)
95 chapter 3 cpu functions user?s manual u16580ee2v0ud00 3.4.6 peripheral i/o registers list . table 3-5: peripheral i/o registers (1/14) address symbol function register name r/w bit units for manipulation reset 181632 fffff000h pal port register al r/w 0000h fffff000h pall port register all r/w 00h fffff001h palh port register alh r/w 00h fffff002h pah port register ah r/w 00h fffff004h pdl port register dl r/w 0000h fffff004h pdll port register dll r/w 00h fffff005h pdlh port register dlh r/w 00h fffff006h pdh port register dh r/w 0000h fffff006h pdhl port register dhl r/w 00h fffff007h pdhh port register dhh r/w 00h fffff008h pcs port register cs r/w 00h fffff00ah pct port register ct r/w 00h fffff00ch pcm port register cm r/w 00h fffff00eh pcd port register cd r/w 00h fffff020h pmal port mode register al r/w ffffh fffff020h pmall port mode register all r/w ffh fffff021h pmalh port mode register alh r/w ffh fffff022h pmah port mode register ah r/w ffh fffff024h pmdl port mode register dl r/w ffffh fffff024h pmdll port mode register dll r/w ffh fffff025h pmdlh port mode register dlh r/w ffh fffff026h pmdh port mode register dh r/w ffffh fffff026h pmdhl port mode register dhl r/w ffh fffff027h pmdhh port mode register dhh r/w ffh fffff028h pmcs port mode register cs r/w ffh fffff02ah pmct port mode register ct r/w ffh fffff02ch pmcm port mode register cm r/w ffh fffff02eh pmcd port mode register cd r/w ffh fffff040h pmcal port mode control register al r/w 0000h fffff040h pmcall port mode control register all r/w 00h fffff041h pmcalh port mode control register alh r/w 00h fffff042h pmcah port mode control register ah r/w 00h fffff044h pmcdl port mode control register dl r/w 0000h fffff044h pmcdll port mode control register dll r/w 00h fffff045h pmcdlh port mode control register dlh r/w 00h fffff046h pmcdh port mode control register dh r/w 0000h fffff046h pmcdhl port mode control register dhl r/w 00h fffff047h pmcdhh port mode control register dhh r/w 00h
96 chapter 3 cpu functions user?s manual u16580ee2v0ud00 fffff048h pmccs port mode control register cs r/w 00h fffff04ah pmcct port mode control register ct r/w 00h fffff04ch pmccm port mode control register cm r/w 00h fffff04eh pmccd port mode control register cd r/w 00h fffff060h csc0 chip area select control register 0 r/w 2c11h fffff062h csc1 chip area select control register 1 r/w 2c11h fffff064h bpc peripheral area select control register r/w 0fffh fffff066h bsc bus size configuration register r/w aaaah fffff068h bec endian configuration register r/w 0000h fffff06eh vswc system wait control register r/w 77h fffff100h imr0 interrupt mask register 0 r/w ffffh fffff100h imr0l interrupt mask register 0l r/w ffh fffff101h imr0h interrupt mask register 0h r/w ffh fffff102h imr1 interrupt mask register 1 r/w ffffh fffff102h imr1l interrupt mask register 1l r/w ffh fffff103h imr1h interrupt mask register 1h r/w ffh fffff104h imr2 interrupt mask register 2 r/w ffffh fffff104h imr2l interrupt mask register 2l r/w ffh fffff105h imr2h interrupt mask register 2h r/w ffh fffff106h imr3 interrupt mask register 3 r/w ffffh fffff106h imr3l interrupt mask register 3l r/w ffh fffff107h imr3h interrupt mask register 3h r/w ffh fffff108h imr4 interrupt mask register 4 r/w ffffh fffff108h imr4l interrupt mask register 4l r/w ffh fffff109h imr4h interrupt mask register 4h r/w ffh fffff10ah imr5 interrupt mask register 5 r/w ffffh fffff10ah imr5l interrupt mask register 5l r/w ffh fffff10bh imr5h interrupt mask register 5h r/w ffh fffff10ch imr6 interrupt mask register 6 r/w ffffh fffff10ch imr6l interrupt mask register 6l r/w ffh fffff10dh imr6h interrupt mask register 6h r/w ffh fffff10eh imr7 interrupt mask register 7 r/w ffffh fffff10eh imr7l interrupt mask register 7l r/w ffh fffff10fh imr7h interrupt mask register 7h r/w ffh fffff110h pic0 interrupt control register 0 r/w 47h fffff112h pic1 interrupt control register 1 r/w 47h fffff114h pic2 interrupt control register 2 r/w 47h fffff116h pic3 interrupt control register 3 r/w 47h fffff118h pic4 interrupt control register 4 r/w 47h fffff11ah pic5 interrupt control register 5 r/w 47h table 3-5: peripheral i/o registers (2/14) address symbol function register name r/w bit units for manipulation reset 1 8 16 32
97 chapter 3 cpu functions user?s manual u16580ee2v0ud00 fffff11ch pic6 interrupt control register 6 r/w 47h fffff11eh pic7 interrupt control register 7 r/w 47h fffff120h pic8 interrupt control register 8 r/w 47h fffff122h pic9 interrupt control register 9 r/w 47h fffff124h pic10 interrupt control register 10 r/w 47h fffff126h pic11 interrupt control register 11 r/w 47h fffff128h pic12 interrupt control register 12 r/w 47h fffff12ah pic13 interrupt control register 13 r/w 47h fffff12ch pic14 interrupt control register 14 r/w 47h fffff12eh pic15 interrupt control register 15 r/w 47h fffff130h pic16 interrupt control register 16 r/w 47h fffff132h pic17 interrupt control register 17 r/w 47h fffff134h pic18 interrupt control register 18 r/w 47h fffff136h pic19 interrupt control register 19 r/w 47h fffff138h pic20 interrupt control register 20 r/w 47h fffff13ah pic21 interrupt control register 21 r/w 47h fffff13ch pic22 interrupt control register 22 r/w 47h fffff13eh pic23 interrupt control register 23 r/w 47h fffff140h pic24 interrupt control register 24 r/w 47h fffff142h pic25 interrupt control register 25 r/w 47h fffff144h pic26 interrupt control register 26 r/w 47h fffff146h pic27 interrupt control register 27 r/w 47h fffff148h pic28 interrupt control register 28 r/w 47h fffff14ah pic29 interrupt control register 29 r/w 47h fffff14ch pic30 interrupt control register 30 r/w 47h fffff14eh pic31 interrupt control register 31 r/w 47h fffff150h pic32 interrupt control register 32 r/w 47h fffff152h pic33 interrupt control register 33 r/w 47h fffff154h pic34 interrupt control register 34 r/w 47h fffff156h pic35 interrupt control register 35 r/w 47h fffff158h pic36 interrupt control register 36 r/w 47h fffff15ah pic37 interrupt control register 37 r/w 47h fffff15ch pic38 interrupt control register 38 r/w 47h fffff15eh pic39 interrupt control register 39 r/w 47h fffff160h pic40 interrupt control register 40 r/w 47h fffff162h pic41 interrupt control register 41 r/w 47h fffff164h pic42 interrupt control register 42 r/w 47h fffff166h pic43 interrupt control register 43 r/w 47h fffff168h pic44 interrupt control register 44 r/w 47h fffff16ah pic45 interrupt control register 45 r/w 47h table 3-5: peripheral i/o registers (3/14) address symbol function register name r/w bit units for manipulation reset 181632
98 chapter 3 cpu functions user?s manual u16580ee2v0ud00 fffff16ch pic46 interrupt control register 46 r/w 47h fffff16eh pic47 interrupt control register 47 r/w 47h fffff170h pic48 interrupt control register 48 r/w 47h fffff172h pic49 interrupt control register 49 r/w 47h fffff174h pic50 interrupt control register 50 r/w 47h fffff176h pic51 interrupt control register 51 r/w 47h fffff178h pic52 interrupt control register 52 r/w 47h fffff17ah pic53 interrupt control register 53 r/w 47h fffff17ch pic54 interrupt control register 54 r/w 47h fffff17eh pic55 interrupt control register 55 r/w 47h fffff180h pic56 interrupt control register 56 r/w 47h fffff182h pic57 interrupt control register 57 r/w 47h fffff184h pic58 interrupt control register 58 r/w 47h fffff186h pic59 interrupt control register 59 r/w 47h fffff188h pic60 interrupt control register 60 r/w 47h fffff18ah pic61 interrupt control register 61 r/w 47h fffff18ch pic62 interrupt control register 62 r/w 47h fffff18eh pic63 interrupt control register 63 r/w 47h fffff190h pic64 interrupt control register 64 r/w 47h fffff192h pic65 interrupt control register 65 r/w 47h fffff194h pic66 interrupt control register 66 r/w 47h fffff196h pic67 interrupt control register 67 r/w 47h fffff198h pic68 interrupt control register 68 r/w 47h fffff19ah pic69 interrupt control register 69 r/w 47h fffff19ch pic70 interrupt control register 70 r/w 47h fffff19eh pic71 interrupt control register 71 r/w 47h fffff1a0h pic72 interrupt control register 72 r/w 47h fffff1a2h pic73 interrupt control register 73 r/w 47h fffff1a4h pic74 interrupt control register 74 r/w 47h fffff1a6h pic75 interrupt control register 75 r/w 47h fffff1a8h pic76 interrupt control register 76 r/w 47h fffff1aah pic77 interrupt control register 77 r/w 47h fffff1ach pic78 interrupt control register 78 r/w 47h fffff1aeh pic79 interrupt control register 79 r/w 47h fffff1b0h pic80 interrupt control register 80 r/w 47h fffff1b2h pic81 interrupt control register 81 r/w 47h fffff1b4h pic82 interrupt control register 82 r/w 47h fffff1b6h pic83 interrupt control register 83 r/w 47h fffff1b8h pic84 interrupt control register 84 r/w 47h fffff1bah pic85 interrupt control register 85 r/w 47h table 3-5: peripheral i/o registers (4/14) address symbol function register name r/w bit units for manipulation reset 1 8 16 32
99 chapter 3 cpu functions user?s manual u16580ee2v0ud00 fffff1bch pic86 interrupt control register 86 r/w 47h fffff1beh pic87 interrupt control register 87 r/w 47h fffff1c0h pic88 interrupt control register 88 r/w 47h fffff1c2h pic89 interrupt control register 89 r/w 47h fffff1c4h pic90 interrupt control register 90 r/w 47h fffff1c6h pic91 interrupt control register 91 r/w 47h fffff1c8h pic92 interrupt control register 92 r/w 47h fffff1cah pic93 interrupt control register 93 r/w 47h fffff1cch pic94 interrupt control register 94 r/w 47h fffff1ceh pic95 interrupt control register 95 r/w 47h fffff1d0h pic96 interrupt control register 96 r/w 47h fffff1d2h pic97 interrupt control register 97 r/w 47h fffff1d4h pic98 interrupt control register 98 r/w 47h fffff1d6h pic99 interrupt control register 99 r/w 47h fffff1d8h pic100 interrupt control register 100 r/w 47h fffff1dah pic101 interrupt control register 101 r/w 47h fffff1dch pic102 interrupt control register 102 r/w 47h fffff1deh pic103 interrupt control register 103 r/w 47h fffff1e0h pic104 interrupt control register 104 r/w 47h fffff1e2h pic105 interrupt control register 105 r/w 47h fffff1fah ispr interrupt service priority register r 00h fffff1fch prcmd command register w undefined fffff200h adm00 a/d converter 0 mode register 0 r/w 00h fffff201h adm01 a/d converter 0 mode register 1 r/w 00h fffff202h adm02 a/d converter 0 mode register 2 r/w 00h fffff210h adcr00 a/d conversion result register 00 r undefined fffff211h adcr00h a/d conversion result register 00h r undefined fffff212h adcr01 a/d conversion result register 01 r undefined fffff213h adcr01h a/d conversion result register 01h r undefined fffff214h adcr02 a/d conversion result register 02 r undefined fffff215h adcr02h a/d conversion result register 02h r undefined fffff216h adcr03 a/d conversion result register 03 r undefined fffff217h adcr03h a/d conversion result register 03h r undefined fffff218h adcr04 a/d conversion result register 04 r undefined fffff219h adcr04h a/d conversion result register 04h r undefined fffff21ah adcr05 a/d conversion result register 05 r undefined fffff21bh adcr05h a/d conversion result register 05h r undefined fffff21ch adcr06 a/d conversion result register 06 r undefined fffff21dh adcr06h a/d conversion result register 06h r undefined table 3-5: peripheral i/o registers (5/14) address symbol function register name r/w bit units for manipulation reset 181632
100 chapter 3 cpu functions user?s manual u16580ee2v0ud00 fffff21eh adcr07 a/d conversion result register 07 r undefined fffff21fh adcr07h a/d conversion result register 07h r undefined fffff220h adcr08 a/d conversion result register 08 r undefined fffff221h adcr08h a/d conversion result register 08h r undefined fffff222h adcr09 a/d conversion result register 09 r undefined fffff223h adcr09h a/d conversion result register 09h r undefined fffff22eh addma0 a/d conversion result register 0 for dma r undefined fffff240h adm10 a/d converter 1 mode register 0 r/w 00h fffff241h adm11 a/d converter 1 mode register 1 r/w 00h fffff242h adm12 a/d converter 1 mode register 2 r/w 00h fffff250h adcr10 a/d conversion result register 10 r undefined fffff251h adcr10h a/d conversion result register 10h r undefined fffff252h adcr11 a/d conversion result register 11 r undefined fffff253h adcr11h a/d conversion result register 11h r undefined fffff254h adcr112 a/d conversion result register 12 r undefined fffff255h adcr12h a/d conversion result register 12h r undefined fffff256h adcr13 a/d conversion result register 13 r undefined fffff257h adcr13h a/d conversion result register 13h r undefined fffff258h adcr14 a/d conversion result register 14 r undefined fffff259h adcr14h a/d conversion result register 14h r undefined fffff25ah adcr15 a/d conversion result register 15 r undefined fffff25bh adcr15h a/d conversion result register 15h r undefined fffff25ch adcr16 a/d conversion result register 16 r undefined fffff25dh adcr16h a/d conversion result register 16h r undefined fffff25eh adcr17 a/d conversion result register 17 r undefined fffff25fh adcr17h a/d conversion result register 17h r undefined fffff260h adcr18 a/d conversion result register 18 r undefined fffff261h adcr18h a/d conversion result register 18h r undefined fffff262h adcr19 a/d conversion result register 19 r undefined fffff263h adcr19h a/d conversion result register 19h r undefined fffff26eh addma1 a/d conversion result register 1 for dma r undefined fffff270h adtrsel0 a/d trigger select register 0 r/w 00h fffff272h adtrsel1 a/d trigger select register 1 r/w 00h fffff300h mar0 memory transfer start address register 0 r/w undefined fffff302h mar1 memory transfer start address register 1 r/w undefined fffff304h mar2 memory transfer start address register 2 r/w undefined fffff306h mar3 memory transfer start address register 3 r/w undefined fffff308h mar4 memory transfer start address register 4 r/w undefined fffff30ah mar5 memory transfer start address register 5 r/w undefined fffff30ch mar6 memory transfer start address register 6 r/w undefined table 3-5: peripheral i/o registers (6/14) address symbol function register name r/w bit units for manipulation reset 1 8 16 32
101 chapter 3 cpu functions user?s manual u16580ee2v0ud00 fffff30eh mar7 memory transfer start address register 7 r/w undefined fffff314h sar2 sfr transfer start address register 2 r/w undefined fffff316h sar3 sfr transfer start address register 3 r/w undefined fffff320h dtcr0 dma transfer count register 0 r/w undefined fffff322h dtcr1 dma transfer count register 1 r/w undefined fffff324h dtcr2 dma transfer count register 2 r/w undefined fffff326h dtcr3 dma transfer count register 3 r/w undefined fffff328h dtcr4 dma transfer count register 4 r/w undefined fffff32ah dtcr5 dma transfer count register 5 r/w undefined fffff32ch dtcr6 dma transfer count register 6 r/w undefined fffff32eh dtcr7 dma transfer count register 7 r/w undefined fffff330h dmamc dma mode control register r/w 00h fffff332h dmas dma status register r/w 00h fffff334h dmadsc dma data size control register r/w 00h fffff348h dtfr4 dma trigger factor register 4 r/w 00h fffff34ah dtfr5 dma trigger factor register 5 r/w 00h fffff34ch dtfr6 dma trigger factor register 6 r/w 00h fffff34eh dtfr7 dma trigger factor register 7 r/w 00h fffff400h p0 port register 0 r undefined fffff402h p1 port register 1 r/w undefined fffff404h p2 port register 2 r/w undefined fffff406h p3 port register 3 r/w undefined fffff408h p4 port register 4 r/w undefined fffff40ah p5 port register 5 r/w undefined fffff40ch p6 port register 6 r/w undefined fffff40eh p7 port register 7 r/w undefined fffff410h p8 port register 8 r/w undefined fffff412h p9 port register 9 r/w undefined fffff414h p10 port register 10 r/w undefined fffff422h pm1 port mode register 1 r/w ffh fffff424h pm2 port mode register 2 r/w ffh fffff426h pm3 port mode register 3 r/w ffh fffff428h pm4 port mode register 4 r/w ffh fffff42ah pm5 port mode register 5 r/w ffh fffff42ch pm6 port mode register 6 r/w ffh fffff42eh pm7 port mode register 7 r/w ffh fffff430h pm8 port mode register 8 r/w ffh fffff432h pm9 port mode register 9 r/w ffh fffff434h pm10 port mode register 10 r/w ffh fffff442h pmc1 port mode control register 1 r/w 00h table 3-5: peripheral i/o registers (7/14) address symbol function register name r/w bit units for manipulation reset 181632
102 chapter 3 cpu functions user?s manual u16580ee2v0ud00 fffff444h pmc2 port mode control register 2 r/w 00h fffff446h pmc3 port mode control register 3 r/w 00h fffff448h pmc4 port mode control register 4 r/w 00h fffff44ah pmc5 port mode control register 5 r/w 00h fffff44ch pmc6 port mode control register 6 r/w 00h fffff44eh pmc7 port mode control register 7 r/w 00h fffff450h pmc8 port mode control register 8 r/w 00h fffff452h pmc9 port mode control register 9 r/w 00h fffff454h pmc10 port mode control register 10 r/w 00h fffff480h bct0 bus cycle type configuration register 0 r/w cccch fffff482h bct1 bus cycle type configuration register 1 r/w cccch fffff484h dwc0 data wait control register 0 r/w 7777h fffff486h dwc1 data wait control register 1 r/w 7777h fffff488h awc address wait control register r/w 0000h fffff48ah bcc bus and cycle control register r/w aaaah fffff48eh dvc bus clock dividing control register r/w 01h fffff4c0h ramerr iram parity error flag register r/w 00h fffff4c2h rampadd iram parity error address register r/w 8000h fffff580h tr0ctl0 tmr0 control register 0 r/w 00h fffff581h tr0ctl1 tmr0 control register 1 r/w 00h fffff582h tr0ioc0 tmr0 i/o control register 0 r/w 00h fffff585h tr0ioc3 tmr0 i/o control register 3 r/w 00h fffff586h tr0ioc4 tmr0 i/o control register 4 r/w 00h fffff587h tr0opt0 tmr0 option register 0 r/w 00h fffff588h tr0opt2 tmr0 option register 2 r/w 00h fffff589h tr0opt3 tmr0 option register 3 r/w 00h fffff58ch tr0opt6 tmr0 option register 6 r/w 00h fffff58dh tr0opt7 tmr0 option register 7 r/w 00h fffff58eh tr0opt1 tmr0 option register 1 r/w 0000h fffff590h tr0ccr5 tmr0 capture/compare register 5 r/w 0000h fffff592h tr0ccr4 tmr0 capture/compare register 4 r/w 0000h fffff598h tr0ccr0 tmr0 capture/compare register 0 r/w 0000h fffff59ah tr0ccr3 tmr0 capture/ compare register 3 r/w 0000h fffff59ch tr0ccr2 tmr0 capture/ compare register 2 r/w 0000h fffff59eh tr0ccr1 tmr0 capture/ compare register 1 r/w 0000h fffff5a0h tr0dtc0 tmr0 dead time set register 0 r/w 0000h fffff5a2h tr0dtc1 tmr0 dead time set register 1 r/w 0000h fffff5a4h tr0cnt tmr0 timer c ounter read register r/w 0000h fffff5a6h tr0sbc tmr0 timer s ub-counter read register r/w 0000h fffff5c0h tr1ctl0 tmr1 control register 0 r/w 00h table 3-5: peripheral i/o registers (8/14) address symbol function register name r/w bit units for manipulation reset 1 8 16 32
103 chapter 3 cpu functions user?s manual u16580ee2v0ud00 fffff5c1h tr1ctl1 tmr1 control register 1 r/w 00h fffff5c2h tr1ioc0 tmr1 i/o control register 0 r/w 00h fffff5c3h tr1ioc1 tmr1 i/o control register 1 r/w 00h fffff5c4h tr1ioc2 tmr1 i/o control register 2 r/w 00h fffff5c5h tr1ioc3 tmr1 i/o control register 3 r/w 00h fffff5c6h tr1ioc4 tmr1 i/o control register 4 r/w 00h fffff5c7h tr1opt0 tmr1 option register 0 r/w 00h fffff5c8h tr1opt2 tmr1 option register 2 r/w 00h fffff5c9h tr1opt3 tmr1 option register 3 r/w 00h fffff5cch tr1opt6 tmr1 option register 6 r/w 00h fffff5cdh tr1opt7 tmr1 option register 7 r/w 00h fffff5ceh tr1opt1 tmr1 option register 1 r/w 0000h fffff5d0h tr1ccr5 tmr1 capture/compare register 5 r/w 0000h fffff5d2h tr1ccr4 tmr1 capture/compare register 4 r/w 0000h fffff5d8h tr1ccr0 tmr1 capture/compare register 0 r/w 0000h fffff5dah tr1ccr3 tmr1 capture/compare register 3 r/w 0000h fffff5dch tr1ccr2 tmr1 capture/compare register 2 r/w 0000h fffff5deh tr1ccr1 tmr1 capture/compare register 1 r/w 0000h fffff5e0h tr1dtc0 tmr1 dead time set register 0 r/w 0000h fffff5e2h tr1dtc1 tmr1 dead time set register 1 r/w 0000h fffff5e4h tr1cnt tmr1 timer counter read register r 0000h fffff5e6h tr1sbc tmr1 timer sub-counter read register r 0000h fffff600h tp0ctl0 tmp0 timer control register 0 r/w 00h fffff601h tp0ctl1 tmp0 timer control register 1 r/w 00h fffff602h tp0ioc0 tmp0 i/o control register 0 r/w 00h fffff603h tp0ioc1 tmp0 i/o control register 1 r/w 00h fffff604h tp0ioc2 tmp0 i/o control register 2 r/w 00h fffff605h tp0opt0 tmp0 option register r/w 00h fffff606h tp0ccr0 tmp0 capture/compare register 0 r/w 0000h fffff608h tp0ccr1 tmp0 capture/compare register 1 r/w 0000h fffff60ah tp0cnt tmp0 count register r 0000h fffff610h tp1ctl0 tmp1 timer control register 0 r/w 00h fffff611h tp1ctl1 tmp1 timer control register 1 r/w 00h fffff612h tp1ioc0 tmp1 i/o control register 0 r/w 00h fffff613h tp1ioc1 tmp1 i/o control register 1 r/w 00h fffff614h tp1ioc2 tmp1 i/o control register 2 r/w 00h fffff615h tp1opt0 tmp1 option register r/w 00h fffff616h tp1ccr0 tmp1 capture/compare register 0 r/w 0000h fffff618h tp1ccr1 tmp1 capture/compare register 1 r/w 0000h fffff61ah tp1cnt tmp1 count register r 0000h table 3-5: peripheral i/o registers (9/14) address symbol function register name r/w bit units for manipulation reset 181632
104 chapter 3 cpu functions user?s manual u16580ee2v0ud00 fffff620h tp2ctl0 tmp2 timer control register 0 r/w 00h fffff621h tp2ctl1 tmp2 timer control register 1 r/w 00h fffff622h tp2ioc0 tmp2 i/o control register 0 r/w 00h fffff623h tp2ioc1 tmp2 i/o control register 1 r/w 00h fffff624h tp2ioc2 tmp2 i/o control register 2 r/w 00h fffff625h tp2opt0 tmp2 option register r/w 00h fffff626h tp2ccr0 tmp2 capture/compare register 0 r/w 0000h fffff628h tp2ccr1 tmp2 capture/compare register 1 r/w 0000h fffff62ah tp2cnt tmp2 count register r 0000h fffff630h tp3ctl0 tmp3 timer control register 0 r/w 00h fffff631h tp3ctl1 tmp3 timer control register 1 r/w 00h fffff632h tp3ioc0 tmp3 i/o control register 0 r/w 00h fffff633h tp3ioc1 tmp3 i/o control register 1 r/w 00h fffff634h tp3ioc2 tmp3 i/o control register 2 r/w 00h fffff635h tp3opt0 tmp3 option register r/w 00h fffff636h tp3ccr0 tmp3 capture/compare register 0 r/w 0000h fffff638h tp3ccr1 tmp3 capture/compare register 1 r/w 0000h fffff63ah tp3cnt tmp3 count register r 0000h fffff640h tp4ctl0 tmp4 timer control register 0 r/w 00h fffff641h tp4ctl1 tmp4 timer control register 1 r/w 00h fffff642h tp4ioc0 tmp4 i/o control register 0 r/w 00h fffff643h tp4ioc1 tmp4 i/o control register 1 r/w 00h fffff644h tp4ioc2 tmp4 i/o control register 2 r/w 00h fffff645h tp4opt0 tmp4 option register r/w 00h fffff646h tp4ccr0 tmp4 capture/compare register 0 r/w 0000h fffff648h tp4ccr1 tmp4 capture/compare register 1 r/w 0000h fffff64ah tp4cnt tmp4 count register r 0000h fffff650h tp5ctl0 tmp5 timer control register 0 r/w 00h fffff651h tp5ctl1 tmp5 timer control register 1 r/w 00h fffff652h tp5ioc0 tmp5 i/o control register 0 r/w 00h fffff653h tp5ioc1 tmp5 i/o control register 1 r/w 00h fffff654h tp5ioc2 tmp5 i/o control register 2 r/w 00h fffff655h tp5opt0 tmp5 option register r/w 00h fffff656h tp5ccr0 tmp5 capture/compare register 0 r/w 0000h fffff658h tp5ccr1 tmp5 capture/compare register 1 r/w 0000h fffff65ah tp5cnt tmp5 count register r 0000h fffff660h tp6ctl0 tmp6 timer control register 0 r/w 00h fffff661h tp6ctl1 tmp6 timer control register 1 r/w 00h fffff662h tp6ioc0 tmp6 i/o control register 0 r/w 00h fffff663h tp6ioc1 tmp6 i/o control register 1 r/w 00h table 3-5: peripheral i/o registers (10/14) address symbol function register name r/w bit units for manipulation reset 1 8 16 32
105 chapter 3 cpu functions user?s manual u16580ee2v0ud00 fffff664h tp6ioc2 tmp6 i/o control register 2 r/w 00h fffff665h tp6opt0 tmp6 option register r/w 00h fffff666h tp6ccr0 tmp6 capture/compare register 0 r/w 0000h fffff668h tp6ccr1 tmp6 capture/compare register 1 r/w 0000h fffff66ah tp6cnt tmp6 count register r 0000h fffff670h tp7ctl0 tmp7 timer control register 0 r/w 00h fffff671h tp7ctl1 tmp7 timer control register 1 r/w 00h fffff672h tp7ioc0 tmp7 i/o control register 0 r/w 00h fffff673h tp7ioc1 tmp7 i/o control register 1 r/w 00h fffff674h tp7ioc2 tmp7 i/o control register 2 r/w 00h fffff675h tp7opt0 tmp7 option register r/w 00h fffff676h tp7ccr0 tmp7 capture/compare register 0 r/w 0000h fffff678h tp7ccr1 tmp7 capture/compare register 1 r/w 0000h fffff67ah tp7cnt tmp7 count register r 0000h fffff680h tp8ctl0 tmp8 timer control register 0 r/w 00h fffff681h tp8ctl1 tmp8 timer control register 1 r/w 00h fffff682h tp8ioc0 tmp8 i/o control register 0 r/w 00h fffff683h tp8ioc1 tmp8 i/o control register 1 r/w 00h fffff684h tp8ioc2 tmp8 i/o control register 2 r/w 00h fffff685h tp8opt0 tmp8 option register r/w 00h fffff686h tp8ccr0 tmp8 capture/compare register 0 r/w 0000h fffff688h tp8ccr1 tmp8 capture/compare register 1 r/w 0000h fffff68ah tp8cnt tmp8 count register r 0000h fffff690h tt0ctl0 tmt0 time r control register 0 r/w 00h fffff691h tt0ctl1 tmt0 time r control register 1 r/w 00h fffff692h tt0ctl2 tmt0 time r control register 2 r/w 00h fffff693h tt0ioc0 tmt0 i/o control register 0 r/w 00h fffff694h tt0ioc1 tmt0 i/o control register 1 r/w 00h fffff695h tt0ioc2 tmt0 i/o control register 2 r/w 00h fffff696h tt0ioc3 tmt0 i/o control register 3 r/w 00h fffff697h tt0opt0 tmt0 option register 0 r/w 00h fffff698h tt0opt1 tmt0 option register 1 r/w 00h fffff699h tt0opt2 tmt0 option register 2 r/w 00h fffff69ah tt0ccr0 tmt0 capture/ compare register 0 r/w 0000h fffff69ch tt0ccr1 tmt0 capture/ compare register 1 r/w 0000h fffff69eh tt0cnt tmt0 counter read register r 0000h fffff6a0h tt1ctl0 tmt1 time r control register 0 r/w 00h fffff6a1h tt1ctl1 tmt1 time r control register 1 r/w 00h fffff6a2h tt1ctl2 tmt1 time r control register 2 r/w 00h fffff6a3h tt1ioc0 tmt1 i/o control register 0 r/w 00h table 3-5: peripheral i/o registers (11/14) address symbol function register name r/w bit units for manipulation reset 181632
106 chapter 3 cpu functions user?s manual u16580ee2v0ud00 fffff6a4h tt1ioc1 tmt1 i/o control register 1 r/w 00h fffff6a5h tt1ioc2 tmt1 i/o control register 2 r/w 00h fffff6a6h tt1ioc3 tmt1 i/o control register 3 r/w 00h fffff6a7h tt1opt0 tmt1 option register 0 r/w 00h fffff6a8h tt1opt1 tmt1 option register 1 r/w 00h fffff6a9h tt1opt2 tmt1 option register 2 r/w 00h fffff6aah tt1ccr0 tmt1 capture/ compare register 0 r/w 0000h fffff6ach tt1ccr1 tmt1 capture/compare register 1 r/w 0000h fffff6aeh tt1cnt tmt1 counter read register r 0000h fffff6b0h tmenc10 timer enc10 count register r/w 0000h fffff6b2h cm100 compare register 100 r/w 0000h fffff6b4h cm101 compare register 101 r/w 0000h fffff6b6h cc100 capture/compare register 100 r/w 0000h fffff6b8h cc101 capture/compare register 101 r/w 0000h fffff6bah ccr10 capture/compare control register 10 r/w 00h fffff6bbh tum10 timer unit mode register 10 r/w 00h fffff6bch tmc10 timer control register 10 r/w 00h fffff6bdh sesa10 signal edge se lection register 10 r/w 00h fffff6beh prm10 prescaler mode register 10 r/w 07h fffff6bfh status10 status register 10 r 00h fffff6f0h tpic0 tmp input source control register 0 r/w 00h fffff6f2h tpic1 tmp input source control register 1 r/w 00h fffff6f4h tpic2 tmp input source control register 2 r/w 00h fffff700h rng random number register r undefined fffff7a0h nrc noise removal time control register r/w 00h fffff802h phs peripheral status register r/w 00h fffff880h intm0 interrupt mode register 0 r/w 00h fffff882h intm1 interrupt mode register 1 r/w 00h fffff884h intm2 interrupt mode register 2 r/w 00h fffff886h intm3 interrupt mode register 3 r/w 00h fffff888h pesc5 port emergency shut off control register 5 r/w 00h fffff88ah esost5 port emergency sh ut off status register 5 r/w 00h fffff88ch pesc6 port emergency sh ut off control register 6 r/w 00h fffff88eh esost6 port emergency sh ut off status register 6 r/w 00h fffff990h tt0tcw timer t0 counter write buffer register r/w 0000h fffff9a0h tt1tcw timer t1 counter write buffer register r/w 0000h fffffa00h uc0ctl0 uartc0 control register 0 r/w 10h fffffa01h uc0ctl1 uartc0 control register 1 r/w 00h fffffa02h uc0ctl2 uartc0 control register 2 r/w 00h fffffa03h uc0opt0 uartc0 option control register 0 r/w 14h table 3-5: peripheral i/o registers (12/14) address symbol function register name r/w bit units for manipulation reset 1 8 16 32
107 chapter 3 cpu functions user?s manual u16580ee2v0ud00 fffffa04h uc0str uartc0 status register r/w 00h fffffa06h uc0rx uartc0 receive data register r 01ffh fffffa06h uc0rxl uartc0 receive data register l r ffh fffffa08h uc0tx uartc0 transmit data register r/w 01ffh fffffa08h uc0txl uartc0 transmit data register l r/w ffh fffffa0ah uc0opt1 uartc0 option control register 1 r/w 00h fffffa0bh uc0str1 uartc0 status register 1 r 00h fffffa20h uc1ctl0 uartc1 control register 0 r/w 10h fffffa21h uc1ctl1 uartc1 control register 1 r/w 00h fffffa22h uc1ctl2 uartc1 control register 2 r/w 00h fffffa23h uc1opt0 uartc1 option control register 0 r/w 14h fffffa24h uc1str uartc1 status register r/w 00h fffffa26h uc1rx uartc1 receive data register r 01ffh fffffa26h uc1rxl uartc1 receive data register l r ffh fffffa28h uc1tx uartc1 transmit data register r/w 01ffh fffffa28h uc1txl uartc1 transmit data register l r/w ffh fffffa2ah uc1opt1 uartc1 option control register 1 r/w 00h fffffa2bh uc1str1 uartc1 status register 1 r 00h fffffd00h cb0ctl0 csib0 control register 0 r/w 01h fffffd01h cb0ctl1 csib0 control register 1 r/w 00h fffffd02h cb0ctl2 csib0 co ntrol register 2 r/w 00h fffffd03h cb0str csib0 state register r/w 00h fffffd04h cb0rx0 csib0 receive data register r 0000h fffffd04h cb0rx0l csib0 receive data register l r 00h fffffd06h cb0tx0l csib0 transm it data register l r/w 00h fffffd06h cb0tx0 csib0 transmit data register r/w 0000h fffffd20h cb1ctl0 csib1 control register 0 r/w 01h fffffd21h cb1ctl1 csib1 control register 1 r/w 00h fffffd22h cb1ctl2 csib1 co ntrol register 2 r/w 00h fffffd23h cb1str csib1 state register r/w 00h fffffd24h cb1rx0 csib1 receive data register r 0000h fffffd24h cb1rx0l csib1 receive data register l r 00h fffffd26h cb1tx0l csib1 transm it data register l r/w 00h fffffd26h cb1tx0 csib1 transmit data register r/w 0000h fffffd40h csim30 csi30 operation mode register r/w 00h fffffd41h csic30 csi30 clock selection register r/w 07h fffffd42h sirb30 csi30 receive data buffer register r 0000h fffffd42h sirb30l csi30 receive data buffer register l r 00h fffffd43h sirb30h csi30 receive data buffer register h r 00h fffffd44h sfcs30l csi30 chip selection csi buffer register l r/w ffh table 3-5: peripheral i/o registers (13/14) address symbol function register name r/w bit units for manipulation reset 181632
108 chapter 3 cpu functions user?s manual u16580ee2v0ud00 fffffd44h sfcs30 csi30 chip selection csi buffer register r/w ffffh fffffd45h sfcs30h csi30 chip selection csi buffer register h r ffh fffffd46h sfdb30l csi30 transmit data csi buffer register l r/w 00h fffffd46h sfdb30 csi30 transmit data csi buffer register r/w 0000h fffffd47h sfdb30h csi30 transmit data csi buffer register h r/w 00h fffffd48h sfa30 csi30 sibuf state register r/w 20h fffffd49h csil30 csi30 transfer data length select register r/w 00h fffffd4ch sfn30 csi30 transfer data number specification register r/w 00h fffffd60h csim31 csi31 operation mode register r/w 00h fffffd61h csic31 csi31 clock selection register r/w 07h fffffd62h sirb31 csi31 receive data buffer register r 0000h fffffd62h sirb31l csi31 receive data buffer register l r 00h fffffd63h sirb31h csi31 receive data buffer register h r 00h fffffd64h sfcs31l csi31 chip selection csi buffer register l r/w ffh fffffd64h sfcs31 csi31 chip selection csi buffer register r/w ffffh fffffd65h sfcs31h csi31 chip selection csi buffer register h r ffh fffffd66h sfdb31l csi31 transmit data csi buffer register l r/w 00h fffffd66h sfdb31 csi31 transmit data csi buffer register r/w 0000h fffffd67h sfdb31h csi31 transmit data csi buffer register h r/w 00h fffffd68h sfa31 csi31 sibuf state register r/w 20h fffffd69h csil31 csi31 transfer data length select register r/w 00h fffffd6ch sfn31 csi31 transfer data number specification register r/w 00h fffffdc0h prsm0 prescaler mode register 0 r/w 00h fffffdc1h prscm0 prescaler compare register 0 r/w 00h fffffdd0h prsm1 prescaler mode register 1 r/w 00h fffffdd1h prscm1 prescaler compare register 1 r/w 00h fffffde0h prsm2 prescaler mode register 2 r/w 00h fffffde1h prscm2 prescaler compare register 2 r/w 00h fffffe00h dmawc0 dma wait control register 0 r/w 37h fffffe02h dmawc1 dma wait control register 1 r/w 07h table 3-5: peripheral i/o registers (14/14) address symbol function register name r/w bit units for manipulation reset 1 8 16 32
109 chapter 3 cpu functions user?s manual u16580ee2v0ud00 3.4.7 programmable peripheral i/o area in the v850e/ph2, the 16 kb area of x0000h to x3fffh is provided as a programmable peripheral i/o area. in this area, the area between x0000h and x0 8ffh is used exclusively for the can controllers (can0, can1). the internal bus of the v850e/ph2 becomes active when the on-chip peripheral i/o register area (ffff000h to fffffffh) or the programmable peripheral i/o re gister area (xxxxm000h to xxxxnfffh) is accessed (m = xx00b, n= xx11b). however, the on-chip peripheral i/o area is allocated to the last 4 kb of the programmable peripheral i/o register area. note that when data is written to this area, the written contents are reflected on the on-chip peripheral i/o area. therefore, access to this area is prohibited. to access the on-chip peripheral i/o area, be sure to specify addresses ffff000h to fffffffh. figure 3-19: programmable peripheral i/o area (outline) remark: m = xx00b, n = m + 11b, p= m + 10b cautions: 1. it is recommended to locate the programmable peripheral area in the first 32 mbyte of the physical memory. 2. the programmable peripheral area is not allowed to overlap the rom or ram areas: bpc must be initialized with a value in the range 0040h to 0ffbh. 3ffffffh 3fff000h 3ffefffh xxxxnfffh xxxxm000h x3fffh x3000h x2fffh x0000h x08ffh 0000000h peripheral i/o register programmable peripheral i/o register internal local bus dedicated area for can controllers on-chip peripheral i/o area programmable peripheral i/o area
110 chapter 3 cpu functions user?s manual u16580ee2v0ud00 (1) peripheral area selection control register (bpc) the peripheral area selection control register (bpc) is used to select a programmable peripheral i/o register area where the registers of the can controller are allocated. this register can be read/written in 16-bit units. figure 3-20: programmable peripheral area control register bpc remark: the recommended value of the bpc register to enable the programmable peripheral i/o area is 87ffh. this setting assigns the programmable peripheral i/o area to addresses from 1ffc000h to 1ffffffh. after reset: 0000h r/w address: fffff064h 1514131211109876543210 bpc pa15 0 pa13 pa12 pa11 pa10 pa9 pa8 pa7 pa6 pa5 pa4 pa3 pa2 pa1 pa 0 (n = 0, 1) pa15 usage of programmable peripheral i/o area 0 disables usage of programmable peripheral i/o area 1 enables usage of programmable peripheral i/o area pa13 to pa0 base address of programmable peripheral i/o area 0000h to 3fffh specifies the base address of the programmable peripheral i/o area (pa13 to pa0 corresponds to a27 to a14, respectively).
111 chapter 3 cpu functions user?s manual u16580ee2v0ud00 (2) registers in the programmable peripheral i/o area in the following table 3-6 the addresses shown are offsets in the programmable peripheral i/o area, which have to be added to base address set by the bpc register. table 3-6: programmable peripheral i/o registers (1/16) address offset symbol function register name r/w bit units for manipulation after reset 1816 0000000h c0gmctrl can0 global macro control register r/w 0000h 0000000h c0gmctrll can0 global macro control register l r/w 00h 0000001h c0gmctrlh can0 global macro control register h r/w 00h 0000002h c0gmcs can0 global macro clock selection register r/w 00h 0000006h c0gmabt can0 global macro automatic block transmission register r/w 0000h 0000006h c0gmabtl can0 global macro automatic block transmission register l r/w 00h 0000007h c0gmabth can0 global macro automatic block transmission register h r/w 00h 0000008h c0gmabtd can0 global macro automatic block transmission delay register r/w 00h 0000040h c0mask1l can0 module mask 1 register l r/w undefined 0000042h c0mask1h can0 module mask 1 register h r/w undefined 0000044h c0mask2l can0 module mask 2 register l r/w undefined 0000046h c0mask2h can0 module mask 2 register h r/w undefined 0000048h c0mask3l can0 module mask 3 register l r/w undefined 000004ah c0mask3h can0 module mask 3 register h r/w undefined 000004ch c0mask4l can0 module mask 4 register l r/w undefined 000004eh c0mask4h can0 module mask 4 register h r/w undefined 0000050h c0ctrl can0 module control register r/w 0000h 0000052h c0lec can0 module last error code register r/w 00h 0000053h c0info can0 module information register r 00h 0000054h c0erc can0 module error counter r/w 0000h 0000056h c0ie can0 module interrupt enable register r/w 0000h 0000056h c0iel can0 module interrupt enable register l r/w 00h 0000057h c0ieh can0 module interrupt enable register h r/w 00h 0000058h c0ints can0 module interrupt status register r/w 0000h 0000058h c0intsl can0 module interrupt status register l r/w 00h 000005ah c0brp can0 module bit-rate prescaler register r/w ffh 000005ch c0btr can0 bit-rate register r/w 370fh 000005eh c0lipt can0 module last in-pointer register r/w undefined 0000060h c0rgpt can0 module receive history list get pointer register r/w undefined 0000060h c0rgptl can0 module receive history list get pointer register l r/w 01h 0000062h c0lopt can0 module last out-pointer register r undefined
112 chapter 3 cpu functions user?s manual u16580ee2v0ud00 0000064h c0tgpt can0 module transmit history list get pointer register r/w undefined 0000064h c0tgptl can0 module transmit history list get pointer register l r/w 01h 0000066h c0ts can0 module time stamp register r/w 0000h 0000066h c0tsl can0 module time stamp register l r/w 00h 0000067h c0tsh can0 module time stamp register h r/w 00h 0000100h c0mdata0100 can0 message data byte 0 and 1 register 00 r/w undefined 0000100h c0mdata000 can0 message data byte 0 register 00 r/w undefined 0000101h c0mdata100 can0 message data byte 1 register 00 r/w undefined 0000102h c0mdata2300 can0 message data byte 2 and 3 register 00 r/w undefined 0000102h c0mdata200 can0 message data byte 2 register 00 r/w undefined 0000103h c0mdata300 can0 message data byte 3 register 00 r/w undefined 0000104h c0mdata4500 can0 message data byte 4 and 5 register 00 r/w undefined 0000104h c0mdata400 can0 message data byte 2 register 00 r/w undefined 0000105h c0mdata500 can0 message data byte 3 register 00 r/w undefined 0000106h c0mdata6700 can0 message data byte 6 and 7 register 00 r/w undefined 0000106h c0mdata600 can0 message data byte 6 register 00 r/w undefined 0000107h c0mdata700 can0 message data byte 7 register 00 r/w undefined 0000108h c0mdlc00 can0 message data length code register 00 r/w undefined 0000109h c0mconf00 can0 message configuration register 00 r/w undefined 000010ah c0midl00 can0 message identifier l register 00 r/w undefined 000010ch c0midh00 can0 message identifier h register 00 r/w undefined 000010eh c0mctrl00 can0 message control register 00 r/w undefined 0000120h c0mdata0101 can0 message data byte 0 and 1 register 01 r/w undefined 0000120h c0mdata001 can0 message data byte 0 register 01 r/w undefined 0000121h c0mdata101 can0 message data byte 1 register 01 r/w undefined 0000122h c0mdata2301 can0 message data byte 2 and 3 register 01 r/w undefined 0000122h c0mdata201 can0 message data byte 2 register 01 r/w undefined 0000123h c0mdata301 can0 message data byte 3 register 01 r/w undefined 0000124h c0mdata4501 can0 message data byte 4 and 5 register 01 r/w undefined 0000124h c0mdata401 can0 message data byte 2 register 01 r/w undefined 0000125h c0mdata501 can0 message data byte 3 register 01 r/w undefined 0000126h c0mdata6701 can0 message data byte 6 and 7 register 01 r/w undefined 0000126h c0mdata601 can0 message data byte 6 register 01 r/w undefined 0000127h c0mdata701 can0 message data byte 7 register 01 r/w undefined 0000128h c0mdlc01 can0 message data length code register 01 r/w undefined 0000129h c0mconf01 can0 message configuration register 01 r/w undefined 000012ah c0midl01 can0 message identifier l register 01 r/w undefined 000012ch c0midh01 can0 message identifier h register 01 r/w undefined 000012eh c0mctrl01 can0 message control register 01 r/w undefined table 3-6: programmable peripheral i/o registers (2/16) address offset symbol function register name r/w bit units for manipulation after reset 1816
113 chapter 3 cpu functions user?s manual u16580ee2v0ud00 0000140h c0mdata0102 can0 message data byte 0 and 1 register 02 r/w undefined 0000140h c0mdata002 can0 message data byte 0 register 02 r/w undefined 0000141h c0mdata102 can0 message data byte 1 register 02 r/w undefined 0000142h c0mdata2302 can0 message data byte 2 and 3 register 02 r/w undefined 0000142h c0mdata202 can0 message data byte 2 register 02 r/w undefined 0000143h c0mdata302 can0 message data byte 3 register 02 r/w undefined 0000144h c0mdata4502 can0 message data byte 4 and 5 register 02 r/w undefined 0000144h c0mdata402 can0 message data byte 2 register 02 r/w undefined 0000145h c0mdata502 can0 message data byte 3 register 02 r/w undefined 0000146h c0mdata6702 can0 message data byte 6 and 7 register 02 r/w undefined 0000146h c0mdata602 can0 message data byte 6 register 02 r/w undefined 0000147h c0mdata702 can0 message data byte 7 register 02 r/w undefined 0000148h c0mdlc02 can0 message data length code register 02 r/w undefined 0000149h c0mconf02 can0 message configuration register 02 r/w undefined 000014ah c0midl02 can0 message id entifier l register 02 r/w undefined 000014ch c0midh02 can0 message identifier h register 02 r/w undefined 000014eh c0mctrl02 can0 message control register 02 r/w undefined 0000160h c0mdata0103 can0 message data byte 0 and 1 register 03 r/w undefined 0000160h c0mdata003 can0 message data byte 0 register 03 r/w undefined 0000161h c0mdata103 can0 message data byte 1 register 03 r/w undefined 0000162h c0mdata2303 can0 message data byte 2 and 3 register 03 r/w undefined 0000162h c0mdata203 can0 message data byte 2 register 03 r/w undefined 0000163h c0mdata303 can0 message data byte 3 register 03 r/w undefined 0000164h c0mdata4503 can0 message data byte 4 and 5 register 03 r/w undefined 0000164h c0mdata403 can0 message data byte 2 register 03 r/w undefined 0000165h c0mdata503 can0 message data byte 3 register 03 r/w undefined 0000166h c0mdata6703 can0 message data byte 6 and 7 register 03 r/w undefined 0000166h c0mdata603 can0 message data byte 6 register 03 r/w undefined 0000167h c0mdata703 can0 message data byte 7 register 03 r/w undefined 0000168h c0mdlc03 can0 message data length code register 03 r/w undefined 0000169h c0mconf03 can0 message configuration register 03 r/w undefined 000016ah c0midl03 can0 message id entifier l register 03 r/w undefined 000016ch c0midh03 can0 message identifier h register 03 r/w undefined 000016eh c0mctrl03 can0 message control register 03 r/w undefined 0000180h c0mdata0104 can0 message data byte 0 and 1 register 04 r/w undefined 0000180h c0mdata004 can0 message data byte 0 register 04 r/w undefined 0000181h c0mdata104 can0 message data byte 1 register 04 r/w undefined 0000182h c0mdata2304 can0 message data byte 2 and 3 register 04 r/w undefined 0000182h c0mdata204 can0 message data byte 2 register 04 r/w undefined 0000183h c0mdata304 can0 message data byte 3 register 04 r/w undefined table 3-6: programmable peripheral i/o registers (3/16) address offset symbol function register name r/w bit units for manipulation after reset 1816
114 chapter 3 cpu functions user?s manual u16580ee2v0ud00 0000184h c0mdata4504 can0 message data byte 4 and 5 register 04 r/w undefined 0000184h c0mdata404 can0 message data byte 2 register 04 r/w undefined 0000185h c0mdata504 can0 message data byte 3 register 04 r/w undefined 0000186h c0mdata6704 can0 message data byte 6 and 7 register 04 r/w undefined 0000186h c0mdata604 can0 message data byte 6 register 04 r/w undefined 0000187h c0mdata704 can0 message data byte 7 register 04 r/w undefined 0000188h c0mdlc04 can0 message data length code register 04 r/w undefined 0000189h c0mconf04 can0 message configuration register 04 r/w undefined 000018ah c0midl04 can0 message identifier l register 04 r/w undefined 000018ch c0midh04 can0 message identifier h register 04 r/w undefined 000018eh c0mctrl04 can0 message control register 04 r/w undefined 00001a0h c0mdata0105 can0 message data byte 0 and 1 register 05 r/w undefined 00001a0h c0mdata005 can0 message data byte 0 register 05 r/w undefined 00001a1h c0mdata105 can0 message data byte 1 register 05 r/w undefined 00001a2h c0mdata2305 can0 message data byte 2 and 3 register 05 r/w undefined 00001a2h c0mdata205 can0 message data byte 2 register 05 r/w undefined 00001a3h c0mdata305 can0 message data byte 3 register 05 r/w undefined 00001a4h c0mdata4505 can0 message data byte 4 and 5 register 05 r/w undefined 00001a4h c0mdata405 can0 message data byte 2 register 05 r/w undefined 00001a5h c0mdata505 can0 message data byte 3 register 05 r/w undefined 00001a6h c0mdata6705 can0 message data byte 6 and 7 register 05 r/w undefined 00001a6h c0mdata605 can0 message data byte 6 register 05 r/w undefined 00001a7h c0mdata705 can0 message data byte 7 register 05 r/w undefined 00001a8h c0mdlc05 can0 message data length code register 05 r/w undefined 00001a9h c0mconf05 can0 message configuration register 05 r/w undefined 00001aah c0midl05 can0 message identifier l register 05 r/w undefined 00001ach c0midh05 can0 message identifier h register 05 r/w undefined 00001aeh c0mctrl05 can0 message control register 05 r/w undefined 00001c0h c0mdata0106 can0 message data byte 0 and 1 register 06 r/w undefined 00001c0h c0mdata006 can0 message data byte 0 register 06 r/w undefined 00001c1h c0mdata106 can0 message data byte 1 register 06 r/w undefined 00001c2h c0mdata2306 can0 message data byte 2 and 3 register 06 r/w undefined 00001c2h c0mdata206 can0 message data byte 2 register 06 r/w undefined 00001c3h c0mdata306 can0 message data byte 3 register 06 r/w undefined 00001c4h c0mdata4506 can0 message data byte 4 and 5 register 06 r/w undefined 00001c4h c0mdata406 can0 message data byte 2 register 06 r/w undefined 00001c5h c0mdata506 can0 message data byte 3 register 06 r/w undefined 00001c6h c0mdata6706 can0 message data byte 6 and 7 register 06 r/w undefined 00001c6h c0mdata606 can0 message data byte 6 register 06 r/w undefined 00001c7h c0mdata706 can0 message data byte 7 register 06 r/w undefined table 3-6: programmable peripheral i/o registers (4/16) address offset symbol function register name r/w bit units for manipulation after reset 1816
115 chapter 3 cpu functions user?s manual u16580ee2v0ud00 00001c8h c0mdlc06 can0 message data length code register 06 r/w undefined 00001c9h c0mconf06 can0 message configuration register 06 r/w undefined 00001cah c0midl06 can0 message identifier l register 06 r/w undefined 00001cch c0midh06 can0 message identifier h register 06 r/w undefined 00001ceh c0mctrl06 can0 message control register 06 r/w undefined 00001e0h c0mdata0107 can0 message data byte 0 and 1 register 07 r/w undefined 00001e0h c0mdata007 can0 message data byte 0 register 07 r/w undefined 00001e1h c0mdata107 can0 message data byte 1 register 07 r/w undefined 00001e2h c0mdata2307 can0 message data byte 2 and 3 register 07 r/w undefined 00001e2h c0mdata207 can0 message data byte 2 register 07 r/w undefined 00001e3h c0mdata307 can0 message data byte 3 register 07 r/w undefined 00001e4h c0mdata4507 can0 message data byte 4 and 5 register 07 r/w undefined 00001e4h c0mdata407 can0 message data byte 2 register 07 r/w undefined 00001e5h c0mdata507 can0 message data byte 3 register 07 r/w undefined 00001e6h c0mdata6707 can0 message data byte 6 and 7 register 07 r/w undefined 00001e6h c0mdata607 can0 message data byte 6 register 07 r/w undefined 00001e7h c0mdata707 can0 message data byte 7 register 07 r/w undefined 00001e8h c0mdlc07 can0 message data length code register 07 r/w undefined 00001e9h c0mconf07 can0 message configuration register 07 r/w undefined 00001eah c0midl07 can0 message identifier l register 07 r/w undefined 00001ech c0midh07 can0 message identifier h register 07 r/w undefined 00001eeh c0mctrl07 can0 message control register 07 r/w undefined 0000200h c0mdata0108 can0 message data byte 0 and 1 register 08 r/w undefined 0000200h c0mdata008 can0 message data byte 0 register 08 r/w undefined 0000201h c0mdata108 can0 message data byte 1 register 08 r/w undefined 0000202h c0mdata2308 can0 message data byte 2 and 3 register 08 r/w undefined 0000202h c0mdata208 can0 message data byte 2 register 08 r/w undefined 0000203h c0mdata308 can0 message data byte 3 register 08 r/w undefined 0000204h c0mdata4508 can0 message data byte 4 and 5 register 08 r/w undefined 0000204h c0mdata408 can0 message data byte 2 register 08 r/w undefined 0000205h c0mdata508 can0 message data byte 3 register 08 r/w undefined 0000206h c0mdata6708 can0 message data byte 6 and 7 register 08 r/w undefined 0000206h c0mdata608 can0 message data byte 6 register 08 r/w undefined 0000207h c0mdata708 can0 message data byte 7 register 08 r/w undefined 0000208h c0mdlc08 can0 message data length code register 08 r/w undefined 0000209h c0mconf08 can0 message configuration register 08 r/w undefined 000020ah c0midl08 can0 message id entifier l register 08 r/w undefined 000020ch c0midh08 can0 message identifier h register 08 r/w undefined 000020eh c0mctrl08 can0 message control register 08 r/w undefined table 3-6: programmable peripheral i/o registers (5/16) address offset symbol function register name r/w bit units for manipulation after reset 1816
116 chapter 3 cpu functions user?s manual u16580ee2v0ud00 0000220h c0mdata0109 can0 message data byte 0 and 1 register 09 r/w undefined 0000220h c0mdata009 can0 message data byte 0 register 09 r/w undefined 0000221h c0mdata109 can0 message data byte 1 register 09 r/w undefined 0000222h c0mdata2309 can0 message data byte 2 and 3 register 09 r/w undefined 0000222h c0mdata209 can0 message data byte 2 register 09 r/w undefined 0000223h c0mdata309 can0 message data byte 3 register 09 r/w undefined 0000224h c0mdata4509 can0 message data byte 4 and 5 register 09 r/w undefined 0000224h c0mdata409 can0 message data byte 2 register 09 r/w undefined 0000225h c0mdata509 can0 message data byte 3 register 09 r/w undefined 0000226h c0mdata6709 can0 message data byte 6 and 7 register 09 r/w undefined 0000226h c0mdata609 can0 message data byte 6 register 09 r/w undefined 0000227h c0mdata709 can0 message data byte 7 register 09 r/w undefined 0000228h c0mdlc09 can0 message data length code register 09 r/w undefined 0000229h c0mconf09 can0 message configuration register 09 r/w undefined 000022ah c0midl09 can0 message identifier l register 09 r/w undefined 000022ch c0midh09 can0 message identifier h register 09 r/w undefined 000022eh c0mctrl09 can0 message control register 09 r/w undefined 0000240h c0mdata0110 can0 message data byte 0 and 1 register 10 r/w undefined 0000240h c0mdata010 can0 message data byte 0 register 10 r/w undefined 0000241h c0mdata110 can0 message data byte 1 register 10 r/w undefined 0000242h c0mdata2310 can0 message data byte 2 and 3 register 10 r/w undefined 0000242h c0mdata210 can0 message data byte 2 register 10 r/w undefined 0000243h c0mdata310 can0 message data byte 3 register 10 r/w undefined 0000244h c0mdata4510 can0 message data byte 4 and 5 register 10 r/w undefined 0000244h c0mdata410 can0 message data byte 2 register 10 r/w undefined 0000245h c0mdata510 can0 message data byte 3 register 10 r/w undefined 0000246h c0mdata6710 can0 message data byte 6 and 7 register 10 r/w undefined 0000246h c0mdata610 can0 message data byte 6 register 10 r/w undefined 0000247h c0mdata710 can0 message data byte 7 register 10 r/w undefined 0000248h c0mdlc10 can0 message data length code register 10 r/w undefined 0000249h c0mconf10 can0 message configuration register 10 r/w undefined 000024ah c0midl10 can0 message identifier l register 10 r/w undefined 000024ch c0midh10 can0 message identifier h register 10 r/w undefined 000024eh c0mctrl10 can0 message control register 10 r/w undefined 0000260h c0mdata0111 can0 message data byte 0 and 1 register 11 r/w undefined 0000260h c0mdata011 can0 message data byte 0 register 11 r/w undefined 0000261h c0mdata111 can0 message data byte 1 register 11 r/w undefined 0000262h c0mdata2311 can0 message data byte 2 and 3 register 11 r/w undefined 0000262h c0mdata211 can0 message data byte 2 register 11 r/w undefined 0000263h c0mdata311 can0 message data byte 3 register 11 r/w undefined table 3-6: programmable peripheral i/o registers (6/16) address offset symbol function register name r/w bit units for manipulation after reset 1816
117 chapter 3 cpu functions user?s manual u16580ee2v0ud00 0000264h c0mdata4511 can0 message data byte 4 and 5 register 11 r/w undefined 0000264h c0mdata411 can0 message data byte 2 register 11 r/w undefined 0000265h c0mdata511 can0 message data byte 3 register 11 r/w undefined 0000266h c0mdata6711 can0 message data byte 6 and 7 register 11 r/w undefined 0000266h c0mdata611 can0 message data byte 6 register 11 r/w undefined 0000267h c0mdata711 can0 message data byte 7 register 11 r/w undefined 0000268h c0mdlc11 can0 message data length code register 11 r/w undefined 0000269h c0mconf11 can0 message configuration register 11 r/w undefined 000026ah c0midl11 can0 message id entifier l register 11 r/w undefined 000026ch c0midh11 can0 message identifier h register 11 r/w undefined 000026eh c0mctrl11 can0 message control register 11 r/w undefined 0000280h c0mdata0112 can0 message data byte 0 and 1 register 12 r/w undefined 0000280h c0mdata012 can0 message data byte 0 register 12 r/w undefined 0000281h c0mdata112 can0 message data byte 1 register 12 r/w undefined 0000282h c0mdata2312 can0 message data byte 2 and 3 register 12 r/w undefined 0000282h c0mdata212 can0 message data byte 2 register 12 r/w undefined 0000283h c0mdata312 can0 message data byte 3 register 12 r/w undefined 0000284h c0mdata4512 can0 message data byte 4 and 5 register 12 r/w undefined 0000284h c0mdata412 can0 message data byte 2 register 12 r/w undefined 0000285h c0mdata512 can0 message data byte 3 register 12 r/w undefined 0000286h c0mdata6712 can0 message data byte 6 and 7 register 12 r/w undefined 0000286h c0mdata612 can0 message data byte 6 register 12 r/w undefined 0000287h c0mdata712 can0 message data byte 7 register 12 r/w undefined 0000288h c0mdlc12 can0 message data length code register 12 r/w undefined 0000289h c0mconf12 can0 message configuration register 12 r/w undefined 000028ah c0midl12 can0 message id entifier l register 12 r/w undefined 000028ch c0midh12 can0 message identifier h register 12 r/w undefined 000028eh c0mctrl12 can0 message control register 12 r/w undefined 00002a0h c0mdata0113 can0 message data byte 0 and 1 register 13 r/w undefined 00002a0h c0mdata013 can0 message data byte 0 register 13 r/w undefined 00002a1h c0mdata113 can0 message data byte 1 register 13 r/w undefined 00002a2h c0mdata2313 can0 message data byte 2 and 3 register 13 r/w undefined 00002a2h c0mdata213 can0 message data byte 2 register 13 r/w undefined 00002a3h c0mdata313 can0 message data byte 3 register 13 r/w undefined 00002a4h c0mdata4513 can0 message data byte 4 and 5 register 13 r/w undefined 00002a4h c0mdata413 can0 message data byte 2 register 13 r/w undefined 00002a5h c0mdata513 can0 message data byte 3 register 13 r/w undefined 00002a6h c0mdata6713 can0 message data byte 6 and 7 register 13 r/w undefined 00002a6h c0mdata613 can0 message data byte 6 register 13 r/w undefined 00002a7h c0mdata713 can0 message data byte 7 register 13 r/w undefined table 3-6: programmable peripheral i/o registers (7/16) address offset symbol function register name r/w bit units for manipulation after reset 1816
118 chapter 3 cpu functions user?s manual u16580ee2v0ud00 00002a8h c0mdlc13 can0 message data length code register 13 r/w undefined 00002a9h c0mconf13 can0 message configuration register 13 r/w undefined 00002aah c0midl13 can0 message identifier l register 13 r/w undefined 00002ach c0midh13 can0 message identifier h register 13 r/w undefined 00002aeh c0mctrl13 can0 message control register 13 r/w undefined 00002c0h c0mdata0114 can0 message data byte 0 and 1 register 14 r/w undefined 00002c0h c0mdata014 can0 message data byte 0 register 14 r/w undefined 00002c1h c0mdata114 can0 message data byte 1 register 14 r/w undefined 00002c2h c0mdata2314 can0 message data byte 2 and 3 register 14 r/w undefined 00002c2h c0mdata214 can0 message data byte 2 register 14 r/w undefined 00002c3h c0mdata314 can0 message data byte 3 register 14 r/w undefined 00002c4h c0mdata4514 can0 message data byte 4 and 5 register 14 r/w undefined 00002c4h c0mdata414 can0 message data byte 2 register 14 r/w undefined 00002c5h c0mdata514 can0 message data byte 3 register 14 r/w undefined 00002c6h c0mdata6714 can0 message data byte 6 and 7 register 14 r/w undefined 00002c6h c0mdata614 can0 message data byte 6 register 14 r/w undefined 00002c7h c0mdata714 can0 message data byte 7 register 14 r/w undefined 00002c8h c0mdlc14 can0 message data length code register 14 r/w undefined 00002c9h c0mconf14 can0 message configuration register 14 r/w undefined 00002cah c0midl14 can0 message identifier l register 14 r/w undefined 00002cch c0midh14 can0 message identifier h register 14 r/w undefined 00002ceh c0mctrl14 can0 message control register 14 r/w undefined 00002e0h c0mdata0115 can0 message data byte 0 and 1 register 15 r/w undefined 00002e0h c0mdata015 can0 message data byte 0 register 15 r/w undefined 00002e1h c0mdata115 can0 message data byte 1 register 15 r/w undefined 00002e2h c0mdata2315 can0 message data byte 2 and 3 register 15 r/w undefined 00002e2h c0mdata215 can0 message data byte 2 register 15 r/w undefined 00002e3h c0mdata315 can0 message data byte 3 register 15 r/w undefined 00002e4h c0mdata4515 can0 message data byte 4 and 5 register 15 r/w undefined 00002e4h c0mdata415 can0 message data byte 2 register 15 r/w undefined 00002e5h c0mdata515 can0 message data byte 3 register 15 r/w undefined 00002e6h c0mdata6715 can0 message data byte 6 and 7 register 15 r/w undefined 00002e6h c0mdata615 can0 message data byte 6 register 15 r/w undefined 00002e7h c0mdata715 can0 message data byte 7 register 15 r/w undefined 00002e8h c0mdlc15 can0 message data length code register 15 r/w undefined 00002e9h c0mconf15 can0 message configuration register 15 r/w undefined 00002eah c0midl15 can0 message identifier l register 15 r/w undefined 00002ech c0midh15 can0 message identifier h register 15 r/w undefined 00002eeh c0mctrl15 can0 message control register 15 r/w undefined table 3-6: programmable peripheral i/o registers (8/16) address offset symbol function register name r/w bit units for manipulation after reset 1816
119 chapter 3 cpu functions user?s manual u16580ee2v0ud00 0000600h c1gmctrl can1 global macro control register r/w 0000h 0000600h c1gmctrll can1 global macro control register l r/w 00h 0000601h c1gmctrlh can1 global macro control register h r/w 00h 0000602h c1gmcs can1 global macro clock selection register r/w 00h 0000606h c1gmabt can1 global macro automatic block transmission register r/w 0000h 0000606h c1gmabtl can1 global macro automatic block transmission register l r/w 00h 0000607h c1gmabth can1 global macro automatic block transmission register h r/w 00h 0000608h c1gmabtd can1 global macro automatic block transmission delay register r/w 00h 0000640h c1mask1l can1 module mask 1 register l r/w undefined 0000642h c1mask1h can1 module mask 1 register h r/w undefined 0000644h c1mask2l can1 module mask 2 register l r/w undefined 0000646h c1mask2h can1 module mask 2 register h r/w undefined 0000648h c1mask3l can1 module mask 3 register l r/w undefined 000064ah c1mask3h can1 module mask 3 register h r/w undefined 000064ch c1mask4l can1 module mask 4 register l r/w undefined 000064eh c1mask4h can1 module mask 4 register h r/w undefined 0000650h c1ctrl can1 module control register r/w 0000h 0000652h c1lec can1 module last error code register r/w 00h 0000653h c1info can1 module information register r 00h 0000654h c1erc can1 module error counter r/w 0000h 0000656h c1ie can1 module interrupt enable register r/w 0000h 0000656h c1iel can1 module interrupt enable register l r/w 00h 0000657h c1ieh can1 module interrupt enable register h r/w 00h 0000658h c1ints can1 module interrupt status register r/w 0000h 0000658h c1intsl can1 module interrupt status register l r/w 00h 000065ah c1brp can1 module bit-rate prescaler register r/w ffh 000065ch c1btr can1 bit-rate register r/w 370fh 000065eh c1lipt can1 module last in-pointer register r/w undefined 0000660h c1rgpt can1 module receive history list get pointer register r/w undefined 0000660h c1rgptl can1 module receive history list get pointer register l r/w 01h 0000662h c1lopt can1 module last out-pointer register r undefined 0000664h c1tgpt can1 module transmit history list get pointer register r/w undefined 0000664h c1tgptl can1 module transmit history list get pointer register l r/w 01h table 3-6: programmable peripheral i/o registers (9/16) address offset symbol function register name r/w bit units for manipulation after reset 1816
120 chapter 3 cpu functions user?s manual u16580ee2v0ud00 0000666h c1ts can1 module time stamp register r/w 0000h 0000666h c1tsl can1 module time stamp register l r/w 00h 0000667h c1tsh can1 module time stamp register h r/w 00h 0000700h c1mdata0100 can1 message data byte 0 and 1 register 00 r/w undefined 0000700h c1mdata000 can1 message data byte 0 register 00 r/w undefined 0000701h c1mdata100 can1 message data byte 1 register 00 r/w undefined 0000702h c1mdata2300 can1 message data byte 2 and 3 register 00 r/w undefined 0000702h c1mdata200 can1 message data byte 2 register 00 r/w undefined 0000703h c1mdata300 can1 message data byte 3 register 00 r/w undefined 0000704h c1mdata4500 can1 message data byte 4 and 5 register 00 r/w undefined 0000704h c1mdata400 can1 message data byte 2 register 00 r/w undefined 0000705h c1mdata500 can1 message data byte 3 register 00 r/w undefined 0000706h c1mdata6700 can1 message data byte 6 and 7 register 00 r/w undefined 0000706h c1mdata600 can1 message data byte 6 register 00 r/w undefined 0000707h c1mdata700 can1 message data byte 7 register 00 r/w undefined 0000708h c1mdlc00 can1 message data length code register 00 r/w undefined 0000709h c1mconf00 can1 message configuration register 00 r/w undefined 000070ah c1midl00 can1 message identifier l register 00 r/w undefined 000070ch c1midh00 can1 message identifier h register 00 r/w undefined 000070eh c1mctrl00 can1 message control register 00 r/w undefined 0000720h c1mdata0101 can1 message data byte 0 and 1 register 01 r/w undefined 0000720h c1mdata001 can1 message data byte 0 register 01 r/w undefined 0000721h c1mdata101 can1 message data byte 1 register 01 r/w undefined 0000722h c1mdata2301 can1 message data byte 2 and 3 register 01 r/w undefined 0000722h c1mdata201 can1 message data byte 2 register 01 r/w undefined 0000723h c1mdata301 can1 message data byte 3 register 01 r/w undefined 0000724h c1mdata4501 can1 message data byte 4 and 5 register 01 r/w undefined 0000724h c1mdata401 can1 message data byte 2 register 01 r/w undefined 0000725h c1mdata501 can1 message data byte 3 register 01 r/w undefined 0000726h c1mdata6701 can1 message data byte 6 and 7 register 01 r/w undefined 0000726h c1mdata601 can1 message data byte 6 register 01 r/w undefined 0000727h c1mdata701 can1 message data byte 7 register 01 r/w undefined 0000728h c1mdlc01 can1 message data length code register 01 r/w undefined 0000729h c1mconf01 can1 message configuration register 01 r/w undefined 000072ah c1midl01 can1 message identifier l register 01 r/w undefined 000072ch c1midh01 can1 message identifier h register 01 r/w undefined 000072eh c1mctrl01 can1 message control register 01 r/w undefined 0000740h c1mdata0102 can1 message data byte 0 and 1 register 02 r/w undefined 0000740h c1mdata002 can1 message data byte 0 register 02 r/w undefined 0000741h c1mdata102 can1 message data byte 1 register 02 r/w undefined table 3-6: programmable peripheral i/o registers (10/16) address offset symbol function register name r/w bit units for manipulation after reset 1816
121 chapter 3 cpu functions user?s manual u16580ee2v0ud00 0000742h c1mdata2302 can1 message data byte 2 and 3 register 02 r/w undefined 0000742h c1mdata202 can1 message data byte 2 register 02 r/w undefined 0000743h c1mdata302 can1 message data byte 3 register 02 r/w undefined 0000744h c1mdata4502 can1 message data byte 4 and 5 register 02 r/w undefined 0000744h c1mdata402 can1 message data byte 2 register 02 r/w undefined 0000745h c1mdata502 can1 message data byte 3 register 02 r/w undefined 0000746h c1mdata6702 can1 message data byte 6 and 7 register 02 r/w undefined 0000746h c1mdata602 can1 message data byte 6 register 02 r/w undefined 0000747h c1mdata702 can1 message data byte 7 register 02 r/w undefined 0000748h c1mdlc02 can1 message data length code register 02 r/w undefined 0000749h c1mconf02 can1 message configuration register 02 r/w undefined 000074ah c1midl02 can1 message id entifier l register 02 r/w undefined 000074ch c1midh02 can1 message identifier h register 02 r/w undefined 000074eh c1mctrl02 can1 message control register 02 r/w undefined 0000760h c1mdata0103 can1 message data byte 0 and 1 register 03 r/w undefined 0000760h c1mdata003 can1 message data byte 0 register 03 r/w undefined 0000761h c1mdata103 can1 message data byte 1 register 03 r/w undefined 0000762h c1mdata2303 can1 message data byte 2 and 3 register 03 r/w undefined 0000762h c1mdata203 can1 message data byte 2 register 03 r/w undefined 0000763h c1mdata303 can1 message data byte 3 register 03 r/w undefined 0000764h c1mdata4503 can1 message data byte 4 and 5 register 03 r/w undefined 0000764h c1mdata403 can1 message data byte 2 register 03 r/w undefined 0000765h c1mdata503 can1 message data byte 3 register 03 r/w undefined 0000766h c1mdata6703 can1 message data byte 6 and 7 register 03 r/w undefined 0000766h c1mdata603 can1 message data byte 6 register 03 r/w undefined 0000767h c1mdata703 can1 message data byte 7 register 03 r/w undefined 0000768h c1mdlc03 can1 message data length code register 03 r/w undefined 0000769h c1mconf03 can1 message configuration register 03 r/w undefined 000076ah c1midl03 can1 message id entifier l register 03 r/w undefined 000076ch c1midh03 can1 message identifier h register 03 r/w undefined 000076eh c1mctrl03 can1 message control register 03 r/w undefined 0000780h c1mdata0104 can1 message data byte 0 and 1 register 04 r/w undefined 0000780h c1mdata004 can1 message data byte 0 register 04 r/w undefined 0000781h c1mdata104 can1 message data byte 1 register 04 r/w undefined 0000782h c1mdata2304 can1 message data byte 2 and 3 register 04 r/w undefined 0000782h c1mdata204 can1 message data byte 2 register 04 r/w undefined 0000783h c1mdata304 can1 message data byte 3 register 04 r/w undefined 0000784h c1mdata4504 can1 message data byte 4 and 5 register 04 r/w undefined 0000784h c1mdata404 can1 message data byte 2 register 04 r/w undefined 0000785h c1mdata504 can1 message data byte 3 register 04 r/w undefined table 3-6: programmable peripheral i/o registers (11/16) address offset symbol function register name r/w bit units for manipulation after reset 1816
122 chapter 3 cpu functions user?s manual u16580ee2v0ud00 0000786h c1mdata6704 can1 message data byte 6 and 7 register 04 r/w undefined 0000786h c1mdata604 can1 message data byte 6 register 04 r/w undefined 0000787h c1mdata704 can1 message data byte 7 register 04 r/w undefined 0000788h c1mdlc04 can1 message data length code register 04 r/w undefined 0000789h c1mconf04 can1 message configuration register 04 r/w undefined 000078ah c1midl04 can1 message identifier l register 04 r/w undefined 000078ch c1midh04 can1 message identifier h register 04 r/w undefined 000078eh c1mctrl04 can1 message control register 04 r/w undefined 00007a0h c1mdata0105 can1 message data byte 0 and 1 register 05 r/w undefined 00007a0h c1mdata005 can1 message data byte 0 register 05 r/w undefined 00007a1h c1mdata105 can1 message data byte 1 register 05 r/w undefined 00007a2h c1mdata2305 can1 message data byte 2 and 3 register 05 r/w undefined 00007a2h c1mdata205 can1 message data byte 2 register 05 r/w undefined 00007a3h c1mdata305 can1 message data byte 3 register 05 r/w undefined 00007a4h c1mdata4505 can1 message data byte 4 and 5 register 05 r/w undefined 00007a4h c1mdata405 can1 message data byte 2 register 05 r/w undefined 00007a5h c1mdata505 can1 message data byte 3 register 05 r/w undefined 00007a6h c1mdata6705 can1 message data byte 6 and 7 register 05 r/w undefined 00007a6h c1mdata605 can1 message data byte 6 register 05 r/w undefined 00007a7h c1mdata705 can1 message data byte 7 register 05 r/w undefined 00007a8h c1mdlc05 can1 message data length code register 05 r/w undefined 00007a9h c1mconf05 can1 message configuration register 05 r/w undefined 00007aah c1midl05 can1 message identifier l register 05 r/w undefined 00007ach c1midh05 can1 message identifier h register 05 r/w undefined 00007aeh c1mctrl05 can1 message control register 05 r/w undefined 00007c0h c1mdata0106 can1 message data byte 0 and 1 register 06 r/w undefined 00007c0h c1mdata006 can1 message data byte 0 register 06 r/w undefined 00007c1h c1mdata106 can1 message data byte 1 register 06 r/w undefined 00007c2h c1mdata2306 can1 message data byte 2 and 3 register 06 r/w undefined 00007c2h c1mdata206 can1 message data byte 2 register 06 r/w undefined 00007c3h c1mdata306 can1 message data byte 3 register 06 r/w undefined 00007c4h c1mdata4506 can1 message data byte 4 and 5 register 06 r/w undefined 00007c4h c1mdata406 can1 message data byte 2 register 06 r/w undefined 00007c5h c1mdata506 can1 message data byte 3 register 06 r/w undefined 00007c6h c1mdata6706 can1 message data byte 6 and 7 register 06 r/w undefined 00007c6h c1mdata606 can1 message data byte 6 register 06 r/w undefined 00007c7h c1mdata706 can1 message data byte 7 register 06 r/w undefined 00007c8h c1mdlc06 can1 message data length code register 06 r/w undefined 00007c9h c1mconf06 can1 message configuration register 06 r/w undefined 00007cah c1midl06 can1 message identifier l register 06 r/w undefined table 3-6: programmable peripheral i/o registers (12/16) address offset symbol function register name r/w bit units for manipulation after reset 1816
123 chapter 3 cpu functions user?s manual u16580ee2v0ud00 00007cch c1midh06 can1 message identifier h register 06 r/w undefined 00007ceh c1mctrl06 can1 message control register 06 r/w undefined 00007e0h c1mdata0107 can1 message data byte 0 and 1 register 07 r/w undefined 00007e0h c1mdata007 can1 message data byte 0 register 07 r/w undefined 00007e1h c1mdata107 can1 message data byte 1 register 07 r/w undefined 00007e2h c1mdata2307 can1 message data byte 2 and 3 register 07 r/w undefined 00007e2h c1mdata207 can1 message data byte 2 register 07 r/w undefined 00007e3h c1mdata307 can1 message data byte 3 register 07 r/w undefined 00007e4h c1mdata4507 can1 message data byte 4 and 5 register 07 r/w undefined 00007e4h c1mdata407 can1 message data byte 2 register 07 r/w undefined 00007e5h c1mdata507 can1 message data byte 3 register 07 r/w undefined 00007e6h c1mdata6707 can1 message data byte 6 and 7 register 07 r/w undefined 00007e6h c1mdata607 can1 message data byte 6 register 07 r/w undefined 00007e7h c1mdata707 can1 message data byte 7 register 07 r/w undefined 00007e8h c1mdlc07 can1 message data length code register 07 r/w undefined 00007e9h c1mconf07 can1 message configuration register 07 r/w undefined 00007eah c1midl07 can1 message identifier l register 07 r/w undefined 00007ech c1midh07 can1 message identifier h register 07 r/w undefined 00007eeh c1mctrl07 can1 message control register 07 r/w undefined 0000800h c1mdata0108 can1 message data byte 0 and 1 register 08 r/w undefined 0000800h c1mdata008 can1 message data byte 0 register 08 r/w undefined 0000801h c1mdata108 can1 message data byte 1 register 08 r/w undefined 0000802h c1mdata2308 can1 message data byte 2 and 3 register 08 r/w undefined 0000802h c1mdata208 can1 message data byte 2 register 08 r/w undefined 0000803h c1mdata308 can1 message data byte 3 register 08 r/w undefined 0000804h c1mdata4508 can1 message data byte 4 and 5 register 08 r/w undefined 0000804h c1mdata408 can1 message data byte 2 register 08 r/w undefined 0000805h c1mdata508 can1 message data byte 3 register 08 r/w undefined 0000806h c1mdata6708 can1 message data byte 6 and 7 register 08 r/w undefined 0000806h c1mdata608 can1 message data byte 6 register 08 r/w undefined 0000807h c1mdata708 can1 message data byte 7 register 08 r/w undefined 0000808h c1mdlc08 can1 message data length code register 08 r/w undefined 0000809h c1mconf08 can1 message configuration register 08 r/w undefined 000080ah c1midl08 can1 message id entifier l register 08 r/w undefined 000080ch c1midh08 can1 message identifier h register 08 r/w undefined 000080eh c1mctrl08 can1 message control register 08 r/w undefined 0000820h c1mdata0109 can1 message data byte 0 and 1 register 09 r/w undefined 0000820h c1mdata009 can1 message data byte 0 register 09 r/w undefined 0000821h c1mdata109 can1 message data byte 1 register 09 r/w undefined table 3-6: programmable peripheral i/o registers (13/16) address offset symbol function register name r/w bit units for manipulation after reset 1816
124 chapter 3 cpu functions user?s manual u16580ee2v0ud00 0000822h c1mdata2309 can1 message data byte 2 and 3 register 09 r/w undefined 0000822h c1mdata209 can1 message data byte 2 register 09 r/w undefined 0000823h c1mdata309 can1 message data byte 3 register 09 r/w undefined 0000824h c1mdata4509 can1 message data byte 4 and 5 register 09 r/w undefined 0000824h c1mdata409 can1 message data byte 2 register 09 r/w undefined 0000825h c1mdata509 can1 message data byte 3 register 09 r/w undefined 0000826h c1mdata6709 can1 message data byte 6 and 7 register 09 r/w undefined 0000826h c1mdata609 can1 message data byte 6 register 09 r/w undefined 0000827h c1mdata709 can1 message data byte 7 register 09 r/w undefined 0000828h c1mdlc09 can1 message data length code register 09 r/w undefined 0000829h c1mconf09 can1 message configuration register 09 r/w undefined 000082ah c1midl09 can1 message identifier l register 09 r/w undefined 000082ch c1midh09 can1 message identifier h register 09 r/w undefined 000082eh c1mctrl09 can1 message control register 09 r/w undefined 0000840h c1mdata0110 can1 message data byte 0 and 1 register 10 r/w undefined 0000840h c1mdata010 can1 message data byte 0 register 10 r/w undefined 0000841h c1mdata110 can1 message data byte 1 register 10 r/w undefined 0000842h c1mdata2310 can1 message data byte 2 and 3 register 10 r/w undefined 0000842h c1mdata210 can1 message data byte 2 register 10 r/w undefined 0000843h c1mdata310 can1 message data byte 3 register 10 r/w undefined 0000844h c1mdata4510 can1 message data byte 4 and 5 register 10 r/w undefined 0000844h c1mdata410 can1 message data byte 2 register 10 r/w undefined 0000845h c1mdata510 can1 message data byte 3 register 10 r/w undefined 0000846h c1mdata6710 can1 message data byte 6 and 7 register 10 r/w undefined 0000846h c1mdata610 can1 message data byte 6 register 10 r/w undefined 0000847h c1mdata710 can1 message data byte 7 register 10 r/w undefined 0000848h c1mdlc10 can1 message data length code register 10 r/w undefined 0000849h c1mconf10 can1 message configuration register 10 r/w undefined 000084ah c1midl10 can1 message identifier l register 10 r/w undefined 000084ch c1midh10 can1 message identifier h register 10 r/w undefined 000084eh c1mctrl10 can1 message control register 10 r/w undefined 0000860h c1mdata0111 can1 message data byte 0 and 1 register 11 r/w undefined 0000860h c1mdata011 can1 message data byte 0 register 11 r/w undefined 0000861h c1mdata111 can1 message data byte 1 register 11 r/w undefined 0000862h c1mdata2311 can1 message data byte 2 and 3 register 11 r/w undefined 0000862h c1mdata211 can1 message data byte 2 register 11 r/w undefined 0000863h c1mdata311 can1 message data byte 3 register 11 r/w undefined 0000864h c1mdata4511 can1 message data byte 4 and 5 register 11 r/w undefined 0000864h c1mdata411 can1 message data byte 2 register 11 r/w undefined 0000865h c1mdata511 can1 message data byte 3 register 11 r/w undefined table 3-6: programmable peripheral i/o registers (14/16) address offset symbol function register name r/w bit units for manipulation after reset 1816
125 chapter 3 cpu functions user?s manual u16580ee2v0ud00 0000866h c1mdata6711 can1 message data byte 6 and 7 register 11 r/w undefined 0000866h c1mdata611 can1 message data byte 6 register 11 r/w undefined 0000867h c1mdata711 can1 message data byte 7 register 11 r/w undefined 0000868h c1mdlc11 can1 message data length code register 11 r/w undefined 0000869h c1mconf11 can1 message configuration register 11 r/w undefined 000086ah c1midl11 can1 message id entifier l register 11 r/w undefined 000086ch c1midh11 can1 message identifier h register 11 r/w undefined 000086eh c1mctrl11 can1 message control register 11 r/w undefined 0000880h c1mdata0112 can1 message data byte 0 and 1 register 12 r/w undefined 0000880h c1mdata012 can1 message data byte 0 register 12 r/w undefined 0000881h c1mdata112 can1 message data byte 1 register 12 r/w undefined 0000882h c1mdata2312 can1 message data byte 2 and 3 register 12 r/w undefined 0000882h c1mdata212 can1 message data byte 2 register 12 r/w undefined 0000883h c1mdata312 can1 message data byte 3 register 12 r/w undefined 0000884h c1mdata4512 can1 message data byte 4 and 5 register 12 r/w undefined 0000884h c1mdata412 can1 message data byte 2 register 12 r/w undefined 0000885h c1mdata512 can1 message data byte 3 register 12 r/w undefined 0000886h c1mdata6712 can1 message data byte 6 and 7 register 12 r/w undefined 0000886h c1mdata612 can1 message data byte 6 register 12 r/w undefined 0000887h c1mdata712 can1 message data byte 7 register 12 r/w undefined 0000888h c1mdlc12 can1 message data length code register 12 r/w undefined 0000889h c1mconf12 can1 message configuration register 12 r/w undefined 000088ah c1midl12 can1 message id entifier l register 12 r/w undefined 000088ch c1midh12 can1 message identifier h register 12 r/w undefined 000088eh c1mctrl12 can1 message control register 12 r/w undefined 00008a0h c1mdata0113 can1 message data byte 0 and 1 register 13 r/w undefined 00008a0h c1mdata013 can1 message data byte 0 register 13 r/w undefined 00008a1h c1mdata113 can1 message data byte 1 register 13 r/w undefined 00008a2h c1mdata2313 can1 message data byte 2 and 3 register 13 r/w undefined 00008a2h c1mdata213 can1 message data byte 2 register 13 r/w undefined 00008a3h c1mdata313 can1 message data byte 3 register 13 r/w undefined 00008a4h c1mdata4513 can1 message data byte 4 and 5 register 13 r/w undefined 00008a4h c1mdata413 can1 message data byte 2 register 13 r/w undefined 00008a5h c1mdata513 can1 message data byte 3 register 13 r/w undefined 00008a6h c1mdata6713 can1 message data byte 6 and 7 register 13 r/w undefined 00008a6h c1mdata613 can1 message data byte 6 register 13 r/w undefined 00008a7h c1mdata713 can1 message data byte 7 register 13 r/w undefined 00008a8h c1mdlc13 can1 message data length code register 13 r/w undefined 00008a9h c1mconf13 can1 message configuration register 13 r/w undefined 00008aah c1midl13 can1 message identifier l register 13 r/w undefined table 3-6: programmable peripheral i/o registers (15/16) address offset symbol function register name r/w bit units for manipulation after reset 1816
126 chapter 3 cpu functions user?s manual u16580ee2v0ud00 00008ach c1midh13 can1 message identifier h register 13 r/w undefined 00008aeh c1mctrl13 can1 message control register 13 r/w undefined 00008c0h c1mdata0114 can1 message data byte 0 and 1 register 14 r/w undefined 00008c0h c1mdata014 can1 message data byte 0 register 14 r/w undefined 00008c1h c1mdata114 can1 message data byte 1 register 14 r/w undefined 00008c2h c1mdata2314 can1 message data byte 2 and 3 register 14 r/w undefined 00008c2h c1mdata214 can1 message data byte 2 register 14 r/w undefined 00008c3h c1mdata314 can1 message data byte 3 register 14 r/w undefined 00008c4h c1mdata4514 can1 message data byte 4 and 5 register 14 r/w undefined 00008c4h c1mdata414 can1 message data byte 2 register 14 r/w undefined 00008c5h c1mdata514 can1 message data byte 3 register 14 r/w undefined 00008c6h c1mdata6714 can1 message data byte 6 and 7 register 14 r/w undefined 00008c6h c1mdata614 can1 message data byte 6 register 14 r/w undefined 00008c7h c1mdata714 can1 message data byte 7 register 14 r/w undefined 00008c8h c1mdlc14 can1 message data length code register 14 r/w undefined 00008c9h c1mconf14 can1 message configuration register 14 r/w undefined 00008cah c1midl14 can1 message identifier l register 14 r/w undefined 00008cch c1midh14 can1 message identifier h register 14 r/w undefined 00008ceh c1mctrl14 can1 message control register 14 r/w undefined 00008e0h c1mdata0115 can1 message data byte 0 and 1 register 15 r/w undefined 00008e0h c1mdata015 can1 message data byte 0 register 15 r/w undefined 00008e1h c1mdata115 can1 message data byte 1 register 15 r/w undefined 00008e2h c1mdata2315 can1 message data byte 2 and 3 register 15 r/w undefined 00008e2h c1mdata215 can1 message data byte 2 register 15 r/w undefined 00008e3h c1mdata315 can1 message data byte 3 register 15 r/w undefined 00008e4h c1mdata4515 can1 message data byte 4 and 5 register 15 r/w undefined 00008e4h c1mdata415 can1 message data byte 2 register 15 r/w undefined 00008e5h c1mdata515 can1 message data byte 3 register 15 r/w undefined 00008e6h c1mdata6715 can1 message data byte 6 and 7 register 15 r/w undefined 00008e6h c1mdata615 can1 message data byte 6 register 15 r/w undefined 00008e7h c1mdata715 can1 message data byte 7 register 15 r/w undefined 00008e8h c1mdlc15 can1 message data length code register 15 r/w undefined 00008e9h c1mconf15 can1 message configuration register 15 r/w undefined 00008eah c1midl15 can1 message identifier l register 15 r/w undefined 00008ech c1midh15 can1 message identifier h register 15 r/w undefined 00008eeh c1mctrl15 can1 message control register 15 r/w undefined table 3-6: programmable peripheral i/o registers (16/16) address offset symbol function register name r/w bit units for manipulation after reset 1816
127 chapter 3 cpu functions user?s manual u16580ee2v0ud00 3.4.8 specific registers specific registers are registers that prevent invalid data from being written if an inadvertent program behaviour occurs. the v850e/ph2 has the following specific registers: ? port registers 5 and 6 (p5, p6) ? port mode registers 5 and 6 (pm5, pm6) ? port mode control registers 5 and 6 (pmc5, pmc6) ? port emergency shut off contro l registers 5 and 6 (pesc5, pesc6) ? port emergency shut off status registers 5 and 6 (esost5, esost6) moreover, there is also a command register (prcmd ), which is a protection register against write operations to the specific registers. write access to the specific registers is performed with a special sequence and illegal store operat ions are notified to the syst em status register (phs). this section of the manual describes the access me thod to these specific registers, rather than the values that can be written to these registers. for details on these register values, please refer to sections 20.3.6 ?port 5? on page 909 and 20.3.7 ?port 6? on page 914 . (1) setting data to specific registers setting data to a specific registers is done in the following sequence. <1> prepare the data to be set to the special register in a general-purpose register. <2> write the data prepared in <1> to the command register (prcmd). <3> write the data to the specific regi ster (using the following instructions). ? store instruction (st/sst instruction) ? bit manipulation instruction (set1/clr1/not1 instruction) example <1> mov 0x02, r10 ; prepare data in r10 <2> st.b r10, prcmd[r0] ; write prcmd register <3> st.b r10, p5 ; set p5 register (next instruction) cautions: 1. interrupts are not acknowledged when executing the store instruction to the prcmd register. if another instruction is placed between steps <2> and <3>, the correct sequence may not be realized if an interrupt is acknowledged for that instruction, resulting in the writing to the protected register to be not done, and an error to be stored in the prerr bit of the phs register. 2. if there is a possibility of an active dma register before <2> and <3>, the specific register may not be written. in this case, ensure that no dma register is active during the sequence <2> to <3>, or repeat the sequencer <2> to <3> as long as the prerr bit of the phs register is set to <1>.
128 chapter 3 cpu functions user?s manual u16580ee2v0ud00 (2) processor command register (prcmd) the prcmd register is an 8-bit register used to prevent data from being written to registers that may have a large influence on the system, possibly causing the application system to unexpectedly stop. only the first write operation to a specific register following the execution of a write operation to the pr cmd register, is valid. as a result, register values can be overwritte n only using a preset sequence, preventing invalid write operations. prcmd register must be written with store instruction execution by cpu only (not with dma transfer). if an illegal store operatio n to a command or specific regist er takes place, it is reported by the prerr flag of the system status register (phs). this register can be written in 8-bit units onl y. undefined data is read from this register. figure 3-21: processor command register (prcmd) after reset: undefined w address: fffff1fch 76543210 prcmd reg7 reg6 reg5 reg4 reg3 reg2 reg1 reg0
129 chapter 3 cpu functions user?s manual u16580ee2v0ud00 (3) system status register (phs) the phs register is an 8-bit register to wh ich the prerr flag showing the generation of protection errors is assigned. if a write operation to a specific register has not been executed in the correct sequence including the access to the command register (prcmd), the write operation to the intended register is not executed, a protection error is generated and the prer r flag is set to 1. the value of this register becomes ?00h? by reset input. this register can be read/written in 8-bit and 1-bit units. figure 3-22: system status register format phs the prerr flag operates under the following conditions. (a) setting condition (prerr flag = 1) ? when a write operation is not performed on the prcmd register and an operation to write a specific register is performed (when <4> in the example 3.4.8 (1) setting data to specific registers is executed without <3>). ? if a write operation (including a bit manipulation instruction) is performed on an on-chip peripheral i/o register other than a specific register after a write operation to the prcmd register (when <4> in the example 3.4.8 (1) setting data to specific registers is not performed for a specific register). remark: even if an on-chip peripheral i/o register is read (including a bit manipulation instruction) between writing the prcmd register and writing a specific register (such as an access to the internal ram), the prerr flag is not set, and data can be written to the special register. (b) clearing condition (preer flag = 0) ? when 0 is written to the prerr flag of the phs register. ? when system reset is executed. cautions: 1. if 0 is written to the prerr bit of the phs register (that is not a specific register) immediately following write to the prcmd register, the prerr bit becomes 0 (write priority). 2. if data is written to the prcmd register (that is not a specific registers) immediately following write to the prcmd register, the prerr bit becomes 1. after reset: 00h r/w address: fffff802h 76543210 phs 0000000prerr prerr detection of protection error 0 protection error did not occur 1 protection error occurred
130 chapter 3 cpu functions user?s manual u16580ee2v0ud00 3.4.9 system wait control register (vswc) the system wait control register (vswc) is a register that controls the bus access wait for the on-chip peripheral i/o registers. access to on-chip peripheral i/o registers is made in 3 clocks (without wait), however, in the v850e/ph2 waits may be required depending on the operation frequency. set the values described in the table below to the vswc register in accordance with the operation frequency used. this register can be read or written in 1-bit or 8-bit units. 3.4.10 dma wait control registers 0 and 1 (dmawc0, dmawc1) the dma wait control registers 0 and 1 (dmawc0, dmawc1) are a registers that control the bus access wait and signal timing for dma transfers. set the values described in the table below to the dmawc0 and dmawc1 registers in accordance with the operation frequency used. this register can be read or written in 1-bit or 8-bit units. register name operating frequency set value address after reset vswc 64 mhz 13h fffff06eh 77h register name operating frequency set value address after reset dmawc0 64 mhz 13h fffffe00h 37h dmawc1 04h fffffe02h 07h
131 chapter 3 cpu functions user?s manual u16580ee2v0ud00 3.4.11 cautions ? initialize the following registers immediately after reset signal release in the following sequence: - system wait control register (vswc) (refer to 3.4.9 system wait control register (vswc) ) - dma wait control registers 0 and 1 (dmawc0,dmawc1) (refer to 3.4.10 dma wait control registers 0 and 1 (dmawc0, dmawc1) )
132 user?s manual u16580ee2v0ud00 [memo]
133 user?s manual u16580ee2v0ud00 chapter 4 bus control function the v850e/ph2 is provided with an external bus in terface function by which external memories, such as rom and ram, and external i/o can be connected. 4.1 features ? 32-bit/16-bit/8-bit data bus sizing function ? 8 chip areas select function ? 4 chip area select signal s externally available (cs0 , cs1 , cs3 and cs4 ) ? wait function - programmable wait function, capable of inserting up to 7 wait states for each memory block - external wait function via wait pin ? idle state insertion function ? external device connection can be enabled via bus control/port alternate function pins ? programmable endian format (little endian/big endian) 4.2 bus control pins the following pins are used for connecting to external devices. bus control pin (function when in control mode) function when in port mode register for port/ control mode switching data bus (d0 to d15) pdl0 to pdl15 (port dl) pmcdl data bus (d16 to d31) pdh0 to pdh15 (port dh) pmcdh address bus (a0 to a15) pal0 to pal15 (port al) pmcal address bus (a16 to a21) pah0 to pah5 (port ah) pmcah chip select (cs0 , cs1 , cs3 and cs4 ) pcs0, pcs1, pcs3 and pcs4 (port cs) pmccs read/write control (rd ,wr ) pct4, pct5 (port ct) pmcct byte enable control (be0 to be3 ) pcd2 to pcd5 (port cd) pmccd external wait control (wait ) pcm0 (port cm) pmccm
134 chapter 4 bus control function user?s manual u16580ee2v0ud00 4.3 memory block function the 64 mb memory space is divided into memory blocks of 2 mb, 4 mb, and 8 mb units. figure 4-1: memory block function 3ffffffh 3ffffffh internal peripheral i/o area (4 kbytes) internal ram area (32 kbytes) external memory area 3ff0000h 3e00000h 3dfffffh 3fff000h 3ff7fffh 3c00000h 3bfffffh 3a00000h 39fffffh 3800000h 37fffffh 3400000h 33fffffh 3000000h 2ffffffh 2800000h 27fffffh 1000000h 0ffffffh 0c00000h 0bfffffh 0400000h 03fffffh 0200000h 01fffffh 0000000h block 1 (2 mbytes) block 0 (2 mbytes) block 3 (2 mbytes) block 13 (2 mbytes) block 14 (2 mbytes) block 12 (2 mbytes) block 15 (2 mbytes) cs7, cs5, cs6, cs4 cs6, cs4 cs4 cs3 block 11 (4 mbytes) block 10 (4 mbytes) block 9 (8 mbytes) block 8 (8 mbytes) block 7 (8 mbytes) block 6 (8 mbytes) 2000000h 1ffffffh 1800000h 17fffffh block 5 (4 mbytes) 0800000h 07fffffh block 4 (4 mbytes) block 2 (2 mbytes) 0600000h 05fffffh cs1, cs3 cs0, cs2, cs1, cs3
135 chapter 4 bus control function user?s manual u16580ee2v0ud00 4.3.1 chip select control function the 64 mb memory area can be divided into 2 mb, 4 mb and 8 mb memory blocks by the chip area selection control registers 0 and 1 (csc0, csc1) to control the chip select signals. the memory area can be effectively used by dividing the memory area into memory blocks using the chip select control function. the priority order is described below. (1) chip area selection control registers 0, 1 (csc0, csc1) these registers can be read/written in 16-bit units. valid by setting each bit (to 1). if different chip area select signals are set to the same block, the priority order is controlled as follows. csc0: peripheral i/o area > cs0 > cs2 > cs1 > cs3 note csc1: peripheral i/o area > cs7 > cs5 > cs6 > cs4 note note: not all the chip area select signals are externally available on output pins. even so, enabling chip area select signals other than cs0 , cs1 , cs3 or cs4 , the setting for the corresponding memory blocks will be effective too, regardless of an external chip select output pin. figure 4-2: chip area select control registers 0, 1 (1/2) after reset: 2c11h r/w address: fffff060h 1514131211109876543210 csc0 cs33 cs32 cs31 cs30 cs23 cs22 cs21 cs20 cs13 cs12 cs11 cs10 cs03 cs02 cs01 cs00 cs3 cs2 cs1 cs0 after reset: 2c11h r/w address: fffff062h 1514131211109876543210 csc1 cs43 cs42 cs41 cs40 cs53 cs52 cs51 cs50 cs63 cs62 cs61 cs60 cs73 cs72 cs71 cs70 cs4 cs5 cs6 cs7
136 chapter 4 bus control function user?s manual u16580ee2v0ud00 figure 4-2: chip area select control registers 0, 1 (2/2) csnm chip select operation cs00 cs0 active during block 0 access cs01 cs0 active during block 1 access. cs02 cs0 active during block 2 access. cs03 cs0 active during block 3 access. cs10 cs1 active during block 0 or 1 access. cs11 cs1 active during block 2 or 3 access. cs12 cs1 active during block 4 access. cs13 cs1 active during block 5 access. cs20 cs2 active during block 0 access. cs21 cs2 active during block 1 access. cs22 cs2 active during block 2 access. cs23 cs2 active during block 3 access. cs30 cs3 active during block 0, 1, 2, or 3 access. cs31 cs3 active during block 4 or 5 access. cs32 cs3 active during block 6 access. cs33 cs3 active during block 7 access. cs40 cs4 active during block 12, 13, 14, or 15 access. cs41 cs4 active during block 10 or 11 access. cs42 cs4 active during block 9 access. cs43 cs4 active during block 8 access. cs50 cs5 active during block 15 access. cs51 cs5 active during block 14 access. cs52 cs5 active during block 13 access. cs53 cs5 active during block 12 access. cs60 cs6 active during block 14 or 15 access. cs61 cs6 active during block 12 or 13 access. cs62 cs6 active during block 11 access. cs63 cs6 active during block 10 access. cs70 cs7 active during block 15 access. cs71 cs7 active during block 14 access. cs72 cs7 active during block 13 access. cs73 cs7 active during block 12 access. remark: dedicated chip select operation is enabled when corresponding csnm bit is set (1), and disabled when csnm is cleared (0) (n = 0 to 7, m = 0 to 3)
137 chapter 4 bus control function user?s manual u16580ee2v0ud00 4.4 bus cycle type control function in the v850e/ph2, the following external devices ca n be connected directly to each memory block. ? sram, external rom, external i/o connected external devices are specified by the bus cycle type configuration registers 0, 1 (bct0, bct1).
138 chapter 4 bus control function user?s manual u16580ee2v0ud00 4.4.1 bus cycle type configuration (1) bus cycle configuration registers 0, 1 (bct0, bct1) these registers can be read/written in 16-bit units cautions: 1. write to the bct0 and bct1 registers after reset, and then do not change the set value. also, do not access an external memory area other than that for this initialization routine until initial setting of the bct0 and bct1 registers is finished. however, it is possible to access external memory areas whose initialization has been finished. 2. the bits marked as 0 and 1 are reserved. the values of these bits must not be changed. otherwise the operation of the external bus interface cannot be ensured. figure 4-3: bus cycle configuration registers 0, 1 (bct0, bct1) after reset: cccch r/w address: fffff480h 1514131211109876543210 bct0 me3100me2100me1100me0100 cs3 cs2 cs1 cs0 after reset: cccch r/w address: fffff482h 1514131211109876543210 bct1 me7100me6100me5100me4100 cs7 cs6 cs5 cs4 men memory controller operation enable for csn area 0 operation disable 1 operation enable
139 chapter 4 bus control function user?s manual u16580ee2v0ud00 4.5 bus access 4.5.1 number of access clocks the number of basic clocks necessary fo r accessing each resource is as follows. notes: 1. the instruction fetch becomes 2 clocks, in case of contention with data access. 2. this is the minimum value. table 4-1: number of bus access clocks resources (bus width) internal ram (32 bits) peripheral i/o (16 bits) external memory (16 bits) bus cycle configuration instruction fetch normal access 1 note 1 - 2 note 2 branch 1 - 2 note 2 operand data access 1 3 note 2 2 note 2
140 chapter 4 bus control function user?s manual u16580ee2v0ud00 4.5.2 bus sizing function the bus sizing function controls data bus width fo r each cs area. the data bus width is specified by using the bus size configuration register (bsc). (1) bus size configuration register (bsc) this register can be read/written in 16-bit units. caution: write to the bsc register after reset, and then do not change the set value. also, do not access an external memory area other than that for this initialization routine until initial setting of the bsc register is finished. however, it is possible to access external memory areas whose initialization has been finished. figure 4-4: bus size confi guration register (bsc) after reset: aaaah r/w address: fffff066h 1514131211109876543210 bsc bs71 bs70 bs61 bs60 bs51 bs50 bs41 bs40 bs31 bs30 bs21 bs20 bs11 bs10 bs01 bs00 cs7 cs6 cs5 cs4 cs3 cs2 cs1 cs0 ben1 ben0 data bus width of csn area 0 0 8 bits 0 1 16 bits 1 0 32 bits 1 1 setting prohibited
141 chapter 4 bus control function user?s manual u16580ee2v0ud00 4.5.3 endian control function the endian control function can be used to set processing of word data in memory either by the big endian method or the little endian method for each cs area selected with the chip select signal (cs0 to cs7 ). switching of the endian method is specified with the endian configuration register (bec). figure 4-5: big endian addresses within word figure 4-6: little endian addresses within word 0008h 0009h 000ah 000bh 0004h 0005h 0006h 0007h 0000h 0001h 0002h 0003h 31 24 23 16 17 8 7 0 000bh 000ah 0009h 0008h 0007h 0006h 0005h 0004h 0003h 0002h 0001h 0000h 31 24 23 16 17 8 7 0
142 chapter 4 bus control function user?s manual u16580ee2v0ud00 (1) endian configuration register (bec) this register can be read/written in 16-bit units. cautions: 1. bits 15, 13, 11, 9, 7, 5, 3, and 1 of the bec register must be cleared (0). if these bits are set to 1, the operation is not guaranteed. 2. set the csn area specified as the programmable peripheral i/o area to little endian format (n = 0 to 7). 3. in the following areas, the data processing method is fixed to little endian method. any setting of big endian method for these areas according to the bec register is invalid. - on-chip peripheral i/o area - internal ram area - fetch area of external memory figure 4-7: endian configuration register (bec) after reset: 0000h r/w address: fffff068h 1514131211109876543210 bec 0 be70 0 be60 0 be50 0 be40 0 be30 0 be20 0 be10 0 be00 cs7 cs6 cs5 cs4 cs3 cs2 cs1 cs0 ben0 endian control 0 little endian method 1 big endian method
143 chapter 4 bus control function user?s manual u16580ee2v0ud00 4.5.4 bus width the v850e/ph2 accesses peripheral i/o and external memory in 8-bit, 16-bit, or 32-bit units. the fol- lowing shows the operation for each type of access. access all data in order starting from the lower order side. (1) byte access (8 bits) (a) when the data bus width is 32 bits (little endian) (b) when the data bus width is 16 bits (little endian) <1> access to address (4n) <2> access to address (4n+1) <3> access to address (4n+2) <4> access to address (4n+3) 7 0 7 0 15 8 23 16 31 24 byte data external data bus address 4n 7 0 7 0 15 8 23 16 31 24 byte data external data bus address 4n + 1 7 0 7 0 15 8 23 16 31 24 byte data external data bus address 4n + 2 7 0 7 0 15 8 23 16 31 24 byte data external data bus address 4n + 3 <1> access to address (4n) <2> access to address (4n+1) <3> access to address (4n+2) <4> access to address (4n+3) 7 0 7 0 byte data 15 8 external data bus 4n address 7 0 7 0 15 8 4n + 1 address byte data external data bus 7 0 7 0 byte data 15 8 external data bus 4n + 2 address 7 0 7 0 15 8 4n + 3 address byte data external data bus
144 chapter 4 bus control function user?s manual u16580ee2v0ud00 (c) when the data bus width is 8 bits (little endian) (d) when the data bus width is 32 bits (big endian) <1> access to address (4n) <2> access to address (4n+1) <3> access to address (4n+2) <4> access to address (4n+3) 7 0 7 0 4n address byte data external data bus 7 0 7 0 4n + 1 address byte data external data bus 7 0 7 0 4n + 2 address byte data external data bus 7 0 7 0 4n + 3 address byte data external data bus <1> access to address (4n) <2> access to address (4n+1) <3> access to address (4n+2) <4> access to address (4n+3) 7 0 7 0 15 8 23 16 31 24 byte data external data bus address 4n 7 0 7 0 15 8 23 16 31 24 byte data external data bus address 4n + 1 7 0 7 0 15 8 23 16 31 24 byte data external data bus address 4n + 2 7 0 7 0 15 8 23 16 31 24 byte data external data bus address 4n + 3
145 chapter 4 bus control function user?s manual u16580ee2v0ud00 (e) when the data bus width is 16 bits (big endian) (f) when the data bus width is 8 bits (big endian) <1> access to address (4n) <2> access to address (4n+1) <3> access to address (4n+2) <4> access to address (4n+3) 7 0 7 0 15 8 4n address byte data external data bus 7 0 7 0 byte data 15 8 external data bus 4n + 1 address 7 0 7 0 15 8 4n + 2 address byte data external data bus 7 0 7 0 byte data 15 8 external data bus 4n + 3 address <1> access to address (4n) <2> access to address (4n+1) <3> access to address (4n+2) <4> access to address (4n+3) 7 0 7 0 4n address byte data external data bus 7 0 7 0 4n + 1 address byte data external data bus 7 0 7 0 4n + 2 address byte data external data bus 7 0 7 0 4n + 3 address byte data external data bus
146 chapter 4 bus control function user?s manual u16580ee2v0ud00 (2) halfword access (16 bits) (a) when the data bus width is 32 bits (little endian) <1> access to address (4n) <2> access to address (4n+1) <3> access to address (4n+2) <4> access to address (4n+3) 7 0 7 0 15 8 15 8 23 16 31 24 external data bus address 4n 4n + 1 halfword data 7 0 7 0 15 8 15 8 23 16 31 24 external data bus address 4n + 1 4n + 2 halfword data 7 0 7 0 15 8 15 8 23 16 31 24 external data bus address 4n + 2 4n + 3 halfword data 7 0 7 0 15 8 15 8 23 16 31 24 external data bus address 4n + 3 7 0 7 0 15 8 15 8 23 16 31 24 external data bus address 4n + 4 halfword data halfword data 1st access 2nd access
147 chapter 4 bus control function user?s manual u16580ee2v0ud00 (b) when the data bus width is 16 bits (little endian) <1> access to address (4n) <2> access to address (4n+1) <3> access to address (4n+2) <4> access to address (4n+3) 7 0 7 0 15 8 15 8 external data bus 4n 4n + 1 address halfword data 7 0 7 0 15 8 15 8 external data bus 4n + 1 address 7 0 7 0 15 8 15 8 external data bus 4n + 2 address halfword data halfword data 1st access 2nd access 7 0 7 0 15 8 15 8 external data bus 4n + 2 4n + 3 address halfword data 7 0 7 0 15 8 15 8 external data bus 4n + 3 address 7 0 7 0 15 8 15 8 external data bus 4n + 4 address halfword data halfword data 1st access 2nd access
148 chapter 4 bus control function user?s manual u16580ee2v0ud00 (c) when the data bus width is 8 bits (little endian) <1> access to address (4n) <2> access to address (4n+1) <3> access to address (4n+2) <4> access to address (4n+3) 7 0 7 0 halfword data halfword data 15 8 external data bus 4n address address 7 0 7 0 15 8 external data bus 4n + 1 1st access 2nd access 7 0 7 0 15 8 external data bus 4n + 1 address address 7 0 7 0 15 8 external data bus 4n + 2 halfword data halfword data 1st access 2nd access 7 0 7 0 15 8 external data bus 4n + 2 address address 7 0 7 0 15 8 external data bus 4n + 3 halfword data halfword data 1st access 2nd access 7 0 7 0 15 8 external data bus 4n + 3 address address 7 0 7 0 15 8 external data bus 4n + 4 halfword data halfword data 1st access 2nd access
149 chapter 4 bus control function user?s manual u16580ee2v0ud00 (d) when the data bus width is 32 bits (big endian) <1> access to address (4n) <2> access to address (4n+1) <3> access to address (4n+2) <4> access to address (4n+3) 7 0 7 0 15 8 15 8 23 16 31 24 external data bus address 4n + 1 4n halfword data 7 0 7 0 15 8 15 8 23 16 31 24 external data bus address 4n + 2 4n + 1 halfword data 7 0 7 0 15 8 15 8 23 16 31 24 external data bus address 4n + 3 4n + 2 halfword data 7 0 7 0 15 8 15 8 23 16 31 24 external data bus address 4n + 3 7 0 7 0 15 8 15 8 23 16 31 24 external data bus address 4n + 4 halfword data halfword data 1st access 2nd access
150 chapter 4 bus control function user?s manual u16580ee2v0ud00 (e) when the data bus width is 16 bits (big endian) <1> access to address (4n) <2> access to address (4n+1) <3> access to address (4n+2) <4> access to address (4n+3) 7 0 7 0 15 8 15 8 external data bus 4n + 1 4n address halfword data 7 0 7 0 15 8 15 8 external data bus 4n + 1 address 7 0 7 0 15 8 15 8 external data bus 4n + 2 address halfword data halfword data 1st access 2nd access 7 0 7 0 15 8 15 8 external data bus 4n + 3 4n + 2 address halfword data 7 0 7 0 15 8 15 8 external data bus 4n + 3 address 7 0 7 0 15 8 15 8 external data bus 4n + 4 address halfword data halfword data 1st access 2nd access
151 chapter 4 bus control function user?s manual u16580ee2v0ud00 (f) when the data bus width is 8 bits (big endian) <1> access to address (4n) <2> access to address (4n+1) <3> access to address (4n+2) <4> access to address (4n+3) 7 0 7 0 15 8 external data bus 4n address address 7 0 7 0 15 8 external data bus 4n + 1 halfword data halfword data 1st access 2nd access 7 0 7 0 15 8 external data bus 4n + 1 address address 7 0 7 0 15 8 external data bus 4n + 2 halfword data halfword data 1st access 2nd access 7 0 7 0 15 8 external data bus 4n + 2 address address 7 0 7 0 15 8 external data bus 4n + 3 halfword data halfword data 1st access 2nd access 7 0 7 0 15 8 external data bus 4n + 3 address address 7 0 7 0 15 8 external data bus 4n + 4 halfword data halfword data 1st access 2nd access
152 chapter 4 bus control function user?s manual u16580ee2v0ud00 (3) word access (32 bits) (a) when the bus width is 32 bits (little endian) <1> access to address (4n) <2> access to address (4n+1) <3> access to address (4n+2) <4> access to address (4n+3) 7 0 7 0 15 8 15 8 23 16 31 24 23 16 31 24 word data external data bus address 4n 4n + 1 4n + 2 4n + 3 7 0 7 0 15 8 15 8 23 16 31 24 23 16 31 24 word data external data bus address address 4n + 1 4n + 2 4n + 3 7 0 7 0 15 8 15 8 23 16 31 24 23 16 31 24 word data external data bus 4n + 4 1st access 2nd access 7 0 7 0 15 8 15 8 23 16 31 24 23 16 31 24 word data external data bus address address 4n + 2 4n + 3 7 0 7 0 15 8 15 8 23 16 31 24 23 16 31 24 word data external data bus 4n + 4 4n + 5 1st access 2nd access 7 0 7 0 15 8 15 8 23 16 31 24 23 16 31 24 word data external data bus address address 4n + 3 7 0 7 0 15 8 15 8 23 16 31 24 23 16 31 24 word data external data bus 4n + 5 4n + 4 4n + 6 1st access 2nd access
153 chapter 4 bus control function user?s manual u16580ee2v0ud00 (b) when the bus width is 16 bits (little endian) <1> access to address (4n) <2> access to address (4n+1) 1st access 2nd access 7 0 7 0 15 8 15 8 23 16 31 24 word data external data bus address 4n 4n + 1 7 0 7 0 15 8 15 8 23 16 31 24 word data external data bus address 4n + 3 4n + 2 1st access 2nd access 3rd access 7 0 7 0 15 8 15 8 23 16 31 24 word data external data bus address 4n + 1 7 0 7 0 15 8 15 8 23 16 31 24 word data external data bus address 4n + 3 4n + 2 7 0 7 0 15 8 15 8 23 16 31 24 word data external data bus address 4n + 4
154 chapter 4 bus control function user?s manual u16580ee2v0ud00 <3> access to address (4n+2) <4> access to address (4n+3) 1st access 2nd access 7 0 7 0 15 8 15 8 23 16 31 24 word data external data bus address 4n + 2 4n + 3 7 0 7 0 15 8 15 8 23 16 31 24 word data external data bus address 4n + 5 4n + 4 1st access 2nd access 3rd access 7 0 7 0 15 8 15 8 23 16 31 24 word data external data bus address 4n + 3 7 0 7 0 15 8 15 8 23 16 31 24 word data external data bus address 4n + 5 4n + 4 7 0 7 0 15 8 15 8 23 16 31 24 word data external data bus address 4n + 6
155 chapter 4 bus control function user?s manual u16580ee2v0ud00 (c) when the data bus width is 8 bits (little endian) <1> access to address (4n) <2> access to address (4n+1) 7 0 7 0 15 8 23 16 31 24 word data external data bus address 4n address 7 0 7 0 15 8 23 16 31 24 word data external data bus 4n + 1 address 7 0 7 0 15 8 23 16 31 24 word data external data bus 4n + 2 address 7 0 7 0 15 8 23 16 31 24 word data external data bus 4n + 3 1st access 2nd access 3rd access 4th access 7 0 7 0 15 8 23 16 31 24 word data external data bus address address address address 4n + 1 7 0 7 0 15 8 23 16 31 24 word data external data bus 4n + 2 7 0 7 0 15 8 23 16 31 24 word data external data bus 4n + 3 7 0 7 0 15 8 23 16 31 24 word data external data bus 4n + 4 1st access 2nd access 3rd access 4th access
156 chapter 4 bus control function user?s manual u16580ee2v0ud00 <3> access to address (4n+2) <4> access to address (4n+3) 7 0 7 0 15 8 23 16 31 24 word data external data bus address address address address 4n + 2 7 0 7 0 15 8 23 16 31 24 word data external data bus 4n + 3 7 0 7 0 15 8 23 16 31 24 word data external data bus 4n + 4 7 0 7 0 15 8 23 16 31 24 word data external data bus 4n + 5 1st access 2nd access 3rd access 4th access 7 0 7 0 15 8 23 16 31 24 word data external data bus address address address address 4n + 3 7 0 7 0 15 8 23 16 31 24 word data external data bus 4n + 4 7 0 7 0 15 8 23 16 31 24 word data external data bus 4n + 5 7 0 7 0 15 8 23 16 31 24 word data external data bus 4n + 6 1st access 2nd access 3rd access 4th access
157 chapter 4 bus control function user?s manual u16580ee2v0ud00 (d) when the data bus width is 32 bits (big endian) <1> access to address (4n) <2> access to address (4n+1) <3> access to address (4n+2) <4> access to address (4n+3) 7 0 7 0 15 8 15 8 23 16 31 24 23 16 31 24 word data external data bus address 4n + 3 4n + 2 4n + 1 4n 7 0 7 0 15 8 15 8 23 16 31 24 23 16 31 24 word data external data bus address address 4n + 1 4n + 2 4n + 3 7 0 7 0 15 8 15 8 23 16 31 24 23 16 31 24 word data external data bus 4n + 4 1st access 2nd access 7 0 7 0 15 8 15 8 23 16 31 24 23 16 31 24 word data external data bus address 4n + 5 4n + 4 address 7 0 7 0 15 8 15 8 23 16 31 24 23 16 31 24 word data external data bus 4n + 3 4n + 2 1st access 2nd access 7 0 7 0 15 8 15 8 23 16 31 24 23 16 31 24 word data external data bus address address 4n + 3 7 0 7 0 15 8 15 8 23 16 31 24 23 16 31 24 word data external data bus 4n + 5 4n + 6 4n + 4 1st access 2nd access
158 chapter 4 bus control function user?s manual u16580ee2v0ud00 (e) when the data bus width is 16 bits (big endian) <1> access to address (4n) <2> access to address (4n+1) 1st access 2nd access 7 0 7 0 15 8 15 8 23 16 31 24 word data external data bus address 4n 4n + 1 7 0 7 0 15 8 15 8 23 16 31 24 word data external data bus address 4n + 3 4n + 2 1st access 2nd access 3rd access 7 0 7 0 15 8 15 8 23 16 31 24 word data external data bus address 4n + 1 7 0 7 0 15 8 15 8 23 16 31 24 word data external data bus address 4n + 2 4n + 3 7 0 7 0 15 8 15 8 23 16 31 24 word data external data bus address 4n + 4
159 chapter 4 bus control function user?s manual u16580ee2v0ud00 <3> access to address (4n+2) <4> access to address (4n+3) 1st access 2nd access 7 0 7 0 15 8 15 8 23 16 31 24 word data external data bus address 4n + 2 4n + 3 7 0 7 0 15 8 15 8 23 16 31 24 word data external data bus address 4n + 5 4n + 4 1st access 2nd access 3rd access 7 0 7 0 15 8 15 8 23 16 31 24 word data external data bus address 4n + 3 7 0 7 0 15 8 15 8 23 16 31 24 word data external data bus address 4n + 4 4n + 5 7 0 7 0 15 8 15 8 23 16 31 24 word data external data bus address 4n + 6
160 chapter 4 bus control function user?s manual u16580ee2v0ud00 (f) when the data bus width is 8 bits (big endian) <1> access to address (4n) <2> access to address (4n+1) 7 0 7 0 15 8 23 16 31 24 word data external data bus address address address address 4n 7 0 7 0 15 8 23 16 31 24 word data external data bus 4n + 1 7 0 7 0 15 8 23 16 31 24 word data external data bus 4n + 2 7 0 7 0 15 8 23 16 31 24 word data external data bus 4n + 3 1st access 2nd access 3rd access 4th access 7 0 7 0 15 8 23 16 31 24 word data external data bus address address address address 4n + 1 7 0 7 0 15 8 23 16 31 24 word data external data bus 4n + 2 7 0 7 0 15 8 23 16 31 24 word data external data bus 4n + 3 7 0 7 0 15 8 23 16 31 24 word data external data bus 4n + 4 1st access 2nd access 3rd access 4th access
161 chapter 4 bus control function user?s manual u16580ee2v0ud00 <3> access to address (4n+2) <4> access to address (4n+3) 7 0 7 0 15 8 23 16 31 24 word data external data bus address address address address 4n + 2 7 0 7 0 15 8 23 16 31 24 word data external data bus 4n + 3 7 0 7 0 15 8 23 16 31 24 word data external data bus 4n + 4 7 0 7 0 15 8 23 16 31 24 word data external data bus 4n + 5 1st access 2nd access 3rd access 4th access 7 0 7 0 15 8 23 16 31 24 word data external data bus address address address address 4n + 3 7 0 7 0 15 8 23 16 31 24 word data external data bus 4n + 4 7 0 7 0 15 8 23 16 31 24 word data external data bus 4n + 5 7 0 7 0 15 8 23 16 31 24 word data external data bus 4n + 6 1st access 2nd access 3rd access 4th access
162 chapter 4 bus control function user?s manual u16580ee2v0ud00 4.6 wait function 4.6.1 programmable wait function (1) data wait control registers 0, 1 (dwc0, dwc1) to facilitate interfacing with low-speed memory or wit h i/os, it is possible to insert up to 7 data wait states with respect to the starting bus cycle for each cs area. the number of wait states can be specified by data wait control registers 0 and 1 (dwc0, dwc1) in programming. just after system reset, all blocks have 7 data wait states inserted. these registers can be read/written in 16-bit units. cautions: 1. the internal rom area (flash memory) and the internal ram area are not subject to programmable waits and ordinarily no wait access is carried out. the internal peripheral i/o area is also not subject to programmable wait states, with wait control performed only by each peripheral function. 2. write to the dwc0 and dwc1 registers after reset, and then do not change the set values. also, do not access an external memory area other than that for this initialization routine until initial setting of the dwc0 and dwc1 registers is finished. however, it is possible to access external memory areas whose initialization has been finished. figure 4-8: data wait control registers 0, 1 (dwc0, dwc1) format remark: n = 0 to 7 after reset: 7777h r/w address: fffff484h 1514131211109876543210 dwc0 0 dw32 dw31 dw30 0 dw22 dw21 dw20 0 dw12 dw11 dw10 0 dw02 dw01 dw00 cs3 cs2 cs1 cs0 after reset: 7777h r/w address: fffff486h 1514131211109876543210 dwc1 0 dw72 dw71 dw70 0 dw62 dw61 dw60 0 dw52 dw51 dw50 0 dw42 dw41 dw40 cs7 cs6 cs5 cs4 dwcn2 dwcn1 dwcn0 number of inserted data wait states during csn area access 0 0 0 no wait states inserted 0011 0102 0113 1004 1015 1106 1117
163 chapter 4 bus control function user?s manual u16580ee2v0ud00 (2) address wait control register (awc) the v850e/ph2 allows insertion of address setup wait and address hold wait states before and after the t1 cycle. the address setup wait and address hold wait states can be set with the awc register for each cs area. this register can be read/written in 16-bit units. cautions: 1. the internal rom area (flash memory) and the internal ram area are not subject to programmable waits and ordinarily no wait access is carried out. the internal peripheral i/o area is also not subject to programmable wait states, with wait control performed only by each peripheral function. 2. write to the awc registers after reset, and then do not change the set values. also, do not access an external memory area other than that for this initialization routine until initial setting of the awc registers is finished. however, it is possible to access external memory areas whose initialization has been finished. figure 4-9: address wait control register (awc) remark: n = 0 to 7 after reset: 0000h r/w address: fffff488h 1514131211109876543210 awc ahw7 asw7 ahw6 asw6 ahw5 asw5 ahw4 asw4 ahw3 asw3 ahw2 asw2 ahw1 asw1 ahw0 asw0 cs7 cs6 cs5 cs4 cs3 cs2 cs1 cs0 ahwn address hold wait insertion during csn area access 0 no insertion 1 address hold wait state in serted after t1 bus cycle asw1 address setup wait insertion during csn area access 0 no insertion 1 address setup wait state inse rted before t1 bus cycle
164 chapter 4 bus control function user?s manual u16580ee2v0ud00 4.7 idle state insertion function to facilitate interfacing with low-speed memory device s, an idle state (ti) ca n be inserted into the current bus cycle after the t2 state to meet the data output float delay time (tdf) on memory read access for each cs space. the bus cycle following the t2 state starts after the idle state is inserted. an idle state is inserted after read/write cycles for sram, external i/o, or external rom. in the following cases, an idle state is inserted in the timing. ? after read/write cycles for sram, external i/o, or external rom the idle state insertion setting c an be specified by program using the bus cycle control register (bcc) and the bus clock dividing control register (dvc). immediately after the system reset, idle state in sertion is automatically programmed for all memory blocks on read access.
165 chapter 4 bus control function user?s manual u16580ee2v0ud00 (1) bus cycle control register (bcc) this register can be read/written in 16-bit units. reset input changes the value of this register to in itial setting aaaah. cautions: 1. idle states cannot be inserted in internal rom, internal ram, on-chip peripheral i/o, or programmable peripheral i/o areas. 2. write to the bcc register after reset, and then do not change the set value. also, do not access an external memory area other than that for this initialization routine until initial setting of the bcc register is finished. however, it is possible to access external memory areas whose initialization has been finished. 3. do not change the settings of bits that are 0 after reset. otherwise the operation of the external bus interface cannot be ensured. figure 4-10: bus cycle control register (bcc) remark: n = 0 to 7 after reset: aaaah r/ w address: fffff48ah 1514131211109876543210 bcc bc710bc610bc510bc410bc310bc210bc110bc010 bcn1 idle state insertion during csn area access 0 no insertion 1 idle state inserted remark: when bit bcn1 bit is set to ?1?, an idle state will be inserted after any read access. if an idle state after write acce ss is necessary, the bcwi bit of the dvc register has to be set additionally.
166 chapter 4 bus control function user?s manual u16580ee2v0ud00 (2) bus clock dividing control register (dvc) this register can be read/written in 8-bit units. reset input changes the value of this register to in itial setting 01h. cautions: 1. idle states cannot be inserted in internal rom, internal ram, on-chip peripheral i/o, or programmable peripheral i/o areas. 2. write to the dvc register after reset, and then do not change the set value. also, do not access an external memory area other than that for this initialization routine until initial setting of the dvc register is finished. however, it is possible to access external memory areas whose initialization has been finished. 3. do not change the settings of bits 0 to 6. otherwise the operation of the external bus interface cannot be ensured. figure 4-11: bus clock dividing control register (dvc) after reset: 01h r/w address: fffff48eh 76543210 dvcbcwi0000001 bcwi idle state insertion after write cycle 0 idle state not inserted after write access 1 idle state inserted after write access note note: bcwi bit setting is only valid when bcn1 bit of the bcc register, corresponding to the csn area for which the write access will be performed, is set to ?1?. (n = 0 to 7)
167 chapter 4 bus control function user?s manual u16580ee2v0ud00 4.8 bus priority order there are two external bus cycles: operand data access and instruction fetch. as for the priority order, the highest priority has the instruction fetch than operand data access. an instruction fetch may be inserted between read access and write access during read modify write access. also, an instruction fetch may be inserted betwee n bus access and bus access during cpu bus clock. table 4-2: bus priority order priority order external bus cycle bus master low high operand data access cpu instruction fetch cpu
168 chapter 4 bus control function user?s manual u16580ee2v0ud00 4.9 boundary operation conditions 4.9.1 program space branching to the on-chip peripheral i/o area is prohibited. if the above is performed, undefined data is fetched, and fetching from the external memory is not performed. 4.9.2 data space the v850e/ph2 is provided with an address misalign function. through this function, regardless of the data format (word, halfword or byte), data can be allocated to all addresses. however, in the case of word data and halfword data, if the data is not subject to boundary alignment, the bus cycle will be generated at least 2 times and bus efficiency will drop. (1) external bus width: 16 bits (a) in the case of halfword-length data access when the address?s lsb is 1, a byte-l ength bus cycle will be generated 2 times. (b) in the case of word-length data access ? when the address?s lsb is 1, bus cycles will be gen erated in the order of byte-length bus cycle, halfword-length bus cycle, and byte-length bus cycle. ? when the address?s lower 2 bits are 10b, a half word-length bus cycle will be generated 2 times. (2) external bus width: 32 bits (a) in the case of halfword-length data access when the address?s lower 2 bits are 11b, a byte-length bus cycle will be generated 2 times. (b) in the case of word-length data access when the address?s lower 2 bits are 10b, a half word-length bus cycle will be generated 2 times.
169 user?s manual u16580ee2v0ud00 chapter 5 memory access control function 5.1 sram, external rom, external i/o interface 5.1.1 features ? sram is accessed in a minimum of 2 states. ? up to 7 states of programmable data waits can be inserted by setting the dwc0 and dwc1 registers. ? data wait can be controlled via wait pin input. ? an idle state can be inserted after a read/write cycle by setting the bcc and dvc registers. ? an address setup wait state and an address hold state can be inserted by setting the asc register.
170 chapter 5 memory access control function user?s manual u16580ee2v0ud00 5.1.2 sram connection examples of connection to sram are shown below. figure 5-1: examples of connection to sram (1/2) (a) when data bus width is 32 bits and data size of sram is 8 bits (b) when data bus width is 8 bits and data size of sram is 8 bits remark: n = 0, 1, 3, 4 v850e/ph2 a2 to a20 d24 to d31 csn rd wr d16 to d23 d8 to d15 d0 to d7 ben3 1 1 1 1 ben2 ben1 ben0 a0 to a18 i/o1 to i/o8 cs oe we sram ( pd444008l 512 kwords 8 bits) a0 to a18 i/o1 to i/o8 cs oe we sram ( pd444008l 512 kwords 8 bits) a0 to a18 i/o1 to i/o8 cs oe we sram ( pd444008l 512 kwords 8 bits) a0 to a18 i/o1 to i/o8 cs oe we sram ( pd444008l 512 kwords 8 bits) v850e/ph2 a0 to a18 d0 to d7 csn rd wr a0 to a18 i/o1 to i/o8 cs oe we sram ( pd444008l 512 kwords 8 bits)
171 chapter 5 memory access control function user?s manual u16580ee2v0ud00 figure 5-1: examples of connection to sram (2/2) (c) when data bus width is 32 bits and data size of sram is 16 bits (d) when data bus width is 16 bits and data size of sram is 16 bits remark: n = 0, 1, 3, 4 v850e/ph2 a2 to a19 d16 to d31 csn rd ben3 ben2 wr d0 to d15 ben1 ben0 a0 to a17 i/o1 to i/o16 cs oe ub lb we sram ( pd444016l 256 kwords 16 bits) a0 to a17 i/o1 to i/o16 cs oe ub lb we sram ( pd444016l 256 kwords 16 bits) v850e/ph2 a1 to a18 csn rd ben1 ben0 wr d0 to d15 a0 to a17 i/o1 to i/o16 cs oe ub lb we sram ( pd444016l 256 kwords 16 bits)
172 chapter 5 memory access control function user?s manual u16580ee2v0ud00 5.1.3 sram, external rom, external i/o access figure 5-2: sram, external rom, external i/o access timing (1/8) (a) read notes: 1. csn output levels depend on the accessed area when enabled by bct0 and bct1 registers. 2. ben0 to ben3 output levels depend on the accessed type (byte, half-word, or word) and the external bus size (8, 16, or 32 bits) specified by the bsc register remarks: 1. n = 0, 1, 3, 4 2. bus clock = f xx /2 3. the circle indicates the sampling timing. 4. the dashed line indicates the high impedance state. bus clock a0 to a21 (output) d0 to d31 (input) csn (output) ben0 ben3 to (output) rd (output) wr (output) wait (input) t1 t2 t1 tw t2 without data wait insertion h with data wait insertion address note 1 address note 2 data data note 2 note 1
173 chapter 5 memory access control function user?s manual u16580ee2v0ud00 figure 5-2: sram, external rom, external i/o access timing (2/8) (b) read (idle state inserted) notes: 1. csn output levels depend on the accessed area when enabled by bct0 and bct1 registers. 2. ben0 to ben3 output levels depend on the accessed type (byte, half-word, or word) and the external bus size (8, 16, or 32 bits) specified by the bsc register remarks: 1. n = 0, 1, 3, 4 2. bus clock = f xx /2 3. the circle indicates the sampling timing. 4. the dashed line indicates the high impedance state. bus clock a0 to a21 (output) csn (output) rd (output) wr (output) t1 t2 ti h address note 1 d0 to d31 (input) ben0 ben3 to (output) wait (input) data note 2
174 chapter 5 memory access control function user?s manual u16580ee2v0ud00 figure 5-2: sram, external rom, external i/o access timing (3/8) (c) read (data wait, idle state inserted) notes: 1. csn output levels depend on the accessed area when enabled by bct0 and bct1 registers. 2. ben0 to ben3 output levels depend on the accessed type (byte, half-word, or word) and the external bus size (8, 16, or 32 bits) specified by the bsc register remarks: 1. n = 0, 1, 3, 4 2. bus clock = f xx /2 3. the circle indicates the sampling timing. 4. the dashed line indicates the high impedance state. bus clock a0 to a21 (output) csn (output) rd (output) wr (output) h ti t1 tw t2 address note 1 d0 to d31 (input) ben0 ben3 to (output) wait (input) note 2 data
175 chapter 5 memory access control function user?s manual u16580ee2v0ud00 figure 5-2: sram, external rom, external i/o access timing (4/8) (d) read (address setup wait and address hold wait state inserted) notes: 1. csn output levels depend on the accessed area when enabled by bct0 and bct1 registers. 2. ben0 to ben3 output levels depend on the accessed type (byte, half-word, or word) and the external bus size (8, 16, or 32 bits) specified by the bsc register remarks: 1. n = 0, 1, 3, 4 2. bus clock = f xx /2 3. the circle indicates the sampling timing. 4. the dashed line indicates the high impedance state. bus clock a0 to a21 (output) csn (output) rd (output) wr (output) t1s t1 t1h t2 h address note 1 d0 to d31 (input) ben0 ben3 to (output) wait (input) data note 2
176 chapter 5 memory access control function user?s manual u16580ee2v0ud00 figure 5-2: sram, external rom, external i/o access timing (5/8) (e) write notes: 1. csn output levels depend on the accessed area when enabled by bct0 and bct1 registers. 2. ben0 to ben3 output levels depend on the accessed type (byte, half-word, or word) and the external bus size (8, 16, or 32 bits) specified by the bsc register remarks: 1. n = 0, 1, 3, 4 2. bus clock = f xx /2 3. the circle indicates the sampling timing. 4. the dashed line indicates the high impedance state. bus clock a0 to a21 (output) csn (output) rd (output) wr (output) t1 t2 t1 tw t2 h address note 1 address d0 to d31 (input) ben0 ben3 to (output) wait (input) without data wait insertion with data wait insertion note 2 data data note 2 note 1
177 chapter 5 memory access control function user?s manual u16580ee2v0ud00 figure 5-2: sram, external rom, external i/o access timing (6/8) (f) write (idle state inserted) notes: 1. csn output levels depend on the accessed area when enabled by bct0 and bct1 registers. 2. ben0 to ben3 output levels depend on the accessed type (byte, half-word, or word) and the external bus size (8, 16, or 32 bits) specified by the bsc register remarks: 1. n = 0, 1, 3, 4 2. bus clock = f xx /2 3. the circle indicates the sampling timing. 4. the dashed line indicates the high impedance state. bus clock a0 to a21 (output) csn (output) rd (output) wr (output) t1 t2 ti h address note 1 d0 to d31 (input) ben1 ben3 to (output) wait (input) note 2 data
178 chapter 5 memory access control function user?s manual u16580ee2v0ud00 figure 5-2: sram, external rom, external i/o access timing (7/8) (g) write (data wait, idle state inserted) notes: 1. csn output levels depend on the accessed area when enabled by bct0 and bct1 registers. 2. ben0 to ben3 output levels depend on the accessed type (byte, half-word, or word) and the external bus size (8, 16, or 32 bits) specified by the bsc register remarks: 1. n = 0, 1, 3, 4 2. bus clock = f xx /2 3. the circle indicates the sampling timing. 4. the dashed line indicates the high impedance state. bus clock a0 to a21 (output) csn (output) rd (output) wr (output) h ti t1 tw t2 address note 1 d0 to d31 (input) ben0 ben3 to (output) wait (input) note 2 data
179 chapter 5 memory access control function user?s manual u16580ee2v0ud00 figure 5-2: sram, external rom, external i/o access timing (8/8) (h) read (address setup wait and address hold wait state inserted) notes: 1. csn output levels depend on the accessed area when enabled by bct0 and bct1 registers. 2. ben0 to ben3 output levels depend on the accessed type (byte, half-word, or word) and the external bus size (8, 16, or 32 bits) specified by the bsc register remarks: 1. n = 0, 1, 3, 4 2. bus clock = f xx /2 3. the circle indicates the sampling timing. 4. the dashed line indicates the high impedance state. bus clock a0 to a21 (output) csn (output) rd (output) wr (output) t1s t1 t1h t2 h address note 1 d0 to d31 (input) ben0 ben3 to (output) wait (input) note 2 data
180 user?s manual u16580ee2v0ud00 [memo]
181 user?s manual u16580ee2v0ud00 chapter 6 dma functi ons (dma controller) 6.1 features the v850e/ph2 includes a direct memory access (dma) controller (dmac) that executes and controls dma transfer. the dmac controls data transfer between internal ram (iram) and peripheral i/o registers, based on dma requests issued by the on-chip peripheral i/o (a/d converters, inverter timers, and serial interfaces), with the following features. ? 2 channels for dma transfer from a/d converter (adc0, adc1) - transfer object: i/o iram - transfer size: 16 bits - dedicated transfer channels for adc0 and adc1 ? 2 channels for dma transfer to pwm timer (tmr0, tmr1) - transfer object: iram i/o - transfer size: 16 bits - dedicated transfer channels for tmr0 and tmr1 ? 2 channels for dma transfer from serial interfaces on reception completion - transfer object: i/o iram - transfer size: 8 or 16 bits - dma request for each channel selectable clocked serial interfaces: csib0, csib1, csi30, csi31 asynchronous serial interface: uartc0, uartc1 ? 2 channels for dma transfer to serial interfaces on transmission repetition - transfer object: iram i/o - transfer size: 8 or 16 bits - dma request for each channel selectable clocked serial interfaces: cs ib0, csib1, cs30, csi31 asynchronous serial interface: uartc0, uartc1 ? up to 256 transfer counts for each channel.
182 chapter 6 dma functions (dma controller) user?s manual u16580ee2v0ud00 6.2 control registers (1) dma transfer memory start address registers 0 to 7 (mar0 to mar7) the marn register specifies the subordinated 16 bits of the dma transfer start address within the internal ram area for the dma channel n (n = 0 to 7). this register can be read or written in 16-bit units. after reset the register content is undefined. figure 6-1: dma transfer memory start address registers 0 to 7 (mar0 to mar7) cautions: 1. since the internal ram area is mapped between 3ff0000h and 3ff7fffh the value written to the marn register has to be in the range from 0000h to 7fffh. 2. the value set to the marn register is increased by each dma transfer of chan- nels. it does not keep the initial value after the dma transfer ends. after reset: undefined r/w address : mar0 fffff300h, mar1 fffff302h mar2 fffff304h, mar3 fffff306h mar4 fffff308h, mar5 fffff30ah mar6 fffff30ch, mar7 fffff30eh 1514131211109876543210 marn marn 15 marn 14 marn 13 marn 12 marn 11 marn 10 marn 9 marn 8 marn 7 marn 6 marn 5 marn 4 marn 3 marn 2 marn 1 marn 0 (n = 0 to 7)
183 chapter 6 dma functions (dma controller) user?s manual u16580ee2v0ud00 (2) dma transfer sfr start address registers 2, 3 (sar2, sar3) the sarn register specifies the start address of the tmr register for which the dma transfer is started on dma channel n (n = 2, 3). this register can be read or written in 8-bit units. after reset the register content is undefined. figure 6-2: dma transfer sfr start address registers 2, 3 (sar2, sar3) notes: 1. although the register address is meaningless, a transfer to this address is always performed when sarn2 to sarn0 bits are equal to 010b or less. 2. although the register address is meaningless, a transfer to this address is always performed when sarn2 to sarn0 bits are equal to 011b or less. caution: during dma transfer (den = 1) the contents of the sarn register may change. after each dma transfer the contents is incremented by 1 until the final value (07h) is reached. when the sarn register contents become s 07h, the initial set value is reloaded. after reset: undefined r/ w address: sar2 fffff314h, sar3 fffff316h 76543210 sarn00000sarn2sarn1sarn0 (n = 2, 3) sarn2 sarn1 sarn0 dma transfer start address of tmr reload register n = 2 n = 3 register address register address 0 0 0 tr0ccr5 fffff590h tr1ccr5 fffff5d0h 0 0 1 tr0ccr4 fffff592h tr1ccr4 fffff5d2h 010? note 1 fffff594h ? note 1 fffff5d4h 011? note 2 fffff596h ? note 2 fffff5d6h 1 0 0 tr0ccr0 fffff598h tr1ccr0 fffff5d8h 1 0 1 tr0ccr3 fffff59ah tr1ccr3 fffff5dah 1 1 0 tr0ccr2 fffff59ch tr1ccr2 fffff5dch 1 1 1 tr0ccr1 fffff59eh tr1ccr1 fffff5deh
184 chapter 6 dma functions (dma controller) user?s manual u16580ee2v0ud00 (3) dma transfer count registers 0 to 7 (dtcr0 to dtcr7) the dtcrn register is an 8-bit register that set the transfer count for dma channel n and stores the remaining transfer count during dma transfer (n = 0 to 7). this register can be read or written in 8-bit units. after reset the register content is undefined. figure 6-3: dma transfer count registers 0 to 7 (dtcr0 to dtcr7) cautions: 1. the value set to the dtcrn register is decreased by each dma transfer of channel n. it does not keep the initial value after the dma transfer ends. therefore, after dma transfer end the dtcrn register values becomes 00h. 2. a dma request becomes only effective after the dtcrn register was written. even if 00h (means a transfer count of 256) is the initial value, the dtrcn register must be rewritten in order to enable a new dma transfer. remark: n = 0 to 7 after reset: undefined r/w address: d tcr0 fffff320h, dtcr1 fffff322h dtcr2 fffff324h, dtcr3 fffff326h dtcr4 fffff328h, dtcr5 fffff32ah dtcr6 fffff32ch, dtcr7 fffff32eh 76543210 dtcrn dtcrn7 dtcrn6 dtcrn5 dtcrn4 dtcrn3 dtcrn2 dtcrn1 dtcrn0 dtcrn 7 dtcrn 6 dtcrn 5 dtcrn 4 dtcrn 3 dtcrn 2 dtcrn 1 dtcrn 0 remaining dma transfer counts 00000000 256 00000001 1 00000010 2 00000011 3 11111110 254 11111111 255
185 chapter 6 dma functions (dma controller) user?s manual u16580ee2v0ud00 (4) dma mode control register (dmamc) the dmamc register is an 8-bit register that controls the operation of the dma channels. this register can be read or written in 8-bit units. reset input clears this register to 00h. figure 6-4: dma mode control register (dmamc) caution: writing of the de1 and de0 bits is prohibited if the corresponding a/d converter is operating. (5) dma status register (dmas) the dmas register is an 8-bit register that displays the transfer status of the dma channels. this register can be read or written in 8-bit units. reset input clears this register to 00h. figure 6-5: dma status register (dmas) remark: n = 0 to 7 after reset: 00h r/w address: dmamc fffff330h 76543210 dmamc de7 de6 de5 de4 de3 de2 de1 de0 den control bit of dma channel n 0 dma transfer operation of channel n disabled 1 dma transfer operation of channel n enabled after reset: 00h r/w address: dmamc fffff332h 76543210 dmas dmas7 dmas6 dmas5 dmas4 dmas3 dmas2 dmas1 dmas0 dmasn status bit of dma channel n 0 dma transfer of channel n is idle or in progress 1 dma transfer of channel n is completed ? the dmasn bit can be read and written, but it can only be cleared by writing 0 to it, and it cannot be set by writing 1 to it. ? since the dmasn bit is not cleared by the dmac, it has to be cleared by software before dma transfer is started.
186 chapter 6 dma functions (dma controller) user?s manual u16580ee2v0ud00 (6) dma data size control register (dmdsc) the dmadsc register is an 8-bit register that c ontrols the transfer data size of dma channels 4 to 7. the data size of dma channels 0 to 3 is fixed, and therefore not selectable. this register can be read or written in 8-bit units. reset input clears this register to 00h. figure 6-6: dma data size control register (dmdsc) remark: n = 4 to 7 after reset: 00h r/w address: dmamc fffff334h 76543210 dmadscdmadsc7dmadsc6dmadsc5dmadsc40000 dmadscn transfer data size of dma channel n 0 8 bits 1 16 bits
187 chapter 6 dma functions (dma controller) user?s manual u16580ee2v0ud00 (7) dma trigger factor registers 4 to 7 (dtfr4 to dtfr7) the dtfrn register is an 8-bit register that controls the dma transfer start trigger of dma channel n via interrupt requests from on-chip peripheral i/o (n = 4 to 7). the interrupt request set by this register serves as dma transfer start factor. this register can be read or written in 8-bit units. reset input clears this register to 00h. cautions: 1. do not set the same transfer start factor by different dtfrn registers. 2. do not rewrite the dtfrn register until a started dma transfer ends (corresponding dtcrn register value is 00h). 3. write the dtfrn register before setting the corresponding dtcrn register. according to the present transfer start factor in the dtfrn register a dma might be started when the dtcrn register is written previously. figure 6-7: dma trigger factor registers 4 to 7 (dtfr4 to dtfr7) remark: n = 4 to 7 after reset: 00h r/w address: dtfr4 fffff348h, dtfr5 fffff34ah dtfr6 fffff34ch, dtfr7 fffff34eh 76543210 dtfrn00000ifcn2ifcn1ifcn0 ifcn2 ifcn1 ifcn0 dma transfer start factor when n = 4, 5 when n = 6, 7 0 0 0 dma request from on-chip peripheral i/o disabled 0 0 1 intuc0r intuc0t 0 1 0 intuc1r intuc1t 011intcb0r intcb0t 100intcb1r intcb1t 1 0 1 intc30 intc30 1 1 0 intc31 intc31 1 1 1 setting prohibited
188 chapter 6 dma functions (dma controller) user?s manual u16580ee2v0ud00 6.3 dma channel priorities the dma channel priorities are fixed as follows. dma channel 0 > dma channel 1 > dma channel 2 >... > dma channel 7 6.4 dma operation 6.4.1 dma transfer of a/d converter result registers (adc0, adc1) the dmac has two dedicated channels to support dma transfer for both a/d converters independently, dma channel 0 for a/d converter 0 and dma channel 1 for a/d converter 1. as dma trigger factor, which requests and starts the dma transfer, the end of conversion interrupt signal of the corresponding a/d converter is pre-defined (intadn) (n = 0, 1). for each dma trigger the data will be transferred from the a/d conver sion result register for dma (addman) into the internal ram specified as destinat ion. while the source transfer address is fixed to the addman register of the corresponding a/d converter (adcn), the destination start address can be set up to any even address in the internal ram. when the dma transfer count of a dma channel terminates, the dma transfer is stopped and a termination interrupt is generated. the maximum dma transfer count is 256. since the dma transfer is performed for each finished a/d conversion, it is possible to transfer more than conversion results of one a/d converter scan sequence. however, the user has to take care that the number of transfer counts complies with the product of a/d converter scan area size and the number of a/d converter start triggers.
189 chapter 6 dma functions (dma controller) user?s manual u16580ee2v0ud00 figure 6-8: initialization of dma transfer for a/d conversion result remark: n = 0, 1 (number of adc channel) x = n (number of dma channel) initialization of dma transfer for a/d conversion result of adcn (dma channel 0 or 1) set up a/d conversion scan range in the admn2 register set up the marx register with destination start address within iram in specify the dma transfer count in the dtcrx register (1 to 256) enable dma transfer channel x: dex bit = 1 enable operation of a/d converter n: adcen bit = 1 adcsn bit = 1? disable operation of a/d converter n: adcen bit = 0 end of initialization clear status bit of dma channel x: dmasx bit = 0 adcen bit = 1? yes no yes no
190 chapter 6 dma functions (dma controller) user?s manual u16580ee2v0ud00 figure 6-9: operation of dma channel 0/1 note: dma transfer completion interrupt has the same interrupt vector address as the corresponding a/d conversion completion interrupt (intadn), and replaces that interrupt. remark: n = 0, 1 (number of adc channel) x = n (number of dma transfer channel) operation of dma channel 0/1 dex bit = 1 ? dex bit newly written ? addmarqn occured ? transfer content from addman register to iram : (marx) addman increment source pointer: marx marx + 2 decrement dma transfer count register: dtcrx dtcrx - 1 dtcrx = 0? set dma transfer status bit: dmasx = 1 generate interrupt signal (intdmax note ) yes no yes yes no no yes no dma transfer will be enabled by write access to the corresponding den bit.
191 chapter 6 dma functions (dma controller) user?s manual u16580ee2v0ud00 figure 6-10: dma channel 0 and 1 trigger signal timing remarks: 1. the dma request by addmarq is disregar ded after intdma is generated, and the dma transfer is not restarted automatically. write ?1? in the corresponding dex bit of the dmamc register again to enable the next transfer of dma channel x. the dex bit is not cleared by hardware. 2. n = 0, 1 (number of the a/d converter channel) x = n (number of the dma channel) setup marx, dtcrx, dmamc register 1000h 1002h 1004h 1006h 1008h 0003h 0002h 0001h 0000h 0000h 100ch 100eh 1010h 0002h 0001h 0000h 100ah 0003h re-setup dtcrx, dmamc register (write dex bit = 1) addmarqn dma transfer marx dtcrx intadn
192 chapter 6 dma functions (dma controller) user?s manual u16580ee2v0ud00 6.4.2 dma transfer of pwm timer reload (tmr0, tmr1) the dmac has two dedicated channels to support dma transfer for both pwm timers tmrn independently, dma channel 2 for tmr0 and dma channel 3 for tmr1. as dma trigger factor, which requests and starts the dma transfer, two corresponding timer interrupt signals are pre-defined (inttrnod or inttrncd). these are the same signals as for reloading the internal buffer compare registers by the contents of the capture/compare registers trnccrm (n = 0, 1)(m = 0 to 5). for each dma trigger data will be transferred from internal ram to the c apture/compare registers of corresponding timer tmrn. the destination start address of the tmrn register (trncc0, trncc2 to trncc5) can be set up by the sarx register, as well as the source start address in the internal ram by the marx register. the destination end address is always fixed to trncc1 register, which also enables the buffer reload in the timer tmrn period (ref. to table 6-1). the dma transfer count is defined by the destination start and end address. however, an additionally dma trigger count is available, which can be specified in the dtcrx register from 1 to 256. after decrementing the dtcrx register the dmac will be prepared fo r a new dma transfer from internal ram to the timer tmrn registers until the dma trigger count terminates (dtcrx register = 0). remark: n = 0, 1 m = 0 to 5 x = n + 2 table 6-1: timer tmr address mapping for dma transfer dma transfer destination address dma transfer source address tmrn registers address offset trnccr5 00h selectable as start address any even address in internal ram area trnccr4 02h trnccr0 08h trnccr3 0ah trnccr2 0ch trnccr1 0eh always end address
193 chapter 6 dma functions (dma controller) user?s manual u16580ee2v0ud00 figure 6-11: initialization of dma transfer for tmrn compare registers remark: n = 0, 1 (number of tmr channel) x = n + 2 (number of dma channel) set up sarx register with tmrn start address offset (trnccr0, trnccr2 to trnccr5) set up the marx register with source start address in iram specify the dma transfer count in the dtcrx register (1 to 256) clear status bit of dma channel x: dmasx bit = 0 enable dma transfer channel x: dex bit = 1 initialization of dma transfer for tmrn compare registers (dma channel 2 or 3) end of initialization
194 chapter 6 dma functions (dma controller) user?s manual u16580ee2v0ud00 figure 6-12: operation of dma channel 2/3 remark: n = 0, 1 (number of tmr channel) x = n + 2 (number of dma transfer channel) initialize destination pointer to 1st tmr compare register: m 2 sarx + address of trnccr5 dex bit = 1 ? dex bit newly written ? inttrnod occurred ? inttrncd occurred ? increment destination pointer: m m + 2 transfer content from iram to tmrn compare register: (m) (marx) increment source pointer: marx marx + 2 m > address of trnccr0 ? decrement dma transfer count register: dtcrx dtcrx - 1 dtcrx = 0? set dma transfer status bit: dmasx = 1 generate interrupt signal (intdmax) no yes no yes yes yes no no yes yes no no dma transfer will be enabled by write access to the corresponding den bit. operation of dma channel 2/3
195 chapter 6 dma functions (dma controller) user?s manual u16580ee2v0ud00 figure 6-13: dma channel 2 and 3 trigger signal timing remarks: 1. the dma request by inttrnod or inttrn cd is disregarded after intdmax is gener- ated, and the dma transfer is not restarted automatically. write ?1? in the corresponding dex bit of the dmamc register again to enable the next transfer of dma channel x. the dex bit is not cleared by hardware. 2. n = 0, 1 (number of the tmr channel) x = n+2 (number of the dma channel) 1000h 1002h 1004h 1006h 1008h 100eh 1010h 04h 02h 05h 06h 07h 04h 07h 04h 01h 0h 100ah 05 h setup marx, dtcrx, sarx register dma transfer marx sarx dtcrx intdmax inttrnod or inttrncd
196 chapter 6 dma functions (dma controller) user?s manual u16580ee2v0ud00 6.4.3 dma transfer of serial interfaces (1) serial data reception with dma transfer the dmac has two dedicated channels (4 and 5) to support the serial data reception. each of both channels can be assigned to a serial interface (csi30, csi31, csib0, csib1, uartc0, uartc1). as dma trigger factor, which requests and starts the dma transfer, the corresponding interrupt signal at the end of reception is pre-defined (ref. to table 6-2). for each dma trigger the data will be transferred fr om the corresponding se rial reception register to internal ram. depending on the serial interfac e the transfer data size can be set to 8 or 16 bits (refer to table 6-2). in case of 8 bits transfer data size, the destination address is incremented by 1 for each occurrence of dma trigger. when selecting 16 bits transfer data size the destination address must be even, and is incremented by 2 for each dma trigger. when the dma transfer count of a dma channel terminates, the dma transfer is stopped and a dma completion interrupt is generated. the maximum dma transfer count is 255. table 6-2: dma configuration of serial data reception serial interface dma trigger factor transfer data size source destination csi30 intc30 8 bits sirb0l any iram address 16 bits sirb0 any even iram address csi31 intc31 8 bits sirb1l any iram address 16 bits sirb1 any even iram address csib0 intcb0t 8 bits cb0rxl any iram address 16 bits cb0rx any even iram address csib1 intcb1t 8 bits cb1rxl any iram address 16 bits cb1rx any even iram address uartc0 intuc0t 8 bits uc0rx any iram address 16 bits setting prohibited uartc1 intuc1t 8 bits uc1rx any iram address 16 bits setting prohibited
197 chapter 6 dma functions (dma controller) user?s manual u16580ee2v0ud00 the procedure of the dma transfer in case of serial data reception is shown in figure 6-14. figure 6-14: initialization of dma transfer for serial data reception remark: n = 0, 1 (number of serial interface channel) x = 4, 5 (number of dma channel) initialization of dma transfer for serial data reception (dma channel 4 or 5) set up marx register with the destination start address in iram specify the dma transfer count in the dtcrx register (1 to 256) clear status bit of dma channel x: dmasx bit = 0 enable dma transfer channel x: dex bit = 1 end of initialization specify the dma trigger factor in the dtfrx register depending on the used serial interface (csi3n, csibn, uartcn) select the dma transfer data size (8 or 16 bits) by the dmadscx bit in the dmadsc register
198 chapter 6 dma functions (dma controller) user?s manual u16580ee2v0ud00 figure 6-15: operation of dma channel 4/5 note: dma transfer completion interrupt has the same interrupt vector address as the corresponding reception completion interrupt specified by dtfrx register, and replaces that interrupt. remark: n = 0, 1 (number of serial interface channel) x = 4, 5 (number of dma transfer channel) operation of dma channel 4/5 dex bit = 1 ? dex bit newly written ? dma trigger factor occurred ? transfer content from serial receive buffer (depending on dtfrx register) to iram : (marx) sirbn or cbnrx increment source pointer: marx marx + 2 decrement dma transfer count register: dtcrx dtcrx - 1 dtcrx = 0? set dma transfer status bit: dmasx = 1 generate interrupt signal (intdmax note ) yes no yes yes no no yes no dma transfer will be enabled by write access to the corresponding den bit. dma trigger factor is the interrupt source specified by dtfrx register. dmadscx bit = 1 ? transfer content from serial receive buffer (depending on dtfrx register) to iram : (marx) sirbnl, cbnrxl or uxnrx increment source pointer: marx marx + 1 yes (16 bit) no (8 bit)
199 chapter 6 dma functions (dma controller) user?s manual u16580ee2v0ud00 figure 6-16: dma channel 4 and 5 trigger signal timing remark: m = 4, 5 n = 0, 1 1000h 1002h 1004h 1006h 1008h 0003h 0002h 0001h 0000h 0000h 100ch 100eh 1010h 0002h 0001h 0000h 100ah 0003h marm, dtcrm, dtrfm, dmamcm dtcrm, dmamcm trigger signal (by dtfrm register) dma transfer marm dtcrm intucnr or intcbnr or intcsi3n
200 chapter 6 dma functions (dma controller) user?s manual u16580ee2v0ud00 (2) serial data transmission with dma transfer the dmac has two dedicated channels (6 and 7) to support the serial data transmission. each of both channels can be assigned to a serial interface (csi30, csi31, csib0, csib1, uartc0, uartc1). as dma trigger factor, which requests and starts the dma transfer, the corresponding transmission enable interrupt signal is pre-defined (refer to table 6-3). for each dma trigger the data will be transferred fr om internal ram to t he corresponding serial transmit register. depending on the serial interface the transfer data size can be set to 8 or 16 bits (refer to table 6-3). in case of 8 bits transfer data size, the source address is incremented by 1 for each occurrence of dma trigger. when selecting 16 bits transfer data size the source address must be even, and is incremented by 2 for each dma trigger. when the dma transfer count of a dma channel terminates, the dma transfer is stopped and a dma completion interrupt is generated. the maximum dma transfer count is 255. note: the serial peripheral chip select lines scs0 to scs3 will not be supported by dma transfer. table 6-3: dma configuration of serial data transmission serial interface dma trigger factor transfer data size source destination csi30 note intc30 8 bits any iram address sfdb0l 16 bits any even iram address sfdb0 csi31 note intc31 8 bits any iram address sfdb1l 16 bits any even iram address sfdb1 csib0 intcb0t 8 bits any iram address cb0txl 16 bits any even iram address cb0tx csib1 intcb1t 8 bits any iram address cb1txl 16 bits any even iram address cb1tx uartc0 intuc0t 8 bits any iram address uc0tx 16 bits setting prohibited uartc1 intuc1t 8 bits any iram address uc1tx 16 bits setting prohibited
201 chapter 6 dma functions (dma controller) user?s manual u16580ee2v0ud00 the procedure of the dma transfer in case of serial data transmission is shown in figure 6-17. figure 6-17: initialization of dma transfer for serial data transmission remark: n = 0, 1 (number of serial interface channel) x = 6, 7 (number of dma channel) initialization of dma transfer for serial data transmission (dma channel 6 or 7) set up marx register with the source start address in iram specify the dma transfer count in the dtcrx register (1 to 256) clear status bit of dma channel x: dmasx bit = 0 enable dma transfer channel x: dex bit = 1 end of initialization specify the dma trigger factor in the dtfrx register depending on the used serial interface (csi3n, csibn, uartcn) select the dma transfer data size (8 or 16 bits) by the dmadscx bit in the dmadsc register
202 chapter 6 dma functions (dma controller) user?s manual u16580ee2v0ud00 figure 6-18: dma channel 6 and 7 trigger signal timing remark: m = 6, 7 n = 0, 1 1000h 1002h 1004h 1006h 1008h 0003h 0002h 0001h 0000h 0000h 100ch 100eh 1010h 0002h 0001h 0000h 100ah 0003h marm, dtcrm, dtrfm, dmamcm dtcrm, dmamcm trigger signal (by dtfrm register) dma transfer marm dtcrm intucnt or intcbnt or intcsi3n
203 chapter 6 dma functions (dma controller) user?s manual u16580ee2v0ud00 figure 6-19: operation of dma channel 6/7 note: dma transfer completion interrupt has the same interrupt vector address as the corresponding transmission start interrupt specified by dtfrx register, and replaces that interrupt. remark: n = 0, 1 (number of serial interface channel) x = 6, 7 (number of dma transfer channel) operation of dma channel 6/7 dex bit = 1 ? dex bit newly written ? dma trigger factor occurred ? transfer content from iram to serial transmit buffer (spec. by dtfrx register): sfdbn or cbntx (marx) increment source pointer: marx marx + 2 decrement dma transfer count register: dtcrx dtcrx - 1 dtcrx = 0? set dma transfer status bit: dmasx = 1 generate interrupt signal (intdmax note ) yes no yes yes no no yes no dma transfer will be enabled by write access to the corresponding den bit. dma trigger factor is the interrupt source specified by dtfrx register. dmadscx bit = 1 ? transfer content from iram to serial transmit buffer (spec. by dtfrx register): sfdbnl, cbntxl or ucntx (marx) increment source pointer: marx marx + 1 yes (16 bit) no (8 bit)
204 chapter 6 dma functions (dma controller) user?s manual u16580ee2v0ud00 6.4.4 forcible termination of dma transfer a once started dma transfer can be forcible terminated when the corresponding den bit in the dmamc register is cleared (0). however, if the den bit is cleared while dma transferring, an once started data transfer is stopped first after it has been finished (see figure 6-20). figure 6-20: cpu and dma controller processing of dma transfer termination (example) sar2 = 0ah dtcr2 = 8 dmas2 = 0 de2 = 1 (dma transfer channel 2 enabled) (dma transfer channel 2 forcibly disabled) dma transfer to tr0ccr3 dma transfer to tr0ccr3 dma transfer to tr0ccr2 dma transfer to tr0ccr2 dma transfer to tr0ccr1 dma transfer to tr0ccr1 dtcr2 =7 dtcr2 = 6 de2 = 0 cpu processing dmac processing dma trigger occurred (inttr0cd) dma trigger occurred (inttr0cd) no further dma trigger (inttr0cd) will be accepted
205 chapter 6 dma functions (dma controller) user?s manual u16580ee2v0ud00 6.5 dma interrupt function the peripheral i/o interrupts of the a/d converters and the serial interfaces, which serve as dma trigger factors, are shared with the dma transfer completion interrupt of the corresponding channel n (intdman) (n = 0, 1, 4 to 7). when a dma channel is enabled the specified peripheral i/o interrupt is no longer applied to the interrupt controller. instead of it the corresponding dma transfer completion interrupt is applied to the appropriate interrupt handler address. in opposite to the other interrupts serving as dma trigger factors, the tmr0 interrupts inttr0od and inttr0cd, and the tmr1 interrupts inttr1od and inttr1cd respectively, are not shared with dma transfer completion interrupt of channel 2 (intdma2) and channel 3 (intdma3) respectively. these dma completion interrupts have dedicated entries in the interrupt source list (refer to table 7-1: ?interrupt/exception source list? on page 207 ). table 6-4 shows the relations between dma trigger factors and dma completion interrupts. note: an interrupt request is not generated for a signal, which serves as dma trigger factor. instead of this the defined dma completion interrupt request is executed on the same interrupt entry address of the dma trigger factor. table 6-4: relations between dma trigger factors and dma completion interrupts dma channel dma trigger factor dma completion interrupt remark name entry handler address 0 intad0 intdma0 intad0 00000670h note 1 intad1 intdma1 intad1 00000680h note 2 inttr0cd or intr0od intdma2 intdma2 000006f0h 3 inttr1cd or intr1od intdma3 intdma3 00000700h 4, 5 intc30 intdma4, intdma5 intc30 000005e0h note intc31 intc31 00000600h note intcb0r intcb0r 00000580h note intcb1r intcb1r 000005b0h note intuc0r intuc0r 00000620h note intuc1r intuc1r 00000650h note 6, 7 intc30 intdma6, intdma7 intc30 000005e0h note intc31 intc31 00000600h note intcb0t intcb0t 00000570h note intcb1t intcib1t 000005a0h note intuc0t intuc0t 00000630h note intuc1t intuc1t 00000660h note
206 chapter 6 dma functions (dma controller) user?s manual u16580ee2v0ud00 figure 6-21: correlation between serial i/o interface interrupts and dma completion interrupts remark: interrupt signals with quote mark (?) are signals, which are directly connected from the cor- responding serial interface. interrupt signals without quote mark are provided to the interrupt controller. intuc0r intuc1r intuc0r' intuc1r' intuc0r' intuc1r' intcb0r' intcb1r' intcsi30' intcsi31' intcb0r intcb1r intcb0r' intcb1r' intcsi31' intcsi30' intcsi30 intcsi31 intuc0r intuc1r intuc0r' intuc1r' intuc0t' intuc1t' intcb0t' intcb1t' intcsi30' intcsi31' intcb0r intcb1r intcb0r' intcb1r' intcsi31' intcsi30' dma channel 4 dma channel 5 dma channel 6 dma channel 7 intdma4 intdma5 intdma6 intdma7
207 user?s manual u16580ee2v0ud00 chapter 7 interrupt/except ion processing function the v850e/ph2 microcontroller is provided with a dedicated interrupt controller (intc) for interrupt servicing, which realizes a high-performance interrupt function that can service interrupt requests from a total of 107 sources. an interrupt is an event that occurs asynchronously (independently of program execution), and an exception is an event that occurs synchronously (dependently on program execution). generally, an exception takes precedence over an interrupt. the v850e/ph2 microcontroller can process interrupt requests from the internal peripheral hardware and external sources. moreover, exception processing can be started (exception trap) by the trap instruction (software except ion) or by generation of an exceptio n event (fetching of an illegal op code). 7.1 features ? interrupts ? non-maskable interrupt: 1 source ? maskable interrupt: 106 sources ? 8 levels programmable priorities ? mask specification for the interrupt request according to priority ? mask can be specified to each maskable interrupt request. ? valid edge for detection of external interrupt request signal can be specified. ? exceptions ? software exceptions: 32 sources ? exception trap: 1 source (illegal op code exception) interrupt/exception sources are listed in table 7-1. table 7-1: interrupt/exception source list (1/5) ty p e classification interrupt/exception source default priority exception code handler address restored pc name control register generating source gener. unit reset interrupt reset ? reset input pin ? 0000h 00000000h undefined non- maskable interrupt nmi ? nmi input pin ? 0010h 00000010h nextpc software exception exception trap0n note ? trap instruction ? ? 004nh note 00000040h nextpc exception trap1n note ? trap instruction ? ? 005nh note 00000050h nextpc exception trap exception ilgop/ dbtrap ? illegal opcode/ dbtrap instruction ? ? 0060h 00000060h nextpc maskable interrupt intp0 pic0 intp0 valid edge input pin 0 0080h 00000080h nextpc interrupt intp1 pic1 intp1 valid edge input pin 1 0090h 00000090h nextpc interrupt intp2 pic2 intp2 valid edge input pin 2 00a0h 000000a0h nextpc interrupt intp3 pic3 intp3 valid edge input pin 3 00b0h 000000b0h nextpc interrupt intp4 pic4 intp4 valid edge input pin 4 00c0h 000000c0h nextpc note: n = 0 to fh
208 chapter 7 interrupt/exception processing function user?s manual u16580ee2v0ud00 maskable interrupt intp5 pic5 intp5 valid edge input pin 5 00d0h 000000d0h nextpc interrupt intp6 pic6 intp6 valid edge input pin 6 00e0h 000000e0h nextpc interrupt intp7 pic7 intp7 valid edge input pin 7 00f0h 000000f0h nextpc interrupt intp8 pic8 intp8 valid edge input pin 8 0100h 00000100h nextpc interrupt intp9 pic9 intp9 valid edge input pin 9 0110h 00000110h nextpc interrupt intp10 pic10 intp10 valid edge input pin 10 0120h 00000120h nextpc interrupt intp11 pic11 intp11 valid edge input pin 11 0130h 00000130h nextpc interrupt intp12 pic12 intp12 valid edge input pin 12 0140h 00000140h nextpc interrupt inttr0ov pic13 tr0cnt overflow tmr0 13 0150h 00000150h nextpc interrupt inttr0cc0 pic14 tr0ccr0 match tmr0 14 0160h 00000160h nextpc interrupt inttr0cc1 pic15 tr0ccr1 match tmr0 15 0170h 00000170h nextpc interrupt inttr0cc2 pic16 tr0ccr2 match tmr0 16 0180h 00000180h nextpc interrupt inttr0cc3 pic17 tr0ccr3 match tmr0 17 0190h 00000190h nextpc interrupt inttr0cc4 pic18 tr0ccr4 match tmr0 18 01a0h 000001a0h nextpc interrupt inttr0cc5 pic19 tr0ccr5 match tmr0 19 01b0h 000001b0h nextpc interrupt inttr0cd pic20 tr0cnt top reversal tmr0 20 01c0h 000001c0h nextpc interrupt inttr0od pic21 tr0cnt bottom reversal tmr0 21 01d0h 000001d0h nextpc interrupt inttr0er pic22 tmr0 error detection tmr0 22 01e0h 000001e0h nextpc interrupt inttr1ov pic23 tr1cnt overflow tmr1 23 01f0h 000001f0h nextpc interrupt inttr1cc0 pic24 tir10 capture input/ tr1ccr0 match tmr1 24 0200h 00000200h nextpc interrupt inttr1cc1 pic25 tir11 capture input/ tr1ccr1 match tmr1 25 0210h 00000210h nextpc interrupt inttr1cc2 pic26 tir12 capture input/ tr1ccr2 match tmr1 26 0220h 00000220h nextpc interrupt inttr1cc3 pic27 tir13 capture input/ tr1ccr3 match tmr1 27 0230h 00000230h nextpc interrupt inttr1cc4 pic28 tr1ccr4 match tmr1 28 0240h 00000240h nextpc interrupt inttr1cc5 pic29 tr1ccr5 match tmr1 29 0250h 00000250h nextpc interrupt inttr1cd pic30 tr1cnt top reversal tmr1 30 0260h 00000260h nextpc interrupt inttr1od pic31 tr1cnt bottom reversal tmr1 31 0270h 00000270h nextpc interrupt inttr1er pic32 tmr1 error detection tmr1 32 0280h 00000280h nextpc interrupt intt0ov pic33 tmt0 overflow tmt0 33 0290h 00000290h nextpc interrupt intt0cc0 pic34 tit00 capture input/ tt0ccr0 match tmt0 34 02a0h 000002a0h nextpc interrupt intt0cc1 pic35 tit01 capture input/ tt0ccr1 match tmt0 35 02b0h 000002b0h nextpc interrupt intt0ec pic36 tmt0 encoder clear tmt0 36 02c0h 000002c0h nextpc interrupt intt1ov pic37 tmt1 overflow tmt1 37 02d0h 000002d0h nextpc interrupt intt1cc0 pic38 tit10 capture input/ tt1ccr0 match tmt1 38 02e0h 000002e0h nextpc interrupt intt1cc1 pic39 tit11 capture input/ tt1ccr1 match tmt1 39 02f0h 000002f0h nextpc table 7-1: interrupt/exception source list (2/5) ty p e classification interrupt/exception source default priority exception code handler address restored pc name control register generating source gener. unit
209 chapter 7 interrupt/exception processing function user?s manual u16580ee2v0ud00 maskable interrupt intt1ec pic40 tmt1 encoder clear tmt1 40 0300h 00000300h nextpc interrupt intp0ov pic41 tmp0 overflow tmp0 41 0310h 00000310h nextpc interrupt intp0cc0 pic42 tip00 capture input/ tp0ccr0 match tmp0 42 0320h 00000320h nextpc interrupt intp0cc1 pic43 tip01 capture input/ tp0ccr1 match tmp0 43 0330h 00000330h nextpc interrupt intp1ov pic44 tmp1 overflow tmp1 44 0340h 00000340h nextpc interrupt intp1cc0 pic45 tip10 pin/ tp1ccr0 match tmp1 45 0350h 00000350h nextpc interrupt intp1cc1 pic46 tip11 capture input/ tp1ccr1 match tmp1 46 0360h 00000360h nextpc interrupt intp2ov pic47 tmp2 overflow tmp2 47 0370h 00000370h nextpc interrupt intp2cc0 pic48 tip20 capture input/ tp2ccr0 match tmp2 48 0380h 00000380h nextpc interrupt intp2cc1 pic49 tip21capture input/ tp2ccr1 match tmp2 49 0390h 00000390h nextpc interrupt intp3ov pic50 tmp3 overflow tmp3 50 03a0h 000003a0h nextpc interrupt intp3cc0 pic51 tip30 capture input/ tp3ccr0 match tmp3 51 03b0h 000003b0h nextpc interrupt intp3cc1 pic52 tip31 capture input/ tp3ccr1 match tmp3 52 03c0h 000003c0h nextpc interrupt intp4ov pic53 tmp4 overflow tmp4 53 03d0h 000003d0h nextpc interrupt intp4cc0 pic54 tip40 capture input/ tp4ccr0 match tmp4 54 03e0h 000003e0h nextpc interrupt intp4cc1 pic55 tip41 capture input/ tp4ccr1 match tmp4 55 03f0h 000003f0h nextpc interrupt intp5ov pic56 tmp5overflow tmp5 56 0400h 00000400h nextpc interrupt intp5cc0 pic57 tip50 capture input/ tp5ccr0 match tmp5 57 0410h 00000410h nextpc interrupt intp5cc1 pic58 tip51 capture input/ tp5ccr1 match tmp5 58 0420h 00000420h nextpc interrupt intp6ov pic59 tmp6 overflow tmp6 59 0430h 00000430h nextpc interrupt intp6cc0 pic60 tip60 capture input/ tp6ccr0 match tmp6 60 0440h 00000440h nextpc interrupt intp6cc1 pic61 tip61 capture input/ tp6ccr1 match tmp6 61 0450h 00000450h nextpc interrupt intp7ov pic62 tmp7 overflow tmp7 62 0460h 00000460h nextpc interrupt intp7cc0 pic63 tip70 capture input/ tp7ccr0 match tmp7 63 0470h 00000470h nextpc interrupt intp7cc1 pic64 tip71 capture input/ tp7ccr1 match tmp7 64 0480h 00000480h nextpc interrupt intp8ov pic65 tmp8 overflow tmp8 65 0490h 00000490h nextpc interrupt intp8cc0 pic66 tp8ccr0 match tmp8 66 04a0h 000004a0h nextpc interrupt intp8cc1 pic67 tp8ccr1 match tmp8 67 04b0h 000004b0h nextpc interrupt intbrg0 pic68 brg0 match brg0 68 04c0h 000004c0h nextpc interrupt intbrg1 pic69 brg1 match brg1 69 04d0h 000004d0h nextpc interrupt intbrg2 pic70 brg2 match brg2 70 04e0h 000004e0h nextpc table 7-1: interrupt/exception source list (3/5) ty p e classification interrupt/exception source default priority exception code handler address restored pc name control register generating source gener. unit
210 chapter 7 interrupt/exception processing function user?s manual u16580ee2v0ud00 maskable interrupt intc0err pic71 fcan0 error fcan0 71 04f0h 000004f0h nextpc interrupt intc0wup pic72 fcan0 wake up fcan0 72 0500h 00000500h nextpc interrupt intc0rec pic73 fcan0 bus reception fcan0 73 0510h 00000510h nextpc interrupt intc0trx pic74 fcan0 bus transmission fcan0 74 0520h 00000520h nextpc interrupt intc1err pic75 fcan1 error fcan1 75 0530h 00000530h nextpc interrupt intc1wup pic76 fcan1 wake up fcan1 76 0540h 00000540h nextpc interrupt intc1rec pic77 fcan1 bus reception fcan1 77 0550h 00000550h nextpc interrupt intc1trx pic78 fcan1 bus transmission fcan1 78 0560h 00000560h nextpc interrupt intcb0t pic79 csib0 transmission enable/ dma transfer completion csib0/ dmac 79 0570h 00000570h nextpc interrupt intcb0r pic80 csib0 reception completion/ dma transfer completion csib0/ dmac 80 0580h 00000580h nextpc interrupt intcb0re pic81 csib0 receive error csib0 81 0590h 00000590h nextpc interrupt intcb1t pic82 csib1 transmission enable/ dma transfer completion csib1/ dmac 82 05a0h 000005a0h nextpc interrupt intcb1r pic83 csib1 reception completion/ dma transfer completion csib1/ dmac 83 05b0h 000005b0h nextpc interrupt intcb1re pic84 csib1 receive error csib1 84 05c0h 000005c0h nextpc interrupt intc30ovf pic85 csi30 overrun csi30 85 05d0h 000005d0h nextpc interrupt intc30 pic86 csi30 transmission enable/ dma transfer completion csi30/ dmac 86 05e0h 000005e0h nextpc interrupt intc31ovf pic87 csi31 overrun csi31 87 05f0h 000005f0h nextpc interrupt intc31 pic88 csi31 transmission enable/ dma transfer completion csi31/ dmac 88 0600h 00000600h nextpc interrupt intuc0re pic89 uartc0 receive error uartc0 89 0610h 00000610h nextpc interrupt intuc0r pic90 uartc0 reception completion/ dma transfer completion uartc0 / dmac 90 0620h 00000620h nextpc interrupt intuc0t pic91 uartc0 transmission enable/ dma transfer completion uartc0 / dmac 91 0630h 00000630h nextpc interrupt intuc1re pic92 uartc1receive error uartc1 92 0640h 00000640h nextpc interrupt intuc1r pic93 uartc1 reception completion/ dma transfer completion uartc1 / dmac 93 0650h 00000650h nextpc interrupt intuc1t pic94 uartc1 transmission enable/ dma transfer completion uartc1 / dmac 94 0660h 00000660h nextpc interrupt intad0 pic95 adc0 conversion completion/ dma transfer completion adc0/ dmac 95 0670h 00000670h nextpc table 7-1: interrupt/exception source list (4/5) ty p e classification interrupt/exception source default priority exception code handler address restored pc name control register generating source gener. unit
211 chapter 7 interrupt/exception processing function user?s manual u16580ee2v0ud00 remarks: 1. default priority: the priority order that takes precedence when two or more maskable interrupt requests at the same software priority level are present at the same time. the highest priority is 0. restored pc: the valu e of pc saved when an interrup t/exception (other than reset) occurs is the value of the current pc, which holds the address of the next instruction to be executed when returning from interrupt handling routine. however, if the interrupt request occurs during execution of a divide instruction (div, divh, divu or divhu), the value of the pc saved is the address of the divide instruction itself (rather than the address of the instruction following the divide instruction), because the division is cancelled in this case, and restarted completely after interrupt servicing. nextpc: the pc value that proceeds the processing following interrupt/ exception processing. 2. the execution address of the illegal instruction when an ille gal opcode exception occurs is calculated by (restored pc - 4). maskable interrupt intad1 pic96 adc1 conversion completion/ dma transfer completion adc1/ dmac 96 0680h 00000680h nextpc interrupt intcc10 pic97 cc10 capture input/ compare match tmenc1 97 0690h 00000690h nextpc interrupt intcc11 pic98 cc11capture input/ compare match tmenc1 98 06a0h 000006a0h nextpc interrupt intcm10 pic99 cm10 compare match tmenc1 99 06b0h 000006b0h nextpc interrupt intcm11 pic100 cm10 compare match tmenc1 100 06c0h 000006c0h nextpc interrupt intovf pic101 tmenc1 overflow tmenc1 101 06d0h 000006d0h nextpc interrupt intudf pic102 tmenc1 underflow tmenc1 102 06e0h 000006e0h nextpc interrupt intdma2 pic103 dma channel 2 transfer completion dmac 103 06f0h 000006f0h nextpc interrupt intdma3 pic104 dma channel 3 transfer completion dmac 104 0700h 00000700h nextpc interrupt intperr pic105 internal ram parity error iram 105 0710h 00000710h nextpc table 7-1: interrupt/exception source list (5/5) ty p e classification interrupt/exception source default priority exception code handler address restored pc name control register generating source gener. unit
212 chapter 7 interrupt/exception processing function user?s manual u16580ee2v0ud00 7.2 non-maskable interrupt a non-maskable interrupt request is acknowledged unconditionally, even when interrupts are in the interrupt disabled (di) status. a nmi is not subject to priority control and takes precedence over all the other interrupts. a non-maskable interrupt request is input from the nmi pin. when the valid edge specified by esn0, esn1 bits of the interrupt mode register 0 (intm0) is detected at the nmi pin, the interrupt occurs. while the service program of the non-maskable interrupt is being executed (psw.np = 1), the acknowledgment of another non-maskable interrupt request is held pending. the pending nmi is acknowledged after the original service program of the non-maskable interrupt under execution has been terminated (by the reti instruction). note that if two or more nmi requests are input during the execution of the service program for a nmi, the number of nmis that will be acknowledged after psw.np is cleared to 0 is only one. remark: psw.np: the np bit of the psw register.
213 chapter 7 interrupt/exception processing function user?s manual u16580ee2v0ud00 7.2.1 operation if a non-maskable interrupt is generated, the cpu performs the following processing, and transfers control to the handler routine: (1) saves the restored pc to fepc. (2) saves the current psw to fepsw. (3) writes exception code 0010h to the higher half-word (fecc) of ecr. (4) sets the np and id bits of the psw and clears the ep bit. (5) sets the handler address (00000010h) corresponding to the non-maskable interrupt to the pc, and transfers control. the processing configuration of a non-maskable interrupt is shown in figure 7-1. figure 7-1: processing configuration of non-maskable interrupt non-maskable interrupt request fepc restored pc fepsw psw ecr.fecc exception code psw.np 1 psw.ep 0 psw.id 1 pc nmi-handler address 0 psw.np intc acknowledgement cpu processing 1 interrupt service interrupt request pending nmi input
214 chapter 7 interrupt/exception processing function user?s manual u16580ee2v0ud00 figure 7-2: acknowledging non-maskable interrupt request (a) if a new nmi request is generated while a nmi service program is being executed (b) if a new nmi request is generated twice while a nmi service program is being executed main routine nmi request nmi request (psw.np = 1) nmi request held pending because psw.np = 1 pending nmi request processed main routine nmi request nmi request held pending because nmi service program is being processed only one nmi request is acknowledged even though two nmi requests are generated nmi request held pending because nmi service program is being processed
215 chapter 7 interrupt/exception processing function user?s manual u16580ee2v0ud00 7.2.2 restore execution is restored from the non-maskable interrupt (nmi) processing by the reti instruction. when the reti instruction is executed, the cpu performs the following processing, and transfers control to the address of the restored pc. <1> restores the values of the pc and the psw from fepc and fepsw, respectively, because the ep bit of the psw is 0 and the np bit of the psw is 1. <2> transfers control back to the address of the restored pc and psw. figure 7-3 illustrates how the re ti instruction is processed. figure 7-3: reti instruction processing caution: when the psw.ep bit and psw.np bit are changed by the ldsr instruction during non-maskable interrupt processing, in order to restore the pc and psw correctly during recovery by the reti instruction, it is necessary to set psw.ep back to 0 and psw.np back to 1 using the ldsr instruction immediately before the reti instruction. remark: the solid line indicates the cpu processing flow. psw.ep reti instruction psw.np original processing restored 1 1 0 0 pc psw eipc eipsw pc psw fepc fepsw
216 chapter 7 interrupt/exception processing function user?s manual u16580ee2v0ud00 7.2.3 non-maskable interrupt status flag (np) the np flag is a status flag that indicates that non-maskable interrupt (nmi) processing is under execution. this flag is set when a nmi interrupt has been acknowledged, and masks all interrupt requests and exceptions to prohibit multiple interrupts from being acknowledged. figure 7-4: non-maskable interrupt status flag (np) 7.2.4 edge detection function the behaviour of the non-maskable interrupt (nmi) can be specified by the interrupt mode register 0 (intm0). the valid edge of the external nmi pin input can be specified by the esn0 and esn1 bits. the intm0 register can be read/written in 8-bit or 1-bit units. figure 7-5: nmi edge detection specification: interrupt mode register 0 (intm0) 31 8765 4 3210 after reset 00000020h psw 0 000000 00000000000000000 np ep id sat cy ov s z np nmi servicing status 0 no nmi interrupt servicing 1 nmi interrupt currently servicing after reset: 00h r/w address: fffff880h 76543210 intm0 es21 es20 es11 es10 es01 es00 esn1 esn0 esn1 esn0 valid edge specification of nmi pin input 0 0 falling edge 0 1 rising edge 1 0 setting prohibited 1 1 both, rising and falling edges
217 chapter 7 interrupt/exception processing function user?s manual u16580ee2v0ud00 7.3 maskable interrupts maskable interrupt requests can be masked by interrupt control registers. the v850e/ph2 has 106 maskable interrupt sources. if two or more maskable interrupt requests are generated at the same time, they are acknowledged according to the default priority. in addition to the default priority, eight levels of priorities can be specified by using the interrupt control registers (programmable priority control). when an interrupt request has been acknowledged, the acknowledgement of other maskable interrupt requests is disabled and the interrupt disabled (di) status is set. when the ei instruction is executed in an interrupt processing routine, the interrupt enabled (ei) status is set, which enables servicing of interrupts having a higher priority than the interrupt request in progress (specified by the interrupt control register). note that only interrupts with a higher priority will have this capability; interrupts with the same priority level cannot be nested. however, if multiple interrupts are executed, the following processing is necessary. (1) save eipc and eipsw in memory or a general-purpose register before executing the ei instruction. (2) execute the di instruction before executing the reti instruction, then reset eipc and eipsw with the values saved in (1). 7.3.1 operation if a maskable interrupt occurs by int input, the cpu performs the following processing, and transfers control to a handler routine: (1) saves the restored pc to eipc. (2) saves the current psw to eipsw. (3) writes an exception code to the lower half-word of ecr (eicc). (4) sets the id bit of the psw and clears the ep bit. (5) sets the handler address corresponding to each interrupt to the pc, and transfers control. the processing configuration of a maskable interrupt is shown in figure 7-6.
218 chapter 7 interrupt/exception processing function user?s manual u16580ee2v0ud00 figure 7-6: maskable interrupt processing note: for the ispr register, see 7.3.6 ?in-service priority register (ispr)? on page 230 . an int input masked by the interrupt controllers and an int input that occurs while another interrupt is being processed (when psw.np = 1 or psw.id = 1) are held pending internally by the interrupt controller. in such case, if the interrupts are unmasked, or when psw.np = 0 and psw.id = 0 as set by the reti and ldsr instructions, input of the pending int starts the new maskable interrupt processing. int input xxif = 1 no xxmk = 0 no is the interrupt mask released? yes yes no no no maskable interrupt request interrupt request held pending psw.np psw.id 1 1 interrupt request held pending 0 0 interrupt processing cpu processing intc accepted yes yes yes priority higher than that of interrupt currently being processed? priority higher than that of other interrupt request? highest default priority of interrupt requests with the same priority? eipc eipsw ecr.eicc psw.ep psw.id corresponding bit of ispr note pc restored pc psw exception code 0 1 1 handler address
219 chapter 7 interrupt/exception processing function user?s manual u16580ee2v0ud00 7.3.2 restore recovery from maskable interrupt processing is carried out by the reti instruction. when the reti instruction is executed, the cpu performs the following steps, and transfers control to the address of the restored pc. (1) restores the values of the pc and the psw from eipc and eipsw because the ep bit of the psw is 0 and the np bit of the psw is 0. (2) transfers control to the address of the restored pc and psw. figure 7-7 illustrates the proces sing of the reti instruction. figure 7-7: reti instruction processing note: for the ispr register, see 7.3.6 ?in-service priority register (ispr)? on page 230 . caution: when the psw.ep bit and the psw.np bit are changed by the ldsr instruction during maskable interrupt processing, in order to restore the pc and psw correctly during recovery by the reti instruction, it is necessary to set psw.ep back to 0 and psw.np back to 0 using the ldsr instruction immediately before the reti instruction. remark: the solid lines show the cpu processing flow. psw.ep reti instruction psw.np restores original processing 1 1 0 0 pc psw eipc eipsw pc psw fepc fepsw
220 chapter 7 interrupt/exception processing function user?s manual u16580ee2v0ud00 7.3.3 priorities of maskable interrupts the v850e/ph2 provides multiple interrupt servic ing in which an interrupt is acknowledged while another interrupt is being servic ed. multiple interrupts can be controlled by priority levels. there are two types of priority level control: control based on the default priority levels, and control based on the programmable priority levels that are s pecified by the interrupt pr iority level specification bit (prn) of the interrupt control register (picn). when two or more interrupts having the same priority level specified by the prn bit are generated at the same time, interrupts are serviced in order depending on the priority level allocated to each interrupt request type (default priority level) beforehand. for more information, refer to table 7-1, ?interrupt/exception source list,? on page 207 . the programmable priority control customizes interrupt requests into eight levels by setting the priority level specification flag. note that when an interrupt request is acknowledged, the id flag of psw is automatically set to 1. therefore, when multiple interrupts are to be used, clear the id flag to 0 beforehand (for example, by placing the ei instruction in the interrupt service program) to set the interrupt enable mode. remark: n = 0 to 105 (number of interrupt)
221 chapter 7 interrupt/exception processing function user?s manual u16580ee2v0ud00 figure 7-8: example of processing in which another interrupt request is issued while an interrupt is being processed (1/2) caution: the values of the eipc and eipsw registers must be saved before executing multiple interrupts. when returning from multiple interrupt servicing, restore the values of eipc and eipsw after exec uting the di instruction. remarks: 1. a to u in the figure are the temporary names of interrupt requests shown for the sake of explanation. 2. the default priority in the figure indicates the relative priority between two interrupt requests. main routine ei ei interrupt request a (level 3) processing of a processing of b processing of c interrupt request c (level 3) processing of d processing of e ei interrupt request e (level 2) processing of f ei processing of g interrupt request g (level 1) interrupt request h (level 1) processing of h interrupt request b is acknowledged because the priority of b is higher than that of a and interrupts are enabled. although the priority of interrupt request d is higher than that of c, d is held pending because interrupts are disabled. interrupt request f is held pending even if interrupts are enabled because its priority is lower than that of e. interrupt request h is held pending even if interrupts are enabled because its priority is the same as that of g. interrupt request b (level 2) interrupt request d (level 2) interrupt request f (level 3)
222 chapter 7 interrupt/exception processing function user?s manual u16580ee2v0ud00 figure 7-8: example of processing in which another interrupt request is issued while an interrupt is being processed (2/2) notes: 1. lower default priority 2. higher default priority caution: the values of the eipc and eipsw registers must be saved before executing multiple interrupts. when returning from multiple interrupt servicing, restore the values of eipc and eipsw after exec uting the di instruction. main routine ei interrupt request i (level 2) process ing of i process ing of k interrupt request j (level 3) process ing of j interrupt request l (level 2) ei ei ei interrupt request o (level 3) interrupt request s (level 1) interrupt request k (level 1) process ing of l process ing of n process ing of m process ing of s process ing of u process ing of t interrupt request m (level 3) interrupt request n (level 1) process ing of o interrupt request p (level 2) interrupt request q (level 1) interrupt request r (level 0) interrupt request u (level 2) note 2 interrupt request t (level 2) note 1 process ing of p process ing of q process ing of r ei if levels 3 to 0 are acknowledged interrupt request j is held pending because its priority is lower than that of i. k that occurs after j is acknowledged because it has the higher priority. interrupt requests m and n are held pending because servicing of l is performed in the interrupt disabled status. pending interrupt requests are acknowledged after servicing of interrupt request l. at this time, interrupt request n is acknowledged first even though m has occurred first because the priority of n is higher than that of m. pending interrupt requests t and u are acknowledged after servicing of s. because the priorities of t and u are the same, u is acknowledged first because it has the higher default priority, regardless of the order in which the interrupt requests have been generated.
223 chapter 7 interrupt/exception processing function user?s manual u16580ee2v0ud00 figure 7-9: example of processing interrupt requests simultaneously generated caution: the values of the eipc and eipsw registers must be saved before executing multiple interrupts. when returning from multiple interrupt servicing, restore the values of eipc and eipsw after exec uting the di instruction. default priority a > b > c main routine ei interrupt request a (level 2) interrupt request b (level 1) interrupt request c (level 1) processing of interrupt request b . . processing of interrupt request c processing of interrupt request a interrupt request b and c are acknowledged first according to their priorities. because the priorities of b and c are the same, b is acknowledged first according to the default priority.
224 chapter 7 interrupt/exception processing function user?s manual u16580ee2v0ud00 7.3.4 interrupt control register (picn) an interrupt control register is assigned to each interrupt request (maskable interrupt) and sets the control conditions for each maskable interrupt request. this register can be read/written in 8-bit or 1-bit units. figure 7-10: interrupt control register (picn) note: automatically reset by hardware when interrupt request is acknowledged. remark: n = 0 to 105 (see table 7-2: addresses and bits of interrupt control registers ) after reset: 47h r/w address: refer to table 7-2 76543210 picn ifn mkn 0 0 0 prn2 prn1 prn0 ifn interrupt request flag n note 0 interrupt request is not issued 1 interrupt request issued mkn interrupt mask flag n 0 interrupt servicing enabled 1 interrupt servicing disabled (ifn flag hold pending) prn2 prn1 prn0 interrupt pr iority specification n 0 0 0 specifies level 0 (highest) 0 0 1 specifies level 1 0 1 0 specifies level 2 0 1 1 specifies level 3 1 0 0 specifies level 4 1 0 1 specifies level 5 1 1 0 specifies level 6 1 1 1 specifies level 7 (lowest)
225 chapter 7 interrupt/exception processing function user?s manual u16580ee2v0ud00 table 7-2: addresses and bits of interrupt control registers (1/3) address register bit associated interrupt 7 6543 2 1 0 fffff110h pic0 if0 mk0 0 0 0 pr02 pr01 pr00 intp0 fffff112h pic1 if1 mk1 0 0 0 pr12 pr11 pr10 intp1 fffff114h pic2 if2 mk2 0 0 0 pr22 pr21 pr20 intp2 fffff116h pic3 if3 mk3 0 0 0 pr32 pr31 pr30 intp3 fffff118h pic4 if4 mk4 0 0 0 pr42 pr41 pr40 intp4 fffff11ah pic5 if5 mk5 0 0 0 pr52 pr51 pr50 intp5 fffff11ch pic6 if6 mk6 0 0 0 pr62 pr61 pr60 intp6 fffff11eh pic7 if7 mk7 0 0 0 pr72 pr71 pr70 intp7 fffff120h pic8 if8 mk8 0 0 0 pr82 pr81 pr80 intp8 fffff122h pic9 if9 mk9 0 0 0 pr92 pr91 pr90 intp9 fffff124h pic10 if10 mk10 0 0 0 pr102 pr101 pr100 intp10 fffff126h pic11 if11 mk11 0 0 0 pr112 pr111 pr110 intp11 fffff128h pic12 if12 mk12 0 0 0 pr122 pr121 pr120 intp12 fffff12ah pic13 if13 mk13 0 0 0 pr132 pr131 pr130 inttr0ov fffff12ch pic14 if14 mk14 0 0 0 pr142 pr141 pr140 inttr0cc0 fffff12eh pic15 if15 mk15 0 0 0 pr152 pr151 pr150 inttr0cc1 fffff130h pic16 if16 mk16 0 0 0 pr162 pr161 pr160 inttr0cc2 fffff132h pic17 if17 mk17 0 0 0 pr172 pr171 pr170 inttr0cc3 fffff134h pic18 if18 mk18 0 0 0 pr182 pr181 pr180 inttr0cc4 fffff136h pic19 if19 mk19 0 0 0 pr192 pr191 pr190 inttr0cc5 fffff138h pic20 if20 mk20 0 0 0 pr202 pr201 pr200 inttr0cd fffff13ah pic21 if21 mk21 0 0 0 pr212 pr211 pr210 inttr0od fffff13ch pic22 if22 mk22 0 0 0 pr222 pr221 pr220 inttr0er fffff13eh pic23 if23 mk23 0 0 0 pr232 pr231 pr230 inttr1ov fffff140h pic24 if24 mk24 0 0 0 pr242 pr241 pr240 inttr1cc0 fffff142h pic25 if25 mk25 0 0 0 pr252 pr251 pr250 inttr1cc1 fffff144h pic26 if26 mk26 0 0 0 pr262 pr261 pr260 inttr1cc2 fffff146h pic27 if27 mk27 0 0 0 pr272 pr271 pr270 inttr1cc3 fffff148h pic28 if28 mk28 0 0 0 pr282 pr281 pr280 inttr1cc4 fffff14ah pic29 if29 mk29 0 0 0 pr292 pr291 pr290 inttr1cc5 fffff14ch pic30 if30 mk30 0 0 0 pr302 pr301 pr300 inttr1cd fffff14eh pic31 if31 mk31 0 0 0 pr312 pr311 pr310 inttr1od fffff150h pic32 if32 mk32 0 0 0 pr322 pr321 pr320 inttr1er fffff152h pic33 if33 mk33 0 0 0 pr332 pr331 pr330 intt0ov fffff154h pic34 if34 mk34 0 0 0 pr342 pr341 pr340 intt0cc0 fffff156h pic35 if35 mk35 0 0 0 pr352 pr351 pr350 intt0cc1 fffff158h pic36 if36 mk36 0 0 0 pr362 pr361 pr360 intt0ec fffff15ah pic37 if37 mk37 0 0 0 pr372 pr371 pr370 intt1ov fffff15ch pic38 if38 mk38 0 0 0 pr382 pr381 pr380 intt1cc0 fffff15eh pic39 if39 mk39 0 0 0 pr392 pr391 pr390 intt1cc1
226 chapter 7 interrupt/exception processing function user?s manual u16580ee2v0ud00 fffff160h pic40 if40 mk40 0 0 0 pr402 pr401 pr400 intt1ec fffff162h pic41 if41 mk41 0 0 0 pr412 pr411 pr410 intp0ov fffff164h pic42 if42 mk42 0 0 0 pr422 pr421 pr420 intp0cc0 fffff166h pic43 if43 mk43 0 0 0 pr432 pr431 pr430 intp0cc1 fffff168h pic44 if44 mk44 0 0 0 pr442 pr441 pr440 intp1ov fffff16ah pic45 if45 mk45 0 0 0 pr452 pr451 pr450 intp1cc0 fffff16ch pic46 if46 mk46 0 0 0 pr462 pr461 pr460 intp1cc1 fffff16eh pic47 if47 mk47 0 0 0 pr472 pr471 pr470 intp2ov fffff170h pic48 if48 mk48 0 0 0 pr482 pr481 pr480 intp2cc0 fffff172h pic49 if49 mk49 0 0 0 pr492 pr491 pr490 intp2cc1 fffff174h pic50 if50 mk50 0 0 0 pr502 pr501 pr500 intp3ov fffff176h pic51 if51 mk51 0 0 0 pr512 pr511 pr510 intp3cc0 fffff178h pic52 if52 mk52 0 0 0 pr522 pr521 pr520 intp3cc1 fffff17ah pic53 if53 mk53 0 0 0 pr532 pr531 pr530 intp4ov fffff17ch pic54 if54 mk54 0 0 0 pr542 pr541 pr540 intp4cc0 fffff17eh pic55 if55 mk55 0 0 0 pr552 pr551 pr550 intp4cc1 fffff180h pic56 if56 mk56 0 0 0 pr562 pr561 pr560 intp5ov fffff182h pic57 if57 mk57 0 0 0 pr572 pr571 pr570 intp5cc0 fffff184h pic58 if58 mk58 0 0 0 pr582 pr581 pr580 intp5cc1 fffff186h pic59 if59 mk59 0 0 0 pr592 pr591 pr590 intp6ov fffff188h pic60 if60 mk60 0 0 0 pr602 pr601 pr600 intp6cc0 fffff18ah pic61 if61 mk61 0 0 0 pr612 pr611 pr610 intp6cc1 fffff18ch pic62 if62 mk62 0 0 0 pr622 pr621 pr620 intp7ov fffff18eh pic63 if63 mk63 0 0 0 pr632 pr631 pr630 intp7cc0 fffff190h pic64 if64 mk64 0 0 0 pr642 pr641 pr640 intp7cc1 fffff192h pic65 if65 mk65 0 0 0 pr652 pr651 pr650 intp8ov fffff194h pic66 if66 mk66 0 0 0 pr662 pr661 pr660 intp8cc0 fffff196h pic67 if67 mk67 0 0 0 pr672 pr671 pr670 intp8cc1 fffff198h pic68 if68 mk68 0 0 0 pr682 pr681 pr680 intbrg0 fffff19ah pic69 if69 mk69 0 0 0 pr692 pr691 pr690 intbrg1 fffff19ch pic70 if70 mk70 0 0 0 pr702 pr701 pr700 intbrg2 fffff19eh pic71 if71 mk71 0 0 0 pr712 pr711 pr710 intc0err fffff1a0h pic72 if72 mk72 0 0 0 pr722 pr721 pr720 intc0wup fffff1a2h pic73 if73 mk73 0 0 0 pr732 pr731 pr730 intc0rec fffff1a4h pic74 if74 mk74 0 0 0 pr742 pr741 pr740 intc0trx fffff1a6h pic75 if75 mk75 0 0 0 pr752 pr751 pr750 intc1err fffff1a8h pic76 if76 mk76 0 0 0 pr762 pr761 pr760 intc1wup fffff1aah pic77 if77 mk77 0 0 0 pr772 pr771 pr770 intc1rec fffff1ach pic78 if78 mk78 0 0 0 pr782 pr781 pr780 intc1trx fffff1aeh pic79 if79 mk79 0 0 0 pr792 pr791 pr790 intcb0t table 7-2: addresses and bits of interrupt control registers (2/3) address register bit associated interrupt 76543210
227 chapter 7 interrupt/exception processing function user?s manual u16580ee2v0ud00 fffff1b0h pic80 if80 mk80 0 0 0 pr802 pr801 pr800 intcb0r fffff1b2h pic81 if81 mk81 0 0 0 pr812 pr811 pr810 intcb0re fffff1b4h pic82 if82 mk82 0 0 0 pr822 pr821 pr820 intcb1t fffff1b6h pic83 if83 mk83 0 0 0 pr832 pr831 pr830 intcb1r fffff1b8h pic84 if84 mk84 0 0 0 pr842 pr841 pr840 intcb1re fffff1bah pic85 if85 mk85 0 0 0 pr852 pr851 pr850 intc30ovf fffff1bch pic86 if86 mk86 0 0 0 pr862 pr861 pr860 intc30 fffff1beh pic87 if87 mk87 0 0 0 pr872 pr871 pr870 intc31ovf fffff1c0h pic88 if88 mk88 0 0 0 pr882 pr881 pr880 intc31 fffff1c2h pic89 if89 mk89 0 0 0 pr892 pr891 pr890 intuc0re fffff1c4h pic90 if90 mk90 0 0 0 pr902 pr901 pr900 intuc0r fffff1c6h pic91 if91 mk91 0 0 0 pr912 pr911 pr910 intuc0t fffff1c8h pic92 if92 mk92 0 0 0 pr922 pr921 pr920 intuc1re fffff1cah pic93 if93 mk93 0 0 0 pr932 pr931 pr930 intuc1r fffff1cch pic94 if94 mk94 0 0 0 pr942 pr941 pr940 intuc1t fffff1ceh pic95 if95 mk95 0 0 0 pr952 pr951 pr950 intad0 fffff1d0h pic96 if96 mk96 0 0 0 pr962 pr961 pr960 intad1 fffff1d2h pic97 if97 mk97 0 0 0 pr972 pr971 pr970 intcc10 fffff1d4h pic98 if98 mk98 0 0 0 pr982 pr981 pr980 intcc11 fffff1d6h pic99 if99 mk99 0 0 0 pr992 pr991 pr990 intcm10 fffff1d8h pic100 if100 mk100 0 0 0 pr1002 pr1001 pr1000 intcm11 fffff1dah pic101 if101 mk101 0 0 0 pr1012 pr1011 pr1010 intovf fffff1dch pic102 if102 mk102 0 0 0 pr1022 pr1021 pr1020 intudf fffff1deh pic103 if103 mk103 0 0 0 pr1032 pr1031 pr1030 intdma2 fffff1e0h pic104 if104 mk104 0 0 0 pr1042 pr1041 pr1040 intdma3 fffff1e2h pic105 if105 mk105 0 0 0 pr1052 pr1051 pr1050 intperr table 7-2: addresses and bits of interrupt control registers (3/3) address register bit associated interrupt 7 6543 2 1 0
228 chapter 7 interrupt/exception processing function user?s manual u16580ee2v0ud00 7.3.5 interrupt mask registers 0 to 6 (imr0 to imr6) the imr0 to imr6 registers set the interrupt mask state for the maskable interrupts. the imk0 to imk104 bits are equivalent to the mkn bit in the corresponding picn register. the imrm register (m = 0 to 6) can be read or written in 16-bit units. if the higher 8 bits of the imrm register are used as the imrmh register and the lower 8 bits as the imrml register, these registers can be read or written in 8-bit or 1-bit units. reset input sets these registers to ffffh. bits 15 to 9 of the imr6 register (bits 7 to 1 of the imr6h register) are fixed to 1. if these bits are not 1, the operation cannot be guaranteed. caution: the device file defines the mkn bit as a reserved word. if a bit is manipulated using the name of mkn, the contents of the picn register, instead of the imrm register, are rewritten (as a result, the contents of the imrm register are also rewritten). figure 7-11: interrupt mask registers 0 to 2 (imr0 to imr2) remark: n = 0 to 105 (see table 7-1 ) after reset: ffffh r/w address: imr0 fffff100h imr0l fffff100h, imr0h fffff101h 15 14 13 12 11 10 9 8 imr0 mk15 mk14 mk13 mk12 mk11 mk10 mk9 mk8 76543210 mk7 mk6 mk5 mk4 mk3 mk2 mk1 mk0 after reset: ffffh r/w address: imr1 fffff102h imr1l fffff102h, imr1h fffff103h 15 14 13 12 11 10 9 8 imr1 mk31 mk30 mk29 mk28 mk27 mk26 mk25 mk24 76543210 mk23 mk22 mk21 mk20 mk19 mk18 mk17 mk16 after reset: ffffh r/w address: imr2 fffff104h imr2l fffff104h, imr2h fffff105h 15 14 13 12 11 10 9 8 imr2 mk47 mk46 mk45 mk44 mk43 mk42 mk41 mk40 76543210 mk39 mk38 mk37 mk36 mk35 mk34 mk33 mk32 imkn interrupt mask flag 0 enable interrupt servicing 1 disable interrupt servicing (pending)
229 chapter 7 interrupt/exception processing function user?s manual u16580ee2v0ud00 figure 7-12: interrupt mask registers 3 to 6 (imr3 to imr6) remark: n = 0 to 105 (see table 7-1 ) after reset: ffffh r/w address: imr3 fffff106h imr3l fffff106h, imr3h fffff107h 15 14 13 12 11 10 9 8 imr3 mk63 mk62 mk61 mk60 mk59 mk58 mk57 mk56 mk55 mk54 mk53 mk52 mk51 mk50 mk49 mk48 after reset: ffffh r/w address: imr4 fffff108h imr4l fffff108h, imr4h fffff109h 15 14 13 12 11 10 9 8 imr4 mk79 mk78 mk77 mk76 mk75 mk74 mk73 mk72 mk71 mk70 mk69 mk68 mk67 mk66 mk65 mk64 after reset: ffffh r/w address: imr5 fffff10ah imr5l fffff10ah, imr5h fffff10bh 15 14 13 12 11 10 9 8 imr5 mk95 mk94 mk93 mk92 mk91 mk90 mk89 mk88 mk87 mk86 mk85 mk84 mk83 mk82 mk81 mk80 after reset: ffffh r/w address: imr6 fffff10ch imr6l fffff10ch, imr6h fffff10dh 15 14 13 12 11 10 9 8 imr6 111111mk105mk104 mk103 mk102 mk101 mk100 mk99 mk98 mk97 mk96 imkn interrupt mask flag 0 enable interrupt servicing 1 disable interrupt servicing (pending)
230 chapter 7 interrupt/exception processing function user?s manual u16580ee2v0ud00 7.3.6 in-service priority register (ispr) the ispr register holds the priority level of the maskable interrupt currently acknowledged. when an interrupt request is acknowledged, the bit of this register corresponding to the priority level of that interrupt request is set to 1 and remain s set while the interrupt is serviced. when the reti instruction is executed, the bit corresponding to the interrupt request having the highest priority is automatically reset to 0 by hardware. howe ver, it is not reset to 0 when execution is returned from non-maskable interrupt servicing or exception processing. reset input clears this register to 00h. this register is read-only, in 8-bit or 1-bit units. caution: in the interrupt enabled (ei) state, if an interrupt is acknowledged during the reading of the ispr register, the value of the ispr register may be read after the bit is set (1) by this interrupt acknowledgment. to read the value of the ispr register properly before interrupt acknowledgment, read it in the interrupt disabled (di) state. figure 7-13: interrupt service priority register (ispr) remark: n = 0 to 7 (priority level) after reset: 00h r address: fffff1fah 76543210 ispr ispr7 ispr6 ispr5 ispr4 ispr3 ispr2 ispr1 ispr0 isprn priority of interrupt currently being acknowledged 0 interrupt request with priority n is not acknowledged 1 interrupt request with priority n is being acknowledged
231 chapter 7 interrupt/exception processing function user?s manual u16580ee2v0ud00 7.3.7 maskable interrupt status flag (id) the id flag is bit 5 of the psw and controls the ma skable interrupt?s operating state, and stores control information regarding enabling or disabling of interrupt requests. figure 7-14: maskable interrupt status flag (id) note: interrupt disable flag (id) function ? this flag is set to 1 by the di instruction and reset to 0 by the ei instruction. its value is also modified by the reti instruction or ldsr instruction when referencing the psw. ? non-maskable interrupt and exceptions are acknowledged regardless of this flag. when a maskable interrupt is acknowledged, the id flag is automatically set to 1 by hardware. ? the interrupt request generated during the acknowledgement disabled period (id = 1) can be acknowledged when the ifn bit of the interrupt control register picn is set to 1, and the id flag is reset to 0. 31 8765 4 3210 after reset 00000020h psw 0 000000 00000000000000000npep id sat cy ov s z id maskable interrupt servicing specification note 0 maskable interrupt request acknowledgment enabled 1 maskable interrupt request acknowledgment disabled (pending)
232 chapter 7 interrupt/exception processing function user?s manual u16580ee2v0ud00 7.3.8 interrupt trigger mode selection the valid edge of the maskable external interrupt input pin (intpn) can be selected by program (n = 0 to 12). the edge that can be selected as the valid edge is one of the following. ? rising edge ? falling edge ? both, the rising and falling edges the edge-detected intpn signal becomes an interrupt source. the valid edge is specified by interrupt mode registers 0 to 3 (intm0 to intm3)
233 chapter 7 interrupt/exception processing function user?s manual u16580ee2v0ud00 (1) interrupt mode register 0 (intm0) the behaviour of the external interrupt input pins intp0 to intp2 can be specified by the interrupt mode register 0 (intm0). the intm0 register can be read/written in 8-bit or 1-bit units. figure 7-15: interrupt mode register 0 (intm0) caution: changing the state of interrupt mode configuration registers esn0/esn1 may trigger an unintended interrupt event for the respective interrupt channels. be sure to mask the respective interrupt channel and clear the interrupt status flag after changing the bits esn0/esn1 of the interrupt channel (n = 0 to 2). after reset: 00h r/w address: fffff880h 76543210 intm0 es21 es20 es11 es10 es01 es00 esn1 esn0 es21 es20 valid edge specification of intp2 pin input 0 0 falling edge 0 1 rising edge 1 0 setting prohibited 1 1 both, rising and falling edges es11 es10 valid edge specification of intp1 pin input 0 0 falling edge 0 1 rising edge 1 0 setting prohibited 1 1 both, rising and falling edges es01 es00 valid edge specification of intp0 pin input 0 0 falling edge 0 1 rising edge 1 0 setting prohibited 1 1 both, rising and falling edges esn1 esn0 valid edge specification of nmi pin input 0 0 falling edge 0 1 rising edge 1 0 setting prohibited 1 1 both, rising and falling edges
234 chapter 7 interrupt/exception processing function user?s manual u16580ee2v0ud00 (2) interrupt mode register 1 (intm1) the behaviour of the external interrupt input pins intp3 to intp6 can be specified by the interrupt mode register 1 (intm1). the intm1 register can be read/written in 8-bit or 1-bit units. figure 7-16: interrupt mode register 1 (intm1) caution: changing the state of interrupt mode configuration registers esn0/esn1 may trigger an unintended interrupt event for the respective interrupt channels. be sure to mask the respective interrupt channel and clear the interrupt status flag after changing the bits esn0/esn1 of the interrupt channel (n = 3 to 6). after reset: 00h r/w address: fffff882h 76543210 intm1 es61 es60 es51 es50 es41 es40 es31 es30 es61 es60 valid edge specification of intp6 pin input 0 0 falling edge 0 1 rising edge 1 0 setting prohibited 1 1 both, rising and falling edges es51 es50 valid edge specification of intp5 pin input 0 0 falling edge 0 1 rising edge 1 0 setting prohibited 1 1 both, rising and falling edges es41 es40 valid edge specification of intp4 pin input 0 0 falling edge 0 1 rising edge 1 0 setting prohibited 1 1 both, rising and falling edges es31 es30 valid edge specification of intp4 pin input 0 0 falling edge 0 1 rising edge 1 0 setting prohibited 1 1 both, rising and falling edges
235 chapter 7 interrupt/exception processing function user?s manual u16580ee2v0ud00 (3) interrupt mode register 2 (intm2) the behaviour of the external interrupt input pins intp7 to intp10 can be specified by the interrupt mode register 2 (intm2). the intm2 register can be read/written in 8-bit or 1-bit units. figure 7-17: interrupt mode register 2 (intm2) caution: changing the state of interrupt mode configuration registers esn0/esn1 may trigger an unintended interrupt event for the respective interrupt channels. be sure to mask the respective interrupt channel and clear the interrupt status flag after changing the bits esn0/esn1 of the interrupt channel (n = 7 to 10). after reset: 00h r/w address: fffff882h 76543210 intm1 es101 es100 es91 es90 es81 es80 es71 es70 es101 es100 valid edge specification of intp10 pin input 0 0 falling edge 0 1 rising edge 1 0 setting prohibited 1 1 both, rising and falling edges es91 es90 valid edge specification of intp9 pin input 0 0 falling edge 0 1 rising edge 1 0 setting prohibited 1 1 both, rising and falling edges es81 es80 valid edge specification of intp8 pin input 0 0 falling edge 0 1 rising edge 1 0 setting prohibited 1 1 both, rising and falling edges es71 es70 valid edge specification of intp7 pin input 0 0 falling edge 0 1 rising edge 1 0 setting prohibited 1 1 both, rising and falling edges
236 chapter 7 interrupt/exception processing function user?s manual u16580ee2v0ud00 (4) interrupt mode register 3 (intm3) the behaviour of the external interrupt input pins intp11 and intp12 can be specified by the interrupt mode register 3 (intm3). the intm3 register can be read/written in 8-bit or 1-bit units. figure 7-18: interrupt mode register 3 (intm3) caution: changing the state of interrupt mode configuration registers esn0/esn1 may trigger an unintended interrupt event for the respective interrupt channels. be sure to mask the respective interrupt channel and clear the interrupt status flag after changing the bits esn0/esn1 of the interrupt channel (n = 11, 12). after reset: 00h r/w address: fffff882h 76543210 intm1 0 0 0 0 es121 es120 es111 es110 es121 es120 valid edge specification of intp12 pin input 0 0 falling edge 0 1 rising edge 1 0 setting prohibited 1 1 both, rising and falling edges es111 es110 valid edge specification of intp11 pin input 0 0 falling edge 0 1 rising edge 1 0 setting prohibited 1 1 both, rising and falling edges
237 chapter 7 interrupt/exception processing function user?s manual u16580ee2v0ud00 7.4 software exception a software exception is generated when the cpu executes the trap instruction, and is always accepted. for details of the instruction function, refer to the v850 family user?s manual architecture. 7.4.1 operation if a software exception occurs, the cpu performs the following processing, and transfers control to the handler routine: <1> saves the current pc to eipc. <2> saves the current psw to eipsw. <3> writes an exception code to the lower 16 bits (eicc) of ecr (interrupt source). <4> sets the ep and id bits of psw. <5> loads the handler address (00000040h or 00000050h) of the software exception routine in the pc, and transfers control. the processing of a software exception is shown below. figure 7-19: software exception processing note: trap instruction format: trap vector (the vector is a value from 0 to 1fh.) the handler address is determined by the trap instruction?s operand (vector). if the vector is 0 to 0fh, it becomes 00000040h, and if the vector is 10h to 1fh, it becomes 00000050h. trap instruction eipc eipsw ecr.eicc psw.ep psw.id pc restored pc psw exception code 1 1 handler address cpu processing exception processing note
238 chapter 7 interrupt/exception processing function user?s manual u16580ee2v0ud00 7.4.2 restore recovery from software exception processing is carried out by the reti instruction. by executing the reti instruction, the cpu carries out the following processing and shifts control to the restored pc?s address. <1> loads the restored pc and psw from ei pc and eipsw because the psw.ep bit is 1. <2> transfers control to the address of the restored pc and psw. the processing of the reti instruction is shown below. figure 7-20: reti instruction processing caution: when the psw.ep bit and the psw.np bit are changed by the ldsr instruction during the software exception process, in order to restore the pc and psw correctly during recovery by the reti instruction, it is necessary to set psw.ep back to 0 using the ldsr instruction immediat ely before the reti instruction. remark: the solid line shows the cpu processing flow. psw.ep reti instruction pc psw eipc eipsw psw.np original processing restored pc psw fepc fepsw 1 1 0 0
239 chapter 7 interrupt/exception processing function user?s manual u16580ee2v0ud00 7.4.3 exception status flag (ep) the ep flag is bit 6 of the psw, and is a status flag used to indicate that exception processing is in progress. this flag is set when an exception occurs. figure 7-21: exception status flag (ep) 31 8765 4 3210 after reset 00000020h psw 0 000000 00000000000000000np ep id sat cy ov s z ep exception processing status 0 exception processing not in progress 1 exception processing in progress
240 chapter 7 interrupt/exception processing function user?s manual u16580ee2v0ud00 7.5 exception trap an exception trap is an interrupt that is requested when the illegal execution of an instruction takes place. in the v850e/ph2, an ille gal opcode trap (ilgop: illegal opcode trap) is considered as an exception trap. 7.5.1 illegal opcode definition the illegal instruction has an opcode (bits 10 to 5) of 11 1111b, a sub-opcode (bits 26 to 23) of 1000b to 1111b, and a sub-opcode (bit 16) of 0b. an exception trap is generated when an instruction applicable to this illegal instruction is executed. figure 7-22: illegal opcode caution: caution since it is possible that this instruction may be assigned to an illegal opcode in the future, it is recommended that it not be used. remark: x: don?t care (1) operation if an exception trap occurs, the cpu performs the following processing, and transfers control to the handler routine. <1> saves the restored pc to dbpc. <2> saves the current psw to dbpsw. <3> sets the psw.np, psw.ep, and psw.id bits. <4> sets the handler address (00000060h) corresponding to the exception trap to the pc, and transfers control. figure 7-23 illustrates the processing of the exception trap. 15 16 23 22 0 1 1 1 1 1 1 27 26 31 0 4 5 10 11 0 1 0 1 0 1 1 1 to
241 chapter 7 interrupt/exception processing function user?s manual u16580ee2v0ud00 figure 7-23: exception trap processing (2) restore recovery from an exception trap is carried out by the dbret instruction. by executing the dbret instruction, the cpu carries out the following processing and controls the address of the restored pc. <1> loads the restored pc an d psw from dbpc and dbpsw. <2> transfers control to the address indicated by the restored pc and psw. figure 7-24 illustrates the restore pr ocessing from an exception trap. figure 7-24: restore processing from exception trap exception trap (ilgop) occurs dbpc dbpsw psw.np psw.ep psw.id pc restored pc psw 1 1 1 00000060h exception processing cpu processing dbret instruction pc psw dbpc dbpsw jump to address of restored pc
242 chapter 7 interrupt/exception processing function user?s manual u16580ee2v0ud00 7.6 periods in which cpu does not acknowledge interrupts the cpu acknowledges an interrupt while an instru ction is being executed. however, no interrupt will be acknowledged between an interrupt request non-sample instruction and the next instruction (interrupt is held pending). the interrupt request non-sample instructions are as follows. ? ei instruction ? di instruction ? ldsr reg2, 0x5 instruction (for psw) ? the store instruction for the command register (prcmd) ? the store, or bit manipulation instructions excluding the tst1 instruction for the following interrupt- related registers: - interrupt control register (picn) - interrupt mask registers 0 to 3 (imr0 to imr3) remark: n = 0 to 105 (see table 7-2, ?addresses and bits of interrupt control registers,? on page 225 )
243 user?s manual u16580ee2v0ud00 chapter 8 clock generator the clock generator (cg) generates and controls the internal system clock (f xx ) that is supplied to each internal unit, such as the cpu. 8.1 features ? multiplier function using a phase locked loop (pll) synthesizer (f xx = 4 f x ) - crystal frequency: f x = 16 mhz - internal system clock: f xx = 64 mhz ? power saving mode: halt mode 8.2 configuration figure 8-1: clock generator remark: f x : external resonator or external clock frequency f xx : internal system clock an external resonator or crystal is connected to x1 and x2 pins, whose frequency is multiplied by the pll synthesizer. by this an internal system clock (f xx ) is generated that is 4 times the frequency (f x ) of the external resonator or crystal. the clock controller enables pll au tomatically and starts clock suppl y to the system after oscillation stabilization time has passed. internal system clock frequency (f xx ) external resonator or crystal frequency (f x ) 64.000 mhz 16.0000 mhz x1 x2 f x f xx cpu on-chip peripheral i/o clock generator (cg)
244 chapter 8 clock generator user?s manual u16580ee2v0ud00 8.3 power save control 8.3.1 overview the power save function of v850e/ph2 supports the halt mode only. in this mode, the clock generator (oscillator and pll synthesizer) continues to operate, but the cpu?s operation clock stops. since the supply of clocks to on-chip peripheral functions other than the cpu continues, operation continues. the power consumption of t he overall system can be r educed by intermittent operation that is achieved due to a combination of halt mode and normal operation mode. the system is switched to halt mode by a specific instruction (t he halt instruction). figure 8-2 shows the operation of the clock generator in normal operation mode and halt mode. figure 8-2: power save mode state transition diagram notes: 1. non-maskable interrupt request signal (nmi) or unmasked maskable interrupt request signal. 2. the oscillation stabilization ti me is necessary after releas e of reset because the pll is initialized by a reset. the stabilizatio n time is determined by default. note 1 normal operation mode halt mode set halt mode wait for stabilization of oscillation and pll reset pin input interrupt request note 2
245 chapter 8 clock generator user?s manual u16580ee2v0ud00 8.3.2 halt mode (1) setting and operation status the halt mode is set when a dedicated instruction (halt) is executed in the normal operation mode. when halt mode is set, clock supply is stoppe d to the cpu only. the clock generator and pll continue operating. clock supply to the ot her on-chip peripheral functions continues. as a result, program execution is stopped, and the internal ram retains the contents before the halt mode was set. the on-chip peripheral functions that are independent of instruction processing by the cpu continue operating. table 18-3 shows the operation status in the halt mode. the average power consumption of the system can be reduced by using the halt mode in combination with the normal operation mode for intermittent operation. cautions: 1. insert five or more nop instructions after the halt instruction. 2. if the halt instruction is executed while an interrupt request is being held pending, the halt mode is set but is released immediately by the pending interrupt request. table 8-1: operation status in halt mode function operation status clock generator operating internal system clock (f xx ) supplied cpu stopped dma operating interrupt contro ller operating ports maintained on-chip peripheral i/o (excluding ports) operating internal data all internal data such as cpu registers, states, data, and the contents of internal ram are retained in the state they were before halt mode was set. a0 to a21 operating d0 to d31 rd wr ben0 to ben3 cs0 , cs1 , cs3 , cs4 bclk, stst, stnxt wait
246 chapter 8 clock generator user?s manual u16580ee2v0ud00 (2) releasing halt mode the halt mode is released by a non-maskable interrupt request signal (nmi), an unmasked maskable interrupt request signal, or reset pin input. after the halt mode has been released, the normal operation mode is restored. (a) releasing halt mode by non-maskable interrupt request signal or unmasked maskable interrupt request signal the halt mode is released by a non-maskable interrupt request signal (intwdt) or an unmasked maskable interrupt request signal, regardless of the priority of the interrupt request. if the halt mode is set in an interrupt servicing routine, however, an interrupt request that is issued later is serviced as follows. ? if an interrupt request signal with a priority lower than or same as the interrupt currently being serviced is generated, the halt mode is released, but the newly generated interrupt request signal is not acknowledged. the interrupt request signal itself is retained. ? if an interrupt request signal with a priority higher than that of the interrupt currently being serviced is issued (including a non-maskable interrupt request signal), the halt mode is released and that interrupt request signal is acknowledged. (b) releasing halt mode by reset pi n input or wdtres signal generation the same operation as the normal reset operation is performed. table 8-2: operation after releasing halt mode by interrupt request signal release source interrupt enabled (ei) status interrupt disabled (di) status non-maskable interrupt request signal execution branches to the handler address unmasked maskable interrupt request signal execution branches to the handler address or the next instruction is executed the next instruction is executed
247 user?s manual u16580ee2v0ud00 chapter 9 16-bit timer/event counter p 9.1 features timer p (tmp) is a 16-bit timer/event counter that can be used in various ways. tmp can perform the following operations. ? pwm output ? interval timer ? external event counter (operation not possible when clock is stopped) ? one-shot pulse output ? pulse width measurement 9.2 function outline ? capture trigger input signal 2 ? external trigger input signal 1 ? clock select 8 ? external event count input 1 ? readable counter 1 ? capture/compare reload register 2 ? capture/compare match interrupt 2 ? timer output (topn0, topn1) 2
248 chapter 9 16-bit timer/event counter p user?s manual u16580ee2v0ud00 9.3 configuration tmp includes the following hardware. note: tipm0 and tipm1 captures inputs are shared with external trigger inputs ttrgpm, and external event inputs tevtpm, and the corresponding topm0 and topm1 outputs. remark: n = 0 to 8 m = n for n= 0 to 7 figure 9-1: block diagram of timer p notes: 1. external pin is not available for tmp8. 2. internal signal inputs (inttt0cc0 and inttt 0cc1 of tmt0, or intcm10 and intcm11 of tmenc1) available on tmp8 only. (ref. to 9.4 (9) tmp input control register 2 (tpic2) ). table 9-1: configuration of tmp0 to tmp8 item configuration timer register 16-bit counter registers tmpn capture/compare registers 0, 1 (tpnccr0, tpnccr1) tmpn counter register (tpncnt) ccr0 buffer register, ccr1 buffer register timer input 2 8 (tipm0, tipm1, ttrgpm, tevtpm) note timer output 2 8 (topm0, topm1) note 1 1 (top81) control registers tmpn control regi sters 0, 1 (tpnctl0, tpnctl1) tmpn i/o control registers 0 to 2 (tpnioc0 to tpnioc2) tmpn option registers 0, 1 (tpnopt0, tpnopt1) f/2 xx f/4 xx f/8 xx f /16 xx f /32 xx f /64 xx f /256 xx f /1024 xx selector internal bus internal bus topn0 topn1 tipn0 tipn1 selector edge detector ccr0 buffer register ccr1 buffer register tpnccr0 tpnccr1 16-bit timer counter tpncnt inttpnov inttpncc0 inttpncc1 output controller clear note 1 note 1 note 1 edge detector tevtpn note 1 ttrgpn note 1 intcm10 note 2 intt0cc0 note 2 intcm11 note 2 intt0cc1 note 2
249 chapter 9 16-bit timer/event counter p user?s manual u16580ee2v0ud00 (1) tmpn capture/compare register 0 (tpnccr0) the tpnccr0 register is a 16-bit register that functions both as a capture register and as a compare register. whether this register functions as a capture register or as a compare register can be controlled with the tpnccs0 bit of the tpnopt0 register, but only in the free-running mode. in the pulse width measurement mode, this register can be used as a dedicated capture register (the compare function cannot be used.) in modes other than the free-running mode and pulse width measurement mode, this register is used as a dedicated compare register. in the initial setting, the tpnccr0 register is a compare register. this register can be read or written in 16-bit units. reset input clears this register to 0000h. figure 9-2: tmpn capture/compare register 0 (tpnccr0) (a) use as compare register tpnccr0 can be rewritten when tpnce = 1 the timing at which the tpnccr0 rewrite values become valid when tpnce = 1 is as follows. (b) use as capture register ?tmp0 to tmp7 the counter value is saved to tpnccr0 upon capture trigger (tipn0) input edge detection. ?tmp8 since tmp8 has no external input pin, the capt ure function can only be used internally for capturing the interrupt signal (inttt0cc0 of tm t0, or intcm10 of tmenc1) specified by the tpic22 bit of tpic2 register (ref. to 9.4 (9) tmp input control register 2 (tpic2) ). after reset: 0000h r/w address: tp0ccr 0 fffff606h, tp1ccr0 fffff616h, tp2ccr0 fffff626h, tp3ccr0 fffff636h, tp4ccr0 fffff646h, tp5ccr0 fffff656h, tp6ccr0 fffff666h, tp7ccr0 fffff676h, tp8ccr0 fffff686h 1514131211109876543210 tpnccr0 (n = 0 to 8) tmp operation mode method of writing tpnccr0 register pwm mode, external trigger pulse output mode reload free-running mode, external event count mode, one-shot pulse output mode, interval timer mode anytime write pulse width measurement mode cannot be used because dedicated capture register
250 chapter 9 16-bit timer/event counter p user?s manual u16580ee2v0ud00 (2) tmpn capture/compare register 1 (tpnccr1) the tpnccr1 register is a 16-bit register that functions both as a capture register and as a compare register. whether this register functions as a capture register or as a compare register can be controlled with the tpnccs1 bit of the tpnopt0 register, but only in the free-running mode. in the pulse width measurement mode, this register can be used as a dedicated capture register (the compare function cannot be used.) in modes other than the free-running mode and pulse width measurement mode, this register is used as a dedicated compare register. in the initial setting, the tpnccr1 register is a reload register. this register can be read or written in 16-bit units. reset input clears this register to 0000h. figure 9-3: tmpn capture/compare register 1 (tpnccr1) (a) use as compare register tpnccr1 can be rewritten when tpnce = 1 the timing at which the tpnccr1 rewrite values become valid when tpnce = 1 is as follows. (b) use as capture register ? tmp0 to tmp7 the counter value is saved to tpnccr1 upon c apture trigger (tipn1) input edge de tection. ?tmp8 since tmp8 has no external input pin, the capture function can only be used internally for capturing the interrupt signal (inttt0cc1 of tmt0, or intcm11 of tmenc1) specified by the tpic22 bit of tpic2 register (ref. to 9.4 (9) tmp input control register 2 (tpic2) ). after reset: 0000h r/w address: tp0 ccr1 fffff608h, tp1ccr1 fffff618h, tp2ccr1 fffff628h, tp3ccr1 fffff638h, tp4ccr1 fffff648h, tp5ccr1 fffff658h, tp6ccr1 fffff668h, tp7ccr1 fffff678h, tp8ccr1 fffff688h 1514131211109876543210 tpnccr1 (n = 0 to 8) tmp operation mode method of writing tpnccr0 register pwm mode, external trigger pulse output mode reload free-running mode, external event count mode, one-shot pulse output mode, interval timer mode anytime write pulse width measurement mode cannot be used because dedicated capture register
251 chapter 9 16-bit timer/event counter p user?s manual u16580ee2v0ud00 (3) tmpn counter register (tpncnt) the tpncnt register is a read buffer register that can read 16-bit counter values. this register is read-only, in 16-bit units. reset input clears this register to 00 00h, as the tpnce bit is cleared to 0. figure 9-4: tmpn counter register (tpncnt) remark: the value of the tpncnt register is cleared to 0000h when the tpnce bit = 0. if the tpncnt register is read at this time, the val ue of the 16-bit counter (ffffh) is not read, but 0000h is read. after reset: 0000h r address: tp0cnt fffff60ah, tp1 cnt fffff61ah, tp2cnt fffff62ah, tp3cnt fffff63ah, tp4cnt fffff64ah, tp5cnt fffff65ah, tp6cnt fffff66ah, tp7cnt fffff67ah, tp8cnt fffff68ah 1514131211109876543210 tpncnt (n = 0 to 8)
252 chapter 9 16-bit timer/event counter p user?s manual u16580ee2v0ud00 9.4 control registers (1) tmpn control register 0 (tpnctl0) the tpnctl0 register is an 8-bit register that controls the operation of timer p. this register can be read or written in 8-bit or 1-bit units. reset input clears this register to 00h. the same value can always be written to the tpnctl0 register by software. figure 9-5: tmpn control register 0 (tpnctl0) caution: set the tpncks2 to tpncks0 bits when tpnce = 0. when the value of the tpnce bit is changed from 0 to 1, the tpncks2 to tpncks0 bits can be set simultaneously. remark: n = 0 to 8 after reset: 00h r/w address: tp0ctl0 fffff600h, tp1ctl0 fffff610h, tp2ctl0 fffff620h, tp3ctl0 fffff630h, tp4ctl0 fffff640h, tp5ctl0 fffff650h, tp6ctl0 fffff660h, tp7ctl0 fffff670h, tp8ctl0 fffff680h 76543210 tpnctl0 tpnce 0 0 0 0 tpncks2 tpncks1 tpncks0 (n = 0 to 8) tpnce timer pn operation control 0 internal operating clock operation disabled (tmpn reset asynchronously) 1 internal operating clock operation enabled ? internal operating clock control and tmpn asynchronous reset are performed with the tpnce bit. when the tpnce bit is cleared to 0, the internal operating clock of tmpn stops (fixed to low level) and tmpn is reset asynchronously. ? when the tpnce bit is set to 1, the intern al operating clock is enabled and count-up operation starts within 2 input clocks after the tpnce bit was set to 1 tpncks2 tpncks1 tpncks0 internal count clock selection 000 f xx /2 001 f xx /4 010 f xx /8 011 f xx /16 100 f xx /32 101 f xx /64 110 f xx /256 111 f xx /1024
253 chapter 9 16-bit timer/event counter p user?s manual u16580ee2v0ud00 (2) tmpn control register 1 (tpnctl1) the tpnctl1 register is an 8-bit register that controls the operation of timer p. this register can be read or written in 8-bit or 1-bit units. reset input clears this register to 00h. figure 9-6: tmpn control register 1 (tpnctl1) (1/2) cautions: 1. always clear the tpnsye bit for the master timers tmp0 and tmp4. 2. always clear the tpnsye bit for tmp8 . do not operate tmp8 in synchronous mode. remark: n = 0 to 8 after reset: 00h r/w address: tp0ctl 1 fffff601h, tp1ctl1 fffff611h, tp2ctl1 fffff621h, tp3ctl1 fffff631h, tp4ctl1 fffff641h, tp5ctl1 fffff651h, tp6ctl1 fffff661h, tp7ctl1 fffff671h, tp8ctl1 fffff681h 76543210 tpnctl1 tpnsye tpnest tpneee 0 0 tpnmd2 tpnmd1 tpnmd0 (n = 0 to 8) tpnsye synchronous mode selection 0 timer pn operates in single operation mode 1 timer pn operates in synchronous operation mode note ? this bit supports synchronous operation of two or more timer p. ? two groups of timers exist, which can be synchronized: tmp0 to tmp3 with tmp0 as master, and tmp4 to tmp7 with tmp4 as master. note: synchronous operation mode is not available for tmp8 (n = 8). tpnest software trigger control 0 no operation 1 in one-shot pulse mode: one-shot pulse software trigger in external trigger pulse output mode: pulse output software trigger ? the tpnest bit functions as a software trigger in the one-shot pulse mode and the external trigger pulse output mode note 1 , if it is set to 1 when tpnce = 1. therefore, be sure to set tpnest to 1 after setting tpnce to 1. ? ttrgpn pin is used as the external trigger input of tmpn. note 2 ? the read value of the tpnest bit is always 0. notes: 1. the trnest bit is invalid even if it is controlled in any other mode. 2. external trigger input pin is not available for tmp8 (n = 8)
254 chapter 9 16-bit timer/event counter p user?s manual u16580ee2v0ud00 figure 9-6: tmpn control register 1 (tpnctl1) (2/2) cautions: 1. rewrite the tpneee and tpnmd2 to tpnmd0 bits only when tpnce = 0. (the same value can be written when tpnce = 1.) the operation is not guaranteed if rewriting is performed when tpnce = 1. if rewriting was mistakenly performed, set tpnce = 0 and then set the bits again. 2. set tp8eee bit of the tr 0ctl1 register always to 0, because tmp8 does not incorporate an external clock input. in case of tp8eee = 1 operation of tmp8 is not guaranteed. remark: n = 0 to 8 tpneee count clock selection 0 use the internal clock (selected by bits tpncks2 to tpncks0) 1 use external clock input (tevtpn input edge) note ? when tpneee = 1 (external clock input tevtpn ), the valid edge is specified by bits tpnees1 and tpnees0. note: external clock input pin is not available for tmp8 (n = 8). tpnmd2 tpnmd1 tpnmd0 timer mode selection 000 interval timer mode note 1, 2 001 external event count mode note 1, 2, 3 010 external trigger pulse output mode note 2, 3 011 one-shot pulse mode note 2 100 pwm mode note 2 1 0 1 free-running mode 110 pulse width measurement mode note 1, 2 1 1 1 setting prohibited notes: 1. setting prohibited for tmp0 and tmp4, when synchronous operation function is enabled (tpnsye = 1). 2. setting prohibited for tmp1 to tmp3, and tmp5 to tmp7, when synchronous operation func tion is enabled (tpnsye = 1). 3. setting prohibited for tmp8.
255 chapter 9 16-bit timer/event counter p user?s manual u16580ee2v0ud00 (3) tmpn i/o control register 0 (tpnioc0) the tpnioc0 register is an 8-bit register that controls the timer output (topn0, topn1). this register can be read or written in 8-bit or 1-bit units. reset input clears this register to 00h. figure 9-7: tmpn i/o control register 0 (tpnioc0) note: topn0 output pin is not available for tmp8. caution: rewrite the tpnol1, tpnoe1, tpnol0, and tpnoe0 bits only when tpnce = 0. (the same value can be written when tpnce = 1.) if rewriting was mistakenly performed, set tpnce = 0 and then set the bits again. remark: n = 0 to 8 after reset: 00h r/w address: tp0ioc 0 fffff602h, tp1ioc0 fffff612h, tp2ioc0 fffff622h, tp3ioc0 fffff632h, tp4ioc0 fffff642h, tp5ioc0 fffff652h, tp6ioc0 fffff662h, tp7ioc0 fffff672h, tp8ioc0 fffff682h 76543210 tpnioc00000tpnol1tpnoe1tpnol0tpnoe0 (n = 0 to 8) tpnol1 timer output level setting (topn1 pin) 0 normal output (low level, when output is inactive.) 1 inverted output (high level, when output is inactive.) tpnoe1 timer output control (topn1 pin) 0 timer output prohibited (topn1 pin output is fixed to inactive level.) 1 timer output enabled (a pulse c an be output from the topn1 pin.) tpnol0 timer output level setting (topn0 pin) note 0 normal output (low level, when output is inactive.) 1 inverted output (high level, when output is inactive.) tpnoe0 timer output control (topn0 pin) note 0 timer output prohibited (topn0 pin output is fixed to inactive level.) 1 timer output enabled (a pulse c an be output from the topn0 pin.)
256 chapter 9 16-bit timer/event counter p user?s manual u16580ee2v0ud00 (4) tmpn i/o control register 1 (tpnioc1) the tpnioc1 register is an 8-bit register that cont rols the valid edge for the external input signals (tipn0, tipn1). this register can be read or written in 8-bit or 1-bit units. reset input clears this register to 00h. figure 9-8: tmpn i/o control register 1 (tpnioc1) note: tipn0 and tipn1 input pins are not available for tmp8. these inputs are only connected internally to capture the interrupt signal s inttt0cc0 and intt0cc1 of tmt0, or intcm10 and intcm11 of tmenc1, specified by the tpic22 bit of tpic2 register (ref. to 9.4 (9) tmp input control register 2 (tpic2) ). cautions: 1. rewrite the tpnis3 to tpnis0 bits only when tpnce = 0. (the same value can be written when tpnce = 1.) if rewriting was mistakenly performed, set tpnce = 0 and then set the bits again. 2. the tpnis3 to tpnis0 bits are valid on ly in the free-running mode and the pulse width measurement mode. in all other modes, a capture operation is not possible. remark: n = 0 to 8 after reset: 00h r/w address: tp0ioc 1 fffff603h, tp1ioc1 fffff613h, tp2ioc1 fffff623h, tp3ioc1 fffff633h, tp4ioc1 fffff643h, tp5ioc1 fffff653h, tp6ioc1 fffff663h, tp7ioc1 fffff673h, tp8ioc1 fffff683h 76543210 tpnioc1 0 0 0 0 tpnis3 tpnis2 tpnis1 tpnis0 (n = 0 to 8) tpnis3 tpnis2 capture input (t ipn1) valid edge setting note 0 0 no edge detection (capture operation invalid) 0 1 rising edge detection 1 0 falling edge detection 1 1 both, rising and falling edge detection tpnis1 tpnis0 capture input (t ipn0) valid edge setting note 0 0 no edge detection (capture operation invalid) 0 1 rising edge detection 1 0 falling edge detection 1 1 both, rising and falling edge detection
257 chapter 9 16-bit timer/event counter p user?s manual u16580ee2v0ud00 (5) tmpn i/o control register 2 (tpnioc2) the tpnioc2 register is an 8-bit register that controls the valid edge of the external event count input signal (tevtpn) and external trigger input signal (ttrgpn). this register can be read or written in 8-bit or 1-bit units. reset input clears this register to 00h. figure 9-9: tmpn i/o control register 2 (tpnioc2) cautions: 1. rewrite the tpnees1, tpnees0, tp nest1, and tpnest0 bits only when tpnce = 0. (the same value can be written when tpnce = 1.) if rewriting was mistakenly performed, set tpnce = 0 and then set the bits again. 2. the tpnees1 and tpnees0 bits are va lid only when tpneee = 1 or when the external event count mode (tpnmd2 to tpnmd0 = 001b of the tpnctl1 register) has been set. remark: n = 0 to 7 after reset: 00h r/w address: tp0ioc 2 fffff604h, tp1ioc2 fffff614h, tp2ioc2 fffff624h, tp3ioc2 fffff634h, tp4ioc2 fffff644h, tp5ioc2 fffff654h, tp6ioc2 fffff664h, tp7ioc2 fffff674h, tp8ioc2 fffff684h 76543210 tpnioc20000tpn ees1 tpnees0 tpnets1 tpnets0 (n = 0 to 7) tp1ees1 tp1ees0 external event counter input (tevtpn) valid edge setting 0 0 no edge detection (capture operation invalid) 0 1 rising edge detection 1 0 falling edge detection 1 1 both, rising and falling edge detection tp1ets1 tp1ets0 external trigger input (ttrgpn) valid edge setting 0 0 no edge detection (capture operation invalid) 0 1 rising edge detection 1 0 falling edge detection 1 1 both, rising and falling edge detection
258 chapter 9 16-bit timer/event counter p user?s manual u16580ee2v0ud00 (6) tmpn option register 0 (tpnopt0) the tpnopt0 register is an 8-bit register used to set the capture/compare operation and detect overflow. this register can be read or written in 8-bit or 1-bit units. reset input clears this register to 00h. figure 9-10: tmpn option register 0 (tpnopt0) caution: rewrite the tpnccs1 and tpnccs0 bits only when tpnce = 0. (the same value can be written when tpnce = 1.) if rewriting was mistakenly performed, set tpnce = 0 and then set the bits again. remark: n = 0 to 8 after reset: 00h r/w address: tp0opt0 fffff605h, tp1opt0 fffff615h, tp2opt0 fffff625h, tp3opt0 fffff635h, tp4opt0 fffff645h, tp5opt0 fffff655h, tp6opt0 fffff665h, tp7opt0 fffff675h, tp8opt0 fffff685h 76543210 tpnopt0 0 0 tpnccs1 tpnccs0 0 0 0 tpnovf (n = 0 to 8) tpnccs1 tpnccr1 register capture/compare selection 0 compare register selection 1 capture register selection the tpnccs1 bit settings are valid only in the free-running mode. tpnccs0 tpnccr0 register capture/compare selection 0 compare register selection 1 capture register selection the tpnccs0 bit settings are valid only in the free-running mode. tpnovf timer p overflow detection flag 0 no overflow occurrence after timer restart or flag reset 1 overflow occurrence ? the tpnovf flag is set when the 16-bit count er value overflows from ffffh to 0000h in the free-running mode or the pulse measurement mode. ? an interrupt request signal (inttpnov) is generated at the same time that the tpnovf flag is set (1). the inttpnov signa l is not generated in modes other than the free-running mode or the pulse measurement mode. ? the tpnovf flag is not cleared even when the tpnovf flag and the tpnopt0 register are read. ? the tpnovf flag can be both read and written, but only reset (0) is accepted. writing 1 has no influence on the operation of timer p.
259 chapter 9 16-bit timer/event counter p user?s manual u16580ee2v0ud00 (7) tmp input control register 0 (tpic0) the tpic0 register is an 8-bit register that controls the external input pin source of the capture register 1 of tmp0 to tmp3. this register can be read or written in 8-bit units. reset input clears this register to 00h. figure 9-11: tmpn input control register 0 (tpic0) after reset: 00h r/ w address: fffff6f0h 76543210 tpic00000tpic03tpic02tpic01tpic00 tpic03 tp3ccr1 register capt ure source input selection 0 capture source input is pin p17/tip31 1 capture source input is pin p16/tip30 tpic02 tp2ccr1 register capt ure source input selection 0 capture source input is pin p15/tip21 1 capture source input is pin p14/tip20 tpic01 tp1ccr1 register capt ure source input selection 0 capture source input is pin p13/tip11 1 capture source input is pin p12/tip10 tpic00 tp0ccr1 register capt ure source input selection 0 capture source input is pin p11/tip01 1 capture source input is pin p10/tip00
260 chapter 9 16-bit timer/event counter p user?s manual u16580ee2v0ud00 (8) tmp input control register 1 (tpic1) the tpic1 register is an 8-bit register that controls the external input pin source of the capture register 1 of tmp4 to tmp7, as well as the internal time trigger source from the fcan controllers of both capture registers 0 and 1 of tmp7. this register can be read or written in 8-bit units. reset input clears this register to 00h. figure 9-12: tmp input control register 1 (tpic1) after reset: 00h r/w address: fffff6f2h 76543210 tpic1 0 0 tip15 tip14 tpic13 tpic12 tpic11 tpic10 tpic15 tipc14 tipc13 capture source input selection of tp7ccr0 tp7ccr1 0 0 0 pin p26/tip70 pin p27/tip71 0 0 1 pin p26/tip70 0 1 0 fcan0 time trigger pin p27/tip71 0 1 1 pin p26/tip70 1 0 0 pin p26/tip70 fcan1 time trigger 101 110fcan0 time trigger 111 tpic12 tp6ccr1 register capture source input selection 0 capture source input is pin p25/tip61 1 capture source input is pin p24/tip60 tpic11 tp5ccr1 register capture source input selection 0 capture source input is pin p23/tip51 1 capture source input is pin p22/tip50 tpic10 tp4ccr1 register capture source input selection 0 capture source input is pin p21/tip41 1 capture source input is pin p20/tip40
261 chapter 9 16-bit timer/event counter p user?s manual u16580ee2v0ud00 (9) tmp input control register 2 (tpic2) the tpic2 register is an 8-bit register that controls the external input pin source of the capture register 1 of tmt0 and tmt1, as well as the internal source of both capture registers 0 and 1 of tmp8. this register can be read or written in 8-bit units. reset input clears this register to 00h. figure 9-13: tmp input control register 1 (tpic1) after reset: 00h r/ w address: fffff6f4h 76543210 tpic200000tpic22tpic21tpic20 tipc22 capture source input selection of tp8ccr0 tp8ccr1 0 inttt0cc0 signal of tmt0 inttt1cc1 signal of tmt0 1 intcm10 signal of tmenc1 intcm11 signal of tmenc1 tpic21 tt1ccr1 register capture source input selection 0 capture source input is pin p74/tit11 1 capture source input is pin p73/tit10 tpic20 tt0ccr1 register capture source input selection 0 capture source input is pin p71/tit01 1 capture source input is pin p70/tit00
262 chapter 9 16-bit timer/event counter p user?s manual u16580ee2v0ud00 9.5 operation timer p can perform the following operations. notes: 1. to use the external event count function, specify that the edge of the capture input tipn1 or tipn0 respectively, shared with event input tevtpn is not detected (by clearing the tpsn3, tpsn2 bits or tpnis1, tpnis0 bits of t he tpnioc1 register respectively to ?00b?) (n = 0 to 7). 2. when using the external trigger pulse output mode, one-shot pulse mode, and pulse width measurement mode, select a count clock (b y clearing the tpneee bit of the tpnctl1 register to 0). remark: n = 0 to 7 9.5.1 anytime rewrite and reload tpnccr0 and tpnccr1 register rewrite is possible for timer p during timer operation (tpnce = 1), but the write method (anytime rewrite, reload) differs depending on the mode. (1) anytime rewrite when the tpnccrm register is written during timer operation, the write data is transferred at that time to the ccrm buffer register and used as the 16-bit counter comparison value. remark: n = 0 to 8 m = 0, 1 operation tpnest (software trigger bit) ttrgpn0 (external trigger input) capture/compare mode compare register rewriting method interval timer mode invalid invalid compare only anytime rewrite external event count mode note 1 invalid invalid compare only anytime rewrite external trigger pulse output mode note 2 valid valid compare only reload one-shot pulse output mode note 2 valid valid compare only anytime rewrite pwm mode invalid invalid compare only reload free-running mode invalid invalid capture/compare selectable anytime rewrite pulse width measurement mode note 2 invalid invalid capture only not applicable
263 chapter 9 16-bit timer/event counter p user?s manual u16580ee2v0ud00 figure 9-14: basic operation flow for anytime write remarks: 1. the above flowchart illustrates an example of the operation in the interval timer mode. 2. n = 0 to 8 start initial settings inttpncc0 output tpnccr1 rewrite transfer to ccr1 buffer register tpnccr0 rewrite transfer to ccr0 buffer register match between ccr0 buffer register and 16-bit counter 16-bit counter clear & start timer operation enable (tpnce = 1) transfer of tpnccr0, tpnccr1 values to ccr0 buffer register and ccr1 buffer register ? ?
264 chapter 9 16-bit timer/event counter p user?s manual u16580ee2v0ud00 figure 9-15: timing diagram for anytime write remarks: 1. d 01 , d 02 : setting values of tpnccr0 register (0000h to ffffh) d 11 , d 12 : setting values of tpnccr1 register (0000h to ffffh) 2. the above timing chart illustrates an example of the operation in the interval timer mode. 3. n = 0 to 8 16-bit counter tpnccr0 tpnccr1 inttpncc0 inttpncc1 ccr0 buffer register ccr1 buffer register d 01 d 01 d 01 d 01 0000h tpnce = 1 d 02 d 02 d 11 d 11 d 11 d 12 d 12 d 12 d 02 d 11 0000h d 12
265 chapter 9 16-bit timer/event counter p user?s manual u16580ee2v0ud00 (2) reload method (batch rewrite) when the tpnccr0 and tpnccr1 registers are written during timer operation via the ccrm buffer register, the write data is used as the 16-bit counter comparison value. the tpnccr0 register and the tpnccr1 register can be rewritten when tpnce = 1. in order for the setting value when the tpnccr0 register and the tpnccr1 register are rewritten to become the 16-bit counter comparison value (in other words, in order for this value to be reloaded to the ccrm buffer register), it is necessary to rewrite tpnccr0 and then write to the tpnccr1 register before the 16-bit counter va lue and the tpnccr0 register value match. thereafter, the values of the tpnccr0 and the tpnccr1 register are reloaded upon tpnccr0 register match. whether to enable or disable the next reload timing is controlled by writing to the tpnccr1 register. thus even when wishing only to rewrite the value of the tpnccr0 register, also write the same value to the tpnccr1 register. figure 9-16: basic operation flow for reload (batch rewrite) caution: writing to the tpnccr1 register includes enabling of reload. thus, rewrite the tpnccr1 register after rewriting the tpnccr0 register. remarks: 1. the above flowchart illustrates an exampl e of the operation in the pwm mode. 2. n = 0 to 8 m = 0, 1 ? ? ? start initial settings reload enable inttpncc0 output tpnccr1 rewrite tpnccr0 rewrite match between tpnccr0 and 16-bit counter 16-bit counter clear & start reload of tpnccrm values to ccrm buffer register timer operation enable (tpnce = 1) transfer of tpnccrm values to ccrm buffer register
266 chapter 9 16-bit timer/event counter p user?s manual u16580ee2v0ud00 figure 9-17: timing chart for reload note: reload is not performed because the tpnccr1 register was not rewritten. remarks: 1. d 01 , d 02 , d 03 : setting value of tpnccr0 register (0000h to ffffh) d 11 , d 12 : setting value of tpnccr1 register (0000h to ffffh) 2. the above timing chart illustrates the oper ation in the pwm mode as an example. 3. n = 0 to 8 d 01 d 01 d 02 d 03 0000h d 01 d 11 d 12 d 12 d 02 d 03 0000h d 11 d 12 d 12 tpnce = 1 note d 02 d 02 d 03 d 11 d 12 d 12 d 12 d 12 16-bit counter tpnccr0 tpnccr1 inttpncc0 inttpncc1 ccr0 buffer register ccr1 buffer register note same value write
267 chapter 9 16-bit timer/event counter p user?s manual u16580ee2v0ud00 9.5.2 interval timer mode (tpnmd2 to tpnmd0 = 000b) in the interval timer mode, an interrupt request signal (inttpncc0) is output upon a match between the setting value of the tpnccr0 register and the value of the 16-bit counter, and the 16-bit counter is cleared. the tpnccr0 regist er can be rewritten when tpnce = 1, and when a value is set to the tpnccr0 register with a write instru ction from the cpu, it is transf erred to the ccr0 buffer register through anytime write, and is used as the value for comparison with the 16-bit counter value. in the interval timer mode, the 16-bit counter is cleared only upon a match between the value of the 16- bit counter and the value of the ccr0 buffer register. 16-bit counter clearing using the tpnccr1 register is not performed. however, the setting value of the tpnccr1 register is transferred to the ccr1 buffer register and comp ared with the value of the 16-bit counter, and an interrupt request (inttpncc1) is output if these values match. moreover, topnm pin output is also possible by setting the tpnoem bit to 1. when the tpnccr1 register is not used, it is recommended to set ffffh as the setting value for the tpnccr1 register. remark: n = 0 to 8 m = 0, 1 figure 9-18: flowchart of basic operation in interval timer mode note: the 16-bit counter is not cleared upon a match between the 16-bit counter and tpnccr1. remark: n = 0 to 8 ? ? ? start initial settings clock selection (tpnctl0: tpncks2 to tpncks0) interval timer mode setting (tpnctl0: tpnmd2 to tpnmd0 = 000) compare register setting (tpnccr0, tpnccr1) timer operation enable (tpnce = 1) transfer of tpnccr0, tpnccr1 values to ccr0 buffer register and ccr1 buffer register match between 16-bit counter and ccr1 buffer register note match between 16-bit counter and ccr0 buffer register, 16-bit counter clear & start inttpncc1 output inttpncc0 output
268 chapter 9 16-bit timer/event counter p user?s manual u16580ee2v0ud00 figure 9-19: basic operation timing in interval timer mode (1/2) (a) d 1 > d 2 > d 3 ; rewrite of tpnccr0 register only; no topn0, topn1 output remarks: 1. d 1 , d 2 : setting values of tpnccr0 register (0000h to ffffh) d 3 : setting value of tpnccr1 register (0000h to ffffh) 2. interval time = (dn + 1) (count clock cycle) 3. n = 0 to 8 16-bit counter inttpncc0 d 1 d 2 d 1 ffffh d 3 d 3 d 3 inttpncc1 tpnccr0 d 1 tpnce = 1 tpnccr1 d 2 0000h d 2 d 1 d 3 d 3 0000h ccr0 buffer register ccr1 buffer register
269 chapter 9 16-bit timer/event counter p user?s manual u16580ee2v0ud00 figure 9-19: basic operation timing in interval timer mode (2/2) (b) d 1 = d 2 ; no tpnccr0, tpnccr1 rewrite; topn1 output remarks: 1. d 1 : setting value of tpnccr0 register (0000h to ffffh) d 2 : setting value of tpnccr1 register (0000h to ffffh) 2. interval time = (dn + 1) (count clock cycle) 3. n = 0 to 8 16-bit counter d 1 inttpncc0 d 1 = d 2 ffffh tpnccr1 inttpncc1 tpnccr0 d 2 tpnce = 1 topn0/topn1 d 1 = d 2 d 1 = d 2 d 1 0000h ccr0 buffer register ccr1 buffer register d 2 0000h
270 chapter 9 16-bit timer/event counter p user?s manual u16580ee2v0ud00 9.5.3 external event count mode (tpnmd2 to tpnmd0 = 001b) in the external event count mode, external event count input (tevtpn pin input) is used as a count-up signal. when the external event count mode is set, count-up is performed using external event count input (tevtpn pin input) , regardless of the sett ing of the tpneee bit of the tpnctl0 register. in the external event count mode, a match interrupt request (inttpncc0) is output upon a match between the setting value of the tpnccr0 register and the value of the 16-bit counter, and the 16-bit counter is cleared. when a value is set to the tpnccr0 register with a write instruction from the cpu, it is transferred to the ccr0 buffer register through anytime write, and is used as the value for comparison with the 16-bit counter value. in the external event count mode, the 16-bit counter is cleared only upon a match between the value of the 16-bit counter and the value of the ccr0 buffer register. 16-bit counter clearing using the tpnccr1 register is not performed. however, the setting value of the tpnccr1 register is transferred to the ccr1 buffer register and compared with the value of the 16-bit counter, and an interrupt request (inttpncc1) is output if these values match. moreover, topnm pin output is also possible by setting the tpnoem bit to 1. the tpnccr0 register can be rewritten when tpnce = 1. when the tpnccr1 register is not used, it is recommended to set ffffh as the sett ing value for the tpnccr1 register. cautions: 1. in external event count mode, when the setting value of the trnccr0 register is set to m, the number of tevtpn pin input edge detection times is m+1. 2. in external event count mode, do not set tpnccr0 register to 0000h. remark: n = 0 to 7 m = 0, 1
271 chapter 9 16-bit timer/event counter p user?s manual u16580ee2v0ud00 figure 9-20: flowchart of basic operation in external event count mode notes: 1. selection of the tpn eee bit has no influence. 2. the 16-bit counter is not cleared upon a match between the 16-bit counter and the ccr1 buffer register. remark: n = 0 to 7 start initial settings external event count mode setting (tpnctl0: tpnmd2 to tpnmd0 = 001) note 1 valid edge setting (tpnioc2: tpnees1, tpnees0) compare register setting (tpnccr0, tpnccr1) inttpncc1 output inttpncc0 output timer operation enable (tpnce = 1) transfer of tpnccr0, tpnccr1 values to ccr0 buffer register and ccr1 buffer register match between 16-bit counter and ccr1 buffer register note 2 match between 16-bit counter and ccr0 buffer register, 16-bit counter clear & start ? ? ?
272 chapter 9 16-bit timer/event counter p user?s manual u16580ee2v0ud00 figure 9-21: basic operation timing in external event count mode (1/2) (a) d1 > d2 > d3; rewrite of tpnccr0 only; no topn0, topn1 output remarks: 1. d 1 , d 2 : setting values of tpnccr0 register (0000h to ffffh) d 3 : setting value of tpnccr1 register (0000h to ffffh) 2. event count = (dn + 1) 3. n = 0 to 7 16-bit counter inttpncc0 d 1 d 2 d 1 ffffh d 3 d 3 d 3 inttpncc1 tpnccr0 d 1 tpnce = 1 tpnccr1 d 2 0000h d 2 d 1 d 3 d 3 0000h ccr0 buffer register ccr1 buffer register
273 chapter 9 16-bit timer/event counter p user?s manual u16580ee2v0ud00 figure 9-21: basic operation timing in external event count mode (1/2) (b) d1 = d2; no tpnccr0, tpnccr1 rewrite; topn0, topn1 output remarks: 1. d1: setting value of tpnccr0 register (0000h to ffffh) d2: setting value of tpnccr1 register (0000h to ffffh) 2. event count = (dn + 1) 3. n = 0 to 7 16-bit counter d 1 inttpncc0 d 1 = d 2 ffffh tpnccr1 inttpncc1 tpnccr0 d 2 tpnce = 1 topn0/topn1 d 1 = d 2 d 1 = d 2 d 1 0000h ccr0 buffer register ccr1 buffer register d 2 0000h
274 chapter 9 16-bit timer/event counter p user?s manual u16580ee2v0ud00 9.5.4 external trigger pulse output mode (tpnmd2 to tpnmd0 = 010b) in the external trigger pulse output mode, setting tpnce = 1 causes external trigger input (ttrgpn pin input) wait with the 16-bit counter stopped at ffffh. the count-up operation starts upon detection of the external trigger input (ttrgpn pin input) edge. regarding topn1 output control, the reload register (tpnccr1) is used as the duty setting register and the compare register (tpnccr0) is used as the cycle setting register. the tpnccr0 register and the tpnccr1 register can be rewritten when tpnce = 1. in order for the setting value wh en the tpnccr0 register and the tpnccr1 register are rewritten to become the 16-bit counter comparison value (in other words, in order for this value to be reloaded to the ccrm buffer register), it is necessary to rewr ite tpnccr0 and then write to the tpnccr1 register before the 16-bit counter value and the tpnccr0 register value match. thereafter, the values of the tpnccr0 and the tpnccr1 register are re loaded upon a tpnccr0 register match. whether to enable or disable the next reload timing is controlled by writing to the tpnccr1 register. thus even when wishing only to rewrite the value of the tpnccr0 register, also write the same value to the tpnccr1 register. reload is disabled even when only the tpnccr0 regist er is rewritten. to stop timer p, set tpnce = 0. if the external trigger (ttrgpn pin input) edge is detected several times in the external trigger pulse mode, the 16-bit counter is cleared at the edge detection timing and count-up starts. to realize the same function (software trigger pulse mode) as external trigger pulse mode using a software trigger instead of external trigger input (ttrgpn pin input), set the tpnest bit of the tpnctl1 register to 1 so that the software trigger is output. the external trigger pulse waveform is output from topn1. the topn0 pin performs toggle output upon a match between the tpnccr0 register and the 16-bit counter. since the tpnccr0 register and the tpnccr1 register have their function fixed to that of a compare register in the external trigger pulse mode, they cannot be used for capture operation in this mode. caution: in the external trigger pulse output m ode, select the internal clock (tpneee bit of tpnctl1 register = 0) for the count clock. remarks: 1. for the reload operation wh en tpnccr0 and tpnccr1 ar e rewritten during timer operation, refer to 9.5.6 pwm mode (tpnmd2 to tpnmd0 = 100b) . 2. n = 0 to 7 m = 0, 1
275 chapter 9 16-bit timer/event counter p user?s manual u16580ee2v0ud00 figure 9-22: flowchart of basic operation in external trigger pulse output mode note: the 16-bit counter is not cleared upon a match between the 16-bit counter and the ccr1 buffer register. remark: n = 0 to 7 start initial settings clock selection (tpnctl1: tpneee = 0) (tpnctl0: tpncks2 to tpncks0) external trigger pulse output mode setting (tpnctl1: tpnmd2 to tpnmd0 = 010) compare register setting (tpnccr0, tpnccr1) match between 16-bit counter and tpnccr1 note inttpncc1 output inttpncc0 output external trigger (tipn0 pin) input 16-bit counter start match between 16-bit counter and tpnccr0, 16-bit counter clear & start 16-bit counter clear & start external trigger (tipn0 pin) input timer operation enable (tpnce = 1) transfer of tpnccr0, tpnccr1 values to ccr0 buffer register and ccr1 buffer register ? ? ?
276 chapter 9 16-bit timer/event counter p user?s manual u16580ee2v0ud00 figure 9-23: basic operation timing in external trigger pulse output mode remarks: 1. d01, d02: setting value of tpnccr0 register (0000h to ffffh) d11, d12: setting value of tpnccr1 register (0000h to ffffh) 2. topn1 output duty = (setting value of tpnccr1 register) / (setting value of tp0ccr0 register) topn1 output cycle = (setting value of tpnccr0 register) (count clock cycle) 3. n = 0 to 7 tpnce = 1 d 11 d 11 d 12 d 11 d 12 d 11 d 12 d 02 d 12 d 02 d 01 d 01 d 01 d 02 d 02 ffffh 16-bit counter external trigger (tipn0 pin) tpnccr0 tpnccr1 topn0 topn1 ccr0 buffer register ccr1 buffer register 0000h 0000h
277 chapter 9 16-bit timer/event counter p user?s manual u16580ee2v0ud00 9.5.5 one-shot pulse mode (tpnmd2 to tpnmd0 = 011b) in the one-shot pulse mode, setting tpnce = 1 causes waiting on tpnest bit setting (1) or ttrgpn pin edge detection trigger note 1 with the 16-bit counter held at ffffh. the 16-bit counter starts counting up upon trigger input, and upon a match between the value of the 16-bit counter and the value of the ccr1 buffer register transferred from the tpncr1 register, topn1 becomes high level; upon a match between the value of the 16-bit counter and the value of the ccr0 register transferred from the tpnccr0 register, topn1 becomes low level and th e 16-bit counter is clea red to 0000h and stops. any trigger input past the first one during 16-bit counter operation is ignored. be sure to input the second and subsequent triggers when the 16-bit counter has stopped at 0000h. in the one-shot pulse mode, the tpnccr0 and tpnccr1 r egisters can be rewritten when tpnce = 1. the setting values rewritten to the tpnccr0 and tpnccr1 register s become valid following execution of a write instruction from the cpu, at which time they are transferred to the ccr0 buffer register and the ccr0 buffer register through anytime write, and become the values for comparison with the 16-bit counter value. the one-shot pulse waveform is output from the topn1 pin. the topn0 pin performs toggle output upon a match be tween the 16-bit counter and the tpnccr0 register note 2 . since the tpnccr0 and tpnccr1 registers have their function fixed to that of a compare register in the one-shot pulse mode, they cannot be used for capture operation in this mode. notes: 1. external trigger input pin (ttrgpn) is not available for tmp8 (n = 8). 2. output pin (topn0) is not available for tmp8 (n = 8). caution: in the one-shot pulse mode, select the internal clock (tpneee bit of tpnctl1 register = 0) for the count clock. remark: n = 0 to 8
278 chapter 9 16-bit timer/event counter p user?s manual u16580ee2v0ud00 figure 9-24: flowchart of basic operation in one-shot pulse mode notes: 1. external trigger input (ttrgpn) is not available for tmp8 (n = 8). 2. the 16-bit counter is not cl eared upon a match between th e 16-bit count er and the ccr1 buffer register. caution: the 16-bit counter is not cleared and trigger input is ignored even if trigger input is performed during the count-up operation of the 16-bit counter. remark: n = 0 to 8 start initial settings ? clock selection (tpnctl1: tpneee = 0) (tpnctl0: tpncks2 to tpncks0) ? one-shot pulse mode setting (tpnctl1: tpnmd2 to tpnmd0 = 011b) ? compare register setting (tpnccr0, tpnccr1) match between 16-bit counter and ccr1 buffer register note 2 inttpncc1 output inttpncc0 output external trigger (tevtpn pin) input note 1 , or tpnest = 1 16-bit counter start match between 16-bit counter and ccr0 buffer register, 16-bit counter clear trigger wait status, 16-bit counter in standby at ffffh trigger wait status, 16-bit counter in standby at 0000h timer operation enable (tpnce = 1) transfer of tpnccr0, tpnccr1 values to ccr0 buffer register and ccr1 buffer register
279 chapter 9 16-bit timer/event counter p user?s manual u16580ee2v0ud00 figure 9-25: timing of basic operation in one-shot pulse mode notes: 1. the 16-bit counter starts counting up when either tpnest = 1 is set or tevtpn is input. 2. external trigger input pin (ttrgpn) is not available for tmp8 (n = 8). 3. output pin (topn0) is not available for tmp8 (n = 8). remarks: 1. d0: setting value of tpnccr0 register (0000h to ffffh) d1: setting value of tpnccr1 register (0000h to ffffh) 2. delay time of one-shot pulse output (topn1) when external pin edge detection trigger is used: (tpnccr1 value + 1) (selected count clock) + 2/(f xx ) + (ttrgpn input filter delay) 3. n = 0 to 8 tpnce = 1 tpnest = 1 d 1 d 0 d 1 d 0 d 1 d 0 d 0 d 0 d 1 d 1 ffffh 16-bit counter external trigger (ttrgpn) tpnccr0 inttpncc0 tpnccr1 inttpncc1 topn1 topn0 ccr0 buffer register ccr1 buffer register 0000h 0000h note 1 note 2 note 3
280 chapter 9 16-bit timer/event counter p user?s manual u16580ee2v0ud00 9.5.6 pwm mode (tpnmd2 to tpnmd0 = 100b) in the pwm mode, tmpn capture/compare register 1 (tpnccr1) is used as the duty setting register and tmpn capture/compare register 0 (tpncc r0) is used as the cycle setting register. variable duty pwm is output by setting these two registers and operating the timer. the tpnccr0 register and the tpnccr1 register can be rewritten when tpnce = 1. in order for the setting value wh en the tpnccr0 register and the tpnccr1 register are rewritten to become the 16-bit counter comparison value (in other words, in order for this value to be reloaded to ccr0 buffer register or ccr1 buffer register), it is necessary to re write tpnccr0 and then write to the tpnccr1 register before the 16-bit counter value and the tpnccr0 register value match. thereafter, the values of the tpnccr0 register and the tpn ccr1 register are reloaded upon a tpnccr0 register match. whether to enable or disable the next reload timing is controlled by writing to the tpnccr1 register. thus even when wishing only to rewrite the value of the tpnccr0 register, also write the same value to the tpnccr1 register. reload is disabled even when only the tpnccr0 register is rewritten. to stop timer p, set tpnce = 0. pwm waveform output is performed from the topn1 pin. the topn0 pin note performs toggle output upon a match between the 16-bit counter and the tpnccr0 register. since the tpnccr0 and tpnccr1 registers have their fu nction fixed that of a compare register in the pwm mode, they cannot be used for capture operation in this mode. note: topn0 output pin is not available for tmp8 (n = 8). remark: n = 0 to 8
281 chapter 9 16-bit timer/event counter p user?s manual u16580ee2v0ud00 figure 9-26: flowchart of basic operation in pwm mode (1/2) (a) values of tpnccr0, tpnccr1 register s not rewritten during timer operation remark: n = 0 to 8 m = 0, 1 start initial settings ? clock selection (tpnctl0: tpncks2 to tpncks0) ? pwm mode settings (tpnctl1: tpnmd2 to tpnmd0 = 100b) ? compare register setting (tpnccr0, tpnccr1) match between 16-bit counter and ccr1 buffer register, topn1 low-level output match between 16-bit counter and ccr0 buffer register, 16-bit counter clear & start topn1 high-level output inttpncc1 output inttpncc0 output timer operation enable (tpnce = 1) transfer of tpnccrm register values to ccrm buffer register
282 chapter 9 16-bit timer/event counter p user?s manual u16580ee2v0ud00 figure 9-26: flowchart of basic operation in pwm mode (2/2) (b) values of tpnccr0, tpnccr1 registers rewritten during timer operation note: the timing of <2> in the above flowchart may differ depending on the rewrite timing of steps <1> and <3> and the value of tpnccr1, but make sure that step <3> comes after step <1>. remark: n = 0 to 8 m = 0, 1 start initial settings ? clock selection (tpnctl0: tpncks2 to tpncks0) ? pwm mode setting (tpnctl1: tpnmd2 to tpnmd0 = 100b) ? compare register setting (tpnccr0, tpnccr1) match between 16-bit counter and tpnccr1, topn1 low-level output match between 16-bit counter and tpnccr0, 16-bit counter clear & start, topn1 high-level output inttpncc1 output inttpncc0 output reload enable inttpncc0 output tpnccr1 rewrite tpnccr0 rewrite ? match between ccr0 buffer register and 16-bit counter ? 16-bit counter clear & start ? values of tpnccrm reloaded to ccrm buffer register note <1> <2> <3> inttpncc1 output timer operation enable (tpnce = 1) transfer of tpnccrm register values to ccrm buffer register match between 16-bit counter and ccr1 buffer register, topn1 low-level output
283 chapter 9 16-bit timer/event counter p user?s manual u16580ee2v0ud00 figure 9-27: basic operation timing in pwm mode (1/2) (a) tpnccr1 value rewritten note: topn0 output pin is not available for tmp8 (n = 8). remarks: 1. d 00 : setting value of tpnccr0 register (0000h to ffffh) d 10 , d 11 , d 12 , d 13 : setting values of tpnccr1 register (0000h to ffffh) 2. topn1 output duty factor = (setting value of tpnccr1 register) / (setting value of tp0ccr0 register + 1) topn1 output cycle = (setting value of tpnccr0 register + 1) (count clock cycle) topn0 output toggle width = (setting value of tpnccr0 register + 1) (count clock cycle) 3. n = 0 to 8 tpnce = 1 16-bit counter tpnccr0 tpnccr1 topn1 topn0 ccr0 buffer register ccr1 buffer register 0000h 0000h d 10 d 11 d 12 d 13 d 00 d 00 d 00 d 00 d 00 d 00 d 10 d 10 d 10 d 11 d 11 d 12 d 12 d 13 ffffh note
284 chapter 9 16-bit timer/event counter p user?s manual u16580ee2v0ud00 figure 9-27: basic operation timing in pwm mode (2/2) (b) tpnccr0, tpnccr1 values rewritten notes: 1. reload is not performed because the tpnccr1 register was not rewritten. 2. topn0 output pin is not available for tmp8 (n = 8). remarks: 1. d 00 , d 01 , d 02 , d 03 : setting values of tpnccr0 register (0000h to ffffh) d 10 , d 11 , d 12 , d 13 : setting values of tpnccr1 register (0000h to ffffh) 2. topn1 output duty factor = (setting value of tpnccr1 register) / (setting value of tp0ccr0 register + 1) topn1 output cycle = (setting value of tpnccr0 register + 1) (count clock cycle) topn0 output toggle width = (setting value of tpnccr0 register + 1) (count clock cycle) 3. n = 0 to 8 tpnce = 1 16-bit counter tpnccr0 tpnccr1 topn1 topn0 0000h 0000h d 10 d 11 d 12 d 12 d 00 d 00 d 10 d 10 d 11 d 11 d 11 d 12 d 12 d 12 d 00 d 01 d 02 d 03 d 01 d 01 d 01 d 02 d 02 d 03 ffffh same value write note note ccr0 buffer register ccr1 buffer register note 2
285 chapter 9 16-bit timer/event counter p user?s manual u16580ee2v0ud00 9.5.7 free-running mode (tpnmd2 to tpnmd0 = 101b) in the free-running mode, both the interval function and the compare function can be realized by operating the 16-bit counter as a free-running counter and selecting capture/compare operation with the tpnccs1 and tpnccs0 bits. the settings of the tpnccs1 and tpnccs0 bits of the tpnopt0 register are valid only in the free-running mode. (a) using tpnccr1 register as compare register an interrupt is output upon a match between the 16-bit counter and the ccr1 buffer register in the free-running mode (interval function). rewrite during compare timer operation is enabled and performed with anytime write. (once the compare value has been written, synchronization with the internal clock is done and this value is used as the 16-bit counter comparison value.) when timer output (topn1) has been enabled, topn1 performs toggle output upon a match between the 16-bit counter and the ccr1 buffer register. (b) using tpnccr1 register as capture register the value of the 16-bit counter is saved to the tpnccr1 register upon tipn1 pin note 1 edge detection. (c) using tpnccr0 register as compare register an interrupt is output upon a match between the 16-bit counter and the ccr0 buffer register in the free-running mode (interval function). rewrite during compare timer operation is enabled and performed with anytime rewrite. when timer output (topn0) has been enabled, topn0 note 2 performs toggle output upon a match between the 16-bit counter and the ccr0 buffer register. (d) using tpnccr0 register as capture register the value of the 16-bit counter is saved to the tpnccr0 register upon tipn0 pin note 1 edge detection. notes: 1. since tmp8 has no external input pin, the capture function can only be used internally for capturing the interrupt signal inttt0cc0 of tmt0, or intcm10 of tmenc1, into the tp8ccr0 register, or the interrupt signal inttt0cc1 of tmt0, or intcm11 of tmenc1 into the tp8ccr1 register respectively, which is specified by the tpic22 bit of tpic2 register (refer to 9.4 (9) tmp input control register 2 (tpic2) ). 2. topn0 output pin is not available for tmp8 (n = 8). tpnccs1 operation 0 use tpnccr1 register as compare register 1 use tpnccr1 register as capture register tpnccs0 operation 0 use tpnccr0 register as compare register 1 use tpnccr0 register as capture register
286 chapter 9 16-bit timer/event counter p user?s manual u16580ee2v0ud00 figure 9-28: flowchart of basic op eration in free-running mode remark: n = 0 to 8 start initial settings ? clock selection (tpnctl0: tpncks2 to tpncks0) ? free-running mode setting (tpnctl1: tpnmd2 to tpnmd0 = 101b) tpnccs1, tpnccs0 setting timer operation enable (tpnce = 1) transfer of tpnccr0 and tpnccr1 values to ccr0 buffer register ccr0 and ccr1 buffer registers respectively match between ccr1 buffer register and 16-bit counter match between ccr0 buffer register and 16-bit counter 16-bit counter overflow timer operation enable (tpnce = 1) transfer of tpnccr1 value to ccr1 buffer register tipn1 edge detection, capture of 16-bit counter value to tpnccr1 tipn0 edge detection, capture of 16-bit counter value to tpnccr0 16-bit counter overflow timer operation enable (tpnce = 1) tipn0 edge detection, capture of 16-bit counter value to tpnccr0 16-bit counter overflow match between ccr1 buffer register and 16-bit counter timer operation enable (tpnce = 1) transfer of tpnccr0 value to ccr0 buffer register 16-bit counter overflow tipn1 edge detection, capture of 16-bit counter value to tpnccr1 match between ccr0 buffer register and 16-bit counter tpnccs1 = 0 tpnccs0 = 0 tpnccs1 = 1 tpnccs0 = 0 tpnccs1 = 0 tpnccs0 = 1 tpnccs1 = 1 tpnccs0 = 1 tipn0 edge detection setting (tpnis1, tpnis0) tipn1 edge detection setting (tpnis3, tpnis2) tipn1, tipn0 edge detection setting (tpnis3 to tpnis0)
287 chapter 9 16-bit timer/event counter p user?s manual u16580ee2v0ud00 (1) tpnccs1 = 0, tpnccs0 = 0 settings (interval function description) when tpnce = 1 is set, the 16-bit counter counts from 0000h to ffffh and the free-running count-up operation continues until tpnce = 0 is set. in this mode, when a value is written to the tpnccr0 and tpnccr1 registers, they are transf erred to the ccr0 buffer register and the ccr1 buffer register (anytime write). in this mode, no one-shot pulse is output even when an one-shot pulse trigger is input. moreover, when tpnoem = 1 is set, topnm performs toggle output upon a match between the 16-bit counter and the ccrm buffer register. figure 9-29: basic operation timing in free-running mode (tpnccs1 = 0, tpnccs0 = 0) note: topn0 output pin is not available for tmp8 (n = 8). remarks: 1. d 00 , d 01 : setting values of tpnccr0 register (0000h to ffffh) d 10 , d 11 : setting values of tpnccr1 register (0000h to ffffh) 2. topnm output rises to the high level when counting is started. 3. n = 0 to 8 m = 0, 1 tpnce = 1 0000h 0000h d 10 d 11 d 10 d 11 d 10 d 00 d 00 d 11 d 11 d 01 d 00 d 00 d 01 d 01 ffffh 16-bit counter tpnccr0 topn0 topn1 inttpncc0 match interupt inttpncc1 match interupt tpnccr1 ccr0 buffer register ccr1 buffer register note
288 chapter 9 16-bit timer/event counter p user?s manual u16580ee2v0ud00 (2) tpnccs1 = 1, tpnccs0 = 1 settings (capture function description) when tpnce = 1, the 16-bit counter counts from 0000h to ffffh and free-running count-up operation continues until tpnce = 0 is set. during this time, values are captured by capture trigger operation and are written to the tpnccr0 and tpnccr1 registers. regarding capture in the vicinity of overflow (ffffh), judgment is made using the overflow flag (tpnovf). however, if overflow occurs twice (2 or more free-running cycles), the capture trigger interval cannot be judged with the tpnovf flag. in this case, the system should be revised. figure 9-30: basic operation timing in free-r unning mode (tpnccs1 = 1, tpnccs0 = 1) remarks: 1. d 00 , d 01 : values captured to tpnccr0 register (0000h to ffffh) d 10 , d 11 : values captured to tpnccr1 register (0000h to ffffh) 2. tipn0: set to rising edge detection (tpnis1, tpnis0 = 01b) tipn1: set to falling edge detec tion (tpnis3, tpnis2 = 10b) 3. n = 0 to 7 d 11 d 10 0000h d 12 16-bit counter ffffh tipn1 tipn0 tpnce = 1 tpnccr1 d 00 d 01 d 12 d 02 d 11 d 10 d 00 d 01 tpnccr0 d 02 d 03 0000h d 03
289 chapter 9 16-bit timer/event counter p user?s manual u16580ee2v0ud00 (3) tpnccs1 = 1, tpnccs0 = 0 settings when tpnce = 1 is set, the counter counts from 0000h to ffffh and free-running count-up operation continues until tpnce = 0 is set. the tpnccr0 register is used as a compare register. an interrupt signal is output upon a match between the value of the 16-bit counter and the setting value transferred to the ccr0 buffer register from the tpnccr0 register as an interval function. even if tpnoe1 = 1 is set to realize the capture function, the tpnccr1 register cannot control topn1. figure 9-31: basic operation timing in free-running mode (tpnccs1 = 1, tpnccs0 = 0) remarks: 1. d00, d01: setting values of tpnccr0 register (0000h to ffffh) d10, d11, d12, d13, d14, d15: values captured to tpnccr1 register (0000h to ffffh) 2. tipn1: set to detection of both rising and fa lling edges (tpnis3, tpnis2 = 11b) 3. n = 0 to 7 d 11 d 10 0000h d 13 d 15 d 14 d 12 16-bit counter ffffh tipn1 tpnccr0 tpnce = 1 tpnccr1 d 00 d 00 d 01 d 10 inttpncc0 match interrupt d 00 d 01 d 11 d 13 d 12 d 14 d 15 d 00 d 01 0000h ccr0 buffer register
290 chapter 9 16-bit timer/event counter p user?s manual u16580ee2v0ud00 (4) tpnccs1 = 0, tpnccs0 = 1 settings when tpnce is set to 1, the 16-bit counter counts from 0000h to ffffh and free-running count-up operation continues until tpnce = 0 is set. the tpnccr1 register is used as a compare register. an interrupt signal is output upon a match between the value of the 16-bit counter and the setting value of the tpnccr1 register as an interval function. when tpnoe1 = 1 is set, topn1 performs toggle output upon mach between the value of the 16-bit counter and the setting value of the tpnccr1 register. figure 9-32: basic operation timing in free-r unning mode (tpnccs1 = 0, tpnccs0 = 1) remarks: 1. d 00 , d 01 , d 02 , d 03 : values captured to tpnccr0 register (0000h to ffffh) d 10 , d 11 , d 12 : setting value of tpnccr1 register (0000h to ffffh) 2. tipn0: set to falling edge detec tion (tpnis1, tpnis0 = 10b) 3. n = 0 to 7 (5) overflow flag when the counter overflows from ffffh to 0000h in the free-running mode, the overflow flag (tpnovf) is set to 1 and an overflow interrupt (inttpnov) is output. be sure to confirm that the overflow flag (tpnovf) is set to ?1? when the overflow interrupt (inttpnov) has occurred. the overflow flag is cleared by writing 0 from the cpu. tpnce = 1 0000h d 10 d 11 d 12 0000h d 00 d 01 d 02 d 03 d 10 d 10 d 11 d 12 d 11 d 01 d 03 d 00 d 11 d 12 ffffh 16-bit counter tipn0 inttpncc1 tpnccr1 tpnccr0 inttpncc0 capture interrupt ccr1 buffer register d 02
291 chapter 9 16-bit timer/event counter p user?s manual u16580ee2v0ud00 9.5.8 pulse width measurement mode (tpnmd2 to tpnmd0 = 110b) in the pulse width measurement mode, free-running count is performed. the value of the 16-bit counter is saved to capture register 0 (tpnccr0), or capture register 1 (tpnccr1) respectively, and the 16-bit counter is cleared upon edge detection of the tipn0 pin, or tipn1 respectively. the external input pulse width can be measured as a result. however, when measuring a large pulse width that exceeds 16-bit counter overflow, perform judgment with the overflow flag. since measurement of pulses for which overflow occurs twice or more is not possible, adjust the operating frequency of the 16-bit counter. depending on the selected capture input sources and specified edge detection three different measurement methods can be applied. <1> pulse period measurement <2> alternating pulse width and pulse space measurement: this requires a fast interrupt handling, in order to measure pulse width and pulse space correctly. <3> simultaneous pulse width and pulse space measurement: both capture inputs are required to measur e pulse width and pulse space simultaneously. the measurements methods are explained in the following sub-chapters. cautions: 1. in the pu lse width measurement mode, sele ct the internal clock (tpneee of tpnctl1 register = 0). 2. pulse width measurement cannot be performed by timer p8 (tmp8). remark: n = 0 to 7
292 chapter 9 16-bit timer/event counter p user?s manual u16580ee2v0ud00 (1) pulse period measurement the pulse period of a signal can be measured in the pulse width measurement mode, when the edge detection of one of the inputs tipn0 and tipn1 is set either to ?rising edge? or ?falling edge?. the detection of the other input should be set to ?no edge detection?. by detection of the specified edge the resulting value is captured in the corresponding capture register (tpnccr0 or tpnccr1), and the timer is cleared and restarts counting. figure 9-33: flowchart of pulse period measurement note: external pulse input is possible for both tipn0 and tipn1, but only one should be selected for the pulse period measurement. specify either ?rising edge? or ?falling edge? for edge detection. specify th e edge of the external input pulse that is not used as ?no edge detection?. remark: n = 0 to 7 m = 0, 1 start initial settings ? clock selection (tpnctl0: tpncks2 to tpncks0) ? pulse width measurement mode setting (tpnctl1: tpnmd2 to tpnmd0 = 110b) ? capture register setting (tpnccr0, tpnccr1) timer operation enable (tpnce = 1) specified edge input to tipnm (rising or falling edge), capture of value to tpnccrm, 16-bit counter clear & start tipn1/tipn0 edge detection setting note (tpnis3 to tpnis0)
293 chapter 9 16-bit timer/event counter p user?s manual u16580ee2v0ud00 figure 9-34: basic operation timing of pulse period measurement remarks: 1. d 00 , d 01 , d 02 : values captured to tpnccr0 register (0000h to ffffh) 2. tipn0: set to detection of rising edge (tpnis1, tpnis0 = 01b) 3. tipn1: set to no edge detection (tpnis3, tpnis2 = 00b) 4. n = 0 to 7 d 00 d 00 d 01 d 01 d 02 d 02 ffffh 0000h 16-bit counter tipn0 tpnccr0 inttpnccr0 inttpnov tpnovf ffffh tpnce = 1 cleared by writing 0 from cpu
294 chapter 9 16-bit timer/event counter p user?s manual u16580ee2v0ud00 (2) alternating pulse width and pulse space measurement the pulse period of a signal can be measured in the pulse width measurement mode alternating in one capture register, when the edge detection of one of the inputs tipn0 and tipn1 is set to ?both rising and falling edges?. the detection of the other input should be set to ?no edge detection?. by detection of a falling or rising edge the resulting value is captured in the corresponding capture register (tpnccr0 or tpnccr1), and the timer is cleared and restarts counting. figure 9-35: flowchart of alternating pulse width and pulse space measurement note: external pulse input is possible for both tipn0 and tipn1, but only one should be selected for the alternating pulse width and pulse space measurement. specify ?both rising and the falling edges? for ed ge detection. specify th e edge of the external input pulse that is not used as ?no edge detection?. remark: n = 0 to 7 m = 0, 1 start initial settings ? clock selection (tpnctl0: tpncks2 to tpncks0) ? pulse width measurement mode setting (tpnctl1: tpnmd2 to tpnmd0 = 110b) ? capture register setting (tpnccr0, tpnccr1) timer operation enable (tpnce = 1) rising edge input to tipnm, capture of value to tpnccrm, 16-bit counter clear & start tipn1/tipn0 edge detection setting note (tpnis3 to tpnis0) falling edge input to tipnm, capture of value to tpnccrm, 16-bit counter clear & start
295 chapter 9 16-bit timer/event counter p user?s manual u16580ee2v0ud00 figure 9-36: basic operation timi ng of alternating pulse width and pulse space measurement remarks: 1. d 00 , d 01 , d 02 , d 03 , d 04 : values captured to tpnccr0 register (0000h to ffffh) 2. tipn0: set to detection of both rising and fa lling edges (tpnis1, tpnis0 = 11b) 3. tipn1: set to no edge detection (tpnis3, tpnis2 = 00b) 4. n = 0 to 7 d 00 d 00 d 01 d 01 d 02 d 02 ffffh 0000h 16-bit counter tipn0 tpnccr0 inttpnccr0 inttpnov tpnovf ffffh tpnce = 1 d 03 d 03 d 04 d 04 cleared by writing 0 from cpu
296 chapter 9 16-bit timer/event counter p user?s manual u16580ee2v0ud00 (3) simultaneous pulse width and pulse space measurement pulse width and pulse space can be measure si multaneously in the pulse width measurement mode, when the signal is input to both inputs tipn0 and tipn1, where both inputs detect opposite edges. alternatively the signal can be input to tipn0 only, when the capture source input selection for capture register 1 is used (ref. to 9.4 (7) tmp input control register 0 (tpic0) and 9.4 (8) tmp input control register 1 (tpic1) ). by detection of the specified edge the resulting values of pulse width or pulse space are captured in the corresponding capture registers (tpnccr0, tp nccr1), and the timer is cleared and restarts counting. figure 9-37: flowchart of simultaneous pulse width and pulse space measurement note: external pulse input must be input to both tipn0 and tipn1, or to tipn0 only, if the internal connection between both inputs is selected. specify ?rising edge? for edge de tection of first input, and ?fa lling edge? for the second input, or vice versa. remark: n = 0 to 7 x = 0, 1 y = 0 when x = 1; y = 1 when x = 0 start initial settings ? clock selection (tpnctl0: tpncks2 to tpncks0) ? pulse width measurement mode setting (tpnctl1: tpnmd2 to tpnmd0 = 110b) ? capture register setting (tpnccr0, tpnccr1) timer operation enable (tpnce = 1) rising edge input to tipnx, capture of value to tpnccrx, 16-bit counter clear & start tipn1/tipn0 edge detection setting note (tpnis3 to tpnis0) falling edge input to tipny, capture of value to tpnccry, 16-bit counter clear & start
297 chapter 9 16-bit timer/event counter p user?s manual u16580ee2v0ud00 figure 9-38: basic operation timing of simultaneous pulse width and pulse space measurement note: the signal to measure has to be assigned to both inputs, tipn0 and tipn1. this can be done either by external pin connection, or internally when selecting tipn1 input on tipn0 pin. in case of internal connection the signal has to be input on tipn0 pin. remarks: 1. d 00 , d 01 , d 02 : values captured to tpnccr0 register (0000h to ffffh) 2. d 10 , d 11 : values captured to tpnccr1 register (000 0h to ffffh) 3. tipn0: set detection to rising edge (tpnis1, tpnis0 = 01b) 4. tipn1: set detection to falling edge (tpnis3, tpnis2 = 10b) 5. n = 0 to 7 d 00 d 10 d 01 ffffh 16-bit counter tipn0, tipn1 note ffffh tpnce = 1 d 11 d 02 d 00 d 01 d 02 0000h tpnccr0 d 10 d 11 0000h tpnccr1 inttpnccr0 inttpnccr1 inttpnov tpnovf cleared by writing 0 from cpu
298 chapter 9 16-bit timer/event counter p user?s manual u16580ee2v0ud00 9.5.9 counter synchronous operation function timer p supports a function to start several timers p simultaneously. for this purpose two timer groups are defined, tmp0 to tmp3, as well as tmp4 to tmp7. for each timer group the counting of one to three slave counters (tmp1 to tmp3, or tmp5 to tmp7) can be synchronized with the corresponding master counter (tmp0 or tmp4). the synchronous operation function is enabled for each incorporated timer by the tpnsye bit in the tpnctl1 register (ref. to 9.4 (2) tmpn control register 1 (tpnctl1) ). when enabling the synchronous operation function, observe the following procedure: <1> clear the synchronous mode selection bit tpmsye of the master counter tmpm to 0. <2> disable the count operation of the master counter tmpm (tpmce = 0). <3> enable the synchronous operation for each of the incorporated slave counters tmps (tpssye = 1). <4> enable the operation of the master counter tmpm (tpmce = 1). master and incorporated slave counters of that group start and clock synchronously. when the master counter is cleared, the slave counters are cleared synchronously too. cautions: 1. in synchronous operation mode, the master counter can be used only in pwm mode (tpmmd2 to tpmmd0 = 100b), external trigger pulse output mode (tpmmd2 to tpmmd0 = 010b), one-shot pulse output mode (tpmmd2 to tpmmd0 = 011b), and free-running mode (tpmmd2 to tpmmd0 = 101b). 2. in synchronous operation mode, the slave counters can be used in free-running mode only (tpsmd2 to tpsmd0 = 101b). remark: n = 0 to 7, m = 0, 4 s = 1 to 3, 5 to 7
299 user?s manual u16580ee2v0ud00 chapter 10 16-bit inverter timer/counter r 10.1 features timer r is a 16-bit timer/counter that provides various motor control functions. ? count clock resolution: 31.25 ns min. (when using 32 mhz count clock) ? general-purpose timer and operation mode supporting various motor control methods ? compare registers with reload buffers ? 10-bit dead time counter - dead time value independently settable through normal phase inverted phase normal phase ? a/d conversion trigger signal generation - generation of a/d conversion trigger with 2 compare registers, trnccr4 and trnccr5 - dedicated output pin (torn7) set with the trnadtrg0 signal and reset with the trnadtrg1 signal ? interrupt thinning out function - thinning out rates of 1/1 to 1/32 ? forced output stop function: eso - high-impedance output of pins torn0 to torn7 possible during eson input ? compare value setting - reload (batch rewrite)/anytime rewrite mode selectable note ? reload mode - reload enabled by writing to trnccr1 register la st, multiple registers si multaneity maintained - peak/valley/peak and valley reload, transfer possible at reload timing note - provision of reload request flag trnrsf - dma transferable register address placement ? high-accuracy t-pwm mode - 0 to 100% duty pwm output possible, including dead time reduction - increased output resolution without software load, because presence/absence of added pulse to pwm output on up-count side can be controlled with lsb of compare register ? 8 selectable count clocks: /2, /4, /8, /16, / 32, /64, /256, /1024 ? active level of output pins torn0 to torn7 settable for each pin ? fail-safe function (error interrupt output possible) - simultaneous active output detection function in normal phase/inverted phase note: high-accuracy t-pwm mode
300 chapter 10 16-bit inverter timer/counter r user?s manual u16580ee2v0ud00 10.2 configuration timer r is configured of the following hardware. note: alternate-function pins remark: n = 0, 1 table 10-1: timer r configuration item configuration counters 16-bit counter 1 16-bit sub-counter 1 10-bit dead time counter 3 registers timer rn counter read register (trncnt) timer rn sub-counter read register (trnsbc) timer rn dead time setting registers 0, 1 (trndtc0, trndtc1) timer rn capture/compare registers 0 to 3 (trnccr0-trnccr3) timer rn compare registers 4, 5 (trnccr4, trnccr5) trnccr0 to trnccr5 buffer registers trndtc0, trndtc1 buffer registers timer input pins 3 (tir10 to tir13, ttrgr1, tevtr1, eson) note timer output pins 8 (torn0 to torn7) note timer input signal - timer output signal trnadtrg0, trnadtrg1 control registers timer rn control registers 0, 1 (trnctl0, trnctl1) timer rn i/o control registers 0 to 4 (trnioc0 to trnioc4) timer rn option registers 0 to 3, 6, 7 (trnopt0 to trnopt3, trnopt6, trnopt7) interrupt requests compare match interrupts (inttrncc0 to inttrncc5) peak interrupt (inttrncd) valley interrupt (inttrnod) overflow interrupt (inttrnov) error interrupt (inttrner)
301 chapter 10 16-bit inverter timer/counter r user?s manual u16580ee2v0ud00 figure 10-1: timer rn block diagram note: timer inputs are only available in tmr1 (n = 1). the tir10 to tir13 capture inputs are shared with tor11 to tor14. external trigger input ttrgr1 is shared with tir10 output, and external event input tevtr1 is shared with tir17 output. remarks: 1. n = 0, 1 2. f xx : internal system clock 16-bit tmrn sub-counter ccr4 buffer ccr5 buffer trnsbc trncnt trncuf trncuf trnadtrg0 torn0 tir10 ttrgr1 tevtr1 tir11 tir12 tir13 torn1 torn2 torn3 torn4 torn5 torn6 torn7 trnadtrg1 inttrno v inttrnod inttrncd inttrncc0 inttrncc1 inttrncc2 inttrncc3 inttrncc4 inttrncc5 load trnsuf trnsuf counter control counter control e d g e d e t e c t o r /2 /1024 /256 /64 /32 /16 /8 /4 output control adtrg control internal bus internal bus 16-bit tmrn counter trndtc1 trndtc0 ccr3 buffer ccr0- trndtc1 ccr0 buffer ccr1 buffer ccr2 buffer trnccr0 trnccr4 trnccr1 trnccr5 trnccr2 trnccr3 & dead time control inttrner note note note note note f xx f xx f xx f xx f xx f xx f xx f xx note
302 chapter 10 16-bit inverter timer/counter r user?s manual u16580ee2v0ud00 (1) tmrn capture/compare register 0 (trnccr0) the trnccr0 register is a 16 -bit register provided with a capture function and a compare function. in the case of the free-running mode only, bit trnccs0 of the trnopt0 register is used to select use of the register as a capture register or as a compare register. in the pulse width measurement mode, this register can be used as a capture-only register. (the register cannot be used as a compare register.) in modes other than the free-running mode and the pulse width measurement mode, the register is used as a compare-only register. this register can be read and written in 16-bit units. reset input clears this register to 0000h. remarks: 1. in the high-accuracy t-pwm mode, writing to bit 0 of the trnccr0 register is ignored. moreover, bit 0 is read as 0. 2. n = 0, 1 figure 10-2: tmrn capture/compare register 0 (trnccr0) (a) use as compare register when trnce = 1, the trnccr0 register write access method is as follows. remarks: 1. for details about the compare register rewrite operation, refer to 10.4.2 compare register rewrite operation . 2. n = 0, 1 caution: to set the carrier frequency in the high-accuracy t-pwm mode, set the trnccr0 reg- ister as follows. number of count clocks of carrier frequency + trndtc0 register value + trndtc1 register value. for details about the carrier wave and dead time settings, refer to 10.10.9 (4) counter operation in high-accuracy t-pwm mode. (b) use as capture register the counter value is saved to the tr1ccr0 register upon detection of the edge of the capture trigger (tir10) input. remark: the capture function is provided only for tmr1. after reset: 0000h r/w address: tr0ccr0 fffff598h, tr1ccr0 fffff5d8h 1514131211109876543210 trnccr0 timer rn operation mode trnccr0 register write access mode pwm mode, external trigger pulse output mode, triangular wave pwm mode, pwm mode with dead time reload free-running mode, external event count mode, one-shot pulse mode, interval timer mode anytime rewrite high-accuracy t-pwm mode reload/anytime rewrite switchable
303 chapter 10 16-bit inverter timer/counter r user?s manual u16580ee2v0ud00 (2) tmrn capture/compare register 1 (trnccr1) the trnccr1 register is a 16-bit register that fu nctions both as a capture register and a compare register. when a compare register is rewritten in the reload mode, the reload request flag (trnrsf) becomes 1 when write access is performed to the trnccr1 register, and all the registers are rewritten at the same time at the next reload timing. in the free-running mode only, the trnccs1 bit of the trnopt0 register is used to select whether to use the trnccr1 register as a capture register or as a compare register. in the pulse width measurement mode, the trnccr1 register can be used as a dedicated capture register. (the register cannot be used as a compare register.) in modes other than the free-running mode and the pulse width measurement mode, all trnccr1 registers function as dedicated compare registers. this register can be read and written in 16-bit units. reset input clears this register to 0000h. remarks: 1. in the high-accuracy t-pwm mode, when bit 0 is set to 1, the additional pulse control function is engaged. (for details about the additional pulse control function, refer to 10.10.9 (6) additional pulse control in high-accuracy t-pwm mode .) 2. n = 0, 1 figure 10-3: tmrn ca pture/compare register 1 (trnccr1) (a) use as compare register when trnce = 1, the trnccr1 register write access method is as follows. remarks: 1. for details about the compare register rewrite operation, refer to 10.4.2 compare register rewrite operation . 2. n = 0, 1 (b) use as capture register the counter value is saved to the tr1ccr1 register upon detection of the edge of the capture trigger (tir11) input. remark: the capture function is provided only for tmr1. after reset: 0000h r/w address: tr0ccr1 fffff59eh, tr1ccr1 fffff5deh 1514131211109876543210 trnccr1 timer rn operation mode trnccr1 register write access mode pwm mode, external trigger pulse output mode, triangular wave pwm mode, pwm mode with dead time reload free-running mode, external event count mode, one-shot pulse mode, interval timer mode anytime rewrite high-accuracy t-pwm mode reload/anytime rewrite switchable
304 chapter 10 16-bit inverter timer/counter r user?s manual u16580ee2v0ud00 (3) tmrn capture/compare register 2 (trnccr2) the trnccr2 register is a 16-bit register that functions both as a capture register and compare register. in the free-running mode only, bit trnccs2 of the trnopt0 register is used to select whether to use the trnccr2 register as a capture register or a compare register. in the pulse width measurement mode, the trnccr2 register can be used as a dedicated capture register. (the register cannot be used as a compare register.) in modes other than the free-running mode and the pulse width measurement mode, all trnccr2 registers function as dedicated compare registers. this register can be read and written in 16-bit units. reset input clears this register to 0000h. remarks: 1. in the high-accuracy t-pwm mode, when bit 0 is set to ?1?, the additional pulse control function is engaged. (for details about th e additional pulse control function, refer to 10.10.9 (6) additional pulse control in high-accuracy t-pwm mode .) 2. n = 0, 1 figure 10-4: tmrn capture/compare register 2 (trnccr2) (a) use as compare register when trnce = 1, the trnccr2 register write access method is as follows. remarks: 1. for details about the compare register rewrite operation, refer to 10.4.2 compare register rewrite operation . 2. n = 0, 1 (b) use as capture register the counter value is saved to the trnccr2 register upon detection of the edge of the capture trigger (tir12) input. remark: the capture function is provided only for tmr1. after reset: 0000h r/w address: tr0ccr2 fffff59ch, tr1ccr2 fffff5dch 1514131211109876543210 trnccr2 timer rn operation mode trnccr2 register write access mode pwm mode, external trigger pulse output mode, triangular wave pwm mode, pwm mode with dead time reload free-running mode, external event count mode, one-shot pulse mode, interval timer mode anytime rewrite high-accuracy t-pwm mode reload /anytime rewrite switchable
305 chapter 10 16-bit inverter timer/counter r user?s manual u16580ee2v0ud00 (4) tmrn capture/compare register 3 (trnccr3) the trnccr3 register is a 16-bit register that fu nctions both as a capture register and a compare register. in the free-running mode only, bit trnccs3 of the trnopt0 register is used to select whether to use the trnccr3 register as a capture register or a compare register. in the pulse width measurement mode, the trnccr3 register can be used as a dedicated capture register. (the register cannot be used as a compare register.) in modes other than the free-running mode and the pulse width measurement mode, all trnccr3 registers function as dedicated compare registers. this register can be read and written in 16-bit units. reset input clears this register to 0000h. remarks: 1. in the high-accuracy t-pwm mode, when bit 0 is set to ?1?, the additional pulse control function is engaged. (for details about the additional pulse control function, refer to 10.10.9 (6) additional pulse control in high-accuracy t-pwm mode .) 2. n = 0, 1 figure 10-5: tmrn ca pture/compare register 3 (trnccr3) (a) use as compare register when trnce = 1, the trnccr3 register write access method is as follows. remarks: 1. for details about the compare register rewrite operation, refer to 10.4.2 compare register rewrite operation . 2. n = 0, 1 (b) use as capture register the counter value is saved to the tr1ccr3 register upon detection of the edge of the capture trigger (tir13) input. remark: the capture function is provided only for tmr1. after reset: 0000h r/w address: tr0ccr3 fffff59ah, tr1ccr3 fffff5dah 1514131211109876543210 trnccr3 timer rn operation mode trnccr3 register write access mode pwm mode, external trigger pulse output mode, triangular wave pwm mode, pwm mode with dead time reload free-running mode, external event count mode, one-shot pulse mode, interval timer mode anytime rewrite high-accuracy t-pwm mode reload/anytime rewrite switchable
306 chapter 10 16-bit inverter timer/counter r user?s manual u16580ee2v0ud00 (5) tmrn compare register 4 (trnccr4) the trnccr4 register is a 16 -bit register that functi ons as a compare function. in the high-accuracy t-pwm mode and the pwm mode with dead time, the interrupt for matches between the counter and the trnccr4 register can be selected as the timing for a/d conversion trigger input. this register can be read and written in 16-bit units. reset input clears this register to 0000h. remarks: 1. in the high-accuracy t-pwm mode, bit 0 of the trnccr4 register is ignored. 2. n = 0, 1 figure 10-6: tmrn compare register 4 (trnccr4) when trnce = 1, the trnccr4 register write access method is as follows. remarks: 1. for details about the compare register rewrite operation, refer to 10.4.2 compare register rewrite operation . 2. n = 0, 1 after reset: 0000h r/w address: tr0ccr4 fffff592h, tr1ccr4 fffff5d2h 1514131211109876543210 trnccr4 timer rn operation mode trnccr4 register write access mode pwm mode, external trigger pulse output mode, triangular wave pwm mode, pwm mode with dead time reload free-running mode, external event count mode, one-shot pulse mode, interval timer mode anytime rewrite high-accuracy t-pwm mode reload/anytime rewrite switchable
307 chapter 10 16-bit inverter timer/counter r user?s manual u16580ee2v0ud00 (6) tmrn compare register 5 (trnccr5) the trnccr5 register is a 16-bit compare register. in the high-accuracy t-pwm mode and the pwm mode with dead time, the interrupt for matches between the counter and the trnccr5 register can be selected as the timing for a/d conversion trigger input. this register can be read and written in 16-bit units. reset input clears this register to 0000h. remarks: 1. in the high-accuracy t-pwm mode, bit 0 of the trnccr5 register is ignored 2. n = 0, 1 figure 10-7: tmrn compare register 5 (trnccr5) when trnce = 1, the trnccr5 register write access method is as follows. remarks: 1. for details about the compare register rewrite operation, refer to 10.4.2 compare register rewrite operation . 2. n = 0, 1 after reset: 0000h r/w address: tr0ccr3 fffff590h, tr1ccr3 fffff5d0h 1514131211109876543210 trnccr5 timer rn operation mode trnccr5 register write access mode pwm mode, external trigger pulse output mode, triangular wave pwm mode, pwm mode with dead time reload free-running mode, external event count mode, one-shot pulse mode, interval timer mode anytime rewrite high-accuracy t-pwm mode reload/anytime rewrite switchable
308 chapter 10 16-bit inverter timer/counter r user?s manual u16580ee2v0ud00 (7) tmrn counter read register (trncnt) the trncnt register is a timer read register that can read the values of the 16-bit counter. this register can only be read in 16-bit units. reset input or setting trnce = 0 clears this register to 0000h. during the interval from when ce = 1 until count up, the value of the trncnt register is ffffh. figure 10-8: tmrn counter read register (trncnt) note: in the high-accuracy t-pwm mode, bit 0 is read as ?0?. remark: n = 0, 1 (8) tmrn sub-counter read register (trnsbc) the trnsbc register can read the value of the 16-bit counter. this register can only be read in 16-bit units. reset input or setting trnce = 0 clears this register to 0000h. remarks: 1. in the high-accuracy t-pwm mode, this register can be used only in the pwm mode with dead time. 2. n = 0, 1 figure 10-9: tmrn sub-counter read register (trnsbc) note: in the high-accuracy t-pwm mode, bit 0 is read as 0. after reset: 0000h r address: tr0cnt fffff5a4h, tr1cnt fffff5e4h 1514131211109876543210 trncnt note after reset: 0000h r address: tr0sbc fffff5a6h, tr1sbc fffff5e6h 1514131211109876543210 trnsbc note
309 chapter 10 16-bit inverter timer/counter r user?s manual u16580ee2v0ud00 (9) tmrn dead time setting register 0 (trndtc0) the trndtc0 register is a 10-bit register that specifies the dead time value. this register can be read and written in 16-bit units. reset input clears this register to 0000h. the dead time counter operates in the high-accuracy t-pwm mode and the pwm mode with dead time. in all other modes, be sure to set the trndtc0 register to 0000h. cautions: 1. when trnce = 1, do not rewrite trndtc0 with a different value. 2. when the trndtc0 register is set to 0000h, dead time is not inserted. 3. bits 0 and 10 to 15 are fixed to 0. remark: n = 0, 1 figure 10-10: tmrn dead time setting register 0 (trndtc0) (10) tmrn dead time setting register 1 (trndtc1) the trndtc1 register is a 10-bit register that specifies the dead time value. this register can be read and written in 16-bit units. reset input clears this register to 0000h. the dead time counter operates in the high-accuracy t-pwm mode and the pwm mode with dead time. in all other modes, be sure to set the trndtc1 register to 0000h. cautions: 1. when trnce = 1, do not rewrite trndtc1 with a different value. 2. when the trndtc1 register is set to 0000h, dead time is not inserted. 3. bits 0 and 10 to 15 are fixed to 0. remark: n = 0, 1 figure 10-11: tmrn dead time setting register 1 (trndtc1) after reset: 0000h r/w address: tr0dtc0 fffff5a0h, tr1dtc0 fffff5e0h 1514131211109876543210 trndtc0 000000 0 after reset: 0000h r/w address: tr0dtc1 fffff5a2h, tr1dtc1 fffff5e2h 1514131211109876543210 trndtc1 000000 0
310 chapter 10 16-bit inverter timer/counter r user?s manual u16580ee2v0ud00 10.3 control registers (1) tmrn control register 0 (trnctl0) the trnctl0 register is an 8-bit register that controls the operation of timer rn. this register can be read and written in 8-bit or 1-bit units. reset input changes the value of this register to initial setting 00h. caution: when trnce = 1, do not rewrite bits ot her than bit trnce of the trnctl0 register. figure 10-12: tmrn control register 0 (trnctl0) (1/2) remark: n = 0, 1 after reset: 00h r/w address: tr0ctl0 fffff580h, tr1ctl0 fffff5c0h 76543210 trnctl0 trnce 0 0 0 0 trncks2 trncks1 trncks0 (n = 0, 1) trnce timer rn operation control 0 internal operating clock operation disabled (reset timer rn asynchronously) 1 internal operating clock operation enabled when bit trnce is set to ?0?, the internal operation clock of timer rn stops (fixed to low level), and timer rn is set asynchronously. when bit trnce is set to ?1?, the internal operation of timer rn is enabled from when bit trnce was set to ?1? and count-up is performed. the time until count-up is as listed in table 10-2, ?tmrn count clock and count delay,? on page 311. remark: by setting trnce = 0 following functions of timer rn are reset. ? internal registers and internal latch ci rcuits other than re gisters that can be written to/from the cpu ? trnovf flag and flags in trnopt6 register ? counter, sub-counter, dead time counte r, counter read register, sub-counter read register ? trnccr0 to trnccr5 buffer registers, trndtc0 buffer register, and trndtc1 buffer register ? timer output (inactive level output)
311 chapter 10 16-bit inverter timer/counter r user?s manual u16580ee2v0ud00 figure 10-12: tmrn control register 0 (trnctl0) (2/2) remark: n = 0, 1 remarks: 1. f xx : system clock 2. f tmrn : base clock of timer rn (f tmrn = f xx /2) 3. n = 0, 1 trncks2 trncks1 trncks0 internal count clock selection of timer rn 000 f xx /2 001 f xx /4 010 f xx /8 011 f xx /16 100 f xx /32 101 f xx /64 110 f xx /256 111 f xx /1024 caution: set bits trncks2 to trncks0 when trnce = 0. when bit trnce is set from 0 to 1, bits trncks2 to trncks0 can be simultaneously set. remark: f xx : system clock table 10-2: tmrn count clock and count delay count clocks ttncks2 ttncks1 ttncks0 count delay minimum maximum f xx /2 0 0 0 3 base clocks 4 base clocks f xx /4 0 0 1 f xx /8 0 1 0 f xx /16 0 1 1 4 base clocks 5 base clocks + 1 count clock f xx /32 1 0 0 f xx /64 1 0 1 f xx /256 1 1 0 f xx /1024 1 1 1
312 chapter 10 16-bit inverter timer/counter r user?s manual u16580ee2v0ud00 (2) tmrn control register 1 (trnctl1) the trnctl1 register is an 8-bit register that controls the operation of timer rn. this register can be read and written in 8-bit or 1-bit units. reset input changes the value of this register to initial setting 00h. cautions: 1. in the one-shot pulse mode and external trigger pulse output mode, write access using ?1?, the same value as that of bit trnest, functions as one trigger. 2. set bits trneee and trnmd2 to trnmd0 when trnce = 0. (the same value as when trnce = 1 can be written). do not perform rewrite when trnce = 1. figure 10-13: tmrn control register 1 (trnctl1) (1/2) remark: n = 0, 1 after reset: 00h r/w address: tr0ctl1 fffff581h, tr1ctl1 fffff5c1h 76543210 trnctl1 0 trnest trneee 0 trn md3 trnmd2 trnmd1 trnmd0 (n = 0, 1) trnest software trigger control 0 no operation 1 enables software trigger control ? in one-shot pulse mode: one-shot pulse software trigger ? in external trigger pulse output mode: pulse output software trigger ? the trnest bit functions as a software trigger in the one-shot pulse mode and the external trigger pulse output mode, if it is set to 1 when trnce = 1. always write trnest = 1 when trnce = 1. ? the read value of the trnest bit is always 0. trneee count clock specification 0 use the internal clock (selected with bits trncks2 to trncks0 of the trnctl0 register) 1 use external clock input (tevtr1 pin input edge) note ? when tr1eee = 1 (external clock input tevtr1), the valid edge is specified by bits tr1ees1 and tr1ees0 of the trnioc2 register. note: external clock input pin is not available for tmr0 (n = 0).
313 chapter 10 16-bit inverter timer/counter r user?s manual u16580ee2v0ud00 figure 10-13: tmrn control register 1 (trnctl1) (2/2) remark: n = 0, 1 trnmd3 trnmd2 trnmd1 trnmd0 timer mode selection 0000interval timer mode 0001 external event count mode note 1 0010 external trigger pulse output mode note 2 0011one-shot pulse mode 0100pwm mode 0101free-r unning mode 0110 pulse width measurement mode note 1 0111tria ngular wave pwm mode 1000high accuracy t-pwm mode 1001pwm mode with d ead time other than above setting prohibited notes: 1. setting prohibited for tmr0. 2. for tmr0 an output pulse can be triggered only by software trigger (tr0est = 1).
314 chapter 10 16-bit inverter timer/counter r user?s manual u16580ee2v0ud00 (3) tmrn i/o control register 0 (trnioc0) the trnioc0 register is an 8-bit register that controls the timer output (pins torn0 to torn3). this register can be read and written in 8-bit or 1-bit units. reset input clears this register to 00h. caution: if the dead time cannot be secured or if spikes (noise) may occur on the output pin, set the trnioc0 register when trnce = 0. when trnce = 1, the trnioc0 register can be write accessed using the same value. figure 10-14: tmrn i/o control register 0 (trnioc0) remark: n = 0, 1 m = 0 to 3 after reset: 00h r/w address: tr0ioc0 fffff582h, tr1ioc0 fffff5c2h 76543210 trnioc0 trnol3 trnoe3 trnol2 trnoe2 trnol1 trnoe1 trnol0 trnoe0 (n = 0, 1) trnolm timer output level setting of tornm pin 0 active level = high level 1 active level = low level trnoem timer output control (tornm pin) 0 disable timer output (inactive level is output) 1 enable timer output
315 chapter 10 16-bit inverter timer/counter r user?s manual u16580ee2v0ud00 (4) tmr1 i/o control register 1 (tr1ioc1) the tr1ioc1 register is an 8-bit register that controls the valid edge of external signal inputs (pins tir10 to tir13). this register can be read and written in 8-bit or 1-bit units. reset input clears this register to 00h. cautions: 1. set the tr1ioc1 register when tr1ce = 0. when tr1ce = 1, write access to the tr1ioc1 register can be performed using the same value. 2. the tr1ioc1 register is valid only in the free-running mode and the pulse width measurement mode. in all other modes, capture operation is not performed. figure 10-15: tmr1 i/o control register 1 (tr1ioc1) after reset: 00h r/w address: fffff5c3h 76543210 tr1ioc1 tr1is7 tr1is6 tr1is5 tr1 is4 tr1is3 tr1is2 tr1is1 tr1is0 tr1is7 tr1is6 capture input (tir13) valid edge setting 0 0 no edge detection (capture operation invalid) 0 1 rising edge detection 1 0 falling edge detection 1 1 both, rising and falling edge detection tr1is5 tr1is4 capture input (tir12) valid edge setting 0 0 no edge detection (capture operation invalid) 0 1 rising edge detection 1 0 falling edge detection 1 1 both, rising and falling edge detection tr1is3 tr1is2 capture input (tir11) valid edge setting 0 0 no edge detection (capture operation invalid) 0 1 rising edge detection 1 0 falling edge detection 1 1 both, rising and falling edge detection tr1is1 tr1is0 capture input (tir10) valid edge setting 0 0 no edge detection (capture operation invalid) 0 1 rising edge detection 1 0 falling edge detection 1 1 both, rising and falling edge detection
316 chapter 10 16-bit inverter timer/counter r user?s manual u16580ee2v0ud00 (5) tmr1 i/o control register 2 (tr1ioc2) the tr1ioc2 register is an 8-bit register that controls the valid edge of external event count input (pin tevtr1) and external tr igger input (pin ttrgr1). this register can be read and written in 8-bit or 1-bit units. reset input clears this register to 00h. caution: set the tr1ioc2 register when tr1ce = 0. when tr1ce = 1, write access to the tr1ioc2 register can be performed using the same value. figure 10-16: tmr1 i/o control register 2 (tr1ioc2) after reset: 00h r/w address: fffff5c4h 76543210 tr1ioc2 0 0 0 0 tr1ees1 tr1ees0 tr1ets1 tr1ets0 tr1ees1 tr1ees0 external event counter input (tevtr1) va lid edge setting 0 0 no edge detection (capture operation invalid) 0 1 rising edge detection 1 0 falling edge detection 1 1 both, rising and falling edge detection remark: bits tr1ees1 and tr1ees0 are valid only when tr1ctl1 register bit tr1eee = 1, or when the external event count mode (tr1ctl1 register bits tr1md3 to tr1md0 = 0001b) is set. tr1ets1 tr1ets0 external trigger in put (ttrgr1) valid edge setting 0 0 no edge detection (capture operation invalid) 0 1 rising edge detection 1 0 falling edge detection 1 1 both, rising and falling edge detection remark: bits tr1ets1 and tr1ets0 are valid only when the external trigger pulse output mode or one-shot pulse mode (tr1ctl1 register bits tr1md3 to tr1md0 = 0010b or 0011b) is set.
317 chapter 10 16-bit inverter timer/counter r user?s manual u16580ee2v0ud00 (6) tmrn i/o control register 3 (trnioc3) the trnioc3 register is an 8-bit register that controls timer output (pins torn4 to torn7). this register can be read and written in 8-bit or 1-bit units. reset input clears this register to 00h. caution: if the dead time cannot be secured or if spikes (noise) may occur on the output pin, set the trnioc3 register when trnce = 0. when trnce = 1, the trnioc0 register can be write accessed using the same value. figure 10-17: tmrn i/o control register 3 (trnioc3) remark: n = 0, 1 m = 4 to 7 after reset: 00h r/w address: tr0ioc3 fffff585h, tr1ioc3 fffff5c5h 76543210 trnioc3 trnol7 trnoe7 trnol6 trn oe6 trnol5 trnoe5 trnol4 trnoe4 (n = 0, 1) trnolm timer output level setting of tornm pin 0 active level = high level 1 active level = low level trnoem timer output control (tornm pin) 0 disable timer output (inactive level is output) 1 enable timer output
318 chapter 10 16-bit inverter timer/counter r user?s manual u16580ee2v0ud00 (7) tmrn i/o control register 4 (trnioc4) the trnioc4 register is an 8-bit register that controls timer output error detection. this register can be read and written in 8-bit or 1-bit units. reset input clears this register to 00h. caution: set the trnioc4 register when trnce = 0. when trnce = 1, write access to the trnioc4 register can be performed using the same value. figure 10-18: tmrn i/o control register 4 (trnioc4) remark: n = 0, 1 after reset: 00h r/w address: tr0ioc3 fffff586h, tr1ioc3 fffff5c6h 76543210 trnioc4 0 trntba2 trntba1 trntba0 0 0 0 trneoc (n = 0, 1) trntba2 timer outputs (torn5/torn6) true bar active detection control 0 no detection of simultaneous active state of pins torn5 and torn6 1 detection of simultaneous active state of pins torn5 and torn6 remark: if simultaneous active state is dete cted when trntba2 = 1, the trntbf flag is set (1), and an error inte rrupt (inttrner) is output. trntba1 timer outputs (torn3/torn4) true bar active detection control 0 no detection of simultaneous active state of pins torn3 and torn4 1 detection of simultaneous active state of pins torn3 and torn4 remark: if simultaneous active state is dete cted when trntba1 = 1, the trntbf flag is set (1), and an error inte rrupt (inttrner) is output. trntba0 timer outputs (torn1/torn2) true bar active detection control 0 no detection of simultaneous active state of pins torn1 and torn2 1 detection of simultaneous active state of pins torn1 and torn2 remark: if simultaneous active state is dete cted when trntba0 = 1, the trntbf flag is set (1), and an error inte rrupt (inttrner) is output. trneoc error interrupt output control 0 disable output of error interrupt (inttrner) 1 enable output of error interrupt (inttrner) remark: for details about error inte rrupt control, refer to 10.9 error interrupts .
319 chapter 10 16-bit inverter timer/counter r user?s manual u16580ee2v0ud00 (8) tmrn option register 0 (trnopt0) the trnopt0 register is an 8-bit register that sets the capture/compare operation and detects overflow. this register can be read and written in 8-bit or 1-bit units. reset input clears this register to 00h. caution: when tr1ce = 1, do not rewrite bits tr1ccs3 to tr1ccs0. figure 10-19: tmrn option register 0 (trnopt0) (1/2) remark: n = 0, 1 after reset: 00h r/w address: fffff587h 76543210 tr0opt000000tr0cmstr0cuftr0ovf after reset: 00h r/w address: fffff5c7h 76543210 tr1opt0 tr1ccs3 tr1ccs2 tr1ccs1 tr1ccs0 0 tr1cms tr1cuf tr1ovf tr1ccs3 tr1ccr3 register capture/compare selection 0 select compare register 1 select capture register remark: bit tr1ccs3 is only valid in the free-running mode. in all other modes, this bit is invalid. tr1ccs2 tr1ccr2 register capture/compare selection 0 select compare register 1 select capture register remark: bit tr1ccs2 is only valid in the free-running mode. in all other modes, this bit is invalid. tr1ccs1 tr1ccr1 register capture/compare selection 0 select compare register 1 select capture register remark: bit tr1ccs1 is only valid in the free-running mode. in all other modes, this bit is invalid. tr1ccs0 trnccr0 register capture/compare selection 0 select compare register 1 select capture register remark: bit tr1ccs0 is only valid in the free-running mode. in all other modes, this bit is invalid.
320 chapter 10 16-bit inverter timer/counter r user?s manual u16580ee2v0ud00 figure 10-19: tmrn option register 0 (trnopt0) (2/2) remark: n = 0, 1 trncms compare register transfer timing mode selection 0 reload mode (batch rewrite): when the trnccr1 register is written to , all the registers are updated at the next reload timing (reload). even if re gisters other than the trnccr1 register are written, reload is not executed. 1 anytime rewrite mode: each register is updated independently, and when write access is performed to a compare register, the register is u pdated to the value used during anytime write access. several clocks are required until the val ue is transferred to the register following write. (refer to 10.4.2 (1) anytime rewrite .) remark: the trncms bit is valid only in the high-accuracy t-pwm mode, in all other modes it is invalid and has to be cleared (trncms = 0). trncuf timer r counter up/down detection flag 0 the timer counter is in up count state. 1 the timer counter is in down count state. remark: the trncuf bit is valid only in the high-accuracy t-pwm mode and triangular wave pwm mode. in all other modes, it is invalid (trncuf = 0). trnovf timer r overflow detection flag 0 no overflow occurrence (after bit was cleared) 1 overflow occurrence remarks: 1. the trnovf bit is set (1) when the 16-bit counter value overflows from ffffh to 0000h. 2. the trnovf bit is cleared (0) when eit her 0 is written to it, or trnce = 0 is set. 3. when trnovf bit is set (1), an overflow interrupt (inttrnov) is simultaneously output. cautions: 1. overflow can only occur in the free-running mode and the t-pwm mode. if, in the high- accuracy t-pwm mode, the set conditions for the trndtc0 and trndtc1 registers are incorrect, the trnovf bit may be set (1). 2. when trnovf = 1, even if the trnovf bit and the trnopt0 register are read, the trnovf bit is not cleared. 3. the trnovf bit can be read and wr itten, but even if ?1? is written to trnovf bit from the cpu, this is ignored.
321 chapter 10 16-bit inverter timer/counter r user?s manual u16580ee2v0ud00 (9) tmrn option register 1 (trnopt1) the trnopt1 register is an 8-bit register used to enable/disable peak/valley interrupts and set interrupt thinning out. this register can be read and written in 16-bit or 8-bit units. reset input clears this register to 00h. cautions: 1. the trnopt1 register write method is as follows. ? in high-accuracy t-pwm mode: anytime write, or reload write ? in mode other than high-accura cy t-pwm mode: reload write 2. do not set trnice = 0 and trnioe = 0. since reload does not occur when trnice, trnioe = 00, the trnopt1 register, which is a reload write register, stops being updated. figure 10-20: tmrn option register 1 (trnopt1) (1/2) remark: n = 0, 1 after reset: 00h r/w add ress: tr0opt1 fffff58eh tr1opt1 fffff5ceh 76543210 trnopt1 trnice trnioe trnrde trni d4 trnid3 trnid2 trnid1 trnid0 (n = 0, 1) trnice peak interrupts (inttrncd) control 0 disable peak interrupt (inttrncd) ou tput in the counter?s peak timing interrupt thinning ou t is not performed. reload operation is disabled in the counter?s peak timing. 1 enable peak interrupt (inttrncd) in the counter?s peak timing interrupt thinning out is performed. reload operation is enabled in the counter?s peak timing. remark: bit trnice is valid only in the pwm mode, high-accuracy t-pwm mode, and pwm mode with dead time. trnioe valley interrupt (inttrnod) control 0 disable valley interrupt (inttrnod) output in the counter?s valley timing reload operation is disabled in the counter?s valley timing. 1 enable valley interrupt (inttrnod) output in the counter?s valley timing reload operation is enabled in the counter?s valley timing. remark: bit trnioe is valid only in the high-accuracy t-pwm mode and triangular wave pwm mode.
322 chapter 10 16-bit inverter timer/counter r user?s manual u16580ee2v0ud00 figure 10-20: tmrn option register 1 (trnopt1) (2/2) remark: n = 0, 1 trnrde reload timing thinning out control 0 don?t perform reload thinning out reload timing occurs at each peak/valley. 1 perform reload thinning out reload timing occurs at the same interval as interrupt thinning out. remark: bit trnrde is valid only in the pwm mode, high-accuracy t-pwm mode, triangular wave pwm output mode, and pwm mode with dead time. trnid4 trnid3 trnid2 trnid1 trnid0 interrupt thinning out rate 00000 no thinning out 00001 1/2 00010 1/3 00011 1/4 11101 1/30 11110 1/31 11111 1/32 caution: if, when trnce = 1, the trnopt 1 register is write accessed (including same value to bits trnid4 to trnid0), the interrupt thin ning out counter is cleared. remark: bits trnid0 to trnid4 are valid only in the pwm mode, high-accuracy t-pwm mode, triangular wave pwm mode, and pwm mode with dead time.
323 chapter 10 16-bit inverter timer/counter r user?s manual u16580ee2v0ud00 (10) tmrn option register 2 (trnopt2) the trnopt2 register is an 8-bit register that controls a/d conversion trigger output (trnadtrg0 signal). this register can be read and written in 8-bit or 1-bit units. reset input clears this register to 00h. caution: the settings of the trnccr5 and trnccr4 registers have an influence on the pwm output of pins torn5 and torn4 at the same time as the trnadtrg0 signal output. therefore, if setting bits trnat05 to trnat02, it is recommended to set the trnopt3 register as follows. ? in the triangular wave pwm mode, when setting trnat05 = 1, set trnoe5 = 0. ? in the pwm mode and triangular wave pwm mode, when setting trnat04 = 1, set trnoe5 = 0. ? in the triangular wave pwm mode, when setting trnat03 = 1, set trnoe4 = 0 ? in the pwm mode and the triangular wave pwm mode, when setting trnat02 = 1, set trnoe4 = 0. figure 10-21: tmrn option register 2 (trnopt2) (1/2) remark: n = 0, 1 after reset: 00h r/w add ress: tr0opt2 fffff588h tr1opt2 fffff5c8h 76543210 trnopt2 0 0 trnat05 trnat04 trnat03 trnat02 trnat01 trnat00 (n = 0, 1) trnat05 trnat04 a/d converter trigger signal (trnadtrg0) generation with occurrence of compare match interrupt (inttrnccr5) 0 0 no trigger signal is generated when inttrnccr5 occurs. 0 1 trigger signal is generated, when inttrnccr5 occurs and tmrn is counting up. 1 0 trigger signal is generated, when inttrnccr5 occurs and tmrn is counting down. 1 1 trigger signal is generated, when inttrnccr5 occurs in any state (tmrn is counting up or down) cautions: 1. bit trnat05 can be set to 1 only in the triangular wave pwm mode and high-accuracy t-pwm mode. in all other modes, be sure to set this bit to 0. 2. bit trnat04 can be set to 1 only in the pwm mode, triangular wave pwm mode, high-accuracy t-pwm mode, and pwm mode with dead time. in all other modes, be sure to set this bit to 0.
324 chapter 10 16-bit inverter timer/counter r user?s manual u16580ee2v0ud00 figure 10-21: tmrn option register 2 (trnopt2) (2/2) remark: n = 0, 1 trnat03 trnat02 a/d converter trigger signal (trnadtrg0) generation with occurrence of compare matc h interrupt (inttrnccr4) 0 0 no trigger signal is generated when inttrnccr4 occurs. 0 1 trigger signal is generated, when inttrnccr4 occurs and tmrn is counting up. 1 0 trigger signal is generated, when inttrnccr4 occurs and tmrn is counting down. 1 1 trigger signal is generated, when inttrnccr4 occurs in any state (tmrn is counting up or down) cautions: 1. bit trnat03 can be set to 1 only in the triangular wave pwm mode and high-accuracy t-pwm mode. in all other modes, be sure to set this bit to 0. 2. bit trnat02 can be set to 1 only in the pwm mode, high-accuracy t-pwm mode, triangular wave pwm mode, and pwm mode with dead time. in all other modes, be sure to set th is bit to 0. trnat01 a/d converter trigger signal (trnadtrg0) generation with occurrence of peak interrupt (inttrncd) 0 no trigger signal is generated when peak interrupt (inttrncd) occurs. 1 trigger signal is generated when peak interrupt (inttrncd) occurs after thinning out. caution: bit trnat01 can be set to 1 only in the pwm mode, high-accuracy t-pwm mode, and pwm mode with dead time. in all other modes, be sure to set this bit to 0. remark: when bit trnat01 is set (1) the trigger signal coincides with the peak interrupt (inttrncd) controlled by the trnopt1 register (including thinning out). trnat00 a/d converter trigger signal (trnadtrg0) generation with occurrence of valley interrupt (inttrnod) 0 no trigger signal is generated when valley interrupt (inttrnod) occurs. 1 trigger signal is generated when va lley interrupt (inttrnod) occurs after thinning out. caution: bit trnat00 can be set to 1 only in the high-accuracy t-pwm mode and triangular wave pwm mode. in all other mo des, be sure to se t this bit to 0. remark: when bit trnat00 is set (1) the trigger signal coincides with the valley interrupt (inttrnod) controlled by the trnopt1 register (including thinning out).
325 chapter 10 16-bit inverter timer/counter r user?s manual u16580ee2v0ud00 (11) tmrn option register 3 (trnopt3) the trnopt3 register is an 8-bit register that controls a/d conversion trigger output (signal trnadtrg1). this register can be read and written in 8-bit or 1-bit units. reset input clears this register to 00h. caution: the settings of the trnccr5 and trnccr4 registers have an influence on the pwm outputs of pins torn5, torn4 at the sa me time as the trnadtrg0 signal output. therefore, if setting bits trnat15 to trnat12, it is recommended to set the trnopt3 register as follows. ? in the triangular wave pwm mode, when setting trnat15 = 1, set trnoe5 = 0. ? in the pwm mode and triangular wave pwm mode, when setting trnat14 = 1, set trnoe5 = 0. ? in the triangular wave pwm mode, when setting trnat13 = 1, set trnoe4 = 0 ? in the pwm mode and the triangular wave pwm mode, when setting trnat12 = 1, set trnoe4 = 0. figure 10-22: tmrn option register 3 (trnopt3) (1/2) remark: n = 0, 1 after reset: 00h r/w add ress: tr0opt3 fffff589h tr1opt3 fffff5c9h 76543210 trnopt3 0 0 trnat15 trnat14 trnat13 trnat12 trnat11 trnat10 (n = 0, 1) trnat15 trnat14 a/d converter trigger signal (trnadtrg1) generation with occurrence of compare match interrupt (inttrnccr5) 0 0 no trigger signal is generated when inttrnccr5 occurs. 0 1 trigger signal is generated, when inttrnccr5 occurs and tmrn is counting up. 1 0 trigger signal is generated, when inttrnccr5 occurs and tmrn is counting down. 1 1 trigger signal is generated, when inttrnccr5 occurs in any state (tmrn is counting up or down) cautions: 1. bit trnat15 can be set to 1 only in the triangular wave pwm mode and high-accuracy t-pwm mode. in all other modes, be sure to set this bit to 0. 2. bit trnat14 can be set to 1 only in the pwm mode, triangular wave pwm mode, high-accuracy t-pwm mode, and pwm mode with dead time. in all other modes, be sure to set this bit to 0.
326 chapter 10 16-bit inverter timer/counter r user?s manual u16580ee2v0ud00 figure 10-22: tmrn option register 3 (trnopt3) format (2/2) remark: n = 0, 1 trnat13 trnat12 a/d converter trigger signal (trnadtrg1) generation with occurrence of compare matc h interrupt (inttrnccr4) 0 0 no trigger signal is generated when inttrnccr4 occurs. 0 1 trigger signal is generated, when inttrnccr4 occurs and tmrn is counting up. 1 0 trigger signal is generated, when inttrnccr4 occurs and tmrn is counting down. 1 1 trigger signal is generated, when inttrnccr4 occurs in any state (tmrn is counting up or down) cautions: 1. bit trnat13 can be set to 1 only in the triangular wave pwm mode and high-accuracy t-pwm mode. in all other modes, be sure to set this bit to 0. 2. bit trnat12 can be set to 1 only in the pwm mode, high-accuracy t-pwm mode, triangular wave pwm mode, and pwm mode with dead time. in all other modes, be sure to set th is bit to 0. trnat11 a/d converter trigger signal (trnadtrg1) generation with occurrence of peak interrupt (inttrncd) 0 no trigger signal is generated when peak interrupt (inttrncd) occurs. 1 trigger signal is generated when peak interrupt (inttrncd) occurs after thinning out. caution: bit trnat11 can be set to 1 only in the pwm mode, high-accuracy t-pwm mode, and pwm mode with dead time. in all other modes, be sure to set this bit to 0. remark: when bit trnat11 is set (1) the trigger signal coincides with the peak interrupt (inttrncd) controlled by the trnopt1 register (including thinning out). trnat10 a/d converter trigger signal (trnadtrg1) generation with occurrence of valley interrupt (inttrnod) 0 no trigger signal is generated when valley interrupt (inttrnod) occurs. 1 trigger signal is generated when va lley interrupt (inttrnod) occurs after thinning out. caution: bit trnat10 can be set to 1 only in the high-accuracy t-pwm mode and triangular wave pwm mode. in all other mo des, be sure to se t this bit to 0. remark: when bit trnat10 is set (1) the trigger signal coincides with the valley interrupt (inttrnod) controlled by the trnopt1 register (including thinning out).
327 chapter 10 16-bit inverter timer/counter r user?s manual u16580ee2v0ud00 (12) tmrn option register 6 (trnopt6) the trnopt6 register is an 8-bit register that controls the various flags of timer rn. this register can be read and written in 8-bit or 1-bit units. reset input or setting trnce = 0 clears this register to 00h. remark: for the functions of the various flags, refer to 10.6 flags . figure 10-23: tmrn option register 6 (trnopt6) remark: n = 0, 1 after reset: 00h r/w add ress: tr0opt6 fffff58ch tr1opt6 fffff5cch 76543210 trnopt600000trntbftrnsuftrnrsf (n = 0, 1) trntbf true bar active detection flag 0 normal phase and inverted phase are not simultaneously active. 1 normal phase and inverted phase are simultaneously active. this flag detects when the normal phase and inverted phase are simultaneously active, while any of bits trntba2 to trntba0 of the trnioc4 register is 1. when bits trntba2 to trntba0 = 000b, simultaneous active is not detected. remarks: 1. the trntbf flag is set (1) upon detec tion that any of the normal phases (torn1, torn3, torn5) and inverted phases (torn2, torn4, torn6) are simultaneously active, and an error interrupt (inttrner) is output at such time. 2. this flag can be cleared by writing ?0? to it. trnsuf timer r sub-counter up/down detection flag 0 sub-counter is counting up 1 sub-counter is counting down the trnsuf flag detects sub-counter coun ting from 0000h until (trnccr0 register value - 2) as up count, and counting from trnccr 0 register value until 0002h as down count. remarks: 1. the trnsuf flag is a read-only flag. 2. the trnsuf flag is valid only in the high-accuracy t-pwm mode. trnrsf reload suspension flag 0 write access to trnccr0 to trnccr5 and trnopt1 registers is enabled (no reload request, or completion of reload). 1 write access to trnccr0 to trnccr5 and trnopt1 registers is disabled (reload request was output). the trnrsf flag indicates output of a reload request. it indicates that the data to be transferred next will be held in the trnccr0 to trnccr5 and trnopt1 registers. the trnrsf flag is set (1) upon write to the trnccr1 register, and cleared (0) upon reload completion.
328 chapter 10 16-bit inverter timer/counter r user?s manual u16580ee2v0ud00 (13) tmrn option register 7 (trnopt7) the trnopt7 register is an 8-bit register that controls time output switching. this register can be read and written in 8-bit or 1-bit units. reset input clears this register to 00h. figure 10-24: tmrn option register 7 (trnopt7) remark: n = 0, 1 after reset: 00h r/w address: tr0opt7 fffff58dh tr1opt7 fffff5cdh 76543210 trnopt70000000trntos (n = 0, 1) trntos timer output (tor n0) switching control 0 output counter?s (trncnt) up/down count flag to torn0 pin 1 output sub-counter?s (trnsbc) up/ down count flag to torn0 pin when trntos = 0, the status of bit trncuf of the trnopt0 register is output to pin torn0. when trntos = 1, the status of bit trnsuf of the trnopt6 register is output to the torn0 pin. remark: the trntos bit is valid only in the high-accuracy t-pwm mode.
329 chapter 10 16-bit inverter timer/counter r user?s manual u16580ee2v0ud00 10.4 basic operation 10.4.1 basic counter operation this section describes the basic operation of the 16-bit counter. for details, refer to the description of the operation of each mode. (1) count start operation the 16-bit counter of timer r starts counting from initial value ffffh in all the modes except the high-accuracy t-pwm mode. the counter counts up ffffh, 0000h, 0001h, 0002h, 0003h, ? for the count operation in the high-accuracy t-pwm mode refer to section 10.10.9 (4) counter operation in high-accuracy t-pwm mode . (2) clear operation the 16-bit counter is cleared to 0000h upon a match between the 16-bit counter and the compare register. counting immediately following the start of count operation and counting from ffffh to 0000h in the case of overflow are not detected as clear operations. (3) overflow operation 16-bit counter overflow occurs when the value of the 16-bit counter changes from ffffh to 0000h. when overflow occurs, bit trnovf of the trnopt0 register is set (to 1), and an interrupt (inttrnov) is output. no overflow interrupt (inttrnov) is output under the following conditions. ? immediately after count operation start ? when compare value is matched and cleared at ffffh caution: be sure to check that the overflow flag (trnovf) is set to 1 following output of the overflow interrupt (inttrnov). (4) counter read operation during count operation in the case of timer r, the value of the 16-bit counter can be read by the trncnt register during count operation.
330 chapter 10 16-bit inverter timer/counter r user?s manual u16580ee2v0ud00 (5) interrupt operation in the case of timer r, the following interrupts are output. ? inttrncc0: functions as trnccrn0 buffer register match interrupt. ? inttrncc1: functions as trnccrn1 buffer register match interrupt. ? inttrncc2: functions as trnccrn2 buffer register match interrupt. ? inttrncc3: functions as trnccrn3 buffer register match interrupt. ? inttrncc4: functions as trnccrn4 buffer register match interrupt. ? inttrncc5: functions as trnccrn5 buffer register match interrupt. ? inttrncd: functions as a peak interrupt at the timing when the counter switches from up count to down count. ? inttrnod: functions as a valley interrupt at the timing when the counter switches from up count to down count. ? inttrnov: functions as an overflow interrupt. ? inttrner: functions as an normal phase/inverted phase simultaneous active detection interrupt. remark: n = 0, 1
331 chapter 10 16-bit inverter timer/counter r user?s manual u16580ee2v0ud00 10.4.2 compare register rewrite operation in the pwm mode, high-accuracy t-pwm mode, pwm mode with dead time, external trigger pulse output mode, and triangular wave pwm mode, the reload function is valid. (in all other modes, reload-related sett ings are invalid.) the compare/control registers with the reload function are listed below. ? trnccr0 to trnccr5 ? trnopt1 compare registers with the reload function can be rewritten in the following modes. ? anytime rewrite mode in this mode, each compare register is updated independently, and when a compare register is written to, the register is updated to the value written during anytime write access. ? reload mode (batch rewrite) when the trnccr1 register is written to, all the registers are updated at the next reload timing (reload). reload does not occur even if a register ot her than the trnccr1 regi ster is written to. a reload request flag (trnrsf) is provided. the compare register can be rewritten using dma transfer. dma transfer is performed as follows. note: dummy data transfer address register name dma transfer sequence fffff590h tr0ccr5 fffff592h tr0ccr4 fffff594h - note fffff596h - note fffff598h tr0ccr0 fffff59ah tr0ccr3 fffff59ch tr0ccr2 fffff59eh tr0ccr1 address register name dma transfer sequence fffff5d0h tr1ccr5 fffff5d2h tr1ccr4 fffff5d4h - note fffff5d6h - note fffff5d8h tr1ccr0 fffff5dah tr1ccr3 fffff5dch tr1ccr2 fffff5deh tr1ccr1
332 chapter 10 16-bit inverter timer/counter r user?s manual u16580ee2v0ud00 for details about the interrupt thinning out function specified by setting the trnopt1 register, refer to 10.7 interrupt thinning out function . notes: 1. rewrite is performed upon valley interrupt. 2. set with trnopt0 register bit trncms = 0, trnopt1 register bit trnrde = 0 mode rewrite timing interval mode anytime rewrite external event count mode anytime rewrite external trigger pulse output mode reload one-shot pulse mode anytime rewrite pwm mode reload free-running mode anytime rewrite pulse width measurement mode reload triangular wave pwm mode reload note 1 high-accuracy t-pwm mode anytime rewrite, reload note 2 pwm mode with dead time reload
333 chapter 10 16-bit inverter timer/counter r user?s manual u16580ee2v0ud00 (1) anytime rewrite anytime rewrite is set by setting trnopt0 register bit trncms = 1. the trnopt1 register bit trnrde setting is ignored. in this mode, the value written to each compare register is immediately transferred to the internal buffer register and compared to the counter value. following write to a compare register (trnccr0 register, etc.), the value is transferred to the internal buffer register after the lapse of 4 clocks (f tmrn ). however, since only the trnccr1 register has a 2-stage configuration, the actual transfer timing is after the lapse of 5 clocks (f tmrn ). figure 10-25: anytime rewrite timing remarks: 1. d01, d02: trnccr0 register se tting value (0000h to ffffh) d11, d12: trnccr1 register se tting value (0000h to ffffh) d21: trnccr2 register settin g value (0000h to ffffh) d31: trnccr3 register settin g value (0000h to ffffh) 2. timing chart using interval timer mode as an example 3. n = 0, 1 counter trnccr0 trnccr1 trnccr2 trnccr3 inttrncc0 inttrncc1 inttrncc2 inttrncc3 trnccr0 buffer trnccr1 buffer trnccr2 buffer trnccr3 buffer 0000h d 11 d 11 d 12 d 11 d 11 d 12 d 12 d 21 d 21 d 21 d 01 d 01 d 02 d 02 d 01 d 12 d 21 0000h d 01 d 02 0000h d 21 d 31 0000h d 31 d 31 d 31 d 31 trnrsf trnce 31 d l
334 chapter 10 16-bit inverter timer/counter r user?s manual u16580ee2v0ud00 (a) cautions related to rewriting trnccr0 register in high-accuracy t-pwm mode when the trnccr0 register is rewritten during operation using the anyt ime rewrite function, anytime transfer of the value to the trnccr0 buffer register is not performed. the timing is shown below. remark: d1: trndtc1 setting value following write to the trnccr0 register, the value of the trnccr0 register is transferred to the trnccr0 buffer register at the next peak or at the valley timing. since trncms = 1 (anytime rewrite), the settings of bits trnioe, trnice, trnrde, and trnid4 to trnid0 have no influence. (b) cautions related to rewriting of trnccr1 to trnccr3 registers rewrite in <1> interval (rewri te before match occurrence) in the case of rewrite before a match betwee n the trnccr1 to trnc cr3 registers and the counter occurs, a match with the counter occurs fo llowing rewrite and the rewr ite value is instantly reflected. counter trnccr0 ?a? ?a? d1 trnccr0 buffer ?a? ?b? d1 ?c? ?b? ?b? ?c? ?c? counter trnccr1,2,3 <1> <2> ?i? ?i? ?i? ?i? ?i? <3> <4> <1> <2> <3> <4> counter trnccr1 ?i? ?i? trnccr1 buffer torn1 ?k? ?k? torn2 ?k? ?k? ?i? ?i?
335 chapter 10 16-bit inverter timer/counter r user?s manual u16580ee2v0ud00 if a value smaller than the counter value is written before match occurrence, no match occurs, so the following output wave results. if no match occurs, the timer output remains unchanged. however, even if a match does not occur the timer output is forcibly changed to normal phase active level at peaks. rewrite in <2> interval (rew rite after match occurrence) in the case of rewrite after a match between the trnccr1 to tr nccr3 registers and the counter occurs, further match occurrences are ignored, so the rewrite value is not reflected. counter trnccr1 ?i? trnccr1 buffer torn1 ?r? ?r? ?i? forced rise torn2 ?i? ?i? ?r? ?r? counter trnccr1 ?i? ?k? trnccr1 buffer inttrncc1 ?k? ?k? torn1 ?k? torn2 ? matches due to rewrite after match occurrence are ignored, and the timer output remains unchanged. ? the inttrncc1 signal becomes valid from the next match after up/down count is switched and the timer output changes. however, a match interrupt is output upon inttrncc1 interrupt output. ?i? ?i? ?k? ?k?
336 chapter 10 16-bit inverter timer/counter r user?s manual u16580ee2v0ud00 rewrite in <3> interval (rewri te before match occurrence) in the case of rewrite before a match betwee n the trnccr1 to trnc cr3 registers and the counter occurs, a match with the counter occurs fo llowing rewrite and the rewr ite value is instantly reflected. if a value larger than the counter value is written before match occurrence, no match occurs, so the following output wave results. if no match occurs, the timer output remains unchanged. however, even if a match occurs, the timer outpu t is forcibly changed to normal phase inactive level at valleys. counter trnccr1 ?i? ?k? trnccr1 buffer torn1 ?k? ?k? torn2 ?i? ?i? ?k? ?k? counter trnccr1 ?i? trnccr1 buffer torn1 ?r? ?r? ?r? forced fall torn2 ?i? ?i? ?r? ?r?
337 chapter 10 16-bit inverter timer/counter r user?s manual u16580ee2v0ud00 rewrite in <4> interval (rew rite after match occurrence) in the case of rewrite after a match between the trnccr1 to tr nccr3 registers and the counter occurs, further match occurrences are ignored, so the rewrite value is not reflected. (c) cautions related to rewriting trnopt1 since the internal interrupt thinning out counter is cleared when the trnopt1 register is written to, the interrupt output interval may temporarily become longer. counter trnccr1 ?i? ?k? trnccr1 buffer inttrncc1 ?k? ?k? ?i? torn1 ? matches due to rewrite after match occurrence are ignored, and the timer output remains unchanged. ? the inttrncc1 signal becomes valid from the next match after up/down count is switched and the timer output changes. however, a match interrupt is output upon inttrncc1 interrupt output. torn2 ?k? ?k? ?i? ?i?
338 chapter 10 16-bit inverter timer/counter r user?s manual u16580ee2v0ud00 (2) batch rewrite (reload mode) batch rewrite is set by setting trnopt0 regi ster bit trncms = 0, trnopt1 register bit trnrde = 0, trnice = 1 (reload enabled at peaks), and trnioe = 1 (reload enabled at valleys). in this mode, the values written to the various compare registers are all transferred at the same time to the respective buffer registers at the reload timing. figure 10-26: basic operation flow during batch rewrite caution: write access to the trnccr1 register includes also the reload enable operation. therefore, rewrite the trnccr1 register after rewriting the other trnccr registers. remarks: 1. this sample flow chart is for the pwm mode. 2. n = 0, 1 start initial settings timer operation enable (trnce = 1) transfer of values of trnccr0 to trnccr3 to buffers trnccr0 to trn cc r 3 rewrite trnccr0 ? match between counter and trnccr0 ? counter clear & start ? transfer of values of trnccr0 to trnccr3 to trnccr0 buffer any order inttrncc0 rewrite trnccr2 rewrite trnccr3 rewrite trnccr1 reload enable read trnrsf trnrsf 1 0
339 chapter 10 16-bit inverter timer/counter r user?s manual u16580ee2v0ud00 figure 10-27: batch rewrite timing (1/2) trnccr0 trnccr0 buffer trnccr1 trnccr1 buffer trnccr2 trnccr2 buffer trnccr3 trnccr3 buffer trnccr4 trnccr4 buffer trnccr5 trnccr5 buffer trnopt1 trnopt1 buffer reload rewrite timing counter inttrnod inttrncd0 reload upon trnccr1 write batch update at reload timing trnrsf setting of reload hold flag flag clearing following reload
340 chapter 10 16-bit inverter timer/counter r user?s manual u16580ee2v0ud00 figure 10-27: batch rewrite timing (2/2) counter reload upon trnccr1 write batch update at reload timing setting of reload hold flag flag clearing following reload trnccr0 tsnccr0 buffer trnccr1 tsnccr1 buffer trnccr2 tsnccr2 buffer trnccr3 tsnccr3 buffer trnccr4 tsnccr4 buffer trnccr5 tsnccr5 buffer trnopt1 tsnopt1 buffer inttrncd0 trnrsf
341 chapter 10 16-bit inverter timer/counter r user?s manual u16580ee2v0ud00 (a) trnccr0 register rewrite operation in high-accuracy t-pwm mode when rewriting the trnccr0 register in the batch rewrite mode, the output waveform changes according to whether reload occurs at a peak or at a valley (trnice = 1, trnioe = 1 settings). rewrite in <1> interval (rewrite during up count) since the next reload timing becomes the peak point, the cycle on the down count side changes and an asymmetrical triangular waveform is outp ut. also, since the cycle changes, reset the duty value as necessary. remark: d1: trndtc1 setting value counter <1> <2> <1> <2> counter trnccr0 ?i? ?k? trnccr0 buffer inttrncd ?k? ?k? torn1 trnccr1 trnccr1 buffer ?k? ?k? ?k? inttrnod ?m? d1 reloadable timing ?n d1? value loaded to counter torn2 ?i? ?i? ?k? ?k? ?n? ?n? ?m? ?m?
342 chapter 10 16-bit inverter timer/counter r user?s manual u16580ee2v0ud00 remark: d1: trndtc1 setting value the counter loads the trnccr0 value minus ?d1? upon occurrence of reload in the high-accuracy t-pwm mode. as a result, the expected waveform can be output even if the cycle value is changed at the peak reload timing. rewrite in <2> interval (rewrite during down count) since the next reload timing be comes the valley point, the cycle va lue changes from the next cycle and the asymmetrical triangular waveform output is held. since the cycle changes, be sure to set again the duty value as required. remark: d1: trndtc1 setting value counter trnccr0 ?i? trnccr0 buffer inttrncd ?k? torn1 trnccr1 trnccr1 buffer ?k? inttrnod ?m? d1 ?r d1? reloadable timing ?r d1? value loaded to counter torn2 ?i? ?i? ?k? ?k? ?m? ?m? ?r? ?r? counter trnccr0 ?i? trnccr0 buffer inttrncd ?k? torn1 trnccr1 trnccr1 buffer ?k? ?k? ?k? inttrnod ?n d1? ?m d1? ?i? reloadable timing torn2 ?i? ?i? ?k? ?k? ?m? ?m? ?n? ?n?
343 chapter 10 16-bit inverter timer/counter r user?s manual u16580ee2v0ud00 (b) trnccr1 to trnccr3 register rewrit e operation in high-accuracy t-pwm mode remark: when trndtc0 = 0, trndtc1 = 0 rewrite in <1> interval (rewrite during up count) since reload is performed at the peak interrupt timing, an asymmetric triangular waveform is output. rewrite in <2> interval (r ewrite during down count) since reload is performed at the valley interrupt timing, an asymmetric triangular waveform is output. counter ?i? inttrncc1 torn1 trnccr1 trnccr1 buffer ?k? ?r? ?r? reloadable timing torn2 <1> <2> <1> <2> ?i? ?i? ?k? ?k? ?r? ?r?
344 chapter 10 16-bit inverter timer/counter r user?s manual u16580ee2v0ud00 10.4.3 list of outputs in each mode (1) timer outputs in each mode the timer outputs (pins torn0 to torn7) in each mode are listed below. table 10-3: list of timer outputs in each mode (1/2) operation mode torn0 torn1 torn2 torn3 interval mode toggle output upon trnccr0 compare match toggle output upon trnccr1 compare match toggle output upon trnccr2 compare match toggle output upon trnccr3 compare match external event count mode toggle output upon trnccr0 compare match toggle output upon trnccr1 compare match toggle output upon trnccr2 compare match toggle output upon trnccr3 compare match external trigger pulse output mode toggle output upon ccr0 compare match or external trigger input external trigger pulse waveform output external trigger pulse waveform output external trigger pulse waveform output one-shot pulse mode active at count start. inactive upon trnccr0 match. active upon trnccr1 match. inactive upon trnccr0 match. active upon trnccr2 match. inactive upon trnccr0 match. active upon trnccr3 match. inactive upon trnccr0 match. pwm mode toggle output upon trnccr0 compare match pwm output upon trnccr1 compare match pwm output upon trnccr2 compare match pwm output upon trnccr3 compare match free-running mode toggle output upon trnccr0 compare match toggle output upon trnccr1 compare match toggle output upon trnccr2 compare match toggle output upon trnccr2 compare match pulse width measurement mode ---- triangular wave pwm mode inactive during up count. active during down count. pwm output upon trnccr1 compare match pwm output upon trnccr2 compare match pwm output upon trnccr3 compare match high-accuracy t-pwm mode inactive during coun- ter or sub-counter up count. active during down count. pwm output (with dead time) upon trnccr1 compare match inverted phase output to torn1 pwm output (with dead time) upon trnccr2 compare match pwm mode with dead time toggle output upon trnccr0 compare match pwm output (with dead time) upon trnccr1 compare match inverted phase output to torn1 pwm output (with dead time) upon trnccr2 compare match
345 chapter 10 16-bit inverter timer/counter r user?s manual u16580ee2v0ud00 note: for details on torn7, refer to 10.4.3 (a) torn7 pin output control . table 10-3: list of timer outputs in each mode (2/2) operation mode torn4 torn5 torn6 torn7 interval mode toggle output upon trnccr4 compare match toggle output upon trnccr5 compare match -- external event count mode toggle output upon trnccr4 compare match toggle output upon trnccr5 compare match -- external trigger pulse output mode external trigger pulse waveform output external trigger pulse waveform output -- one-shot pulse mode high upon trnccr4 match. inactive upon trnccr0 match. high upon trnccr5 match. inactive upon trnccr0 match. -- pwm mode pwm output upon trnccr4 compare match pwm output upon trnccr5 compare match - pulse output upon a/d conversion trigger note free-running mode toggle output upon trnccr4 compare match toggle output upon trnccr5 compare match -- pulse width measurement mode ---- triangular wave pwm mode pwm output upon trnccr4 compare match pwm output upon trnccr5 compare match - pulse output upon a/d conversion trigger note high-accuracy t- p w m m o d e inverted phase output to torn3 pwm output (with dead time) upon trnccr3 compare match inverted phase output to torn5 pulse output upon a/d conversion trigger note pwm mode with dead time inverted phase output to torn3 pwm output (with dead time) upon trnccr3 compare match inverted phase output to torn5 pulse output upon a/d conversion trigger note
346 chapter 10 16-bit inverter timer/counter r user?s manual u16580ee2v0ud00 (a) torn7 pin output control the a/d conversion signals can be output to pin torn7. pin torn7 is set (to 1) by the trnadtrg0 signal trigger, and it is reset (to 0) by the trnadtrg1 signal trigger. if the trnadtrg0 trigger occurs while pin torn7 is set (to 1), its set (1) status is maintained. if the trnadtrg1 trigger occurs while pin torn7 is rese t (0), the (0) status is maintained. if the trnadtrg0 and trnadtrg1 signal triggers occur simultaneously, pin torn7 is reset (to 0). figure 10-28: torn7 pin output timing 1 remark: case 1: when trnccr4 < trnccr5 , trnopt2 = 04h, trnopt3 = 10h case 2: when trnccr4 < trnccr5 , trnopt2 = 04h, trnopt3 = 20h case 3: when trnccr4 < trnccr5 , trnopt2 = 08h, trnopt3 = 10h trnccr4 trnccr5 trnadt0 trnadt1 torn7 trncnt case 1 trnadt0 trnadt1 torn7 trnadt0 trnadt1 torn7 case 2 case 3
347 chapter 10 16-bit inverter timer/counter r user?s manual u16580ee2v0ud00 (2) interrupts in each mode the interrupts in each mode (inttrncc0 to inttrncc5, inttrnov, inttrner) are listed below. notes: 1. a compare match interrupt is output when the trndtc1 register is set to 000h. inttrncd can be used as the peak interrupt. 2. if set in the range of 0000h trnccrm < trndtc0, (trn ccr0 - trndtc1)< trnccrm trnccr0 (m = 1 to 5), no compare match interrupt is output. 3. if set to trnccr0 < trnccrm (m to 1 to 5), no compare match interrupt is output. remarks: 1. ? - ? in the table indicates inactive level output. 2. n = 0, 1 table 10-4: list of interrupts in each mode (1/2) operation mode inttrncc0 inttrncc1 inttrncc2 inttrncc3 interval mode trnccr0 compare match interrupt trnccr1 compare match interrupt trnccr2 compare match interrupt trnccr3 compare match interrupt external event count mode trnccr0 compare match interrupt trnccr1 compare match interrupt trnccr2 compare match interrupt trnccr3 compare match interrupt external trigger pulse output mode trnccr0 compare match interrupt trnccr1 compare match interrupt trnccr2 compare match interrupt trnccr3 compare match interrupt one-shot pulse mode trnccr0 compare match interrupt trnccr1 compare match interrupt trnccr2 compare match interrupt trnccr3 compare match interrupt pwm mode trnccr0 compare match interrupt trnccr1 compare match interrupt trnccr2 compare match interrupt trnccr3 compare match interrupt free-running mode trnccr0 compare match interrupt trnccr1 compare match interrupt trnccr2 compare match interrupt trnccr3 compare match interrupt pulse width measurement mode tir10 capture interrupt tir11 capture interrupt tir12 capture interrupt tir13 capture interrupt triangular wave pwm mode tir10 capture interrupt tir11 capture interrupt tir12 capture interrupt tir13 capture interrupt high-accuracy t-pwm mode trnccr0 compare match interrupt note 1 trnccr1 compare match interrupt note 2 trnccr2 compare match interrupt note 2 trnccr3 compare match interrupt note 2 pwm mode with dead time trnccr0 compare match interrupt trnccr1 compare match interrupt note 3 trnccr2 compare match interrupt note 3 trnccr3 compare match interrupt note 3
348 chapter 10 16-bit inverter timer/counter r user?s manual u16580ee2v0ud00 notes: 1. if set in the range of 0000h trnccrm < trndtc0, (trnccr0 - trndtc1) < trnccrm trnccr0 (m = 1 to 5), no compare match interrupt is output. 2. if set to trnccr0 < trnccrm (m = 1 to 5), no compare match interrupt is output. 3. if a setting error has been made for trnccr0, trndtc0, trndtc1, an overflow interrupt (inttrnov) is output. remarks: 1. ? - ? in the table indicates inactive level output. 2. n = 0, 1 table 10-4: list of interrupts in each mode (2/2) operation mode inttrncc4 inttrncc5 inttrnov inttrner interval mode trnccr4 compare match interrupt trnccr5 compare match interrupt -- external event count mode trnccr4 compare match interrupt trnccr5 compare match interrupt -- external trigger pulse output mode trnccr4 compare match interrupt trnccr5 compare match interrupt -- one-shot pulse mode trnccr4 compare match interrupt trnccr5 compare match interrupt -- pwm mode trnccr4 compare match interrupt trnccr5 compare match interrupt - error interrupt free-running mode trnccr4 compare match interrupt trnccr5 compare match interrupt overflow interrupt - pulse width measurement mode - - overflow interrupt - triangular wave pwm mode trnccr4 compare match interrupt trnccr5 compare match interrupt - error interrupt high-accuracy t-pwm mode trnccr4 compare match interrupt note 1 trnccr5 compare match interrupt note 1 overflow interrupt note 3 error interrupt pwm mode with dead time trnccr4 compare match interrupt note 2 trnccr5 compare match interrupt note 2 - error interrupt
349 chapter 10 16-bit inverter timer/counter r user?s manual u16580ee2v0ud00 (3) a/d conversion triggers, peak interrupts, and valley interrupts in each mode the a/d conversion triggers, peak interrupts, and valley interrupts in each mode are listed below. remarks: 1. the inttrncd interrupt and inttrnod interrupt are the occurrence conditions following interrupt thinning out. 2. n = 0, 1 table 10-5: list of a/d conversion triggers, peak interrupts and valley interrupts in each mode operation mode trnadtrg0 trnadtrg1 inttrncd inttrnod interval mode - - - - external event count mode ---- external trigger pulse output mode ---- one-shot pulse mode - - - - pwm mode select from interrupts inttrncd, inttrncc4, inttrncc5 select from interrupts inttrncd, inttrncc4, inttrncc5 peak interrupt at same timing as inttrncc0 interrupt - free-running mode - - - - pulse width measurement mode ---- triangular wave pwm mode select from interrupts inttrncd, inttrncc4, inttrncc5 select from interrupts inttrncd, inttrncc4, inttrncc5 - valley interrupt at counter valley (upon switching from down to up count) high-accuracy t-pwm mode select from interrupts inttrncd, inttrncc4, inttrncc5 select from interrupts inttrncd, inttrncc4, inttrncc5 peak interrupt valley interrupt at counter valley (upon switching from down to up count) pwm mode with dead time select from interrupts inttrncd, inttrncc4, inttrncc5 select from interrupts inttrncd, inttrncc4, inttrncc5 peak interrupt at same timing as inttrncc0 interrupt -
350 chapter 10 16-bit inverter timer/counter r user?s manual u16580ee2v0ud00 10.5 match interrupts match interrupts consist of compare match interrupts (inttrncc0 to inttrncc5), peak interrupts (inttrncd), and valley interrupts (inttrnod). for details about error interrupts, refer to 10.9 error interrupts . compare match interrupts (inttrncc0 to inttrnc c5) are interrupts that occur following a match between the trnccr0 to trnccr5 registers and the coun ter, and are output in all modes (no operation mode restrictions). peak interrupts (inttrncd) are output in the pwm mode, triangular wave pwm mode, high-accuracy t-pwm mode, and pwm mode with dead time. if the counter is a triangular wave operation mode (triangular wave pwm mode, high-accuracy pwm mode), a peak interrupt is output when the counter switches from up count to down count. if the counter is in a saw tooth wave operation mode (pwm mode, pwm mode with dead time), a peak interrupt occurs upon a match between the counter and the trnccr0 register (same timing as inttrncc0 interrupt). valley interrupts occur when the counter switches from down count to up count in the triangular wave pwm mode and high-accuracy t-pwm mode. figure 10-29: interrupt signal output example (1/2) i j k x = p d1 i j k i j k ffffh 0h trndtc0 trnccr0 trnccr1 trnccr2 trnccr3 k p (for cycle setting) i (u phase duty) j (v phase duty) k (w phase duty) trndtc0 d0 trndtc1 d1 x counter inttrncd0 (peak interrupt) inttrnod (valley interrupt) inttrncc1 inttrncc2 inttrncc3
351 chapter 10 16-bit inverter timer/counter r user?s manual u16580ee2v0ud00 figure 10-29: interrupt signal output example (2/2) p ffffh 0h trnccr0 trnccr1 trnccr2 trnccr3 p i j k p counter inttrncd0 (peak interrupt) inttrnod (valley interrupt) inttrncc1 inttrncc2 inttrncc3 trnccr3 l inttrncc0 inttrncc4
352 chapter 10 16-bit inverter timer/counter r user?s manual u16580ee2v0ud00 10.5.1 compare match interrupt related cautions (1) cautions in high-accuracy t-pwm mode compare match interrupts occur upon a match between the counter and a compare register (trnccr0 to trnccr5). however, in the high-accuracy t-pwm mode, the compare register can be set exceeding the counter?s count operation range. therefore, under the following conditions, no compare interrupt is output. ? restrictions related to compare match interrupt with trnccr0 register (inttrncc0) in the high-accuracy t-pwm mode, when trndtc1 000h, no compare match interrupt (inttrncc0) is output. (use inttrnod (valley interrupt) and inttrncd (peak interrupt) as the cycle interrupts.) ? restrictions related to tr nccr1 to trnccr3 register in the high-accuracy t-pwm mode, if set in the range of 0000h trnccrm < trndtc0, (trnccr0 - trndtc1) < trnccrm trnccr0, no interrupt occu rs upon a match between the compare value and the counter. remark: m = 1 to 3 ? restrictions related to tr nccr4 and trnccr5 registers in the high-accuracy t-pwm mode, if set in the range of 0000h trnccr4, trnccr5 < trndtc0, (trnccr0 - trndtc1) < trnccr4, trnccr5 trnccr0, no compare match interrupt is output since no match between the compare value and counter occurs. when trnccr4 and trnccr5 registers are used as trigger causes for a/d triggers, perform setting in the range of trndtc0 trnccr4, trnccr5 (trnccr0 - trndtc1). trncnt trnsbc 0000h trndtc0 trnccr0 -trndtc1 trnccr0 trnccrm setting range in which no inttrncc1m interrupt occurs trnccrm setting range in which inttrncc1m interrupt occurs trnccrm setting range in which no inttrncc1m interrupt occurs trncnt trnsbc 0000h trndtc0 trnccr0 -trndtc1 trnccr0 setting range of trnccr4 or trnccr5, in which inttrncc4 or inttrncc5 interrupts occur
353 chapter 10 16-bit inverter timer/counter r user?s manual u16580ee2v0ud00 (2) cautions in pwm mode with dead time compare match interrupts are output upon a match between the counter and compare registers (trnccr0 to trnccr5). however, in the high-a ccuracy t-pwm mode, the compare register can be set exceeding the counter?s count operation range. therefore, under the following conditions, no compare interrupt is output. ? restrictions rela ted to trnccrm in the pwm mode with dead time, if setting is performed in the following range, no match between the compare value and counter occurs, and no compare match interrupt is output: when trnccr0 < trnccrm (trnccr0 + trndtc0), trnccr4, trnccr5 registers are used as trigger causes for a/d triggers, perform settings with trnccr4, trnccr5 trnccr0. remark: m = 1 to 5 trncnt trnsbc 0000h trnccr0 +trndtc0 trnccr0 setting range in which inttrnccm interrupts are not output setting range in which inttrnccm interrupts are output
354 chapter 10 16-bit inverter timer/counter r user?s manual u16580ee2v0ud00 10.6 flags 10.6.1 up count flags timer rn has two counters, a counter and a sub-counter. trncuf is the counter?s up/down status flag. it operates in the triangular wave pwm mode and high- accuracy t-pwm mode, and is fixed to 0 in all other modes. trnsuf is the sub-counter?s up/down status flag. it operates in the high-accuracy t-pwm mode, and is fixed to 0 in all other modes. for both trncuf and trnsuf, 0 indicates the up count status, and 1 indicates the down count status. figure 10-30: up count flags timings (1/2) in the triangular wave pwm mode, the values of trncuf are as follows. 0 counter < trnccr0+1 0 (up count) trnccr0+1 counter > 0 1 (down count) in the high-accuracy t-pwm mode, the values of trncuf/trnsuf are as follows. [trncuf] trndtc0 counter < (trnccr0 - trndtc1) 0 (up count) trnccr0-trndtc1 counter > trndtc0 1 (down count) [trnsuf] 0 sub-counter < trnccr0 0 (up count) trnccr0 sub-counter > 0 1 (down count) x = p d1 fffeh 0h trndtc0 x counter trncuf trnsuf sub-counter trnccr0
355 chapter 10 16-bit inverter timer/counter r user?s manual u16580ee2v0ud00 figure 10-30: up count flags timings (2/2) 10.6.2 normal phase/inverted phase simultaneous active detection flag timer rn has a flag (trntbf) that detects normal phase/inverted phase simultaneous active states. the trntbf flag is valid in the pwm mode, triangular wave pwm mode, high-accuracy t-pwm mode, and pwm mode with dead time. figure 10-31: normal phase/inverted phase simultaneous active detection flag timing trncuf torn0 trnsuf torn0 tsnccr0 0000h counter sub-counter trndtc0 trntos = 1 sub-counter up/down status output to torn0 trntos = 0 sub-counter up/down status output to torn0 trnccr0- trndtc1 counter torn1 torn2 trntba0 ?1? trntbf set after 1 base clock 0 write clear torn1 torn2 trntba0 ?1? set after 1 base clock 0 write clear trntbf inttrner inttrner
356 chapter 10 16-bit inverter timer/counter r user?s manual u16580ee2v0ud00 10.6.3 reload hold flag in the case of timer rn, the reload hold flag (trnrsf) is set to ?1? upon occurrence of a reload request (when the trnccr1 register is written to). when reload occurs and the values are transferred to all the buffer registers, the reload hold flag is cleared to ?0?. the trnrsf flag is valid in the following operation modes. ? external trigger pulse output mode ? pwm mode ? triangular wave pwm mode ? high-accuracy t-pwm mode (trncms = 0) ? pwm mode with dead time caution: the trnrsf flag is set to ?1? following the lapse of 4 base clocks after trnccr1 reg- ister write completion. figure 10-32: reload hold flag timings x y x y trnccr1 trnccr1 buffers trnrsf reload timing x y x y trnccr1 trnccr1 buffers trnrsf reload timing trnccr1 trnccr1 buffers trnrsf x y x y reload timing reload thinning out period
357 chapter 10 16-bit inverter timer/counter r user?s manual u16580ee2v0ud00 10.7 interrupt thinning out function the operations related to the interrupt thinning out function are indicated below. ? the interrupts subject to thinning out are inttrncd (peak interrupt) and inttrnod (valley interrupt). ? trnopt1 register bit trnice is used to enable inttrncd interrupt output and to specify thinning out count targets. ? trnopt1 register bit trnioe is used to ena ble inttrnod interrupt output and to specify thinning out count targets. ? trnopt2 register bit trnrde is used to specify reload thinning yes/no. ? if thinning out yes is specified, reload is executed at the same timing as interrupt output following thinning out. ? if thinning out no is specified, reload is execut ed at the reload timing after write access to the trnccr1 register. ? the reload/anytime rewrite method can be specified with trnopt0 register bit trncms. ? when trncms = 0, the register value is updated in synchronization with reload, but when trncms = 1, the register value is updated immediately after write access. caution: when write access is performed to the trnopt1 register, the internal thinning out counter is cleared when the register value is updated. therefore, the interrupt interval may temporarily become longer than expected. to prevent this, it is recommended to set trncsm = 0 and trnrde = 1, and to change the interrupt thinning out count with the reloaded setting according to interrupt thinning out. using this method, the interrupt interval is kept the same as the setting value.
358 chapter 10 16-bit inverter timer/counter r user?s manual u16580ee2v0ud00 10.7.1 operation of interrupt thinning out function figure 10-33: interrupt thinning out operations (1/2) (a) when trnice = 1, trnioe = 1 (peak/valley interrupt output) trnid4-0 = 00h (no th inning out ) trnid4-0 = 01h (mask 1 ) trnid4-0 = 02h (mask 2 ) trnid4-0 = 03h (mask 3 ) trnid4-0 = 04h (mask 4 ) trnid4-0 = 05h (mask 5 ) trnid4-0 = 06h (mask 6 ) counter inttrncd inttrnod inttrncd inttrnod inttrncd inttrnod inttrncd inttrnod inttrncd inttrnod inttrncd inttrnod inttrncd inttrnod
359 chapter 10 16-bit inverter timer/counter r user?s manual u16580ee2v0ud00 figure 10-33: interrupt thinning out operations (2/2) (b) when trnice = 1, trnioe = 0 (peak interrupt only output) (c) when trnice = 0, trnioe = 1 (valley interrupt only output) counter trnid4-0 = 00h (no th inning out ) inttrncd inttrnod trnid4-0 = 01h (mask 1) inttrncd inttrnod trnid4-0 = 02h (mask 2) inttrncd inttrnod trnid4-0 = 03h (mask 3) inttrncd inttrnod trnid4-0 = 04h (mask 4) inttrncd inttrnod counter trnid4-0 = 00h (no t hinni ng out) inttrncd inttrnod trnid4-0 = 01h (mask 1) inttrncd inttrnod trnid4-0 = 02h (mask 2) inttrncd inttrnod trnid4-0 = 03h (mask 3) inttrncd inttrnod trnid4-0 = 04h (mask 4) inttrncd inttrnod
360 chapter 10 16-bit inverter timer/counter r user?s manual u16580ee2v0ud00 10.7.2 operation examples when peak interrupts and valley interrupts occur alternately (1) register settings set both trnopt1 register bit trnice and trnopt1 register bit trnioe to 1. (2) operation example figure 10-34: examples when peak interrupts and valley interrupts occur alternately (1/2) (a) when trncms = 0, trnrde = 1 (reload thi nning out control) (recommended settings) (b) when trncms = 0, trnrde = 0 (no reload control) counter inttrncd inttrnod trnids4 to 0 trnid4 to 0 reloa d* clear interrupt thinning out counter * reload is executed at the thinned out interrupt output timing. all other reload timings are ignored. 00 01 02 02 04 00 01 02 02 04 00 01 02 03 04 00 01 02 03 04 counter inttrncd inttrnod trnids4 to 0 trnid4 to 0 relo ad * interrupt thinning out counter clear * reload is executed at the reload timing after rewrite. 00 01 02 02 04 00 01 02 00 04 00 01 02 03 04 00 01 02 03 04
361 chapter 10 16-bit inverter timer/counter r user?s manual u16580ee2v0ud00 figure 10-34: examples when peak interrupts and valley interrupts occur alternately (2/2) (c) when trncms = 1, trnrde = x (anytime rewrite) 10.7.3 interrupt thinning out function during counter saw tooth wave operation the operations related to the interrupt thinning out function during counter saw tooth wave operation (pwm mode, pwm mode with dead time) are indicated below. ? the interrupt subject to thinning out is inttrncd (peak interrupt). the saw tooth wave operation occurs upon a matc h between the trnccr0 regi ster and counter occurs. ? trnopt1 register bit trnice is used to enable inttrncd interrupt output and to specify thinning out count targets. ? the trnopt1 register bit trnioe setting is in valid. inttrnod interrupt output is prohibited. ? trnopt1 register bit trnrde is used to specify reload thinning out yes/no. ? if thinning out yes is specified, reload is executed at the same timing as interrupt output following thinning out. ? if thinning out no is specified, reload is execut ed at the reload timing after write access to the trnccr1 register. caution: when write access is performed to the trnopt1 register, the internal thinning out counter is cleared when the register value is updated. therefore, the interrupt interval may temporarily become longer than expected. to prevent this, it is recommended to set trncsm = 0 and trnrde = 1, and to change the interrupt thinning out count with the reloaded setting according to interrupt thinning out. using this method, the interrupt interval is kept the same as the setting value. counter inttrncd inttrnod trnids4 to 0 trnid4 to 0 instantly reflected interrupt thinning out counter clear * instantly reflected after rewrite. the reload timing is ignored. * the clear timing is transfer to the buffer, not register rewrite. 00 01 02 02 04 00 01 02 03 04 00 01 02 00 04 00 01 02 03 04
362 chapter 10 16-bit inverter timer/counter r user?s manual u16580ee2v0ud00 10.8 a/d conversion trigger function this section describes the operation of the a/d conversion triggers output in the pwm mode, triangular wave pwm mode, high-accuracy t-pwm mode, and pwm mode with dead time. in these modes, the trnccr4 and trnccr5 registers are used as match interrupts and for the a/d conversion trigger function, with no influence on timer outputs in terms of the compare operation. for the a/d conversion triggers that can be output in each mode, refer to 10.4.3 (3) a/d conversion triggers, peak inter- rupts, and valley interrupts in each mode . figure 10-35: a/d conversion trigger output controller the above figure shows the a/d conversion trigger controller. as shown in this figure, it is possible to select and perform or output of compare match interrupts (inttrncc5, inttrncc4) and peak interrupts (inttrncd), valley interrupts (inttrnod) interrupt signals, sub-counter peak timing, and sub-counter valley timing. in the case of timer r, there are two identical a/d conversion trigger controllers, and each one can be controlled independently. trnadtrg0 trncuf inttrncc5 trncuf inttrncc4 inttrnod inttrncd0 trnat [05 04 03 02 01 00] trnadtrg1 trnat [15 14 13 12 11 10] s r torn7 peak of trncnt valley of trncnt thinning out circuit thinning out circuit trnice trnioe
363 chapter 10 16-bit inverter timer/counter r user?s manual u16580ee2v0ud00 10.8.1 a/d conversion trigger operation timer r has a function for generating a/d conversion start triggers (trnadtrg0, trnadtrg1 signals), freely selecting 4 trigger sources. the following 4 triggers sources are provided, which can be specified with trnopt2 register bits trnat05 to trnat00 and trnopt3 register bits trnat15 to trnat10. here, control of the trnadtrg0 using trnat05 to trnat00 is described. the same type of control can be achieved for the trnadtrg1 signal with control bits trnat15 to trnat10 (1) trnadtrg0 signal output control ? trnopt2 register trnat00 = 1: output of a/d conversion trigger upon valley interrupt (inttrnod) output ? trnopt2 register trnat01 = 1: output of a/d conversion trigger upon peak interrupt (inttrncd) output ? trnopt2 register trnat02 = 1: a/d conversion trigger outputtable upon compare match interrupt (inttrncc4) during counter up count ? trnopt2 register trnat03 = 1: a/d conversion trigger outputtable upon compare match interrupt (inttrncc4) during counter down count ? trnopt2 register trnat04 = 1: a/d conversion trigger outputtable upon compare match interrupt (inttrncc5) during counter up count ? trnopt2 register trnat05 = 1: a/d conversion trigger outputtable upon compare match interrupt (inttrncc5) during counter down count the a/d conversion start trigger signals selected with bits trnat05 to trnat00 are all o red and output to the trnadtrg0 pin. the peak and valley interrupts (inttrnod, inttrncd) selected with bits trnat00 and trnat01 are the signals after interrupt thinning out. therefore, they are output at the timing when interrupt thinning out control is received, and when interrupt output enable (bits trnice and trnioe) is not enabled, neither is any a/d conversion start trigger output. moreover, trnopt2 register bits trnat05 to trnat00 can be rewritten during operation. when the a/d conversion start trigger setting bit is rewritten during operation, this is instantly reflected to the output status of the a/d conversion start trigger. these control bits do not have a reload function and are write accessed only in the anytime write mode.
364 chapter 10 16-bit inverter timer/counter r user?s manual u16580ee2v0ud00 figure 10-36: a/d conversion trigger timings (1/2) (a) when trnice = 1, trnioe = 1, trni d4-trnid0 = 00h (no interrupt thinning out) [when trnat05 to 00 = 100100] perform ored output o inttrncc4 and inttrncc5 ? setting at which a/d conversion start trigger is output for both up/down count upon match interrupt [when trnat05 to 00 = 000010] output inttrncd [when trnat05 to 00 = 000100] output inttrncc4 during up count [when trnat05 to 00 = 001000] output inttrncc4 during down count [when trnat05 to 00 = 010000] output inttrncc5 during up count [when trnat05 to 00 = 100000] output inttrncc5 during down count [when trnat05 to 00 = 000011] ? setting at which a/d conversion start trigger is output for both peaks and valleys [when trnat05 to 00 = 000001] output inttrnod counter inttrncd inttrnod trnadtrg0 inttrncc4 inttrncc5 trncuf trnadtrg0 trnadtrg0 trnadtrg0 trnadtrg0 trnadtrg0 trnadtrg0 trnadtrg0
365 chapter 10 16-bit inverter timer/counter r user?s manual u16580ee2v0ud00 figure 10-36: a/d conversion trigger timings (2/2) (b) when trnice = 0, trnioe = 1, trnid4 to trnid0 = 02h (interrupt thinning out) (c) 0 when trnice = 0, trnioe = 1, trnid4 to trnid0 = 02h (interrupt thinning out) (2) cautions related to a/d conversion triggers ? in the pwm mode and pwm mode with dead time, no valley interrupt (inttrnod) is output. only peak interrupts (inttrncd) are valid. counter inttrncd inttrnod [when trnat05-00 = 000011] both inttrncd and inttrnod are selected, but peak not output due to interrupt thinning out specifica tion. trnadtrg0 counter inttrncd inttrnod [when trnat05-00 = 000101] ? inttrncd is thinned out, but inttrncc4 is not. trnadtrg0 inttrncc4 inttrncc5 trncuf
366 chapter 10 16-bit inverter timer/counter r user?s manual u16580ee2v0ud00 10.9 error interrupts 10.9.1 error interrupt and error signal output functions timer r has an error interrupt (inttrner) and an error signal output (trner). as the errors detected with timer r, normal phase/inverted phase simultaneous active (fault of dead time controller) are detected as errors in the high-accuracy t-pwm mode, pwm mode with dead time, and pwm mode. regarding normal phase/inverted phase simultaneous active errors, following error occurrence, the error occurrence can be confirmed by reading bit trntbf of the trnopt6 register. moreover, detection on/off switching control in each phase (torn1/torn2, torn3/torn4, torn5/ torn6) is possible using bits trntba2 to trntba0 of the trnioc4 register. the possibility of normal phase/in verted phase simultaneous active error detection in each mode is indicated below. remark: : error detection possible : error detection not possible figure 10-37: error interrupt (inttrner) an d error signal (trner) output controller output of the error signal (trner) due to normal phase/inverted phase simultaneous active error is active level during detection of normal phase/inverted phase simultaneous active. mode normal phase/inverted phase simultaneous active detection interval mode external event count mode external trigger pulse output mode one-shot pulse mode pwm mode free-running mode pulse width measurement mode triangular wave pwm mode high-accuracy t-pwm mode pwm mode with dead time trnce trneoc torn1 trnol1 torn2 trnol2 trnol3 trnol4 torn5 trnol5 torn6 trnol6 trner trntba [2 1 0] inttrner error detection possible mode torn3 torn4
367 chapter 10 16-bit inverter timer/counter r user?s manual u16580ee2v0ud00 (1) in pwm mode the case of normal phase/inverted phase simultaneous active in the pwm mode is described below. as shown in the figure below, an error interrupt (inttrner) is output when the trnccr1 and trnccr2 registers are set so that pins torn1 an d torn2 simultaneously output ?h?. similarly, an error interrupt (inttrner) is output when the trnccr3 and trnccr4 registers are set so that pins torn3 and torn4 simultaneously output ?h?. figure 10-38: error interrupt and error signal output controller in pwm mode if the output active level is switched by manipulating trnioc0 register bits trnol1 and trnol2, the following results. torn1 torn2 torn3 torn4 trnccr2 trnccr3 trnccr1 trnccr4 trnccr0 inttrner trnccr2 trnccr3 trnccr1 trnccr4 trnccr2 trnccr3 trnccr1 trnccr4 trnccr1 trnccr4 trnccr2 trnccr3 trnccr2 trnccr3 when trnol1 = 0, trnol2 = 0 trncnt torn1 torn2 when trnol1 = 1, trnol2 = 0 trncnt torn1 torn2 when trnol1 = 0, trnol2 = 1 trncnt torn1 torn2 when trnol1 = 1, trnol2 = 1 trncnt torn1 torn2 inttrner inttrner inttrner inttrner
368 chapter 10 16-bit inverter timer/counter r user?s manual u16580ee2v0ud00 (2) in triangular wave pwm mode the case of normal phase/inverted phase simultaneous active in the triangular wave pwm mode is described below. as shown in the figure below, an error output (inttrner) is output when the trnccr0 and trnccr1 registers are set so that pins torn1 and torn2 simultaneously output ?h?. similarly, an error interrupt (inttrner) is output when the trnccr3 and trnccr4 registers are set so that pins torn3 and torn4 simultaneously output ?h?. figure 10-39: error interrupt and error signal output controller in triangular wave pwm mode torn1 torn2 torn3 torn4 inttrner trnccr2 trnccr3 trnccr1 trnccr4 trnccr1 trnccr4 trnccr2 trnccr3 trnccr1 trnccr4
369 chapter 10 16-bit inverter timer/counter r user?s manual u16580ee2v0ud00 (3) in high-accuracy t-pwm mode/pwm mode with dead time in the high-accuracy t-pwm mode and pwm mode with dead time, no error occurs except when the dead time setting is ?0?. if an error occurs, this is likely due to an internal circuit fault. figure 10-40: error interrupt and error signal output controller in high-accuracy t-pwm mode / pwm mode with dead time torn1 torn2 inttrner trntbf ?l? counter a glitch may occur during normal phase/inverted phase switching. the detection flag (trntbf) is not set. torn1 torn2 inttrner trntbf ?l? counter a glitch may occur during normal phase/inverted phase switching. the detection flag (trntbf) is not set.
370 chapter 10 16-bit inverter timer/counter r user?s manual u16580ee2v0ud00 10.10 operation in each mode 10.10.1 interval timer mode (1) outline of interval timer mode in the interval timer mode, a compare match interrupt (inttrncc0) occurs and the counter is cleared upon a match between the setting value of the trnccr0 register and the counter value. the occurrence interval for this counter and trnccr0 register match interrupt becomes the interval time. in the interval timer mode, the counter is cleared only upon a match between the counter and the value of the trnccr0 register. counter clearing using the trnccr1 to trnccr5 registers is not performed. however, the setting values of the trnccr1 to trnccr5 registers are co mpared to the counter values transferred to the trnccr1 to trnccr5 buffer registers and compare match interrupts (inttrncc1 to inttrnccr5) are output. the trnccr0 to trnccr5 registers can be rewri tten using the anytime write method, regardless of the value of bit trnce. pins torn0 to torn7 are toggle output controlled when bits trnoe0 to trnoe7 are set to 1. figure 10-41: basic operation fl ow in interval timer mode note: in the case of a match betwee n the counter and trnccr1 to trnccr5 registers, the counter is not cleared. start initial settings ? clock selection (trnctl0: trncks2 to trncks0) ? interval mode setting (trnctl1: trnmd3 to trnmd0 = 0000) ? compare register setting (trnccr0 to trnccr5) timer operation enable (trnce = 1) transfer of trnccr0 to trnccr5 values to trnccr0 to trnccr5 buffers match between counter and trnccr1 to trnccr5 buffer values note match between counter and trnccr0 buffer value, counter clear & start inttrncc1 to inttrncc5 occurrence inttrncc0 occurrence
371 chapter 10 16-bit inverter timer/counter r user?s manual u16580ee2v0ud00 chapter 10 16-bit inverter timer/counter r (2) interval timer mode operation list (a) compare registers (b) input pins (c) output pins (d) interrupts register rewrite method rewrite during operation function trnccr0 reload possible compare value trnccr1 to trnccr3 reload possible compare value trnccr4, trnccr5 reload possible compare value pin function tir1m - (m = 0 to 3) ttrgr1 - tevtr1 - pin function tornm toggle output upon trnccrm register compare match (m = 0 to 5) torn6, torn7 - interrupt function inttrnccm trnccrm register compare match (m = 0 to 5) inttrnov - inttrner -
372 chapter 10 16-bit inverter timer/counter r user?s manual u16580ee2v0ud00 figure 10-42: basic timing in interval timer mode (1/2) (a) when d1>d2>d3, only value of trnccr0 register is rewritten, torn0 and torn1 are not output (trnoe0, 1 = 0, trnol0 = 0, trnol1 = 1) remarks: 1. d1, d2: setting values of trn ccr0 register (0000h to ffffh) d3: setting values of trnccr1 register (0000h to ffffh) 2. interval time = (dm + 1) (count clock cycle) 3. m = 1 to 3, n = 0, 1 counter d1 d 2 inttrncc0 d1 d2 d1 ffffh trnccr1 d3 d3 d3 inttrncc1 trnccr0 d3 trnce a: interval time (d1 + 1) count clock a a b torn0 torn1 low high a: interval time (d2 + 1) count clock
373 chapter 10 16-bit inverter timer/counter r user?s manual u16580ee2v0ud00 figure 10-42: basic timing in interval timer mode (2/2) (b) when d1 = d2, values of trnccr0 and trnccr1 registers not rewritten, torn1 output performed (trnoe0, 1 = 1, trnol0 = 0, trnol1 = 1) remarks: 1. d1: setting value of trnccr0 register (0000h to ffffh) d2: setting value of trnccr1 register (0000h to ffffh) 2. interval time = (dm + 1) (count clock cycle) 3. torn0, torn1 toggle time = (dm + 1) (count clock cycle) 4. m = 1, 2, n = 0, 1 counter d1 inttrncc0 d1 = d2 ffffh trnccr1 inttrncc1 trnccr0 d2 trnce d1 = d2 d1 = d2 interval time interval time interval time torn0 torn1
374 chapter 10 16-bit inverter timer/counter r user?s manual u16580ee2v0ud00 10.10.2 external event count mode (1) outline of external event count mode in the external event count mode, count up starts upon external event input (tevtrn pin). (the external event input (tevtrn) is used as the count clock, regardless of bit trneee of the trnctl1 register.) in the external event count mode, the counter is cleared only upon a match between the counter and the value of the trnccr0 register. coun ter clearing us ing the trnccr1 to trnccr5 registers is not performed. however, the values of the trnccr1 to trnccr5 registers are transferred to the trnccr1 to trnccr5 buffer registers, compared to the counter value, and compare match interrupts (inttrncc1to intrnccr5) are output. the trnccr0 to trnccr5 registers can be rewritten with t he anytime write me thod, regardless of the value of bit trnce. pins torn0 to torn7 are toggle output controlled when bits trnoe0 to trnoe7 are set to 1. when using only one co mpare register channel, it is re commended to set the trnccr1 to trnccr5 registers to ffffh. [external event count operation flow] <1> trnctl1 register bits trnmd3 to trnmd0 = 0001b (mode setting) edge detection set with tr nioc2 register bits trnees1 and trnees0 (trnees1, trnees0 = settin g other than 00b) <2> trnctl0 register bit trnce = 1 (count enable) <3> tevtrn pin input edge detection (count-up start) cautions: 1. in the case of the external event count mode, when the setting value of the trnccr0 register is set to m, the number of tevtrn pin input edge detection times is m+1. 2. do not set the value of the trnccr0 register to 0000h in external event count mode. remark: n = 0, 1
375 chapter 10 16-bit inverter timer/counter r user?s manual u16580ee2v0ud00 (2) external event count mode operation list (a) compare registers (b) input pins (c) output pins (d) interrupts register rewrite method rewrite during operation function trnccr0 anytime rewrite possible compare value trnccr1 to trnccr3 anytime rewrite possible compare value trnccr4, trnccr5 anytime rewrite possible compare value pin function tir1m - (m = 0 to 3) ttrgr1 - tevtr1 - pin function tornm toggle output upon trnccrm register compare match (m = 0 to 5) torn6, torn7 - interrupt function inttrnccm trnccrm register compare match (m = 0 to 5) inttrnov - inttrner -
376 chapter 10 16-bit inverter timer/counter r user?s manual u16580ee2v0ud00 figure 10-43: basic operation timing in external event count mode (1/4) (a) when d1>d2>d3, only value of trnccr0 register is rewritten, torn0 and torn1 are not output. the signal input from tevtrn and internally synchronized is counted as the count clock (trnoe0, 1 = 0, trnol0 = 0, trnol1 = 1) remarks: 1. d1, d2: setting values of trn ccr0 register (0000h to ffffh) d3: setting value of trnccr1 register (0000h to ffffh) 2. number of event counts = (dm + 1) (m = 1, 2) 3. n = 0, 1 counter d1 d 2 inttrncc0 d1 d2 d1 ffffh trnccr1 d3 d3 d3 inttrncc1 trnccr0 d3 trnce torn0 torn1 low high tevtrn
377 chapter 10 16-bit inverter timer/counter r user?s manual u16580ee2v0ud00 figure 10-43: basic operation timing in external event count mode (2/4) (b) when d1 = d2, trnccr0 and trnccr1 register values are not rewritten, torn0 and torn1 are output (trnoe0, 1 = 1, trnol0 = 0, trnol1 = 1) remarks: 1. d1: setting value of trnccr0 register (0000h to ffffh) d2: setting value of trnccr1 register (0000h to ffffh) 2. number of event counts = (dm + 1) (m = 1, 2) 3. n = 0, 1 c ounter d1 inttrncc0 d1 = d2 ffffh t rnccr1 inttrncc1 t rnccr0 d2 t rnce d1 = d2 d1 = d2 t orn0 t orn1 t evtrn
378 chapter 10 16-bit inverter timer/counter r user?s manual u16580ee2v0ud00 figure 10-43: basic operation timing in external event count mode (3/4) (c) when d1 = d2, trnccr0 and tr nccr1 register values are not rewritten, torn0 and torn1 are output (trnoe0, 1 = 1, trnol0 = 0, trnol1 = 1) remarks: 1. d1: setting value of trnccr0 register (0000h) d2: setting value of trnccr1 register (0000h) 2. number of event counts = (dm + 1) (m = 1, 2) 3. n = 0, 1 c ounter 0000h inttrncc0 ffffh trnccr1 inttrncc1 trnccr0 0000h trnce torn0 torn1 0000h
379 chapter 10 16-bit inverter timer/counter r user?s manual u16580ee2v0ud00 figure 10-43: basic operation timing in external event count mode (4/4) (d) when d1 = d2, trnccr0, trnccr1 register values are not rewritten, torn0 and torn1 are output (trnoe0, 1 = 1, trnol0 = 0, trnol1 = 1) remarks: 1. d1: setting value of tr nccr0 register (0001h) d2: setting value of tr nccr1 register (0000h) 2. number of event counts = (dm + 1) (m = 1, 2) 3. n = 0, 1 counter inttrncc0 ffffh trnccr1 inttrncc1 trnccr0 trnce torn0 torn1 0001h 0001h 0000h
380 chapter 10 16-bit inverter timer/counter r user?s manual u16580ee2v0ud00 10.10.3 external trigger pulse output mode (1) outline of external trigger pulse output mode when, in the external trigger pulse mode, the du ty is set to the trnccr1 to trnccr5 registers, the cycle is set to the trnccr0 register, and tr nce = 1 is set, external trigger input (ttrgrn pin) wait results, with the counter remaining stopped at ffffh. upon detection of the valid edge of external trigger input (ttrgrn pin), or when the trnest bit of the trnctl1 register is set, count up starts. an external trigger pulse is output from pins torn1 to torn5, and toggle output is performed from pin torn0 upon a match with the trnccr0 register. moreover, during the count operation, upon a match between the counter and the trnccr0 register, a compare match interrupt (inttrncc0) is output, and upon a match between the counter and trnccr1 to trnccr5 registers, compare match interrupts (inttrncc1 to inttrncc5) are output. the trnccr0 to trnccr5 registers can be rewritten during count operation. compare register reload is performed at the timing when the counter value and the trnccr0 register match. however, when write access to the trnccr1 register is performed, the next reload timing becomes valid, so that even if wishing to rewrite only the value of the trnccr0 register, write the same value to the trnccr1 register. in this ca se, reload is not performed even if only the trnccr0 register is rewritten. if, during operation in the external trigger pulse output mode, the external trigger (ttrgrn pin) edge is detected several times, or if the trnest bit of the trnctl1 register is set (to 1), the counter is cleared and count up is resumed. moreover, if at this time, the torn1 to torn5 pins are in the low level status, the torn1 to torn5 pin outputs become high level when an external trigger is input. if the torn1 pin is in the high le vel status, it remains high level even if external trigger input occurs. in the external trigger pulse output mode, the trnccr0 to trnccr3 registers have their function fixed as compare registers, so the capture function cannot be used. remark: n = 0, 1 caution: in the external trigger pulse mode, se t bit trneee of the trnc tl1 register to 0.
381 chapter 10 16-bit inverter timer/counter r user?s manual u16580ee2v0ud00 (2) external trigger pulse output mode operation list (a) compare registers (b) input pins (c) output pins (d) interrupts register rewrite method rewrite during operation function trnccr0 reload possible cycle trnccr1 to trnccr3 reload possible duty trnccr4, trnccr5 reload possible duty pin function tir1m - (m = 0 to 3) ttrgr1 counter clear & start through external trigger input tevtr1 timer count through external event count input pin function torn0 toggle output upon trnccr0 register compare match or external trigger input tornm external trigger pulse waveform output (m = 1 to 5) torn6, torn7 - interrupt function inttrnccm trnccrm register compare match (m = 0 to 5) inttrnov - inttrner -
382 chapter 10 16-bit inverter timer/counter r user?s manual u16580ee2v0ud00 figure 10-44: basic operation flow in external trigger pulse output mode note: the counter is not cleared upon a match betw een the counter and the trnccr1 to trnccr5 buffer register. remark: n = 0, 1 start match between counter and trnccr1 to trnccr5 external trigger (ttrgrn pin) input counter starts counting. ittrncc0 occurrence counter clear & start initial settings timer operation enable (trnce = 1) transfer of values of trnccr0 to trnccr5 to buffers trnccr0 to trnccr5 match between counter and trnccr0, counter clear & start external trigger (ttrgrn pin) input ? clock selection (trnctl1: trneee = 0) (trnctl0: trncks2 to trncks0) ? external trigger pulse output mode setting (trnctl1: trnmd3 to trnmd0 = 0010) ? compare register setting (trnccr0 to trnccr5) ittrncc1 to ittrncc5 occurrence note
383 chapter 10 16-bit inverter timer/counter r user?s manual u16580ee2v0ud00 figure 10-45: basic operation timing in external trigger pulse output mode (a) when values of trnccr0 and trnccr1 registers are rewritten, torn0 and torn1 are output (trnoe0, 1 = 1, trnol0, 1 = 0) remarks: 1. d01, d02: setting values of tr nccr0 register (0000h to ffffh) d11, d12: setting values of tr nccr1 register (0000h to ffffh) 2. torn1 (pwm) duty = (setting value of trnccr1 register) (count clock cycle) torn1 (pwm) cycle = (setting value of trnccr0 register + 1) (count clock cycle) 3. pin torn0 is toggled when the counter is cleared immediately following count start. 4. n = 0, 1 counter trnccr1 ffffh trnccr0 buffer buffer trnccr0 trnce external trigger (ttrgrn pin) d 01 d 02 d 01 d 02 d 01 d 02 d 11 d 11 0000h 0000h d 12 d 12 torn0 torn1 toggle output d 11 d 12 toggle output trnrsf flag trnccr1
384 chapter 10 16-bit inverter timer/counter r user?s manual u16580ee2v0ud00 10.10.4 one-shot pulse mode (1) outline of one-shot pulse mode when, in the one-shot pulse mode, the duty is set to the trnccr0 register, the output duty delay value is set to the trnccr1 to trnccr5 registers, and bit trnce of the trnctl0 register is set to 1, external trigger input (ttrgrn pin) wait results, with the counter remaining stopped at ffffh. upon detection of the valid edge of external trigger input (ttrgrn pin), or when bit trnest of the trnctl0 register is set to 1, count up starts. the torn1 to torn5 pins become high level upon a match between the counter and trnccr1 to trnccr5 registers. moreover, upon a match between the counter and trnccr0 register, the torn1 to torn5 pins become low level, and the counter is cleared to 0000h and then stops. the torn0 pin performs toggle output during the count operation upon a match between the counter and the trnccr0 buffer register. moreover, upon a match between the counter and trnccr0 register during count operation, a compare match interrupt (inttrncc0) is output, and upon a match between the counter and trnccr1 to trnccr5 buffer registers, compare match interrupts (inttrncc1 to inttrnccr5) are output. the trnccr0 and trnccr1 registers can be rewritten using the an ytime write method, regardless of the value of bit trnce. even a trigger is input during the counter operation, it is ignored. be sure to input the second trigger when the counter is stopped at 0000h. in the one-shot pulse mode, registers trnccr0 to trnccr3 have their function fixed as compare registers, so the capture function cannot be used. [one-shot pulse operation flow] <1> trnctl1 register bits trnmd3 to trnmd0 = 0011b (one-shot pulse mode) <2> trnccr0 register setting (duty setting ), trnioc0 register bit trnoe1 = 1 (torn1 pin output enable) <3> trnctl0 register bit trnce = 1 (counter operation enable):torn1 = low-level output <4> trnctl1 register bit trnest = 1 or ttrgrn pin edge detection (count-up start): torn1 = low-level output <5> match between counter value and trnccr1 buffer register: torn1 = high-level output <6> match between counter value and trnccr0 buffer register:torn1 = low-level output, count clear <7> count stop: torn1 = low-level output <8> trnce = 0 (operation reset) <9> <1> to <2> can be in any order. caution: in the one-shot pulse mode, set bi t trneee of the trnctl1 register to 0.
385 chapter 10 16-bit inverter timer/counter r user?s manual u16580ee2v0ud00 (2) one-shot pulse mode operation list (a) compare registers (b) input pins (c) output pins (d) interrupts register rewrite method rewrite during operation function trnccr0 anytime rewrite possible cycle trnccr1 to trnccr3 anytime rewrite possible output delay value trnccr4, trnccr5 anytime rewrite possible output delay value pin function tir1m - (m = 0 to 3) ttrgr1 - tevtr1 - pin function torn0 active at count start, inac tive upon trnccr0 register match tornm active upon trnccrm register match, inactive upon trnccr0 register match (m = 1 to 5) torn6, torn7 - interrupt function inttrnccm trnccrm register compare match inttrnov - inttrner -
386 chapter 10 16-bit inverter timer/counter r user?s manual u16580ee2v0ud00 figure 10-46: basic operation flow in one-shot pulse mode note: the counter is not cleared upon a match betw een the counter and the trnccr1 to trnccr5 buffer registers. caution: the counter is not cleared even if trigger input is realized while the counter counts up, and the trigger input is ignored. remark: n = 0, 1 start timer operation enable (trnce = 1) transfer of values of trnccr0 to trnccr5 to buffers trnccr0 to trnccr5 initial settings clock selection (trnctl1: trneee = 0) (trnctl0: trncks2 to trncks0) one-shot pulse mode setting (trnctl1: trnmd2 to trnmd0 = 011) compare register setting (trnccr0 to trnccr5) trigger wait status, counter in standby at ffffh trigger wait status, counter in standby at 0000h external trigger (ttrgrn pin) input, or trnest = 1 counter starts counting. match between counter and buffers trnccr1 to trnccr5 match between counter and buffer trnccr0, counter clear inttrncc0 occurrence note inttrncc1 to inttrncc5 occurrence ? ? ?
387 chapter 10 16-bit inverter timer/counter r user?s manual u16580ee2v0ud00 figure 10-47: basic operation timing in one-shot pulse mode (a) (trnoe0, 1 = 1, trnol0, 1 = 0) note: count up starts when the value of trnest becomes 1 or ttrgrn is input. remarks: 1. d0: setting value of trnccr0 register (0000h to ffffh) d1: setting value of trnccr1 register (0000h to ffffh) 2. torn1 (output delay) = (setting value of trnccr1 register) (count clock cycle) torn1 (output pulse width) = {(settin g value of trnccr0 register +1) - (setting value of trnccr1 register)} (count clock cycle) 3. n = 0, 1 0000h counter inttrncc0 ffffh trnccr1 inttrncc1 trnccr0 trnce external trigger (ttrgrn pin) torn1 trnest d0 d0 d0 d1 d1 d1 d0 d1 note d0 d0 trnccr0 buffer 0000h d1 trnccr1 buffer torn0 one-shot pulse output
388 chapter 10 16-bit inverter timer/counter r user?s manual u16580ee2v0ud00 10.10.5 pwm mode (1) outline of pwm mode when, in the pwm mode, the duty is set to the trnccr1 to trnccr5 registers, the cycle is set to the trnccr0 register, and trnce = 1 is set, variable duty pwm output is performed from pins torn1 to torn5. simultaneously with the start of count up oper ation, pins torn1 to torn5 becomes high level, and upon a match between the counter and the trnccr1 to trnccr5 registers, becomes low level. next, the torn1 to torn5 pins become high level upon a match with the trnccr0 register. the torn0 pin performs toggle output upon a match with the trnccr0 buffer register. during count operation, a compare match interrupt (inttrncc0) is output upon a match between the counter and trnccr0 register, and compare match interrupts (inttrncc1 to inttrncc5) are output upon a match betw een the counter and trnccr1 to trnccr5 registers. the trnccr0 to trnccr5 registers can be rewritten during count operation. compare register reload occurs upon a match between the counter value and the trnccr0 buffer register. however, since the next reload timing becomes valid when the trnccr1 register is written to, write the same value to the trnccr1 register even when wishing to rewrite only the value of the trnccr0 register. reloading is not performed if only the trnccr0 register is rewritten. in the pwm mode, the trnccr0 to trnccr3 regi sters have their function fixed as compare registers, so the capture function cannot be used.
389 chapter 10 16-bit inverter timer/counter r user?s manual u16580ee2v0ud00 (2) pwm mode operation list (a) compare register (b) input pins (c) output pins (d) interrupts register rewrite method rewrite during operation function trnccr0 reload possible cycle trnccr1 to trnccr3 reload possible duty trnccr4, trnccr5 reload possible duty pin function tir1m - (m = 0 to 3) ttrgr1 - tevtr1 - pin function torn0 toggle output upon trnccr0 register compare match tornm pwm output upon trnccrm register compare match (m = 1 to 5) torn6 - torn7 pulse output through a/d conversion trigger interrupt function inttrnccm trnccrm register compare match inttrnov - inttrner error
390 chapter 10 16-bit inverter timer/counter r user?s manual u16580ee2v0ud00 figure 10-48: basic operation mode in pwm mode (1/2) (a) when values of trnccr0 to trnccr5 registers are rewr itten during timer operation remark: n = 0, 1 m = 0 to 5 start inttrncc0 occurrence timer operation enable transfer of value of trnccrm to trnccrm buffer torn1 to torn5 output low level upon a match between counter and trnccr1 to trnccr5 bffers. upon a match between counter and trnccr0 buffer, counter clear & start, and torn1 to torn5 output high level. inttrncc1 to inttrncc5 occurrence initial settings clock selection (trnctl0: trncks2 to trncks0) pwm mode setting (trnctl1: trnmd3 to trnmd0 = 0100) compare register setting (trnccr0 to trnccr5) ? ? ?
391 chapter 10 16-bit inverter timer/counter r user?s manual u16580ee2v0ud00 figure 10-48: basic operation flow in pwm mode (2/2) (b) when values of trnccr0 to trnccr5 registers are rewr itten during timer operation note: regarding the sequence, the timing of <2> may differ depending on the <1> or <3> rewrite timing, the value of the trnccr1 register, etc., but of <1> and <3>, always make <3> the last. remark: n = 0, 1 m = 0 to 5 start inttrncc0 occurrence upon a match between counter and trnccr1 to trnccr5 buffers, torn1 to torn5 output low level. timer operation enable (trnce = 1) transfer of value of trnccrm to trnccrm buffer upon a match between counter and trnccr1 to trnccr5, torn1 to torn5 output low level trnccr0 rewrite trnccr1 rewrite upon a match between counter and trnccr0, counter clear & start, and torn1 to torn5 output high level. <1> inttrncc1 to inttrncc5 occurrence inttrncc0 occurrence inttrncc1 to inttrncc5 occurrence initial settings clock selection (trnctl0: trncks2 to trncks0) pwm mode setting (trnctl1: trnmd3 to trnmd0 = 0100) compare register setting (trnccr0 to trnccr5) match between trnccr0 buffer and counter counter clear & start value of trnccrm is reloaded to ccrm buffer. <2> <3> note reload enable ? ? ? ? ? ?
392 chapter 10 16-bit inverter timer/counter r user?s manual u16580ee2v0ud00 figure 10-49: basic operati on timing in pwm mode (1/2) (a) when only value of trnccr1 is rewritten, and torn0 and torn1 are output (trnoe0, 1 = 1, trnol0, 1 = 0) remarks: 1. d00: setting value of trnccr0 register (0000h to ffffh) d10, d11, d12, d13: setting values of trnccr1 register (0000h to ffffh) 2. torn1 (pwm) duty = (setting value of trnccr1 register) (count clock cycle) torn1 (pwm) cycle = (setting value of tr nccr0 register + 1) (count clock cycle) torn0 is toggled immediately following count er start and at (setting value of trnccr0 register + 1) (count clock cycle) 3. n = 0, 1 counter ffffh trnccr1 trnccr0 trnce torn1 trnccr0 buffer trnccr1 buffer d 00 d 00 0000h d 10 d 11 d 12 d 13 d 10 d 11 d 12 d 13 0000h d 00 d 00 d 00 d 00 d 10 d 10 d 11 d 12 torn0 trnrsf flag
393 chapter 10 16-bit inverter timer/counter r user?s manual u16580ee2v0ud00 figure 10-49: basic operation timing in pwm mode (2/2) (b) when values of trnccr0 and trnccr1 register are rewritten, torn0 and torn1 are output (trnoe0, 1 = 1, trnol0, 1 = 0) note: the trnccr1 register was not written to, so transfer to the trnccr0 buffer register was not performed. held until the next reload timing. remarks: 1. d00, d01, d02, d03: setting values of trnccr0 register (0000h to ffffh) d10, d11, d12, d13: setting values of trnccr1 register (0000h to ffffh) 2. the torn0 and torn1 pins become high level at timer count start. 3. n = 0, 1 counter ffffh trnccr1 trnccr0 trnce torn1 trnccr0 buffer trnccr1 buffer d 00 0000h d 10 d 11 d 12 d 12 d 10 d 11 d 12 0000h d 00 d 01 d 02 d 03 d 01 d 01 d 02 d 00 d 01 d 02 d 03 d 12 d 10 d 11 d 11 d 12 note note write same value torn0 trnrsf flag
394 chapter 10 16-bit inverter timer/counter r user?s manual u16580ee2v0ud00 10.10.6 free-running mode (1) outline of free-running mode the operation timing of the free-running mode is shown below. the operation for bits trnccs0 to trnccs3 of register trnopt0 is specified. figure 10-50: basic operation flow in free-running mode remarks: 1. this is an example when using the trnccr0 and trnccr1 registers. when using the trnccr2 and trnccr3 registers, the operation is controlled in the same manner via bits trnccs3 and trnccs2. 2. n = 0, 1 start trnccs1, trnccs0 settings initial settings clock selection (trnctl0: trncks2 to trncks0) free-running mode setting (trnctl1: trnmd3 to trnmd0 = 0101) match between trnccr1 buffer and counter match between trnccr0 buffer and counter tirn0 edge detection settings (trnis1, trnis0) trnccs1 = 0 trnccs0 = 0 trnccs1 = 0 trnccs0 = 0 trnccs1 = 1 trnccs0 = 1 trnccs1 = 1 trnccs0 = 1 timer operation enable (trnce = 1) transfer of values of trnccr0 and trnccr1 to trnccr0 and trnccr1 buffers timer operation enable (trnce = 1) transfer of value of trnccr1 to trnccr1 buffer counter overflow timer operation enable (trnce = 1) transfer of value of trnccr0 to trnccr0 buffer match between trnccr1 buffer and counter tirn0 edge detection, capture of counter value to trnccr0 counter overflow counter overflow counter overflow match between trnccr1 buffer and counter timer operation enable (trnce = 1) tirn1 and tirn0 edge detection settings (trnis3, trnis2) tirn1 edge detection, capture of counter value to trnccr1 tirn0 edge detection, capture of counter value to trnccr0 tirn1 edge detection, capture of counter value to trnccr1 tirn1 edge detection settings (trnis3, trnis2) ? ?
395 chapter 10 16-bit inverter timer/counter r user?s manual u16580ee2v0ud00 (2) free-running mode operation list (a) compare registers (b) input pins (c) output pins (d) interrupts register rewrite method rewrite during operation function trnccr0 anytime rewrite possible compare value trnccr1 to trnccr3 anytime rewrite possible compare value trnccr4, trnccr5 anytime rewrite possible compare value pin function tir1m - (m = 0 to 3) ttrgr1 - tevtr1 - pin function tornm toggle output upon trnccrm register compare match (m = 0 to 5) torn6, torn7 - interrupt function inttrnccm trnccrm register compare match (m = 0 to 5) inttrnov overflow inttrner -
396 chapter 10 16-bit inverter timer/counter r user?s manual u16580ee2v0ud00 (3) compare function (trnccs1 = 0, trnccs0 = 0) when trnctl0 register bit trnce is set to 1, the counter counts from 0000h to ffffh. an overflow interrupt (inttrnov) is output when the counter value changes from ffffh to 0000h, and the counter is cleared. the count operation is performed in the free-running mode until trnce = 0 is set. moreover, during count operation, a compare match interrupt (inttrncc0) is output upon a match between the counter and trnccr0 buffer register, and a compare match interrupt (inttrncc1) is output upon a match between the counter and trnccr1 buffer register. the trnccr0 and trnccr1 registers can be rewritten using the an ytime write method, regardless of the value of the trnce bit. the torn0 and torn1 pins are toggle output controlled when bits register trnoe0 and trnoe1 of the trnioc0 register are set to 1.
397 chapter 10 16-bit inverter timer/counter r user?s manual u16580ee2v0ud00 figure 10-51: basic operation timing in free-running mode (compare function) when values of trnccr0 and trnccr1 registers are rewritte n, torn0, torn1 are output (trnoe0, 1 = 1, trnol0, 1 = 0) remarks: 1. d00, d01: setting values of tr nccr0 register (0000h to ffffh) d10, d11: setting values of tr nccr1 register (0000h to ffffh) 2. torn0 (toggle) width = (setting value of trnccr0 register + 1) (count clock cycle) 3. torn1 (toggle) width = (setting value of trnccr1 register + 1) (count clock cycle) 4. pins torn0 and torn1 become high level at count start. 5. n = 0, 1 0000h counter ffffh trnccr1 trnccr0 trnce inttrncc1 d 00 d 00 d 01 d 11 d 11 d 10 d 00 d 01 d 11 d 10 inttrncc0 d 00 d 01 d 10 d 11 0000h trnccr0 buffer trnccr1 buffer torn0 torn1 inttrnov trnovf trnovf 0 write clear trnovf 0 write clear
398 chapter 10 16-bit inverter timer/counter r user?s manual u16580ee2v0ud00 (4) capture function (trnccs1 = 1, trnccs0 = 1) when trnctl0 register bit trnce is set to 1, the counter counts from 0000h to ffffh. an overflow interrupt (inttrnov) is output when the value of the counter changes from ffffh to 0000h, and the counter is cleared. the count operation is performed in the free-running mode until trnce = 0 is set. when, during count operation, the counter value is captured to the trnccr0 and trnccr1 registers through detection of the valid edge of capture input (tirn1, tirn0), a capture interrupt (inttrncc0, inttrncc1) is output. regarding capture in the vicinity of overflow (f fffh), judgment is possible with the overflow flag (trnovf). however, judgment with the trnovf flag is not possible when the capture trigger interval is such that it includes two overflow occurrences (2 or more free-running cycles). figure 10-52: basic operation timing in free-running mode (capture function) when torn0, torn1 are not output (trnoe0, 1 = 0, trnol0, 1 = 0) remarks: 1. d00, d01: values captured to trnccr0 register (0000h to ffffh) d10, d11: values captured to trnccr1 register (0000h to ffffh) 2. tirn0: setting to rising edge detection (trnioc1 register bits trnis1, trnis0 = 01) tirn1: setting to falling edge detection (trnioc1 register bits trnis3, trnis2 = 10) 3. n = 0, 1 d 11 d 10 0000h d 12 counter ffffh tirn1 tirn0 trnce trnccr1 d 00 d 01 d 12 d 02 d 11 d 10 d 00 d 01 trnccr0 d 02 d 03 0000h d 03
399 chapter 10 16-bit inverter timer/counter r user?s manual u16580ee2v0ud00 (5) compare/capture function (trnccs1 = 0, trnccs0 = 1) when trnctl0 register bit trnce is set to 1, the counter counts from 0000h to ffffh, an overflow interrupt (inttrnov) is output when the value of the counter changes from ffffh to 0000h, and the counter is cleared. the count ope ration is performed in the free-running mode until trnce = 0 is set. the trnccr1 register is used as a compare register, and as the interval function upon a match between the counter and trnccr1 register, a compare match interrupt (inttrncc1) is output. since the trnccr0 register is set to the capture function, the torn0 pin cannot be controlled even when trnioc0 register bit trnoe0 is set to 1. figure 10-53: basic operation timing in free-running mode (compare/capture function) when value of trnccr1 is rewritten, torn0, torn1 are output (trnoe0, 1 = 1, trnol0, 1 = 0) remarks: 1. d00, d01: setting values of tr nccr1 register (0000h to ffffh) d10, d11, d12, d13, d14, d15: values captured to trnccr0 register (0000h to ffffh) 2. tirn0: setting to rising edge detection (trnioc1 register bits ttnis1, ttnis0 = 11) 3. n = 0, 1 counter ffffh trnccr1 tirn0 trnce d 00 d 02 d 03 d 10 d 11 d 10 trnccr0 0000h d 12 d 00 d 01 d 11 d 12 d 01 d 02 d 03 d 11 trnccr1 buffer inttrncc1 d 10 d 11 d 12 0000h inttrncc0 match interrupt capture interrupt inttrnov overflow interrupt torn0 torn1 low
400 chapter 10 16-bit inverter timer/counter r user?s manual u16580ee2v0ud00 (6) overflow flag when, in the free-running mode, the counter over flows from ffffh to 0000h, the overflow flag (trnovf) is set to ?1?, and an overflow interrupt (inttrnov) is output. the overflow flag is cleared through 0 write from the cpu. (the overflow flag is not cleared by just being read.) 10.10.7 pulse width measurement mode (1) outline of pulse width measurement mode in the pulse width measurement mode, counting is performed in the free-running mode. the counter value is saved to the trnccr0 register, an d the counter is cleared to 0000h. as a result, the external input pulse width can be measured. however, when measuring a long pulse width that exceeds counter overflow, perform judgment with the overflow flag. measurement of pulses during which overflow occurs twice or more is not possible, so adjust the counter's operating frequency. even in the case of tirn1 to tirn3 pin edge detection, pulse width measurement can be similarly performed by using the trnccr1 to trnccr3 registers. figure 10-54: basic operation timing in pulse width measurement mode (trnoe0, 1 = 0, trnol0, 1 = 0) remarks: 1. d00, d01, d02, d03: values captured to trnccr0 register (0000h to ffffh) 2. tirn0: setting to rising edge/falling edge (both edges) detection (trnioc1 register bits ttnis1, ttnis0 = 11) 3. n = 1 counter ffffh inttrncc0 tirn0 trnce trnovf d 00 trnccr0 0000h d 00 d 01 d 02 d 03 d 01 d 02 d 03 ffffh inttrnov cleared through 0 write from cpu
401 chapter 10 16-bit inverter timer/counter r user?s manual u16580ee2v0ud00 (2) pulse width measurement mode operation list (a) compare register (b) input pins (c) output pins (d) interrupts register rewrite method rewrite during operation function trnccr0 anytime rewrite possible compare value trnccr1 to trnccr3 anytime rewrite possible compare value trnccr4, trnccr5 anytime rewrite possible compare value pin function tir1m input capture trigger, transfer counter value to tr1ccrm register (m = 0 to 3) ttrgr1 - tevtr1 - pin function torn0 to torn5 - torn6, torn7 - interrupt function inttrnccm tir1m capture (m = 0 to 3) inttrncc4, inttrncc5 - inttrnov overflow inttrner -
402 chapter 10 16-bit inverter timer/counter r user?s manual u16580ee2v0ud00 10.10.8 triangular wave pwm mode (1) outline of triangular wave pwm mode in the triangular wave pwm mode, similarly to in the pwm mode, when the duty is set to the trnccr1 to trnccr5 registers, the cycle is set to the trnccr0 register , and trnce = 1 is set, variable duty and cycle type triangular wave pwm output is performed from pins torn1 to torn5. the torn0 pin is toggle output upon a match with the trnccr0 buffer register and upon counter underflow. upon a match between the counter and trnccr0 register during count operation, compare match interrupts (inttrncc0 to inttrncc5) are output, and upon a match between the counter and trnccr1 to trnccr5 registers, a compare match interrupt (inttrncc1) is output. moreover, upon counter underflow, an overflow interrupt (inttrnov) is output. the trnccr0 to trnccr5 registers can be rewritten during count operation. compare register reload occurs upon a match between the counter value and the trnccr0 buffer register. however, since the next reload timing becomes valid when the trnccr1 register is written to, write the same value to the trnccr1 register even when wishing to rewrite only the value of the trnccr0 register. reloading is not performed if only the trnccr0 register is rewritten. the reload timing is the underflow timing. in the triangular wave pwm mode, the trnccr0 to trnccr3 registers have their function fixed as compare registers, so the capture function cannot be used. remark: in the triangular wave pwm mode, set the trnccr0 register to a value of 0 trnccr0 fffeh.
403 chapter 10 16-bit inverter timer/counter r user?s manual u16580ee2v0ud00 (2) triangular wave pwm mode operation list (a) compare registers (b) input pins (c) output pins (d) interrupts register rewrite method rewrite during operation function trnccr0 reload possible 1/2 of cycle trnccr1 to trnccr3 reload possible 1/2 of duty trnccr4, trnccr5 reload possible 1/2 of duty pin function tir1m - (m = 0 to 3) ttrgr1 - tevtr1 - pin function torn0 inactive during counter up count, active during down count tornm pwm output upon trnccrm register compare match (m = 0 to 5) torn6 - torn7 pulse output through a/d conversion trigger interrupt function inttrnccm trnccrm register compare match (m = 0 to 5) inttrnov - inttrner error
404 chapter 10 16-bit inverter timer/counter r user?s manual u16580ee2v0ud00 figure 10-55: basic operation timing in triangular wave pwm mode when torn0, torn1 are output (trnoe0, 1 = 1, trnol0, 1 = 0) remark: n = 0, 1 d 00 d 10 counter ffffh inttrncc0 trnce d 00 trnccr0 0000h ffffh trnccr1 0000h d 10 d 10 inttrncc1 d 00 d 10 d 00 inttrnov torn0 torn1
405 chapter 10 16-bit inverter timer/counter r user?s manual u16580ee2v0ud00 10.10.9 high-accuracy t-pwm mode (1) outline of high-accuracy t-pwm mode the high-accuracy t-pwm mode generates 6-phas e pwm using four 16-bit counters (up/down, 2 counts, 15 real bits) and 16-bit compare registers (lsb = additional pulse control). the carrier wave cycle calculated with ?trncc r0-trndtc0-trndtc1? is set to the trnccr0 register. the duty of the u phase, v phase, and w phase voltage data signal is set with the trnccr1 to trnccr3 registers. the dead time is set with the trndtc0 and trndtc1 registers, and the trndtc0 register can be used to set the inverted phase (off) normal phase (on) dead time, while the trndtc1 register can be used to set the normal phase (off) inverted phase (on) dead time. the counter operation consists in performing up count with the trndtc0 register value as the minimum value, and upon a match with the maxi mum value indicated by ?trnccr0-trndtc1?, performing down count. the 10-bit counters for dead time generation (trndtt1 to trndtt3) load the setting values of the trndtc0 and trndtc1 registers upon a match between the counter and the trnccr1 to trnccr3 registers, and perform down-count. upon a match between the 16-bit counter and th e trnccr1 to trnccr3 registers, inttrncc1 to inttrncc3, which are used as the respective compare match interrupt signals, are output. (in the 0% output vicinity and 100% output vicinity, no interrupt signal may be output.) figure 10-56: high-accuracy t-pwm mode block diagram trncnt (16-bit up/down counter - 2) trnccr3 (w phase output data) trnccr1 (u phase output data) trnccr2 (v phase output data) trndtt1 trndtc1 to1 to2 to3 to4 to5 to6 torn1(u) torn2(u) torn3(v) torn4(v) torn5(w) torn6(w) u/d sel0 inttrnod (valley interrupt) trnsbc (16-bit up/down counter - 2) u/d sel1 trnccr0 buffer 0000h sel trndtc0 trnccr0-trndtc1 inttrncd0 (peak interrupt) sel torn0 load load trntos trndtc0 trndtt2 trndtt3 load load trndtt4 trndtt5 trndtt6
406 chapter 10 16-bit inverter timer/counter r user?s manual u16580ee2v0ud00 (2) high-accuracy t-pwm mode operation list (a) compare registers (b) input pins (c) output pins (d) interrupts notes: 1. only when trndtc1 = 000h 2. when trnccr0, trndtc0, and trndtc1 registers are incorrectly set. register rewrite method rewrite during operation function trnccr0 reload, anytime rewrite possible cycle trnccr1 to trnccr3 reload, anytime rewrite possible pwm duty trnccr4, trnccr5 reload, anytime rewrite possible pwm duty (selectable as a/d conversion trigger) pin function tir1m - (m = 0 to 3) ttrgr1 - tevtr1 - pin function torn0 inactive during counter or sub-counter up count, active during down count torn1 pwm output upon trnccr1 compare match (with dead time) torn2 inverted output to torn1 torn3 pwm output upon trnccr2 compare match (with dead time) torn4 inverted output to torn3 torn5 pwm output upon trnccr3 compare match (with dead time) torn6 inverted output to torn5 torn7 pulse output through a/d conversion trigger interrupt function inttrnccr0 inttrnccr0 compare match note 1 inttrncc1 to inttrncc5 trnccr1 to trnccr5 compare match inttrnov overflow note 2 inttrner error inttrnod through interrupt inttrncd peak interrupt
407 chapter 10 16-bit inverter timer/counter r user?s manual u16580ee2v0ud00 (3) high-accuracy t-pwm mode settings (a) mode settings the high-accuracy t-pwm mode is selected by setting trnctl1 register bits trnmd4 to 0 = 1000b. (b) output level/output enable settings set bits trnol0-trnol7 and trnoe0-trnoe7 of the trnioc0, trnioc3 registers, to enable output level/output enable. pin torn0 indicates the counter?s and sub-counter?s up count/down count status. the counter/ sub-counter can be switched wit h trnopt7 register bit trntor. pin torn7 is the external a/d conversion output pin. set this pin as required. (c) error interrupt output enable set error interrupt output enable upon detection of normal phase/inverted phase simultaneous active. error interrupt output is enabled by sett ing trnioc4 register bit trneoc to ?1?. in the high-accuracy t-pwm mode, when the dead time setting is other than ?000h?, the error interrupt (inttrner) never goes active, regardless of which value the trnccr0 to trnccr3 registers are set. however, an error may be detected upon the occurrence of a timer rn internal circuit fault. if the dead time setting is ?000h?, a glitch may occur upon occurrence of an error interrupt (inttrner) at the normal phase and inverted phase switch timing. (d) rewrite timing for regist ers with reload function batch rewrite/anytime rewrite can be set for registers with the reload function. this setting is performed with trnopt0 register bit rncms. (the default is ?0? batch rewrite). to perform batch rewrite, be sure to set trnopt1 register bit trnice or trnioe. (if bit trnice and bit trnioe are both ?0?, the reload timing does not occur.) if anytime rewrite is selected, unintended output may occur depending on the rewrite timing. (when using the anytime rewrite function, refer to cautions (a) to (c) in 10.4.2 (1) anytime rewrite .) (e) interrupt and thinning out function settings the interrupt and thinning out function settings are performed with the trnopt1 register. if a peak interrupt (inttrncd) is required, set bit tr nice to 1. if a valley interrupt (inttrnod) is required, set bit trnioe to 1. to use the thinning out function for peak/valley interrupts, perform settings with the trnid4 to trnid0 registers. (f) reload thinning out function setting to set the reload timing to the same timing as the interrupt timing, set trnopt1 register bit trnrde to 1.
408 chapter 10 16-bit inverter timer/counter r user?s manual u16580ee2v0ud00 (g) a/d conversion trigger output settings to set a/d conversion trigger 0 (trnadtrg0 si gnal), set trnopt2 register bits trnat05 to trnat00. with bits trnat05 to trnat00, peak interrupt (inttrncd) and valley interrupt (inttrnod) ena- ble/disable is performed at the trnccr5 register match timing (counter up count/down count), and the trnccr4 register match timing (counter up count/down count). to set a/d conversion trigger 1 (trnadtrg1 si gnal), set trnopt3 register bits trnat15 to trnat10. with bits trnat15 to trnat10, peak interrupt (inttrncd) and valley interrupt (inttrnod) ena- ble/disable is performed at the trnccr5 register match timing (counter up count/down count), and trnccr4 register match timing (counter up count/down count). set the trnccr4 and trnccr5 registers? compare values. for the trnadtrg0 and trnadtrg1 signals, also perform the thinning out function setting. caution: to use the torn7 pin, correctly perform the trnopt2 and trnopt3 register and the trnccr4 and trnccr5 register settings. (h) dead time settings the dead time settings are performed with the trndtc0 and trndtc1 registers. the dead time can be obtained with counter operation clock cycle (p) trndtc0, trndtc1. the time until torn2,torn4,torn6 pin inactive change torn1,torn3,torn5 pin active change can be set with the trndtc0 register. the time until torn1,torn3,torn5 pin inactive change torn2,torn4,torn6 pin active change can be set with the trndtc1 register. (i) carrier wave cycle for the carrier wave cycle, set the trnccr0 register using the following equation. trnccr0 = (carrier wave cycle/ counter operation clock cycle) + trndtc1 + trndtc0 for the setting value of the trnccr0 register, meet the following conditions keeping in mind the dead time. trnccr0 > 3 max (trndtc0, trndtc1) + min (trndtc0, trndtc1) trnccr0 fffeh (max(a,b) indicates the larger value of a and b, and min(a,b) indicates the smaller value of a and b.) (j) duty (pwm width) setting for the duty setting, perform the u phase, v phase, and w phase settings with the trnccr1 to trnccr3 registers. the setting range of th e trnccr1 to trnccr3 registers is 0000h trnccr1, trnccr2, trnccr3 trnccr0 + 1. do not set trnccr0 + 2 < trnccr1, trnccr2, trnccr3. lsb (least significant bit) of the trnccr1 to trnccr3 registers means the additional pulse setting. for example, if trnccr1 = 0003h is set, compare to when trnccr1 = 0002h is set, the inverted phase (pin torn2) change is an 1-count clock delay (during counter up count).
409 chapter 10 16-bit inverter timer/counter r user?s manual u16580ee2v0ud00 (4) counter operation in high-accuracy t-pwm mode at initial value fffeh, the trndtc0 value is l oaded to the counter immediately after trnce = 1 is set, and the counter counts up in +2 step s. then, upon a match with trnccr0 to trndtc1, the counter counts down in - 2 steps. the counter operation is as follows. figure 10-57: counter operation in high-accuracy t-pwm mode remark: minimum counter value: trndtc0 maximum counter value: trnccr0 - trndtc1 carrier wave cycle: (trnccr0-trndt c0-trndtc1) count clock cycle at initial value fffeh, the value of trndtc0 register is loaded to the sub-counter immediately after trnce = 1 is set. then, until a match with 0000h, the sub-counter counts down in - 2 steps, and the counter value is loaded to the sub-counter at the counter?s up count down count switch timing. the trndtc0 register goes on coun ting up, and upon a match with the trnccr0 register, starts counting down in - 2 steps. at the same time, upon a match between the counter and the trndtc0 register, the counter value is loaded and down count is continued. the sub-counter operation is as follows. figure 10-58: sub-counter operation in high-accuracy t-pwm mode fffeh 0000h trnccr0 trndtc0 trnccr0- trndtc1 trncnt +2 count 2 count trnce = ?1? fffeh 0000h trnccr0 trndtc0 trnccr0- trndtc1 trncnt +2 count 2 count trnce = ?1? trnsbc load load
410 chapter 10 16-bit inverter timer/counter r user?s manual u16580ee2v0ud00 (5) basic operation in high-accuracy t-pwm mode the figure 10-59 shows the timing chart when trnccr0 = 0010h, trndtc0 = 0002h, trndtc1 = 0004h, and the trnccr1 register is set from 0000h to 0010h (one part only shown). in this example, trnol6 to trnol1 = 000000b is set. if trnccr1 > trndtc0, pin torn2 changes with the following compare match. since trnccr1 = (trndtc0-0001h) is an additional pulse, compared to when trnccr1 = (trndtc0 - 0002h), pin torn2 changes with an 1 count clock delay. figure 10-59: timer output example when trnce = 1 is set (initial) (high-accuracy t-pwm mode) remarks: 1. trnccr0 = 0010h, trndtc0 = 0002h, trndtc1 = 0004h 2. td0: time depends on dead time setting of trndtc0 register td1: time depends on dead time setting of trndtc1 register ts1: time is determined through sub-counter compare, when sub-counter value > counter value 3. n = 0, 1 trnccr0 torn1 torn2 counter fffe 0002 0004 0008 000a 000c 000a 0008 0006 0004 0002 0004 0006 fffe 0000 0002 0004 0006 0008 000e 0010 000e 000c 000a 0000 0002 sub-counter trnce trncuf trnsuf trndtc0 trndtc1 0010h (for cycle setting) 002h (for dead time setting) 004h (for dead time setting) [trnccr1 = 0000h] torn1 torn2 [trnccr1 = 0001h] torn1 torn2 [trnccr1 = 0002h] torn1 torn2 [trnccr1 = 0004h] torn1 torn2 [trnccr1 = 0008h] torn1 torn2 [trnccr1 = 000ah] torn1 torn2 [trnccr1 = 000ch] torn1 torn2 [trnccr1 = 000eh] torn1 torn2 [trnccr1 = 0010h] t s1 ?l? ?l? ?l? t d1 t d1 t d1 t d0 t d0 t d0
411 chapter 10 16-bit inverter timer/counter r user?s manual u16580ee2v0ud00 the figure 10-60 shows the timing chart when trnccr0 = 0010h, trndtc0 = 0002h, trndtc1 = 0004h, and the trnccr1 register is set from 0000h to 0010h (one part only shown). in this example, trnol6 to trnol1 = 000000b is set. as can be seen in this figure, a normal phase (pin torn1) that is active (high level) is output when 0000h trnccr1 (trnccr0 - trndtc0 + 0001h). also, the inverted phase (pin torn0) that is active (high level) is output when (trndtc0 + trndtc1) < trnccr1 trnccr0. figure 10-60: timer output example during operation (high-accuracy t-pwm mode) remarks: 1. trnccr0 = 0010h, trndtc0 = 0002h, trndtc1 = 0004h 2. td0: time depends on dead time setting of trndtc0 register td1: time depends on dead time setting of trndtc1 register ts0: time is determined through sub-counter compare, when sub-counter value < counter value ts1: time is determined through sub-counter compare, when sub-counter value > counter value 3. n = 0, 1 trnccr0 torn1 torn2 0004 0006 0008 000a 000c 000a 0008 0006 0004 0002 0004 0006 0000 0002 0004 0006 0008 000e 0010 000e 000c 000a 0000 0002 trnce trncuf trnsuf trndtc0 trndtc1 [trnccr1 = 0000h] torn1 torn2 [trnccr1 = 0001h] torn1 torn2 [trnccr1 = 0002h] torn1 torn2 [trnccr1 = 0004h] torn1 torn2 [trnccr1 = 0008h] torn1 torn2 [trnccr1 = 000ah] torn1 torn2 [trnccr1 = 000ch] torn1 torn2 [trnccr1 = 000eh] torn1 torn2 [trnccr1 = 0010h] t s1 ?l? ?l? ?l? ?l? ?l? ?l? t d1 t d1 t d1 t d0 t d0 t d0 0004 0002 000c 000a counter sub-counter 0010h (for cycle setting) 002h (for dead time setting) 004h (for dead time setting)
412 chapter 10 16-bit inverter timer/counter r user?s manual u16580ee2v0ud00 (6) additional pulse control in high-accuracy t-pwm mode in the high-accuracy t-pwm mode, additional pulse can be set by setting the lsb of the duty setting registers (trnccr1 to trnccr3) to ?1?. with the additional pulse control function, finer duty control can be performed (higher accuracy). torn1 pin output examples are provided below fo r when additional pulse control is and is not performed. the settings used here are trnccr = 12, trndtc0, and trndtc1 = 0. figure 10-61: torn1 pin output example wh en performing additional pulse control remarks: 1. trnccr0 = 12, trndtc0 = 0, trndtc1 = 0 2. n = 0, 1 the locations where additional pulse control is performed are when an odd value has been set to the trnccr1 register. in the above figure, the arrows and numbers indicate the duty width of the torn1 pin output within 1 cycle. as can be seen in the above figure, when additional pulse control is performed, the output width (duty ratio) of pin torn1 can be controlled in 1 count clock steps from 12 clocks to 0 clocks. 0 2 4 6 8 10 12 10 8 6 4 2 0 2 4 11 10 9 8 7 6 5 4 3 2 1 0 12 trnccr1 = 0 trnccr1 = 1 trnccr1 = 2 trnccr1 = 3 trnccr1 = 4 trnccr1 = 5 trnccr1 = 6 trnccr1 = 7 trnccr1 = 8 trnccr1 = 9 trnccr1 = 10 trnccr1 = 11 trnccr1 = 12 123456789101112 count clock counter value
413 chapter 10 16-bit inverter timer/counter r user?s manual u16580ee2v0ud00 figure 10-62: torn1 pin output example when additional pulse control is not performed remarks: 1. trnccr0 = 12, trndtc0 = 0, trndtc1 = 0 2. n = 0, 1 the figure above is an example when additional pulse control is not performed. in the above figure, the arrows and numbers indicate the duty width of the torn1 pin output within 1 cycle. when additional pulse control is not performed, the output width of pin torn1 can be controlled in 2 count clock steps from 12 clocks to 0 clocks. in this case, the duty change amount is larger compared to when additional pulse control is performed. trnccr1 = 0 trnccr1 = 2 trnccr1 = 4 trnccr1 = 6 trnccr1 = 8 trnccr1 = 10 trnccr1 = 12 0 2 4 6 8 10 12 10 8 6 4 2 0 2 4 10 8 6 4 2 0 12 123456789101112 count clock
414 chapter 10 16-bit inverter timer/counter r user?s manual u16580ee2v0ud00 (7) caution on timer output in high-accuracy t-pwm mode there are cautions for trnccr1 to trnccr3 as follows when varying 6-phase pwm duty by using reload (batch rewrite). (a) in case of trnccr0 + 2 trnccrm (setting prohibited) figure 10-63a shows the case wh en the value of ?trnccr0 + 2 or more? is set to the trnccr1 register. when the trnccr1 register setting is changed like this, a match between the 16-bit counter and trnccr1 register does not occur thereafter. therefore, the torn1 pin output level is forcibly changed to inactive level at the followi ng 16-bit sub-counter tro ugh timing. output will be switched at 16-bit sub-counter peak/trough timing after that. figure 10-63: timings of timer output in high-accuracy t-pwm mode (1/3) (a) output when trnccr0 + 2 trnccr1 note: m = 1 to 3 16-bit counter 0000h reload timing torn1 torn2 y x trnccr1 y 16-bit sub-counter output is toggled at a peak/trough timing of 16-bit sub-counter when trnccr1 > trnccr0 + 1 x x x x x x x y y
415 chapter 10 16-bit inverter timer/counter r user?s manual u16580ee2v0ud00 (b) in case of rewriting from tr nccrm = 0000h to trnccrm = trnccr0 figure 10-63b shows the output waveform where the trnccr1 register setting is changed from 100% output to 0% output. the torn1 pin output is inverted upon a match between the trnccr1 register and 16-bit sub-counter, and the torn2 pin output is inverted after the dead time count. figure 10-63: timings of timer output in high-accuracy t-pwm mode (2/3) (b) output when rewriting from tr nccr1 = 0000h to trnccr1 = trnccr0 note: m = 1 to 3 (c) in case of rewriting from ?trndtc0 + trndtc1 < trnccrm < trnccr0 ? trndtc0 ? trndtc1? to ?trnccrm < trndtc0 + trndtc1? figure 10-63c shows the output waveform w hen rewriting the trn ccr1 register from x (trndtc0 + trndtc1 < x < trnccr0 ? trndtc0 ? trndtc1) to y (y < trndtc0 + trndtc1). in this case, the torn1 pin output becomes active when the torn1 pin set condition occurs upon a match between the 16-bit counter (or 16-bit sub-counter) and the trnccr1 regis- ter immediately after reload (batch rewrite). (c) output when rewriting from trndtc0 + trndtc1 < trnccr1 < trnccr0 ? trndtc0 ? trndtc1 to trnccr1 < trndtc0 + trndtc1 note: m = 1 to 3 16-bit counter 0000h reload timing torn1 torn2 n = trnccr0 0000h trnccr1 n 16-bit sub-counter output is inverted upon a match between 16-bit sub-counter and trnccr1 16-bit counter 0000h reload timing torn1 torn2 y x trnccr1 x 16-bit sub-cou ter x x x y y n
416 chapter 10 16-bit inverter timer/counter r user?s manual u16580ee2v0ud00 (d) in case of rewriting from ?trndtc0 + trndtc1 < trnccrm < trnccr0 ? trndtc0 ? trndtc1? to ?trnccr0 ? trndtc1 + 1 < trnccrm < trnccr0? figure 10-63d shows the output waveform when rewriting the trnccr1 register from x (trndtc0 + trndtc1 < x < trnccr0 ? trndtc0 ? trndtc1) to y (trnccr0 ? trndtc0 ? trndtc1 < trndtc0 < trnccr0). in this case, the torn2 pin output becomes inactive (high level) when the torn2 pin set condition occurs upon a match between the 16-bit counter (or 16- bit sub-counter) and trnccrm register immediately after batch rewrite. figure 10-63: timings of timer output in high-accuracy t-pwm mode (3/3) (d) output when rewriting from ?trndtc0 + trndtc1 < trnccr1 < trnccr0 ? trndtc0 ? trndtc1? to ?trnccr0 ? trndtc1 + 1 < trnccr1 < trnccr0? note: m = 1 to 3 16-bit counter 0000h reload timing torn1 torn2 y x trnccr1 x 16-bit sub-counter x x y y y
417 chapter 10 16-bit inverter timer/counter r user?s manual u16580ee2v0ud00 (8) timer output change after compare register updating timer output is affected when the compare register value is updated during reload execution. the timer output level is changed at any timing listed in tables 10-1 and 10-2. table 10-1: positive phase operation condition list operation symbol condition set st1 match between counting up near the 16-b it sub-counter trough and compare register values (< trndtc0) clear rt1 match between counting down near the 16 -bit sub-counter trough and compare register values (< trndtc0) set st2 at completion of dead time counter (trndtc0) operation clear rt2 when 16-bit counter value matches with compare register value during count-down operation set st3 100% output for pwm duty clear rt3 when no match occurs until 16-bit sub-counter counts down to 0000h clear rt4 trnccr0 and trndtc0 settings are changed at a reload timing. though neither a match (nor a match interrupt) occurs between trnccr0 and trndtc0, the operation is cleared by special processing. clear rt5 the operation is cleared upon a match between peripheral 16-bit sub-counter peak and compare register values in positive phase active level. table 10-2: negative phase operation condition list operation symbol condition set sb1 match between counting down near the 16-b it sub-counter peak and compare register values (> trnccr0 - trndtc1) clear rb1 match between counting up near the 16 -bit sub-counter peak and compare register values (> trnccr0 - trndtc1) set sb2 at completion of dead time counter (trndtc1) operation clear rb2 when 16-bit counter value matches with compare register value during count-up operation set sb3 100% output for pwm duty clear rb3 when no match occurs until 16-bit sub-counter counts up to trnccr0 clear rb4 trnccr0 and trndtc0 settings are changed at a reload timing. though neither a match (nor a match interrupt) occurs between trnccr0 and trndtc1, the operation is cleared by special processing. clear rb5 the operation is cleared upon a match be tween peripheral 16-bit sub-counter trough and compare register values in negative phase active level.
418 chapter 10 16-bit inverter timer/counter r user?s manual u16580ee2v0ud00 figure 10-64: timer output change after compare register updating timings (1/3) (a) trnccr1 to trnccr3 = 0000h 0000h < trnccr1 to trnccr3 < trndtc0 (b) trnccr1 to trnccr3 = 0000h trnccr1 to trnccr3 = trndtc0, trndtc0 + 1 table 10-3: compare register value after trough reload (trndtc0 < trndtc1) compare register value immediately before trough reload compare register value after trough reload (trndtc0 < trndtc1) figure no. 0000h 0000h < trnccr1 to trnccr3 < trndtc0 figureaa trnccr1 to trnccr3 = 0000h, trndtc0 + 1 figureab trndtc0 + 1 < trnccr1 to trnccr3 trndtc0 2 figure 10-64c trndtc0 2 < trnccr1 to trnccr3 < trnccr0 ? trndtc0 ? trndtc1 figure 10-64d trnccr0 ? trndtc0 ? trndtc1 trnccr1 to trnccr3 < trnccr0 ? trndtc1 figure 10-64e trnccr0 ? trndtc1 trnccr1 to trnccr3 < trnccr0 figure 10-64f trnccr1 to trnccr3 = trnccr0 figure 10-64g trndtt1 to trndtt3 torn1, torn3, torn5 torn2, torn4, torn6 16-bit counter 16-bit sub-counter 0000h st3 st1 rt1 trnccr0 st1 rt1 ?l? trnccr1 to trnccr3 trndtt1 to trndtt3 torn1, torn3, torn5 torn2, torn4, torn6 16-bit counter 16-bit sub-counter 0000h st3 st1 rt1 trnccr0 st1 rt4 ?l? trnccr1 to trnccr3
419 chapter 10 16-bit inverter timer/counter r user?s manual u16580ee2v0ud00 figure 10-64: timer output change after compare register updating timings (2/3) (c) trnccr1 to trnccr3 = 0000h trndtc0 < trnccr1 to trnccr3 < trndtc0 2 when the values of trnccr1 to trnccr3 are chan ged from ?0000h trnccr1 to trnccr3 < trndtc0? to ?trndtc0 < trnccr1 to trnccr3 < trndtc0 2?, the positive phase will be 100% output for one cycle, as shown in figure 10-64c. to prevent this phenomenon, change ?0000h trnccr1 to trnccr3 < trndtc0? to ?trndtc0 < trnccr1 to trnccr3 < trndtc 2? through trndtc0, or directly change ?0000h trnccr1 to trnccr3 < trndtc0? to ?trndtc0 2 trnccr1 to trnccr3?. (d) trnccr1 to trnccr3 = 0000h trndtc0 2 < trnccr1 to trnccr3 < trnccr0 ? trndtc1 ? trndtc0 trndtt1 to trndtt3 torn1, torn3, torn5 torn2, torn5, torn6 16-bit counter 16-bit sub-counter 0000h st3 st2 rt2 trnccr0 rb2 st2 rt2 rb2 ?l? trnccr1 to trnccr3 trndtt1 to trndtt3 torn1, torn3, torn5 torn2, torn4, torn6 16-bit counter 16-bit sub-counter 0000h st3 sb2 st2 rt2 rt3 trnccr0 rb2 st2 rt2 sb2 rb2 sb2 trnccr1 to trnccr3
420 chapter 10 16-bit inverter timer/counter r user?s manual u16580ee2v0ud00 figure 10-64: timer output change after compare register updating timings (3/3) (e) trnccr1 to trnccr3 = 0000h trnccr0 ? trndtc1 ? trndtc0 < trnccr1 to trnccr3 < trnccr0 ? trndtc1 (f) trnccr1 to trnccr3 = 0000h trnccr0 ? trndtc1 < trnccr1 to trnccr3 < trnccr0 (g) trnccr1 to trnccr3 = 0000h trnccr0 ? trndtc1 < trnccr1 to trnccr3 < trnccr0 trndtt1 to trndtt3 torn1, torn3, torn5 torn2, torn4, torn6 16-bit counter 16-bit sub-counter 0000h st3 sb2 rt2 rt3 trnccr0 rb2 rt2 sb2 rb2 sb2 trnccr1 to trnccr3 trndtt1 to trndtt3 torn1, torn3, torn5 torn2, torn4, torn6 16-bit counter 16-bit sub-counter 0000h st3 sb2 rt3 trnccr0 rb1 sb1 rb1 sb1 trnccr1 to trnccr3 trndtt1 to trndtt3 torn1, torn3, torn5 torn2, torn4, torn6 16-bit counter 16-bit sub-counter 0000h st3 sb2 rt3 trnccr0 sb3 sb3 trnccr1 to trnccr3
421 chapter 10 16-bit inverter timer/counter r user?s manual u16580ee2v0ud00 figure 10-65: compare register value after trough reload timing (1/3) (a) trnccr1 to tr nccr3 = trnccr0 trnccr1 to trnccr3 = 0000h (b) trnccr1 to trnccr3 = trnccr0 0000h < trnccr1 to trnccr3 < trndtc0 table 10-4: compare register value after trough reload compare register value immediately before trough reload compare register value after trough reload figure no. trnccr0 trnccr1 to trnccr3 = 0000h figure 10-65a 0000h < trnccr1 to trnccr3 < trndtc0 figure 10-65b trnccr1 to trnccr3 = trndtc0, trndtc0 + 1 figure 10-65c trndtc0 + 1 < trnccr1 to trnccr3 < trndtc0 + trndtc1 figure 10-65d trndtc0 + trndtc1 < trnccr1 to trnccr3 < trnccr0 ? trndtc0 ? trndtc1 figure 10-65e trnccr0 ? trndtc0 ? trndtc1 trnccr1 to trnccr3 < trnccr0 ? trndtc1 figure 10-65f trnccr0 ? trndtc1 trnccr1 to trnccr3 < trnccr0 figure 10-65g trndtt1 to trndtt3 torn1, torn3, torn5 torn2, torn4, torn6 16-bit counter 16-bit sub-counter 0000h sb3 st2 trnccr0 st3 rb5 trnccr1 to trnccr3 trndtt1 to trndtt3 torn1, torn3, torn5 torn2, torn4, torn6 16-bit counter 16-bit sub-counter 0000h sb3 st2 trnccr0 st1 rb5 rt1 trnccr1 to trnccr3
422 chapter 10 16-bit inverter timer/counter r user?s manual u16580ee2v0ud00 figure 10-65: compare register value after trough reload timing (2/3) (c) trnccr1 to trnccr3 = trnccr0 trnccr1 to trnccr3 = trndtc0, trndtc0 + 1 (d) trnccr1 to trnccr3 = trnccr0 trndtc0 + 1 < trnccr1 to trnccr3 trndtc0 + trndtc1 (e) trnccr1 to trnccr3 = trnccr0 trndtc0 + trndtc1 < trnccr1 to trnccr3 < trnccr0 ? trndtc1 ? trndtc0 trndtt1 to trndtt3 torn1, torn3, torn5 torn2, torn4, torn6 16-bit counter 16-bit sub-counter 0000h sb3 st2 trnccr0 st1 rb5 rt1 trnccr1 to trnccr3 trndtt1 to trndtt3 torn1, torn3, torn5 torn2, torn4, torn6 16-bit counter 16-bit sub-counter 0000h sb3 st2 trnccr0 st2 rb2 rt2 trnccr1 to trnccr3 trndtt1 to trndtt3 torn1, torn3, torn5 torn2, torn4, torn6 16-bit counter 16-bit sub-counter 0000h sb3 st2 trnccr0 st2 rb2 rt2 rt2 sb2 sb2 rb2 trnccr1 to trnccr3
423 chapter 10 16-bit inverter timer/counter r user?s manual u16580ee2v0ud00 figure 10-65: compare register value after trough reload timing (3/3) (f) trnccr1 to trnccr3 = trnccr0 trnccr0 ? trndtc1 ? trndtc0 < trnccr1 to trnccr3 < trnccr0 ? trndtc1 (g) trnccr1 to trnccr3 = trnccr0 trndtc0 ? trndtc1 ? trndtc0 < trnccr1 to trnccr3 < trnccr0 table 10-5: compare register value after trough reload (trndtc1 < trndtc0) compare register value immediately before peak reload compare register value after trough reload (trndtc1 < trndtc0) figure no. trnccr0 trnccr0 ? trndtc1 trnccr1 to trnccr3 < trnccr0 figure 10-66a trnccr1 to trnccr3 < trnccr0 ? trndtc1 figure 10-66b trnccr0 ? trndtc1 2 trnccr1 to trnccr3 < trnccr0 ? trndtc1 figure 10-66c trndtc0 + trndtc1 < trnccr1 to trnccr3 < trnccr0 ? trndtc1 2 figure 10-66d trndtc0 + 1 < trnccr1 to trnccr3 < trndtc0 + trndtc1 figure 10-66e 0000h < trnccr1 to trnccr3 trndtc0 + trndtc1 figure 10-66f trnccr1 to trnccr3 = 0000h figure 10-66g trndtt1 to trndtt3 torn1, torn3, torn5 torn2, torn4, torn6 16-bit counter 16-bit sub-counter 0000h sb3 trnccr0 rb2 rt2 rt2 sb2 sb2 rb2 trnccr1 to trnccr3 ?l? trndtt1 to trndtt3 torn1, torn3, torn5 torn2, torn4, torn6 16-bit counter 16-bit sub-counter 0000h sb3 trnccr0 rb1 sb1 sb1 rb1 trnccr1 to trnccr3 ?l?
424 chapter 10 16-bit inverter timer/counter r user?s manual u16580ee2v0ud00 figure 10-66: compare register value after trough reload (trndtc1 < trndtc0) (1/3) (a) trnccr1 to trnccr3 = trnccr0 trnccr0 ? trndtc1 < trnccr1 to trnccr3 < trnccr0 (b) trnccr1 to trnccr3 = trnccr0 trnccr1 to trnccr3 = trndtc0 ? trndtc1 trndtt1 to trndtt3 torn1, torn3, torn5 torn2, torn4, torn6 16-bit counter 16-bit sub-counter 0000h sb3 sb1 rb1 trnccr0 sb1 rb1 ?l? trnccr1 to trnccr3 trndtt1 to trndtt3 torn1, torn3, torn5 torn2, torn4, torn6 16-bit counter 16-bit sub-counter 0000h sb3 sb1 rb1 trnccr0 sb1 rb4 ?l? trnccr1 to trnccr3
425 chapter 10 16-bit inverter timer/counter r user?s manual u16580ee2v0ud00 figure 10-66: compare register value after trough reload (trndtc1 < trndtc0) (2/3) (c) trnccr1 to trnccr3 = trnccr0 trnccr0 ? trndtc1 x 2 < trnccr1 to trnccr3 < trnccr0 ? trndtc1 when the values of trnccr1 to trnccr3 are changed from ?trnccr0 ? trndtc1 < trnccr1 to trnccr3 trnccr0? to ?trnccr0 ? trndtc1 2 < trnccr1 to trnccr3 < trnccr0 ? trndtc1?, the n egative phase will be 100% output for one cycle, as shown in figure below. to prevent this phenomenon, change ?trnccr0 ? trndtc1 < trnccr1 to trnccr3 trnccr0? to ?trndtc0 < tr nccr1 to trnccr3 < trndt1 2? through ?trnccr0 ? trndtc1?, or directly change ?trnccr0 ? trndtc1 < trnccr1 to trnccr3 < trnccr0? to ?trnccr1 to trnccr3 trnccr0 ? trndtc1 2?. (d) trnccr1 to trnccr3 = trnccr0 trndtc0 + trndtc1 < trnccr1 to trnccr3 < trnccr0 ? trndtc1 x 2 trndtt1 to trndtt3 torn1, torn3, torn5 torn2, torn4, torn6 16-bit sub-counter 16-bit sub-counter 0000h sb3 sb1 rb1 trnccr0 sb1 rt2 ?l? trnccr1 to trnccr3 rb1 rt2 trndtt1 to trndtt3 torn1, torn3, torn5 torn2, torn4, torn6 16-bit counter 16-bit sub-counter 0000h sb3 st2 rb3 trnccr0 sb2 rt2 trnccr1 to trnccr3 rb2 st2 st2 rt2 sb2 rb2
426 chapter 10 16-bit inverter timer/counter r user?s manual u16580ee2v0ud00 figure 10-66: compare register value after trough reload (trndtc1 < trndtc0) (3/3) (e) trnccr1 to trnccr3 = trnccr0 trndtc0 + 1 < trnccr1 to trnccr3 trndtc0 + trndtc1 (f) trnccr1 to trnccr3 = trnccr0 0000h < trnccr1 to trnccr3 trndtc0 + 1 (g) trnccr1 to trnccr3 = trnccr0 trnccr1 to trnccr3 = 0000h trndtt1 to trndtt3 torn1, torn3, torn5 torn2, torn4, torn6 16-bit counter 16-bit sub-counter 0000h sb3 st2 rb3 trnccr0 rt2 trnccr1 to trnccr3 rb2 st2 st2 rt2 rb2 trndtt1 to trndtt3 torn1, torn3, torn5 torn2, torn4, torn6 16-bit counter 16-bit sub-counter 0000h sb3 st2 rb3 trnccr0 rt1 trnccr1 to trnccr3 st1 st1 rt1 trndtt1 to trndtt3 torn1, torn3, torn5 torn2, torn4, torn6 16-bit counter 16-bit sub-counter 0000h sb3 st2 rb3 trnccr0 trnccr1 to trnccr3 st3 st3
427 chapter 10 16-bit inverter timer/counter r user?s manual u16580ee2v0ud00 figure 10-67: compare register value after trough reload (1/3) (a) trnccr1 to trnccr3 = 0000h trnccr1 to trnccr3 = trnccr0 (b) trtrnccr1 to trnccr3 = 0000h trnccr0 ? trndtc1 < trtrnccr1 to trnccr3 < trnccr0 table 10-6: compare register value after trough reload compare register value immediately before peak reload compare register value after trough reload figure no. 0000h trnccr1 to trnccr3 = trnccr0 figure 10-67a trnccr0 ? trndtc1 < trnccr1 to trnccr3 < trnccr0 figure 10-67b trnccr1 to trnccr3 = trnccr0 ? trndtc1 figure 10-67c trnccr0 ? trndtc0 ? trndtc1 trnccr1 to trnccr3 < trnccr0 ? trndtc1 figure 10-67d trndtc0 + trndtc1 < trnccr1 to trnccr3 < trnccr0 ? trndtc0 ? trndtc1 figure 10-67e trndtc0 + 1 < trnccr1 to trnccr3 trndtc0 + trndtc1 figure 10-67f 0000h < trnccr1 to trnccr3 trndtc0 + 1 figure 10-67g trndtt1 to trndtt3 torn1, torn3, torn5 torn2, torn4, torn6 16-bit counter 16-bit sub-counter 0000h rt5 sb2 trnccr0 trnccr1 to trnccr3 trndtt1 to trndtt3 torn1, torn3, torn5 torn2, torn4, torn6 16-bit counter 16-bit sub-counter 0000h sb2 rb1 trnccr0 sb1 rt5 trnccr1 to trnccr3
428 chapter 10 16-bit inverter timer/counter r user?s manual u16580ee2v0ud00 figure 10-67: compare register value after trough reload (2/3) (c) trnccr1 to trnccr3 = 0000h trnccr1 to trnccr3 = trnccr0 ? trndtc1 (d) trnccr1 to trnccr3 = 0000h trnccr0 ? trndtc0 ? trndtc1 < trnccr1 to trnccr3 < trnccr0 ? trndtc1 (e) trnccr1 to trnccr3 = 0000h trndtc0 + trndtc1 < trnccr1 to trnccr3 trnccr0 ? trndtc0 ? trndtc1 trndtt1 to trndtt3 torn1, torn3, torn5 torn2, torn4, torn6 16-bit counter 16-bit sub-counter 0000h sb2 rb1 trnccr0 sb1 rt1 trnccr1 to trnccr3 rb1 trndtt1 to trndtt3 torn1, torn3, torn5 torn2, torn4, torn6 16-bit counter 16-bit sub-counter 0000h sb2 rb2 trnccr0 sb2 rt1 trnccr1 to trnccr3 rb2 rt1 trndtt1 to trndtt3 torn1, torn3, torn5 torn2, torn4, torn6 16-bit counter 16-bit sub-counter 0000h sb2 rb2 trnccr0 sb2 rt2 trnccr1 to trnccr3 rb2 rt2 st2 st2
429 chapter 10 16-bit inverter timer/counter r user?s manual u16580ee2v0ud00 figure 10-67: compare register value after trough reload (3/3) (f) trnccr1 to trnccr3 = 0000h trndtc0 + 1 < trnccr1 to trnccr3 < trndtc0 + trndtc1 (g) trnccr1 to trnccr3 = 0000h 0000h < trnccr1 to trnccr3 trndtc0 + 1 trndtt1 to trndtt3 torn1, torn3, torn5 torn2, torn4, torn6 16-bit sub-counter 16-bit sub-counter 0000h ?l? rb2 trnccr0 rt2 trnccr1 to trnccr3 rb2 rt2 st2 st2 trndtt1 to trndtt3 torn1, torn3, torn5 torn2, torn4, torn6 16-bit counter 16-bit sub-counter 0000h ?l? trnccr0 rt1 trnccr1 to trnccr3 rt1 st1 st1
430 chapter 10 16-bit inverter timer/counter r user?s manual u16580ee2v0ud00 (9) dead time control in high-accuracy t-pwm mode in the high-accuracy t-pwm mode, the trnccr1 to trnccr3 registers are used for duty setting and the trnccr0 register is used for cycle setting. by using these four registers, duty variable type 6-phase pwm waveform can be output. to implement dead time control, there are three 10- bit down-counters that synchronously operate with the count clock of the 16-bit counter, and two dead time setting registers (trndtc0, trndtc1). the trndtc0 register is used to set the dead time from when a negative phase changes to inac- tive until a positive phase changes to active. th e trndtc1 register is used to set the dead time from when a positive phase changes to inacti ve until a negative phase changes to active. the output waveform in case of trndtc0 = x, trndtc1 = y is shown below. figure 10-68: output waveform example when dead time is set trndtt1 torn1 torn2 trndtt2 torn3 torn4 trndtt3 torn5 torn6 ?l? ?l? trnccr1 trnccr2 trndtc0 = ?x? trndtc1 = ?y? 16-bit counter 16-bit sub-counter x y xy x y x ?l? trnccr1 trnccr1 trnccr1 trnccr2 snccr2 trnccr3 trnccr3 trnccr3
431 chapter 10 16-bit inverter timer/counter r user?s manual u16580ee2v0ud00 (10) cautions on dead time control in high-accuracy t-pwm mode (a) rewriting of trndtc0 and trndtc1 registers the setting of the dead time in the trndtc0, trndtc1 registers can be rewritten during opera- tion. note the following cautions when rewriting the dead time setting during operation. cautions: 1. rewrite the trndtc0 and trndtc1 registers when using the reload function (trncms = 0). 2. when the trndtc0 and trndtc1 registers are rewritten, carrier-wave cycles will be changed. in cases where carrier-wave cycles should not be changed, rewrite the trnccr0 register value at the sam e time as changing the trndtc0 and trndtc1 registers. 3. rewriting is prohibited when trncms = 1. 4. in case of changing trnccr0 and trnccr1 at a 16-bit counter peak: match interrupts (inttrncc1 to inttrncc5) will not occur immediately after reload execution if the values set in the trnccr1 to trnccr5 register matches with and trnccr0 ? trndtc1 (the new maximum value of main counter) after updating. figure 10-69: dead time control in high-accuracy t-pwm mode 5. in case of changing tr0dtc0 at a 16-bit counter trough: match interrupts (inttrncc1 to inttrncc5) will not occur immediately after reload execution if the values set in the trnccr1 to trnccr5 register match with tr0dtc0 (the new minimum value of main counter) after updating. inttrncc1 trnccr1 16-bit counter 16-bit sub-counter trnccr0 trnccr0 to trndtc1 0000h reload execution inttrncc1 trnccr1 16-bit counter 16-bit sub-counter trnccr0 trndtc0 0000h reload execution
432 chapter 10 16-bit inverter timer/counter r user?s manual u16580ee2v0ud00 (11) caution on rewriting cycles in high-accuracy t-pwm mode in high-accuracy t-pwm mode, setting conditi ons for the trnccr0, trndtc0, and trndtc1 registers are as follows. ? 3 max (trndtc0, trnd tc1) + min (trndtc0, trndtc1) < trnccr0 0002h < trnccr0 fffeh ? max (a, b) indicates the greater value of a and b, and min (a, b) indicates the smaller value of a and b. figure 10-70 shows an operation example when the setting range is exceeded. this example shows the case where the trndtc0 register is set out of the range ?trndtc0 trnccr0 ? trndtc1?. though the 16-bit counter executes count-down operation, the count- down operation is executed from 0000h because no match occurs. in this case, the count opera- tion continues by loading the tr ndtc0 register setting value. however, no match with trnccr0 ? trndtc1 occurs in the count-up operation, thus the 16-bit counter overflows. in this case, the count operation continues by loading the trndtc0 register setting value again. an overflow interrupt (inttrnov) occurs when the 16-bit counter loads the trndtc0 register setting value from 0000h or when an overflow occurs at fffeh, and then the trnovf flag is set. an overflow interrupt (inttrnov) does not occur if the trnccr0, trndtc0, and trndtc1 reg- isters are set correctly, so this can be used for detecting incorrect settings. figure 10-70: operation example setting is out of range fffeh 0000h trndtc0 trnccr0 to trndtc1 16-bit counter 16-bit sub-counter inttrnov changed to ?trndtc0 trnccr0 trndtc1? (out of settable range)
433 chapter 10 16-bit inverter timer/counter r user?s manual u16580ee2v0ud00 (12) error interrupt (inttrner) in high-accuracy t-pwm mode the positive/negative simultaneous active detection function can be used in the high-accuracy t-pwm mode. error interrupts (inttrner) do not occur in the high-accuracy t-pwm mode. in case of occurrence, the internal circuits may be damaged. figure 10-71: error interrupt operation example 16-bit counter torn1 torn2 inttrner trntbf damage occurrence in torn2 control circuit error interrupt output positive/negative simultaneous active detection flag set ?0? write clear
434 chapter 10 16-bit inverter timer/counter r user?s manual u16580ee2v0ud00 10.10.10 pwm mode with dead time (1) outline of pwm mode with dead time in the pwm mode with dead time, 6-phase pwm is generated using the 16-bit counter?s saw tooth wave operation and four 16-bit counters. the counter?s maximum value is set with the trnccr0 register. the duties of the u phase, v phase, and w phase voltage data signals are set with the trnccr1 to trnccr3 registers. the dead time is set with the trndtc0 and trndtc1 registers, and the dead time for inverted phase normal phase and the dead time for normal phase inverted phase can be independently set with the trndtc0 register and trndtc1 register, respectively. the counter?s operation consists in performing up count with 0000h as the minimum value, and when the maximum value (cycle) indicated by the trnccr0 register is matched, the counter is cleared (0000h), and the counter continues up-count operation. the 10-bit dead time counters (trndtt1 to trndtt3) reload the setting value of the trndtc0 and trndtc1 registers upon a match between the counter and the trnccr1 to trnccr3 registers, and perform down count. upon a match between the 16-bit counter a nd the trnccr0 to trnccr3 registers, the corresponding compare match interrupts (inttrncc1 to inttrncc3) are output. figure 10-72: block diagram in pwm mode with dead time trnccr0 to1 to2 to3 to4 to5 to6 torn1(u) torn2(u) torn3(v) torn4(v) torn5(w) torn6(w) inttrncc0 inttrncd0 0001h 0001h 0001h trnccr0+trndtc0 load sel clear load load load trncnt (16-bit up counter + 1) trnsbc (16-bit up counter + 1) trnccr1 (u phase output data) trnccr2 (v phase output data) trnccr3 (w phase output data) trndtt1 (10-bit counter) trndtt2 (10-bit counter) trndtt3 (10-bit counter) trndtc0,1 (dead time value)
435 chapter 10 16-bit inverter timer/counter r user?s manual u16580ee2v0ud00 (2) pwm mode with dead time operation list (a) compare registers (b) input pins (c) output pins (d) interrupts register rewrite method rewrite during operation function trnccr0 reload possible cycle trnccr1 to trnccr3 reload possible pwm duty trnccr4, trnccr5 reload possible pwm duty pin function tir1m - (m = 0 to 3) ttrgr1 - tevtr1 - pin function torn0 toggle output upon trnccr0 register compare match torn1 pwm output (with dead time) upon trnccr1 register compare match torn2 inverted phase output to torn1 torn3 pwm output (with dead time) upon trnccr2 register compare match torn4 inverted phase output to torn3 torn5 pwm output (with dead time) upon trnccr3 register compare match torn6 inverted phase output to torn5 torn7 pulse output through a/d conversion trigger interrupt function inttrnccm trnccrm register compare match (m = 0 to 5) inttrnov - inttrner error
436 chapter 10 16-bit inverter timer/counter r user?s manual u16580ee2v0ud00 figure 10-73: output waveform example in pwm mode with dead time remarks: 1. the maximum value that can be set to the trnccr1 to trnccr3 registers is trnccr0 + trndtc0. 2. if ?0000h? is set to the trnccr1 to trnccr3 registers, pwm is output with 0% duty. 3. if trnccr0 + trndtc0 is set to the trnccr 1 to trnccr3 registers, pwm is output with 100% duty. 4. the maximum value of the trnccr0 register is ffffh - trndtc0. 5. perform setting so as to satisfy condition ffffh > trnccr0 + trndtc0. i j k ffffh 0h trnccr0 trnccr1 trnccr2 trnccr3 trndtc0 d0 trndtc1 d1 d0 d0 d1 d0 d0 d1 d0 d0 d1 d1 i j m d1 trndtt1 trndtt2 trndtt3 torn1 torn2 torn3 torn4 torn5 torn6 counter m (for cycle setting) i (u phase duty) j (v phase duty) k (w phase duty) u phase output width = i - d0 u phase output width = i + d1 v phase output width = j - d0 v phase output width = j + d1 w phase output width = k - d0 w phase output width = k + d1
437 chapter 10 16-bit inverter timer/counter r user?s manual u16580ee2v0ud00 (3) pwm mode with dead time settings (a) mode setting the pwm mode with dead time is set by setting trnctl1 register bits trnmd4 to trnmd0 = 1001. (b) output level/output enable settings output level/output enable is set by setting the trnol0 to trnol7 and trnoe0 to trnoe7 bits of the trnioc0 and trnioc3 registers. pin torn0 performs toggle output upon cycl e match (match between the counter and the trnccr0 register). pin torn7 is the output for a/d conversion. set this pin as required. (c) error output enable set error output enable when normal phase/inverted phase simultaneous active is detected. error output is enabled by setting trnioc4 register bit trneoc to 1. moreover, the pin for detecting simultaneous active can also be set, by setting trnioc4 register bits trntba2 to trntba0. in the pwm mode with dead time, inttrner does not become active, regardless of which value the user sets to the trnccr0 to trnccr3 registers, except when the dead time setting is 0. when an error occurs, this indicates an internal circuit fault. (d) interrupt and thinning out function settings a peak interrupt (inttrncd) occurs upon a match between the trnccr0 register and the counter (bit trnioe control is invalid). to output a peak interrupt, set trnice = 1. use of the thinning out function for peak interrupts is done with the trnid4 to trnid0 registers. (e) reload thinning out function setting to set the reload timing to the same timing as the interrupt timing, set trnopt1 register bit trnrde to 1. the reload timing occurs when trnice = 1. (f) a/d conversion trigger output setting a/d conversion trigger 0 (trnadtrg0 signal) is set with trnopt2 register bits trnat04, trnat02, and trnat01. the trnccr5 register match timing, trnccr4 register match timing, and peak interrupt (inttrncd) enable/disable settings are performed with bits trnat04, trnat02, and trnat01. do not set trnat05, trnat03, and trnat00 to ?1?. a/d conversion trigger 1 (trnadtrg1 signal) is set with trnopt3 register bits trnat14, trnat12, and trnat11. the trnccr5 register match timing, trnccr4 register match timing, and peak interrupt (inttrncd) enable/disable settings are performed with bits trnat14, trnat12, and trnat11. do not set bits trnat15, trnat13, and trnat10 to ?1?. set the compare values of the trnccr4 and trnccr5 registers.
438 chapter 10 16-bit inverter timer/counter r user?s manual u16580ee2v0ud00 (g) dead time settings the dead time settings are performed with the trndtc0 and trndtc1 registers. the dead time can be obtained with count clock cycle trndtc0,trndtc1. the time until torn2, torn4, torn6 pin inactive change torn1, torn3, torn5 pin active change can be set with the trndtc0 register. the time until torn1,torn3,torn5 pin inactive change torn2, torn4, torn6 pin active change can be set with the trndtc1 register. (h) pwm cycle, duty (pwm width) setting the duty is set with the trnccr1 to trnccr3 registers. the setting range of the trnccr1 to trnccr3 registers is 0000h trnccrm (trnccr0 + trndtc0) the trnccr0 and trndtc0 registers must be set so as to satisfy trnccr0 + trndtc0 < ffffh. remark: n = 0, 1 m = 1 to 3 (4) operation in pwm mode with dead time the figure shows the timing chart wh en trnccr0 = 0007h, trndtc0 = 0002h, trndtc1 = 0002h, and the trnccr0 register is set to 0000h to 0007h (one part). when the compare value of the trnccr1 register is incremented/decremented by 1 at a time, the pwm width is incremented/decremented 1 count clock at a time, but at the points indicated by arrows in the figure, incrementing/decrementing is done by trndtc1+1 count clock. this occurs when the trnccr1 register is rewritten from the setting value of the trndtc0 register to trndtc0+0001h (because dead time control is required).
439 chapter 10 16-bit inverter timer/counter r user?s manual u16580ee2v0ud00 figure 10-74: timer output example when trnce = 1 is set (initial) (pwm mode with dead time) (5) dead time control in pwm mode with dead time in the pwm mode with dead time, compare regi sters (trnccr1 to tr nccr3) are used as the duty setting registers, and ano ther compare register (trnccr0) is used as the cycle setting register. through the use of these four registers, a variable duty 6-phase pwm waveform is output. to realize dead time control, three 10-bit down counters that operate in synchronization with the counter?s count clock, and dead time setting registers (trndtc0, trndtc1) are provided. the trndtc0 register is used to set the dead time from when the inverted phase becomes inactive to when the normal phase becomes active, and the trndtc1 register is used to set the dead time from when the normal phase becomes inactive to when the inverted phase becomes active. the following figure shows an output example when trndtc0 = x, trndtc1 = y. trnccr0 torn1 torn2 ffff 0000 0001 0002 0003 0004 0005 0006 0007 0000 0001 0002 0003 0004 ffff 0008 0009 0002 0003 0004 0005 0006 0007 0008 0009 0002 0003 0004 trnce trndtc0 trndtc1 [trnccr1 = 0000h] torn1 torn2 [trnccr1 = 0001h] torn1 torn2 [trnccr1 = 0002h] torn1 torn2 [trnccr1 = 0003h] torn1 torn2 [trnccr1 = 0004h] torn1 torn2 [trnccr1 = 0005h] torn1 torn2 [trnccr1 = 0007h] torn1 torn2 [trnccr1 = 0009h] torn1 torn2 [trnccr1 = 000ah] ?l? ?h? ?l? ?l? ?l? ?l? ?l? counter sub-counter 0007h (for cycle setting) 002h (for dead time setting) 002h (for dead time setting)
440 chapter 10 16-bit inverter timer/counter r user?s manual u16580ee2v0ud00 figure 10-75: output waveform example in pwm mode with dead time trndtt1, 2, 3 trndtc0 = ?x? trndtc1 = ?y? torn1, 3, 5 torn2, 4, 6 xy xy xy trnccr0 counter
441 chapter 10 16-bit inverter timer/counter r user?s manual u16580ee2v0ud00 (6) error interrupt (inttrner) in pwm mode with dead time in the pwm mode with dead time, the normal phase/inverted phase simultaneous active detection function can be used. when using the pwm mode with dead time, no error interrupt (inttrner) is output as long as no hardware fault occurs (except when trndtc0, trndtc1 = 0000h is set). also, when trndtc0, trndtc1 = 000h is set, glitches may occur upon error interrupt (inttrner) output. in this case, the occurrence of glitches during error interrupt (inttrner) output can be prevented by setting bit trneoc to 0. figure 10-76: error interrupt (inttrner) in pwm mode with dead time torn1 torn2 inttrner trntbf ?l? counter glitches may occur during normal/inverted phase switching. the detection flag (trntbf) is not set.
442 user?s manual u16580ee2v0ud00 [memo]
443 user?s manual u16580ee2v0ud00 chapter 11 16-bit time r/event counter t 11.1 features timer t (tmt) is a 16-bit timer/event counter that provides general-purpose functions. timer t can perform the following operations. ? interval timer function ? external event count function ? one-shot pulse output function ? external trigger pulse function ? 16-bit accuracy pwm output function ? free-running function ? pulse width measurement function ? 2-phase encoder function ? triangular wave pwm output function ? offset trigger generation function 11.2 function outline ? capture trigger input signal 2 ? encoder input signal 2 ? encoder clear signal 1 ? external trigger input signal 1 ? external event input 1 ? readable counter 1 ? count write buffer 1 ? capture/compare reload register 2 ? capture/compare match interrupt 2 ? timer output (to) 2 ? capture/compare match signal 2 ? overflow interrupt 1 ? encoder clear interrupt 1
444 chapter 11 16-bit timer/event counter t user?s manual u16580ee2v0ud00 11.3 configuration timer t is configured of the following hardware. note: alternate-function pins remark: n = 0, 1 table 11-1: timer t configuration item configuration counter 16-bit counter registers tmtn capture/compare registers 0, 1 (ttnccr0, ttnccr1) tmtn counter read buff er register (ttncnt) tmtn counter write buffer register (ttntcw) ttnccr0 buffer register, ttnccr1 buffer register timer input pins 7 (titn0, titn1, tevttn, ttrgtn, tenctn0, tenctn1, tecrtn) note timer output pins 2 (totn0, totn1) note timer input signals timer output signals ttneqc0, ttneqc1 control registers tmtn control regi sters 0, 1 (ttnctl0 to ttnctl2) tmtn i/o control re gisters 0 to 2 (ttnioc0 to ttnioc3) tmtn option registers 0, 1 (ttnopt0 to ttnopt2) interrupts compare match interrupt (intttncc0, intttncc1) overflow interrupt (intttnov) encoder clear inte rrupt (intttnec)
445 chapter 11 16-bit ti mer/event counter t user?s manual u16580ee2v0ud00 note: when ttnce = 0 remark: n = 0, 1 table 11-2: list of timer t registers address register name symbol r/w manipulable bit units after reset 1816 fffff690h tmt0 control register 0 tt0ctl0 r/w 00h fffff691h tmt0 control register 1 tt0ctl1 r/w 00h fffff692h tmt0 control register 2 tt0ctl2 r/w 00h fffff693h tmt0 i/o control register 0 tt0ioc0 r/w 00h fffff694h tmt0i/o control register 1 tt0ioc1 r/w 00h fffff695h tmt0 i/o control register 2 tt0ioc2 r/w 00h fffff696h tmt0 i/o control register 3 tt0ioc3 r/w 00h fffff697h tmt0 option register 0 tt0opt0 r/w 00h fffff698h tmt0 option register 1 tt0opt1 r/w 00h fffff699h tmt0 option register 2 tt0opt2 r/w 00h fffff69ah tmt0 capture/compare register 0 tt0ccr0 r/w 0000h fffff69ch tmt0 capture/compare register 1 tt0ccr1 r/w 0000h fffff69eh tmt0 counter read buffer register tt0cnt r 0000h note fffff990h tmt0 counter write buffer register tt0tcw r/w 0000h fffff6a0h tmt1 control register 0 tt1ctl0 r/w 00h fffff6a1h tmt1 control register 1 tt1ctl1 r/w 00h fffff6a2h tmt1 control register 2 tt1ctl2 r/w 00h fffff6a3h tmt1 i/o control register 0 tt1ioc0 r/w 00h fffff6a4h tmt1i/o control register 1 tt1ioc1 r/w 00h fffff6a5h tmt1 i/o control register 2 tt1ioc2 r/w 00h fffff6a6h tmt1 i/o control register 3 tt1ioc3 r/w 00h fffff6a7h tmt1 option register 0 tt1opt1 r/w 00h fffff6a8h tmt1 option register 1 tt1opt1 r/w 00h fffff6a9h tmt1 option register 2 tt1opt2 r/w 00h fffff6aah tmt1 capture/compare register 0 tt1ccr0 r/w 0000h fffff6ach tmt1 capture/compare register 1 tt1ccr1 r/w 0000h fffff6aeh tmt1 counter read buffer register tt1cnt r 0000h note fffff9a0h tmt1 counter write buffer register tt1tcw r/w 0000h
446 chapter 11 16-bit timer/event counter t user?s manual u16580ee2v0ud00 figure 11-1: block diagram of timer t remark: n = 0, 1 m = 0, 1 clock generator /4 /8 /16 /32 /64 counter control count up/down ttnccr1 buffer to control ttnccr1 ttneqc1/ intttncc1 ttneqc0/ intttncc0 totn0 intttnov ttrgtn tevttn titn1 titn0 ttnccr1 ttnccr0 edge detector load ttnccr0 buffer load totn1 ttnccr0 clear clear encoder clock generator tenctn0 tenctn1 tecrtn load ttntcw intttnec load /256 /1024 /2 ttncnt counter internal bus internal bus
447 chapter 11 16-bit ti mer/event counter t user?s manual u16580ee2v0ud00 (1) tmtn capture/compare register 0 (ttnccr0) the ttnccr0 register is a 16-bit register that functions bot h as a capture register and as a compare register. this register can be read and written in 16-bit units only. reset input clears this register to 0000h. figure 11-2: tmtn capture/compare register 0 (ttnccr0) the capture and compare functions are as follows in each mode. notes: 1. the batch write reload timing is the counter underflow timing only. 2. the condition is set with the ttnecm0 and ttnecm1 bits of the ttnctl2 register. remark: n = 0, 1 after reset: 0000h r/w add ress: tt0ccr0 fffff69ah, tt1ccr0 fffff6aah 1514131211109876543210 ttnccr0 table 11-3: capture/compare functions in each mode operation mode capture/ compare setting of ttnccr0 register rewriting method during compare counter clear function interval mode compare only anytime write compare match external event count mode compare only anytime write compare match external trigger pulse output mode compare only batch write (reload) compare match one-shot pulse mode compare only anytime write compare match pwm mode compare only batch write (reload) compare match free-running mode capture/compare selectable anytime write - pulse width measurement mode capture only - external input (titn0 pin) triangular wave pwm mode compare only batch write (reload) note 1 compare match encoder compare mode compare only anytime write depends on set condition note 2 offset trigger generation mode capture only - external input (titn0 pin)
448 chapter 11 16-bit timer/event counter t user?s manual u16580ee2v0ud00 ? use as compare register when ttnce = 1, the ttnccr0 register rewrite method differs according to the operation mode. refer to table 11-3: capture/compare functions in each mode . (for details about the compare register rewrite operation, refer to 11.5.2 method for writing to compare register .) ? use as capture register the counter value is saved to the ttncr0 register upon titn0 pin input edge detection. the function to clear counters following capture differs according to the operation mode. refer to table 11-3: capture/compare functions in each mode . (2) tmtn capture/compare register 1 (ttnccr1) the ttnccr1 register is a 16-bit register that fu nctions both as a capture register and a compare register. this register can be read and written in 16-bit units only. reset input clears this register to 0000h. figure 11-3: tmtn capture/compare register 1 (ttnccr1) after reset: 0000h r/w address: tt0ccr1 fffff69ch, tt1ccr1 fffff6ach 1514131211109876543210 ttnccr1
449 chapter 11 16-bit ti mer/event counter t user?s manual u16580ee2v0ud00 the capture/compare functions in each operation mode are as follows. notes: 1. the batch write reload timing is the counter underflow occurrence timing only. 2. the conditions are set with bits ttnecm0 and ttnecm1 of ttnctl2 register. 3. the batch write reload timing is the counter?s 0000h clear timing only. remark: n = 0, 1 ? use as compare register when ttnce = 1, the write method of regist er ttnccr1 differs accord ing to the operation mode. refer to table 11-4: capture/compare functions in each mode . (for details about the compare register rewrite operation, refer to 11.5.2 method for writing to compare register .) ? use as capture register the counter value upon titn1 pin input edge detection is saved to the ttnccr1 register. the function to clear the counter following capture also differs according to the mode. refer to table 11-4: capture/compare functions in each mode . table 11-4: capture/compare functions in each mode operation mode capture/compare setting of ttnccr1 register rewriting method during compare counter clear function interval mode compare only anytime write - external event count mode compare only anytime write - external trigger pulse output mode compare only batch write (reload) - one-shot pulse mode compare only anytime write - pwm mode compare only batch write (reload) - free-running mode capture/compare selectable anytime write - pulse width measurement mode capture only - external input (titn1 pin) triangular wave pwm mode compare only batch write (reload) note 1 - encoder compare mode compare only anytime write depends on set conditions note 2 offset trigger generation mode compare only batch write (reload) note 3 -
450 chapter 11 16-bit timer/event counter t user?s manual u16580ee2v0ud00 (3) tmtn counter write buffer register (ttntcw) the ttntcw register is a write buffer register that can write the counter value. the setting value is valid only in the encoder compare mode, encoder capture mode. in all other modes, the setting value is invalid. this register can be read and written in 16-bit units. reset input clears this register to 0000h. remark: when ttnecc of register ttnctl2 = 0, the setting value is loaded to the counter when the ttnce bit is set (to 1). (when ttnecc = 1, the counter holds its value, so it is not reloaded.) figure 11-4: tmtn counter write buffer register (ttntcw) (4) tmtn counter read buffer register (ttncnt) the ttncnt register is a read buffer register that can read the counter value. this register can be read in 16-bit units only. reset input clears this register to 0000h. remark: when, in the encoder compare mode, encoder capture mode, the value of the ttnce bit is changed from ?1? to ?0?, the value that can be read by the ttncnt register differs according to the following conditions. ? when bit ttnecc of the ttnctl2 register = 0, 0000h can be read. ? when bit ttnecc = 1, the value held when bit ttnce was cleared to "0" can be read. figure 11-5: tmtn counter read buffer register (ttncnt) after reset: 0000h r/w address: tt0tcw fffff990h, tt1tcw fffff9a0h 1514131211109876543210 ttntcw after reset: 0000h r/w address: tt0cnt fffff69eh, tt1cnt fffff6aeh 1514131211109876543210 ttncnt
451 chapter 11 16-bit ti mer/event counter t user?s manual u16580ee2v0ud00 11.4 control registers (1) tmtn control register 0 (ttnctl0) ttnctl0 is an 8-bit register that controls the operation of tmtn. this register can be read and written in 8-bit or 1-bit units. reset input clears this register to 00h. reset input clears this register to 00h. when ttnce = 1, only the ttnce bit of the ttnctl0 register can be changed. perform write access to the other bits using the same values. figure 11-6: tmtn control register 0 (ttnctl0) (1/2) remark: n = 0, 1 after reset: 00h r/w address: tt0ctl0 fffff690h, tt1ctl0 fffff6a0h 76543210 ttnctl0ttnce0000ttncks2ttncks1ttncks0 (n = 0, 1) trnce tmtn operation control 0 internal operating clock operation disabled (tmtn reset asynchronously) 1 internal operating clock operation enabled when bit ttnce is set to ?0?, the internal operation clock of tmtn stops (fixed to low level), and tmtn is reset asynchronously. when bit ttnce is set to ?1?, the internal operation of tmtn is enabled from when bit ttnce was set to ?1? and count-up is performed . the time until count-up is as listed in table tmtn count clock and time until count-up. remarks: 1. in the encoder compare mode, encoder capture mode, the functions that are reset when ttnce = 0 and ttnecc = 1 are as follows. ? compare match detector (int errupt output low level) ? timer output (output inactive level) ? edge detector for other than pins tenctn0, tenctn1, and tecrtn 2. the following functions are not reset. ? counter ? flags in ttnopt1 register ? ttnccr0 buffer, ttnccr1 buffer register, counter read buffer register ? tenctn0, tenctn1, tecrtn pin edge detector 3. in modes other than the above, (in which ttnecc is fixed to 0), the functions that are reset by ttnce = 0 are as follows. ? internal registers other than register s that can be written from the cpu, and internal latch circuits
452 chapter 11 16-bit timer/event counter t user?s manual u16580ee2v0ud00 figure 11-6: tmtn control register 0 (ttnctl0) (2/2) remarks: 1. f xx : system clock 2. f tmtn : base clock of tmtn (f tmtn = f xx /2) 3. n = 0, 1 ttncks2 ttncks1 ttncks0 internal count clock selection 000 f xx /2 001 f xx /4 010 f xx /8 011 f xx /16 100 f xx /32 101 f xx /64 110 f xx /256 111 f xx /1024 table 11-5: tmtn count clock and count delay count clocks ttncks2 ttncks1 ttncks0 count delay minimum maximum f xx /2 0 0 0 3 base clocks 4 base clocks f xx /4001 f xx /8010 f xx /16 0 1 1 4 base clocks 5 base clocks + 1 count clock f xx /32100 f xx /64101 f xx /256 1 1 0 f xx /1024111
453 chapter 11 16-bit ti mer/event counter t user?s manual u16580ee2v0ud00 (2) tmtn control register 1 (ttnctl1) the ttnctl1 register is an 8-bit register that controls the operation of tmtn. this register can be read and written in 8-bit or 1-bit units. reset input clears this register to 00h. set the ttnctl1 register when ttnce = 0. when ttnce = 1, the bits other than bit ttnest (ttneee, ttnmd3 to ttnmd0, ttnsye) can be wr ite accessed using the same value. caution: in the one-shot pulse mode and external trigger pulse output mode, write access using "1", the same value as that of bit ttnest, functions as one trigger. figure 11-7: tmtn control register 1 (ttnctl1) (1/2) caution: rewrite the ttn eee bit only when ttnce = 0. (the same value can be written when ttnce = 1.) the operation is not guaranteed if rewriting is performed when ttnce = 1. if rewriting was mistakenly performed, set ttnce = 0 and then set the bit again. remark: n = 0, 1 after reset: 00h r/w addre ss: tr0ctl1 fffff691h, tr1ctl1 fffff6a1h 76543210 ttnctl1 0 ttnest ttneee 0 ttn md3 ttnmd2 ttnmd1 ttnmd0 (n = 0, 1) ttnest software trigger control 0 no operation 1 enable software trigger control ? in one-shot pulse mode (one-shot pulse software trigger) can be made to function as a software trigger by setting ttnets to 1 when ttnce = 1. always write tt nest = 1 when ttnce = 1. ? in external trigger pulse output mode (pulse output software trigger) remark: ?0? is always read out from the ttnest bit. ttneee count clock selection 0 use of clock selected with bits tt ncks2 to ttncks0 of ttnctl0 register 1 use of external clock (tevttn pin input edge) specification of the valid edge when ttneee = 1 (external cloc k: tevttn pin) is set with bits ttnees1 and ttnees0 of ttnioc2 register.) remark: the setting of bit ttneee is invalid in the external even t count mode, encoder compare mode, encoder capture mode, encoder capture/compare mode.
454 chapter 11 16-bit timer/event counter t user?s manual u16580ee2v0ud00 figure 11-7: tmtn control register 1 (ttnctl1) (2/2) caution: rewrite the ttnmd3 to ttnmd0 bits only when ttnce = 0. (the same value can be written when ttnce = 1.) the operation is not guaranteed if rewriting is performed when ttnce = 1. if rewriting was mistakenly performed, set ttnce = 0. remark: n = 0, 1 ttnmd3 ttnmd2 ttnmd1 ttnmd0 timer mode 0000interval mode 0001external event count mode 0010external trigger pulse output mode 0011one-shot pulse mode 0100pwm mode 0101free-running mode 0110pulse width measurement mode 0111triangular wave pwm mode 1000encoder compare mode 1100offset trigger generation mode other than above setting prohibited
455 chapter 11 16-bit ti mer/event counter t user?s manual u16580ee2v0ud00 (3) tmtn control register 2 (ttnctl2) the ttnctl2 register is an 8-bit register that controls the operation of tmtn. this register can be read and written in 8-bit or 1-bit units. reset input clears this register to 00h. the settings of the ttnctl2 register are valid only in the encoder compare mode. the settings of this register are invalid in all other modes. set the ttnctl2 register when ttnce = 0. when ttnce = 1, write access to the ttnctl2 register can be performed with the same value. figure 11-8: tmtn control register 2 (ttnctl2) (1/2) remark: n = 0, 1 after reset: 00h r/w addre ss: tr0ctl1 fffff692h, tr1ctl1 fffff6a2h 76543210 ttnctl2 ttnecc 0 0 ttnlde ttnecm1 ttnecm0 ttnuds1 ttnuds0 (n = 0, 1) ttnecc selection of initialization/hold of counter value when ttnce = 0 0 initialize counter value when ttnce = 0 1 hold counter value when ttnce = 0 when ttnecc = 0, setting ttnce = 0 causes the counter to be re set to ffffh, the capture registers (ttnccr0/ttnccr1) to be re set to 0000h, and the encoder-dedicated flags (ttneof/ttneuf/ttnesf) to be reset to 0. when ttnecc = 0, the value of the ttntcw register is loaded to the counter when ttnce is set from 0 to 1. when ttnecc = 1, setting ttnce = 0 causes th e values of the counter, capture registers (ttnccr0/ttnccr1), and enco der dedicated flags (ttneo f/ttneuf/ttnesf) to be held. when ttnecc = 1, the value of the ttnt cw register is not loaded to the counter. remark: the setting of bit ttnecc is valid in the encoder compare mode. ttnlde encoder load enable 0 disable transfer of compare setting value to counter 1 enable transfer of compare setting value (ttnccr0) to counter when underflow occurs remark: the setting of bit ttnlde is valid in the encoder compare mode and bits ttnecm1 and ttnecm0 are set as follows. ? ttnecm1 = 0, ttnecm0 = 0 or 1 ttnecm1 encoder clear mode on match of counter and ttnccr1 register 0 no clear condition 1 when the counter and ttnccr1 register match, clear the counter if the next count is a down count (ttnesf = 1) remark: the setting of bit ttnecm1 is valid in the encoder compare mode.
456 chapter 11 16-bit timer/event counter t user?s manual u16580ee2v0ud00 figure 11-8: tmtn control register 2 (ttnctl2) (2/2) remarks: 1. when bits ttnuds1 and ttnuds0 are set to 10b or 11b, the settings of bits ttneis1 and ttneis0 of the ttnioc3 register are invalid, and these bits are fixed to the setting for detection of both edges. 2. n = 0, 1 ttnecm0 encoder clear mode on match of counter and ttnccr0 register 0 no clear condition 1 when the counter and ttnccr0 register ma tch, clear the counter if the next count is a down count (ttnesf = 0) remark: the setting of bit ttnecm0 is valid in the encoder compare mode. ttnuds1 ttnuds0 encoder operation mode 0 0 upon detection of the valid edge of the a phase of encoder input (tenctn0 pin), the following count operation is performed in the b phase of encoder input. ? when "high", count down. ? when "low", count up. 0 1 count up upon detection of valid edge of a phase of encoder input (tenctn0 pin). count down upon detection of valid edge of b phase of encoder input (tenctn1 pin). 1 0 count up at rising edge of a phase of encoder input (tenctn0 pin). count down at falling edge of a phase of encoder input. however, count operation is performed only when b phase of encoder input (tenctn1 pin) is ?low?. 1 1 detection of both edges of phase a of encoder input (tenctn0 pin)/phase b of encode r input (tenctn1 pin). judgment of count operation based on combination of detection edge and input level.
457 chapter 11 16-bit ti mer/event counter t user?s manual u16580ee2v0ud00 (4) tmtn i/o control register 0 (ttnioc0) the ttnioc0 register is an 8-bit register that controls timer output (totn0 and totn1 pins). this register can be read and written in 8-bit or 1-bit units. reset input clears this register to 00h. set the ttnioc0 register when ttnce = 0. when ttnce = 1, write access to the ttnioc0 register can be performed using the same value. figure 11-9: tmtn i/o control register 0 (ttnioc0) remark: n = 0, 1 m = 0, 1 after reset: 00h r/w add ress: tr0ioc0 fffff693h, tr1ioc0 fffff6a3h 76543210 ttnioc00000ttnol1ttnoe1ttnol0ttnoe0 (n = 0, 1) ttnolm timer output level setting (totnm pin) 0 normal output (low level, when output is inactive.) 1 inverted output (high level, when output is inactive.) ttnoem timer output control (totnm pin) 0 timer output disabled (totnm pin output is fixed to inactive level.) 1 timer output enabled (a pulse c an be output from the totnm pin.)
458 chapter 11 16-bit timer/event counter t user?s manual u16580ee2v0ud00 (5) tmtn i/o control register 1 (ttnioc1) the ttnioc1 register is an 8-bit register that controls the valid edge of capture input (titn1 and titn0 pins). this register can be read and written in 8-bit or 1-bit units. reset input clears this register to 00h. set the ttnioc1 register when ttnce = 0. when ttnce = 1, write access to the ttnioc1 register can be performed using the same value. figure 11-10: tmtn i/o control register 1 (ttnioc1) remark: n = 0, 1 after reset: 00h r/w address: tr0ioc1 fffff694h, tr1ioc1 fffff6a4h 76543210 ttnioc1 0 0 0 0 ttnis3 ttnis2 ttnis1 ttnis0 (n = 0, 1) ttnis3 ttnis2 capture input (titn1) valid edge setting 0 0 no edge detection (capture operation invalid) 0 1 rising edge detection 1 0 falling edge detection 1 1 both, rising and falling edge detection capture operation is performed and capture interrupt (intttncc1) is output upon edge detection. remark: the setting of bits ttnis3 and ttnis2 are valid in the free-running mode and pulse width measurement mode. ttnis1 ttnis0 capture input (titn0) valid edge setting 0 0 no edge detection (capture operation invalid) 0 1 rising edge detection 1 0 falling edge detection 1 1 both, rising and falling edge detection capture operation is performed and capture interrupt (intttncc0) is output upon edge detection. remark: the setting of bits ttnis1 and ttnis0 are valid in the free-running mode and pulse width measurement mode.
459 chapter 11 16-bit ti mer/event counter t user?s manual u16580ee2v0ud00 (6) tmtn i/o control register 2 (ttnioc2) the ttnioc2 register is an 8-bit register that controls the valid edge of external event count input (tevttn pin) and external trigger input (ttrgtn pin). this register can be read and written in 8-bit or 1-bit units. reset input clears this register to 00h. set the ttnioc2 register when ttnce = 0. when ttnce = 1, write access to the ttnioc2 register can be performed using the same value. figure 11-11: tmtn i/o control register 2 (ttnioc2) remark: n = 0, 1 after reset: 00h r/w add ress: tr0ioc2 fffff695h, tr1ioc2 fffff6a5h 76543210 ttnioc20000ttnees1ttnees0ttnets1ttnets0 (n = 0, 1) tt1ees1 tt1ees0 external event counte r input (tevttn) valid edge setting 0 0 no edge detection (capture operation invalid) 0 1 rising edge detection 1 0 falling edge detection 1 1 both, rising and falling edge detection remark: the settings of bits ttnees1 and ttn ees0 are valid in the external event count mode, or when bit ttneee of the ttnctl1 register = 1. tt1ets1 tt1ets0 external trigger in put (ttrgtn) valid edge setting 0 0 no edge detection (capture operation invalid) 0 1 rising edge detection 1 0 falling edge detection 1 1 both, rising and falling edge detection remark: the settings of bits ttnets1 and ttnets0 are valid in the external trigger pulse output mode and the one-shot pulse mode.
460 chapter 11 16-bit timer/event counter t user?s manual u16580ee2v0ud00 (7) tmtn i/o control register 3 (ttnioc3) the ttnioc3 register is an 8-bit register that controls the valid edge of encoder clear input (tecrtn pin) and encoder input (tenctn1 and tenctn0 pins). this register can be read and written in 8-bit or 1-bit units. reset input clears this register to 00h. set the ttnioc3 register when ttnce = 0. when ttnce = 1, write access to the ttnioc2 register can be performed using the same value. figure 11-12: tmtn i/o control register 3 (ttnioc3) (1/2) remark: n = 0, 1 after reset: 00h r/w address: tr0ioc3 fffff696h, tr1ioc3 fffff6a6h 76543210 ttnioc3 ttnsce ttnzcl ttnbcl ttnac l ttnecs1 ttnecs0 ttneis1 ttneis0 (n = 0, 1) ttnsce selects the encode r counter clear method 0 clear upon detection of edge of tecrtn pin 1 clear upon match of clear condition level when ttnsce = 1, the counter is cleared to 0000h if all the conditions set with bits ttnzcl, ttnbcl, and ttnacl are matched. when ttnsce = 1, the se ttings of bits ttnecs 1 and ttnecs0 are invalid, so no encoder clear interrupt (intttnec) is output. when ttnsce = 0, the settings of bits tt nzcl, ttnbcl, and ttnacl are invalid. the settings of bits ttnecs1 and ttnecs0 become valid, and the encoder clear interrupt (intttnec) is output. caution: when ttnsce = 1, be sure to set bits ttnuds1, and ttnuds0 of the ttnctl2 register to 10b or 11b. ttnzcl sets the clear level for the z phase of encoder input (tecrtn pin) 0 clear condition = low level 1 clear condition = high level remark: the ttnzcl bit is valid when ttnsce = 1. ttnbcl sets the clear level for the b phase of encoder input (tenctn1 pin) 0 clear condition = low level 1 clear condition = high level remark: the ttnbcl bit is valid when ttnsce = 1. ttnacl sets the clear level for the a phase of encoder input (tenctn0 pin) 0 clear condition = low level 1 clear condition = high level remark: the ttnacl bit is valid when ttnsce = 1.
461 chapter 11 16-bit ti mer/event counter t user?s manual u16580ee2v0ud00 figure 11-12: tmtn i/o control register 3 (ttnioc3) (2/2) remark: n = 0, 1 ttnecs1 ttnecs0 set the valid edge of encoder clear input (tecrtn pin) 0 0 no edge detection 0 1 rising edge detection 1 0 falling edge detection 1 1 both rising and falling edge detection the encoder clear interrupt (intttnec) is output upon detection of the valid edge set with bits ttnecs1, ttnecs0. caution: when ttnsce = 1, the encoder clear interrupt (intttnec) is not output. remark: bits ttnecs1 and ttnecs0 are valid in the encoder compare mode and when ttnsce = 0. ttneis1 ttneis0 set the valid edge of the encoder input signal (tenctn1/tenctn0 pins) 0 0 no edge detection 0 1 rising edge detection 1 0 falling edge detection 1 1 both rising and falling edge detection remark: bits ttneis1 and ttneis0 are valid when bits ttnuds1 and ttnuds0 of register ttnctl2 are ?00b? or ?01b?.
462 chapter 11 16-bit timer/event counter t user?s manual u16580ee2v0ud00 (8) tmtn option register 0 (ttnopt0) the ttnopt0 register is an 8-bit register that sets the capture/compare operation and detects overflow. this register can be read and written in 8-bit or 1-bit units. reset input clears this register to 00h. set the bits of the ttnopt0 register other than ttnovf when ttnce = 0. when ttnce = 1, write access of bits of the ttnopt0 register other than ttnovf can be performed using the same value. figure 11-13: tmtn option register 0 (ttnopt0) remark: n = 0, 1 after reset: 00h r/w address: tr0ioc3 fffff697h, tr1ioc3 fffff6a7h 76543210 ttnopt0 0 0 ttnccs1 ttnccs0 0 0 0 ttnovf (n = 0, 1) ttnccs1 specifies the operatio n mode of register ttnccr1 0 operation as compare register 1 operation as capture register remark: the setting of bit ttnccs1 is valid in the free-running mode only. ttnccs0 specifies the operatio n mode of register ttnccr0 0 operation as compare register 1 operation as capture register remark: the setting of bit ttnccs0 is valid in the free-running mode only. ttnovf flag that indicates tmtn overflow 0 no overflow occurrence after timer restart or flag reset 1 overflow occurrence in the free-running mode, pulse width measurement mode, and offset trigger generation mode, if the counter value is counted up from ffffh, overflow occurs, the ttnovf flag is set (1), and the counter is cleared to 0000h. the counter is also cleared by writing 0. at the same time that the ttnovf flag is set (1 ), an overflow interrupt (intttnov) occurs. if 0 is written to the ttnovf flag, or if tt necc = 0 and ttnce = 0 are set, the counter is cleared. remark: overflow does not occur during compare match & clear operation for counter value ffffh and comp are value ffffh. cautions: 1. if overflow occurs in the encoder compare mode, the encoder-dedi- cated overflow flag (ttneof) is set, and the overflow flag (ttnovf) is not set. at this time, the overflow interrupt (intttnov) is output. 2. when ttnovf = 1, the ttnovf flag is not cleared even if the ttnovf flag and ttnopt0 register are read. 3. the ttnovf flag can be read and written, but even if 1 is written to the ttnovf flag from the cpu, this is invalid.
463 chapter 11 16-bit ti mer/event counter t user?s manual u16580ee2v0ud00 (9) tmtn option register 1 (ttnopt1) the ttnopt1 register is an 8-bit register that detects encoder-dedicated underflow, overflow, and counter up/down operation. this register can be read and written in 8-bit or 1-bit units. reset input clears this register to 00h. the setting of the ttnopt1 register is valid only in the encoder compare mode. in all other modes, the setting value is invalid. figure 11-14: tmtn option register 1 (ttnopt1) (1/2) remark: n = 0, 1 after reset: 00h r/w add ress: tr0ioc3 fffff698h, tr1ioc3 fffff6a8h 76543210 ttnopt100000ttneufttneofttnesf (n = 0, 1) ttneuf indication of encoder underflow 0 no underflow indicated 1 indicates counter underflow in the encoder compare mode if the counter value is counted down from 00 00h, underflow occurs, the ovf flag is set (to 1), and the counter is set to ffffh. when t he ttneuf flag is set (to 1), an overflow interrupt (intttnov) occu rs at the same time. the ttneuf flag is cleared (to 0) under the following conditions. ? when 0 is written by cpu instruction ? when ttnce = 0 is set while ttnecc = 0 cautions: 1. the ttneuf flag is not cleared even if it is read. 2. the ttneuf flag can be read and wri tten, but even if 1 is written to the ttneuf flag, this is invalid. remark: when bit ttnecc of the ttnctl2 register is 1, the flag status is held even if the value of bit ttnce is changed from 1 to 0.
464 chapter 11 16-bit timer/event counter t user?s manual u16580ee2v0ud00 figure 11-14: tmtn option register 1 (ttnopt1) (2/2) remark: n = 0, 1 ttneof indication of encoder overflow 0 no overflow indicated 1 indicates counter overflow in the encoder compare mode if the counter value is counted up from ffff h, overflow occurs, the ovf flag is set (1), and the counter is cleared to 0000h. at the same time that the ttneof flag is set (1), an overflow interrupt (intttnov) occurs. howe ver, the ttnovf flag is not set (to 1). the ttneof flag is cleared (0) under the following conditions. ? when 0 is written by cpu instruction ? when ttnce = 0 is set while ttnecc = 0 cautions: 1. the ttneof flag is not cleared even if it is read. 2. the ttneof flag can be read and written, but even if 1 is written to the ttneof flag from the cpu, this is invalid. remark: when bit ttnecc of the ttnctl2 register is 1, the flag status is held even if the value of bit ttnce is changed from 1 to 0. ttnesf indication of encoder count direction 0 indicates the up count operation of th e counter in the encoder compare mode. 1 indicates the down count operation of the counter in the encoder compare mode. the ttnesf flag is cleared (to 0) under the following conditions. ? when ttnce = 0 is set while ttnecc = 0 remark: when bit ttnecc of the ttnctl2 register is 1, the flag status is held even if the value of bit ttnce is changed from 1 to 0.
465 chapter 11 16-bit ti mer/event counter t user?s manual u16580ee2v0ud00 (10) tmtn option register 2 (ttnopt2) the ttnopt2 register is an 8-bit register that indicates the reload request status when performing write access to compare registers using the reload method. this register can only be read in 8-bit or 1-bit units. reset input clears this register to 00h. the read contents of the ttnopt2 register are valid only in the external trigger pulse mode, pwm mode, and offset trigger generation using the reload method. in all other modes, the read contents are 0. figure 11-15: tmtn option register 2 (ttnopt2) remark: n = 0, 1 after reset: 00h r/w add ress: tr0ioc3 fffff699h, tr1ioc3 fffff6a9h 76543210 ttnopt20000000ttnrsf (n = 0, 1) ttnrsf reload status flag 0 no reload request, or reload completed 1 reload request was output it indicates that the data to be transferre d next is held pending in the ttnccr0 and ttnccr1 registers. the ttnrsf flag is set (1) by writing to the ttnccr1 register, and it is cleared (0) upon reload completion. caution: when ttnrsf = 1, do not pe rform write access to the ttnccr0 and ttnccr1 registers.
466 chapter 11 16-bit timer/event counter t user?s manual u16580ee2v0ud00 11.5 basic operation 11.5.1 basic counter operation this section describes the basic operation of the counter. for details, refer to chapter 11.6 operation in each mode . (1) counter start operation (a) encoder compare mode the count operation is controlled by the phases of pins tenctn0 and tenctn1. when ttnce = 0 and ttnecc = 0, the counter is initialized by the ttntcw register and the count operation is started. (the setting value of the ttntcw register is loaded to the counter at the timing when ttnce changes from 0 to 1.) (b) triangular wave pwm mode the counter starts counting from initial value ffffh. it counts up ffffh, 0000h, 0001h, 0002h, 0003h? following count up operation, the counter counts down upon a match with the ttnccr0 register. (c) modes other than the above the counter starts counting from initial value ffffh. it counts up ffffh, 0000h, 0001h, 0002h, 0003h? (2) counter clear operation there are the following five counter clear causes. ? clear through match between counter value and compare setting value. ? capture and clear through capture input ? counter clear through encoder clear input (tecrtn pin) ? counter clear through match with clear condition level ? clear through clear signal input (ttnsyci) for synchronization function during slave operation remark: n = 0, 1
467 chapter 11 16-bit ti mer/event counter t user?s manual u16580ee2v0ud00 note: conditions are set with bits ttnecm0 and ttnecm1 of the ttnctl2 register. (3) counter reset and hold operations in the encoder compare mode, counter value hold is controlled with bit ttnecc of the ttnctl2 register. if ttnce = 0 is set when ttnecc = 0, the counter is reset to 0000h. the setting value of the ttntcw register is loaded to the counter when ttnce = 1 is set next. if ttnce = 0 is set when ttnecc = 1, the counter value is held as is. counting resumes from the held value when ttnce = 1 is set next. (4) counter read operation during counter operation in tmt, the counter value can be read during count operation using the ttncnt register. remark: n = 0, 1 table 11-6: counter clear operation operation mode clear cause ttnccr0 ttnccr1 other interval mode compare match - - external event count mode compare match - - external trigger pulse output mode comp are match - external trigger (ttrgtn pin) one-shot pulse mode compare match - - pwm mode compare match - - free-running mode - - - pulse width measurement mode - - external input (titn0 and titn1 pins) triangular wave pwm mode compare match - - encoder compare mode depends on set conditions note depends on set conditions note pin tecrtn, clear condition level match offset trigger generation mode - - external input (titn0 pin)
468 chapter 11 16-bit timer/event counter t user?s manual u16580ee2v0ud00 (5) overflow operation counter overflow occurs in the free-running mode, pulse width measurement mode, encoder compare mode and offset trigger generation mode. overflow occurs when the counter value changes from ffffh to 0000h. in the free-running mode, pulse width measurement mode, offset trigger generation mode, the overflow flag (ttnovf) is set to 1 and an overflow interrupt (intttnov) is output. at this time, the ttneof flag is not set. in the encoder compare mode, the encoder dedicated overflow flag (ttneof) is set to 1 and an overflow interrupt (intttnov) occurs. at this time, the ttnovf flag is not set. under the following conditions, overflow does not occur. ? when the counter value changes from initia l setting ffffh to 0000h immediately after counting start ? when ffffh is set to the compare register, and the counter is cleared to 0000h upon a match between the counter value and the compare setting value. ? when, in the pulse width measurement mode and offset trigger generation mode, capture operation is performed for counter value ffffh, and the counter is cleared to 0000h. (6) underflow operation counter underflow occurs in the triangular wave pwm mode and encoder compare mode. underflow occurs when the counter value changes from 0000h to ffffh. when underflow occurs in the triangular wave pwm mode, an overflow interrupt (intttnov) occurs. at this time, the ttnovf flag is not set. in the encoder compare mode, the encoder dedicated underflow flag (ttneuf) is set to 1, and an overflow interrupt (intttnov) occurs. underflow does not occur during count down immediately following counter start. (7) description of interrupt signal operation in tmt, the following interrupt signals are output. note: in the encoder compare mode, when ttnsce = 0, an encoder clear interrupt (intttnec) is output. remark: n = 0, 1 name occurrence cause intttncc0 ? match between counter and setting value of ttnccr0 register ? capture to ttnccr0 register due to titn0 pin input intttncc1 ? match between counter and setting value of ttnccr1 register ? capture to ttnccr1 register due to titn1 pin input intttnov overflow and underflow occurrence intttnec note counter clearing through tecrtn pin
469 chapter 11 16-bit ti mer/event counter t user?s manual u16580ee2v0ud00 11.5.2 method for writing to compare register the ttnccr0 and ttnccr1 registers can be rewritten during timer operation (ttnce = 1). there are two write modes (anytime write, reload), depending on the mode. (1) anytime rewrite method when the ttnccr0 and ttnccr1 regi sters are written during timer operation, the write value is immediately transferred to the ttnccr0 buffer register and ttnccr1 buffer register and is used as the value to be compared with the counter. figure 11-16: basic operation flow for anytime rewrite remarks: 1. the interval mode is used as an example. 2. n = 0, 1 start initial settings intttncc0 occurrence ttnccr1 rewrite transfer to buffer ttnccr1 ttnccr0 rewrite transfer to buffer ttnccr0 ? match between ttnccr0 value and counter ? counter clear & start timer operation enable (ttnce = 1) values of ttnccr0 and ttnccr1 are transferred to buffers ttnccr0 and ttnccr1.
470 chapter 11 16-bit timer/event counter t user?s manual u16580ee2v0ud00 figure 11-17: basic anytime rewrite operation timing remarks: 1. d 01 , d 02 : setting values of ttnccr0 register (0000h to ffffh) d 11 , d 12 : setting values of ttnccr1 register (0000h to ffffh) 2. the interval mode is used as an example. 3. n = 0, 1 counter ttnccr0 ttnccr0 buffer ttnccr1 ttnccr1 buffer d 01 d 01 d 02 d 11 d 11 d 12 d 12 intttncc0 intttncc1 d 01 0000h d 11 d 12 d 02 ttnce d 01 d 02 0000h d 11 d 12
471 chapter 11 16-bit ti mer/event counter t user?s manual u16580ee2v0ud00 (2) reload method (batch rewrite) when ttnccr0, ttnccr1 register write is performed during timer operation, the written value is used as the comparison value for the counter via the ttnccr0 and ttnccr1 buffer registers. under the reload method, rewrite the ttnccr0 register before the ttnccr0 register value is matched, and next, write to the ttnccr1 register. then, when the ttnccr0 register is matched or the counter is cl eared to 0000h through external input, the values of the ttnccr0 regist er and ttnccr1 register are reloaded. by writing to the ttnccr1 register, the value becomes valid at the next reload timing. therefore, even if wishing to rewrite only the valu e of the ttnccr0, rewrite the same value to the ttnccr1 register to make the next reload valid. figure 11-18: basic operation flow for reload (batch rewrite) caution: rewrite to th e ttnccr1 register includes enabli ng reload. therefore, rewrite the ttnccr1 register after rewriting the ttnccr0 register. remarks: 1. the pwm mode is used as an example. 2. n = 0, 1 start initial settings reload enable intttncc0 occurrence ttnccr1 rewrite ttnccr0 rewrite ? match between ttnccr0 value and counter ? counter clear & start ? reload of value of ttnccr0 and ttnccr1 to ttnccr0 and ttnccr1 buffers timer operation enable (tt0ce = 1) values of ttnccr0 and ttnccr1 are transferred to buffers ttnccr0 and ttnccr1.
472 chapter 11 16-bit timer/event counter t user?s manual u16580ee2v0ud00 figure 11-19: basic reload operation timing note: since the ttnccr1 register is not written to, reloading is not performed even if ttnccr0 is rewritten. remarks: 1. d 01 , d 02 , d 03 : setting values of ttnccr0 register (000 0h to ffffh) d 11 , d 12 : setting values of ttnccr1 register (0000h to ffffh) 2. the pwm mode is used as an example. 3. n = 0, 1 table 11-7: capture/compare rewrite methods in each mode operation mode capture/compare rewrite method ttnccr0 ttnccr1 interval mode compare only (anytime write type) external event count mode external trigger pulse output mode compare only (reload type) one-shot pulse mode compare only (anytime write type) pwm mode compare only (reload type) free-running mode capture/compare selectable (when compare is selected, anytime write type) pulse width measurement mode capture only triangular wave pwm mode compare only (reload type) encoder compare mode compare only (anytime write type) offset trigger generation mode capt ure only compare only (reload type) d 02 counter ttnccr0 ttnccr0 buffer ttnccr1 ttnccr1 buffer intttncc0 intttncc1 d 01 d 11 0000h d 03 d 01 d 02 d 12 d 12 0000h d 11 d 12 write same value d 12 d 12 d 12 d 12 d 11 d 01 d 02 d 02 d 03 note d 12 note ttnce d 03
473 chapter 11 16-bit ti mer/event counter t user?s manual u16580ee2v0ud00 11.6 operation in each mode 11.6.1 interval timer mode in the interval timer mode, a compare match interrupt (intttncc0) occurs and the counter is cleared upon a match between the setting value of the ttnccr0 register and the counte r value. the occurrence interval for this counter and ttnccr0 register match interrupt becomes the interval time. in the interval timer mode, the counter is cleared only upon a match between the counter and the value of the ttnccr0 register. counter clearing using the ttnccr1 register is not performed. however, the setting value of the ttnccr1 is compared to the counter value transferred to the ttnccr1 buffer register and a compare match interrupt (intttncc1) is output. the ttnccr0 and ttnccr1 registers can be rewri tten using the anytime write method, regardless of the value of bit ttnce. pins totn0 and totn1 are toggle output controlled when bits ttnoe0 and ttnoe1 are set to 1. figure 11-20: basic operation flow in interval timer mode note: in the case of a match between the counter and ttnccr1 register, the counter is not cleared. start initial settings ? clock selection (ttnctl0: ttncks2 to ttncks0) ? interval mode setting (ttnctl1: ttnmd3 to ttnmd0 = 0000) ? compare register setting (ttnccr0, ttnccr1) timer operation enable (ttnce = 1) transfer of ttnccr0 and ttnccr1 values to ttnccr0 and ttnccr1 buffers match between counter and ttnccr1 buffer value note match between counter and ttnccr0 buffer value, counter clear & start intttncc1 occurrence intttncc0 occurrence
474 chapter 11 16-bit timer/event counter t user?s manual u16580ee2v0ud00 figure 11-21: basic timing in interval timer mode (1/2) (a) when d1>d2>d3, only value of ttnccr0 register is rewritten, totn0 and totn1 are not output (ttnoe0, 1 = 0, ttnol0 = 0, ttnol1 = 1) remarks: 1. d1, d2: setting values of ttnccr0 register (0000h to ffffh) d3: setting values of ttnccr1 register (0000h to ffffh) 2. interval time = (dm + 1) (count clock cycle) 3. m = 1 to 3, n = 0, 1 counter d1 d 2 intttncc0 d1 d2 d1 ffffh ttnccr1 d3 d3 d3 intttncc1 ttnccr0 d3 ttnce a: interval time (d1 + 1) ? count clock a a b totn0 totn1 low high a: interval time (d2 + 1) ? count clock
475 chapter 11 16-bit ti mer/event counter t user?s manual u16580ee2v0ud00 figure 11-21: basic timing in interval timer mode (2/2) (b) when d1 = d2, values of ttnccr0 and ttnccr1 registers not rewritten, totn1 output performed (ttnoe0, 1 = 1, ttnol0 = 0, ttnol1 = 1) remarks: 1. d1: setting value of ttnccr0 register (0000h to ffffh) d2: setting value of ttnccr1 register (0000h to ffffh) 2. interval time = (dm + 1) (count clock cycle) 3. totn0, totn1 toggle time = (dm + 1) (count clock cycle) 4. m = 1, 2, n = 0, 1 counter d1 intttncc0 d1 = d2 ffffh ttnccr1 intttncc1 ttnccr0 d2 ttnce d1 = d2 d1 = d2 interval time interval time interval time totn0 totn1
476 chapter 11 16-bit timer/event counter t user?s manual u16580ee2v0ud00 11.6.2 external event count mode in the external event count mode, count up starts upon external event input (tevttn pin). (the external event input (tevttn) is used as the c ount clock, regardless of bit ttneee of the ttnctl1 register.) in the external event count mode, the counter is cleared only upon a match between the counter and the value of the ttnccr0 register. counter clearing using the ttnccr1 register does not work. however, the value of the ttnccr1 register is tran sferred to the ttnccr1 buff er register, compared to the counter value, and a compare match interrupt (intttncc1) is output. the ttnccr0 and ttnccr1 registers can be rewritten with the anytime write method, regardless of the value of bit ttnce. pins totn0 and totn1 are toggle output controlled when bits ttnoe0 and ttnoe1 are set to 1. when using only one compare register channel, it is recommended to set the ttnccr1 register to ffffh. [external event count operation flow] <1> ttnctl1 register bits ttnmd3 to ttnmd0 = 0001b (mode setting) edge detection set with ttnioc2 register bits ttnees1 an d ttnees0 (ttnees1, ttnees0 = setting other than 01b) <2> ttnctl0 register bit ttnce = 1 (count enable) <3> tevttn pin input edge detection (count-up start) cautions: 1. in external event count mode, when the setting value of the ttnccr0 register is set to m, the number of tevttn pin input edge detection times is m+1. 2. in external event count mode, do not send the ttnccr0 register to 0000h. remark: n = 0, 1
477 chapter 11 16-bit ti mer/event counter t user?s manual u16580ee2v0ud00 figure 11-22: basic operation timing in external event count mode (1/4) (a) when d1>d2>d3, only value of ttnccr0 re gister is rewritten, totn0 and totn1 are not output. the signal input from tevttn and internally synchronized is counted as the count clock (ttnoe0, 1 = 0, ttnol0 = 0, ttnol1 = 1) remarks: 1. d1, d2: setting values of ttnccr0 register (0000h to ffffh) d3: setting value of ttnccr1 register (0000h to ffffh) 2. number of event counts = (dm + 1) (m = 1, 2) 3. n = 0, 1 counter d1 d 2 intttncc0 d1 d2 d1 ffffh ttnccr1 d3 d3 d3 intttncc1 ttnccr0 d3 ttnce totn0 totn1 low high tevttn
478 chapter 11 16-bit timer/event counter t user?s manual u16580ee2v0ud00 figure 11-22: operation timing in ex ternal event count mode (2/4) (b) when d1 = d2, ttnccr0 and ttnccr1 register values are not rewritten, totn0 and totn1 are output (ttnoe0, 1 = 1, ttnol0 = 0, ttnol1 = 1) remarks: 1. d1: setting value of ttnccr0 re gister (0000h to ffffh) d2: setting value of ttnccr1 re gister (0000h to ffffh) 2. number of event counts = (dm + 1) (m = 1, 2) 3. n = 0, 1 c ounter d1 intttncc0 d1 = d2 ffffh t tnccr1 intttncc1 t tnccr0 d2 t tnce d1 = d2 d1 = d2 t otn0 t otn1 t evttn
479 chapter 11 16-bit ti mer/event counter t user?s manual u16580ee2v0ud00 figure 11-22: operation timing in external event count mode (3/4) (c) when d1 = d2, ttnccr0 and ttnccr1 register values are not rewrit ten, totn0 and totn1 are output (ttnoe0, 1 = 1, ttnol0 = 0, ttnol1 = 1) remarks: 1. d1: setting value of ttn ccr0 register (0000h) d2: setting value of ttn ccr1 register (0000h) 2. number of event counts = (dm + 1) (m = 1, 2) 3. n = 0, 1 c ounter 0000h intttncc0 ffffh ttnccr1 intttncc1 ttnccr0 0000h ttnce totn0 totn1 0000h
480 chapter 11 16-bit timer/event counter t user?s manual u16580ee2v0ud00 figure 11-22: basic operation timing in external event count mode (4/4) (d) when d1 = d2, ttnccr0, ttnccr1 register values are not rewritten, totn0 and totn1 are output (ttnoe0, 1 = 1, ttnol0 = 0, ttnol1 = 1) remarks: 1. d1: setting value of ttn ccr0 register (0001h) d2: setting value of ttn ccr1 register (0000h) 2. number of event counts = (dm + 1) (m = 1, 2) 3. n = 0, 1 counter intttncc0 ffffh ttnccr1 intttncc1 ttnccr0 ttnce totn0 totn1 0001h 0001h 0000h
481 chapter 11 16-bit ti mer/event counter t user?s manual u16580ee2v0ud00 11.6.3 external trigger pulse output mode when, in the external trigger pulse mode, the duty is set to the ttnccr1 register, the cycle is set to the ttnccr0 register, and ttnce = 1 is set, external trigger input (ttrgtn pin) wait results, with the counter remaining stopped at ffffh. upon detection of the valid edge of external trigger input (ttrgtn pin), or when the ttnest bit of the ttnctl1 register is set, count up starts. an external trigger pulse is output from pin totn1, and toggle output is performed from pin totn0 upon a match with the ttnccr0 register. moreover, during the count operation, upon a match between the counter and the ttnccr0 register, a compare match interrupt (intttncc0) is output, and upon a match between the counte r and ttnccr1 register, a compare matc h interrupt (inttt ncc1) is output. the ttnccr0 and ttnccr1 registers can be rewritten during count operation. compare register reload is performed at the timing when the counter value and the ttnccr0 register match. however, when write access to the ttnccr1 register is performed, the next reload timing becomes valid, so that even if wishing to rewrite only the value of the ttnccr0 register, write the same value to the ttnccr1 register. in this case, reload is not performed even if only th e ttnccr0 register is rewritten. if, during operation in the external trigger pulse output mode, the external trigger (ttrgtn pin) edge is detected several times, or if the ttnest bit of the ttnctl1 register is set (to 1), the counter is cleared and count up is resumed. moreover, if at this time, the totn1 pin is in the low level status, the totn1 pin output becomes high level when an external trigge r is input. if the totn1 pin is in the high level status, it remains high level even if external trigger input occurs. in the external trigger pulse output mode, the ttnccr0 and ttnccr1 registers have their function fixed as compare registers, so the capture function cannot be used. caution: in the external trigger pulse mode, set bit ttneee of the ttnctl1 register to 0. remark: n = 0, 1
482 chapter 11 16-bit timer/event counter t user?s manual u16580ee2v0ud00 figure 11-23: basic operation flow in external trigger pulse output mode note: the counter is not cleared upon a match between the counter and the ttnccr1 buffer register. remark: n = 0, 1 start match between counter and ttnccr1 external trigger (ttrgtn pin) input counter starts counting. itttncc0 occurrence counter clear & start initial settings timer operation enable (ttnce = 1) transfer of values of ttnccr0 and ttnccr1 to buffers ttnccr0 and ttnccr1 match between counter and ttnccr0, counter clear & start external trigger (ttrgtn pin) input clock selection (ttnctl1: ttneee = 0) (ttnctl0: ttncks2 to ttncks0) external trigger pulse output mode setting (ttnctl1: ttnmd3 to ttnmd0 = 0010) compare register setting (ttnccr0, ttnccr1) itttncc1 occurrence note ? ? ?
483 chapter 11 16-bit ti mer/event counter t user?s manual u16580ee2v0ud00 figure 11-24: basic operation timing in external trigger pulse output mode (a) when values of ttnccr0 and ttnccr1 registers are rewritten, totn0 and totn1 are output (ttnoe0, 1 = 1, ttnol0, 1 = 0) remarks: 1. d 01 , d 02 : setting values of ttnccr0 register (0000h to ffffh) d 11 , d 12 : setting values of ttnccr1 register (0000h to ffffh) 2. totn1 (pwm) duty = (setting value of ttnccr1 register) (count clock cycle) totn1 (pwm) cycle = (setting value of ttnccr0 register + 1) (count clock cycle) 3. pin totn0 is toggled when the counter is cleared immediately following count start. 4. n = 0, 1 counter ttnccr1 ffffh ttnccr0 buffer ttnccr1 buffer ttnccr0 ttnce external trigger (ttrgtn pin) d 01 d 02 d 01 d 02 d 01 d 02 d 11 d 11 0000h 0000h d 12 d 12 totn0 totn1 toggle output d 11 d 12 toggle output ttnrsf flag
484 chapter 11 16-bit timer/event counter t user?s manual u16580ee2v0ud00 11.6.4 one-shot pulse mode when, in the one-shot pulse mode, the duty is set to the ttnccr0 register, the output duty delay value is set to the ttnccr1 register, and bit ttnce of the ttnctl0 register is set to 1, external trigger input (ttrgtn pin) wait results, with the counter remaining stopped at ffffh. upon detection of the valid edge of external trigger input (ttrgtn pin), or when bit ttnest of the ttnctl0 register is set to 1, count up starts. the totn1 pin becomes high le vel upon a match betwe en the counter and ttnccr1 register. moreover, upon a matc h between the counter and ttnccr0 register, the totn1 pin becomes low level, and the counter is cleared to 0000h and then stops. the totn0 pin performs toggle output during the count operation upon a match between the counter and the ttnccr0 buffer register. moreover, upon a match between the counter and ttnccr0 register during count operation, a compare match interrupt (intttncc0) is output, and upon a match between the counter and ttnccr1 buffer register, a compare ma tch interrupt (intttncc1) is output. the ttnccr0 and ttnccr1 registers can be rewritte n using the anytime write method, regardless of the value of bit ttnce. even if a trigger is input during the counter operation, it is ignored. be sure to input the second trigger when the counter is stopped at 0000h. in the one-shot pulse mode, registers ttnccr0 and ttnccr1 have their function fixed as compare registers, so the capture function cannot be used. [one-shot pulse operation flow] <1> ttnctl1 register bits ttnmd3 to ttnmd0 = 0011b (one-shot pulse mode) <2> ttnccr0 register setting (duty setting), ttnioc0 register bit ttnoe1 = 1 (totn1 pin output enable) <3> ttnctl0 register bit ttnce = 1 (counter operation enable): totn1 = low-level output <4> ttnctl1 register bit ttnest = 1 or ttrgtn pin edge detection (count-up start): totn1 = low-level output <5> match between counter value and ttnccr1 buffer register: totn1 = high-level output <6> match between counter value and ttnccr0 buffer register: totn1 = low-level output, count clear <7> count stop: totn1 = low-level output <8> ttnce = 0 (operation reset) <1> to <2> can be in any order. caution: in the one-shot pulse mode, set bit ttneee of the ttnctl1 register to 0.
485 chapter 11 16-bit ti mer/event counter t user?s manual u16580ee2v0ud00 figure 11-25: basic operation flow in one-shot pulse mode note: the counter is not cleared upon a match between the counter and the ttnccr1 buffer register. caution: the counter is not cleared even if trigger input is realized while the counter counts up, and the trigger input is ignored. remark: n = 0, 1 start timer operation enable (ttnce = 1) transfer of values of ttnccr0 and ttnccr1 to buffers ttnccr0 and ttnccr1 initial settings clock selection (ttnctl1: ttneee = 0) (ttnctl0: ttncks2 to ttncks0) one-shot pulse mode setting (ttnctl1: ttnmd2 to ttnmd0 = 011) compare register setting (ttnccr0, ttnccr1) trigger wait status, counter in standby at ffffh trigger wait status, counter in standby at 0000h external trigger (ttrgtn pin) input, or ttnest = 1 counter starts counting. match between counter and buffer ttnccr1 match between counter and buffer ttnccr0, counter clear intttncc0 occurrence note intttncc1 occurrence ? ? ?
486 chapter 11 16-bit timer/event counter t user?s manual u16580ee2v0ud00 figure 11-26: basic operation timing in one-shot pulse mode (a) (ttnoe0, 1 = 1, ttnol0, 1 = 0) note: count up starts when the value of ttnest becomes 1 or ttrgtn is input. remarks: 1. d0: setting value of ttnccr0 re gister (0000h to ffffh) d1: setting value of ttnccr1 re gister (0000h to ffffh) 2. totn1 (output delay) = (setting value of ttnccr1 re gister) (count clock cycle) totn1 (output pulse width) = {(setting value of ttnccr0 register +1) - (setting value of ttnccr1 register)} (count clock cycle) 3. n = 0, 1 0000h counter intttncc0 ffffh ttnccr1 intttncc1 ttnccr0 ttnce external trigger (ttrgtn pin) totn1 ttnest d0 d0 d0 d1 d1 d1 d0 d1 note d0 d0 ttnccr0 buffer 0000h d1 ttnccr1 buffer totn0 one-shot pulse output
487 chapter 11 16-bit ti mer/event counter t user?s manual u16580ee2v0ud00 11.6.5 pwm mode when, in the pwm mode, the duty is set to the ttnccr1 register, the cycle is set to the ttnccr0 register, and ttnce = 1 is set, variable duty pwm output is performed from pin totn1. simultaneously with the start of count up operation, pin totn1 becomes high level, and upon a match between the counter and the ttnccr1 register, becomes low level. next, the totn1 pin becomes high level upon a match with the ttnccr0 register. the totn0 pin performs toggle output upon a match with the ttnccr0 buffer register. during count operation, a compare match interrupt (intttncc0) is output upon a match between the counter and ttnccr0 register, and a compare matc h interrupt (intttncc1) is output upon a match between the co unter and ttnccr1 register. the ttnccr0 and ttnccr1 registers can be rewritten during count operation. compare register reload occurs upon a match between the counter value and the ttnccr0 buffer register. however, since the next reload timing becomes valid when the ttnccr1 register is written to, write the same value to the ttnccr1 register even when wishing to rewrite only the value of the ttnccr0 register. reloading is not performed if only the ttnccr0 register is rewritten. in the pwm mode, the ttnccr0 and ttnccr1 registers have thei r function fixed as compare registers, so the capture function cannot be used. figure 11-27: basic operation mode in pwm mode (1/2) (a) when values of ttnccr0 and ttnccr1 regi sters are rewritten during timer operation remark: n = 0, 1 m = 0, 1 start intttncc0 occurrence timer operation enable transfer of value of ttnccrm to ttnccrm buffer totn1 outputs low level upon a match between counter and ttnccr1 buffer. upon a match between counter and ttnccr0 buffer, counter clear & start, and totn1 outputs high level. intttncc1 occurrence initial settings clock selection (ttnctl0: ttncks2 to ttncks0) pwm mode setting (ttnctl1: ttnmd3 to ttnmd0 = 0100) compare register setting (ttnccr0, ttnccr1) ? ? ?
488 chapter 11 16-bit timer/event counter t user?s manual u16580ee2v0ud00 figure 11-27: basic operation flow in pwm mode (2/2) (b) when values of ttnccr0 and ttnccr1 registers are rewritten during timer operation note: regarding the sequence, the timing of <2> may differ depending on the <1> or <3> rewrite timing, the value of the ttnccr1 register, etc., but of <1> and <3>, always make <3> the last. remark: n = 0, 1 m = 0, 1 start intttncc0 occurrence upon a match between counter and ttnccr1 buffer, totn1 outputs low level. timer operation enable (ttnce = 1) transfer of value of ttnccrm to ttnccrm buffer upon a match between counter and ttnccr1, totn1 outputs low level ttnccr0 rewrite ttnccr1 rewrite upon a match between counter and ttnccr0, counter clear & start, and totn1 outputs high level. <1> intttncc1 occurrence intttncc0 occurrence intttncc1 occurrence initial settings clock selection (ttnctl0: ttncks2 to ttncks0) pwm mode setting (ttnctl1: ttnmd3 to ttnmd0 = 0100) compare register setting (ttnccr0, ttnccr1) match between ttnccr0 buffer and counter counter clear & start value of ttnccrm is reloaded to ccrm buffer. <2> <3> note reload enable ? ? ? ? ? ?
489 chapter 11 16-bit ti mer/event counter t user?s manual u16580ee2v0ud00 figure 11-28: basic operation timing in pwm mode (1/2) (a) when only value of ttnccr1 is rewr itten, and totn0 and totn1 are output (ttnoe0, 1 = 1, ttnol0, 1 = 0) remarks: 1. d 00 : setting value of ttnccr0 re gister (0000h to ffffh) d 10 , d 11 , d 12 , d 13 : setting values of ttnccr1 register (0000h to ffffh) 2. totn1 (pwm) duty = (setting value of ttnccr1 register) (count clock cycle) totn1 (pwm) cycle = (setting value of ttnccr0 register + 1) (count clock cycle) 3. totn0 is toggled immediately following counter start and at (setting value of ttnccr0 register + 1) (count clock cycle) 4. n = 0, 1 counter ffffh ttnccr1 ttnccr0 ttnce totn1 ttnccr0 buffer ttnccr1 buffer d 00 d 00 0000h d 10 d 11 d 12 d 13 d 10 d 11 d 12 d 13 0000h d 00 d 00 d 00 d 00 d 10 d 10 d 11 d 12 totn0 ttnrsf flag
490 chapter 11 16-bit timer/event counter t user?s manual u16580ee2v0ud00 figure 11-28: basic operati on timing in pwm mode (2/2) (b) when values of ttnccr0 and ttnccr1 register are rewritten, totn0 and totn1 are output (ttnoe0, 1 = 1, ttnol0, 1 = 0) note: the ttnccr1 register was not written to, so tran sfer to the ttnccr0 bu ffer register was not performed. held until the next reload timing. remarks: 1. d 00 , d 01 , d 02 , d 03 : setting values of ttnccr0 register (000 0h to ffffh) d 10 , d 11 , d 12 , d 13 : setting values of ttnccr1 register (000 0h to ffffh) 2. the totn0 and totn1 pins become high level at timer count start. 3. n = 0, 1 counter ffffh ttnccr1 ttnccr0 ttnce totn1 ttnccr0 buffer ttnccr1 buffer d 00 0000h d 10 d 11 d 12 d 12 d 10 d 11 d 12 0000h d 00 d 01 d 02 d 03 d 01 d 01 d 02 d 00 d 01 d 02 d 03 d 12 d 10 d 11 d 11 d 12 note note write same va totn0 ttnrsf flag
491 chapter 11 16-bit ti mer/event counter t user?s manual u16580ee2v0ud00 11.6.6 free-running mode the operation timing of the free-running mode is shown below. the operation for bits ttnccs1 and ttnccs0 of register ttnopt0 is specified. figure 11-29: basic operation flow in free-running mode remark: n = 0, 1 start ttnccs1, ttnccs0 settings initial settings clock selection (ttnctl0: ttncks2 to ttncks0) free-running mode setting (ttnctl1: ttnmd3 to ttnmd0 = 0101) match between ttnccr1 buffer and counter match between ttnccr0 buffer and counter titn0 edge detection settings (ttnis1, ttnis0) ttnccs1 = 0 ttnccs0 = 0 ttnccs1 = 0 ttnccs0 = 0 ttnccs1 = 1 ttnccs0 = 1 ttnccs1 = 1 ttnccs0 = 1 timer operation enable (ttnce = 1) transfer of values of ttnccr0 and ttnccr1 to ttnccr0 and ttnccr1 buffers timer operation enable (ttnce = 1) transfer of value of ttnccr1 to ttnccr1 buffer counter overflow timer operation enable (ttnce = 1) transfer of value of ttnccr0 to ttnccr0 buffer match between ttnccr1 buffer and counter titn0 edge detection, capture of counter value to ttnccr0 counter overflow counter overflow counter overflow match between ttnccr1 buffer and counter timer operation enable (ttnce = 1) titn1 and titn0 edge detection settings (ttnis3, ttnis2) titn1 edge detection, capture of counter value to ttnccr1 titn0 edge detection, capture of counter value to ttnccr0 titn1 edge detection, capture of counter value to ttnccr1 titn1 edge detection settings (ttnis3, ttnis2) ? ?
492 chapter 11 16-bit timer/event counter t user?s manual u16580ee2v0ud00 (1) compare function (ttnccs1 = 0, ttnccs0 = 0) when ttnctl0 register bit ttnce is set to 1, the counter counts from 0000h to ffffh. an overflow interrupt (intttnov) is output when the counter value changes from ffffh to 0000h, and the counter is cleared. the count operation is performed in the free-running mode until ttnce = 0 is set. moreover, during count operation, a compare match interrupt (intttncc0) is output upon a match between the counter and ttnccr0 buffer register, and a compare match interrupt (intttncc1) is output upon a match between the counter and ttnccr1 buffer register. the ttnccr0 and ttnccr1 registers can be rewritten using the anytime write method, regardless of the value of the ttnce bit. the totn0 and totn1 pins are toggle output controlled when bits register ttnoe0 and ttnoe1 of the ttnioc0 register are set to 1.
493 chapter 11 16-bit ti mer/event counter t user?s manual u16580ee2v0ud00 figure 11-30: basic operation timing in free-running mode (compare function) (a) when values of ttnccr0 and ttnccr1 regist ers are rewritten, to tn0, totn1 are output (ttnoe0, 1 = 1, ttnol0, 1 = 0) remarks: 1. d 00 , d 01 : setting values of ttnccr0 register (0000h to ffffh) d 10 , d 11 : setting values of ttnccr1 register (0000h to ffffh) 2. totn0 (toggle) width = (setting value of ttn ccr0 register + 1) (count clock cycle) 3. totn1 (toggle) width = (setting value of ttn ccr1 register + 1) (count clock cycle) 4. pins totn0 and totn1 become high level at count start. 5. n = 0, 1 0000h counter ffffh ttnccr1 ttnccr0 ttnce intttncc1 d 00 d 00 d 01 d 11 d 11 d 10 d 00 d 01 d 11 d 10 intttncc0 d 00 d 01 d 10 d 11 0000h ttnccr0 buffer ttnccr1 buffer totn0 totn1 intttnov ttnovf ttnovf 0 write clear ttnovf 0 write clear
494 chapter 11 16-bit timer/event counter t user?s manual u16580ee2v0ud00 (2) capture function (ttnccs1 = 1, ttnccs0 = 1) when ttnctl0 register bit ttnce is set to 1, the counter counts from 0000h to ffffh. an overflow interrupt (intttnov) is output when the value of the counter changes from ffffh to 0000h, and the counter is cleared. the count operation is performed in the free-running mode until ttnce = 0 is set. when, during count operation, the counter value is captured to the ttnccr0 and ttnccr1 registers th rough detection of the valid edge of captur e input (titn1, titn0), a capture interrupt (intttncc0, intttncc1) is output. regarding capture in the vicinity of overflow (f fffh), judgment is possible with the overflow flag (ttnovf). however, judgment with the ttnovf flag is not possible when the capture trigger inter- val is such that it includes two overflow occurrences (2 or more free-running cycles). figure 11-31: basic operation timing in free-running mode (capture function) (a) when totn0, totn1 are not output (ttnoe0, 1 = 0, ttnol0, 1 = 0) remarks: 1. d 00 , d 01 : values captured to ttnccr0 register (0000h to ffffh) d 10 , d 11 : values captured to ttnccr1 register (0000h to ffffh) 2. titn0: setting to rising edge detection (ttnioc1 register bits ttnis1, ttnis0 = 01) titn1: setting to falling edge detection (ttnioc1 register bits ttnis3, ttnis2 = 10) 3. n = 0, 1 d 11 d 10 0000h d 12 counter ffffh titn1 titn0 ttnce ttnccr1 d 00 d 01 d 12 d 02 d 11 d 10 d 00 d 01 ttnccr0 d 02 d 03 0000h d 03
495 chapter 11 16-bit ti mer/event counter t user?s manual u16580ee2v0ud00 (3) compare/capture function (ttnccs1 = 0, ttnccs0 = 1) when ttnctl0 register bit ttnce is set to 1, the counter counts from 0000h to ffffh, an overflow interrupt (intttnov) is output when t he value of the counter changes from ffffh to 0000h, and the counter is cleared. the count ope ration is performed in the free-running mode until ttnce = 0 is set. the ttnccr1 register is us ed as a compare regist er, and as the interval function upon a match between the counter and ttnccr1 register, a compare match interrupt (intttncc1) is output. since the ttnccr0 register is set to the capture function, the totn0 pin cannot be controlled even when ttnioc0 register bit ttnoe0 is set to 1. figure 11-32: basic operation timing in free-running mode (compare/capture function) (a) when value of ttnccr1 is rewritten, totn0, totn1 are output (ttnoe0, 1 = 1, ttnol0, 1 = 0) remarks: 1. d 00 , d 01 : setting values of ttnccr1 register (0000h to ffffh) d 10 , d 11 , d 12 , d 13 , d 14 , d 15 : values captured to ttnccr0 register (000 0h to ffffh) 2. titn0: setting to rising edge detection (ttnioc1 register bits ttnis1, ttnis0 = 11) 3. n = 0, 1 counter ffffh ttnccr1 titn0 ttnce d 00 d 02 d 03 d 10 d 11 d 10 ttnccr0 0000h d 12 d 00 d 01 d 11 d 12 d 01 d 02 d 03 d 11 ttnccr1 buffer intttncc1 d 10 d 11 d 12 0000h intttncc0 match interrupt capture interrupt intttnov overflow interrupt totn0 totn1 low
496 chapter 11 16-bit timer/event counter t user?s manual u16580ee2v0ud00 (4) overflow flag when, in the free-running mode, the counter over flows from ffffh to 0000h, the overflow flag (ttnovf) is set to "1", and an overflow interrupt (intttnov) is output. the overflow flag is cleared through 0 write from the cpu. (the overflow flag is not cleared by just being read.) 11.6.7 pulse width measurement mode in the pulse width measurement mode, counting is performed in the free-running mode. the counter value is saved to the ttnccr0 register, and the count er is cleared to 0000h. as a result, the external input pulse width can be measured. however, when measuring a long pulse width that exceeds counter overflow, perform judgment with the overflow flag. measurement of pulses during which overflow occurs twice or more is not possible, so adjust the counter's operating frequency. even in the case of titn1 pin edge detection, pulse width measurement can be similarly performed by using the ttnccr1 register. figure 11-33: basic operation timing in pulse width measurement mode (a) (ttnoe0, 1 = 0, ttnol0, 1 = 0) remarks: 1. d 00 , d 01 , d 02 , d 03 : values captured to ttnccr0 register (0000h to ffffh) 2. titn0: setting to rising edge/falling edge (both edges) detection (ttnioc1 register bits ttnis1, ttnis0 = 11) 3. n = 0, 1 counter ffffh intttncc0 titn0 ttnce ttnovf d 00 ttnccr0 0000h d 00 d 01 d 02 d 03 d 01 d 02 d 03 ffffh intttnov cleared through 0 write from cpu
497 chapter 11 16-bit ti mer/event counter t user?s manual u16580ee2v0ud00 11.6.8 triangular wave pwm mode in the triangular wave pwm mode, similarly to in the pwm mode, when the duty is set to the ttnccr1 register, the cycle is set to the ttnccr0 register, and ttnce = 1 is set, variable duty and cycle type triangular wave pwm output is performed from pin totn1. the totn0 pin is toggle output upon a match with the ttnccr0 buffer register and upon counter underflow. upon a match between the counter and ttnccr0 register during count operation, a compare match interrupt (intttncc0) is output, and upon a matc h between the counter and ttnccr1 re gister, a compare match interrupt (intttncc1) is output. moreover, upon counter under flow, an overflow interrupt (intttnov) is output. the ttnccr0 and ttnccr1 registers can be rewritten during count operation. compare register reload occurs upon a match between the counter value and the ttnccr0 buffer register. however, since the next reload timing becomes valid when the ttnccr1 register is written to, write the same value to the ttnccr1 register even when wishing to rewrite only the value of the ttnccr0 register. reloading is not performed if only th e ttnccr0 register is rewritten. th e reload timing is the underflow timing. in the triangular wave pwm mode, the ttnccr0 and ttnccr1 regi sters have their function fixed as compare registers, so the capture function cannot be used. remark: in the triangular wave pwm mode, set the ttnccr0 register to a value of 0 ttnccr0 fffeh.
498 chapter 11 16-bit timer/event counter t user?s manual u16580ee2v0ud00 figure 11-34: basic operation timing in triangular wave pwm mode (a) when totn0, totn1 are output (ttnoe0, 1 = 1, ttnol0, 1 = 0) remark: n = 0, 1 d 00 d 10 counter ffffh intttncc0 ttnce d 00 ttnccr0 0000h ffffh ttnccr1 0000h d 10 d 10 intttncc1 d 00 d 10 d 00 intttnov totn0 totn1
499 chapter 11 16-bit ti mer/event counter t user?s manual u16580ee2v0ud00 11.6.9 encoder count function the encoder compare mode is provided as follows. (1) counter up/down control counter up/down control is performed and the co unter is operated according to the phase of signals tenctn0 and tenctn1 from the encoder and the set conditions of bits ttnuds1 and ttnuds0 of the ttnctl2 register. (2) basic operation to use the ttnccr0 and ttnccr1 registers are compare-only registers, enable rewrite during timer operation. the rewrite method is anytime write. a compare match interrupt (intttncc0) is ou tput upon a match between the counter and ttnccr0 register. a compare match interrupt (intttncc1) is output upon a match between the counter and ttnccr1 register. (3) counter clear operation clearing of the counter to 0000h is performed under the following conditions. mode ttnccr0 register ttnccr1 register encoder compare mode compare only compare only clear condition method whereby counter is cleared to 0000h upon match with compare register (setting of tt nctl2 register bits ttnecm1, ttnecm0) method whereby counter is cleared to 0000h upon detection of edge of pin tecrt0 (setting of bits ttnecs1, ttnecs0 when ttnioc3 register bit ttnsce = 0) method whereby counter is cleared to 0000h by special clear function of encoder (setting of bits ttnzcl, ttnbcl, ttnacl when ttnioc3 register bit ttnsce = 1)
500 chapter 11 16-bit timer/event counter t user?s manual u16580ee2v0ud00 (4) control through ttnctl2 register the settings of the ttnctl2 register in the encoder compare mode (ttnmd3 to ttnmd0 = 1000b) are as follows. ? in the case of bits ttnuds1 and ttnuds0, up/down judgment control is performed for the phase input from pins tenctn0 and tenctn1. ? in the case of bits ttnecm1 and ttnecm0, counter clear control is performed upon a match between the counter value and the compare setting value. bits ttnecm1 and ttnecm0 are valid in mo des where the ttnccr0 or ttnccr1 register is used as a compare-only register. these bits are invalid in modes where the ttnccr0 or ttnccr1 register is used as a capture-only register. ? the ttnlde bit controls the function to load to the coun ter the setting valu e of the ttnccr0 register upon occurrence of counter underflow. bit ttnlde is valid only when the ttnecm bit se tting is 00b, 01b, in a mode where the ttnccr0 or ttnccr1 register is used as a compare-only register. in the case of all other settings, bit ttnlde is invalid even if manipulated. as an example of the use of the encoder coun t function, counter operation becomes possible between the setting values of registers 0000h to ttnccr0 by using the counter load functions (ttnlde = 1) indicated with ? ? ? in the table, and the function for clearing the counter to 0000h in case the count operation following a match with the ttnccr0 buffer register is up count (ttnecm0 = 1). (refer to 11.6.9 (4) (c) counter load function for ttnccr0 register setting value upon underflow (bit ttnlde of register ttnctl2)) ). ttnmd3 to 0 ttnuds1 to 0 ttnecm1 ttnecm0 ttnlde clear load 1000b all settings possible 00b 01b 10b 11b 000 - - 1 1 0 ttnccr0 - 1 ? 1 0 invalid ttnccr1 - 1 invalid ttnccr0 ttnccr1 -
501 chapter 11 16-bit ti mer/event counter t user?s manual u16580ee2v0ud00 (a) up/down count selection specification ( ttnctl2 register bits ttnuds1, ttnuds0) counter up/down is judged according to the settings of bits ttnuds1 and ttnuds0, and the phases input from pins tenctn0 and tenctn1. bits ttnuds1 and ttnuds0 are valid only in the encoder compare mode. <1> ttnctl2: ttnuds1, 0 = 00b (count judgment mode 1) operation example: ttnioc3: ttneis3 to 2 tenctn1 pin inpu t edge detection specification invalid ttnioc3: ttneis1 to 0 = 10b tenctn0 pin input rising edge detection figure 11-35: encoder count function up/down c ount selection specification timings (1/6) (a) timing 1 remarks: 1. counting is performed when the edges of the tenctn0/tenctn1 pin inputs overlap. 2. n = 0, 1 a phase (pin tenctn0) b phase (pin tenctn1) count rising edge high level down falling edge both edges rising edge low level up falling edge both edges tenctn0 tenctn1 0007 0006 0005 0004 0005 0006 0007 counter down count up count
502 chapter 11 16-bit timer/event counter t user?s manual u16580ee2v0ud00 <2> ttnctl2: ttnuds1, 0 = 01b (count judgment mode 2) operation example: ttnioc3: ttneis3, 2 = 10b tenctn1 pin input rising edge detection ttnioc3: ttneis1, 0 = 10b tenctn0 pin input rising edge detection figure 11-35: encoder count function up/down count selection specification timings (2/6) (b) timing 2 remarks: 1. the count value is held when the edges of the tenctn0/tenctn1 pin inputs overlap. 2. n = 0, 1 a phase (pin tenctn0) b phase (pin tenctn1) count low level rising edge down falling edge both edges high level rising edge falling edge both edges rising edge low level up falling edge both edges rising edge high level falling edge both edges simultaneous pin tenctn0/tenctn1 inputs hold tenctn0 tenctn1 0006 0007 0007 0006 0005 counter up count down count hold 0008
503 chapter 11 16-bit ti mer/event counter t user?s manual u16580ee2v0ud00 <3> ttnctl2: ttnuds1, 0 = 10b (count judgment mode 3) operation example: ttnioc3: ttneis3 to 0 (pins tenctn1, tenctn0) edge detection specification invalid figure 11-35: encoder count function up/down c ount selection specification timings (3/6) (c) timing 3 remark: n = 0, 1 a phase (pin tenctn0) b phase (pin tenctn1) count low level falling edge hold rising edge low level down high level rising edge hold falling edge high level rising edge high level high level falling edge falling edge low level up low level rising edge hold rising edge rising edge hold falling edge rising edge rising edge falling edge down falling edge falling edge up tenctn0 tenctn1 0007 0006 0006 0005 0005 0006 counter 0005 0006 0007 down count up count up down up down
504 chapter 11 16-bit timer/event counter t user?s manual u16580ee2v0ud00 <4> ttnctl2: ttnuds1, 0 = 11b (count judgment mode 4) operation example 1: ttnioc2: ttneis3 to 0 (pins tenctn1, tenctn0) edge detection specification invalid figure 11-35: encoder count function up/down count selection specification timings (4/6) (d) timing 4 remark: n = 0, 1 a phase (pin tenctn0) b phase (pin tenctn1) count low level falling edge down rising edge low level high level rising edge falling edge high level rising edge high level up high level falling edge falling edge low level low level rising edge simultaneous pin tenctn0/tenctn1 inputs hold tenctn0 tenctn1 counter up count down count 04 03 05 06 07 08 09 0a 09 08 07 06 05
505 chapter 11 16-bit ti mer/event counter t user?s manual u16580ee2v0ud00 operation example 2: ttnioc2: ttneis3 to 0 (pins tenctn1, tenctn0) edge detect ion specification invalid. figure 11-35: encoder count function up/down c ount selection specification timings (5/6) (e) timing 5 remarks: 1. the count value is held when the edges of the tenctn0/tenctn1 pin inputs overlap. 2. n = 0, 1 tenctn0 tenctn1 counter up count down count 04 03 05 06 07 08 07 06 05 hold up count 06 up count
506 chapter 11 16-bit timer/event counter t user?s manual u16580ee2v0ud00 (b) counter clear condition setting upon match between counter value and compare setting value (ttnctl2 register bits ttnecm1, ttnecm0) counter operation is performed according to the setting values of these bits upon a match between the counter value and the compare setting value. <1> ttnecm1, 0 = 00b counter clear is not performed upon a match between the counter and compare values. <2> ttnecm1, 0 = 01b counter clear is performed upon a match between the counter and the ttnccr0 register. <3> ttnecm1, 0 = 10b operation is performed under the following conditions upon a match between the counter and ttnccr1 register. <4> ttnecm1, 0 = 11b ? operation is performed under the following conditions upon a match between the counter and ttnccr0 register. ? operation is performed under the following conditions upon a match between the counter and ttnccr1 register. caution: in encoder compare mode (ttnmd3 to ttnmd0 bits = 1000b), if the compare regis- ters (ttnccr0, ttnccr1) are set to the same value of ttntcw register when ttnecc bit = 0, the timer cannot perform the comparison with the compare registers (ttnccr0, ttnccr1) and ttntcw register (which is the start value of ttncnt). in this case the ?encoder clear mode on match of counter and compare register? does not work at the start timing (ttnecm0 = 1, and/or ttnecm1 = 1). next count operation description up count clear counter to 0000h. down count down count the counter value. next count operation description up count up count the counter value. down count clear counter to 0000h. next count operation description up count clear counter to 0000h. down count down count the counter value. next count operation description up count up count the counter value. down count clear counter to 0000h.
507 chapter 11 16-bit ti mer/event counter t user?s manual u16580ee2v0ud00 (c) counter load function for ttnccr0 register setting value upon underflow (bit ttnlde of register ttnctl2)) the setting value of the ttnccr0 register can be loaded to the counter upon counter underflow, by setting ttnlde = 1. bit ttnlde is only valid in the encoder compare mode. count operation between 0000h and setting value of ttnccr0 register setting set ttnlde = 1, ttnecm1, 0 = 01b and perform count operation. when ttnecm0 = 1, the counter is cleared to 0000h if the next count following a match between the counter and ttnccr0 register is up count. when ttnlde = 1, the setting value of the ttnccr0 register is loaded to the counter upon underflow. therefore, the setting value of the ttnccr0 register is used as the maximum count value and count operation can be realized within 0000h-ttnccr0 register setting values. figure 11-35: encoder count function up/down c ount selection specification timings (6/6) (f) timing 6 remark: n = 0, 1 ttnccr0 0000h counter match between counter value and ttnccr0 setting value counter underflow counter cleared to 0000h ttnccr0 setting value loaded to counter
508 chapter 11 16-bit timer/event counter t user?s manual u16580ee2v0ud00 (5) counter clearing to 0000h through encoder cl ear input (pin tecrtn) (ttnioc3 register bits ttnsce, ttnecs1, ttnecs0) there are two methods to clear the counter to 0000h through tecrtn pin input, and encoder clear input is controlled by bit ttnsce. bits ttnzcl, ttnbcl, ttnacl, ttnecs1, and ttnecs0 are controlled by the setting of bit ttnsce. these clear methods are valid in the encoder compare mode. <1> method to clear counter to 0000h through detection of valid edge of tecrtn pin input (ttnsce = 0) when ttnsce = 0, the counter is cleared to 0000h in synchronization with the internal operation clock upon detection of the valid edge set through tecrtn pin input edge detection specification. at this time, an encoder clear interrupt (in tttnec) is output. when ttnsce = 0, the setting of bits ttnzcl, ttnbcl, and ttnacl are invalid. figure 11-36: counter clearing to 0000h through encoder clear inpu t (pin tecrtn) timings (1/4) (a) when ttnsce = 0, ttnecs1, 0 = 01b, ttnuds = 11b are set remark: n = 0, 1 ttnsce ttnzcl ttnbcl ttnacl ttnecs1, 0 method 0 invalid invalid invalid <1> 1 ?? invalid <2> tenctn0 tenctn1 tecrtn m intttnec 0 m + 1 1 2 base clock count signal counter counter clear
509 chapter 11 16-bit ti mer/event counter t user?s manual u16580ee2v0ud00 <2> method to clear counter to 0000h through detection of level clear condition (ttnsce = 1) when ttnsce = 1, the counter is cleared to 0000h according to the clear condition level of pins tecrtn, tenctn1, and tenctn0 set with bits ttnzcl, ttnbcl, and ttnacl. at this time, no encoder clear interrupt (intttnec) is output. when ttnsce = 1, the settings of bits ttnecs1 and ttnecs0 are invalid. operation example: when ttnsce = 1, ttncla = 1, ttnclb = 0, ttnclz = 1, ttnuds = 11b are set tecrtn pin: high level, tenctn1 pin: low level, tenctn0 pin: high level figure 11-36: counter clearing to 0000h through encode r clear input (pin tecrtn) timings (2/4) (b) when tecrtn pin input is delayed from tenctn1 pin input during up count remark: n = 0, 1 tenctn0 tenctn1 tecrtn h l 0 m m+1 ttnccr0 0 ttnccr1 intttncc1 m+1 intttncc0 h m ttnccr0 intttncc0 when ?m+1? set to ttnccr0 when ?0000h? set to ttnccr1 when ?m? set to ttnccr0 count clock counter compare match interrupt not output signal after edge detection base clock
510 chapter 11 16-bit timer/event counter t user?s manual u16580ee2v0ud00 figure 11-36: counter clearing to 0000h through enco der clear input (pin tecrtn) timings (3/4) (c) when tecrtn pin input and tenctn1 pin input occur simultaneously during up count (d) when tecrtn pin input occurs earlier than tenctn1 pin input during up count no miscount occurs due to tecrtn pin input dela y because the clear condition is set according to the levels of pins tenctn0, tenctn1 and tecr tn, and the counter is cleared to 0000h upon clear condition detection. remark: n = 0, 1 tenctn0 tenctn1 tecrtn h l 0 m h signal after edge detection base clock counter count clock tenctn0 tenctn1 tecrtn h l 0 m h signal after edge detection base clock counter count clock
511 chapter 11 16-bit ti mer/event counter t user?s manual u16580ee2v0ud00 figure 11-36: counter clearing to 0000h through encode r clear input (pin tecrtn) timings (4/4) (e) when tecrtn pin input occurs later tha n tenctn1 pin input during down count no miscount occurs due to the tecrtn pin input delay during down count, similarly to during up count. remark: n = 0, 1 tenctn0 tenctn1 tecrtn h l 0 m m-1 h m-1 ttnccr0 0 ttnccr1 intttncc1 intttncc0 m ttnccr0 intttncc0 signal after edge detection when ?m-1? set to ttnccr0 when ?0000h? set to ttnccr1 compare match interrupt not output when ?m? set to ttncr0 base clock counter count clock
512 chapter 11 16-bit timer/event counter t user?s manual u16580ee2v0ud00 (6) counter hold through bit ttnecc (a) initial counter operation through bit ttnecc setting figure 11-37: counter hold through bit ttnecc timings (1/5) (a) count operation when ttnecc = 0 is set the setting value of the ttntcw register is loaded to the counter and count operation is performed from the setting value of the ttntcw register. (initial value 0000h of ttntcw register) (b) count operation when ttnecc = 1 is set since the setting value of the ttntcw register is not loaded to the counter, the count operation is performed from initial value ffffh. as the initial operation, it is recommended to set ttnecc = 0 and load to the counter the value set to the ttntcw register, then start the count operation. remark: n = 0, 1 ttnce ffffh ttnecc low m m+1 ttntcw m internal count signal base clock counter ffffh high 0000h m ttnce ttnecc ttntcw base clock internal count signal counter
513 chapter 11 16-bit ti mer/event counter t user?s manual u16580ee2v0ud00 (b) bit ttnecc rewrite timing and its influence on counter <1> when setting value of bit ttnecc is rewritten 0 1 0 when ttnce = 1 even if bit ttnecc rewrite is performed while ttnce = 1, this has no influence on the counter operation. judgment as whether to hold or reset the counter value is performed while ttnce = 0. moreover, judgment as to whether to load the setting value of the ttntcw register to the counter is performed at the timing when the value of bit ttnce changes from 0 to 1. figure 11-37: counter hold through bit ttnecc timings (2/5) (c) when setting value of bit ttnecc is rewritten 0 1 0 when ttnce = 1 <2> when setting value of bit ttnecc is rewritten 1 0 1 while ttnce = 0 the counter is reset when the setting value of bit ttnecc is changed from 1 to 0 while ttnce = 0. then, when ttnecc = 1 is set again and the value of bit ttnce is changed from 0 to 1, counting restarts from the counter's initial value ffffh, without the setting value of the ttntcw being loaded to the counter. (d) when setting value of bit ttnecc is rewritten 1 0 1 while ttnce = 0 remark: n = 0, 1 ttnecc ttnce l tcw h h l ffffh l l tcw no influence on operation internal count signal counter start enc-mode tcw load start new enc-mode tcw load count not hold counter reset lh h l ffffh h l n ttnecc ttnce counter hold counter reset change enc-mode tcw not load internal count signal counter
514 chapter 11 16-bit timer/event counter t user?s manual u16580ee2v0ud00 (c) rewrite timing of bit ttnecc when ttnce = 0 and ttnecc = 0, setting ttnce = 1 causes the setting value of the ttntcw register to be loaded to the counter. perform rewrite of the ttnecc bit after the operation clock has become valid (after several clocks: tbd), following setting of ttnce = 1. if bit ttnecc is rewritten before the operation clock becomes valid, counting starts from ffffh without loading the setting value of the ttntcw register to the counter. figure 11-37: counter hold through bit ttnecc timings (3/5) (e) basic timing in encoder compare mode (1) < register setting conditions> ? ttnctl0: ttnmd3 to 0 = 1000b encoder compare mode ? ttnctl1: ttnuds1, 0 = 00b judgment of up/down count with count judgment mode 1 ? ttnctl1: ttnecm1, 0 = 01b counter clear upon match between counter value and ttnccr0 buffer register ? ttnctl1: ttnlde = 1 loading of setting value of ttnccr0 re gister (p) upon underflow occurrence ? ttnioc3: ttneis1, 0 = 01b detection of rising edge of tenctn0 and tenctn1 pin inputs ? ttnioc3: ttnsce = 0, ttnecs1-0 = 00b valid edge detection clear (no edge specified) since ttnuds1, 0 and ttneis1, 0 that control the count operation are set to 00b and 01b (rising edge detection), respectively, the counter is operated through detection of the phase of pin tenctn1 upon detection of the rising edge of tenctn0 pin input. a compare match interrupt (intttncc0) is output upon a match between the counter value and the ttnccr0 compare reg- ister (p). at this time, the counter is cleared to 0000h if the next count operation is up count. a compare match interrupt (intttncc1) is output upon a match between the counter value and the ttnccr1 buffer register (q). the counter is not cleared up on a match between the counter value and the ttnccr1 register. if underflow occurs when ttnlde = 1 is set, the setting value of the ttnccr0 buffer register (m) is loaded to the counter. a count operation is possible between 0000h and the setting value of the ttnccr0 register by setting ttnlde = 1 and ttnecm0 = 1. remark: n = 0, 1 p ttnccr0 p ttnesf ttneuf q ttnccr1 q intttncc0 intttncc1 tenctn0 tenctn1 encoder counter count clear load to counter load to counter up count down count
515 chapter 11 16-bit ti mer/event counter t user?s manual u16580ee2v0ud00 figure 11-37: counter hold through bit ttnecc timings (4/5) (f) basic timing in encoder compare mode (2) ? ttnctl0: ttnmd3 to 0 = 1000b encoder compare mode ? ttnctl1: ttnuds1, 0 = 11b judgment of up/down count with count judgment mode 4 ? ttnctl1: ttnecm1, 0 = 00b no clear operation upon match between counter value and compare ? ttnctl1: ttnlde = 0 no loading of setting value of ttnccr0 register (p) to counter ? ttnioc3: ttnsce = 0, ttnecs1-0 = 01b valid edge detection clear (rising edge specified) since ttnuds1, 0 that control the count operation are set to 11b, the counter is operated through detection of the phase of pins tenctn0 and tenctn1. a compare match interrupt (intttncc0) is output upon a match between the counter value and the ttnccr0 buffer register (p). a compare match interrupt (intttncc1) is output upon a match between the counter value and the ttnccr1 buffer register (q). the counter is not cleared upon a match with the ttnccr0 register or the ttnccr1 register. clearing of the counter to 0000h is done upon detection of the valid edge of the encoder clear input (pin tecrtn) when ttnsce = 0. when ttnecs = 01b is set, the counter is cleared to 0000h in synchronization with the operation clock, following detection of the rising edge of the tecrtn pin input. remark: n = 0, 1 ttnccr0 ttnccr1 intttncc0 p q tecrtn intttncc1 ttnesf p q ttnccr0 ttnccr1 0000h tenctn0 tenctn1 encoder counter
516 chapter 11 16-bit timer/event counter t user?s manual u16580ee2v0ud00 figure 11-37: counter hold through bit ttnecc timings (5/5) (g) basic timing in encoder compare mode (3) ? ttnctl0: ttnmd3 to 0 = 1000b encoder compare mode ? ttnctl1: ttnuds1 to 0 = 11b judgment of up/down count with count judgment mode 4 ? ttnctl1: ttnecm1 to 0 = 11b counter clear upon match between counter value and ttnccr0 buffer register counter clear upon match between counter value and ttnccr1 buffer register (since ttnctl1: ttnecm1 to 0 = 11b, the setting of bit ttnlde is invalid.) ? ttnioc3: ttnsce = 0, ttnecs1 to 0 = 00b valid edge detection clear (no edge specified) since ttnuds1, 0 that control the count operation are set to 11b, the counter is operated through detection of the phase of pins tenctn0 and tenctn1. a compare match interrupt (intttncc0) is output upon a match between the counter value and the ttnccr0 buffer (p). at this time, the counter is cleared to 0000h if the next count operation is up count. a compare match interrupt (intttncc1) is output upon a match between the counter value and the ttnccr1 buffer (q). at this time, the counter is cleared to 0000h if the next count operation is down count. remark: n = 0, 1 q ttnccr1 ttnesf ttnccr0 ttnccr1 p ttnccr0 0000h q intttncc0 intttncc1 p tenctn0 tenctn1 encoder counter counter clear match interrupt output counter clear match interrupt output up count down count
517 chapter 11 16-bit ti mer/event counter t user?s manual u16580ee2v0ud00 11.6.10 offset trigger generation mode in the offset trigger generation mode, the count value is saved to the capture register (ttnccr0) upon detection of the valid edge of th e titn0 pin, and a capture interr upt (intttncc0) is output. the counter is cleared to 0000h by capture input. (c ounter clear operation is not performed using the ttnccr1 register.) the ttnccr0 register and the ttnccr1 register have their functions fixed as a capture register and a compare register, respectively. the ttnccr1 register can be rewritten during count operation. regard- ing compare register reload, the capture & clear timing upon detection of titn0 pin input serves as the reload timing. during count operation, a capture interrupt (in tttncc0) is output upon capture to the ttnccr0 register through titn0 pin input, and a compare match interrupt (intttncc1) is output upon a match between the counter and the ttnccr1 register. the totn0 pin becomes the level set with bit ttnol0. if ttnol0 = 0, a low level is output a and if ttnol0 = 1, a high level is output. the totn1 pin is reset upon a match between the counter and the ttnccr1 re gister, and is set when the counter is cleared to 0000h. figure 11-38: basic timing in offset trigger generation mode remark: n = 0, 1 in the offset trigger generation mode, the setting value of the ttnccr1 regist er is reloaded to the ttnccr1 buffer register upon detection of the valid edge of pin titn0. until the edge of the titn0 pin input is detected, the value of the ttnccr1 register is not reloaded to the ttnccr1 buffer register, even if this value is changed. pin totn1 is set when the counter is cleared to 0000h upon detection of the valid edge of pin titn0, and it is reset upon a match between the counter value and the ttnccr1 register. therefore, pin totn1 remains high level if the valid edge of the titn0 pin input is detected before a match with the ttnccr1 register occurs. xxxx i j k i j m n m n ttnccr0 ttnccr1 titn0 intttncc0 inttticc1 0000h k m n ttnccb1 n totn1 totn0 fixed (according to setting value of ttnol0) compare match interrupt capture interrupt compare match interrupt capture interrupt compare match interrupt capture interrupt
518 user?s manual u16580ee2v0ud00 [memo]
519 user?s manual u16580ee2v0ud00 chapter 12 16-bit 2-phase e ncoder input up/down co unter/general purpose timer (tmenc10) 12.1 features timer enc10 (tmenc10) is a 16-bit up/down counter that performs the following operations. ? general-purpose timer mode: - free-running timer - pwm output ? up/down counter mode -udc mode a -udc mode b 12.2 function outline ? compare register 2 ? capture/compare register 2 ? interrupt request source - capture/compare match interrupt 2 - compare match interrupt 2 - overflow interrupt 1 - underflow interrupt 1 ? capture request signal 2 - the tmenc10 value can be latched using the valid edge of the ticc10, ticc11 pins corresponding to the capture/compare register as the capture trigger. ? base clock (f clk ) = f xx /4 (f clk = 16 mhz @ f xx = 64 mhz) ? count clocks selectable through division by prescaler ? 2-phase encoder input the 2-phase encoder signal from external is used as the count clock of the timer counter with the external clock input pins (tiud1, tcud1). the counter mode can be selected from among the four following modes. mode 1: counts the input pulses of the count pulse input pin. up/down is specified by the le vel of one more input pin. mode 2: counts up/down using the respective input pulses of the up count pulse input pin and down count pulse input pin. mode 3: counts up/down using the phase relationship of the pulses input to 2 pins. mode 4: counts up/down using the phase relationship of the pulses input to 2 pins. counting is done using the respective rising edge s and the falling edges of the pulses. ? pwm output function - in the general-purpose timer mode, 16-bit resolution pwm output can be output from the to1 pin.
520 chapter 12 16-bit 2-phase encoder input up/d own counter/general purpose timer (tmenc10) user?s manual u16580ee2v0ud00 ? timer clear - the following timer clear operations are performed according to the mode that is used. (a) general-purpose timer mode: timer clear operation is possible upon occurrence of match with cm100 set value. (b) up/down counter mode: the timer clear operation can be selected from among the following four conditions. - timer clear performed upon occurrence of match with cm100 set value during tmenc10 up count operation, and timer clear performed upon occurrence of match with cm101 set value during tmenc10 down count operation. - timer clear performed only by external input. - timer clear performed upon occurrence of match between tmenc10 count value and cm100 set value. - timer clear performed upon occurrence of external input and match between tmenc10 count value and cm100 set value. ? external pulse output (to1) 1 remark: f xx : internal system clock
521 chapter 12 16-bit 2-phase encoder input up/down counter/general purpose timer (tmenc10) user?s manual u16580ee2v0ud00 12.3 basic configuration the basic configuration is shown below. remark: f xx : internal system clock table 12-1: timer enc10 configuration list timer count clock register read/write generated interrupt signal capture trigger timer enc10 f xx /8, f xx /16, f xx /32, f xx /64, f xx /128, f xx /256, f xx /512 tmenc10 read/write intovf intudf - cm100 read/write intcm10 - cm101 read/write intcm11 - cc100 read/write intcc10 ticc10 cc101 read/write intcc11 ticc11
522 chapter 12 16-bit 2-phase encoder input up/d own counter/general purpose timer (tmenc10) user?s manual u16580ee2v0ud00 figure 12-1 shows the block diagram of timer enc10. figure 12-1: block diagram of timer enc10 (tmenc10) note: the ticc11 interrupt is the signal of the interrupt from the ticc11 pin or the interrupt from the ticc10 pin, selected by the csl bit of the csl1 register. remark: f xx : internal system clock 1/2, 1/4, 1/8, 1/16, 1/32, 1/64, 1/128 edge detector output control selector selector edge detector edge detector edge detector edge detector clr1, clr0 cm11 cm10 tmenc1 tm10 clear controller cc11 cc10 msel cmd tm1ubd enmd alvt1 rlen tm1udf tm1ovf clear tclr internal bus internal bus tclr1/ ticc10 tcud1/ ticc11 tiud1 f xx /4 intcc10 intcc11 to1 intcm10 intcm11 intovf intudf
523 chapter 12 16-bit 2-phase encoder input up/down counter/general purpose timer (tmenc10) user?s manual u16580ee2v0ud00 (1) timer enc10 (tmenc10) tmenc10 is a 2-phase encoder input up/down counter and general-purpose timer. it can be read/written in 16-bit units. reset input clears tmenc10 to 0000h. cautions: 1. write to tmenc10 is enabled only when the tm1ce bit of the tmc10 register is ?0? (count operation disabled). 2. it is prohibited to clear the cmd bit (general-purpose timer mode) to 0 and to set the msel bit (udc mode b) of the tum register to 1. 3. continuous reading of tmenc10 is prohibited. if tmenc10 is continuously read, the second value read may differ from the actual value. if tmenc1n must be read twice, be sure to read another register between the first and the second read operation. 4. writing the same value to the tmenc10, cc100, and cc101 registers, and the status10 register is prohibited. writing the same value to the ccr10, tum10, tmc10, sesa10, and prm10 registers, and cm100 and cm101 registers is permitted (writing the same value is guaranteed even during a count operation). figure 12-2: timer enc10 (tmenc10) tmenc10 start and stop is controlled by the tm1ce bit of timer control register 10 (tmc10). the tmenc10 operation consists of the following two modes. (a) general-purpose timer mode in the general-purpose timer mode, tmenc10 operates as a 16-bit interval timer, free-running timer, or for pwm output. counting is performed based on the clock selected by software. division by the prescaler can be selected for the count clock from among f xx /8, f xx /16, f xx /32, f xx /64, f xx /128, f xx /256, or f xx /512 with bits prm102 to prm100 of prescaler mode register 10 (prm10) (f xx : internal system clock). (b) up/down counter mode (udc mode) in the udc mode, tmenc10 functions as a 16-b it up/down counter, counting based on the tcud1 and tiud1 input signals. two operation modes can be set with the msel bit of the tum register for this mode. ? udc mode a (when cmd bit = 1, msel bit = 0) tmenc10 can be cleared by setting the clr1 and clr0 bits of the tmc10 register. ? udc mode b (when cmd bit = 1, msel bit = 1) tmenc10 is cleared upon match with cm100 during tmenc10 up count operation. tmenc10 is cleared upon match with cm101 during tmenc10 down count operation. after reset: 0000h r/w address: fffff6b0h 1514131211109876543210 tmenc10
524 chapter 12 16-bit 2-phase encoder input up/d own counter/general purpose timer (tmenc10) user?s manual u16580ee2v0ud00 when the tm1ce bit of the tmc10 register is ?1?, tmenc10 counts up when the operation mode is the general-purpose mode, and counts up/down when the operation mode is the udc mode. the conditions for clearing the tmenc10 are classified as follows depending on the operation mode. remark: : indicates that the set value of that bit is ignored. table 12-2: timer enc10 (tmenc10) clear conditions operation mode tum10 register tmc10 register tmenc10 clear cmd bit msel bit enmd bit clr1 bit clr0 bit general-purpose timer mode 00 0 clearing not performed 1 cleared upon match with cm100 set value udc mode a 1 0 0 0 cleared only by tclr1 input 0 1 cleared upon match with cm1n0 set value during up count operation 1 0 cleared by tclr1 input or upon match with cm100 set value during up count operation 1 1 clearing not performed udc mode b 1 1 cleared upon match with cm100 set value during up count operation or upon match with cm101 set value during down count operation settings other than the above setting prohibited
525 chapter 12 16-bit 2-phase encoder input up/down counter/general purpose timer (tmenc10) user?s manual u16580ee2v0ud00 (2) compare register 100 (cm100) cm100 is a 16-bit register that always compares its value with the value of tmenc10. when the value of a compare register matches the value of tmenc10, an interrupt signal is generated. the interrupt generation timing in the various modes is described below. ? in the general-purpose timer mode (cmd bit of tum10 register = 0) and udc mode a (msel bit of tum10 register = 0), an interrupt signal (intcm10) is always generated upon occurrence of a match. ? in udc mode b (msel bit of tum10 register = 1), an interrupt signal (intcm10) is generated only upon occurrence of a match during up count operation. this register can be read/written in 16-bit units. reset input clears this register to 0000h. caution: when the tm1ce bit of the tmc10 register is 1, it is prohibited to overwrite the value of the cm100 register. figure 12-3: compare register 100 (cm100) after reset: 0000h r/w address: fffff6b2h 1514131211109876543210 cm100
526 chapter 12 16-bit 2-phase encoder input up/d own counter/general purpose timer (tmenc10) user?s manual u16580ee2v0ud00 (3) compare register 101 (cm101) cm101 is a 16-bit register that always compares its value with the value of tmenc10. when the value of a compare register matches the value of tmenc10, an interrupt signal is generated. the interrupt generation timing in the various modes is described below. ? in the general-purpose timer mode (cmd bit of tum10 register = 0) and udc mode a (msel bit of tum10 register = 0), an interrupt signal (intcm11) is always generated upon occurrence of a match. ? in udc mode b (msel bit of tumn register = 1), an interrupt signal (intcm11) is generated only upon occurrence of a match during down count operation. this register can be read/written in 16-bit units. reset input clears this register to 0000h. caution: when the tm1ce bit of the tmc10 register is 1, it is prohibited to overwrite the value of the cm101 register. figure 12-4: compare register 101 (cm101) after reset: 0000h r/w address: fffff6b4h 1514131211109876543210 cm101
527 chapter 12 16-bit 2-phase encoder input up/down counter/general purpose timer (tmenc10) user?s manual u16580ee2v0ud00 (4) capture/compare register 100 (cc100) cc100 is a 16-bit register. it can be used as a capture register or as a compare register through specification with capture/compare control register n (ccr). this register can be read/written in 16-bit units. reset input clears this register to 0000h. cautions: 1. when used as a capture register (cms0 bit of ccr register = 0), write access is prohibited. 2. when used as a compare register (cms0 bit of ccr register = 1) and the tm1ce bit of the tmc10 register is 1, overwriting the cc100 register values is prohibited. 3. when the tm1ce bit of the tmc10 register is 0, the capture trigger is disabled. 4. when the operation mode is changed from capture register to compare register, set a new compare value. 5. continuous reading of cc100 is prohibited. if cc100 is continuously read, the second read value may differ from the actual value. if cc100 must be read twice, be sure to read another register between the first and the second read operation. figure 12-5: capture/compare register 100 (cc100) (a) when set as a capture register when cc100 is set as a capture register, the valid edge of the corresponding external ticc10 signal is detected as the capture trigger. tmenc10 latches the count value in synchronization with the capture trigger (capture operation). the latched value is held in the capture register until the next capture operation. the valid edge of external interrupts (rising e dge, falling edge, both edges) is selected with signal edge selection register 10 (sesa10). when the cc100 register is specified as a capture register, an intcc10 interrupt is generated upon detection of the valid edge of the external ticc10 signal. (b) when set as a compare register when cc100 is set as a compare register, it always compares its own value with the value of tmenc10. if the value of cc100 matches the value of the tmenc10, cc100 generates an interrupt signal (intcc10). after reset: 0000h r/w address: fffff6b6h 1514131211109876543210 cc100
528 chapter 12 16-bit 2-phase encoder input up/d own counter/general purpose timer (tmenc10) user?s manual u16580ee2v0ud00 (5) capture/compare register 101 (cc101) cc101 is a 16-bit register. it can be used as a capture register or as a compare register through specification with capture/compare cont rol register (ccr). this register can be read/written in 16-bit units. reset input clears this register to 0000h. cautions: 1. when used as a capture register (cms1 bit of ccr register = 0), write access is prohibited. 2. when used as a compare register (cms1 bit of ccrn register = 1) and the tm1ce bit of the tmc10 register is 1, overwriting the cc101 register values is prohibited. 3. when the tm1ce bit of the tmc10 register is 0, the capture trigger is disabled. 4. when the operation mode is changed from capture register to compare register, set a new compare value. 5. continuous reading of cc101 is prohibi ted. if cc101 is continuously read, the second read value may differ from the actual value. if cc101 must be read twice, be sure to read another register between the first and the second read operation. figure 12-6: capture/compare register 101 (cc101) (a) when set as a capture register when cc101 is set as a capture register, the valid edge of the corresponding external ticc11 signal is detected as the capture trigger. tmenc1 0 latches the count value in synchronization with the capture trigger (capture operation). the latched value is held in the capture register until the next capture operation. the valid edge of external interrup ts (rising edge, falling edge, both edges) is selected with signal edge selection regi ster 10 (sesa10). when the cc101 register is specified as a capture register, an intcc11 interrupt is generated upon detection of the valid edge of the external ticc11 signal. (b) when set as a compare register when cc101 is set as a compare register, it always compares its own value with the value of tmenc10. if the value of cc101 matches the value of the tmenc10, cc101 generates an interrupt signal (intcc11). after reset: 0000h r/w address: fffff6b8h 1514131211109876543210 cc101
529 chapter 12 16-bit 2-phase encoder input up/down counter/general purpose timer (tmenc10) user?s manual u16580ee2v0ud00 12.4 control registers (1) timer unit mode register 10 (tum10) the tum10 register is an 8-bit register used to specify the tmenc10 operation mode or to control the operation of the pwm output pin. this register can be read/written in 8-bit or 1-bit units. reset input clears this register to 00h. cautions: 1. changing the value of the tum10 register during tmenc10 operation (tm1ce bit of tmc register = 1) is prohibited. 2. when the cmd bit = 0 (general-purpose timer mode), setting msel bit = 1 (udc mode b) is prohibited. figure 12-7: timer unit mode register 10 (tum10) after reset: 00h r/ w address: fffff6bbh 76543210 tum10 cmd 0 0 0 toe alvt1 0 msel cmd tmenc10 operation mode specification 0 general-purpose timer mode (up count) 1 udc mode (up/down count) toe timer output (to1) control 0 timer output disabled 1 timer output enabled when cmd bit = 1 (udc mode), timer output is not performed regardle ss of the setting of the toe bit. at this time, timer output consists of the inverted phase level of the level set by the alvt1 bit. alvt1 active level specification for timer output (to1) 0 active level is high level 1 active level is low level when cmd bit = 1 (udc mode), timer output is not performed regardle ss of the setting of the toe bit. at this time, timer output consists of the inverted phase level of the level set by the alvt1 bit. msel mode selection in udc mode (up/down count) 0 udc mode a. tmenc10 can be cleared by setting the clr1, clr0 bits of the tmc10 register. 1 udc mode b. tmenc10 is cleared in the following cases. ? upon match with cm100 during tmenc10 up count operation ? upon match with cm101 during tmenc10 down count operation when udc mode b is set, the enmd, clr1, and clr0 bits of the tmc10 register become invalid.
530 chapter 12 16-bit 2-phase encoder input up/d own counter/general purpose timer (tmenc10) user?s manual u16580ee2v0ud00 (2) timer control register 10 (tmc10) the tmc10 register is used to enable/disable tmenc10 operation and to set transfer and timer clear operations. this register can be read/written in 8-bit or 1-bit units. reset input clears this register to 00h. caution: changing the values of the tmc10 register bits other than the tm1ce bit during tmenc10 operation (tm1ce bit = 1) is prohibited. figure 12-8: timer control register 10 (tmc10) (1/2) after reset: 00h r/w address: fffff6bch 76543210 tmc10 0 tm1ce 0 0 rlen enmd clr1 clr0 tm1ce tmenc10 operation control 0 count operation disabled 1 count operation enabled rlen transfer operation control in udc mode a 0 transfer operation from cm100 register to tmenc10 disabled 1 transfer operation from cm100 register to tmenc10 enabled ? when rlen = 1, the value set to cm100 is transferred to tmenc10 upon occurrence of tmenc10 underflow. ? when the cmd bit of the tum10 register = 0 (general-purpose timer mode), the rlen bit settings are invalid, and a transfer operation is not executed even if the rlen bit is set to 1. ? when the msel bit of the tum10 register = 1 (udc mode b), the rlen bit settings are invalid, and a transfer operation is not executed even if the rlen bit is set to 1. enmd clear operation control in general purpose mode 0 clear disabled (free-running mode) clearing is not performed even when tmenc10 and cm100 values match. 1 clear enabled clearing is performed upon match of tmenc10 and cm100 values. when the cmd bit of the tum10 register = 1 (udc mode), the enmd bit setting becomes invalid.
531 chapter 12 16-bit 2-phase encoder input up/down counter/general purpose timer (tmenc10) user?s manual u16580ee2v0ud00 figure 12-8: timer control register 10 (tmc10) (2/2) clr1 clr0 clear operation control in udc mode a 0 0 clear only by external input (tclr1) 0 1 clear upon match of tmenc10 count value and cm100 set value 1 0 clear by tclr1 input or upon match of tmenc10 count value and cm100 set value 1 1 no clearing ? clearing by match of the tmenc10 count value and cm100 set value is valid only during tmenc10 up count operation (tme nc10 is not cleared during tmenc10 down count operation). ? when the cmd bit of the tum10 register = 0 (general-purpose timer mode), the clr1 and clr0 bit settings are invalid. ? when the msel bit of the tum10 register = 1 (udc mode b), the clr1 and clr0 bit settings are invalid. ? when clearing by tclr1n has been enabled with bits clr1 and clr0, clearing is performed whether the value of the tm1cen bit is 1 or 0.
532 chapter 12 16-bit 2-phase encoder input up/d own counter/general purpose timer (tmenc10) user?s manual u16580ee2v0ud00 (3) capture/compare control register 10 (ccr10) the ccr10 register specifies the operation mode of the capture/compare registers (cc100, cc101). this register can be read or written in 8-bit or 1-bit units. reset input clears this register to 00h. cautions: 1. overwriting the ccr10 register during tmenc10 operation (tm1ce bit = 1) is prohibited. 2. the tcud1 pin is used for the udc mode and shared with the external capture input pin ticc11. therefore, in the udc mode, the external capture function cannot be used. 3. the tclr1 pin is used for the udc mode and alternately shared with the external capture input pin ticc10. therefore, when the tclr1 input is used in udc mode a, the external capture function cannot be used. figure 12-9: capture/compare control register 10(ccr10) after reset: 00h r/w address: fffff6bah 76543210 ccr10 0 0 0000cms1cms0 cms1 cc101 operation mode specification 0 cc101 operates as capture register 1 cc101 operates as compare register cms0 cc100 operation mode specification 0 cc100 operates as capture register 1 cc100 operates as compare register
533 chapter 12 16-bit 2-phase encoder input up/down counter/general purpose timer (tmenc10) user?s manual u16580ee2v0ud00 (4) signal edge selectio n register 10 (sesa10) the sesa10 register specifies the va lid edge of external interrupt requests from external pins (ticc10, ticc11, tclr1). the valid edge (rising edge, fa lling edge, or both edges) can be sp ecified independe ntly for each pin. this register can be read or written in 8-bit or 1-bit units. reset input clears this register to 00h. cautions: 1. changing the valu es of the sesa10 register bi ts during tmenc10 operation (tm1ce bit = 1) is prohibited. 2. be sure to set (1) the tm1ce bit of timer control register 1 (tmc10) even when tmenc10 is not used and the ticc10 and ticc11 pins are used as external interrupts intcc10 and intcc11 respectively. 3. before setting the trigger mode of th e ticc10, ticc11, and tclr1n pins, set the pm10 and pmc10 registers. if the pm10 and pmc10 registers are set after the sesa10 register has been set, an ille gal interrupt, incorr ect counting, and incorrect clearing may occur, depending on the timing of setting the pm10 and pmc10 registers. figure 12-10: signal edge selecti on register 10 (sesa10) (1/2) after reset: 00h r/ w address: fffff6bdh 76543210 sesa10 tesud1 tesud0 cesud1 cesud0 ies111 ies110 ies101 ies100 tiud, tcud1 tclr1 ticc11 capture trigger ticc10 capture trigger tesud1 tesud0 valid edge specification of tiud1 and tcud1 pins 0 0 falling edge 0 1 rising edge 1 0 setting prohibited 1 1 both, rising and falling edges ? the set values of the tesud1 and tesud0 bits are only valid in udc mode a and udc mode b. ? if mode 4 is specified as the operation mode of tmenc10 (specified with prm102 to prm100 bits of prm10 register), the vali d edge specifications for the tiud1 and tcud1 pins (tesud1 and tesud0 bits) are not valid. cesud1 cesud0 valid edge and level specification of tclr1 pins 0 0 falling edge (tmenc10 cleared after edge detection) 0 1 rising edge (tmenc10 cleared after edge detection) 1 0 low level (tmenc10 clear status held) 1 1 high level (tmenc10 clear status held) the set values of the cesud1 and cesud0 bits are valid only in udc mode a.
534 chapter 12 16-bit 2-phase encoder input up/d own counter/general purpose timer (tmenc10) user?s manual u16580ee2v0ud00 figure 12-10: signal edge selectio n register 10 (sesa10) (2/2) ies111 ies110 valid edge specification of ticc11 capture trigger input pin 0 0 falling edge 0 1 rising edge 1 0 setting prohibited 1 1 both, rising and falling edges a valid edge on the ticc11 pin triggers the capture register cc101. simultaneously an interrupt (intcc11) is generated. ies101 ies100 valid edge specification of ticc10 capture trigger input pin 0 0 falling edge 0 1 rising edge 1 0 setting prohibited 1 1 both, rising and falling edges a valid edge on the ticc10 pin triggers the capture register cc100. simultaneously an interrupt (intcc10) is generated.
535 chapter 12 16-bit 2-phase encoder input up/down counter/general purpose timer (tmenc10) user?s manual u16580ee2v0ud00 (5) prescaler mode register 10 (prm10) the prm register is used to perform the following selections. ? selection of count clock in the general-purpose timer mode (cmd bit of tum10 register = 0) ? selection of count operation mode in the udc mode (cmd bit = 1) this register can be read or written in 8-bit or 1-bit units. reset input clears this register to 07h. cautions: 1. overwriting the prm10 register during tmenc10 operation (tm1ce bit = 1) is pro- hibited. 2. when the cmd bit of the tum10 register = 1 (udc mode), setting the values of the prm2 to prm0 bits to 000b, 001b, 010b, and 011b is prohibited. 3. when tmenc10 is in mode 4, specification of the valid edge for the tiud1 and tcud1 pins is invalid. figure 12-11: prescaler mode register 10 (prm10) remark: f xx : internal system clock (a) in general-purpose timer mode (cmd bit = 0) the count clock is fixed to the internal clock. the clock rate of tmenc10 is specified by the prm102 to prm100 bits. after reset: 07h r/ w address: fffff6beh 76543210 prm1000000prm102prm101prm100 prm102 prm101 prm100 cmd = 0 cmd = 1 count clock count clock udc mode 000setting prohibited setting prohibited 001f xx /8 010f xx /16 011f xx /32 100f xx /64 tiud1 mode 1 101f xx /128 mode 2 110f xx /256 mode 3 111f xx /512 mode 4
536 chapter 12 16-bit 2-phase encoder input up/d own counter/general purpose timer (tmenc10) user?s manual u16580ee2v0ud00 (b) udc mode (cmd bit = 1) the tmenc10 count triggers in the udc mode are as follows. operation mode tmenc10 operation mode 1 down count when tcud1 = high level up count when tcud1 = low level mode 2 up count upon detection of valid edge of tiud1 input down count upon detection of valid edge of tcud1 input mode 3 automatic judgment by t cud1 input level upon detection of valid edge of tiud1 input mode 4 automatic judgment upon detection of both edges of tiud1 input and both edges of tcud1 input
537 chapter 12 16-bit 2-phase encoder input up/down counter/general purpose timer (tmenc10) user?s manual u16580ee2v0ud00 (6) status register 10 (status10) the status10 register indicates the operating status of tmenc10. this register is read-only in 8-bit or 1-bit units. reset input clears this register to 00h. caution: overwriting the status10 register during tmenc10 operation (tm1ce bit = 1) is pro- hibited. figure 12-12: status register 10 (status10) after reset: 00h r/w address: fffff6bfh 76543210 status1000000tm1udftm1ovftm1ubd tm1udf tmenc10 underflow flag 0 no tmenc10 count underflow 1 tmenc10 count underflow the tm1udf bit is cleared (0) upon completion of read access to the status10 register from the cpu. tm1ovf tmenc10 overflow flag 0 no tmenc10 count overflow 1 tmenc10 count overflow the tm1ovf bit is cleared (0) upon completi on of read access to the status10 register from the cpu. tm1ubd tmenc10 up/down counter operation status 0 tmenc10 up count in progress 1 tmenc10 down count in progress the state of the tm1ubd bit differs according to the mode as follows. ? the tm1ubd bit is fixed to 0 when the cm d bit of the tum10 register = 0 (general- purpose timer mode). ? the tm1ubd bit indicates the tmenc10 up/do wn count status when the cmd bit of the tum register = 1 (udc mode)
538 chapter 12 16-bit 2-phase encoder input up/d own counter/general purpose timer (tmenc10) user?s manual u16580ee2v0ud00 12.5 operation 12.5.1 basic operation the following two operation modes can be selected for tmenc10. (1) general-purpose timer mode (cmd bit of tum10 register = 0) in the general-purpose timer mode, the tmenc10 operates either as a 16-bit interval timer or as a pwm output timer (count operation is up count only). the count clock to tmenc10 is selected by prescaler mode register 10 (prm10). (2) up/down counter mode (udc mode) (cmd bit of tum10 register = 1) in the udc mode, tmenc10 operates as a 16-bit up/down counter. external clock input (tiud1, tcud1 pins) set by prm10 register setting is used as the tmenc10 count clock. the udc mode is further divided into two modes according to the tmenc10 clear conditions. ? udc mode a (tum10 register?s cmd bit = 1, msel bit = 0) the tmenc10 clear source can be selected as exte rnal clear input (tclr1), the internal signal indicating a match between the tmenc10 count value and the cm100 set value during an up count operation, or the logical sum (or) of the two signals, using the clr1 and clr0 bits of the tmc10 register. tmenc10 can transfer (reload) the value of cm100 upon occurrence of tmenc10 underflow, when the rlen bit of the tmc10 register is set (1). ? udc mode b (tum10 register?s cmd bit = 1, msel bit = 1) the status of tmenc10 after a match of the tmenc10 count value and cm100 set value is as follows. <1> in case of an up count operation, tmenc10 is cleared (0000h), and the intcm10 interrupt is generated. <2> in case of a down count operation, the tmenc10 count value is decremented (-1). the status of tmenc10 after a match of the tmenc10 count value and cm101 set value is as follows. <1> in case of an up count operation, the tmenc10 count value is incremented (+1). <2> in case of a down count operation, tmenc10 is cleared (0000h), and the intcm11 interrupt is generated.
539 chapter 12 16-bit 2-phase encoder input up/down counter/general purpose timer (tmenc10) user?s manual u16580ee2v0ud00 12.5.2 operation in general-purpose timer mode tmenc10 can perform the following operations in the general-purpose timer mode. (1) interval operation tmenc10 and cm100 always compare their values and the intcm10 interrupt is generated upon occurrence of a match. tmenc10 is cleared (0000h) at the count clock following the match. furthermore, when one more count clock is input, tmenc10 counts up to 0001h. the interval time can be calculated by the following formula. interval time = (cm100 value + 1) tmenc10 count clock rate caution: interval operation can be achieved by se tting the enmd bit of the tmc register to 1. (2) free-running operation tmenc10 performs full count operation from 0000 h to ffffh, and after the tm1ovf bit of the status10 register is set (1), tmenc10 is cleared and resumes counting. the free-running cycle can be calculated by the following formula. free-running cycle = 65,536 tmenc10 count clock rate caution: the free-running operation can be achieved by setting the enmd bit of the tmc register to 0. (3) compare function tmenc10 connects two compare register (cm100, cm101) channels and two capture/compare register (cc100, cc101) channels. when the tmenc10 count value and the set value of one of the compare registers match, a match interrupt (intcm 10, intcm11, intcc10 note , intcc11 note ) is output. particularly in the case of an interval operation, tmenc10 is cleared upon generation of the intcm10 interrupt. note: this match interrupt is generated when cc100 and cc101 are set to the compare register mode.
540 chapter 12 16-bit 2-phase encoder input up/d own counter/general purpose timer (tmenc10) user?s manual u16580ee2v0ud00 (4) capture function tmenc10 connects two capture/compare register (cc100, cc101) channels. when cc100 and cc101 are set to the capture register mode, the value of tmenc10 is captured in synchronization with the corresponding capture trigger signal. furthermore, an interrupt request (intcc10, intcc11) is generated by the ticc10, ticc11 input signals. remark: cc100 and cc101 are capture/compare registers. which of these registers is used is specified with capture/compare control register 1 (ccr10). the valid edge of the capture trigger is spec ified by signal edge select ion register 10 (sesa10). if both the rising edge and the fallin g edge are selected as the capt ure triggers, it is possible to measure the input pulse width from external. if a single edge is selected as the capture trigger, the input pulse cycle ca n be measured. (5) pwm output operation pwm output operation is performed from the to1 pin by setting tmenc10 to the general-purpose timer mode (cmd bit of the tum10 register = 0). the resolution is 16 bits, and the count clock can be selected from among seven internal clocks (f xx /8, f xx /16, f xx /32, f xx /64, f xx /128, f xx /256, f xx /512). figure 12-13: tmenc10 block diagram (during pwm output operation) remark: f xx : internal system clock table 12-3: capture trigger signal to 16-bit capture register capture register capture trigger signal cc100 ticc10 cc101 ticc11 tmenc1 (16 bits) compare register (cm10) compare register (cm11) s intcm10 intcm11 alvt1 tum1 register clear 16 16 to1n q r f xx /8 f xx /16 f xx /32 f xx /64 f xx /128 f xx /256 f xx /512
541 chapter 12 16-bit 2-phase encoder input up/down counter/general purpose timer (tmenc10) user?s manual u16580ee2v0ud00 ? description of operation the pwm output cycle is specified by using the compare register cm100. when the value of this register matches the value of tmenc10, the intcm10 interrupt is generated, and tmenc10 is cleared at the next count clock after the match. the required pwm output duty is set by using the compare register cm101. figure 12-14: pwm signal output exam ple (when alvt10 bit = 0 is set) cautions: 1. changing the values of the cm100 and cm101 registers is prohibited during tmenc10 operation (tm1ce bit of tmc10 register = 1). 2. changing the value of the alvt1 bit of the tum register is prohibited during tmenc10 operation. 3. pwm signal output is performed from the second pwm cycle after the tm1ce bit is set (1). cm10 set value cm11 set value tmenc1 to1 intcm10 intcm11
542 chapter 12 16-bit 2-phase encoder input up/d own counter/general purpose timer (tmenc10) user?s manual u16580ee2v0ud00 12.5.3 operation in udc mode (1) overview of operation in udc mode the count clock input to tmenc10 in the udc mode (cmd bit of tum10 register = 1) can only be externally input from the tiud1 and tcud1 pins. up/down count judgment in the udc mode is determined based on the phase difference of the tiud1 and tcud1 pin inputs according to the prm10 register setting (there is a total of four choices). the udc mode is further divided into two modes ac cording to the tmenc10 clear conditions (count operation is performed only with tiud1, tcud1 input in both modes). ? udc mode a (tum register?s cmd bit = 1, msel bit = 0) the tmenc10 clear source can be selected as only external clear input (tclr1), a match signal between the tmenc10 count value and the cm100 set value during up count operation, or logical sum (or) of the two signals, using bits clr1 and clr0 of the tmc10 register. tmenc10 can transfer (reload) the value of cm100 upon occurrence of tmenc10 underflow, when the rlen bit of the tmc10 register is set (1). ? udc mode b (tumn register?s cmd bit = 1, msel bit = 1) the status of tmenc10 after match of the tmenc10 count value and cm100 set value is as follows. <1> in case of an up count operation, tmenc10 is cleared (0000h), and the intcm10 interrupt is generated. <2> in case of a down count operation, the tmenc10 count value is decremented (-1). the status of tmenc10 after match of the tmenc10 count value and cm101 set value is as follows. <1> in case of an up count operation, the tmenc10 count value is incremented (+1). <2> in case of a down count operation, tmenc10 is cleared (0000h), and the intcm11 interrupt is generated. table 12-4: list of count operations in udc mode prm10 register operation mode tm1n operation prm102 prm101 prm100 1 0 0 mode 1 down count when tcud1 = high level up count when tcud1 = low level 1 0 1 mode 2 up count upon detection of valid edge of tiud1 input down count upon detection of valid edge of tcud1 input 1 1 0 mode 3 automatic judgment in tcud1 input level upon detection of valid edge of tiud1 input 1 1 1 mode 4 automatic judgment upon detection of both edges of tiud1 input and both edges of tcud1 input
543 chapter 12 16-bit 2-phase encoder input up/down counter/general purpose timer (tmenc10) user?s manual u16580ee2v0ud00 (2) up/down count operation in udc mode tmenc10 up/down count judgment in the udc mode is determined based on the phase difference of the tiud1 and tcud1 pin inputs according to the prm register setting. (a) mode 1 (prm12 to prm10 bits = 100b) in mode 1, the following count operations are performed based on the level of the tcud1 pin upon detection of the valid edge of the tiud1 pin. ? tmenc10 down count operation when tcud1 pin = high level ? tmenc10 up count operation when tcud1 pin = low level figure 12-15: mode 1 (when rising edge is specified as valid edge of tiud1 pin) figure 12-16: mode 1 (when rising edge is specified as valid edge of tiud1 pin): in case of simultaneous tiud1, tcud1 pin edge timing tiud1 tcud1 tmenc1 0006h 0007h down count up count 0005h 0004h 0005h 0006h 0007h 0007h tiud1 tcud1 tmenc1 0006h down count up count 0005h 0004h 0005h 0006h 0007h
544 chapter 12 16-bit 2-phase encoder input up/d own counter/general purpose timer (tmenc10) user?s manual u16580ee2v0ud00 (b) mode 2 (prm102 to prm100 bits = 101b) the count conditions in mode 2 are as follows. ? tmenc10 up count upon detection of valid edge of tiud1 pin ? tmenc10 down count upon detection of valid edge of tcud1 pin caution: if the count clock is simultaneously input to the tiud1 pin and the tcud1 pin, count operation is not performed and the immediately preceding value is held. figure 12-17: mode 2 (when rising edge is sp ecified as valid edge of tiud1, tcud1 pins) 0006h tiud1 tcud1 tmenc1 0007h 0008h up count hold value down count 0007h 0006h 0005h
545 chapter 12 16-bit 2-phase encoder input up/down counter/general purpose timer (tmenc10) user?s manual u16580ee2v0ud00 (c) mode 3 (prm102 to prm100 bits = 110b) in mode 3, when two signals 90 degrees out of phase are input to the tiud1 and tcud1 pins, the level of the tcud1 pin is sampled at the timing of the valid edge of the tiud1 pin (refer to figure 12-18 ). if the tcud1 pin level sampled at the valid edge timing of the tiud1 pin is low, tmenc10 counts down. if the tcud1 pin level sampled at the valid edge timing of the tiud1 pin is high, tmenc10 counts up. figure 12-18: mode 3 (when rising edge is specified as valid edge of tiud1 pin) figure 12-19: mode 3 (when rising edge is specified as valid edge of tiud1 pin): in case of simultaneous tiud1, tcud1 pin edge timing 0007h tiud1 tcud1 tmenc1 0008h up count down count 0009h 000ah 0009h 0008h 0007h 0007h tiud1 tcud1 tmenc1 0008h up count down count 0009h 000ah 0009h 0008h 0007h
546 chapter 12 16-bit 2-phase encoder input up/d own counter/general purpose timer (tmenc10) user?s manual u16580ee2v0ud00 (d) mode 4 (prm102 to prm100 bits = 111b) in mode 4, when two signals out of phase are input to the tiud1 and tcud1 pins, up/down operation is automatically judged and counting is performed according to the timing shown in figure 12-20 . in mode 4, counting is executed at both the rising and falling edges of the two signals input to the tiud1 and tcud1 pins. therefore, tmenc10 counts four times per cycle of an input signal ( 4 count). figure 12-20: mode 4 cautions: 1. when mode 4 is specified as the operation mode of tmenc10, the valid edge specifications for pins tiud1 and tcud1 are not valid. 2. if the tiud1 pin edge a nd tcud1 pin edge are input simultaneously in mode 4, tmenc10 continues the same count operation (up or down) it was performing immediately before the input. tiud1 tcud1 tmenc1 0004h 0003h 0006h 0005h 0008h 0007h 000ah 0009h 0008h 0009h 0006h 0007h 0005h up count down count
547 chapter 12 16-bit 2-phase encoder input up/down counter/general purpose timer (tmenc10) user?s manual u16580ee2v0ud00 (3) operation in udc mode a (a) interval operation the operations at the count clock following a match of the tmenc10 count value and the cm100 set value are as follows. ? in case of up count operation: tmenc10 is cleared (0000h) and the intcm10 interrupt is generated. ? in case of down count operation: the tmenc10 count value is decremented (-1) and the intcm10 interrupt is generated. remark: the interval operation can be combined with the transfer operation. (b) transfer operation the operations at the next count clock after the count value of tmenc10 becomes 0000h during tmenc10 count down operation are as follows. ? in case of down count operation: the data held in cm100 is transferred. ? in case of up count operation: the tmenc10 count value is incremented (+1). remarks: 1. transfer enable/disable can be set with the rlen bit of the tmc10 register. 2. the transfer operation can be combined with the interval operation. figure 12-21: example of tmenc10 operation when interval operation and transfer operation are combined tmenc1 and cm10 match & timer clear tmenc1 underflow & cm10 data transfer tmenc1 count value cm10 set value up count down count 0000h
548 chapter 12 16-bit 2-phase encoder input up/d own counter/general purpose timer (tmenc10) user?s manual u16580ee2v0ud00 (c) compare function tm1n connects two compare register (cm100, cm101) channels and two capture/compare register (cc100, cc101) channels. when the tmenc10 count value and the set value of one of the compare registers match, a match interrupt (intcm10, intcm11, intcc10 note , intcc11 note ) is output. note: this match interrupt is generated when cc100 and cc101 are set to the compare register mode. (d) capture function tmenc10 connects two capture/compare register (cc100, cc101) channels. when cc100 and cc101 are set to the capture register mode, the value of tmenc10 is captured in synchronization with the corresponding capture trigger signal. when the tmenc10 is set to the capture register mode, a capture interrupt (intcc10, intcc11) is generated upon detection of the valid edge. (4) operation in udc mode b (a) basic operation the operations at the next count clock after the count value of tmenc10 and the cm100 set value match when tmenc10 is in ud c mode b are as follows. ? in case of up count operation: tmenc10 is cleared (0000h) and the intcm10 interrupt is generated. ? in case of down count operation: the tmenc10 count value is decremented (-1). the operations at the next count clock after the count value of tmenc10 and the cm101 set value match when tmenc10 is in ud c mode b are as follows. ? in case of up count operation: the tmenc10 count value is incremented (+1). ? in case of down count operation: tmenc10 is cleared (0000h) and the intcm11 interrupt is generated. figure 12-22: example of tm1operation in udc mode cm10 set value cm11 set value tmenc1 count value clear tmenc1 not cleared if count clock counts down following match clear tmenc1 not cleared if count clock counts up following match
549 chapter 12 16-bit 2-phase encoder input up/down counter/general purpose timer (tmenc10) user?s manual u16580ee2v0ud00 (b) compare function tmenc10 connects two compare register (cm100, cm101) channels and two capture/compare register (cc100, cc101) channels. when the tmenc10 count value and the set value of one of the compare registers match, a match interrupt (intcm10 (only during up count operation), intcm11 (only during down count operation), intcc10 note , intcc11 note ) is output. note: this match interrupt is generated when cc100 and cc101 are set to the compare register mode. (c) capture function tmenc10 connects two capture/compare register (cc100, cc101) channels. when cc100 and cc101 are set to the capture register mode, the value of tmenc10 is captured in synchronization with the corresponding capture trigger signal. when the tmenc10 is set to the capture register mode, a capture interrupt (intcc10, intcc11) is generated upon detection of the valid edge.
550 chapter 12 16-bit 2-phase encoder input up/d own counter/general purpose timer (tmenc10) user?s manual u16580ee2v0ud00 12.6 supplementary description of internal operation 12.6.1 clearing of count value in udc mode b when tmenc10 is in udc mode b, the co unt value clear operation is as follows. ? in case of tmenc10 up count operation: tmenc10 is cleared upon match with cm100 ? in case of tmenc10 down count operation: tmenc10 is cleared upon match with cm101 figure 12-23: clear operation upon match with cm100 during tmenc10 up count operation remark: items between parentheses in the above figure apply to down count operation. figure 12-24: clear operation upon match with cm101 during tmenc10 down count operation remark: items between parentheses in the above figure apply to up count operation. count clock (rising edge set as valid edge) cm10 fffeh clear tmenc1 (not clear tmenc1) tmenc1 ffffh 0000h (fffeh) 0001h (fffdh) ffffh up count up count (down count) count clock (rising edge set as valid edge) cm11 00ffh tmenc1 00feh 0000h (00ffh) ffffh (0100h) 00feh up count down count (up count) clear tmenc1 (not clear tmenc1)
551 chapter 12 16-bit 2-phase encoder input up/down counter/general purpose timer (tmenc10) user?s manual u16580ee2v0ud00 12.6.2 clearing of count value upon occurrence of compare match the internal operation during tmenc10 clear operation upon occurrence of a compare match is as follows. figure 12-25: count value clear operation upon compare match caution: the operations at the next count clock after the count value of tmenc10 and the cm100 set value match are as follows. ? in case of up count: clear operation is performed. ? in case of down count: clear operation is not performed. remark: items between parentheses in the above figure apply to down count operation. 12.6.3 transfer operation the internal operation during tmenc10 transfer operation is as follows. figure 12-26: internal operation during transfer operation caution: the count operations after the tmenc10 count value becomes 0000h are as follows. ? in case of down count: transfer operation is performed. ? in case of up count: transfer operation is not performed. remark: items between parentheses in the above figure apply to up count operation. count clock (rising edge set as valid edge) cm10 fffeh tmenc1 ffffh 0000h (fffeh) 0001h (fffdh) ffffh up count up count (down count) clear tmenc1 (not clear tmenc1) count clock (rising edge set as valid edge) cm10 0001h transfer operation is performed. (transfer operation is not performed.) tmenc1 0000h ffffh (0001h) fffeh (0002h) ffffh down count down count (up count)
552 chapter 12 16-bit 2-phase encoder input up/d own counter/general purpose timer (tmenc10) user?s manual u16580ee2v0ud00 12.6.4 interrupt signal output upon compare match an interrupt signal is output when the count value of tmenc10 matches the set value of the cm100, cm101, cc10 note , or cc11 note register. the interrupt generation timing is as follows. note: when cc100 and cc101 are set to the compare register mode. figure 12-27: interrupt output upon compare match (cm101 with operation mode set to general-purpose timer mode and count clock set to f xx /8) remark: f clk : base clock an interrupt signal such as illustra ted in figure 12-27 is output at t he next count following match of the tmenc10 count value and the set value of a corresponding compare register. 12.6.5 tm1ubd flag (bit 0 of status register) operation in the udc mode (cmd bit of tum register = 1), the tm1ubd flag changes as follows during tmenc10 up/down count operation at every internal operation clock. figure 12-28: tm1ubdn flag operation count clock f xx /4 cm11 0007h tmenc1 internal match signal intcm11 0008h 000bh 0009h 0009h 000ah count clock tm1ubd 0001h 0000h tmenc1 0000h 0001h 0001h 0000h
553 user?s manual u16580ee2v0ud00 chapter 13 auxiliary frequenc y output f unction (afo) 13.1 features ? frequency up to 8 mbps ? programmable frequency output ? interval timer function ? interrupt request signal (intbrg2) 13.2 configuration the afo function includes the following hardware. table 13-1: afo configuration figure 13-1: block diagram of auxiliary frequency output function item configuration control registers prescaler mode registers 2 (prsm2) prescaler compare registers 2 (prscm2) afo intbrg2 prscm2 8-bit counter output control f xx f/2 xx f/4 xx f/8 xx
554 chapter 13 auxiliary frequency output function (afo) user?s manual u16580ee2v0ud00 13.3 control registers (1) prescaler mode register 2 (prsm2) the prsm2 register controls generation of a baud rate signal for the afo function. this register can be read or written in 8-bit or 1-bit units. reset input clears this register to 00h. figure 13-2: prescaler mode register 2 (prsm2) cautions: 1. do not rewrite the prsm2 register during operation. 2. set the bgcs21, bgcs20 bits before setting the bgce2 bit to 1. after reset: 00h r/w address: fffffde0h 76543210 prsm2 0 0 bgce2 0 0 bgcs21 bgcs20 bgce2 baud rate generator output control 0 disabled 1 enabled bgcs21 bgcs20 baud rate generator clock selection (f bgcs2 ) setting value (k) 00f xx 0 01f xx /2 1 10f xx /4 2 11f xx /8 3
555 chapter 13 auxiliary frequency output function (afo) user?s manual u16580ee2v0ud00 (2) prescaler compare registers 2 (prscm2) the prscm2 register is an 8-bit compare register. this register can be read or written in 8-bit units. reset input clears this register to 00h. figure 13-3: prescaler compare register 2 (prscm2) cautions: 1. do not rewrite the prscm2 register during operation. 2. set the prscm2 register before setting the bgce2 bit of the prsm2 register to 1. 3. do not set the afo clock to a higher frequency than 8 mhz. remark: f bgcs2 : clock frequency selected by the bgcs21, bgcs20 bits of the prsm2 register. after reset: 00h r/w address: fffffde1h 76543210 prscm2 prscm27 prscm26 prscm25 prscm 24 prscm23 prscm22 prscm21 prscm20 prscm 27 prscm 26 prscm 25 prscm 24 prscm 23 prscm 22 prscm 21 prscm 20 afo clock n 00000000f bgsc2 /256 256 00000001f bgsc2 1 00000010f bgsc2 /2 2 :::::::: : : 11111100f bgsc2 /252 252 11111101f bgsc2 /253 253 11111110f bgsc2 /254 254 11111111f bgsc2 /255 255
556 chapter 13 auxiliary frequency output function (afo) user?s manual u16580ee2v0ud00 13.4 operation 13.4.1 auxiliary frequency output the auxiliary frequency output (afo) is enabled as soon as the shar ed port (p75) is set into control output mode by setting bit 5 of the pm7 register to 0 and bit 5 of the pmc7 register to 1. 13.4.2 auxiliary frequency generation the auxiliary frequency output clock is generated by dividing the main clock. the baud rate generated from the main clock is obtained by the following equation. remarks: 1. f afo : afo clock 2. f bgcs2 : clock frequency selected by the bgcs21, bgcs20 bits of the prsm2 register. 3. f xx : main clock oscillation frequency 4. k: prsm2 register setting value (2 k 5) 5. n: prscmm register setting value (1 to 255), when prscm2 = 01h to ffh, or n = 256, when prscm2 = 00h. 13.4.3 interval timer function the afo function can be used as interval timer re gardless whether the auxilia ry frequency output is used or not. for this purpose an interrupt request signal (intbrg2) is assigned, which can be handled like any maskable interrupt. f afo f bgcs2 n2 ------------------- f xx 2 k n2 --------------------------- - ==
557 user?s manual u16580ee2v0ud00 chapter 14 a/d converter 14.1 features ? analog input: 2 10 channels (ani00 to ani09, ani10 to ani19) ? 10-bit resolution ? on-chip a/d conversion result register (adcrn0 to adcrn9): 10 bits 10 ? a/d conversion trigger mode - a/d trigger mode - timer trigger mode - external trigger mode ? successive approximation method ? dma transfer support of a/d conversion result to internal ram remark: n = 0, 1
558 chapter 14 a/d converter user?s manual u16580ee2v0ud00 14.2 configuration the a/d converter of the v850e/ph2 adopts the successive approximation method, and uses a/d con- verter n mode registers 0, 1, 2 (admn0, admn1, admn2), and the a/d conversion result register (adcrn0 to adcrn9) to perform a/d conversion operations (n = 0, 1). (1) input circuit the input circuit selects the analog input (anin0 to anin9) according to the mode set by the admn0, admn1, and admn2 registers. (2) c-array holds the charge of the differential voltage between the voltage input from the analog input pins (anin0 to anin9) and the reference voltage (1/2 av dd ), and redistributes the sampled charges. (3) c-dummy this block holds the reference voltage (1/2 av dd ) and assigns the reference of the comparator input. (4) voltage comparator the voltage comparator compares the c-array comparison potential with the c-dummy reference potential. (5) a/d conversion result regi ster (adcrnm), a/d conversion re sult register nh (adcrnmh) (n = 0, 1)(m = 0 to 9) adcrnm is a 10-bit register that holds a/d conversion results. each time a/d conversion is completed, the conversion results are loaded from the successive approximation register (sar). reset input makes this register undefined. (6) a/d conversion result register for dma transfer (addman) (n = 0, 1) addman is a 16-bit register that holds the last 10-bit a/d conversion result and an over rung flag for indicating a dma transfer failure. (7) anin0 to anin9 pins (n = 0, 1) these are 10-channel analog input pins for the a/d converter n. they input the analog signals to be a/d converted. caution: make sure that the voltages input to anin0 to anin9 do not exceed the rated values. if a voltage higher than av dd or lower than av ssn (even within the range of the absolute maximum ratings) is input to a channel, the conversion value of the channel is undefined, and the conversion values of the other channels may also be affected. (8) av refn pins (n = 0, 1) this is the pin for inputting the reference voltage of the a/d converter. it converts signals input to the anin0 to anin9 pins to digital signals based on the voltage applied between av ssn and av refn .
559 chapter 14 a/d converter user?s manual u16580ee2v0ud00 (9) av ssn pin (n = 0, 1) this is the ground pin of the a/d converter. always use this pin at the same potential as that of the ev ss pin even when the a/d converter is not used. (10) av dd pin this is the analog power supply pin of both a/d converters (adc0, adc1). figure 14-1: block diagram of a/d converter (adcn) remarks: 1. f xx : main clock 2. n = 0, 1 cautions: 1. if there is noise at the analog input pins (anin0 to anin9) or at the reference voltage input pin (av refn ), that noise may generate an illegal conversion result. software processing will be needed to avoid a negative effect on the system from this illegal conversion result. an example of this software processing is shown below. ? take the average result of a number of a/d conversions and use that as the a/d conversion result. ? execute a number of a/d conversions consecutively and use those results, omitting any exceptional results that may have been obtained. 2. do not apply a voltage outside the av ssn to av refn range to the pins that are used as a/d converter input pins. successive approximation register (sar) comparator av refn av dd av ssn c-dummy c-array adcrn9 (adcrn9h) adcrn8 (adcrn8h) adcrn7 (adcrn7h) adcrn6 (adcrn6h) adcrn5 (adcrn5h) adcrn4 (adcrn4h) adcrn2 (adcrn2h) adcrn1 (adcrn1h) adcrn0 (adcrn0h) addman adcrn3 (adcrn3h) intadn addmarqn controller f/4 xx adtrgn anin0 anin1 anin2 anin3 anin4 anin5 anin6 anin7 anin8 anin9 tr0adtrg0 trigger events from tmr0 trigger events from tmr1 tr1adtrg0 tr0adtrg1 tr1adtrg1 inttr0od inttr1od inttr0cd inttr1cd trigger selector edge detection input circuit
560 chapter 14 a/d converter user?s manual u16580ee2v0ud00 14.3 control registers (1) a/d converter n mode register 0 (admn0) the admn0 register is an 8-bit register that specifies the operation mode, and executes conversion operations. this register can be read or written in 8-bit or 1- bit units. however, bit 6 can only be read. writing this bit is ignored. reset input sets this register to 00h. cautions: 1. when the adcen bit is 1 in the timer trigger mode and external trigger mode, the trigger signal standby state is set. to clear the adcen bit, write 0 or reset. in the a/d trigger mode, the conversion trigger is set by writing 1 to the adcen bit. after the operation, when the mode is changed to the timer trigger mode or external trigger mode without clearing the adcen bit, the trigger input standby state is set immediately after changing the register. 2. changing the setting of the bsn and msn bits is prohibited while a/d conversion is enabled (adcen bit = 1). 3. when data is written to the admn0 register during an a/d conversion operation, the conversion operation is initialized and conversion is executed from the beginning. figure 14-2: a/d converter n mode register 0 (admn0) remark: n = 0, 1 after reset: 00h r/w ad dress: adm00 fffff200h, adm10 fffff240h 76543210 admn0adcenadcsnbsnmsn0000 (n = 0, 1) adcen a/d conversion o peration control of adcn 0 disables a/d conversion operation of adcn 1 enables a/d conversion operation adcn adcsn a/d conversion status flag of adcn 0 a/d conversion of adcn is stopped 1 a/d conversion of adcn is operating bsn adcn buffer mode specification 0 1-buffer mode 1 4-buffer mode msn adcn operation mode specification 0 scan mode 1 select mode
561 chapter 14 a/d converter user?s manual u16580ee2v0ud00 (2) a/d converter n mode register 1 (admn1) the admn1 register is an 8-bit register that specifies the conversion operation time and trigger mode. this register can be read or written in 8-bit or 1-bit units. reset input sets this register to 00h. cautions: 1. changing the setting of the egan1, egan0, and frn3 to frn0 bits is prohibited while a/d conversion is enabled (adcen bit of the admn0 register = 1). 2. when data is written to the admn1 register during an a/d conversion operation, the conversion operation is initialized and conversion is executed from the beginning. figure 14-3: a/d converter n mode register 1 (admn1) (1/2) remark: n = 0, 1 after reset: 00h r/w add ress: adm01 fffff201h, adm11 fffff241h 76543210 admn1 egan1 egan0 trgn1 trgn0 frn3 frn2 frn1 frn0 (n = 0, 1) egan1 egan0 valid edge specification of external trigger input (adtrgn) 0 0 no edge detected (does not operate as external trigger) 0 1 falling edge detected 1 0 rising edge detected 1 1 both edges, falling and rising edge detected trgn1 trgn0 adcn trigger mode specification 0 0 a/d trigger mode 0 1 timer trigger mode 1 0 external trigger mode 1 1 setting prohibited
562 chapter 14 a/d converter user?s manual u16580ee2v0ud00 figure 14-3: a/d converter n mode register 1 (admn1) (2/2) notes: 1. set the conversion operation time in the range of 2 to 10 s. 2. after the adcen bit is set from 0 to 1 to secu re the stabilization time of the a/d converter, conversion is started after t he a/d stabilization time has elap sed only before the first a/d conversion is executed. cautions: 1. do not change the set value of the a/d conversion time (frn3 to frn0 bits) during an a/d conversion operation (adcen bit = 1). to change the value, clear the adcen bit to 0. 2. when the trigger mode (trgn1 and tgrn0 bits) is changed midway, a/d conversion can be started immediately without having to secure the a/d stabilization time by re-setting the adce bit to 1. remarks: 1. f xx : main clock 2. n = 0, 1 frn3 frn2 frn1 frn0 number of conversion clocks conversion operation time note 1 f xx = 64 mhz a/d stabilization time note 2 00001282.0 s 64/f xx 00012564.0 s 128/f xx 00103846.0 s 160/f xx 00115128.0 s 160/f xx 0100640setting prohibited 160/f xx 0101768 160/f xx others than above setting prohibited
563 chapter 14 a/d converter user?s manual u16580ee2v0ud00 (3) a/d converter n mode register 2 (admn2) the admn2 register is an 8-bit register that specifies the analog input pin of the a/d converter n (n = 0, 1). this register can be read or written in 8-bit or 1-bit units. reset input sets this register to 00h. cautions: 1. if a channel for which no analog input pin exists is specified, the result of a/d conversion is undefined. 2. changing the setting of the anisn3 to anisn0 bits is prohibited while a/d conversion is enabled (adcen bit of the admn0 register = 1). 3. when data is written to the admn2 register during an a/d conversion operation, the conversion operation is initialized and conversion is executed from the beginning. figure 14-4: a/d converter n mode register 2 (admn2) remark: n = 0, 1 after reset: 00h r/w add ress: adm01 fffff201h, adm11 fffff241h 76543210 admn20000anisn3anisn2anisn1anin0 (n = 0, 1) anin3 anin2 anin2 anin0 specificatio n of analog input pins for a/d conversion select mode scan mode 0000anin0 anin0 0001anin1 anin0, anin1 0010anin2 anin0 to anin2 0011anin3 anin0 to anin3 0100anin4 anin0 to anin4 0101anin5 anin0 to anin5 0110anin6 anin0 to anin6 0111anin7 anin0 to anin7 1000anin8 anin0 to anin8 1001anin9 anin0 to anin9 others than above setting prohibited
564 chapter 14 a/d converter user?s manual u16580ee2v0ud00 (4) a/d converter n trigger source select register (adtrseln) the adtrseln register is an 8-bit register that specifies the timer trigger signal in the timer trigger mode (trgn1, trgn0 bits of admn1 register = 01b). this register can be read or written in 8-bit units. reset input sets this register to 00h. caution: before changing the setting of the adt rseln register, stop the a/d conversion oper- ation (by clearing the adcen bit of the admn0 register to 0). the operation is not guaranteed if the setting of the adtrseln register is changed while a/d conversion is enabled (adcen bit = 1). figure 14-5: a/d converter n trigger source select register (adtrseln) remark: n = 0, 1 after reset: 00h r/w address: adtrsel0 fffff270h, adtrsel1 fffff272h 76543210 adtrseln 0 0 0 0 tseln3 t seln2 tseln1 tseln0 (n = 0, 1) tseln3 tseln2 tseln2 tseln0 tr igger source selection in timer trigger mode 0000none. all trigger sources are ignored. 0001tr0adtrg0 signal (from tmr0) 0010tr0adtrg1 signal (from tmr0) 0011tr1adtrg0 signal (from tmr1) 0100tr1adtrg1 signal (from tmr1) 0101inttr0od interrupt (from tmr0) 0110inttr0cd interrupt (from tmr0) 0111inttr1od interrupt (from tmr1) 1000inttr1cd interrupt (from tmr1) others than above s etting prohibited
565 chapter 14 a/d converter user?s manual u16580ee2v0ud00 (5) a/d conversion result registers n0 to n9 , n0h to n9h (adcrn0 to adcrn9, adcrn0h to adcrn9h) the adcrnm register is a 10-bit register holding the a/d conversion results (n = 0, 1)(m = 0 to 9). these registers are read-only in 16-bit or 8-bit units. when 16-bit access is performed, the adcrnm register is specified, and when 8 bit access is performed, the adcrnmh register holding the higher 8 bits of the conversion result is specified. when reading the 10-bit data of the a/d conversion results from the adcrnm register, only the higher 10 bits are valid and the lower 6 bits are always read as 0. reset input causes an undefined register content. figure 14-6: a/d conversion result registers n0 to n9, n0h to n9h (adcrn0 to adcrn9, adcrn0h to adcrn9h) remark: n = 0, 1 m = 0 to 9 after reset: undefined r address: adcr00 fffff210h, adcr10 fffff250h, adcr01 fffff212h, adcr11 fffff252h, adcr02 fffff214h, adcr12 fffff254h, adcr03 fffff216h, adcr13 fffff256h, adcr04 fffff218h, adcr14 fffff258h, adcr05 fffff21ah, adcr15 fffff25ah, adcr06 fffff21ch, adcr16 fffff25ch, adcr07 fffff21eh, adcr17 fffff25eh, adcr08 fffff220h, adcr18 fffff260h, adcr09 fffff222h, adcr19 fffff262h, 1514131211109876543210 adcrnm adnm9 adnm8 adnm7 adnm6 adnm5 adnm4 adnm3 adnm2 adnm1 adnm0 000000 adcrnmh after reset: undefined r address: ad cr00h fffff210h, adcr10h fffff250h, adcr01h fffff212h, adcr11h fffff252h, adcr02h fffff214h, adcr12h fffff254h, adcr03h fffff216h, adcr13h fffff256h, adcr04h fffff218h, adcr14h fffff258h, adcr05h fffff21ah, adcr15h fffff25ah, adcr06h fffff21ch, adcr16h fffff25ch, adcr07h fffff21eh, adcr17h fffff25eh, adcr08h fffff220h, adcr18h fffff260h, adcr09h fffff222h, adcr19h fffff262h, 76543210 adcrnmh adnm9 adnm8 adnm7 adnm6 adnm5 adnm4 adnm3 adnm2
566 chapter 14 a/d converter user?s manual u16580ee2v0ud00 the correspondence between each analog input pin and the adcrnm register is shown in table 14-1 below. the relationship between the analog voltage input to the analog input pins (anin0 to anin9) and the a/d conversion result (of the a/d conversion result register (adcrnm)) is as follows: or, int( ): function that returns the integer value v in : analog input voltage av ref : av ref pin voltage adcr: value of a/d conversi on result register (adcrnm) figure 14-7 shows the relationship between the analog input voltage and the a/d conversion results. remark: n = 0, 1 m = 0 to 9 table 14-1: assignment of a/d conversion result registers to analog input pins analog input pin assignment of a/ d conversion result registers select 1 buffer mode/ scan mode select 4 buffer mode anin0 adcrn0, adcrn0h adcrn0 to adcrn3, adcrn0h to adcrn3h anin1 adcrn1, adcrn1h anin2 adcrn2, adcrn2h anin3 adcrn3, adcrn3h anin4 adcrn4, adcrn4h adcrn4 to adcrn7, adcrn4h to adcrn7h anin5 adcrn5, adcrn5h anin6 adcrn6, adcrn6h anin7 adcrn7, adcrn7h anin8 adcrn8, adcrn8h adcrn8 to adcrn9, adcrn8h to adcrn9h anin9 adcrn9, adcrn9h adcr int v in av ref ------------------ 1024 0,5 + ?? ?? = adcr 0,5 ? () av ref 1024 ------------------ v in adcr 0,5 + () av ref 1024 ------------------ <
567 chapter 14 a/d converter user?s manual u16580ee2v0ud00 figure 14-7: relationship between analog input voltage and a/d conversion results remark: n = 0, 1 m = 0 to 9 1023 1022 1021 3 2 1 0 input voltage/av ref 1 2048 1 1024 3 2048 2 1024 5 2048 2048 2048 2048 3 1024 1024 1024 2043 1022 2045 1023 2047 1 a/d conversion results (adcrnm)
568 chapter 14 a/d converter user?s manual u16580ee2v0ud00 (6) a/d conversion result register n for dma (addman) the addman register is a 16-bit register holding the result of the latest a/d conversion operation, and is used for dma transfer of adcn results into the internal ram. it has an overrun detection flag indicating an overrun situation of the dma transfer mechanism (n = 0, 1). this register is read-only in 16-bit units. reset input causes an undefined register content. caution: do not read the addman register by cpu during dma transfer activities. if this register is read by cpu, overflow detection cannot be ensured. figure 14-8: a/d conversion result registers n0 to n9, n0h to n9h (adcrn0 to adcrn9, adcrn0h to adcrn9h) remark: n = 0, 1 after reset: undefined r address: addma0 fffff224h, addma1 fffff264h 1514131211109876543210 addman addma n9 addma n8 addma n7 addma n6 addma n5 addma n4 addma n3 addma n2 addma n1 addma n0 00000 odfn addman9 to addman0 a/d conversion result for dma transfer 000h to 3ffh latest a/d conversion result value odfn overrun detection flag 0 no a/d conversion result overrun was detected. 1 at least one a/d conversion result was overrun since the last read of the addman register. ? the odfn flag is used for indicating a dma transfer failure of the a/d conversion results. ? the odfn flag is cleared (0), when the a/d conversion is stopped (adcen bit of the admn0 register is cleared to 0).
569 chapter 14 a/d converter user?s manual u16580ee2v0ud00 14.4 operation 14.4.1 basic operation a/d conversion is executed by the following procedure. <1> the selection of the analog input and specification of the operation mode, trigger mode, etc. should be specified using the admn0, admn1 or admn2 registers note 1 (n = 0, 1). when the adcen bit of the admn0 register is set to 1, a/d conversion starts in the a/d trigger mode. in the timer trigger mode and external trigger mode, the trigger standby state note 2 is set. <2> when a/d conversion is started, the c-array voltage on the analog input side and the c-array volt- age on the reference side are compared by the comparator. <3> when the comparison of the 10 bits ends, the conversion results are stored in the adcrnm register. when a/d conversion has been performed the specified number of times, the a/d conversion end interrupt (intadn) is generated (n = 0, 1), (m = 0 to 9). notes: 1. if the setting of the admn0, admn1 or admn2 registers (n = 0, 1) is changed during a/d conversion, the operation immediately before is stopped, and the result of the conversion is not stored in the adcrnm regist er (m = 0 to 9). the a/d co nversion operation is then initialized, and conversion is executed from the beginning again. 2. during the timer trigger mode and external trigger mode, if the adcen bit of the admn0 register is set to 1, the mode changes to the trigger standby state. the a/d conversion oper- ation is started by the trigger signal (adcsn bit in the admn0 register = 1), and the trigger standby state (adcsn bit = 0) is returned when the a/d conversion operation ends.
570 chapter 14 a/d converter user?s manual u16580ee2v0ud00 14.4.2 operation mode and trigger mode various conversion operations can be specified for the a/d converter by specifying the operation mode and trigger mode. the operation mode and trigger mode are set by the admn0 and admn1registers. the following table shows the relationship between the operation mode and trigger mode. table 14-2: relationship between operation mode and trigger mode (1) trigger mode there are three types of trigger modes that serve as the start timing of a/d conversion processing: a/d trigger mode, timer trigger mode, and external trigger mode. these trigger modes are set by the trgn1 and trgn0 bits of the admn1 register. (a) a/d trigger mode this mode starts the conversion timing of the analog input set to the anin0 to anin9 pins, and by setting the adcen bit of the admn0 register to 1, starts a/d conversion. unless the adcen bit is cleared to 0 after conversion, the next conversion operation is repeated. if data is written to the admn0 to admn2 registers during conversion, conversion is stopped and then executed from the beginning again. (b) timer trigger mode this mode specifies the conversion timing of th e analog input set for the anin0 to anin9 pins using signals from the inverter timer r (tmr0, tmr1). the adtrseln register specifies the analog input co nversion timing by selecting either one of the a/d converter trigger signals (tr0adtrg0, tr 0adtrg1, tr1adtrg0, tr1adtrg1) or one of the top and bottom reversal interrupts (inttr0cd, intr0od, inttr1cd, inttr1od) connected to the 16-bit inverter timer r (tmr0, tmr1). if the adcen bit of the admn0 register is set to 1, the a/d converter waits for an event input (tr0adtrg0, tr0adtrg1, tr1adtrg0, tr1adtrg1, inttr0cd, intr0od, inttr1cd, or inttr1od), and starts conversion when the event occurs (adcsn bit of the admn0 register = 1). when conversion has finished, the converter waits for an event input again (adcsn bit = 0). if data is written to the admn0 to admn2 registers during conversion, conversion is stopped and then executed from the beginning again. trigger mode operation mode register set value admn0 admn1 a/d trigger select 1 buffer xx010000b xx000xxxb 4 buffers xx110000b scan xx000000b timer trigger select 1 buffer xx010000b xx010xxxb 4 buffers xx110000b scan xx000000b external trigger select 1 buffer xx010000b xx100xxxb 4 buffers xx110000b scan xx000000b
571 chapter 14 a/d converter user?s manual u16580ee2v0ud00 (c) external trigger mode this mode specifies the conversion timing of the analog input to the anin0 to anin9 pins using the adtrgn pin. the egan1 and egan0 bits of the admn1 register are used to specify the valid edge to be input to the adtrgn pin. when the adcen bit of the admn0 register is set to 1, the a/d converter waits for an external trigger (adtrgn), and starts conversion when the valid edge of adtrgn is detected (adcsn bit of the admn0 register = 1). when the converter has finished its conversion operation, it waits for an external trigger again (adcsn bit = 0). if the valid edge is detected at the adtrgn pin during conversion, conversion is executed from the beginning again. if data is written to the admn0 to admn2 registers during conversion, conversion is stopped and then executed from the beginning again. (2) operation mode there are two operation modes that set the anin0 to anin9 pins: select mode and scan mode. the select mode has sub-modes that consist of 1-buffer mode and 4-buffer mode. these modes are set by the bsn and msn bits of the admn0 register. (a) select mode in this mode, one analog input specified by the admn2 register is a/d converted. the conversion results are stored in the adcrnm register corresponding to the analog input (aninm). for this mode, the 1-buffer mode and 4-buffer mode are provided for storing the a/d conversion results (m = 0 to 9). ?1-buffer mode in this mode, one analog input specified by the adm2 register is a/d converted. the conversion results are stored in the adcrnm register corresponding to the analog input (aninm) (m = 0 to 9). the aninm and adcrnm register co rrespond one to on e, and an a/d conversion end interrupt (intadn) is generated each time one a/d conversion ends. after conversion has finished, the next conversion operation is repeated, unless the adcen bit of the admn0 register is cleared to 0.
572 chapter 14 a/d converter user?s manual u16580ee2v0ud00 figure 14-9: select mode operation timing: 1-buffer mode (anin1) remark: n = 0, 1 m = 0 to 9 anin1 (input) a/d conversion data 1 (anin1) data 2 (anin1) data 3 (anin1) data 4 (anin1) data 5 (anin1) data 6 (anin1) data 1 data 2 data 3 data 4 data 5 data 6 data 1 (anin1) data 2 (anin1) data 3 (anin1) data 4 (anin1) data 5 (anin1) adcrn1 register intadn interrupt conversion start (admn0 register setting) adcen bit set adcen bit set adcen bit set adcen bit set conversion start (admn0 register setting) anin0 anin1 anin2 anin3 anin4 anin5 anin6 anin7 anin8 anin9 adcrn0 adcrn1 adcrn2 adcrn3 adcrn4 adcrn5 adcrn6 adcrn7 adcrn8 adcrn9 a/d converter (adcn) adcrnm register analog input
573 chapter 14 a/d converter user?s manual u16580ee2v0ud00 ?4-buffer mode in this mode, one analo g input is a/d converte d and the results are st ored in the adcrnm regis- ters. the a/d conversion end interrupt (intadn) is generated when the four a/d conversions end (m = 0 to 3 when one of the analog input channels anin0 to anin3 is specified, m = 4 to 7 when one of analog input channels anin4 to anin7 is specified, and m = 8 to 9 when one of the analog input channels anin8 or anin9 is specified). after conversion has finished, the next conversi on operation is repeated, unless the adcen bit of the adm0 register is cleared to 0. figure 14-10: select mode operation timing: 4-buffer mode (anin2) remark: n = 0, 1 m = 0 to 9 anin2 (input) a/d conversion data 1 (anin2) data 2 (anin2) data 3 (anin2) data 4 (anin2) data 5 (anin2) data 6 (anin2) data 1 data 2 data 3 data 4 data 5 data 6 data 1 (anin2) adcrn0 data 2 (anin2) adcrn1 data 3 (anin2) adcrn2 data 4 (anin2) adcrn3 data 5 (anin2) adcrn0 adcrnm register intadn interrupt conversion start (admn0 register setting) conversion start (admn0 register setting) anin8 anin9 adcrn8 adcrn9 anin0 anin1 anin2 anin3 anin4 anin5 anin6 anin7 adcrn0 adcrn1 adcrn2 adcrn3 adcrn4 adcrn5 adcrn6 adcrn7 adcrnm register analog input a/d converter (adcn)
574 chapter 14 a/d converter user?s manual u16580ee2v0ud00 (b) scan mode in this mode, the analog inputs specified by the admn2 register are selected sequentially from the anin0 pin, and a/d conversion is executed. the a/d conversion results are stored in the adcrnm register corresponding to the analog input (m = 0 to 9). when the conversion of the specified analog input ends, the a/d conversion end interrupt (intadn) is generated. after conversion has finished, the next conversion operation is repeated, unless the adcen bit of the admn0 register is cleared to 0. figure 14-11: scan mode operation timing: 4-channel scan (ani0 to ani3) remark: n = 0, 1 m = 0 to 9 anin3 (input) anin0 (input) anin1 (input) anin2 (input) a/d conversion data 1 (anin0) data 2 (anin1) data 3 (anin2) data 4 (anin3) data 5 (anin0) data 6 (anin1) data 1 data 2 data 3 data 4 data 5 data 6 data 1 (anin0) adcr0 data 2 (anin1) adcr1 data 3 (anin2) adcr2 data 4 (anin3) adcr3 data 5 (anin0) adcr0 adcrnm register intadn interrupt conversion start (admn0 register setting) conversion start (admn0 register setting) a/d converter (adcn) anin8 anin9 adcrn8 adcrn9 anin0 anin1 anin2 anin3 anin4 anin5 anin6 anin7 adcrn0 adcrn1 adcrn2 adcrn3 adcrn4 adcrn5 adcrn6 adcrn7 adcrnm register analog input
575 chapter 14 a/d converter user?s manual u16580ee2v0ud00 14.5 operation in a/d trigger mode when the adcen bit of the admn0 register is set to 1, a/d conversion is started. 14.5.1 select mode operation in this mode, the analog input specified by the admn2 register is a/d converted. the conversion results are stored in the adcrnm register corresponding to the analog input. in the select mode, the 1-buffer mode and 4-buffer mode are supported according to the storing method of the a/d conversion results (n = 0, 1), (m = 0 to 9). (1) 1-buffer mode (a/d trigger select: 1 buffer) in this mode, one analog input is a/d converted once. the conversion results are stored in one adcrn register. the analog input and adcrn register correspond one to one. each time an a/d conversion is executed, an a/d conversion end interrupt (intad) is generated and a/d conversion ends. the next conversion operation is repeated, unless the adce bit of the adm0 register is cleared to 0. table 14-3: correspondence between analog input pins and adcrnm register (a/d trigger select: 1 buffer) this mode is most appropriate for applications in which the results of each first-time a/d conver- sion are read. figure 14-12: example of 1-buffer mode operation (a/d trigger select: 1 buffer) <1> the adcen bit of admn0 register is set to 1 (enable) <2> anin2 is a/d converted <3> the conversion result is stored in adcrn2 register <4> the intad interrupt is generated remark: n = 0, 1 m = 0 to 9 analog input a/d conversion result register aninm adcrnm anin0 anin1 anin2 anin3 anin4 anin5 anin6 anin7 anin8 anin9 adcrn0 adcrn1 adcrn2 adcrn3 adcrn4 adcrn5 adcrn6 adcrn7 adcrn8 adcrn9 a/d converter (adcn) admn2
576 chapter 14 a/d converter user?s manual u16580ee2v0ud00 (2) 4-buffer mode (a/d trigger select: 4 buffers) in this mode, one analog input is a/d converted four times (two times for analog input anin8 or anin9) and the results are stored in the adcrn m register. when the 4th a/d conversion ends, an a/d conversion end interrupt (intadn) is generated and the a/d conversion is stopped. the next conversion operation is repeated, unless the adcen bit of the admn0 register is cleared to 0. table 14-4: correspondence between analog input pins and adcrnm register (a/d trigger select: 4 buffers) this mode is suitable for applic ations in which the average of th e a/d conversion results is calcu- lated. analog input a/d conversion result register ani0 to ani3 adcrn0 (1st time) adcrn1 (2nd time) adcrn2 (3rd time) adcrn3 (4th time) ani4 to ani7 adcrn4 (1st time) adcrn5 (2nd time) adcrn6 (3rd time) adcrn7 (4th time) anin8, anin9 adcrn8 (1st time) adcrn9 (2nd time)
577 chapter 14 a/d converter user?s manual u16580ee2v0ud00 figure 14-13: example of 4-buffer mode operation (a/d trigger select: 4 buffers) <1> the adcen bit of admn0 register is set to 1 (enable) <2> anin3 is a/d converted <3> the conversion result is stored in adcrn0 register <4> anin3 is a/d converted <5> the conversion result is stored in adcrn1 register <6> anin3 is a/d converted <7> the conversion result is stored in adcrn2 register <8> anin3 is a/d converted <9> the conversion result is stored in adcrn3 register <10> the intad interrupt is generated remark: n = 0, 1 m = 0 to 9 adcrn8 adcrn9 adcrn0 adcrn1 adcrn2 adcrn3 adcrn4 adcrn5 adcrn6 adcrn7 anin0 anin1 anin2 anin3 anin4 anin5 anin6 anin7 anin8 anin9 a/d converter (adcn) (4) admn2
578 chapter 14 a/d converter user?s manual u16580ee2v0ud00 14.5.2 scan mode operations in this mode, the analog inputs specified by the admn2 register are selected sequentially from the anin0 pin, and a/d conversion is executed. the a/d conversion results are stored in the adcrnm register corresponding to the analog input (m = 0 to 9). when conversion of all the specified analog input ends, the a/d conversion end interrupt (intadn) is generated, and a/d conversion is stopped. the next conversion operation is repeated, unless the adcen bit of the admn0 register is cleared to 0. table 14-5: correspondence between analog input pins and adcrnm register (a/d trigger scan) note: set by the anisn3 to anisn0 bits of the admn2 register. this mode is most appropriate fo r applications in which multiple analog inputs are constantly monitored. analog input a/d conversion result register anin0 ? ? ? aninm note adcrn0 ? ? ? adcrnm
579 chapter 14 a/d converter user?s manual u16580ee2v0ud00 figure 14-14: example of scan mode operation (a/d trigger scan) <1> the adcen bit of admn0 register is set to 1 (enable) <2> anin0 is a/d converted <3> the conversion result is stored in adcrn0 <4> anin1 is a/d converted <5> the conversion result is stored in adcrn1 <6> anin2 is a/d converted <7> the conversion result is stored in adcrn2 <8> anin3 is a/d converted <9> the conversion result is stored in adcrn3 <10> anin4 is a/d converted <11> the conversion resu lt is stored in adcrn4 <12> anin5 is a/d converted <13> the conversion resu lt is stored in adcrn5 <14> the intad interrupt is generated remark: n = 0, 1 m = 0 to 9 anin0 anin1 anin2 anin3 anin4 anin5 anin6 anin7 anin8 anin9 adcrn8 adcrn9 adcrn0 adcrn1 adcrn2 adcrn3 adcrn4 adcrn5 adcrn6 adcrn7 admn2 a/d converter (adcn)
580 chapter 14 a/d converter user?s manual u16580ee2v0ud00 14.6 operation in timer trigger mode in this mode, the conversion timing of the analog inpu t signal set by the anin0 to anin9 pins is defined by a timer event signal (a/d converter trigger signal, or top and bottom reversal interrupt) of the inverter timers r0 and r1 (tmr0, tmr1). the analog input conversion timing is generated when an a/d converter trigger signal from the timers (tr0adtrg0, tr0adtrg1, tr1adtrg0, tr1adtrg1), or a top or bottom reversal interrupt (inttr0cd, intr0od, inttr1cd, inttr1od) is generated by inverter timer r0 or r1 (tmr0 or tmr1). when the adcen bit of the admn0 register is set to 1, the a/d converter waits for the signal (tr0adtrg0, tr0adtrg1, tr1adtrg0, tr1adt rg1) or interrupt (inttr0cd, intr0od, inttr1cd, inttr1od), and starts conversion when the timer event occurs (adcsn bit of the admn0 register = 1). when conversion is finished, the conv erter waits for a timer event signal again (adcsn bit = 0). if the timer event signal occurs during conversion, the conversion operation is executed from the beginning again. if data is written to the admn0 to admn2 registers during conversion, the conversion operation is stopped and executed from the beginning again. 14.6.1 select mode operation in this mode, an analog input (anin0 to anin9) sp ecified by the admn2 register is a/d converted. the conversion results are stored in the adcrnm register corresponding to the analog input. in the select mode, the 1-buffer mode and 4-buffer mode are provided according to the storing method of the a/d conversion results. (1) 1-buffer mode operation (timer trigger select: 1 buffer) in this mode, one analog input is a/d converted once and the conversion results are stored in one adcrnm register. one analog input is a/d converted once using the trigger of the timer event signals (tr0adtrg0, tr0adtrg1, tr1adtrg0, tr1adtrg1, inttr 0cd, intr0od, inttr1cd, inttr1od) and the results are stored in one adcrnm register. an a/d conversion end interrupt (intadn) is gen- erated for each a/d conversion. unless the adcen bit of the admn0 register is cleared to 0, a/d conversion is repeated each time a timer event signal is generated.
581 chapter 14 a/d converter user?s manual u16580ee2v0ud00 table 14-6: correspondence between analog input pins and adcrnm register (1-buffer mode (timer trigger select: 1 buffer)) remark: n = 0, 1 m = 0 to 9 figure 14-15: example of 1-buffer mode operation (timer trigger select: 1 buffer) (anin1) <1> the adcen bit of admn0 register is set to 1 (enable) <2> the tr0adtrg0 signal is generated <3> anin1 is a/d converted <4> the conversion result is stored in adcrn1 <5> the intadn interrupt is generated remark: n = 0, 1 trigger analog input a/d conversion result register timer event signal (tr0adtrg0, tr0adtrg1, tr1adtrg0, tr1adtrg1, inttr0cd, intr0od, inttr1cd, inttr1od) anin0 adcrn0 anin1 adcrn1 anin2 adcrn2 anin3 adcrn3 anin4 adcrn4 anin5 adcrn5 anin6 adcrn6 anin7 adcrn7 anin8 adcrn8 anin9 adcrn9 a/d converter (adcn) anin0 anin1 anin2 anin3 anin4 anin5 anin6 anin7 anin8 anin9 adcrn0 adcrn1 adcrn2 adcrn3 adcrn4 adcrn5 adcrn6 adcrn7 adcrn8 adcrn9 tr0adtrg0
582 chapter 14 a/d converter user?s manual u16580ee2v0ud00 (2) 4-buffer mode operation (timer trigger select: 4 buffers) in this mode, a/d conversion of one analog input is executed four times, and the results are stored in the adcrnm register. one analog input is a/d converted four times using the timer event signals (tr0adtrg0, tr0adtrg1, tr1adtrg0, tr1adtrg1, inttr0c d, intr0od, inttr1cd, inttr1od) as a trigger, and the results are stored in four adcrnm registers. the a/d conversion end interrupt (intadn) is generated when the four a/d conversions end. after conversion has finished, the next conversi on is repeated when a timer event signal is generated, unless the adcen bit of the admn0 register is cleared to 0. this mode is suitable for app lications in which the average of the a/d conversion results is calculated. table 14-7: correspondence between analog input pins and adcrnm register (4-buffer mode (timer trigger select: 4 buffers)) remark: n = 0, 1 m = 0 to 9 trigger analog input a/d conversion result register timer event signal (tr0adtrg0, tr0adtrg1, tr1adtrg0, tr1adtrg1, inttr0cd, intr0od, inttr1cd, inttr1od) ani0 to ani3 adcrn0 (1st time) adcrn1 (2nd time) adcrn2 (3rd time) adcrn3 (4th time) ani4 to ani7 adcrn4 (1st time) adcrn5 (2nd time) adcrn6 (3rd time) adcrn7 (4th time) anin8, anin9 adcrn8 (1st time) adcrn9 (2nd time)
583 chapter 14 a/d converter user?s manual u16580ee2v0ud00 figure 14-16: example of 4-buffer mode operation (timer trigger select: 4 buffers) (anin3) <1> the adcen bit of admn0 register is set to 1 (enable) <2> thetr0adtrg0 signal is generated <3> anin3 is a/d converted <4> the conversion result is stored in adcr0 <5> thetr0adtrg0 signal is generated <6> anin3 is a/d converted <7> the conversion result is stored in adcr1 <8> thetr0adtrg0 signal is generated <9> anin3 is a/d converted <10> the conversion resu lt is stored in adcr2 <11> thetr0adtrg0 signal is generated <12> anin3 is a/d converted <13> the conversion resu lt is stored in adcr3 <14> the intadn interrupt is generated remark: n = 0, 1 anin0 anin1 anin2 anin3 anin4 anin5 anin6 anin7 anin8 anin9 tr0adtrg0 adcrn0 adcrn1 adcrn2 adcrn3 adcrn4 adcrn5 adcrn6 adcrn7 adcrn8 adcrn9 a/d converter (4) (4)
584 chapter 14 a/d converter user?s manual u16580ee2v0ud00 14.6.2 scan mode operation in this mode, the analog inputs specified by the admn2 register are selected sequentially from the anin0 pin and are a/d converted the specified number of times using the timer event signal as a trigger. the result of conversion is stored in the adcrnm register corresponding to the analog input. when all the specified analog input signals have been converted, an a/d conversion end interrupt (intadn) occurs. after conversion has finished, the a/d converter waits for a trigger unless the adcen bit of the admn0 register is cleared to 0. when a timer event occurs again, the converter starts a/d conversion again, starting from the anin0 input. this mode is most appropriate fo r applications in which multiple analog inputs are constantly monitored. table 14-8: correspondence between analog input pins and adcrnm register (scan mode (timer trigger scan)) remark: n = 0, 1 m = 0 to 9 trigger analog input a/d conversion result register timer event signal (tr0adtrg0, tr0adtrg1, tr1adtrg0, tr1adtrg1, inttr0cd, intr0od, inttr1cd, inttr1od) anin0 adcrn0 anin1 adcrn1 anin2 adcrn2 anin3 adcrn3 anin4 adcrn4 anin5 adcrn5 anin6 adcrn6 anin7 adcrn7 anin8 adcrn8 anin9 adcrn9
585 chapter 14 a/d converter user?s manual u16580ee2v0ud00 figure 14-17: example of scan mode operat ion (timer trigger scan) (anin0 to anin4) <1> the adcen bit of admn0 register is set to 1 (enable) <2> the tr0adtrg0 signal is generated <3> anin0 is a/d converted <4> the conversion result is stored in adcrn0 <5> anin1 is a/d converted <6> the conversion result is stored in adcrn1 <7> anin2 is a/d converted <8> the conversion result is stored in adcrn2 <9> anin3 is a/d converted <10> the conversion resu lt is stored in adcrn3 <11> anin4 is a/d converted <12> the conversion resu lt is stored in adcrn4 <13> the intadn interrupt is generated remark: n = 0, 1 a/d converter (adcn) anin0 anin1 anin2 anin3 anin4 anin5 anin6 anin7 anin8 anin9 adcrn0 adcrn1 adcrn2 adcrn3 adcrn4 adcrn5 adcrn6 adcrn7 adcrn8 adcrn9 tr0adtrg0
586 chapter 14 a/d converter user?s manual u16580ee2v0ud00 14.7 operation in external trigger mode in this mode, the conversion timing of the analog sign als input to the anin0 to anin9 pins is specified by the adtrgn pin. detection of the valid edge at the adtrgn input pin is specified by using the egan1 and egan0 bits of the admn1 register. when the adcen bit of the admn0 register is set to 1, the a/d converter waits for an external trigger (adtrgn), and starts conversion when the valid edge of adtrgn is detected (adcsn bit of the admn0 register = 1). when the converter has ended conversion, it waits for the external trigger again (adcsn bit = 0). if the valid edge is detected at the adtrgn pin dur ing conversion, conversion is executed from the beginning again. if data is written to the admn0 to admn2 registers during conversion, conversion is stopped and executed from the beginning again. 14.7.1 select mode operations in this mode, one analog input (anin0 to anin9) specified by the admn2 register is a/d converted. the conversion results are stored in the adcrnm register corresponding to the analog input. in the select mode, there are two select modes: 1-buffer mode and 4-buffer mode, according to the storing method of the conversion results. (1) 1-buffer mode (external trigger select: 1 buffer) in this mode, one analog input is a/d converted using the adtrgn signal as a trigger. the conversion results are stored in one adcrnm register. the analog input and the a/d conversion results register correspond one to one. the a/d conversion end interrupt (intadn) is generated for each a/d conversion, and a/d conversion is stopped. table 14-9: correspondence between analog input pins and adcrnm register (external trigger select: 1 buffer) while the adcen bit of the admn0 register is 1, a/d conversion is repeated every time a trigger is input from the adtrgn pin. this mode is most appropriate for applications in which the results are read after each a/d conver- sion. trigger analog input a/d conversion result register adtrgn signal aninm adcrnm
587 chapter 14 a/d converter user?s manual u16580ee2v0ud00 figure 14-18: example of 1-buffer mode operation (external trigger select: 1 buffer) (anin1) <1> the adcen bit of admn0 is set to 1 (enable) <2> the external trigger is generated <3> anin1 is a/d converted <4> the conversion result is stored in adcrn1 <5> the intadn interrupt is generated remark: n = 0, 1 m = 0 to 9 anin0 anin1 anin2 anin3 anin4 anin5 anin6 anin7 anin8 anin9 adcrn0 adcrn1 adcrn2 adcrn3 adcrn4 adcrn5 adcrn6 adcrn8 adcrn9 adcrn7 a/d converter (adcn) adtrgn
588 chapter 14 a/d converter user?s manual u16580ee2v0ud00 (2) 4-buffer mode (external trigger select: 4 buffers) in this mode, one analog input is a/d converted four times using the adtrgn signal as a trigger and the results are stored in the adcrnm register. the a/d conversion end interrupt (intadn) is generated and a/d conversion is stopped after the 4th a/d conversion. table 14-10: correspondence between analog input pins and adcrnm register (external trigger select: 4 buffers)) while the adcen bit of the admn0 register is 1, a/d conversion is repeated every time a trigger is input from the adtrgn pin. this mode is suitable for applic ations in which the average of th e a/d conversion results is calcu- lated. trigger analog input a/d conversion result register adtrgn signal ani0 to ani3 adcrn0 (1st time) adcrn1 (2nd time) adcrn2 (3rd time) adcrn3 (4th time) ani4 to ani7 adcrn4 (1st time) adcrn5 (2nd time) adcrn6 (3rd time) adcrn7 (4th time) anin8, anin9 adcrn8 (1st time) adcrn9 (2nd time)
589 chapter 14 a/d converter user?s manual u16580ee2v0ud00 figure 14-19: example of 4-buffer mode operation (external trigger select: 4 buffers) (anin2) <1> the adcen bit of admn0 register is set to 1 (enable) <2> the external trigger is generated <3> anin2 is a/d converted <4> the conversion result is stored in adcrn0 <5> the external trigger is generated <6> anin2 is a/d converted <7> the conversion result is stored in adcrn1 <8> the external trigger is generated <9> anin2 is a/d converted <10> the conversion resu lt is stored in adcrn2 <11> the external trigger is generated <12> anin2 is a/d converted <13> the conversion resu lt is stored in adcrn3 <14> the intad interrupt is generated remark: n = 0, 1 m = 0 to 9 anin0 anin1 anin2 anin3 anin4 anin5 anin6 anin7 anin8 anin9 adcrn0 adcrn1 adcrn2 adcrn3 adcrn4 adcrn5 adcrn6 adcrn8 adcrn9 adcrn7 adtrgn a/d converter (adcn) (4) (4)
590 chapter 14 a/d converter user?s manual u16580ee2v0ud00 14.7.2 scan mode operation in this mode, the analog inputs specified by the admn2 register are selected sequentially from the anin0 pin using the adtrgn signal as a trigger, and a/d converted. the a/d conversion results are stored in the adcrnm register corresponding to the analog input aninm (n = 0, 1)(m = 0 to 9). when conversion of all the specified analog inputs has ended, the a/d conversion end interrupt (intadn) is generated.n unless the adce bit of the admn0 register is cleared to 0 after end of conversion, the a/d converter waits for a trigger. the converter starts a/d conversion from the anin0 input when a trigger is input to the adtrgn pin again. table 14-11: correspondence between analog input pins and adcrnm register (external trigger scan) when a trigger is input to the adtrgn pin while the adcen bit of the admn0 register is 1, a/d conversion is started again. this is most appropriate for app lications in which multiple analog inputs are constantly monitored. remark: n = 0, 1 m = 0 to 9 trigger analog input a/d conversion result register adtrgn signal anin0 adcrn0 anin1 adcrn1 anin2 adcrn2 anin3 adcrn3 anin4 adcrn4 anin5 adcrn5 anin6 adcrn6 anin7 adcrn7 anin8 adcrn8 anin9 adcrn9
591 chapter 14 a/d converter user?s manual u16580ee2v0ud00 figure 14-20: example of scan mode operatio n (external trigger scan) (anin0 to anin3) <1> the adcen bit of admn0 register is set to 1 (enable) <2> the external trigger is generated <3> anin0 is a/d converted <4> the conversion result is stored in adcrn0 <5> anin1 is a/d converted <6> the conversion result is stored in adcrn1 <7> anin2 is a/d converted <8> the conversion result is stored in adcrn2 <9> anin3 is a/d converted <10> the conversion resu lt is stored in adcrn3 <11> the intadn interrupt is generated remark: n = 0, 1 anin0 anin1 anin2 anin3 anin4 anin5 anin6 anin7 anin8 anin9 adcrn0 adcrn1 adcrn2 adcrn3 adcrn4 adcrn5 adcrn6 adcrn8 adcrn9 adcrn7 adtrgn a/d converter (adcn)
592 chapter 14 a/d converter user?s manual u16580ee2v0ud00 14.8 precautions (1) stopping conversion operation when the adcen bit of the admn0 register is cleared to 0 during a conversion operation, the conversion operation stops and the conversion re sults are not stored in the adcrnm register (n = 0, 1), (m = 0 to 9). (2) external/timer trigger interval set the interval (input time interval) of the trigger in the external or timer trigger mode longer than the conversion time specified by the frn3 to frn0 bits of the admn1 register. when 0 < interval conversion operation time when the following external trigger or timer trigger is input during a conversion operation, the conversion operation is aborted and the conversion starts according to the last external trigger input or timer trigger input. when conversion operations are aborted, the conversion results are not stored in the adcrnm register (n = 0, 1) (m = 0 to 9). however, the number of times the trigger has been input is counted. when an interrupt occurs, the va lues that have been conver ted are stored in the adcrnm register. (3) operation in halt mode a/d conversion continues in the halt mode. when this mode is released by nmi input or unmasked maskable interrupt input (see section 8.3.2 (2) ?releasing halt mode? on page 246 ), the admn0, admn1, and admn2 register s as well as the adcrnm register hold the value (n = 0, 1) (m = 0 to 9). (4) input range of anin0 to anin9 use the input voltage at anin0 to anin9 within the specified range. if a voltage outside the range of av ref is input to any of these pins (even with in the absolute maximum rating range), the converted value of the channel is undefined. in addition, the converted value of the other channels may also be affected. (5) conflicts (a) conflict between writing a/d conversion result registers (adcrnm, adcrnmh) at end of conversion and reading adcrnm and adcrnmh registers by instruction reading the adcrnm and adcrnmh registers takes precedence. after these registers have been read, the new conversion result is wr itten to the adcrnm and adcrnmh registers. (b) conflict between writing adcrnm and adcrn mh at end of conversion and input of external trigger signal the external trigger signal is not accepted during a/d conversion. therefore, it is not accepted while adcrnm and adcrnmh are being written. (c) conflict between writing adcrnm and a dcrnmh at end of conversion and writing admn1 or admn2 register if admn1 or admn2 register is written immediately after adcrnm and adcrnmh have been written on completion of a/d conversion, the conversion result is written to the adcrnm and adcrnmh registers, but the a/d conversion end interrupt (intadn) may not occur depending on the timing.
593 user?s manual u16580ee2v0ud00 chapter 15 asynchronous seri al interface c (uartc) 15.1 features ? transfer speed: 16 bps to 2000 kbps ? full-duplex communication: internal uartc receive data register n (ucnrx) internal uartc transmit data register n (ucntx) ? 2-pin configuration: txdcn: transmit data output pin rxdcn: receive data input pin ? receive error output function - parity error - framing error - overrun error ? interrupt sources: 3 - receive error interrupt (intucnre) - reception complete interrupt (intucnr) - transmission enable interrupt (intucnt) ? character length: 7, 8 bits ? parity function: odd, even, 0, none ? transmission stop bit: 1, 2 bits ? on-chip dedicated baud rate generator ? msb/lsb-first transfer selectable ? transmit/receive data level inversion possible ? 13 to 20 bits selectable for the sbf (sync break field) in the lin (local interconnect network) communication format ? recognition of 11 bits or more possible for sbf reception in lin communication format ? sbf reception flag provided ? extension bit operation possible (uses parity bit as 9th data bit) ? transfer and reception status flags remark: n = 0, 1
594 chapter 15 asynchronous serial interface c (uartc) user?s manual u16580ee2v0ud00 15.2 configuration (1) uartcn control register 0 (ucnctl0) the ucnctl0 register is an 8-bit register used to specify the asynchronous serial interface operation. (2) uartcn control register 1 (ucnctl1) the ucnctl1 register is an 8-bit register used to select the input clock for the asynchronous serial interface. (3) uartcn control register 2 (ucnctl2) the ucnctl2 register is an 8-bit register used to control the baud rate for the asynchronous serial interface. (4) uartcn option control register 0 (ucnopt0) the ucnopt0 register is an 8-bit register used to control serial transfer for the asynchronous serial interface. (5) uartcn option control register 1 (ucnopt1) the ucnopt1 register is an 8-bit register used to control the extension bit operation. (6) uartcn status register (ucnstr) the ucnstr register consists of flags indicating the error contents when a reception error occurs. each one of the reception error flags is set (to 1) upon occurrence of a reception error and is reset (to 0) by reading the ucnstr register. (7) uartcn status register 1 (ucnstr1) the ucnstr1 register indicates the operating status during a reception. (8) uartcn receive shift register this is a shift register used to convert the serial data input to the rxdcn pin into parallel data. upon reception of 1 byte of data and detection of the stop bit, the receive data is transferred to the ucnrx register. this register cannot be manipulated directly. (9) uartcn receive data register (ucnrx) the ucnrx register is an 8-bit register that holds receive data. when 7 characters are received, 0 is stored in the highest bit (when lsb first received). in the reception enabled status, receive data is transferred from the uartcn receive shift register to the ucnrx register in synchronization with the completion of shift-in processing of 1 frame. transfer to the ucnrx register also causes reception complete interrupt (intucnr) to be output. (10) uartcn transmit shift register the transmit shift register is a shift register used to convert the parallel data transferred from the ucntx register into serial data. when 1 byte of data is transferred from the ucntx register, the shift register data is output from the txdcn pin. this register cannot be manipulated directly.
595 chapter 15 asynchronous serial interface c (uartc) user?s manual u16580ee2v0ud00 (11) uartcn transmit data register (ucntx) the ucntx register is an 8-bit transmit data buffer. transmission starts when transmit data is written to the ucntx register. when data can be written to the ucntx register (when data of one frame is transferred from the ucntx register to the uartcn transmit shift register), the transmission enable interr upt (inucnt) is generated. figure 15-1: block diagram of asynchronous serial interface n remarks: 1. n = 0, 1 2. f xx : internal system clock internal bus internal bus ucnotp0 ucnotp1 ucnctl0 ucnstr ucnstr1 ucnctl1 ucnctl2 receive shift register ucnrx filter selector ucntx transmit shift register transmission controller reception controller selector baud rate generator baud rate generator intucnre intucnr intucnt txdcn rxdcn f/2 xx f/4 xx f/8 xx f /32 xx f /128 xx f /64 xx f /256 xx f /1024 xx f /512 xx f /2048 xx f /8192 xx f /16 xx reception unit transmission unit clock selector
596 chapter 15 asynchronous serial interface c (uartc) user?s manual u16580ee2v0ud00 15.3 control registers (1) uartcn control register 0 (ucnctl0) the ucnctl0 register is an 8-bit register that controls the uartcn serial transfer operation. this register can be read or written in 8-bit or 1-bit units. reset input sets this register to 10h. caution: be sure to set the ucnpwr bit = 1 and the ucnrxe bit = 1 while the rxdcn pin is high level (when ucnrdl bit of ucnop0 register = 0). if the ucnpwr bit = 1 and the ucnrxe bit = 1 are set while the rxdcn pin is low level, reception will inadvertently start. figure 15-2: uartcn control register 0 (ucnctl0) (1/2) after reset: 10h r/w address: uc0ctl0 fffffa00h, uc1ctl0 fffffa20h 76543210 ucnctl0 ucnpwr ucntxe ucnrxe ucndir ucnps1 ucnps0 ucncl ucnsl (n = 0, 1) ucnpwr uartcn operation control 0 stops clock operation (uartcn reset asynchronously) 1 enables operating clock operation operating clock control and uartcn asynchronous reset are performed with the ucnpwr bit. the txdcn pin output is fixed to high level by setting the ucnpwr bit to 0. ucntxe transmission operation enable 0 stops transmission operation 1 enables transmission operation ? the txdcn pin output is fixed to high level by setting the ucnpwr bit to 0. since the ucntxe bit is initialized by the operating clock, to initialize the transmission unit, set ucntxe from 0 to 1, and 2 clocks later, the transmission enabled status is entered. ? when ucnpwr bit = 0, the value writt en to the ucntxe bit is ignored. ucnrxe reception operation enable 0 stops reception operation 1 enables reception operation ? the receive operation is stopped by setting th e ucnrxe bit to 0. therefore, even if the prescribed data is transferred, no reception completion interrupt is output and the uartcn reception data regi ster (ucnrx) is not updated. since the ucnrxe bit is synchronized using the operating clock, to initialize the reception unit, set ucnrxe from 0 to 1, and 2 clocks later, the reception enabled status is entered. ? when ucnpwr bit = 0, the value written to the ucnrxe bit is ignored.
597 chapter 15 asynchronous serial interface c (uartc) user?s manual u16580ee2v0ud00 figure 15-2: uartcn control register 0 (ucnctl0) (2/2) remark: for details of parity, see 15.5.9 ?parity types and operations? on page 621 . ucndir transfer direction selection 0 msb-first transfer 1 lsb-first transfer this bit can be rewritten only when ucnpwr bit = 0 or ucntxe bit = ucnrxe bit = 0. ucnps1 ucnps0 parity selection during transmission during reception 0 0 no parity output reception with no parity 0 1 0 parity output reception with 0 parity 1 0 odd parity output odd parity check 1 1 even parity output even parity check ? these bits can be rewritten only when ucnpwr bit = 0 or ucntxe bit = ucnrxe bit =0. ? if ?reception with 0 parity? is selected duri ng reception, a parity check is not performed. therefore, since the ucnpe bit of the ucnsta0 register is not set, no error interrupt is output. ? when transmission and reception are performed in the lin format, set the ucnps1 and ucnps0 bits to 00b. ucncl data character length specification 07 bits 18 bits this bit can be rewritten only when ucnpwr bit = 0 or ucntxe bit = ucnrxe bit = 0. ucnsl stop bit length specification 01 bit 12 bits this bit can be rewritten only when ucnpwr bit = 0 or ucntxe bit = ucnrxe bit = 0.
598 chapter 15 asynchronous serial interface c (uartc) user?s manual u16580ee2v0ud00 (2) uartcn control register 1 (ucnctl1) the ucnctl1 register is an 8-bit register that selects the uartcn base clock (f xclk ) . this register can be read or written in 8-bit units. reset input clears this register to 00h. figure 15-3: uartcn control register 1 (ucnctl1) remark: f xx : internal system clock after reset: 00h r/w address: uc0ctl1 fffffa01h, uc1ctl1 fffffa21h 76543210 ucnctl1 0 0 0 0 ucncks3 ucncks2 ucncks1 ucncks0 (n = 0, 1) ucncks3 ucncks2 ucncks1 ucncks0 base clock (f xclk ) selection 0000f xx /2 0001f xx /4 0010f xx /8 0011f xx /16 0100f xx /32 0101f xx /64 0110f xx /128 0111f xx /256 1-00f xx /512 1-01f xx /1024 1-10f xx /2048 1-11f xx /8192
599 chapter 15 asynchronous serial interface c (uartc) user?s manual u16580ee2v0ud00 (3) uartcn control register 2 (ucnctl2) the ucnctl2 register is an 8-bit register that specifies the divisor to control the baud rate (serial transfer speed) clock of uartcn. this register can be read or written in 8-bit units. reset input sets this register to ffh. figure 15-4: uartcn contro l register 2 (ucnctl2) remark: f xclk : clock frequency selected by the ucncks3 to ucncks0 bits of the ucnctl1 register after reset: ffh r/w address: uc0ctl2 fffffa02h, uc1ctl2 fffffa22h 76543210 ucnctl2 ucnbrs7 ucnbrs6 ucnbrs5 ucnbrs4 ucnbrs3 ucnbrs2 ucnbrs1 ucnbrs0 (n = 0, 1) ucn brs7 ucn brs6 ucn brs5 ucn brs4 ucn brs3 ucn brs2 ucn brs1 ucn brs0 default (k) serial clock 000000 - - -setting prohibited 00000100 4f xclk /4 00000101 5f xclk /5 00000110 6f xclk /6 :::::::: :: 11111100252f xclk /252 11111101253f xclk /253 11111110254f xclk /254 11111111255f xclk /255
600 chapter 15 asynchronous serial interface c (uartc) user?s manual u16580ee2v0ud00 (4) uartcn option control register 0 (ucnopt0) the ucnopt0 register is an 8-bit register that controls the serial transfer operation of the uartcn register. this register can be read or written in 8-bit or 1-bit units. reset input sets this register to 14h. figure 15-5: uartcn option control register 0 (ucnopt0) (1/2) after reset: 14h r/w address: uc0opt0 fffffa03h, uc1opt0 fffffa23h 76543210 ucnopt0 ucnsrf ucnsrt ucnstt ucnsls2 ucnsls1 ucnsls0 ucntdl ucnrdl (n = 0, 1) ucnsrf sbf reception flag 0 when ucnpwr of ucnctl0 register = 0 and ucnrxe of ucnctl0 register = 0 are set. also upon normal end of sbf reception. 1 during sbf reception ? sbf (sync brake field) reception is judged during lin communication. ? the ucnsrf bit is held high when a sbf reception error occurs, and then sbf reception is started again. ucnsrt sbf reception trigger 0? 1 sbf reception trigger ? this is the sbf reception trigger bit during lin communication, and when read, ?0? is always read. for sbf reception, set the ucnsrt bit (to 1) to enable reception. ? set the ucnsrt bit after setting the ucnpw r bit of the ucnctl0 register to 1 and the ucnrxe bit of the uc nctl0 register to 1. ucnstt sbf transmission trigger 0? 1 sbf transmission trigger ? this is the sbf transmission trigger bit during lin communication, and when read, ?0? is always read. ? set the ucnsrt bit after setting the ucnpw r bit of the ucnctl0 register to 1 and the ucnrxe bit of the uc nctl0 register to 1.
601 chapter 15 asynchronous serial interface c (uartc) user?s manual u16580ee2v0ud00 figure 15-5: uartcn option control register 0 (ucnopt0) (2/2) ucnsls2 ucnsls1 ucnsls0 sbf length selection 1 0 1 13-bit output (reset value) 1 0 0 14-bit output 1 1 1 15-bit output 0 1 0 16-bit output 0 0 1 17-bit output 0 0 0 18-bit output 0 1 1 19-bit output 1 1 0 20-bit output this register can be set when the ucnpwr bi t of the ucnctl0 register is 0 or when the ucnrxe bit of the ucnctl0 register is 0. ucntdl transmit data level 0 normal output of transfer data 1 inverted output of transfer data ? the value of the txdcn pin can be inverted using the ucntdl bit. ? this bit can be set when the ucnpwr bit of the ucnctl0 regist er is 0 or when the ucntxe bit of the ucnctl0 register is 0. ucnrdl receive data level 0 normal input of transfer data 1 inverted input of transfer data ? the value of the rxdcn pin can be inverted using the ucnrdl bit. ? this bit can be set when the ucnpwr bi t of the ucnctl0 register is 0 or the ucnrxe bit of the ucnctl0 register is 0.
602 chapter 15 asynchronous serial interface c (uartc) user?s manual u16580ee2v0ud00 (5) uartcn option control register 1 (ucnopt1) the ucnopt1 register is an 8-bit register that controls the extension bit operation of the uartcn. the register can be read or written in 8-bit or 1-bit units. reset input clears this register to 00h. figure 15-6: uartcn option control register 1 (ucnopt1) after reset: 00h r/w address: uc0opt1 fffffa0ah, uc1opt1 fffffa2ah 76543210 ucnopt10000000ucnebe (n = 0, 1) ucnebe extension bit operation enable 0 extension bit operation disabled. transfer data length set by ucncl bit of the ucnctl0 register. 1 extension bit operation enabled. ? during extension bit operation a 9-th data bit is sent or received instead of the parity bit. ? extension bit operation is only effective wh en the parity selection is set to no parity (ucnps1, ucnps0 bits = 00b), and the character length is set to 8 bits (ucncl bit = 1). in all other cases the se tting of ucnebe bit is ignored.
603 chapter 15 asynchronous serial interface c (uartc) user?s manual u16580ee2v0ud00 table 15-1: relation between uartcn register settings and data format note: insertion of extension bit register bit settings data format ucnebe ucnps1 ucnps0 ucncl ucnsl d0 - d6 d7 d8 d9 d10 00000datastop 0 1 data stop stop 1 0 data data stop 1 1 data data stop stop other than 00b 0 0 data parity stop 0 1 data parity stop stop 1 0 data data parity stop 1 1 data data parity stop stop 10000datastop 0 1 data stop stop 1 0 data data data note stop 11 data data data note stop stop other than 00b 0 0 data parity stop 0 1 data parity stop stop 1 0 data data parity stop 1 1 data data parity stop stop
604 chapter 15 asynchronous serial interface c (uartc) user?s manual u16580ee2v0ud00 (6) uartcn status register (ucnstr) the ucnstr register is an 8-bit register that displays the uartcn transfer status and reception error contents. this register can be read or written in 8-bit or 1-bit units, but the ucntsf bit is a read-only bit, while the ucnpe, ucnfe, and ucnove bits can both be read and written. however, these bits can only be cleared by writing 0 and they cannot be set by writing 1. (if 1 is written to them, the hold status is entered.) the initialization condit ions are shown below. figure 15-7: uartcn status register (ucnstr) (1/2) register/bit initialization conditions ucnstr register reset input ucnpwr bit of ucnctl0 register = 0 ucntsf bit ucntxe bit of ucnctl0 register = 0 ucnpe, ucnfe, ucnove bits 0 write ucnrxe bit of ucnctl0 register = 0 after reset: 00h r/w addr ess: uc0str fffffa04h, uc1str fffffa24h 76543210 ucnstr ucntsf 0 0 0 0 ucnpe ucnfe ucnove (n = 0, 1) ucntsf transfer status flag 0 ? when ucnpwr bit of ucnctl0 register = 0 or ucntxe bit of ucnctl0 register = 0 has been set. ? when, following transfer completion, there was no next data transfer from ucntx 1 write to ucntxb bit the ucntsf bit is always 1 when performing c ontinuous transmission. when initializing the transmission unit, check that the ucntsf bit = 0 before performing initialization. the transmit data is not guaranteed when initialization is performed while ucntsf bit = 1. ucnpe parity error flag 0 ? when ucnpwr bit of ucnctl0 register = 0 or ucnrxe bit of ucnctl0 register = 0 has been set. ? when 0 has been written 1 ? when parity of data and parity bit do not match during reception. ? the operation of the ucnpe bit is controlled by the settings of the ucnps1 and ucnps0 bits of the ucnctl0 register. ? the ucnpe bit can be read and written, but it can only be cleared by writing 0 to it, and it cannot be set by writing 1 to it. when 1 is written to this bit, the hold status is entered.
605 chapter 15 asynchronous serial interface c (uartc) user?s manual u16580ee2v0ud00 figure 15-7: uartcn status register (ucnstr) (2/2) ucnfe framing error flag 0 ? when ucnpwr bit of ucnctl0 regi ster = 0 or ucnrxe bit of ucnctl0 register = 0 has been set ? when 0 has been written 1 when no stop bit is detected during reception ? only the first bit of the receive data stop bits is checked, regardless of the value of the ucnsl bit of the ucnctl0 register. ? the ucnfe bit can be both read and written, but it can only be cleared by writing 0 to it, and it cannot be set by writing 1 to it. wh en 1 is written to this bit, the hold status is entered. ucnove overrun error flag 0 ? when ucnpwr bit of ucnctl0 regi ster = 0 or ucnrxe bit of ucnctl0 register = 0 has been set. ? when 0 has been written 1 when receive data has been set to the ucnrxb register and the next receive operation is completed before that receive data has been read ? when an overrun error occurs, the data is discarded without the next receive data being written to the receive buffer. ? the ucnove bit can be both read and written, but it can only be cleared by writing 0 to it. when 1 is written to this bit, the hold status is entered.
606 chapter 15 asynchronous serial interface c (uartc) user?s manual u16580ee2v0ud00 (7) uartcn status register 1 (ucnstr1) the ucnstr1 register is an 8-bit register that displays the uartcn reception status. the register is read only, and be read in 8-bit or 1-bit units. reset input clears this register to 00h. figure 15-8: uartcn status register 1 (ucnstr1) after reset: 00h r address: uc0str1 fffffa0bh, uc1str1 fffffa2bh 76543210 ucnstr10000000ucnrsf (n = 0, 1) ucnrsf receive status flag 0 ? when ucnpwr bit of ucnctl0 register = 0 or ucnrxe bit of ucnctl0 register = 0 has been set. ? when the stop bit has been detected. 1 during reception, when the start bit has been detected. the ucnrsf flag is set (1) by the start bit dete ction, and it is cleared (0) by detection of the first stop bit condition. in case of a two st op bit setting (ucnsl bi t of ucnctl0 register = 1), the ucnrsf flag is cleared during the first stop bit timing, simultaneously with the reception complete inte rrupt timing (intucnr)
607 chapter 15 asynchronous serial interface c (uartc) user?s manual u16580ee2v0ud00 (8) uartcn receive data re gister (ucnrx, ucnrxl) the ucnrx register is a 16-bit buffer register that stores parallel data converted by receive shift register. it is overlayed by an 8-bit register ucnrxl on the lower 8 bits, which stores the lower byte of the received data. the data stored in the receive shift register is transferred to the ucnrx register upon completion of reception of one data frame. when extension bit operation is enabled (ucnebe bi t of ucnopt1 register = 1) the 9th data bit is received in bit 8 of the ucnrx register. when the extension bi t operation is disabled (ucnebe bit = 0) the data bits are received in the lower byte of the ucnrx register. the lower byte can be read also by 8-bit access of the ucnrxl register. during lsb-first reception when the data length has been specified as 7 bits and th extension bit operation is disabled, the receive data is transferred to bits 6 to 0 of the uxnrxl register and the msb always becomes 0. during msb-first reception, the receive data is transferred to bits 7 to 1 of the ucnrxl register and the lsb always becomes 0. when an overrun error (ucnove bit = 1) occurs, the receive data at this time is not transferred to the ucnrx and uxnrxl register respectively. the ucnrx register is read-only, in 16-bit units. the ucnrxl register is read-only, in 8-bit units. in addition to reset input, the ucnrx register can be set to 1ffh, and the ucnrxl register can be set to ffh respectively, by clearing the ucnpwr bit of the ucnctl0 register to 0. figure 15-9: uartcn receive data register (ucnrx, ucnrxl) after reset: 1ffh r address: uc0rx fffffa06h, uc1rx fffffa26h 1514131211109876543210 ucnrx 0000000 (n = 0, 1) ucnrxl after reset: ffh r address: uc0rxl fffffa06h, uc1rxl fffffa26h 76543210 ucnrxl (n = 0, 1)
608 chapter 15 asynchronous serial interface c (uartc) user?s manual u16580ee2v0ud00 (9) uartcn transmit data register (ucntx, ucntxl) the ucntx register is a 16-bit buffer register used to set transmit data. it is overlayed by an 8-bit register ucntxl on the lower 8 bits. the ucntxl register is used for setting the transmit data when 7-bit or 8-bit data character length is specified (ucnebe bit = 0). the ucntx register can be read or written in 16-bit units. the ucntxl register can be read or written in 8-bit units. reset input sets the ucntx register to 1ffh, and the ucntxl register to ffh. figure 15-10: uartcn transmit data register (ucntx, ucntxl) after reset: 1ffh r/w address: uc0tx fffffa08h, uc1tx fffffa28h 1514131211109876543210 ucntx 0000000 (n = 0, 1) ucntxl after reset: ffh r/w address: uc0txl fffffa08h, uc1txl fffffa28h 76543210 ucntxl (n = 0, 1)
609 chapter 15 asynchronous serial interface c (uartc) user?s manual u16580ee2v0ud00 15.4 interrupt requests the following three interrupt requests are generated from uartcn. ? receive error interrupt (intucnre) ? reception complete interrupt (intucnr) ? transmission enable interrupt (intucnt) the default priority for these three interrupt requests is highest for the receive error interrupt, followed by the reception complete interrupt, and the transmission enable interrupt. (1) receive error interrupt (intucnre) a receive error interrupt is generated when one or more of the three types of receive errors (parity error, framing error, or overrun error) occur. (refer to 15.3 (6) uartcn status register (ucnstr) ) (2) reception complete interrupt (intucnr) a reception complete interrupt is output when data is shifted into the uartcn receive shift register and transferred to the ucnrx register in the reception enabled status. a reception complete interrupt will not be gene rated when a receptio n error has occurred. no reception complete interrupt is generated in the reception disabled status. (3) transmission enable interrupt (intucnt) a transmission enable interrupt is generated when transmit data is transferred from the ucntx register to the uartcn transmit shift register in the transmission enabled status. table 15-2: default priorities of uartcn interrupts interrupt priority receive error (intucnre) high reception complete (intucnr) transmission enable (intucnt) low
610 chapter 15 asynchronous serial interface c (uartc) user?s manual u16580ee2v0ud00 15.5 operation 15.5.1 data format full-duplex serial data reception and transmission is performed. as shown in figure 15-11, one data frame of transmit/r eceive data consists of a start bit, character bits, parity bit, and stop bit(s). specification of the character bit length within 1 data fr ame, parity selection, specification of the stop bit length, and specification of msb/lsb-first transfer are performed using the ucnctl0 register. uartcn features additionally the extension bit operation for a ninth transfer data bit, which can be specified in the ucnopt1 register. moreover, control of uart output/inverted output for the txdcn bit is performed using the ucntdl bit of the ucnopt0 register. ? start bit 1 bit ? character bits 7 bits/8 bits/9 bits ? parity bit even parity/odd parity/0 parity/no parity note ? stop bit 1 bit/2 bits note: extension bit operation presumes no parity setting. figure 15-11: uartc transmit/receive data format (1/2) (a) 8-bit data length, lsb first, even parity, 1 stop bit, transfer data: 55h (b) 8-bit data length, msb first, even parity, 1 stop bit, transfer data: 55h (c) 8-bit data length, msb first, even parity, 1 stop bit, transfer data: 55h, txdcn inversion 1 data frame start bit d0 d1 d2 d3 d4 d5 d6 d7 parity bit stop bit 1 data frame start bit d7 d6 d5 d4 d3 d2 d1 d0 parity bit stop bit 1 data frame start bit d7 d6 d5 d4 d3 d2 d1 d0 parity bit stop bit
611 chapter 15 asynchronous serial interface c (uartc) user?s manual u16580ee2v0ud00 figure 15-11: uartc transmit/receive data format (2/2) (d) 7-bit data length, lsb first, odd parity, 2 stop bits, transfer data: 36h (e) 8-bit data length, lsb first, no parity, 1 stop bit, transfer data: 87h (f) 9-bit data length, lsb first, no parity, 1 stop bit, transfer data: 155h 1 data frame start bit d0 d1 d2 d3 d4 d5 d6 parity bit stop bit stop bit 1 data frame start bit d0 d1 d2 d3 d4 d5 d6 d7 stop bit 1 data frame start bit d0 d1 d2 d3 d4 d5 d6 d7 d8 stop bit
612 chapter 15 asynchronous serial interface c (uartc) user?s manual u16580ee2v0ud00 15.5.2 sbf transmission/reception format the uartc has a sbf (sync break field) transmission /reception control function to enable use of the lin (local interconnect network) function. figure 15-12: lin transmission manipulation outline notes: 1. the interval between each field is controlled by software. 2. sbf output is performed by hardware. the output width is the bit length set by bits ucnsbl2 to ucnsbl0 of the ucnopt0 register. if even finer output width adjustments are required, such adjustments can be performed using bits ucnbrs7 to ucnbrs0 of the ucnctln register. 3. 80h transfer in the 8-bit mode is substituted for the wake-up signal frame. 4. a transmission enable interrupt (intucnt) is ou tput at the start of each transmission. the intucnt signal is also output at the start of each sbf transmission. sleep bus wake-up signal frame synch break field synch field ident field data field data field check sum field intucnr interrupt txdcn (output) note 3 8 bits note 1 note 2 13 bits sbf transmission note 4 55h transmission data transmission data transmission data transmission data transmission
613 chapter 15 asynchronous serial interface c (uartc) user?s manual u16580ee2v0ud00 figure 15-13: lin reception manipulation outline notes: 1. the wakeup signal is sent by the pin edge detector, uartc is enabled, and the sbf reception mode is set. 2. the receive operation is performed until detection of the stop bit. upon detection of sbf reception of 11 or more bits, normal sbf reception end is judged, and an interrupt signal is output. upon detection of sbf reception of less than 11 bits, a sbf reception error is judged, no interrupt signal is output, and the mode returns to the sbf reception mode. 3. if sbf reception ends normally, an interrupt signal is output. the timer is enabled by a sbf reception complete interrupt. moreover, error detection for the ucnove, ucnpe, and ucnfe bits of the ucnstr register is suppressed and uart communication error detection processing and uartcn receive shift register and data transfer of the ucnrx register are not performed. the uartcn receive shift register holds the initial value, ffh. 4. the rxdcn pin is connected to ti (capture input) of the timer, the transfer rate is calculated, and the baud rate error is calculated. the value of the ucnctl2 register obtained by compensating the baud rate error after dropping uartc enable is set again, causing the status to become the reception status. 5. check-sum field distinctions are made by so ftware. the uartc is initialized following csf reception, and the processing for setting the sbf reception mode again is performed by software. reception interrupt (intucnr) edge detection capture timer disable disable enable txdcn (output) enable note 2 13 bits sbf reception note 3 note 4 note 1 sf reception id reception data transmission data transmission note 5 data transmission sleep bus wake-up signal frame synch break field synch field ident field data field data field check sum field
614 chapter 15 asynchronous serial interface c (uartc) user?s manual u16580ee2v0ud00 15.5.3 sbf transmit operation when the ucnpwr bit = the ucntxe bit of the ucnctl0 register = 1, the transmission enabled status is entered, and sbf transmission is started by setting (to 1) the sbf transmission trigger (ucnstt bit of ucnopt0 register). thereafter, a low-level width of bits 13 to 20 specified by the ucnsls2 to ucnsls0 bits of the ucnopt0 register is output. a transmission enable interrupt (intucnt) is generated upon sbf transmission start. following the end of sbf transmission, the ucnstt bit is automatically cleared. thereafter, the uart transmission mode is restored. transmission is suspended until the data to be transmitted next is written to the ucntx register, or until the sbf transmission trigge r (ucnstt bit) is set. figure 15-14: sbf transmission timing intucnt interrupt 12345678910111213 stop bit setting of ucnstt bit
615 chapter 15 asynchronous serial interface c (uartc) user?s manual u16580ee2v0ud00 15.5.4 sbf receive operation the reception enabled status is achieved by setting the ucnpwr bit of the ucnctl0 register to 1 and then setting the ucnrx bit of the ucnctl0 register to 1. the sbf reception wait status is set by setting the sbf reception trigger (ucnsrt bit of the ucnopt0 register) to 1. in the sbf reception wait status, similarly to the uart reception wait status, the rxdcn pin is monitored and start bit detection is performed. following detection of the start bit, reception is started and the internal counter counts up according to the set baud rate. when a stop bit is received, if the sbf width is 11 or more bits, normal processing is judged and a reception complete interrupt (i ntucnr) is output. error detection for the ucnove, ucnpe, and ucnfe bits of the ucnstr register is suppressed and uart communication error detection processing is not performed. moreover, uartcn reception shift register and data transfer of the ucnrx register are not performed and ffh, the initial valu e, is held. if the sbf width is 10 or fewer bits, reception is terminated as error processing without outputting an interrupt, and the sbf reception mode is returned to. the ucnsrf bit is not cleared at this time. figure 15-15: sbf reception timing (a) normal sbf reception (detection of stop bit in more than 10.5 bits) (b) sbf reception error (detection of stop bit in 10.5 or fewer bits) ucnsrf 123456 11.5 7 8 9 10 11 intucnr interrupt ucnsrf 123456 10.5 78910 intucnr interrupt
616 chapter 15 asynchronous serial interface c (uartc) user?s manual u16580ee2v0ud00 15.5.5 uart transmit operation the transmission enabled status is set by setting the ucntxe bit of the ucnctl0 register to 1, after ucnpwr bit was set to 1, and transmission is started by writing transmit data to the ucntx register. the start bit, parity bit, and stop bit are automatically added. the data in the ucntx register is transferred to the uartcn transmit shift register upon the start of the transmit operation. a transmission enable interrupt (intucnt) is generated upon completion of transmission of the data of the ucntx register to the uartcn transmit shift register, and thereafter the contents of the uartcn transmit shift register are output to the txdcn pin lsb first. write of the next transmit data to the ucntx regist er is enabled by generating the intucnt signal. continuous transmission is enabled by writing the data to be transmitted next to the ucntx register during transfer. figure 15-16: uart transmission remark: if new data is written to the ucntx register due to a transmission enable interrupt (intucnt) before the complete frame has been transferred, the next transmission enable interrupt occurs at that time the stop bit begins. start bit d0 d1 d2 d3 d4 d5 d6 d7 parity bit stop bit intucnt
617 chapter 15 asynchronous serial interface c (uartc) user?s manual u16580ee2v0ud00 15.5.6 continuous transmit operation uartcn can write the next transmit data to the ucntx register when the uartcn transmit shift register starts the shift operation. the transfer timing of the uartcn transmit shift register can be judged from the transmission enable interrupt (intucnt). transmission can be performed without interruption even during interrupt processing following the transmission of 1 data frame via the intucnt signal, and an efficient communication rate can thus be achieved. during continuous transmission, overrun (the completion of the next transmission before the first transmission completion processing has been executed) may occur. an overrun can be detected by incorporating a program that can count the number of transmit data and by referencing transfer status flag (ucntsf bit of ucnstr register). caution: during continuous transmission execution, perform initialization after checking that the ucntsf bit is 0. the transmit data cannot be guaranteed when initialization is performed when the ucntsf bit is 1. figure 15-17: continuous transmission processing flow start register settings ucntx write ye s ye s no no occurrence of transmission interrupt? required number of writes performed? end
618 chapter 15 asynchronous serial interface c (uartc) user?s manual u16580ee2v0ud00 figure 15-18: continuous transfer operation timing (a) transmission start (b) transmission end start data (1) data (1) txdcn ucntx transmission shift register intucnt ucntsf data (2) data (2) data (1) data (3) parity stop start data (2) parity stop start start data (n - 1) data (n - 1) data (n - 1) data (n) ff data (n) txdcn ucntx transmission shift register intucnt ucntsf ucnpwr or ucntxe parity stop stop start data (n) parity parity stop
619 chapter 15 asynchronous serial interface c (uartc) user?s manual u16580ee2v0ud00 15.5.7 uart receive operation the reception wait status is set by setting the ucnpwr bit of the ucnctl0 register to 1 and then setting the ucnrx bit of the ucnctl0 register to 1. in the reception wait status, the rxdcn pin is monitored and start bit detection is performed. start bit detection is performed using a two-step detection routine. first, an 8-bit counter starts upon detection of the falling edge of the rxdc n pin. when the 8-bit counter has counted the ucnctl2 register setting value, the level of the rxdcn pin is monitored again (corresponds to the ? mark in figure 15-19). if the rxdcn pin is low level at this time too, a start bit is recognized. after a start bit has been recognized, the receive operation starts, and serial data is saved to the uartcn receive shift register according to the set baud rate. additionally the ucnrsf flag of ucnstr1 register is set (1) to indicate the receive operation status. when the reception complete interrupt (intucnr) is output upon reception of the stop bit, the data of the uartcn receive shift register is written to the ucnrx register, and the ucnrsf flag is cleared (0) simultaneously. however, if an overrun error occurs (ucnove bit = 1), the receive data at this time is not written to the ucnrx register, and a reception error interrupt (intucnre) is output. even if a parity error (ucnpe bit = 1) or a framing error (ucnfe bit = 1) occurs during reception, reception continues until the stop bit reception position, but a reception error interrupt (intucnre) is output following reception completion. figure 15-19: uart reception timing cautions: 1. be sure to read the ucnrx register even when a reception error occurs. if the ucnrx register is not read, an overrun error occurs during reception of the next data, and reception errors continue occurring indefinitely. 2. the operation during reception is performed assuming that there is only one stop bit. a second stop bit is ignored. start bit d0 d1 d2 d3 d4 d5 d6 d7 parity bit stop bit intucnr ucnrx ucnrsf
620 chapter 15 asynchronous serial interface c (uartc) user?s manual u16580ee2v0ud00 15.5.8 receive error errors during a receive operation are of three types: parity errors, framing errors, and overrun errors. a data reception result error flag is set to the ucnstr register and a reception error interrupt (intucnre) is output. during reception error interrupt processing, it is possible to ascertain which error occurred during reception by reading the contents of the ucnstr register. the reception error flag is cleared by writing 0 to it. table 15-3: reception error causes cautions: 1. in case of a reception error the reception complete interrupt (intucnr) is not generated. instead of this a reception error interrupt (intucnre) can be received. 2. be sure to read the ucnrx register even when a reception error occurs. if the ucnrx register is not read, an overrun error occurs during reception of the next data, and reception errors continue occurring indefinitely. error flag reception error cause ucnpe parity error received parity bit does not match the setting ucnfe framing error stop bit not detected ucnove overrun error reception of next data completed before data was read from receive buffer
621 chapter 15 asynchronous serial interface c (uartc) user?s manual u16580ee2v0ud00 15.5.9 parity types and operations caution: when using the lin function, fix th e ucnps1 and ucnps0 bits of the ucnctl0 register to 00. the parity bit is used to detect bit errors in the communication data. normally the same parity is used on the transmission side and the reception side. in the case of even parity and odd parity, it is possible to detect ?1? bit errors (odd count). in the case of 0 parity and no parity, errors cannot be detected. (1) even parity (a) during transmission the number of bits whose value is ?1? among the transmit data, including the parity bit, is controlled so as to be an even number. the parity bit values are as follows. ? odd number of bits whose value is ?1? among transmit data: 1 ? even number of bits whose value is ?1? among transmit data: 0 (b) during reception the number of bits whose value is ?1? among the reception data, including the parity bit, is counted, and if it is an odd number, a parity error is output. (2) odd parity (a) during transmission opposite to even parity, the number of bits whose value is ?1? among the transmit data, including the parity bit, is controlled so that it is an odd number. the parity bit values are as follows. ? odd number of bits whose value is ?1? among transmit data: 0 ? even number of bits whose value is ?1? among transmit data: 1 (b) during reception the number of bits whose value is ?1? among the receive data, including the parity bit, is counted, and if it is an even number, a parity error is output. (3) 0 parity during transmission, the parity bit is always made 0, regardless of the transmit data. during reception, parity bit check is not performed. therefore, no parity error is generated, regardless of whether the parity bit is 0 or 1. (4) no parity no parity bit is added to the transmit data. reception is performed assuming that there is no parity bit. no parity error occurs since there is no parity bit.
622 chapter 15 asynchronous serial interface c (uartc) user?s manual u16580ee2v0ud00 15.5.10 receive data noise filter this filter performs the rxdcn pin samp ling using the internal system clock (f xx /2). when the same sampling value is read twice, the match detector output changes and sampling as the input data is performed. moreover, since the circuit is as shown in figure 15 -20, the processing that goes on within the receive operation is delayed by 2 clocks in relation to the external signal status. figure 15-20: noise filter circuit match detector in f/2 xx rxdcn qin ld_en q receive data signal
623 chapter 15 asynchronous serial interface c (uartc) user?s manual u16580ee2v0ud00 15.6 dedicated baud rate generator 15.6.1 baud rate generator configuration the dedicated baud rate generator consists of a source clock selector block and an 8-bit programmable counter, and generates a serial clock during transmission and reception with uartcn. regarding the serial clock, a dedicated baud rate generator output can be selected for each channel. there is an 8-bit counter for transmission and another one for reception. figure 15-21: configuration of baud rate generator remarks: 1. n = 0, 1 2. f xx : internal system clock (1) base clock (clock) when the ucnpwr bit of the ucnctl0 register is 1, the clock selected by bits ucncks3 to ucncks0 of the ucnctl1 register is supplied to the 8-bit counter. this clock is called the base clock (clock) and its frequency is called f xclk . when the ucnpwr bit = 0, the clock is fixed to the low level. (2) serial clock generation a serial clock can be generated by setting the ucnctl1 register and the ucnctl2 register (n = 0, 1). the base clock is selected by ucncks3 to ucncks0 bits of the ucnctl1 register. the frequency division value for the 8-bit counter can be set using bits ucnbrs7 to ucnbrs0 of the ucnctl2 register. clock (f ) xclk selector ucnpwr 8-bit counter match detector baud rate ucnctl2: ucnbrs7 to ucnbrs0 1/2 ucnpwr, ucntxen (or ucnrxe) ucnctl1: ucncks3 to ucncks0 f/4 xx f/8 xx f /16 xx f /32 xx f /64 xx f /128 xx f /256 xx f /512 xx f /1024 xx f /2048 xx f /8192 xx f/2 xx
624 chapter 15 asynchronous serial interface c (uartc) user?s manual u16580ee2v0ud00 15.6.2 baud rate the baud rate is obtained by the following equation. f xclk = frequency of base clock (clock) selected by bits ucncks3 to ucncks0 of ucnctl1 register k = value set using bits ucnbrs7 to ucnbrs0 of ucnctl2 register (k = 4, 5, 6,..., 255) 15.6.3 baud rate error the baud rate error is obtained by the following equation. cautions: 1. the baud rate error during transmission must be within the error tolerance on the receiving side. 2. the baud rate error during reception must satisfy the range indicated in section 15.6.5 ?allowable baud rate range during reception? on page 626. example base clock (f xclk ) frequency = 16 mhz = 16,000,000 hz setting value of bits ucnbrs7 to ucnbrs0 of ucnctl2 register = 00110100b (k = 52) target baud rate = 153,600 baud rate = 16,000,000/ (2 52) = 153,846 [bps] error = (153,846/153,600 - 1) 100 = 0.160 [%] baud rate = [bps] 2 k f xclk error actual baud rate (baud rate with error) desired baud rate (correct baud rate) ----------------------------------------------------------------------------------------------------- 1 ? ?? ?? 100 = % []
625 chapter 15 asynchronous serial interface c (uartc) user?s manual u16580ee2v0ud00 15.6.4 baud rate setting example remark: f xx : internal system clock error: baud rate error table 15-4: baud rate generator setting data baud rate [bps] f xx = 64 mhz ucnctl1 ucnctl2 error [%] 50 0bh 4eh 0.16 300 09h 68h 0.16 600 08h 68h 0.16 1200 07h 68h 0.16 2400 06h 68h 0.16 4800 05h 68h 0.16 9600 04h 68h 0.16 10400 04h 60h 0.16 19200 03h 68h 0.16 31250 02h 80h 0.00 38400 02h 68h 0.16 56000 01h 8fh -0.10 76800 01h 68h 0.16 125000 01h 40h 0.00 153600 01h 34h 0.16 250000 01h 20h 0.00 312500 00h 33h 0.39 1000000 00h 10h 0.00 2000000 00h 08h 0.00
626 chapter 15 asynchronous serial interface c (uartc) user?s manual u16580ee2v0ud00 15.6.5 allowable baud rate range during reception the baud rate error range at the destination that is allowable during reception is shown below. caution: the baud rate error during reception must be set within the allowable error range using the following equation. figure 15-22: allowable baud rate range during reception remark: n = 0 to 2 as shown in figure 15-22, the receive data latch timing is determined by the counter set using the ucnctl2 register following start bit detection. the transmit data can be normally received if up to the last data (stop bit) can be received in time for this latch timing. when this is applied to 11-b it reception, the following re sults in terms of logic. fl = (br) -1 br: uartcn baud rate (n = 0, 1) k: ucnctl2 setting value (n = 0, 1) fl: 1-bit data length latch timing margin: 2 clocks minimum allowable transfer rate: fl 1 data frame (11 fl) flmin flmax uartcn transfer rate start bit bit 0 bit 1 bit 7 parity bit minimum allowable transfer rate maximum allowable transfer rate stop bit start bit bit 0 bit 1 bit 7 parity bit latch timing stop bit start bit bit 0 bit 1 bit 7 parity bit stop bit flmin = 11 fl - fl = fl k - 2 21k + 2 2k 2k
627 chapter 15 asynchronous serial interface c (uartc) user?s manual u16580ee2v0ud00 therefore, the maximum baud rate that can be received by the destination is as follows. similarly, obtaining the following maximum allo wable transfer rate yields the following. therefore, the minimum baud rate that can be received by the destination is as follows. obtaining the allowable baud rate error for uartcn and the destination from the above-described equations for obtaining the minimum and maximum baud rate values yields the following. remarks: 1. the reception accuracy depends on the bit count in 1 frame, the input clock frequency, and the division ratio (k). the higher the input clock frequency and the larger the division ratio (k), the higher the accuracy is. 2. k: ucnctl2 setting value (n = 0, 1) table 15-5: maximum/minimum allowable baud rate error divide ratio (k) maximum allowable baud rate error minimum allowable baud rate error 8 +3.53% -3.61% 20 +4.26% -4.31% 50 +4.56% -4.58% 100 +4.66% -4.67% 255 +4.72% -4.73% brmax = (flmin/11) -1 = br 21k + 2 22k flmax = 11 fl - fl = fl 10 11 k + 2 2 k 21k - 2 2 k flmax = fl 11 21k - 2 20k brmin = (flmax/11) -1 = br 21k - 2 20k
628 chapter 15 asynchronous serial interface c (uartc) user?s manual u16580ee2v0ud00 15.6.6 baud rate during continuous transmission during continuous transmission, the transfer rate from the stop bit to the next start bit is usually 2 clocks longer. however, timing initialization is performed through start bit detection by the receiving side, so this has no influence on the transfer result. figure 15-23: transfer rate during continuous transfer assuming 1 bit data length: fl, stop bit length: flstp, and base clock frequency: f xclk, we obtain the following equation. therefore, the transfer rate during continuous transmission is as follows. start bit bit 0 bit 1 bit 7 parity bit stop bit fl 1 data frame fl fl fl fl fl fl flstp start bit of 2nd byte start bit bit 0 flstp = fl + 2/f xclk transfer rate = 11 fl + 2/f xclk
629 user?s manual u16580ee2v0ud00 chapter 16 clocked seri al interface b (csib) 16.1 features ? transfer rate: maximum 8 mbps ? master mode and slave mode selectable ? serial clock and data phase switchable ? transmission data length: 8 to 16 bits (selectable in 1-bit units) ? transfer data msb-first/lsb-first switchable ? transmission mode, reception mode, and transmission/reception mode selectable ? 3-wire serial interface - sobn: serial data output - sibn: serial data input -sckbn : serial clock output ? slave select function supported - ssbn : serial slave select input ? interrupt request signals 3 - reception error interrupt (intcbnre) - reception complete interrupt (intcbnr) - transmission enable interrupt (intcbnt) remark: n = 0, 1 16.2 configuration csib includes the following hardware. table 16-1: csibn configuration item configuration registers csibn receive data register (cbnrx) csibn transmit data register (cbntx) control registers csibn control register 0 (cbnctl0) csibn control register 1 (cbnctl1) csibn control register 2 (cbnctl2) csibn status register (cbnstr)
630 chapter 16 clocked serial interface b (csib) user?s manual u16580ee2v0ud00 figure 16-1: block diagram of csibn remarks: 1. n = 0, 1 2. f xx : internal system clock f brg0 : clock from brg0 f brg1 : clock from brg1 internal bus cbnctl2 cbnctl0 cbnstr controller intcbnre intcbnr sobn intcbnt cbntx so latch phase control shift register cbnrx cbnctl1 phase control sibn f brg1 f brg0 f/8 xx f /128 xx f /16 xx f /32 xx f /64 xx sckbn ssbn selector
631 chapter 16 clocked serial interface b (csib) user?s manual u16580ee2v0ud00 (1) csibn receive data re gister (cbnrx, cbnrxl) the cbnrx register is a 16-bit buffer register that holds receive data. it is overlayed by an 8-bit register cbnrxl on the lower 8 bits, which is used when the transfer data length is 8 bits. the receive operation is started by reading the cbnrx or cbnrxl registers during reception enabled status. the cbnrx register is re ad-only, in 16-bit units. the cbnrxl register is read-only, in 8-bit units. reset input clears the cbnrx register to 0000h, and the cbnrxl register to 00h accordingly. in addition to reset input, the cbnrx or cbnrxl registers can be initialized by clearing (0) the cbnpwr bit of the cbnctl0 register. figure 16-2: csibn receive data register (cbnrx, cbnrxl) after reset: 0000h r address: cb0rx fffffd04h, cb1rx fffffd24h 1514131211109876543210 cbnrx (n = 0, 1) cbnrxl after reset: 00h r address: cb0rxl fffffd04h, cb1rxl fffffd24h 76543210 cbnrxl (n = 0, 1)
632 chapter 16 clocked serial interface b (csib) user?s manual u16580ee2v0ud00 (2) csib transmit data register (cbntx) the cbntx register is a 16-bit buffer register used to write the csib transfer data. it is overlayed by an 8-bit register cbntxl on the lower 8 bits, which is used when the transfer data length is 8 bits. the transmit operation is started by writing data to the cbntx or cbntxl registers during transmission enabled status. the cbntx register can be read or written in 16-bit units. the cbntxl register can be read or written in 8-bit units. reset input clears the cbntx register to 0000h, and the cbnrxl register to 00h accordingly. in addition to reset input, the cbntx and cbntxl registers can be initialized by clearing (to 0) the cbnpwr bit of the cbnctl0 register. figure 16-3: csibn transmit data register (cbntx, cbntxl) after reset: 0000h r/w address: cb0tx fffffd06h, cb1tx fffffd26h 1514131211109876543210 cbntx (n = 0, 1) cbntxl after reset: 00h r/w address: cb0txl fffffd06h, cb1txl fffffd26h 76543210 cbntxl (n = 0, 1)
633 chapter 16 clocked serial interface b (csib) user?s manual u16580ee2v0ud00 16.3 control registers the following registers are used to control csib. ? csibn control register 0 (cbnctl0) ? csibn control register 1 (cbnctl1) ? csibn control register 2 (cbnctl2) ? csibn status register (cbnstr) (1) csibn control register 0 (cbnctl0) the cbnctl0 register is a register that c ontrols the csib serial transfer operation. this register can be read or written in 8-bit or 1-bit units. reset input sets this register to 01h. caution: be sure to set bit 3 to 0 when written to the cbnctl0 register. figure 16-4: csibn control re gister 0 (cbnctl0) (1/2) note: rewrite is possible only when the cbnpwr bit = 0. however, cbnpwr bit = 1 can also be set at the same time. after reset: 01h r/w address: cb0ctl0 fffffd00h, cb1ctl0 fffffd20h 76543210 cbnctl0 cbnpwr cbntxe note cbnrxe note cbndir note 0 cbnsse note cbntms note cbnsce (n = 0, 1) cbnpwr csibn operation control 0 stops clock operation and reset the internal circuit 1 enables operating clock operation the cbnpwr bit controls the csib operating clock and resets the internal circuit. cbntxe note transmission operation enable 0 stops transmission operation 1 enables transmission operation the sobn serial output pin is fixed to low level and communication is stopped by clearing the cbntxe bit to 0. cbnrxe note reception operation enable 0 stops reception operation 1 enables reception operation when the cbnrxe bit is cleared to 0, no rec eption complete interrupt is output even when the prescribed data is transferred in order to stop the receive operation, and the cbnrx register is not updated.
634 chapter 16 clocked serial interface b (csib) user?s manual u16580ee2v0ud00 figure 16-4: csibn control register 0 (cbnctl0) (2/2) note: rewrite is possible only when the cbnpwr bit = 0. however, cbnpwr bit = 1 can also be set at the same time. cbndir note transfer direction selection 0 msb-first transfer 1 lsb-first transfer cbnsse note slave selection operation enable 0 slave selection function disabled 1 slave selection function enabled when the csibn serves as slave, it executes transmission/recepti on in synchronization with the clock only when a low level is input to the ssbn pin. cbntms note transfer mode selection 0 single transfer mode 1 continuous transfer mode when the cbntms bit = 0, the single tran sfer mode is entered, so continuous transmission/continuous reception are not su pported. even in the case of transmission only, an interrupt is output upon completion of reception transfer. cbnsce serial clock enable 0 clock output stopped 1 clock output enabled the transfer clock is stopped after the la st data in the master reception mode. clear (0) the cbnsce bit prior to when the last data is read in the single transfer mode, and 1 clock before the completion of reception of the last data in the continuous transfer mode. the transfer clock can be output by setting the cbnsce bit to 1 again after the last data has been read.
635 chapter 16 clocked serial interface b (csib) user?s manual u16580ee2v0ud00 (2) csibn control register 1 (cbnctl1) the cbnctl1 register is an 8-bit register that controls the csib serial transfer operation. this register can be read or written in 8-bit or 1-bit units. reset input clears this register to 00h. caution: the cbnctl1 register can be rewritten when the cbnpwr bit of the cbnctl0 register is 0 or when both the cbntxe and cbnrxe bits are 0. figure 16-5: csibn control register 1 (cbnctl1) note: for details on the baud rate generator refer to 16.7 ?baud rate generator? on page 657 . after reset: 00h r/w address: cb0ctl1 fffffd01h, cb1ctl1 fffffd21h 76543210 cbnctl1 0 0 0 cbnckp cbndap cbncks2 cbncks1 cbncks0 (n = 0, 1) cbnckp cbndap specification of data transm ission/reception timing in relation to clock phase 00 01 10 11 cbncks2 cbncks1 cbncks0 base clock (f xcclk ) mode 000 f brg0 note master mode 001 f brg1 note master mode 010f xx /8 master mode 011f xx /16 master mode 100f xx /32 master mode 101f xx /64 master mode 110f xx /128 master mode 1 1 1 external clock (sckbn )slave mode d7 d6 d5 d4 d3 d2 d1 d0 sckbn (i/o) sibn capture sobn (output) d7 d6 d5 d4 d3 d2 d1 d0 sckbn (i/o) sibn capture sobn (output) d7 d6 d5 d4 d3 d2 d1 d0 sckbn (i/o) sibn capture (output) d7 d6 d5 d4 d3 d2 d1 d0 sckbn (i/o) sibn capture (output)
636 chapter 16 clocked serial interface b (csib) user?s manual u16580ee2v0ud00 (3) csibn control register 2 (cbnctl2) the cbnctl2 register is an 8-bit register that controls the number of csib serial transfer bits. this register can be read or written in 8-bit units. reset input clears this register to 00h. caution: the cbnctl2 register can be rewritten only when the cbnpwr bit of the cbnctl0 register is 0 or when both the cb0txe and cb0rxe bits are 0. figure 16-6: csibn contro l register 2 (cbnctl2) after reset: 00h r/w address: cb0ctl2 fffffd02h, cb1ctl2 fffffd22h 76543210 cbnctl2 0 0 0 0 cbncl3 cbncl2 cbncl1 cbncl0 (n = 0, 1) cbncl3 cbncl2 cbncl1 cbncl0 serial register bit length 00008 bits 00019 bits 001010 bits 001111 bits 010012 bits 010113 bits 011014 bits 011115 bits 1 16 bits caution: if the number of transfer bits is other than 8 or 16, prepare and use data stuffed from the lsb of th e cbntx and cbnrx registers. remark: : don?t care
637 chapter 16 clocked serial interface b (csib) user?s manual u16580ee2v0ud00 (a) transfer data length function the csib transfer data length can be set in 1-bit units between 8 and 16 bits using bits cbncl3 to cbncl0 of the cbnctl2 register. when the transfer bit length is set to a value other than 16 bits, set the data to the cbntx or cbnrx register starting from the lsb, regardless of whether the transfer start bit is the msb or lsb. any data can be set for the higher bits that are not used, but the receive data becomes 0 following serial transfer. figure 16-7: effect of transfer data length setting (a) transfer bit length = 10 bits, msb first (b) transfer bit length = 12 bits, lsb first 15 10 9 0 sobn sibn insertion of 0 0 sobn 11 12 15 sibn insertion of 0
638 chapter 16 clocked serial interface b (csib) user?s manual u16580ee2v0ud00 (4) csibn status register (cbnstr) the cbnstr register is an 8-bit register that displays the csib status. this register can be read or written in 8-bit or 1-bit units, but the cbnstf flag is a read-only. reset input clears this register to 00h. in addition to reset input, the cbnstr register can be initialized by clearing (0) the cbnpwr bit of the cbnctl0 register. figure 16-8: csibn status register (cbnstr) after reset: 00h r/w address: cb0ctl0 fffffd03h, cb1ctl0 fffffd23h 76543210 cbnstrcbntsf000000cbnove (n = 0, 1) cbntsf csibn operation control 0 idle status 1 operating status during transmission, this register is set (1) when data is prepared in the cbntx register, and during reception, it is set (1) when a dum my read of the cbnrx register is performed. the clear timing is after the edge of the last clock. cbnove overrun error flag 0no overrun 1overrun ? an overrun error occurs when the next reception starts without performing a cpu read of the value of the cbnrx register up on completion of the receive operation. in this case the cbnove flag displays the overrun error occurrence status, and a reception error interrupt (intcbnre) is generated. ? the cbnove flag is cleared by writing 0 to it . it cannot be set even by writing 1 to it.
639 chapter 16 clocked serial interface b (csib) user?s manual u16580ee2v0ud00 16.4 operation 16.4.1 single transfer mode (maste r mode, transmission/reception mode) figure 16-9: single transfer mode (mas ter mode, transmission/reception mode) msb first (cbndir bit of cbnctl0 register = 0), cbnckp bit of the cbnctl1 register = 0, cbndap bit of the cbnctl1 register = 0, transfer data length = 8 bits (csncl3 to cbncl0 bits of cbnctl2 register = 0000b) <1> set the cbnctl1 and cbnctl2 registers to specify the transfer mode. <2> set the cbntxe and cbnrxe bits of the cbnctl0 register to 1 at the same time as specifying the transfer mode using the cbndir bit of th e cbnctl0 register, to set the transmission/ reception enable status. <3> set the cbnpwr bit of the cbnctl0 register to 1 to enable csib operating clock supply. <4> write transfer data to the cbntx register (transmission start). <5> the reception complete interrupt (intcbnr) is output, notifying the cpu that reading the cbnrx (cbnrxl) register is possible. <6> read the cbnrx register before clearing the cbnpwr bit to 0. <7> check that the cbntsf bit of the cbnstr register is 0 and clear the cbnpwr bit to 0 to stop clock supply to csib (end of transmission/reception). to continue transfer, repeat steps <4> to <6> before <7>. remarks: 1. the processing of steps <2> and <3> can be set simultaneously. 2. n = 0, 1 cbntx register write (55h) cbnrx register read (aah) (aah) (55h) 1 0 1 1 0 1 abh 56h adh 5ah b5h 6ah d5h aah 55h (transmit data) sckbn pin cbntx register aah 00h 00h cbnrx register shift register n intcbnr signal sibn pin sobn pin 0 0 0 1 0 0 1 0 1 1 <1> <4> <5> <7> <6> <2> <3>
640 chapter 16 clocked serial interface b (csib) user?s manual u16580ee2v0ud00 16.4.2 single transfer mode (master mode, transmission mode) figure 16-10: single transfer mode (master mode, transmission mode) msb first (cbndir bit of cbnctl0 register = 0), cbnckp bit of the cbnctl1 register = 0, cbndap bit of the cbnctl1 register = 0, transfer data length = 8 bits (csncl3 to cbncl0 bits of cbnctl2 register = 0000b) <1> set the cbnctl1 and cbnctl2 registers to specify the transfer mode. <2> set the cbntxe bit of the cbnctl0 register to 1 at the same time as specifying the transfer mode using the cbndir bit of the cbnctl0 regi ster, to set the transmission/reception enable status. <3> set the cbnpwr bit of the cbnctl0 register to 1 to enable csib operating clock supply. <4> write transfer data to the cbntx register (transmission start). <5> the reception complete interr upt (intcbnr) is output, notifyin g the cpu that writing the cbntx (cbntxl) register is possible. <6> check that the cbntsf bit of the cbnstr register is 0 and clear the cbnpwr bit to 0 to stop clock supply to csib (end of transmission/reception). to continue transfer, repeat steps <4> and <5> before <6>. remarks: 1. the processing of steps <2> and <3> can be set simultaneously. 2. n = 0, 1 cbntx register write (55h) aah 54h a8h 50h a0h 40h 80h 00h 55h (transmit data) cbntx register shift register n <1> <4> <5> <6> <2> <3> sckbn pin intcbnr signal sibn pin cbntsf bit (55h) 0 1 0 0 1 0 l 1 1 sobn pin
641 chapter 16 clocked serial interface b (csib) user?s manual u16580ee2v0ud00 16.4.3 single transfer mode (master mode, reception mode) figure 16-11: single transfer mode (master mode, reception mode) msb first (cbndir bit of cbnctl0 register = 0), cbnckp bit of the cbnctl1 register = 0, cbndap bit of the cbnctl1 register = 0, transfer data length = 8 bits (csncl3 to cbncl0 bits of cbnctl2 register = 0000b) <1> set the cbnctl1 and cbnctl2 registers to specify the transfer mode. <2> set the cbnrxe bit of the cbnctl0 register to 1 at the same time as specifying the transfer mode using the cbndir bit of the cbnctl0 register, to set the reception enabled status. <3> set the cbnpwr bit of the cbnctl0 register to 1 to enable csib operating clock supply. <4> perform a dummy read of the cbnrx register (reception start trigger). <5> the reception complete interrupt (intcbnr) is output, notifying the cpu that reading the cbnrx (cbnrxl) register is possible. <6> clear the cbnsce bit of the cbnctl0 register to 0 to set the reception end data status. <7> read the cbnrx register before clearing the cbnpwr bit to 0. <8> check that the cbntsf bit of the cbnstr register is 0 and clear the cbnpwr bit to 0 to stop clock supply to csib (end of reception). to continue transfer, repeat steps <4> and <5> before <6>. (at this time, <4> is not a dummy read, but a receive data read combined with the reception trigger.) remarks: 1. the processing of steps <2> and <3> can be set simultaneously. 2. n = 0, 1 (aah) 1 0 1 1 0 1 abh 56h adh 5ah b5h 6ah d5h aah 55h (receive data) sckbn pin cbnrx register cbnrx register read (55h) shift register n cbnsce bit intcbnr signal sibn pin sobn pin 0 0 l <1> <2> <3> <4> <5> <6> <8> <7> cbnrx register read (aah) aah 00h 00h
642 chapter 16 clocked serial interface b (csib) user?s manual u16580ee2v0ud00 16.4.4 continuous mode (master mode, transmission/reception mode) figure 16-12: continuous mode (master mode, transmission/reception mode) msb first (cbndir bit of cbnctl0 register = 0), cbnckp bit of the cbnctl1 register = 1, cbndap bit of the cbnctl1 register = 0, transfer data length = 8 bits (csncl3 to cbncl0 bits of cbnctl2 register = 0000b) <1> set the cbnctl1 and cbnctl2 registers to specify the transfer mode. <2> set the cbntxe and cbnrxe bits of the cbnctl0 register to 1 at the same time as specifying the transfer mode using the cbndir bit of the cbnctl0 register, to set the transmission/ reception enabled status. <3> set the cbnpwr bit of the cbnctl0 register is 1 to enable csib operating clock supply. <4> write transfer data to the cbntx register (transmission start). <5> the transmission enable interrupt (intcbnt) is received and transfer data is written to the cbntx register. <6> the reception complete interrupt (intcbnr) is output, notifying the cpu that reading the cbnrx (cbnrxl) register is possible. read the cbnrx register before the next receive data arrives or before the cbnpwr bit is cleared to 0. <7> check that the cbntsf bit of the cbnstr register is 0 and clear the cbnpwr bit to 0 to stop clock supply to csib (end of transmission/reception). to continue transfer, repeat steps <4> to <6> before <7>. remark: n = 0, 1 <1> <2> <3> <7> <6> <6> <5> <4> 96h 00h cch 1 1 1 1 1 1 1 0 0 0 0 0 0 0 1 1 1 1 1 1 55h cbntx register sckbn pin sobn pin sibn pin intcbnt signal intcbnr signal shift register n so latch 0 0 0 0 0 0 aah 96h cch 1 1 1 0 0 0 00h
643 chapter 16 clocked serial interface b (csib) user?s manual u16580ee2v0ud00 16.4.5 continuous mode (master mode, transmission mode) figure 16-13: continuous mode (master mode, transmission mode) msb first (cbndir bit of cbnctl0 register = 0), cbnckp bit of the cbnctl1 register = 0, cbndap bit of the cbnctl1 register = 0, transfer data length = 8 bits (csncl3 to cbncl0 bits of cbnctl2 register = 0000b) <1> set the cbnctl1 and cbnctl2 registers to specify the transfer mode. <2> set the cbntxe of the cbnctl0 register to 1 at the same time as specifying the transfer mode using the cbndir bit of the cbnctl0 register, to set the transmission/reception enabled status. <3> set the cbnpwr bit of the cbnctl0 register is 1 to enable csib operating clock supply. <4> write transfer data to the cbntx register (transmission start). <5> the transmission enable interrupt (intcbnt) is received and transfer data is written to the cbntx register. <6> check that the cbntsf bit of the cbnstr register is 0 and clear the cbnpwr bit to 0 to stop clock supply to csib (end of transmission/reception). to continue transfer, repeat steps <4> and <5> before <6>. remark: n = 0, 1 <1> <2> <3> <6> <5> <4> 0 1 1 1 1 1 1 1 l 0 0 0 0 0 sckbn pin sobn pin sibn pin intcbnt signal 0 0 1 shift register n so latch aah cbntx register cbntsf bit 55h 00h 00h
644 chapter 16 clocked serial interface b (csib) user?s manual u16580ee2v0ud00 16.4.6 continuous mode (master mode, reception mode) figure 16-14: continuous mode (master mode, reception mode) msb first (cbndir bit of cbnctl0 register = 0), cbnckp bit of the cbnctl1 register = 0, cbndap bit of the cbnctl1 register = 1, transfer data length = 8 bits (csncl3 to cbncl0 bits of cbnctl2 register = 0000b) <1> set the cbnctl1 and cbnctl2 registers to specify the transfer mode. <2> set the cbnrxe bit of the cbnctl0 register to 1 at the same time as specifying the transfer mode using the cbndir bit of the cbnctl0 register, to set the reception enabled status. <3> set the cbnpwr bit of the cbnctl0 register is 1 to enable csib operating clock supply. <4> perform a dummy read of the cbnrx register (reception start trigger). <5> the reception complete interrupt (intcbnr) is output, notifying the cpu that reading the cbnrx (cbnrxl) register is possible. read the cbnrx register before the next receive data arrives or before the cbnpwr bit is cleared to 0. <6> clear the cbnsce bit of the cbnctl0 register is 0 to set the reception end data status. <7> check that the cbntsf bit of the cbnstr register is 0 and clear the cbnpwr bit to 0 to stop clock supply to csib (end of reception). to continue transfer, repeat steps <4> and <5> before <6>. remark: n = 0, 1 <1> <2> <3> <7> <5> <5> <6> <4> 1 0 0 0 0 0 0 01 1 1 1 1 55h sckbn pin cbnsce bit sibn pin intcnr signal shift register n cbnrx register 1 1 0 55h aah aah 00h 00h
645 chapter 16 clocked serial interface b (csib) user?s manual u16580ee2v0ud00 16.4.7 continuous reception mode (error) figure 16-15: continuous reception mode (error) msb first (cbndir bit of cbnctl0 register = 0), cbnckp bit of the cbnctl1 register = 0, cbndap bit of the cbnctl1 register = 1, transfer data length = 8 bits (csncl3 to cbncl0 bits of cbnctl2 register = 0000b) <1> set the cbnctl1 and cbnctl2 registers to specify the transfer mode. <2> set the cbntxe and cbnrxe bits of the cbnctl0 register to 1 at the same time as specifying the transfer mode using the cbndir bit of th e cbnctl0 register, to set the transmission/ reception enable status. <3> set the cbnpwr bit of the cbnctl0 register to 1 to enable csib operating clock supply. <4> perform a dummy read of the cbnrx register (reception start trigger). <5> the reception complete interrupt (intcbnr) is output, notifying the cpu that reading the cbnrx (cbnrxl) register is possible. <6> if the data could not be read before the end of the next transfer, a receive error interrupt (intcbnre) is output and the cbnove flag of the cbnstr register is set (1). the cbnrx register is read as error restore processing. <7> check that the cbntsf bit of the cbnstr register is 0 and clear the cbnpwr bit to 0 to stop clock supply to csibn (end of reception). remark: n = 0, 1 1 0 0 0 0 0 011 1 1 1 1 sckbn pin sibn pin intcbnr signal intcbnre signal 0 1 0 <1> <2> <3> <7> <6> <5> <4> 00h shift register n cbnrx register cbnove flag 55h 55h aah
646 chapter 16 clocked serial interface b (csib) user?s manual u16580ee2v0ud00 16.4.8 continuous mode (slave mode, transmission/reception mode) figure 16-16: continuous mode (slave mode, transmission/reception mode) msb first (cbndir bit of cbnctl0 register = 0), cbnckp bit of the cbnctl1 register = 0, cbndap bit of the cbnctl1 register = 1, transfer data length = 8 bits (csncl3 to cbncl0 bits of cbnctl2 register = 0000b) <1> set the cbnctl1 and cbnctl2 registers to specify the transfer mode. <2> set the cbntxe and cbnrxe bits of the cbnctl0 register to 1 at the same time as specifying the transfer mode using the cbndir bit of the cbnctl0 register, to set the transmission/ reception enabled status. <3> set the cbnpwr bit of the cbnctl0 register to 1 to enable csib operating clock supply. <4> write the transfer data to the cbntx register. <5> the transmission enable interrup t (intcbnt) is received and the transfer data is written to the cbntx register. <6> the reception complete interrupt (intcbnr) is output, notifying the cpu that reading the cbnrx register is possible. read the cbnrx register before the next receive data arrives or before the cbnpwr bit is cleared to 0. <7> check that the cbntsf bit of the cbnstr register is 0 and clear the cbnpwr bit to 0 to stop clock supply to csib (end of transmission/reception). to continue transfer, repeat steps <4> to <6> before <7>. remark: n = 0, 1 <1> <2> <3> <7> <6> <6> <5> <4> 96h 00h cch 1 1 1 1 1 1 1 0 0 0 0 0 0 0 1 1 1 1 1 1 55h cbntx register sckbn pin sobn pin sibn pin intcbnt signal intcbnr signal shift register n so latch cbnrx register 0 0 0 0 0 0 aah 96h cch 1 0 0 0 1 1 00h
647 chapter 16 clocked serial interface b (csib) user?s manual u16580ee2v0ud00 16.4.9 continuous mode (slave mode, reception mode) figure 16-17: continuous mode (slave mode, reception mode) msb first (cbndir bit of cbnctl0 register = 0), cbnckp bit of the cbnctl1 register = 0, cbndap bit of the cbnctl1 register = 0, transfer data length = 8 bits (csncl3 to cbncl0 bits of cbnctl2 register = 0000b) <1> set the cbnctl1 and cbnctl2 registers to specify the transfer mode. <2> set the cbnrxe bit of the cbnctl0 register to 1 at the same time as specifying the transfer mode using the cbndir bit of the cbnctl0 register, to set the reception enabled status. <3> set the cbnpwr bit of the cbnctl0 register to 1 to enable csib operating clock supply. <4> perform a dummy read of the cbnrx register (reception start trigger). <5> the reception complete interrupt (intcbnr) is output, notifying the cpu that reading the cbnrx register is possible. read the cbnrx register before the next receive data arrives or before the cbnpwr bit is cleared to 0. <6> check that the cbntsf bit of the cbnstr register is 0 and clear the cbnpwr bit to 0 to stop clock supply to csib (end of reception). to continue transfer, repeat steps <4> and <5> before <6>. remark: n = 0, 1 <1> <2> <3> <6> <5> <5> <4> 1 0 0 0 0 0 0 01 1 1 1 1 55h sckbn pin sibn pin intcbnr signal shift register n cbnrx register 1 1 55h aah 00h 00h aah 0
648 chapter 16 clocked serial interface b (csib) user?s manual u16580ee2v0ud00 16.4.10 clock timing figure 16-18: csibn clock timing (1/2) (a) cbnckp = 0, cbndap = 0 (b) cbnckp = 1, cbndap = 0 remark: n = 0, 1 d6 d5 d4 d3 d2 d1 d0 d7 sibn capture reg-r/w sobn pin intcbnt interrupt intcbnr interrupt cbntsf bit sckbn pin d6 d5 d4 d3 d2 d1 d0 d7 sibn capture reg-r/w sobn pin intcbnt interrupt intcbnr interrupt cbntsf bit sckbn pin
649 chapter 16 clocked serial interface b (csib) user?s manual u16580ee2v0ud00 figure 16-18: csibn clock timing (2/2) (c) cbnckp = 0, cbndap = 1 (d) cbnckp = 1, cbndap = 1 remark: n = 0, 1 d6 d5 d4 d3 d2 d1 d0 d7 sibn capture reg-r/w sobn pin intcbnt interrupt intcbnr interrupt cbntsf bit sckbn pin d6 d5 d4 d3 d2 d1 d0 d7 sibn capture reg-r/w sobn pin intcbnt interrupt intcbnr interrupt cbntsf bit sckbn pin
650 chapter 16 clocked serial interface b (csib) user?s manual u16580ee2v0ud00 16.5 output pins (1) sckbn pin when csibn operation is disabled (cbnpwr bit of cbnctl0 register = 0), the sckbn pin output status is as follows. remarks: 1. the sckbn pin output changes when the cbnc kp bit of the cbnctl1 register is rewritten. 2. n = 0, 1 (2) sobn pin when csibn operation is disabled (cbnpwr bit = 0), the sobn pin output status is as follows. remarks: 1. the sobn pin output changes when any one of the cbntxe, cbndap, and cbndir bits of the cbnctl1 register is rewritten. 2. n = 0, 1 3. : don?t care cbnckp sckbn pin output 0 fixed to high level 1 fixed to low level cbntxe cbndap cbndir sobn pin output 0 fixed to high level 1 0 sobn latch value (low level) 1 0 cbntxn value (msb) 1 cbntxn value (lsb)
651 chapter 16 clocked serial interface b (csib) user?s manual u16580ee2v0ud00 16.6 operation flow (1) single transmission figure 16-19: operation flow of single transmission note: set the cbnsce bit of cbnctl0 register to 1 as part of the initial settings. remark: n = 0, 1 start no ye s intcbnr = 1 transfer data exists? end ye s no initial settings (cbnctl0 / cbnctl1 registers etc.) note cbntx register write (transfer start)
652 chapter 16 clocked serial interface b (csib) user?s manual u16580ee2v0ud00 (2) single reception (master) figure 16-20: operation flow of single reception (master) note: set the cbnsce bit of cbnctl0 register to 1 as part of the initial settings. remark: n = 0, 1 start no no intcbnr = 1 last data? end ye s ye s dummy read of cbnrx register cbnctl0.cbnsce bit = 0 cbnctl0.cbnsce bit = 1 cbnrx register read cbnrx register read initial settings (cbnctl0 / cbnctl1 registers etc.) note
653 chapter 16 clocked serial interface b (csib) user?s manual u16580ee2v0ud00 (3) single reception (slave) figure 16-21: operation flow of single reception (slave) note: set the cbnsce bit of cbnctl0 register to 1 as part of the initial settings. remark: n = 0, 1 start no no intcbnr = 1 last data? end ye s ye s cbnrx register read initial settings (cbnctl0 / cbnctl1 registers etc.) note dummy read of cbnrx register
654 chapter 16 clocked serial interface b (csib) user?s manual u16580ee2v0ud00 (4) continuous transmission figure 16-22: operation flow of continuous transmission note: set the cbnsce bit of cbnctl0 register to 1 as part of the initial settings. remarks: 1. the steps below the broken line constitute the transmission flow. execute only steps below the broken line when starting the second and subsequent transmissions. 2. n = 0, 1 start no ye s intcbnt = 1 data to be transferred next exists? end ye s no cbntx register write (transfer start) initial settings (cbnctl0 / cbnctl1 registers etc.) note
655 chapter 16 clocked serial interface b (csib) user?s manual u16580ee2v0ud00 (5) continuous reception (master) figure 16-23: operation flow of continuous reception (master) note: set the cbnsce bit of cbnctl0 register to 1 as part of the initial settings. remarks: 1. the steps below the broken line constitute the transmission flow. execute only steps below the broken line when starting the second and subsequent transmissions. 2. n = 0, 1 no no intcbnr = 1 data currently received = last data? ye s ye s cbnctl0.cbnsce bit = 0 cbnrx register read no intcbnr = 1 end ye s cbnctl0.cbnsce bit = 1 cbnrx register read cbnrx register read start initial settings (cbnctl0 / cbnctl1 registers etc.) note dummy read of cbnrx register
656 chapter 16 clocked serial interface b (csib) user?s manual u16580ee2v0ud00 (6) continuous reception (slave) figure 16-24: operation flow of continuous reception (slave) note: set the cbnsce bit of cbnctl0 register to 1 as part of the initial settings. remarks: 1. the steps below the broken line constitute the transmission flow. execute only steps below the broken line when starting the second and subsequent transmissions. 2. n = 0, 1 start no no intcbnr = 1 last data? end ye s ye s cbnrx register read initial settings (cbnctl0 / cbnctl1 registers etc.) note dummy read of cbnrx register
657 chapter 16 clocked serial interface b (csib) user?s manual u16580ee2v0ud00 16.7 baud rate generator 16.7.1 configuration figure 16-25: block diagram of baud rate generators 0 and 1 (brg0, brg1) the baud rate generators 0 and 1 (brg0, brg1) and csib0 and csib1 are connected as shown in the following block diagram. figure 16-26: block diagram of csibn baud rate generators remarks: 1. an unused baud rate generator (brgm) can be employed as interval timer generating a dedicated interrupt request (intbrgm). 2. m = 0, 1 brgoutm intbrgm prscmm 8-bit counter output control f/8 xx f /16 xx f /32 xx f /64 xx csib0 csib1 intbrg0 brgout0 brgout1 intbrg1 brg0 brg1 f/4 xx f/4 xx
658 chapter 16 clocked serial interface b (csib) user?s manual u16580ee2v0ud00 16.7.2 control registers (1) prescaler mode registers 0 and 1 (prsm0, prsm1) the prsmm register controls generation of a baud rate signal for csib (m = 0, 1). this register can be read or written in 8-bit or 1-bit units. reset input clears this register to 00h. figure 16-27: prescaler mode registers 0 and 1 (prsm0, prsm1) cautions: 1. do not rewrite the prsmm register during operation. 2. set the bgcsm1, bgcs m0 bits before setting the bgcem bit to 1. remark: m = 0, 1 after reset: 00h r/w address: prsm0 fffffdc0h, prsm1 fffffdd0h 76543210 prsmm 0 0 bgcem 0 0 bgcsm1 bgcsm0 (m = 0, 1) bgcem baud rate generator output control 0 disabled 1 enabled bgcsm1 bgcsm0 baud rate generator clock selection (f bgcsm ) setting value (k) 00f xx /4 2 01f xx /8 3 10f xx /16 4 11f xx /32 5
659 chapter 16 clocked serial interface b (csib) user?s manual u16580ee2v0ud00 (2) prescaler compare registers 0 and 1 (prscm0, prscm1) the prscmm register is an 8-bit compare register (m = 0, 1). this register can be read or written in 8-bit units. reset input clears this register to 00h. figure 16-28: prescaler compare registers 0 and 1 (prscm0, prscm1) cautions: 1. do not rewrite the prscmm register during operation. 2. set the prscmm register before sett ing the bgcem bit of the prsmm register to 1. remarks: 1. f bgcsm : clock frequency selected by the bgcsm1, bgcsm0 bits of the prsmm register. 2. m = 0, 1 after reset: 00h r/w address: prsm0 fffffdc1h, prsm1 fffffdd1h 76543210 prscmm prscmm7 prscmm6 prscmm5 prscmm4 prscmm3 prscmm2 prscmm1 prscmm0 (m = 0, 1) prscm m7 prscm m6 prscm m5 prscm m4 prscm m3 prscm m2 prscm m1 prscm m0 serial clock n 00000000f bgscm /512 256 00000001f bgscm /2 1 00000010f bgscm /4 2 :::::::: : : 11111100f bgscm /504 252 11111101f bgscm /506 253 11111110f bgscm /508 254 11111111f bgscm /510 255
660 chapter 16 clocked serial interface b (csib) user?s manual u16580ee2v0ud00 16.7.3 baud rate generation the transmission/reception clock is generated by dividing the main clock. the baud rate generated from the main clock is obtained by the following equation. remarks: 1. f brgm : brgm count clock 2. f bgcsm : clock frequency selected by the bgcsm1, bgcsm0 bits of the prsmm register. 3. f xx : main clock oscillation frequency 4. k: prsmm register setting value (2 k 5) 5. n: prscmm register setting value (1 to 255), when prscmm = 01h to ffh, or n = 256, when prscmm = 00h. 6. m = 0, 1 f brgm f bgcsm n2 -------------------- f xx 2 k n2 --------------------------- - ==
661 user?s manual u16580ee2v0ud00 chapter 17 clocked seri al interface 3 (csi3) 17.1 features ? transfer rate: maximum 8 mbps ? master mode and slave mode selectable ? serial clock and data phase switchable ? transmission data length: 8 to 16 bits (selectable in 1-bit units) ? transfer data msb-first/lsb-first switchable ? transmission mode, reception mode, and transmission/reception mode selectable ? 3-wire serial interface - so3n: serial data output - si3n: serial data input -sck3n : serial clock i/o ? four external chips select signal outputs (scs3n0 to scs3n3) ? interrupt request signals 2 - transmission/reception comp letion interrupt (intc3n) - csibufn overflow interrupt (intc3novf) ? sixteen on-chip 20-bit transmit/receive buffers (csibufn) ? on-chip dedicated baud rate generator remark: n = 0, 1
662 chapter 17 clocked serial interface 3 (csi3) user?s manual u16580ee2v0ud00 17.2 configuration csi3n is controlled by the clocked serial interface mode register 3n (csim3n) (n = 0, 1). (1) clocked serial interface mode registers 30, 31 (csim30, csim31) the csim3n register is an 8-bit register for specifying the operation of csi3n. (2) clocked serial interface clock select registers 30, 31 (csic30, csic31) the csic3n register is an 8-bi t register for controlling the oper ation clock and operating mode of csi3n. (3) serial i/o shift registers 30, 31 (sio30, sio30) the sio3n register is an 8-bit register for converting between serial data and parallel data. sio3n is used for both transmission and reception. data is shifted in (reception) or shifted out (transmission) beginning at either the msb side or the lsb side. (4) receive data buffer registers 30, 31 (sirb30, sirb31) the sirb3n register is a 16-bit buffer register that stores receive data. this register is also divided into two registers: the higher 8 bits (sirb3nh) and lower 8 bits (sirb3nl). (5) chip select csi buffer register 30, 31 (sfcs30, sfcs31) the sfcs3n register is a 16-bit buffer register that stores chip select data. the lower 8 bits can also be accessed by an 8-bit buffer register (sfcs3nl). (6) transmit data csi buffer registers 30, 31 (sfdb30, sfdb31) the sfdb3n register is a 16-bit buffer register that stores transmit data. this register is also divided into two registers: the higher 8 bits (sfdb3nh) and lower 8 bits (sfdb3nl). (7) csibuf status registers 30, 31 (sfa30, sfa31) the sfa3n register is an 8-bit register that indicates the status of csi data buffer register n (csibufn) or the transfer status. (8) transfer data length select registers 30, 31 (csil30, csil31) the csil3n register is an 8-bit register that selects the csi3n transfer data length. (9) transfer data number specification registers 30, 31 (sfn30, sfn31) the sfn3n register is an 8-bit register that sets the number of csi3n transfer data in consecutive mode. (10) csi data buffer registers 0, 1 (csibuf0, csibuf1) by consecutively writing transmit data to the sfdb3n register from where it is transferred, the data can be stored in the csibufn register while th e csibufn pointer for writing is automatically incremented (csibufn). the csibufn is a 16-bit buffer register.
663 chapter 17 clocked serial interface 3 (csi3) user?s manual u16580ee2v0ud00 figure 17-1: block diagram of clocked serial interface 3n (csi3n) remarks: 1. n = 0, 1 2. f xx : main clock f xclk : basic clock selected by cks3n2 to cks3n0 bits of csic3n register so3n sck3n intc3n si3n scs3n3 scs3n2 scs3n1 scs3n0 sck3n transfer control csi data buffer register n (csibufn) brg3n prescaler output f xx receive data buffer register 3n (sirb3n) shift register n (sio3n) 0 19 15 16 intc3novf transfer data control csibuf status register 3n (sfa3n) transmit data csi buffer register 3n (sfdb3n) chip select csi buffer register 3n (sfcs3n) selector chip select control f xclk clocked serial interface clock select register 3n (csic3n) mdln1 mdln0 cks3n2 cks3n1 cks3n0 mdln2
664 chapter 17 clocked serial interface 3 (csi3) user?s manual u16580ee2v0ud00 17.3 control registers (1) clocked serial interface mode registers 3n (csim3n) the csim3n register controls the operation of csi3n (n = 0, 1). this registers can be read or written in 8-bit or 1-bit units. reset input sets this register to 00h. cautions: 1. writing the trmdn, dirn, csitn, cswen, and csmdn bits is enabled only when ctxen bit = 0 and crxen bit = 0. 2. to use csi3n, be sure to set the external pins related to the csi3n function to control the mode and set the csic3n register. then set the csicaen bit to 1 before setting the other bits. figure 17-2: clocked serial interface mode register 3n (csim3n) (1/2) remark: n = 0, 1 after reset: 00h r/w address: csim30 fffffd40h, csim31 fffffd60h 76543210 csim3n csicaen ctxen crxen trmdn dirn csitn cswen csmdn (n = 0, 1) csicaen csi3n operation clock control 0 stops clock supply to csi3n 1 supplies clock to csi3n cautions: 1. the csi3n unit is reset wh en the csicaen bit = 0, and csi3n is stopped. to operate csi3n, first set the csicaen bit to 1. 2. when rewriting the csicaen bit from 0 to 1 or from 1 to 0, simultaneously rewriting the bits other than the csicaen bit of the csim3n register is prohibited. when the csicaen bit = 0, rewritin g the bits other than the csicaen bit of the csim3n register, an d the sfdb3n, sfdb3nl, and sfa3n registers is prohibited. ctxen transmission operation enable 0 disables transmission 1 enables transmission caution: the ctxen bit is reset when the csicaen bit is cleared to 0. crxen reception operation enable 0 disables reception 1 enables reception caution: the crxen bit is reset when the csicaen bit is cleared to 0.
665 chapter 17 clocked serial interface 3 (csi3) user?s manual u16580ee2v0ud00 figure 17-2: clocked serial interface mode register 3n (csim3n) (2/2) remark: n = 0, 1 trmdn transfer mode specification 0 single mode 1 consecutive mode dirn transfer direction specification 0 msb-first transfer 1 lsb-first transfer specifies the transfer direction when data is written from the sfdb3n register to the csibufn register or read from the sirb3n and csibufn registers. csitn transmission completion interrupt (intc3n) control 0 no delay 1 delay mode (the interrupt request si gnal is delayed by half a cycle.) cautions: 1. the delay mode (csit bit = 1) is valid only in the master mode (cks3n2 to cks3n0 bits of the csic 3n register other than 111b). in the slave mode (cks3n2 to cks3n0 bi ts = 111b), do not set the delay mode. if the delay mode is set, intc3n is not affected by the csitn bit. 2. if the csitn bit is set to 1 in the consecutive mode (trmdn bit = 1), the intc3n interrup t is not output except when the last data set by the sfnn3 to sfnn0 bits of the sfn3n re gister is transferred, but a delay of half a clock can be inserted between each data transferred. cswen transfer wait control 0 disables transfer wait. 1 enables transfer wait (1 wait cycl e inserted on starting transfer). caution: inserting a transfer wait cycle (csw en bit = 1) is valid only in the master mode (cks3n2 to cks3n0 bi ts of the csic3n register other than 111b). in the slave mode (cks3n2 to cks3n0 bits = 111b), do not insert a transfer wait cycle. if set, a transfer wait cycle is not inserted. csmdn chip select mode specification 0 disables inactive level setting of ch ip select outputs (scs3n0 to scs3n3) during transfer wait. 1 enables inactive level setting of chip select outputs (scs3n0 to scs3n3) during transfer wait. caution: the csmdn bit setting is valid on ly when the transfer wait is enabled (cswen bit = 1) and the master mode is specified (cks3n0 bits of the csic3n register other than 111b). in all other cases the csmdn bit setti ng is invalid and no inactive level setting of chip select outputs betw een two consecutive transfers takes place.
666 chapter 17 clocked serial interface 3 (csi3) user?s manual u16580ee2v0ud00 (2) clocked serial interface clock select register 3n (csic3n) the csic3n register is an 8-bit register that controls the operation clock and operating mode of csi3n. this register can be read or written in 8-bit or 1-bit units. reset input sets this register to 07h. caution: data can be written to the csic3n register only when the ctxen bit = 0 and crxen bit = 0 in the csim3n register. figure 17-3: clocked serial interface clock select register 3n (csic3n) (1/3) after reset: 07h r/w address: csic30 fffffd41h, csic31 fffffd61h 76543210 csic3n mdln2 mdln1 mdln0 ckpn dapn cks3n2 cks3n1 cks3n0 (n = 0, 1) mdln2 mdln1 mdln0 set value (n) transfer clock (brg3n output signal) 000?brg3n stop mode (power save) 0011f xclk /2 0102f xclk /4 0113f xclk /6 1004f xclk /8 1015f xclk /10 1106f xclk /12 1117f xclk /14 caution: in the slave mode ( cks3n2 to cks3n0 bits = 11 1b), it is recommended to clear the mdln2 to mdln0 bits to 000 (brg3n stop mode).
667 chapter 17 clocked serial interface 3 (csi3) user?s manual u16580ee2v0ud00 figure 17-3: clocked serial interface clock select register 3n (csic3n) (2/3) note: if the ckpn bit is set to 1 in the master mode (cks3n2 to cks3n0 bits are other than 111b), the sck3n pin outputs a low level when it is inactive. if the ctxen bit of the csim3n register is cleared to 0 (disabling transmission) and crxen bit is cleared to 0 (disabling reception), the sck3n pin outputs a high level. therefore, take the following measures to fix the sck3n pin to low level when csi3n is not used. [sck3n pin] <1> clear the corresponding port bit (p82 of the p8 register for csi30, or p92 of the p9 register for csi31) to 0: the port output level is set to low. <2> clear the corresponding bit in the port mode register (pm82 of the pm8 register for csi30, or pm92 of the pm9 register for csi31) to 0: the pin is set into output mode. <3> clear the corresponding bit in the port mode control register (pmc82 of the pmc8 register for csi30, or pmc92 of the pmc9 register for csi31) to 0: the pin is set into port mode (fixed to low-level output). <4> clear the ctxen and crxen bits of the csim3n register to 0: transmission and reception are disabled. <5> set the ctxen or crxen bit of the csim3n register to 1: transmission or reception is enabled (b oth transmission and reception can also be enabled). <6> set the corresponding bit in the port mode control register (pmc82 of the pmc8 register for csi30, or pmc92 of the pmc9 register for csi31) to 1: the pin is set in the control mode (sck3n pin output). because the register set values <1> and <2> are retained, control can be performed only by <3> to <6> once they have been set. remark: n = 0, 1 ckpn dapn specification of data transmis sion/reception timing in relation to clock phase 0 0 0 1 1 note 0 1 note 1 d7 d6 d5 d4 d3 d2 d1 d0 sck3n (i/o) si3n capture so3n (output) d7 d6 d5 d4 d3 d2 d1 d0 sck3n (i/o) si3n capture so3n (output) d7 d6 d5 d4 d3 d2 d1 d0 sck3n (i/o) si3n capture so3n (output) d7 d6 d5 d4 d3 d2 d1 d0 sck3n (i/o) si3n capture so3n (output)
668 chapter 17 clocked serial interface 3 (csi3) user?s manual u16580ee2v0ud00 figure 17-3: clocked serial interface clock select register 3n (csic3n) (3/3) remarks: 1. f xx : main clock 2. n = 0, 1 cks3n2 cks3n1 cks3n0 set value (k) basic clock (f xclk )mode 0000f xx master mode 0011f xx /2 master mode 0102f xx /4 master mode 0113f xx /8 master mode 1004f xx /16 master mode 1015f xx /32 master mode 1106f xx /64 master mode 111?external clock (sck3n )slave mode
669 chapter 17 clocked serial interface 3 (csi3) user?s manual u16580ee2v0ud00 (3) receive data buffer register 3n (sirb3n, sirb3nl, sirb3nh) the sirb3n register is a 16-bit buffer register that stores receive data. it is overlayed by an 8-bit buffer register sirb3nl on the lower 8 bits, and an 8-bit buffer register sirb3nh on the higher 8 bits. by consecutively reading this register in the consecutive mode (trmdn bit of the csim3n register = 1), the received data in the csibufn register can be sequentially read while the csibufn pointer for re ading is incremented. in the single mode (trmdn bit of the csim3n register = 0), received data is read by reading the sirb3n register and it is judged that the sirb3n register has become empty. the sirb3n register is read-only, in 16-bit units. the sirb3nl and sirb3nh registers are read-only, in 8-bit units. reset input clears the sirb3n register to 0000h, and the sirb3nl and sirb3nh registers to 00h accordingly. in addition to reset input, the sirb3n as well as the sirb3nl and sirb3nh registers are initialized by clearing (to 0) the csicaen bit of the csim3n register. figure 17-4: receive data buffer register 3n (sirb3n, sirb3nl, sirb3nh) note: in consecutive mode (trmdn bit of the csim3n register = 1): undefined remark: n = 0, 1 after reset: 0000h note r address: sirb30 fffffd42h, sirb31 fffffd62h 1514131211109876543210 sirb3n sirb n15 sirb n14 sirb n13 sirb n12 sirb n11 sirb n10 sirb n9 sirb n8 sirb n7 sirb n6 sirb n5 sirb n4 sirb n3 sirb n2 sirb n1 sirb n0 (n = 0, 1) sirb3nh sirb3nl after reset: 00h note r address: sirb30l fffffd42h, sirb31l fffffd62h 76543210 sirb3nl sirbn7 sirbn6 sirbn5 sirbn4 sirbn3 sirbn2 sirbn1 sirbn0 (n = 0, 1) after reset: 00h note r address: sirb30h fffffd43h, sirb31h fffffd63h 76543210 sirb3nh sirbn15 sirbn14 sirbn13 si rbn12 sirbn11 sirbn10 sirbn9 sirbn8 (n = 0, 1)
670 chapter 17 clocked serial interface 3 (csi3) user?s manual u16580ee2v0ud00 (4) chip select csi buffer register 3n (sfcs3n, sfcs3nl) the sfcs3n register is a 16-bit buffer register that stores transmit data. it is overlayed by an 8-bit buffer register sfcs3nl on the lower 8 bits. when chip select data is written to the sfcs3n (sfcs3nl) register, the data is stored in the csibufn register following the csibufn pointer for writing. the store operation is executed after next write of the transmit data csi buffer register sfdb3n (sfdb3nl). when the data of this register is read, the value of the transmit data written last is read. the sfcs3n register can be read or written in 16-bit units. the sfcs3nl register can be read or written, in 8-bit or 1-bit units. reset input clears the sfcs3n register to ffffh, and the sfcs3nl register to ffh accordingly. figure 17-5: chip select csi buffer register 3n (sfcs3n, sfcs3nl) remark: n = 0, 1 after reset: ffffh r/w address: sfcs30 fffffd44h, sfcs31 fffffd64h 1514131211109876543210 sfcs3n sfcs n15 sfcs n14 sfcs n13 sfcs n12 sfcs n11 sfcs n10 sfcs n9 sfcs n8 sfcs n7 sfcs n6 sfcs n5 sfcs n4 sfcs n3 sfcs n2 sfcs n1 sfcs n0 (n = 0, 1) sfcs3nl after reset: ffh rw address: sfcs30l fffffd44h, sfcs31l fffffd64h 76543210 sfcs3nl sfcsn7 sfcsn6 sfcsn5 sfcsn4 sfcsn3 sfcsn2 sfcsn1 sfcsn0 (n = 0, 1)
671 chapter 17 clocked serial interface 3 (csi3) user?s manual u16580ee2v0ud00 (5) transmit data csi buffer register 3n (sfdb3n, sfdb3nl, sfdb3nh) the sfdb3n register is a 16-bit buffer register that stores transmit data. it is overlayed by an 8-bit buffer register sfdb3nl on the lower 8 bits, and an 8-bit buffer register sfdb3nh on the higher 8 bits. when transmit data is written to the sfdb3n register, the data is sequentially stored in the csibufn register while the csibufn pointer for writing is incremented. when the data of this register is read, the value of the transmit data written last is read. the sfdb3n register can be read or written in 16-bit units. the sfdb3nl and sfdb3nh registers can be read or written, in 8-bit or 1-bit units. reset input clears the sfdb3n register to 0000h, and the sfdb3nl and sfdb3nh registers to 00h accordingly. figure 17-6: transmit data csi buffer register 3n (sfdb3n, sfdb3nl, sfdb3nh) remark: n = 0, 1 after reset: 0000h r/w add ress: sfdb30 fffffd46h, sfdb31 fffffd66h 1514131211109876543210 sfdb3n sfdb n15 sfdb n14 sfdb n13 sfdb n12 sfdb n11 sfdb n10 sfdb n9 sfdb n8 sfdb n7 sfdb n6 sfdb n5 sfdb n4 sfdb n3 sfdb n2 sfdb n1 sfdb n0 (n = 0, 1) sfdb3nh sfdb3nl after reset: 00h rw address: sfdb30l fffffd46h, sfdb31l fffffd66h 76543210 sfdb3nl sfdbn7 sfdbn6 sfdbn5 sfdbn4 sfdbn3 sfdbn2 sfdbn1 sfdbn0 (n = 0, 1) after reset: 00h r/w address: sfdb30h fffffd47h, sfdb31h fffffd67h 76543210 sfdb3nh sfdbn15 sfdbn14 sfdbn13 sf dbn12 sfdbn11 sfdbn10 sfdbn9 sfdbn8 (n = 0, 1)
672 chapter 17 clocked serial interface 3 (csi3) user?s manual u16580ee2v0ud00 (6) csibuf status register 3n (sfa3n) the sfa3n register indicates the status of the csibufn register or the transfer status. this register can be read or written in 8-bit or 1-bit units (however, bits 6 to 0 can only be read. they do not change even if they are written). reset input clears the register to 20h. cautions: 1. reading the sfa3n register is prohibited when the csicaen bit of the csim3n register is cleared (0). 2. because the values of the sffuln, sfempn, csotn, and sfpn3 to sfpn0 bits may change at any time during transfer, their values during transfer may differ from the actual values. especially, use the csotn bit independently (do not use this bit in relation with the other bits). to detect the end of transfer by the sfa3n register, check to see if the sfempn bit is 1 after the data to be transferred has been written to the csibufn register. 3. if the sfa3n register is read immediately after data has been written to the sfdb3n and sfdb3nl registers, the valu es of the sffuln, sfempn, and sfpn3 to sfpn0 bits do not change in time. 4. if the sfa3n register is read before the sffuln bit is set to 1 and the 17th data is written, the csibufn overflow interrupt (intc3novf) is generated. figure 17-7: csibuf status register 3n (sfa3n)(1/3) remark: n = 0, 1 after reset: 00h r/w addr ess: sfa30 fffffd48h, sfa31 fffffd68h 76543210 sfa3n fpclrn sffuln sfempn csotn sfpn3 sfpn2 sfpn1 sfpn0 (n = 0, 1) fpclrn csibufn pointer clear operation 0 no operation 1 clear all csibufn pointers cautions: 1. this bit is always 0 when it is read. 2. if 1 is written to th e fpclrn bit in the middle of transfer, transfer is aborted. because all the csibufn pointers are cleared to 0, the remaining data in the csibufn register is ignored. if 1 is written to the fpclrn bit, be sure to read the sfa3n register to check to see if all the csibufn pointers have been correctly cleared to 0 (sffuln bit = 0, sfempn bit = 1, sfpn3 to sfpn0 bits = 0000b). nothing happens even if 0 is written to the fpclrn bit.
673 chapter 17 clocked serial interface 3 (csi3) user?s manual u16580ee2v0ud00 figure 17-7: csibuf status register 3n (sfa3n)(2/3) remark: n = 0, 1 sffuln csibufn full status flag 0 csibufn register has a vacancy 1 csibufn is full cautions: 1. this bit is cleared to 0 wh en the csicaen bit of the csim3n register is cleared to 0 and the fpclr bit is set to 1. 2. if transfer of 16 data is specifi ed in the consecutive mode (trmdn bit of the csim3n register = 1) (sfn n3 to sfnn0 bits of the sfn3n register = 0000b), the sffuln bit is set to 1 in the same way as in the single mode (trmdn bit of the csim 3n register = 0) when 16 data are in the csibufn register. if even on e of the data has been completely transferred, the sffuln bit is clea red to 0. however, this does not mean that the csibufn register has a vacancy. sfempn csibufn empty status flag 0 data is in csibufn register 1 csibufn is empty cautions: 1. this flag is cleared to 0 when the csicaen bit of the csim3n register is cleared to 0 and the fpclr bit is set to 1. 2. if the data written to the csibufn register has been transferred in the consecutive mode (trmdn bit of the csim3n register = 1), the sfemp bit is set to 1 in the same way as in the single mode (trmdn bit of the csim3n register = 0) even if receive data is stored in the csibuf register. csotn transfer status flag 0 idle status 1 transfer or transfer start processing in progress cautions: 1. this flag is cleared to 0 when the csicaen bit of the csim3n register is cleared to 0 and the fpclrn bit is set to 1, or when the ctxen and crxen bits of the csim3n register are cleared to 0. 2. this flag is set (1) from when tr ansfer is started until there is no more transfer data in the csibufn regist er in the single mode (trmdn bit of the csim3n register = 0) or unti l the specified number of data has been transferred in the consecutive mode (trmdn bit of the csim3n register = 1).
674 chapter 17 clocked serial interface 3 (csi3) user?s manual u16580ee2v0ud00 figure 17-7: csibuf status register 3n (sfa3n)(3/3) remark: n = 0, 1 sfpn3 sfpn2 sfpn1 sfpn0 csibufn pointer status 0h to fh (0 to 15) ? in the single mode (t rmdn bit of the csim3n register = 0), the ?number of transfer data remaining in csibufn register (csibufn pointer value for writing ? csibufn pointer value for sio3n loading)? can be read. ? in the consecutive mode (trmdn bit of the csim3n register = 1), the ?number of data completely transferred (value of csibufn pointer for sio3n loading/storing)? can be read. if the sfpn3 to sfpn0 bits are 0h, however, the number of transferred data is as follows, depending on the setting of the sfempn bit. when sfempn bit = 0: number of transferred data = 0 when sfempn bit = 1: number of transferred data = 16 or status before starting transfer (before writing transfer data) caution: these bits are cleared to 0 in synchronization with the operating clock when the fpclrn bit = 1. however, the values of these bits are held until the csicaen bit of the csim3n register is cleared to 0 or the fpclrn bit is set to 1.
675 chapter 17 clocked serial interface 3 (csi3) user?s manual u16580ee2v0ud00 (7) transfer data length select register 3n (csil3n) the csil3n register is used to select the transfer data length of csi3n. this register can be read or written in 8-bit or 1-bit units. reset input clears the register to 00h. caution: the csil3n register may be transferring data when the ctxen or crxen bit of the csim3n register is 1. before writing data to the csil3n register, be sure to clear the ctxen and crxen bits to 0. figure 17-8: transfer data length select register 3n (csil3n) remark: n = 0, 1 m = 0 to 3 after reset: 00h r/w add ress: csil30 fffffd49h, csil31 fffffd69h 76543210 csil3n cslvn3 cslvn2 cslvn1 cslvn0 ccln3 ccln2 ccln1 ccln0 (n = 0, 1) cslvnm chip select output (scs3nm) level setting (n = 0, 1; m = 0 to 3) 0 active level of scsnm output is low level 1 active level of scsnm output is high level ccln3 ccln2 ccln1 ccln0 transfer data length 000016 bits 10008 bits 10019 bits 101010 bits 101111 bits 110012 bits 110113 bits 111014 bits 111115 bits other than above setting prohibited caution: if a transfer data length other th an 16 bits is specified (ccln3 to ccln0 bits = 0000), an undefined value is re ad to the higher excess bits of the sirb3n and csibufn registers (see 10.3 .5 (3) data transfer direction specification function).
676 chapter 17 clocked serial interface 3 (csi3) user?s manual u16580ee2v0ud00 (8) transfer data number specification register 3n (sfn3n) the sfn3n register is used to set the number of transfer data of csi3n in the consecutive mode (trmdn bit of the csim3n register = 1). this register can be read or written in 8-bit or 1-bit units. figure 17-9: transfer data number specification register 3n (sfn3n) remark: n = 0, 1 after reset: 00h r/w addr ess: sfn30 fffffd49h, sfn31 fffffd69h 76543210 sfn3n 0 0 0 0 sfnn3 sfnn2 sfnn1 sfnn0 (n = 0, 1) sfnn3 sfnn2 sfnn1 sfnn0 number of transfer data 000016 00011 00102 00113 01004 01015 01106 01117 10008 10019 101010 101111 110012 110113 111014 111115 caution: writing data exceeding the value set by the sfnn3 to sfnn0 bits (number of csi3n transfer data) to the csib ufn register is prohibited (data is ignored even if written).
677 chapter 17 clocked serial interface 3 (csi3) user?s manual u16580ee2v0ud00 17.4 dedicated baud rate generator 3n (brg3n) the transfer clock of csi3n can be selected from the output of a dedicated baud rate generator (brg3n) or external clock (n = 0, 1). the serial clock source is specified by the csic3n register. in the master mode (cks3n2 to cks3n0 bits of the csic3n register other than 111b), brg3n is selected as the clock source. (1) transfer clock figure 17-10: transfer clock of csi3n remarks: 1. n = 0, 1 2. f xx : main clock f xclk : basic clock selected by csic3n register prescaler (1/1, 1/2, 1/4, 1/8, 1/16, 1/32, 1/64) clocked serial interface clock select register 3n (csic3n) selector brg3n (1/2, 1/4, 1/6, 1/8, 1/10, 1/12, 1/14) transfer clock f xx sck3n mdln1 mdln0 cks3n2 cks3n1 cks3n0 mdln2 f xclk
678 chapter 17 clocked serial interface 3 (csi3) user?s manual u16580ee2v0ud00 (2) baud rate the baud rate is calculated by the following expression. remarks: 1. f xx : main clock 2. k: value set by cks3n2 to cks3n0 bits of csic3n register (0 k 6) 3. n: value set by mdln2 to mdln0 bits of csic3n register (1 n 7) cautions: 1. if the cks3n2 to cks3n0 bits of the csic3n register are cleared to 000b, setting the mdln2 to mdln0 bits of the csic3n register to 001b is prohibited. 2. because the maximum transfer rate in the master mode (cks3n2 to cks3n0 bits other than 111b) is 8 mbps, do not exceed this value. example: when the main clock f xx is 64 mhz, the maximum transfer rate is set when the cks3n2 to cks3n0 bits = 000b and the mdln2 to mdln0 bits = 100b. baud rate f xx n2 k1 + () ---------------------------- - [bps] =
679 chapter 17 clocked serial interface 3 (csi3) user?s manual u16580ee2v0ud00 17.5 operation 17.5.1 operation modes remarks: 1. ctxen bit: bit 6 of csim3n register crxen bit: bit 5 of csim3n register trmdn bit: bit 4 of csim3n register dirn bit: bit 3 of csim3n register csitn bit: bit 2 of csim3n register cswen bit: bit 1 of csim3n register csmdn bit: bit 0 of csim3n register cks3n2 to cks3n0 bits: bits 2 to 0 of csic3n register 2. n = 0, 1 table 17-1: operation modes trmdn bit cks3n2 to cks3n0 bits ctxen and crxen bits dirn bit csitn bit cswen bit csmdn bit single mode master mode transmission/ reception/ transmission and reception msb/lsb first intc3n delay mode enabled/ disabled transfer wait disabled intermediate inactive level of chip select outputs disabled transfer wait enabled intermediate inactive level of chip select outputs enabled slave mode ? ? ? consecutive mode master mode intc3n delay mode enabled/ disabled transfer wait disabled intermediate inactive level of chip select outputs disabled transfer wait enabled intermediate inactive level of chip select outputs enabled slave mode ? ?
680 chapter 17 clocked serial interface 3 (csi3) user?s manual u16580ee2v0ud00 17.5.2 function of csi data buffer register (csibufn) by consecutively writing the transmit data to the sfcs3n register and the sfdb3n register from where it is transferred, the data can be stored in the csibufn register while the csibufn pointer for writing is automatically incremented (the csibufn register size is 20 bits 16) (n = 0, 1). when the chip select outputs scs3n0 to scs3n3 are used, write sfcs3n register before the sfdb3n register. however, in slave mode the chip select outputs scs3n0 to scss3n3 keep the inactive level and therefore writing to the sfcs3n register is not necessary. the condition under which transfer is to be started (sfempn bit of the sfa3n register = 0) is satisfied when data is written to the lower 8 bits of the sfdb3n register (or sfdb3nl register). if a transfer data length of 9 bits or more is specif ied (ccln3 to ccln0 bits of the csil3n register = 0000b, or 1001b to 1111b), data must be written to the sfdb3n regist er in 16-bit units or to the sfdb3nh and sfdb3nl registers, in that order, in 8-bit units. if the transfer data length is set to 8 bits (ccln3 to ccln0 bits = 1000b), data must be written to the sfdb3nl register in 8-bit units or to the sfdb3n register in 16-bit units. if data is written to the sfdb3nl register in 16-bit units, however, the higher 8 bits of the data (of the sfdb3nh register) are ignored and not transferred. the sffuln bit of the sfa3n register is set to 1 when 16 data exist in the csibufn register and outputs a csibufn overflow interrupt (intc3novf) when the sffuln bit = 1 and when the 17th transfer data is written. sixteen data exist in the csibufn register in the single mode (trmdn bit of the csim3n register = 0) when ?csibufn pointer value for writing = csibufn pointer value for sio3n loading, and sffuln bit = 1?. when the csibufn pointer for sio3n loading is incremented after completion of transfer, the csibufn register has a vacancy of one data (in the consecutive mode (trmdn bit = 1), the csibufn register does not have a vacancy even if one data has been transferred). figure 17-11: function of csi data buffer register n (csibufn) remark: n = 0, 1 csi data buffer register n (csibufn) 15 16 19 15 0 0 transfer data 0 cs data 0 cs data 1 cs data 2 cs data 3 cs data 4 transfer data 1 transfer data 2 transfer data 3 transfer data 4 sfpn3 to sfpn0 70 3 4 3 4 csibuf status register 3n (sfa3n) incremented sio3n load csibufn pointer incremented write csibufn pointer transmit data csi buffer register 3n (sfdb3n) sfdb3nh sfdb3nl 15 8 7 0 chip select csi buffer register 3n (sfcs3n) 15 8 7 0 sfcs3n3 to sfcs3n0
681 chapter 17 clocked serial interface 3 (csi3) user?s manual u16580ee2v0ud00 17.5.3 data transfer direction specification function the data transfer direction can be changed by using the dirn bit of the csim3n register (n = 0, 1). (1) msb first (dirn bit = 0) figure 17-12: data transfer direction specification (msb first) (a) transfer direction: msb first, transfer data length: 8 bits (b) writing from sfdb3n register to csibufn register (c) reading from csibufn register or sfdb3n register remark: n = 0, 1 di7 di6 di5 di4 di3 di2 di1 di0 do7 do6 do5 do4 do3 do2 do1 do0 sck3n (i/o) si3n (input) so3n (output) sfdb3n csibufn data 00h sio3n 15 8 7 0 so3n si3n sfdb3n (read value) csibufn or sirb3n undefined value data sio3n 15 8 7 0 so3n si3n
682 chapter 17 clocked serial interface 3 (csi3) user?s manual u16580ee2v0ud00 (2) lsb first (dirn bit = 1) figure 17-13: data transfer direction specification (lsb first) (a) transfer direction: lsb first, transfer data length: 8 bits (b) writing from sfdb3n register to csibufn register (c) reading from csibufn register or sfdb3n register remark: n = 0, 1 di0 di1 di2 di3 di4 di5 di6 di7 do0 do1 do2 do3 do4 do5 do6 do7 sck3n (i/o) si3n (input) so3n (output) sfdb3n csibufn data 00h sio3n 15 8 7 0 so3n si3n sfdb3n (read value) csibufn or sirb3n 00h data sio3n 15 8 7 0 so3n si3n
683 chapter 17 clocked serial interface 3 (csi3) user?s manual u16580ee2v0ud00 17.5.4 transfer data length changing function the transfer data length can be set from 8 to 16 bits in 1-bit units, by using the ccln3 to ccln0 bits of the csil3n register (n = 1, 0). figure 17-14: transfer data length changing function transfer data length: 16 bits (ccln3 to ccln0 bits of csil3n register = 0000b), transfer direction: msb first (d irn bit of csim3n register = 0) remark: n = 0, 1 di15 di14 di13 di12 di2 di1 di0 do15 do14 do13 do12 do2 do1 do0 sck3n (i/o) si3n (input) so3n (output)
684 chapter 17 clocked serial interface 3 (csi3) user?s manual u16580ee2v0ud00 17.5.5 function to select serial clock and data phase the serial clock and data phase can be changed by using the ckpn and dapn bits of the csic3n register (n = 0, 1). figure 17-15: clock timing (a) when ckpn bit = 0, dapn bit = 0 (b) when ckpn bit = 0, dapn bit = 1 (c) when ckpn bit = 1, dapn bit = 0 (d) when ckpn bit = 1, dapn bit = 1 remark: n = 0, 1 intc3n interrupt si3n capture sck3n so3n d7 d6 d5 d4 d3 d2 d1 d0 intc3n interrupt si3n capture sck3n so3n d7 d6 d5 d4 d3 d2 d1 d0 intc3n interrupt si3n capture sck3n so3n d7 d6 d5 d4 d3 d2 d1 d0 intc3n interrupt si3n capture sck3n so3n d7 d6 d5 d4 d3 d2 d1 d0
685 chapter 17 clocked serial interface 3 (csi3) user?s manual u16580ee2v0ud00 17.5.6 master mode the master mode is set and data is transferred with the transfer clock output to the sck3n pin when the cks3n2 to cks3n0 bits of the csic3n register are set to a value other than 111b (sck3n pin input is invalid) (n = 0, 1). the default output level of the sck3n pin is high when the ckpn bit of the csic3n register is 0, and low when the ckpn bit is 1. in master mode the chip select outputs (scs3n0 to scs3n3) are effective. figure 17-16: master mode ckpn and dapn bits of csic3n register = 00b, active level of cs outputs: low level (cslvn3 to cslvn0 bits of csil3n register = 0000b) transfer data length: 8 bits (ccln3 to ccln0 bits of csil3n register = 1000b) remark: n = 0, 1 di7 di6 di5 di4 di3 di2 di1 di0 do7 do6 do5 do4 do3 do2 do1 do0 sck3n (output) si3n (input) so3n (output) scs3n0 to scs3n3 (output) cs data
686 chapter 17 clocked serial interface 3 (csi3) user?s manual u16580ee2v0ud00 17.5.7 slave mode the slave mode is set when the cks3n2 to cks3n0 bits of the csic3n register are set to 111b, and data is transferred with the transfer clock input to the sck3n pin (in the slave mode, it is recommended to set the mdln2 to mdln0 bits of the csic3n register to 000b and set the brgn stop mode) (n = 0, 1). the chip select outputs (scs3n0 to scs3n3) are ineffective in slave mode, the output levels are fixed to inactive level (chip select outputs are effective in master mode only). figure 17-17: slave mode ckpn and dapn bits of csic3n register = 00b, active level of cs outputs: low level (cslvn3 to cslvn0 bits of csil3n register = 0000b) transfer data length: 8 bits (ccln3 to ccln0 bits of csil3n register = 1000b) the conditions under which data can be transferred in the slave mode are listed in the table below. remarks: 1. ctxen bit: bit 6 of csim3n register crxen bit: bit 5 of csim3n register sfempn bit: bit 5 of sfa3n register 2. n = 0, 1 table 17-2: conditions under which data can be transferred in slave mode transfer mode ctxen bit crxen bit csibufn register sirb3n register and sio3n register single mode transmission mode 1 0 data is in csibufn register (sfempn bit = 0). ? reception mode 0 1 dummy data is in csibufn register (sfempn bit = 0). sirb3n register or sio3n register is empty. transmission/ reception mode 1 1 data is in csibufn register (sfempn bit = 0). consecutive mode transmission mode 1 0 data is in csibufn register (sfempn bit = 0). ? reception mode 0 1 dummy data is in csibufn register (sfempn bit = 0). ? transmission/ reception mode 1 1 data is in csibufn register (sfempn bit = 0). ? di7 di6 di5 di4 di3 di2 di1 di0 do7 do6 do5 do4 do3 do2 do1 do0 sck3n (input) si3n (input) so3n (output) scs3n0 to scs3n3 (output) h (inactive level)
687 chapter 17 clocked serial interface 3 (csi3) user?s manual u16580ee2v0ud00 17.5.8 transfer clock selection function in the master mode (cks3n2 to cks3n0 bits of the csic3n register other than 111b), the bit transfer rate can be selected by setting the cks3n2 to cks3n0 and mdln2 to mdln0 bits of the csic3n register (ref. to 17.3 (2) clocked serial interface clock select registers 30, 31 (csic30, csic31) ). 17.5.9 single mode the single mode is set when the trmdn bit of the csim3n register is 0 (n = 0, 1). in this mode, transfer is started when the ctxen bit or crxen bit is set to 1 and when data is in the csibufn register (sfempn bit = 0 in the sfa3n register). if no data is in the csibufn register (sfempn bit = 1), transfer is kept waiting until a given start condition is satisfied. when data is written to the csibufn register while the ctxen or crxen bit is 1, the csotn bit of the sfa3n register (transfer status flag) is set to 1, and the chip select data (cs data) corresponding to sio3n load csibufn pointer is tran sferred to the chip select output buffer. however, in slave mode (cks3n2 to cks3n0 bits of the csic3n register = 111b) the chip select outputs (scs3n0 to scs3n3) keep always the inactive level. if transfer is not in the wait status, the transfer data indicated by the sio3n load csibufn pointer is loaded from the csibufn register to the sio3n register, and transfer processing is started. if the sirb3n register is empty when one data has been transferred in the reception mode or transmission/reception mode, the received data is stored from the sio3n register to the sirb3n register, the transmission/reception completion interrupt (intc3n) is output, and the sio3n load csibufn pointer is incremented. if the sirb3n register is not empty, the next transfer processing is started. however, storing the receive data in the sirb3n register, outputting the intc3n interrupt, and incrementing the sio3n load csibufn pointer are held pending, until the previously received data is read from the sirb3n register and the sirb3n register becomes empty. in the transmission mode, the intc3n interrupt is output and the sio3n load pointer is incremented when transfer processing of one data has been completed (the sirb3n register is always empty because no data is stored from the sio3n register to the sirb3n register). in all modes (transmission, reception, and transmission/reception modes), if the csibufn register is empty (write csibufn pointer value = sio3n load csibufn pointer value) when transfer processing of one data has been completed, the csotn bit is cleared to 0. the value of the ?number of remaining data in the csibufn register (write csibufn pointer ? sio3n load pointer)? can always be read from the sfpn3 to sfpn0 bits of the sfa3n register. caution: when writing data to the sfdb3n register, be sure to confirm that the sffuln bit of the sfa3n register is 0. even if data is written to this register when sffuln bit is 1, the csibufn overflow interrupt (intc3novf) is output, and the written data is ignored.
688 chapter 17 clocked serial interface 3 (csi3) user?s manual u16580ee2v0ud00 figure 17-18: single mode note: transfer of cs data will be perf ormed in master mode only. remark: n = 0, 1 sio3n sirb3n so3n si3n csi data buffer register n (csibufn) 15 16 19 15 0 0 transfer data 0 cs data 0 cs data 1 cs data 2 cs data 3 cs data 4 note transfer data 1 transfer data 2 transfer data 3 transfer data 4 sfpn3 to sfpn0 70 3 4 3 4 csibuf status register 3n (sfa3n) incremented sio3n load csibufn pointer incremented write csibufn pointer transmit data csi buffer register 3n (sfdb3n) sfdb3nh sfdb3nl 15 8 7 0 chip select csi buffer register 3n (sfcs3n) 15 8 7 0 difference sfcs3n3 to sfcs3n0 scs3n0 scs3n1 scs3n2 scs3n3 chip select output buffer
689 chapter 17 clocked serial interface 3 (csi3) user?s manual u16580ee2v0ud00 17.5.10 consecutive mode the consecutive mode is set when the trmdn bi t of the csim3n register is 1 (n = 0, 1). in this mode, transfer is started when the ctxen bi t or crxen bit is 1 and when data is in the csibufn register (sfempn bit of the sfa3n register = 0). at this time, set the number of transfer data in advance by using the sfnn3 to sfnn0 bits of the sfn3n register. seventeen or more transfer data cannot be set. if 17 or more transfer data are written to the csibufn register, the excess data are ignored and not transferred. do not write data exceeding the number of transfer data specified by the sfnn3 to sfnn0 bits of the sfn3n register to the csibufn register. if no data is in the csibufn register (sfempn bit = 1), transfer is kept waiting until a given start condition is satisfied. if data is written to the csibufn register when th e ctxen or crxen bit is 1, the csotn bit (transfer status flag) of the sfa3n register is set to 1 and the chip select data (cs data) according to the sio3n load/store csibufn pointer is tran sferred to the chip select output buffer. however, in slave mode (cks3n2 to cks3n0 bits of the csic3n register = 111b) the chip select outputs (scs3n0 to scs3n3) keep always the inactive level. if transfer is not in the wait status, the transfer data indicated by the sio3n load/store csibufn pointer is loaded from the csibufn register to sio3n register. then transfer processing is started. when transfer processing of one data is completed in the reception mode or transmission/reception mode, the received data is overwritten from the sio3n register to the transfer data in the csibufn register indicated by the sio3n load/store csibufn pointer, and then the pointer is incremented. by consecutively reading the transfer data from the si rb3n register after all data in the csibufn register have been transferred (when the intc3n interrupt has occurred), the receive data can be sequentially read while the read csibuf n pointer is incremented. in the transmission mode, the sio3n load/store csibufn pointer is incremented when transfer processing of one data has been completed. in all modes (transmission, reception, and transmission/reception modes), when data has been transferred by the value set by the sfnn3 to sfnn0 bits of the sfn3n register, the csotn bit is cleared to 0 and the transmission/reception completion interrupt (intc3n) is output. to transfer the next data, be sure to write 1 to the fpclrn bit of the sfa3n register and clear all the csibufn pointers to 0. the ?number of transferred data (sio3n load/store csibufn pointer value)? can always be read from the sfpn3 to sfpn0 bits of the sfa3n register. caution: the sfa3n register is in the same status when transfer data is written (before start of transfer) after the csibufn pointer is cleared (fpclrn bit of the sfa3n register = 1) and when 16 data have been transferred (sffuln bit = 0, sfempn bit = 1, sfpn3 to sfpn0 bits = 0000b).
690 chapter 17 clocked serial interface 3 (csi3) user?s manual u16580ee2v0ud00 figure 17-19: consecutive mode note: transfer of cs data will be perf ormed in master mode only. remark: n = 0, 1 sio3n sirb3n so3n si3n csi data buffer register n (csibufn) 15 16 19 15 0 0 transfer data 0 cs data 0 cs data 1 cs data 2 cs data 3 note transfer data 1 transfer data 2 transfer data 3 sfpn3 to sfpn0 70 3 4 3 4 csibuf status register 3n (sfa3n) transmit data csi buffer register 3n (sfdb3n) sfdb3nh sfdb3nl 15 8 7 0 chip select csi buffer register 3n (sfcs3n) 15 8 7 0 sfcs3n3 to sfcs3n0 scs3n0 scs3n1 scs3n2 scs3n3 chip select output buffer incremented read csibufn pointer incremented sio3n load/store csibufn pointer incremented write csibufn pointer
691 chapter 17 clocked serial interface 3 (csi3) user?s manual u16580ee2v0ud00 17.5.11 transmission mode the transmission mode is set when the ctxen bit of the csim3n register is set to 1 and the crxen bit is cleared to 0. in this mode, transmission is started by a trigger that writes transmit data to the sfdb3n register or sets the ctxen bit to 1 when transmit data is in the sfdb3n register (n = 0, 1). even in the single mode (trmdn bit of the csim3n register = 0), whether the sirb3n or sio3n register is empty has nothing to do with starting transmission. the value input to the si3n pin during transmission is latched in the shift register (sio3n) but is not transferred to the sirb3n and csibufn registers at the end of transmission. the transmission/reception completion interrupt (intc3n) occurs immediately after data is sent out from the sio3n register. 17.5.12 reception mode the reception mode is set when the ctxen bit of the csim3n register is cleared to 0 and crxen bit is set to 1. in this mode, reception is started by using the processing of writing dummy data to the sfdb3n register as a trigger (n = 0, 1). in the single mode (trmdn bit of the csim3n register = 0), however, the condition of starting reception includes that the sirb3n or sio3n register is empty. (if reception to the sio3n register is completed when th e previously received data is held in the sirb3n register without being read, the previously received data is read from the sirb3n register and the wait status continues until the sirb3n register becomes empty.) the so3n pin outputs a low level. the transmission/reception completion interrupt (intc3n) occurs immediately after receive data is transferred from the sio3n register to the sirb3n register. 17.5.13 transmission/reception mode the transmission/reception mode is set when both the ctxen and crxen bits of the csim3n register are set to 1. in this mode, transmission/reception is started by using the processing to write transmit data to the sfdb3n register as a trigger (n = 0, 1). in the single mode (trmdn bit of the csim3n register = 0), however, the condition of starting transmission/reception includes that the sirb3n or sio3n register is empty. (if reception to the sio3n register is completed when the previously received data is held in the sirb3n register without being read, the previously received data is read from the sirb3n register and the wait status continues until the sirb3n register becomes empty.)
692 chapter 17 clocked serial interface 3 (csi3) user?s manual u16580ee2v0ud00 17.5.14 delay control of transmission/r eception completion interrupt (intc3n) in the master mode (cks3n2 to cks3n0 bits of the csic3n register other than 111b), occurrence of the transmission/reception completion interrupt (intc3n) can be delayed by half a clock (1/2 serial clock), depending on the setting of the csitn bit of the csim3n register (csitn bit = 1). the csitn bit is valid only in the master mode. in the slave mode (cks3n2 to cks3n0 bits = 111b), setting the csitn bit to 1 is prohibited (even if set, the intc3n interrupt is not affected). caution: if the csitn bit of the csim3n register is set to 1 in the consecutive mode (trmdn bit of the csim3n register = 1), the intc3n interrupt is not output at the end of data other than the last data set by the sfnn3 to sfnn0 bits of the sfn3n register, but a delay of half a clock can be inserted between each data transfer. figure 17-20: delay control of transmission/ reception completion interrupt (intc3n): csitn bit of the csim3n register = 1, cswen bit of the csim3n register = 0, ckpn and dapn bits of the csic3n register = 00b, transfer data length: 8 bits (ccln3 to ccln0 bits of the csil3n register = 1000b) remark: n = 0, 1 di7 di7 di6 di5 di4 di3 di2 di1 di0 delay do7 do6 do5 do4 do3 do2 do1 do0 do7 sck3n (output) si3n (input) so3n (output) intc3n interrupt delay
693 chapter 17 clocked serial interface 3 (csi3) user?s manual u16580ee2v0ud00 17.5.15 transfer wait function in the master mode (cks3n2 to cks3n0 bits of the csic3n register other than 111b), starting transfer can be delayed by one clock, depending on the setting of the cswen bit of the csim3n register (cswen bit = 1). the cswen bit is valid only in the master mode. in the slave mode (cks3n2 to cks3n0 bits = 111b), setting the cswen bit to 1 is prohibited (even if set, transfer wait is not inserted). when the transfer wait function is enabled (cswen bit = 1), the chip select outputs can be during transfer wait (cswe bit = 1) the chip select outputs (scs3n0 to scs3n3) can be configured for an intermediate inactive level output of half a clock period by setting the csmdn bit of the csim3n register to 1. figure 17-21: transfer wait function (1/3) (a) transfer wait enabled (cswen bit = 1), intc3n delay disabled (csitn bit = 0), ckpn and dapn bits = 00b, transfer data length: 8 bits (ccln3 to ccln0 bits = 1000b) intermediate inactive chip select level disabled (csmdn = 0) remark: n = 0, 1 di7 di6 di5 do7 cs data cs data do6 do5 sck3n (output) si3n (input) so3n (output) intc3n interrupt scs3n0 to scs3n3 (outputs) di7 di1 di0 wait do1 do0 do7
694 chapter 17 clocked serial interface 3 (csi3) user?s manual u16580ee2v0ud00 figure 17-21: transfer wait function (2/3) (b) transfer wait enabled (cswen bit = 1), intc3n delay disabled (csitn bit = 0), ckpn and dapn bits = 00b, transfer data length: 8 bits (ccln3 to ccln0 bits = 1000b), intermediate inactive chip select level enabled (csmdn = 1) remarks: 1. when the csibufn register is empty at the time of <1>, the chip select pins output an inactive level and maintain it. when the csibufn register is not empty at the time of <1>, the chip select pins output an inactive level up to the time of <2>, and output subsequently the succeeding chip select data moreover, in single mode (trmdn bit of the csim3n register = 0) the chip select pins output an inactive level from the time <1> and held it pending until the previously receive data is read from the sirb3n register and the sirb3n register becomes empty. 2. n = 0, 1 di7 di6 di5 do7 cs data <1> <2> cs data do6 do5 sck3n (output) si3n (input) so3n (output) intc3n interrupt scs3n0 to scs3n3 (outputs) di7 di1 di0 wait do1 do0 do7
695 chapter 17 clocked serial interface 3 (csi3) user?s manual u16580ee2v0ud00 figure 17-21: transfer wait function (3/3) (c) transfer wait enabled (cswen bit = 1), intc3n delay enabled (csitn bit = 1), ckpn and dapn bits = 00b, transfer data length: 8 bits (ccln3 to ccln0 bits = 1000b), intermediate inactive chip select level disabled (csmdn = 0) remark: n = 0, 1 di7 di6 di5 do7 do6 do5 sck3n (output) si3n (input) so3n (output) intc3n interrupt di7 di1 di0 wait delay do1 do0 do7 delay cs data cs data scs3n0 to scs3n3 (outputs)
696 chapter 17 clocked serial interface 3 (csi3) user?s manual u16580ee2v0ud00 17.5.16 output pins (1) sck3n pin the sck3n pin outputs a high level when both the ctxen and crxen bits of the csim3n register are 0 (n = 0, 1). in the master mode (cks3n2 to cks3n0 bits = other than 111 in the csic3n register), this pin outputs the default level when the fpclrn bit of the sfa3n register is set to 1. in the slave mode (cks3n2 to cks3n0 bits = 111 in the csic3n register), the default output level of the sck3n pin is fixed to the high level. table 17-3: default output level of sck3n pin note: default value after reset, or value when csicaen bit of the csim3n register is cleared to 0. remarks: 1. the output of the sck3n pin changes if the ckpn bit is rewritten in the master mode. 2. n = 0, 1 (2) so3n pin the so3n pin outputs a low level when both the ctxen and crxen bits of the csim3n register are 0 (n = 0, 1). this pin outputs a low level when the fpclrn bit of the sfa3n register is set to 1 (the previous value is retained only in the slave mode (cks3n2 to cks3n0 bits of the csic3n register = 111b) and when the dapn bit of the csic3n register is 0). table 17-4: default output level of so3n pin note: default value after reset, or value when csicaen bit of the csim3n register is cleared to 0 remark: n = 0, 1 ckpn bit cks3n2 to cks3n0 bits default output level of sck3n pin 0 111b (slave mode) high level note other than 111b (master mode) high level 1 111b (slave mode) high level other than 111b (master mode) low level default output level of so3n pin low level note
697 chapter 17 clocked serial interface 3 (csi3) user?s manual u16580ee2v0ud00 (3) scs3n0 to scs3n3 pins the scs3n0 to scs3n3 pins output the default level when both the ctxen and crxen bits of the csim3n register are 0, or when the csicaen bit of the csim3n register is cleared to 0 (n = 0, 1). these pins output the default level when the fpclrn bit of the sfa3n register is set to 1. in slave mode these pins output always the default level (inactive level). table 17-5: default output level of scs3n0 to scs3n3 pins note: default value after reset. remark: n = 0, 1 17.5.17 csibufn overflow interrupt signal (intc3novf) the intc3novf interrupt is output when 16 data exist in the csibufn register and when the 17th data is written (to the sfdb3n or sfdb3nl register). the 17th data is not written but ignored. in the single mode (trmdn bit of the csim3n register = 0), 16 data exist in the csibufn register when ?write csibufn pointer value = sio3n load csibufn pointer value? and sffuln bit of the sfa3n register = 1. when transfer is completed and the sio3n load csibufn pointer is incremented, the csibufn register has one vacancy (the csibufn register has no vacancy even when transfer of one data has been completed in the consecutive mode (trmdn bit = 1)). cslvn bit default output level of scs3n0 to scs3n3 pins 0 high level note 1low level
698 chapter 17 clocked serial interface 3 (csi3) user?s manual u16580ee2v0ud00 17.6 operating procedures 17.6.1 single mode (master mode, transmission mode) figure 17-22: single mode (master mode, transmission mode) msb first (dir bit = 0), ckp bit = 0, dap bit = 0 transfer data length: 8 bits (ccln3 to ccln0 bits = 1000b) intc3n interrupt not delayed (csit bit = 0), transfer wait: disabled (cswe bit = 0), chip select active level: l-level (cslvn3 to cslvn0 bits = 0000b) note: during this period a reception from the slave is put on hold until at least one transmit data has been loaded to the csibufn register by writing the sfdb3n register (sfempn flag of sfa3n register = 0) in order to start the transfer. remark: n = 0, 1 ctxen bit sfempn flag sfdb3n register write csibuf3n [0] 55h aah cch cs0 <1> <2> <3> <4> cs1 cs2 csibuf3n [1] csibuf3n [2] sck3n pin so3n pin csotn flag intc3n signal scs3n0 to scs3n3 pins <5> <6> <6> <7> note <6> h (inactive) 111 1 1 111 0 00 000 11 0 11 00 00 0h 0h 0h 1h 1h 1h 2h sfp3 to sfp0 bits 0
699 chapter 17 clocked serial interface 3 (csi3) user?s manual u16580ee2v0ud00 <1> when the csicaen bit of the csim3n register is set to 1, operating clock supply is enabled. <2> specify the transfer mode by setting the csic3n and csil3n registers. <3> write 1 to the fpclrn bit of the sfa3n register to clear all the csibufn pointers to 0. <4> confirm that the sffuln bit = 0, sfempn bit = 1, and sfpn3 to sfpn0 bits = 0000 in the sfa3n register. <5> specify the transfer mode by using the trmdn, dirn, csitn, cswen, and csmdn bits of the csim3n register and, at the same time, enable transmission by setting the ctxen bit to 1. <6> confirm that the sffuln bit of the sfa3n register is 0, and then write first cs data to the sfcs3n register and subsequently write transfer data to the sfdb3n register. if it is clearly known that the sffuln bit is 0 be cause transfer data is written to that bit by the interrupt servicing routine of intc3n, it is not always necessary to confirm that the sffuln bit is 0. <7> confirm that the intc3n interrupt has occurred and the sfempn bit of the sfa3n register is 1, and disable transmission by clearing the ctxen bit of the csim3n register to 0 (end of transmission). remarks: 1. to execute a further transfer, repeat <6> before <7>. 2. n = 0, 1
700 chapter 17 clocked serial interface 3 (csi3) user?s manual u16580ee2v0ud00 17.6.2 single mode (master mode, reception mode) figure 17-23: single mode (master mode, reception mode) msb first (dir bit = 0), ckp bit = 1, dap bit = 1 transfer data length: 8 bits (ccln3 to ccln0 bits = 1000b) intc3n interrupt not delayed (csit bit = 0), transfer wait: disabled (cswe bit = 0), chip select active level: l-level (cslvn3 to cslvn0 bits = 0000b) notes: 1. while the sirb3n register is full a new transfer start of reception from the slave is put on hold until the sirb3n register is read. 2. during this period a reception from the slave is put on hold until at least one dummy transmit data has been loaded to the csibufn register by writing the sfdb3n register (sfempn flag of sfa3n register = 0) in order to start the transfer. remark: n = 0, 1 crxen bit sfdb3n register write csibuf3n [0] dummy 55h cs0 cs1 cs2 aah csibuf3n [1] csibuf3n [2] sck3n pin si3n pin csotn flag intc3n signal sirb3n register sirb3n register read scs3n0 to scs3n3 pins h (inactive) cch <1> <2> <3> <4> <5> <6> <6> <7> <7> <7> note 2 note 1 <6> <8> 111 1 1 111 0 00 000 11 0 11 00 00 dummy dummy 0h 0h 0h 1h 1h 1h 2h sfempn flag sfp3 to sfp0 bits 0
701 chapter 17 clocked serial interface 3 (csi3) user?s manual u16580ee2v0ud00 <1> when the csicaen bit of the csim3n register is set to 1, operating clock supply is enabled. <2> specify the transfer mode by setting the csic3n and csil3n registers. <3> write 1 to the fpclrn bit of the sfa3n register to clear all the csibufn pointers to 0. <4> confirm that the sffuln bit = 0, sfempn bit = 1, and sfpn3 to sfpn0 bits = 0000 in the sfa3n register. <5> specify the transfer mode by using the trmdn, dirn, csitn, cswen, and csmdn bits of the csim3n register and, at the same time, enable reception by setting the crxen bit to 1. <6> confirm that the sffuln bit of the sfa3n register is 0, and then write first cs data to the sfcs3n register and subsequently write dummy transfer data to the sfdb3n register (reception start trigger). if it is clearly known that the sffuln bit is 0 because dummy transfer data is written to that bit by the interrupt servicing routine of intc3n, it is not always necessary to confirm that the sffuln bit is 0. <7> confirm that the intc3n interrupt has occurred, and then read the sirb3n register. <8> confirm that the intc3n interrupt has occurred and the sfempn bit is 1, and disable reception by clearing the crxen bit of the csim3n register to 0 (end of reception). remarks: 1. to execute a further transfer, repeat <6> and <7> before <8>. perform writing dummy transfer data in <6> every time transfer is executed. 2. the so3n pin output is fixed to low level (default value). 3. n = 0, 1
702 chapter 17 clocked serial interface 3 (csi3) user?s manual u16580ee2v0ud00 17.6.3 single mode (master mode, transmission/reception mode) figure 17-24: single mode (master mode, transmission/reception mode) msb first (dir bit = 0), ckp bit = 1, dap bit = 0 transfer data length: 8 bits (ccln3 to ccln0 bits = 1000b) intc3n interrupt not delayed (csit bit = 0), transfer wait: disabled (cswe bit = 0), chip select active level: l-level (cslvn3 to cslvn0 bits = 0000b) notes: 1. while the sirb3n register is full a new transfer start of reception from the slave is put on hold until the sirb3n register is read. 2. during this period a reception from the slave is put on hold until at least one transmit data has been loaded to the csibufn register by writing the sfdb3n register (sfempn flag of sfa3n register = 0) in order to start the transfer. remark: n = 0, 1 ctxen bit, crxen bit sfdb3n register write csibuf3n [0] 55h aah 33h cch cs0 cs1 cs2 96h csibuf3n [1] csibuf3n [2] sck3n pin so3n pin si3n pin csotn flag intc3n signal sirb3n register sirb3n register read scs3n0 to scs3n3 pins 111 1 11 111 1111111 111 0 00 0 00 00 000 00 000 h (inactive) 00 00 11 0 0 0 1 0 1 1 99h <1> <2> <3> <4> <5> <6> <6> <7> <7> <7> <6> <8> 0h 0h 0h 1h 1h 1h 2h sfempn flag sfp3 to sfp0 bits note 2 note 1
703 chapter 17 clocked serial interface 3 (csi3) user?s manual u16580ee2v0ud00 <1> when the csicaen bit of the csim3n register is set to 1, operating clock supply is enabled. <2> specify the transfer mode by setting the csic3n and csil3n registers. <3> write 1 to the fpclrn bit of the sfa3n register to clear all the csibufn pointers to 0. <4> confirm that the sffuln bit = 0, sfempn bit = 1, and sfpn3 to sfpn0 bits = 0000 in the sfa3n register. <5> specify the transfer mode by using the trmdn, dirn, csitn, cswen, and csmdn bits of the csim3n register and, at the same time, enable transmission/reception by setting the ctxen and crxen bits to 1. <6> confirm that the sffuln bit of the sfa3n register is 0, and then write first cs data to the sfcs3n register and subsequently write transfer data to the sfdb3n register. if it is clearly known that the sffuln bit is 0 be cause transfer data is written to that bit by the interrupt servicing routine of intc3n, it is not always necessary to confirm that the sffuln bit is 0. <7> confirm that the intc3n interrupt has occurred, and then read the sirb3n register. <8> confirm that the intc3n interrupt has occurred and the sfempn bit is 1, and disable transmission/reception by clearing the ctxen and crxen bits of the csim3n register to 0 (end of transmission/reception). remarks: 1. to execute a further transfer, repeat <6> before <7>. 2. n = 0, 1
704 chapter 17 clocked serial interface 3 (csi3) user?s manual u16580ee2v0ud00 17.6.4 single mode (slave mode, transmission mode) figure 17-25: single mode (slave mode, transmission mode) msb first (dir bit = 0), ckp bit = 1, dap bit = 1 transfer data length: 8 bits (ccln3 to ccln0 bits = 1000b) intc3n interrupt not delayed (csit bit = 0), transfer wait: disabled (cswe bit = 0), chip select active level: l-level (cslvn3 to cslvn0 bits = 0000b) note: during this period a transmission to the master will be ig nored until at least one transmit data is loaded to the csibufn register by writing the sfdb3n register (sfempn flag of sfa3n register = 0). remark: n = 0, 1 ctxen bit sfdb3n register write csibuf3n [0] 55h aah <1> <2> <3> <4> csibuf3n [1] csibuf3n [2] sck3n pin so3n pin csotn flag intc3n signal scs3n0 to scs3n3 pins <5> <6> <6> <7> <6> h (inactive level) 111 1 1 111 0 00 000 11 0 11 00 00 0h 0h 0h 1h 1h 1h 2h sfempn flag sfp3 to sfp0 bits cch note note 0
705 chapter 17 clocked serial interface 3 (csi3) user?s manual u16580ee2v0ud00 <1> when the csicaen bit of the csim3n register is set to 1, operating clock supply is enabled. <2> specify the transfer mode by setting the csic3n and csil3n registers. <3> write 1 to the fpclrn bit of the sfa3n register to clear all the csibufn pointers to 0. <4> confirm that the sffuln bit = 0, sfempn bit = 1, and sfpn3 to sfpn0 bits = 0000 in the sfa3n register. <5> specify the transfer mode by using the trmdn, dirn, csitn, cswen, and csmdn bits of the csim3n register and, at the same time, enable transmission by setting the ctxen bit to 1. <6> confirm that the sffuln bit of the sfa3n register is 0, and then write transfer data to the sfdb3n register. since the chip select outputs (scs3n0 to scs3n3) are ineffective in the slave mode and always output the inactive level, writing of cs data to the sfcs3n register is not necessary. if it is clearly known that the sffuln bit is 0 be cause transfer data is written to that bit by the interrupt servicing routine of intc3n, it is not always necessary to confirm that the sffuln bit is 0. <7> confirm that the intc3n interrupt has occurred and the sfempn bit is 1, and disable transmission by clearing the ctxen bit of the csim3n register to 0 (end of transmission). remarks: 1. to execute a further transfer, repeat <6> before <7>. 2. n = 0, 1
706 chapter 17 clocked serial interface 3 (csi3) user?s manual u16580ee2v0ud00 17.6.5 single mode (slave mode, reception mode) figure 17-26: single mode (slave mode, reception mode) msb first (dir bit = 0), ckp bit = 0, dap bit = 0 transfer data length: 8 bits (ccln3 to ccln0 bits = 1000b) intc3n interrupt not delayed (csit bit = 0), transfer wait: disabled (cswe bit = 0), chip select active level: l-level (cslvn3 to cslvn0 bits = 0000b) notes: 1. during this period a transmission/reception from the master will be igno red until at least one dummy transmit data is loaded to the csibufn register by writing the sfdb3n register (sfempn flag of sfa3n register = 0). 2. while the sirb3n register is full a new rece ption from the master will be ignored until the sirb3n register is read. remark: n = 0, 1 crxen bit sfdb3n register write csibuf3n [0] dummy 55h aah csibuf3n [1] csibuf3n [2] sck3n pin si3n pin csotn flag intc3n signal sirb3n register sirb3n register read scs3n0 to scs3n3 pins h (inactive level) cch <1> <2> <3> <4> <5> <6> <6> <7> <7> <7><6> <8> 111 1 1 111 0 00 000 11 0 11 00 00 dummy dummy 0h 0h 0h 1h 1h 1h 2h sfempn flag sfp3 to sfp0 bits note 1 note 2 note 1 0
707 chapter 17 clocked serial interface 3 (csi3) user?s manual u16580ee2v0ud00 <1> when the csicaen bit of the csim3n register is set to 1, operating clock supply is enabled. <2> specify the transfer mode by setting the csic3n and csil3n registers. <3> write 1 to the fpclrn bit of the sfa3n register to clear all the csibufn pointers to 0. <4> confirm that the sffuln bit = 0, sfempn bit = 1, and sfpn3 to sfpn0 bits = 0000 in the sfa3n register. <5> specify the transfer mode by using the trmdn, dirn, csitn, cswen, and csmdn bits of the csim3n register and, at the same time, enable reception by setting the crxen bit to 1. <6> confirm that the sffuln bit of the sfa3n register is 0, and then write dummy transfer data to the sfdb3n register (reception start trigger). since the chip select outputs (scs3n0 to scs3n3) are ineffective in the slave mode and always output the inactive level, writing of cs data to the sfcs3n register is not necessary. if it is clearly known that the sffuln bit is 0 because dummy transfer data is written to that bit by the interrupt servicing routine of intc3n, it is not always necessary to confirm that the sffuln bit is 0. <7> confirm that the intc3n interrupt has occurred, and then read the sirb3n register. <8> confirm that the intc3n interrupt has occurred and the sfempn bit is 1, and disable reception by clearing the crxen bit of the csim3n register to 0 (end of reception). remarks: 1. to execute a further transfer, repeat <6> and <7> before <8>. perform writing dummy transfer data in <6> every time transfer is executed. 2. the so3n pin output is fixed to low level (default value). 3. n = 0, 1
708 chapter 17 clocked serial interface 3 (csi3) user?s manual u16580ee2v0ud00 17.6.6 single mode (slave mode, transmission/reception mode) figure 17-27: single mode (slave mode, transmission/reception mode) msb first (dir bit = 0), ckp bit = 0, dap bit = 1 transfer data length: 8 bits (ccln3 to ccln0 bits = 1000b) intc3n interrupt not delayed (csit bit = 0), transfer wait: disabled (cswe bit = 0), chip select active level: l-level (cslvn3 to cslvn0 bits = 0000b) notes: 1. during this period a transmission/reception from the master will be igno red until at least one transmit data is loaded to the csibufn register by writing the sfdb3n register (sfempn flag of sfa3n register = 0). 2. while the sirb3n register is full a new tr ansmission/reception from the master will be ignored until the sirb3n register is read. remark: n = 0, 1 ctxen bit, crxen bit sfdb3n register write csibuf3n [0] 55h aah cch 96h csibuf3n [1] csibuf3n [2] sck3n pin so3n pin si3n pin csotn flag intc3n signal sirb3n register sirb3n register read scs3n0 to scs3n3 pins 111 1 11 111 1111111 111 0 00 0 00 00 000 00 000 h (inactive level) 00 00 11 0 0 0 1 0 1 1 99h <1> <2> <3> <4> <5> <6> <6> <7> <7> <7> <6> <8> 0h 0h 0h 1h 1h 1h 2h sfempn flag sfp3 to sfp0 bits note 1 note 2 note 1 33h
709 chapter 17 clocked serial interface 3 (csi3) user?s manual u16580ee2v0ud00 <1> when the csicaen bit of the csim3n register is set to 1, operating clock supply is enabled. <2> specify the transfer mode by setting the csic3n and csil3n registers. <3> write 1 to the fpclrn bit of the sfa3n register to clear all the csibufn pointers to 0. <4> confirm that the sffuln bit = 0, sfempn bit = 1, and sfpn3 to sfpn0 bits = 0000 in the sfa3n register. <5> specify the transfer mode by using the trmdn, dirn, csitn, cswen, and csmdn bits of the csim3n register and, at the same time, enable transmission/reception by setting the ctxen and crxen bits to 1. <6> confirm that the sffuln bit of the sfa3n register is 0, and then write transfer data to the sfdb3n register. since the chip select outputs (scs3n0 to scs3n3) are ineffective in the slave mode and always output the inactive level, writing of cs data to the sfcs3n register is not necessary. if it is clearly known that the sffuln bit is 0 be cause transfer data is written to that bit by the interrupt servicing routine of intc3n, it is not always necessary to confirm that the sffuln bit is 0. <7> confirm that the intc3n interrupt has occurred, and then read the sirb3n register. <8> confirm that the intc3n interrupt has occurred and the sfempn bit is 1, and disable transmission/reception by clearing the ctxen and crxen bits of the csim3n register to 0 (end of transmission/reception). remarks: 1. to execute a further transfer, repeat <6> and <7> before <8>. 2. n = 0, 1
710 chapter 17 clocked serial interface 3 (csi3) user?s manual u16580ee2v0ud00 17.6.7 consecutive mode (master mode, transmission mode) figure 17-28: consecutive mode (master mode, transmission mode) msb first (dir bit = 0), ckp bit = 0, dap bit = 0 transfer data length: 8 bits (ccln3 to ccln0 bits = 1000b) intc3n interrupt not delayed (csit bit = 0), transfer wait: disabled (cswe bit = 0), chip select active level: l-level (cslvn3 to cslvn0 bits = 0000b) note: during this period a reception from the slave is put on hold until at least one transmit data has been loaded to the csibufn register by writing the sfdb3n register (sfempn flag of sfa3n register = 0) in order to start the transfer. ctxen bit sfdb3n register write csibuf3n [0] 55h aah cch cs0 cs1 cs2 csibuf3n [1] csibuf3n [2] sck3n pin so3n pin csotn flag intc3n signal scs3n0 to scs3n3 pins <1> <2> <3> <4> <5> <6> <7> <7> <7> note <8> <9> <10> h (inactive) 111 1 1 111 0 00 000 11 0 11 00 00 sfempn flag sfp3 to sfp0 bits sfn3 to sfn0 bits 1h 0h 3h 2h 3h 0h 0
711 chapter 17 clocked serial interface 3 (csi3) user?s manual u16580ee2v0ud00 <1> when the csicaen bit of the csim3n register is set to 1, operating clock supply is enabled. <2> specify the transfer mode by setting the csic3n and csil3n registers. <3> write 1 to the fpclrn bit of the sfa3n register to clear all the csibufn pointers to 0. <4> confirm that the sffuln bit = 0, sfempn bit = 1, and sfpn3 to sfpn0 bits = 0000 in the sfa3n register. <5> specify the transfer mode by using the trmdn, dirn, csitn, cswen, and csmdn bits of the csim3n register and, at the same time, enable transmission by setting the ctxen bit to 1. <6> set the number of data to be transmitted by using the sfnn3 to sfnn0 bits of the sfn3n register. <7> write first cs data to the sfcs3n register and subsequently write transfer data to the sfdb3n register. writing data exceeding the set value of the sfn3n register is prohibited. <8> confirm that the intc3n interrupt has occurred and the sfempn bit is 1. then write 1 to the fpclrn bit of the sfa3n register, and clear all the csibufn pointers to 0 in preparation for the next transfer. <9> confirm that the sffuln bit = 0, sfempn bit = 1, and sfpn3 to sfpn0 bits = 0000 in the sfa3n register. <10> disable transmission by clearing the ctxen bit of the csim3n register to 0 (end of transmission). remarks: 1. to execute a further transfer, repeat <6> to <9> before <10>. 2. n = 0, 1
712 chapter 17 clocked serial interface 3 (csi3) user?s manual u16580ee2v0ud00 17.6.8 consecutive mode (master mode, reception mode) figure 17-29: consecutive mode (master mode, reception mode) msb first (dir bit = 0), ckp bit = 0, dap bit = 1 transfer data length: 8 bits (ccln3 to ccln0 bits = 1000b) intc3n interrupt not delayed (csit bit = 0), transfer wait: disabled (cswe bit = 0), chip select active level: l-level (cslvn3 to cslvn0 bits = 0000b) note: during this period a reception from the slave is put on hold until at least one dummy transmit data has been loaded to the csibufn register by writing the sfdb3n register (sfempn flag of sfa3n register = 0) in order to start the transfer. remark: n = 0, 1 crxen bit sfempn flag sfdb3n register write csibuf3n [0] dummy 55h dummy cs0 1h cs1 cs2 csibuf3n [1] csibuf3n [2] sck3n pin si3n pin csotn flag intc3n signal sirb3n register read sfp3 to sfp0 bits sfn3 to sfn0 bits scs3n0 to scs3n3 pins h (inactive) <1> <2> <3> <4> <5> <6> <11> <7> <7> <7> <9> <10> <8> <8> <8> dummy aah 0h 3h 2h 3h 0h 111 1 1 111 0 00 000 11 0 11 00 00 cch note 0
713 chapter 17 clocked serial interface 3 (csi3) user?s manual u16580ee2v0ud00 <1> when the csicaen bit of the csim3n register is set to 1, operating clock supply is enabled. <2> specify the transfer mode by setting the csic3n and csil3n registers. <3> write 1 to the fpclrn bit of the sfa3n register to clear all the csibufn pointers to 0. <4> confirm that the sffuln bit = 0, sfempn bit = 1, and sfpn3 to sfpn0 bits = 0000 in the sfa3n register. <5> specify the transfer mode by using the trmdn, dirn, csitn, cswen, and csmdn bits of the csim3n register and, at the same time, enable reception by setting the crxen bit to 1. <6> set the number of data to be received by using the sfnn3 to sfnn0 bits of the sfn3n register. <7> write first cs data to the sfcs3n register and subsequently write dummy transfer data to the sfdb3n register (reception start trigger). writing dummy data exceeding the set value of the sfn3n register is prohibited. <8> confirm that the intc3n interrupt has occurred and the sfempn bit is 1. then read the sirb3n register (sequentially read the receive data stored in the csibufn register). <9> write 1 to the fpclrn bit of the sfa3n register, and clear all the csibufn pointers to 0 in preparation for the next transfer. <10> confirm that the sffuln bit = 0, sfempn bit = 1, and sfpn3 to sfpn0 bits = 0000 in the sfa3n register. <11> disable reception by clearing the crxen bit of the csim3n register to 0 (end of reception). remarks: 1. to execute a further transfer, repeat <6> to <10> before <11>. perform writing dummy transfer data in <7> every time transfer is executed. 2. the so3n pin output is fixed to low level (default value). 3. n = 0, 1
714 chapter 17 clocked serial interface 3 (csi3) user?s manual u16580ee2v0ud00 17.6.9 consecutive mode (master mode, transmission/reception mode) figure 17-30: consecutive mode (master mode, transmission/reception mode) msb first (dir bit = 0), ckp bit = 0, dap bit = 1 transfer data length: 8 bits (ccln3 to ccln0 bits = 1000b) intc3n interrupt not delayed (csit bit = 0), transfer wait: disabled (cswe bit = 0), chip select active level: l-level (cslvn3 to cslvn0 bits = 0000b) note: during this period a reception from the slave is put on hold until at least one transmit data has been loaded to the csibufn register by writing the sfdb3n register (sfempn flag of sfa3n register = 0) in order to start the transfer. remark: n = 0, 1 ctxen bit, crxen bit sfempn flag sfdb3n register write csibuf3n [0] 55h cch 96h 33h cs0 1h cs1 cs2 csibuf3n [1] csibuf3n [2] sck3n pin so3n pin si3n pin csotn flag intc3n signal sirb3n register read sfp3 to sfp0 bits sfn3 to sfn0 bits scs3n0 to scs3n3 pins 111 1 11 111 1111111 111 0 00 0 00 00 000 00 000 h (inactive) 00 00 11 0 0 0 1 0 1 1 <1> <2> <3> <4> <5> <6> <11> <7> <7> <7> note <9> <10> <8> <8> <8> aah 0h 3h 2h 3h 0h 99h
715 chapter 17 clocked serial interface 3 (csi3) user?s manual u16580ee2v0ud00 <1> when the csicaen bit of the csim3n register is set to 1, operating clock supply is enabled. <2> specify the transfer mode by setting the csic3n and csil3n registers. <3> write 1 to the fpclrn bit of the sfa3n register to clear all the csibufn pointers to 0. <4> confirm that the sffuln bit = 0, sfempn bit = 1, and sfpn3 to sfpn0 bits = 0000 in the sfa3n register. <5> specify the transfer mode by using the trmdn, dirn, csitn, cswen, and csmdn bits of the csim3n register and, at the same time, enable transmission/reception by setting both the ctxen and crxen bits to 1. <6> set the number of data to be transmitted/received by using the sfnn3 to sfnn0 bits of the sfn3n register. <7> write first cs data to the sfcs3n register and subsequently write transfer data to the sfdb3n register. writing data exceeding the set value of the sfn3n register is prohibited. <8> confirm that the intc3n interrupt has occurred and the sfempn bit is 1. then read the sirb3n register (sequentially read the receive data stored in the csibufn register). <9> write 1 to the fpclrn bit of the sfa3n register, and clear all the csibufn pointers to 0 in preparation for the next transfer. <10> confirm that the sffuln bit = 0, sfempn bit = 1, and sfpn3 to sfpn0 bits = 0000 in the sfa3n register. <11> disable transmission/reception by clearing th e ctxen and crxen bits of the csim3n register to 0 (end of transmission/reception). remarks: 1. to execute a further transfer, repeat <6> to <10> before <11>. 2. n = 0, 1
716 chapter 17 clocked serial interface 3 (csi3) user?s manual u16580ee2v0ud00 17.6.10 consecutive mode (slave mode, transmission mode) figure 17-31: consecutive mode (slave mode, transmission mode) msb first (dir bit = 0), ckp bit = 1, dap bit = 1 transfer data length: 8 bits (ccln3 to ccln0 bits = 1000b) intc3n interrupt not delayed (csit bit = 0), transfer wait: disabled (cswe bit = 0), chip select active level: l-level (cslvn3 to cslvn0 bits = 0000b) note: during this period a reception re quest from the master will be ig nored until at least one transmit data is loaded to the csibufn register by writing the sfdb3n register (sfempn flag of sfa3n register = 0). remark: n = 0, 1 ctxen bit sfdb3n register write csibuf3n [0] 55h aah csibuf3n [1] csibuf3n [2] sck3n pin so3n pin csotn flag intc3n signal scs3n0 to scs3n3 pins <1> <2> <3> <4> <5> <6> <7> <7> <7> note <8> <9> <10> h (inactive) 111 1 1 111 0 00 000 11 0 11 00 00 sfempn flag sfp3 to sfp0 bits sfn3 to sfn0 bits 1h 0h 3h 2h 3h 0h cch 0
717 chapter 17 clocked serial interface 3 (csi3) user?s manual u16580ee2v0ud00 <1> when the csicaen bit of the csim3n register is set to 1, operating clock supply is enabled. <2> specify the transfer mode by setting the csic3n and csil3n registers. <3> write 1 to the fpclrn bit of the sfa3n register to clear all the csibufn pointers to 0. <4> confirm that the sffuln bit = 0, sfempn bit = 1, and sfpn3 to sfpn0 bits = 0000 in the sfa3n register. <5> specify the transfer mode by using the trmdn, dirn, csitn, cswen, and csmdn bits of the csim3n register and, at the same time, enable transmission by setting the ctxen bit to 1. <6> set the number of data to be transmitted by using the sfnn3 to sfnn0 bits of the sfn3n register. <7> write transfer data to the sfdb3n register. writing data exceeding the set value of the sfn3n register is prohibited. since the chip select outputs (scs3n0 to scs3n3) are ineffective in the slave mode and always output the inactive level, writing of cs data to the sfcs3n register is not necessary. <8> confirm that the intc3n interrupt has occurred and the sfempn bit is 1. then write 1 to the fpclrn bit of the sfa3n register, and clear all the csibufn pointers to 0 in preparation for the next transfer. <9> confirm that the sffuln bit = 0, sfempn bit = 1, and sfpn3 to sfpn0 bits = 0000 in the sfa3n register. <10> disable transmission by clearing the ctxen bit of the csim3n register to 0 (end of transmission). remarks: 1. to execute a further transfer, repeat <6> to <9> before <10>. 2. n = 0, 1
718 chapter 17 clocked serial interface 3 (csi3) user?s manual u16580ee2v0ud00 17.6.11 consecutive mode (slave mode, reception mode) figure 17-32: consecutive mode (slave mode, reception mode) msb first (dir bit = 0), ckp bit = 0, dap bit = 0 transfer data length: 8 bits (ccln3 to ccln0 bits = 1000b) intc3n interrupt not delayed (csit bit = 0), transfer wait: disabled (cswe bit = 0), chip select active level: l-level (cslvn3 to cslvn0 bits = 0000b) note: during this period a transmission fr om the master will be ignored un til at least one transmit data is loaded to the csibufn register by writing the sfdb3n register (sfempn flag of sfa3n register = 0). remark: n = 0, 1 crxen bit sfempn flag sfdb3n register write csibuf3n [0] dummy 55h dummy 1h csibuf3n [1] csibuf3n [2] sck3n pin si3n pin csotn flag intc3n signal sirb3n register read sfp3 to sfp0 bits sfn3 to sfn0 bits scs3n0 to scs3n3 pins h (inactive) <1> <2> <3> <4> <5> <6> <11> <7> <7> <7> <9> <10> <8> <8> <8> dummy aah 0h 3h 2h 3h 0h 111 1 1 0 00 000 11 0 11 00 00 cch note 111 0
719 chapter 17 clocked serial interface 3 (csi3) user?s manual u16580ee2v0ud00 <1> when the csicaen bit of the csim3n register is set to 1, operating clock supply is enabled. <2> specify the transfer mode by setting the csic3n and csil3n registers. <3> write 1 to the fpclrn bit of the sfa3n register to clear all the csibufn pointers to 0. <4> confirm that the sffuln bit = 0, sfempn bit = 1, and sfpn3 to sfpn0 bits = 0000 in the sfa3n register. <5> specify the transfer mode by using the trmdn, dirn, csitn, cswen, and csmdn bits of the csim3n register and, at the same time, enable reception by setting the crxen bit to 1. <6> set the number of data to be received by using the sfnn3 to sfnn0 bits of the sfn3n register. <7> write dummy transfer data to the sfdb3n register (reception start trigger). writing dummy data exceeding the set value of the sfn3n register is prohibited. since the chip select outputs (scs3n0 to scs3n3) are ineffective in the slave mode and always output the inactive level, writing of cs data to the sfcs3n register is not necessary. <8> confirm that the intc3n interrupt has occurred and the sfempn bit is 1. then read the sirb3n register (sequentially read the receive data stored in the csibufn register). <9> write 1 to the fpclrn bit of the sfa3n register, and clear all the csibufn pointers to 0 in preparation for the next transfer. <10> confirm that the sffuln bit = 0, sfempn bit = 1, and sfpn3 to sfpn0 bits = 0000 in the sfa3n register. <11> disable reception by clearing the crxen bit of the csim3n register to 0 (end of reception). remarks: 1. to execute a further transfer, repeat <6> to <10> before <11>. perform writing dummy transfer data in <7> every time transfer is executed. 2. the so3n pin output is fixed to low level (default value). 3. n = 0, 1
720 chapter 17 clocked serial interface 3 (csi3) user?s manual u16580ee2v0ud00 17.6.12 consecutive mode (in slave mode and transmission/reception mode) figure 17-33: consecutive mode (slave mode, transmission/reception mode) msb first (dir bit = 0), ckp bit = 0, dap bit = 1 transfer data length: 8 bits (ccln3 to ccln0 bits = 1000b) intc3n interrupt not delayed (csit bit = 0), transfer wait: disabled (cswe bit = 0), chip select active level: l-level (cslvn3 to cslvn0 bits = 0000b) note: during this period a transmission/reception from the master will be ignored until at least one transmit data is loaded to the csibufn register by writing the sfdb3n register (sfempn flag of sfa3n register = 0). remark: n = 0, 1 ctxen bit, crxen bit sfempn flag sfdb3n register write csibuf3n [0] 55h cch 96h 1h csibuf3n [1] csibuf3n [2] sck3n pin so3n pin si3n pin csotn flag intc3n signal sirb3n register read sfp3 to sfp0 bits sfn3 to sfn0 bits scs3n0 to scs3n3 pins 111 1 11 111 1111111 111 0 00 0 00 00 000 00 000 h (inactive) 00 00 11 0 0 0 1 0 1 1 <1> <2> <3> <4> <5> <6> <11> <7> <7> <7> note <9> <10> <8> <8> <8> aah 0h 3h 2h 3h 0h 99h 33h
721 chapter 17 clocked serial interface 3 (csi3) user?s manual u16580ee2v0ud00 <1> when the csicaen bit of the csim3n register is set to 1, operating clock supply is enabled. <2> specify the transfer mode by setting the csic3n and csil3n registers. <3> write 1 to the fpclrn bit of the sfa3n register to clear all the csibufn pointers to 0. <4> confirm that the sffuln bit = 0, sfempn bit = 1, and sfpn3 to sfpn0 bits = 0000 in the sfa3n register. <5> specify the transfer mode by using the trmdn, dirn, csitn, cswen, and csmdn bits of the csim3n register and, at the same time, enable transmission/reception by setting both the ctxen and crxen bits to 1. <6> set the number of data to be transmitted/received by using the sfnn3 to sfnn0 bits of the sfn3n register. <7> write transfer data to the sfdb3n register. writing data exceeding the set value of the sfn3n register is prohibited. since the chip select outputs (scs3n0 to scs3n3) are ineffective in the slave mode and always output the inactive level, writing of cs data to the sfcs3n register is not necessary. <8> confirm that the intc3n interrupt has occurred and the sfempn bit is 1. then read the sirb3n register (sequentially read the receive data stored in the csibufn register). <9> write 1 to the fpclrn bit of the sfa3n register, and clear all the csibufn pointers to 0 in preparation for the next transfer. <10> confirm that the sffuln bit = 0, sfempn bit = 1, and sfpn3 to sfpn0 bits = 0000 in the sfa3n register. <11> disable transmission/reception by clearing th e ctxen and crxen bits of the csim3n register to 0 (end of transmission/reception). remarks: 1. to execute a further transfer, repeat <6> to <10> before <11>. 2. n = 0, 1
722 chapter 17 clocked serial interface 3 (csi3) user?s manual u16580ee2v0ud00 17.7 cautions the following points must be observed when using csi3n (n = 0, 1). cautions: 1. the csi3n unit is reset and csi3n is stopped when the csicaen bit of the csim3n register is cleared to 0. to operate csi3n, first set the csicaen bit to 1. usually, before clearing the csicaen bit to 0, clear both the ctxen and crxen bits to 0 (after the end of transfer). 2. be sure to write 1 to the fpclrn bit of the sfa3n register to clear all the csibufn pointers to 0 before enabling transfer by setting the ctxen or crxen bit of the csim3n register to 1. if the ctxen or crxen bit is set to 1 without clearing the pointers, and if the previously transferred data remains in the csibufn register, transferring that data is immediately started. if transfer data is set to the csibufn register before transfer is enabled, transfer is started as soon as the ctxen or crxen bit is set to 1. 3. if the sfa3n register is read immediately after data has been written to the sfdb3n and sfdb3nl registers, the sffu ln, sfempn, and sfpn3 to sfpn0 bits of the sfa3n register may not change their values in time. if the sfa3n register is read before the sffuln bit is set to 1 and a 17th data is written, the csibufn overflow interrupt (intc3novf) occurs. 4. when using csi3n in configuration with dma transfer, observe that only single mode is permitted (trmdn bit of csim3n register = 0), and chip select csi regis- ters (sfcs3n, sfcs3nl) are not supported.
723 user?s manual u16580ee2v0ud00 chapter 18 afcan controller 18.1 outline description this product features an on-chip 2-channel can (controller area network) controller that complies with can protocol as standardized in iso 11898. 18.1.1 features ? compliant with iso 11898 and tested according to iso/dis 16845 (can conformance test) ? standard frame and extended frame transmission/reception enabled ? transfer rate: 1 mbps max. ? 32 message buffers/2 channels ? receive/transmit history list function ? automatic block transmission function ? multi-buffer receive block function ? mask setting of four patterns is possible for each channel 18.1.2 implementation implemented in v850e/ph2 are 2 afcan modules. the actual mapping of the sfr depends on the content of the bpc register (please refer to 3.4.7 ?programmable peripheral i/o area? on page 109 ). for a complete list refer to table 3-6, ?programmable peripheral i/o registers,? on page 111 . each module has it?s own channel offset to this base address. these offsets are as follows: table 18-1: can channel offsets can channel channel offset type can0 0x0000 afcan can1 0x0600
724 chapter 18 afcan controller user?s manual u16580ee2v0ud00 18.1.3 overview of functions table 18-2 presents an overview of the can controller functions. note: this function is valid only with a macro having an advanced time stamp function. table 18-2: overview of functions function details protocol can protocol iso 118 98 (standard and extended frame transmission/reception) baud rate maximum 1 mbps data storage storing messages in the can ram number of messages - 32 message buffers/2 channels - each message buffer can be set to be either a transmit message buffer or a receive message buffer. message reception - unique id can be set to each message buffer. - mask setting of four patterns is possible for each channel. - a receive completion interrupt is generated each time a message is received and stored in a message buffer. - two or more receive message buffers can be used as a fifo receive buffer (multi-buffer receive block function). - receive history list function message transmission - unique id can be set to each message buffer. - transmit completion interrupt for each message buffer - message buffer number 0 to 7 specified as the transmit message buffer can be used for automatic block transfer. message transmission interval is programmable (automatic block transmission function (hereafter referred to as ?abt?)). - transmission history list function remote frame processing remote frame processing by transmit message buffer time stamp function - the time stam p function can be set for a message reception when a 16-bit timer is used in combination. time stamp capture trigger can be select ed (sof or eof in a can message frame can be detected.). - the time stamp function can be set for a transmit message. - a specific byte in a data field can be replaced by a capture time stamp note diagnostic function - readable error counters - ?valid protocol operation flag? for verification of bus connections - receive-only mode - single-shot mode - can protocol error type decoding - self-test mode forced release from bus- off state - default mode can be set while bus is off, so that bus can be forcibly released from the bus-off state. power save mode - can sleep mode (can be woken up by can bus) - can stop mode (cannot be woken up by can bus)
725 chapter 18 afcan controller user?s manual u16580ee2v0ud00 18.1.4 configuration the can controller is composed of the following four blocks. (1) npb interface this functional block provides an npb (nec peripheral i/o bus) interface and means of transmitting and receiving signals between the can module and the host cpu. (2) mcm (message control module) this functional block controls access to the can protocol layer and to the can ram within the can module. (3) can protocol layer this functional block is involved in the operat ion of the can protocol and its related settings. (4) can ram this is the can memory functional block, which is used to store message ids, message data, etc. figure 18-1: block diagram of can module remark: n = 0, 1, m = 0 to 31 can module can ram npb (nec peripheral i/o bus) message control module npb interface interrupt request intcnrex intcntrx intcnerr intcnwup can protocol layer can transceiver message buffer 0 message buffer 1 message buffer 2 message buffer 3 message buffer m c1mask1 c1mask2 c1mask3 c1mask4 ... can_h can_l can bus cantxn canrxn cpu
726 chapter 18 afcan controller user?s manual u16580ee2v0ud00 18.2 can protocol can (c ontroller a rea n etwork) is a high-speed multiplex communication protocol for real-time communication in automotive applications (class c). can is prescribed by iso 11898. for details, refer to the iso 11898 specifications. the can specification is generally divided into two layers: a physical layer and a data link layer. in turn, the data link layer includes logica l link and medium access control. the composition of these layers is illustrated below. figure 18-2: composition of layers note: can controller specification 18.2.1 frame format (1) standard format frame - the standard format frame uses 11-bit identifiers, which means that it can handle up to 2048 messages. (2) extended format frame - the extended format frame uses 29-bit (11 bits + 18 bits) identifiers which increase the number of messages that can be handled to 2048 2 18 messages. - extended format frame is set when ?recessive level? (cmos level equals ?1?) is set for both the srr and ide bits in the arbitration field. physical layer prescription of signal level and bit description data link layer note logical link control (llc) medium access control (mac) acceptance filtering overload report recovery management data capsuled/not capsuled frame coding (stuffing/not stuffing) medium access management error detection error report acknowledgement seriated/not seriated higher lower
727 chapter 18 afcan controller user?s manual u16580ee2v0ud00 18.2.2 frame types the following four types of frames are used in the can protocol. (1) bus value the bus values are divided into dominant and recessive. - dominant level is indicated by logical 0. - recessive level is indicated by logical 1. when a dominant level and a recessive level are transmitted simultaneously, the bus value becomes dominant level. table 18-3: frame types frame type description data frame frame used to transmit data remote frame frame used to request a data frame error frame frame used to report error detection overload frame frame used to delay the next data frame or remote frame
728 chapter 18 afcan controller user?s manual u16580ee2v0ud00 18.2.3 data frame and remote frame (1) data frame a data frame is composed of seven fields. figure 18-3: data frame remark: d: dominant = 0 r: recessive = 1 r d interframe space end of frame (eof) ack field crc field data field control field arbitration field start of frame (sof) data frame <1> <2> <3> <4> <5> <6> <7> <8>
729 chapter 18 afcan controller user?s manual u16580ee2v0ud00 (2) remote frame a remote frame is composed of six fields. figure 18-4: remote frame remarks: 1. the data field is not transferred even if the control field?s data length code is not ?0000b?. 2. d: dominant = 0 r: recessive = 1 interframe space end of frame (eof) ack field crc field control field arbitration field start of frame (sof) remote frame <1> <2> <3> <5> <6> <7> <8> r d
730 chapter 18 afcan controller user?s manual u16580ee2v0ud00 (3) description of fields <1> start of frame (sof) the start of frame field is located at the start of a data frame or remote frame. figure 18-5: start of frame (sof) remark: d: dominant = 0 r: recessive = 1 ? if dominant level is detected in the bus idle state, a hard-synchronization is performed (the current tq is assigned to be the sync segment). ? if dominant level is sampled at the sample point following such a hard-synchronization, the bit is assigned to be a sof. if recessive level is detected, the protocol layer returns to the bus idle state and regards the preceding dominant pulse as a disturbance only. no error frame is generated in such case. r d 1 bit start of frame (interframe space or bus idle) (arbitration field)
731 chapter 18 afcan controller user?s manual u16580ee2v0ud00 <2> arbitration field the arbitration field is used to set the priority, data frame/remote frame, and frame format. figure 18-6: arbitration field (in standard format mode) cautions: 1. id28 to id18 are identifiers. 2. an identifier is transmitted msb first. remark: d: dominant = 0 r: recessive = 1 figure 18-7: arbitration field (in extended format mode) cautions: 1. id28 to id18 are identifiers. 2. an identifier is transmitted msb first. remark: d: dominant = 0 r: recessive = 1 table 18-4: rtr frame settings frame type rtr bit data frame 0 (d) remote frame 1 (r) table 18-5: frame format setting (ide bit) and number of identifier (id) bits frame format srr bit ide bit number. of bits standard format mode none 0 (d) 11 bits extended format mode 1 (r) 1 (r) 29 bits identifier arbitration field (control field) (11 bits) id28 id18 (1 bit) (1 bit) r d ide (r1) r0 rtr r d r1 r0 rtr ide srr identifier identifier arbitration field (control field) (11 bits) (18 bits) id28 id18 id17 id0 (1 bit) (1 bit) (1 bit)
732 chapter 18 afcan controller user?s manual u16580ee2v0ud00 <3> control field the control field sets ?n? as the number of data bytes in the data field (n = 0 to 8). figure 18-8: control field remark: d: dominant = 0 r: recessive = 1 in a standard format frame, the control field?s ide bit is the same as the r1 bit. caution: in the remote frame, there is no data field even if the data length code is not 0000b. table 18-6: data length setting data length code data byte count dlc3 dlc2 dlc1 dlc0 0000 0 bytes 0001 1 byte 0010 2 bytes 0011 3 bytes 0100 4 bytes 0101 5 bytes 0110 6 bytes 0111 7 bytes 1000 8 bytes other than above 8 bytes regardless of the value of dlc3 to dlc0 control field (data field) (arbitration field) r d r1 (ide) r0 rtr dlc2 dlc3 dlc1 dlc0 control field (data field) (arbitration field) r d r1 (ide) r0 rtr dlc2 dlc3 dlc1 dlc0
733 chapter 18 afcan controller user?s manual u16580ee2v0ud00 <4> data field the data field contains the amount of data (byte units) set by the control field. up to 8 units of data can be set. figure 18-9: data field remark: d: dominant = 0 r: recessive = 1 <5> crc field the crc field is a 16-bit field that is used to check for errors in transmit data. figure 18-10: crc field remark: d: dominant = 0 r: recessive = 1 - the polynomial p(x) used to generate the 15-bit crc sequence is expressed as follows. p(x) = x15 + x14 + x10 + x8 + x7 + x4 + x3 + 1 - transmitting node: transmits the crc sequence calculated from the data (before bit stuffing) in the start of frame, arbitration field, control field, and data field. - receiving node: compares the crc sequence ca lculated using data bi ts that exclude the stuffing bits in the receive data with the crc sequence in the crc field. if the two crc sequences do not match, the node issues an error frame. (8 bits) msb lsb data7 (8 bits) msb lsb data field (crc field) (control field) r d data0 r d crc sequence crc delimiter (1 bit) (15 bits) crc field (ack field) (data field or control field)
734 chapter 18 afcan controller user?s manual u16580ee2v0ud00 <6> ack field the ack field is used to acknowledge normal reception. figure 18-11: ack field remark: d: dominant = 0 r: recessive = 1 - if no crc error is detected, the receiving node sets the ack slot to the dominant level. - the transmitting node outputs two recessive-level bits. <7> end of frame (eof) the end of frame field indicates the end of data frame/remote frame. figure 18-12: end of frame (eof) remark: d: dominant = 0 r: recessive = 1 ack slot (1 bit) ack delimiter (1 bit) ack field (end of frame) (crc field) r d r d end of frame (7 bits) (interframe space or overload frame) (ack field)
735 chapter 18 afcan controller user?s manual u16580ee2v0ud00 <8> interframe space the interframe space is inserted after a data frame, remote frame, error frame, or overload frame to separate one frame from the next. - the bus state differs depending on the error status. (a) error active node the interframe space consists of a 3-bit intermission field and a bus idle field. figure 18-13: interframe space (error active node) remarks: 1. bus idle: state in which the bus is not used by any node. 2. d: dominant = 0 r: recessive = 1 (b) error passive node the interframe space consists of an intermission field, a suspend transmission field, and a bus idle field. figure 18-14: interframe space (error passive node) remarks: 1. bus idle: state in which the bus is not used by any node. suspend transmission: sequence of 8 recessi ve-level bits transmitted from the node in the error passive status. 2. d: dominant = 0 r: recessive = 1 usually, the intermission field is 3 bits. if the transmitting node detects a dominant level at the third bit of the intermission field, however, it executes transmission. interframe space intermission (3 bits) bus idle (0 to bits) (frame) (frame) r d r d interframe space intermission (3 bits) suspend transmission (8 bits) bus idle (0 to bits) (frame) (frame)
736 chapter 18 afcan controller user?s manual u16580ee2v0ud00 18.2.4 error frame an error frame is output by a node that has detected an error. figure 18-15: error frame remark: d: dominant = 0 r: recessive = 1 table 18-7: operation in error status error status operation error active a node in this status can transmit immediately after a 3-bit intermission. error passive a node in this status can transmit 8 bits after the intermission. table 18-8: definition error frame fields no. name bit count definition <1> error flag1 6 error active node: outputs 6 dominant-level bits consecutively. error passive node: outputs 6 recessive-level bits consecutively. if another node outputs a dominant level while one node is outputting a passive error flag, the passive error flag is not cleared until the same level is detected 6 bits in a row. <2> error flag2 0 to 6 nodes receiving error flag 1 detect bit stuff errors and issues this error flag. <3> error delimiter 8 outputs 8 recessive-level bits consecutively. if a dominant level is detected at the 8th bit, an overload frame is transmitted from the next bit. <4> error bit ? the bit at which the error was detected. the error flag is output from the bit next to the error bit. in the case of a crc error, this bit is output following the ack delimiter. <5> interframe space/overload frame ? an interframe space or overload frame starts from here. 6 bits 0 to 6 bits 8 bits (<4>) (<5>) interframe space or overload frame error delimiter error flag2 error flag1 error bit error frame <1> r d <2> <3>
737 chapter 18 afcan controller user?s manual u16580ee2v0ud00 18.2.5 overload frame an overload frame is transmitte d under the following conditions. - when the receiving node has not completed the reception operation note - if a dominant level is detected at the first two bits during intermission - if a dominant level is detected at the last bit (7th bit) of the end of frame or at the last bit (8th bit) of the error - delimiter/overload delimiter note: the can is internally fast enough to process all received frames not generating overload frames. figure 18-16: overload frame remark: d: dominant = 0 r: recessive = 1 table 18-9: definition of overload frame fields no name bit count definition <1> overload flag 6 outputs 6 dominant-level bits consecutively. <2> overload flag from other node 0 to 6 the node that received an overlo ad flag in the interframe space outputs an overload flag. <3> overload delimiter 8 outputs 8 recessive-level bits consecutively. if a dominant level is detected at the 8t h bit, an overload frame is transmitted from the next bit. <4> frame ? output following an end of frame, error delimiter, or overload delimiter. <5> interframe space/ overload frame ? an interframe space or overload frame starts from here. 6 bits 0 to 6 bits 8 bits (<4>) (<5>) interframe space or overload frame overload delimiter overload flag overload flag frame overload frame <1> r d <2> <3>
738 chapter 18 afcan controller user?s manual u16580ee2v0ud00 18.3 functions 18.3.1 determining bus priority (1) when a node starts transmission: - during bus idle, the node that output data first transmits the data. (2) when more than one node starts transmission: - the node that outputs the dominant level for the longest consecutively from the first bit of the arbitration field acquires the bus priority (if a dominant level and a recessive level are simultaneously transmitted, the dominant level is taken as the bus value). - the transmitting node compares its output arbitration field and the data level on the bus. (3) priority of data frame and remote frame - when a data frame and a remote frame are on the bus, the data frame has priority because its rtr bit, the last bit in the arbitration field, carries a dominant level. remark: if the extended-format data frame and the standard-format remote frame conflict on the bus (if id28 to id18 of both of them are the same), the standard-format remote frames takes priority. 18.3.2 bit stuffing bit stuffing is used to establis h synchronization by appending 1-bit inverted data if the same level continues for 5 bits, in order to prevent a burst error. table 18-10: determining bus priority level match continuous transmission level mismatch continuous transmission table 18-11: bit stuffing transmission during the transmission of a data frame or remote frame, when the same level continues for 5 bits in the data between the start of frame and the ack field, 1 inverted-level bit of data is inserted before the following bit. reception during the reception of a data frame or remote frame, when the same level continues for 5 bits in the data between the start of frame and the ack field, reception is continued after deleting the next bit.
739 chapter 18 afcan controller user?s manual u16580ee2v0ud00 18.3.3 multi masters as the bus priority (a node acquiring transmit functions) is determined by the identifier, any node can be the bus master. 18.3.4 multi cast although there is one transmitting node, two or more nodes can receive the same data at the same time because the same identifier can be set to two or more nodes. 18.3.5 can sleep mode/can stop mode function the can sleep mode/can stop mode function puts the can controller in waiting mode to achieve low power consumption. the controller is woken up from the can sleep mode by bus operation but it is not woken up from the can stop mode by bus operation (the can stop mode is controlled by cpu access). 18.3.6 error control function (1) error types table 18-12: error types type description of error detection state detection method detection condition transmission/ reception field/frame bit error comparison of output level and level on the bus (except stuff bit) mismatch of levels transmitting/ receiving node bit that outputting data on the bus at the start of frame to end of frame, error frame and overload frame. stuff error check the receive data at the stuff bit 6 consecutive bits of the same output level receiving node start of frame to crc sequence crc error comparison of the crc sequence generated from the receive data and the received crc sequence mismatch of crc receiving node crc field form error field/frame check of the fixed format detection of fixed format violation receiving node - crc delimiter - ack field - end of frame - error frame - overload frame ack error check of the ack slot by the transmitting node detection of recessive level in ack slot transmitting node ack slot
740 chapter 18 afcan controller user?s manual u16580ee2v0ud00 (2) output timing of error frame (3) processing in case of error the transmission node re-transmits the data frame or remote frame after the error frame (however, it does not re-transmit the frame in the single-shot mode.). (4) error state (a) types of error states the following three types of error states are defined by the can specification. - error active - error passive - bus-off these types of error states are classified by the values of the tec7 to tec0 bits (transmission error counter bits) and the rec6 to rec0 bits (reception error counter bits) of the can error counter register as shown in table 18-14, ?types of error states,? on page 741. the present error state is indicated by the can module information register (cninfo). when each error counter value becomes equal to or greater than the error warning level (96), the tecs0 or recs0 bit of the cninfo register is set to 1. in this case, the bus state must be tested because it is considered that the bus has a serious fault. an error counter value of 128 or more indicates an error passive state and the tecs1 or recs1 bit of the cninfo register is set to 1. - if the value of the transmission error counter is greater than or equal to 256 (actually, the transmission error counter does not indicate a value greater than or equal to 256), the bus-off state is reached and the boff bit of the cninfo register is set to 1. - if only one node is active on the bus at startup (i.e., a particular case such as when the bus is connected only to the local station), ack is not returned even if data is transmitted. consequently, re-transmission of the error frame and data is repeated. in the error passive state, however, the transmission error counter is not incremen ted and the bus-off state is not reached. table 18-13: output timing of error frame type output timing bit error, stuff error, form error, ack error error frame output is started at the timing of the bit following the detected error. crc error error frame output is started at the ti ming of the bit following the ack delimiter.
741 chapter 18 afcan controller user?s manual u16580ee2v0ud00 note: the value of the transmission error counter (tec) is invalid when the boff bit is set to 1. if an error that increments the value of the transmission error counter by +8 while the counter value is in a range of 248 to 255, the counter is not incremented and the bus-off state is assumed. table 18-14: types of error states type operation value of error counter indication of cninfo register operation specific to given error state error active transmission 0-95 tecs1, 0 = 00 ? outputs an active error flag (6 consecutive dominant- level bits) on detection of the error. reception 0-95 recs1, 0 = 00 transmission 96-127 tecs1, 0 = 01 reception 96-127 recs1,0 = 01 error passive transmission 128-255 tecs1,0 = 11 ? outputs a passive error flag (6 consecutive recessive- level bits) on detection of the error. ? transmits 8 recessive-level bits, in between transmis- sions, following an intermission (suspend transmission) reception 128 or more recs1,0 = 11 bus-off transmission 256 or more (not indicated) note boff = 1, tecs = 11 ? communication is not possible. messages are not stored when receiving frames, however, the following operations of <1>, <2>, and <3> are done. <1> tsout toggles. <2> rec is incremented/decremented. <3> valid bit is set. ? if the initialization mode is set and then 11 recessive- level bits are generated 128 times in a row in an operation mode other than t he initialization mode, the error counter is reset to 0 and the error active state can be restored.
742 chapter 18 afcan controller user?s manual u16580ee2v0ud00 (b) error counter the error counter counts up when an error has occurred, and counts down upon successful transmission and reception. the error counter is updated during the first bit of the error delimiter. (c) occurrence of bit error in intermission an overload frame is generated. caution: if an error occurs, it is controlled according to the contents of the transmission error counter and reception error counter before the error occurred. the value of the error counter is incremented after the error flag has been output. table 18-15: error counter state transmission error counter (tec7 to tec0) reception error counter (rec6 to rec0) receiving node detects an error (except bit error in the active error flag or overload flag). no change +1 (when reps = 0) receiving node detects dominant level following error flag of error frame. no change +8 (when reps = 0) transmitting node transmits an error flag. [as exceptions, the error counter does not change in the following cases.] <1> ack error is detected in error passive state and dominant level is not detected while the passive error flag is being output. <2> a stuff error is detected in an arbitration field that transmitted a recessive level as a stuff bit, but a dominant level is detected. +8 no change bit error detection while active error flag or overload flag is being output (error-active transmitting node) +8 no change bit error detection while active error flag or overload flag is being output (error-active receiving node) no change +8(when reps = 0) when the node detects 14 consecutiv e dominant-level bits from the beginning of the active error flag or overload flag, and then subsequently detects 8 consecutive dominant-level bits. when the node detects 8 consecutive dominant levels after a passive error flag +8 (during transmission) +8 (during reception, when reps = 0) when the transmitting node has completed transmission without error (0 if error counter = 0) ?1 no change when the receiving node has completed reception without error no change ?1 (1 rec6 to rec0 127, when reps = 0) 0 (rec6 to rec0 = 0, when reps = 0) value of 119 to 127 is set (when reps = 1)
743 chapter 18 afcan controller user?s manual u16580ee2v0ud00 (5) recovery from bus-off state when the can module is in the bus-off state, the transmission pins (ctxdn) cut off from the can bus always output the recessive level. the can module recovers from the bus-off state in the following bus-off recovery sequence. <1> a request to enter th e can initialization mode <2> a request to enter a can operation mode (a) recovery operation through normal recovery sequence (b) forced recovery operation that skips recovery sequence (a) recovery operation from bus-off state through normal recovery sequence the can module first issues a request to enter the initialization mode (refer to timing <1> in ?recovery operation from bus-off state through normal recovery sequence? on page 744). this request will be immediately ac knowledged, and the opmode bits of the cnctrl register are cleared to 000b. processing such as analyzing the fault that has caused the bus-off state, re-defining the can module and message buffer using application software, or stopping the operation of the can module can be performed by clearing the gom bit to 0. next, the user requests to change the mode from the initialization mode to an operation mode (refer to timing <2> in figure 18-17, ?recovery operation from bus-off state through normal recovery sequence,? on page 744). this starts an operation to recover the can module from the bus-off state. the conditions under which the module can recover from the bus-off state are defined by the can protocol iso 11898, and it is necessary to detect 11 consecutive recessive- level bits 128 times. at this time, the request to change the mode to an operation mode is held pending until the recovery conditions are satisfied. when the recovery conditions are satisfied (refer to timing <3> in ?recovery operation from bus-off state through normal recovery sequence? on page 744), the can module can enter the operation mode it has requested. until the can module enters this operation mode, it stays in the initialization mode. whether the can module has completely entered the operation mode can be confirmed by reading the opmode bits of the cnctrl register. during the bus-off period and bus-off recovery sequence, the boff bit of the cninfo register stays set (to 1). in the bus-off recovery sequence, the reception error counter (bits rec0 to rec6) counts the number of times 11 consecutive recessive-level bits have been detected on the bus. therefore, the recovery state can be checked by reading rec0 to rec6 bits. caution: in the bus-off recovery sequence, the reception error counter (bits rec0 to rec6) counts up (+1) each time 11 consecutive recessive-level bits have been detected. even during the bus-off period, the can module can enter the can sleep mode or can stop mode. in this case, the bus-off recovery sequence star ts not entering a can initialization mode at the same time when the can sl eep mode is released. note that the bus-off recovery sequence will start when the can module will be woken up by the detection of the dominant edge other than clearing psmode by software.
744 chapter 18 afcan controller user?s manual u16580ee2v0ud00 figure 18-17: recovery operation from bus-off state through normal recovery sequence (b) forced recovery operation that skips bus-off recovery sequence the can module can be forcibly released from the bus-off state, regardless of the bus state, by skipping the bus-off recovery sequence. here is the procedure. first, the can module requests to enter the initialization mode. for the operation and points to be noted at this time, refer to 18.3.6 (5) (a)?recovery operation from bus-off state through nor- mal recovery sequence? on page 743 . next, the module requests to enter an operation mode. at the same time, the ccerc bit of the cnctrl register must be set to 1. as a result, the bus-off recovery sequence defined by the can protocol iso 11898 is skipped, and the module immediately enters the operation mode. in this case, the module is connected to the can bus after it has monitored 11 consecutive recessive-level bits. for details, refer to the processing in figure 18-78, ?setting can sleep mode/stop mode,? on page 854 . caution: this function is not defined by the can protocol iso 11898. when using this function, thoroughly evaluate its effect on the network system. (6) initializing can module er ror counter register (cne rc) in initialization mode if it is necessary to initialize the can module error counter register (cnerc) and can module information register (cninfo) for debugging or evaluating a program, they can be initialized to the default value by setting the ccerc bit of the cn ctrl register in the initialization mode. when initialization has been completed, the ccerc bit is automatically cleared to 0. cautions: 1. this function is enabled only in the initialization mode. even if the ccerc bit is set to 1 in a can operation mode, th e cnerc and cninfo registers are not initialized. 2. the ccerc bit can be set at the same time as the request to enter a can operation mode. remark: n = 0, 1 ?error-passive? 00h 00h 00h 00h 80h tec[7:0] ffh boff bit in cninfo register opmode[2:0] in cnctrl register (user writings) opmode[2:0] in cnctrl register (user readings) tec[7:0] in cnerc register reps, rec[6:0] in cnerc register tec > ffh 00h 00h 00h ffh < tec [7:0] ?bus-off? ?bus-off-recovery-sequence? ?error-active? 00h tec[7:0] < 80h 00h reps, rec[6:0] < 80h 00h reps, rec[6:0] 80h <1> <2> <3> undefined
745 chapter 18 afcan controller user?s manual u16580ee2v0ud00 18.3.7 baud rate control function (1) prescaler the can controller has a prescaler that divides the clock (f can ) supplied to can. this prescaler generates a can protocol layer basic clock (f tq ) that is the can module system clock (f canmod ) divided by 1 to 256 (refer to 18.6.13 and figure 18-38, ?can module n bit rate prescaler reg- ister (cnbrp),? on page 781 ). (2) data bit time (8 to 25 time quanta) one data bit time is defined as shown in figure 18-18. the can controller sets time segment 1, time segment 2, and re-synchronization jump width (sjw) as the parameter of data bit time, as shown in figure 18-18. time segment 1 is equivalent to the total of the propagation (prop) segment and phase segment 1 that are defined by the can protocol specification. time segment 2 is equivalent to phase segment 2. figure 18-18: segment setting note: ipt: information processing time remark: reference: the can standard iso 11898 specification defines the segments constituting the data bit time as shown in figure 18-19 on the next page. table 18-16: segment setting segment name settable range notes on setting to confirm to can specification time segment 1 (tseg1) 2tq to 16tq ? time segment 2 (tseg2) 1tq to 8tq ipt note of the can controller is 0tq. to conform to the can protocol specification, therefore, a length equal to phase segment 1 must be set here. this means that the length of time segment 1 minus 1tq is the settable upper limit of time segment 2. re-synchronization jump width (sjw) 1tq to 4tq the length of time segmen t 1 minus 1tq or 4 tq, whichever is smaller. data bit time(dbt) phase segment 1 prop segment sync segment phase segment 2 time segment 1(tseg1) time segment 2 (tseg2) sample point (spt)
746 chapter 18 afcan controller user?s manual u16580ee2v0ud00 figure 18-19: configuration of data bit time defi ned by can specification note: ipt: information processing time table 18-17: configuration of data bit time defined by can specification segment name segment length description sync segment (synchronization segment) 1 this segment starts at the edge where the level changes from recessive to dominant when hard-synchronization is established. prop segment programmable to 1 to 8 or more this segment absorbs the delay of the output buffer, can bus, and input buffer. the length of this segment is set so that ack is returned before the start of phase segment 1. time of prop segment (delay of output buffer) + 2 (delay of can bus) + (delay of input buffer) this segment compensates for an error of data bit time. the longer this segment, the wider the permissible range but the slower the communication speed. phase segment 1 programmable to 1 to 8 phase segment 2 phase segment 1 or ipt note , whichever greater sjw programmable from 1tq to length of segment 1 or 4tq, whichever is smaller this width sets the upper limit of expansion or contraction of the phase segment during re-synchronization phase segment 1 prop segment sync segment phase segment 2 sample point (spt) sjw data bit time(dbt)
747 chapter 18 afcan controller user?s manual u16580ee2v0ud00 (3) synchronizing data bit - the receiving node establishes synchronization by a level change on the bus because it does not have a sync signal. - the transmitting node transmits data in synchronization with the bit timing of the transmitting node. (a) hard-synchronization this synchronization is established when the receiving node detects the start of frame in the interframe space. - when a falling edge is detected on the bus, t hat tq means the sync segment and the next segment is the prop segment. in this case, sy nchronization is established regardless of sjw. figure 18-20: hard-synchronization at recogn ition of dominant level during bus idle start of frame interframe space canbus bit timing phase segment 1 prop segment sync segment phase segment 2
748 chapter 18 afcan controller user?s manual u16580ee2v0ud00 (b) re-synchronization synchronization is established again if a level change is detected on the bus during reception (only if a recessive level was sampled previously). - the phase error of the edge is given by the relative position of the detected edge and sync segment. - 0: if the edge is within the sync segment positive: if the edge is before the sample point (phase error) negative: if the edge is after the sample point (phase error) if phase error is positive: phase segment 1 is longer by specified sjw. if phase error is negative: phase segm ent 2 is shorter by specified sjw. - the sample point of the data of the receiving node moves relatively due to the ?discrepancy? in baud rate between the transmitting node and receiving node. figure 18-21: re-synchronization can bus bit timing can bus bit timing data bit time(dbt) phase segment 1 prop segment sync segment phase segment 2 phase segment 1 prop segment sync segment phase segment 2 sample point sample point if phase error is negative if phase error is positve
749 chapter 18 afcan controller user?s manual u16580ee2v0ud00 18.4 connection with target system the microcontroller incorporated a can has to be connected to the can bus using an external transceiver. figure 18-22: connection to can bus remark: n = 0, 1 microcontroller incorporated a can transceiver ctxdn crxdn canl canh
750 chapter 18 afcan controller user?s manual u16580ee2v0ud00 18.5 internal registers of can controller 18.5.1 can controller configuration table 18-18: list of can controller registers (1/2) item register name can global registers can globa l control register (cngmctrl) can global clock selection register (cngmcs) can global automatic block transmi ssion control register (cngmabt) can global configuration register (cngmconf) can global automatic block transm ission delay register (cngmabtd) can module registers can module ma sk 1 register (cnmask1l, cnmask1h) can module mask 2 register (cnmask2l, cnmask2h) can module mask3 register (cnmask3l, cnmask3h) can module mask 4 regist ers (cnmask4l, cnmask4h) can module control register (cnctrl) can module last error code register (cnlec) can module information register (cninfo) can module error coun ter register (cnerc) can module interrupt enable register (cnie) can module interrupt st atus register (cnints) can module bit rate prescaler register (cnbrp) can module bit rate register (cnbtr) can module last in-pointer register (cnlipt) can module receive history list register (cnrgpt) can module last out-pointer register (cnlopt) can module transmit history list register (cntgpt) can module time stamp register (cnts) message buffer registers can message data byte 01 register m (cnmdata01m) can message data byte 0 register m (cnmdata0m) can message data byte 1 register m (cnmdata1m) can message data byte 23 register m (cnmdata23m) can message data byte 2 register m (cnmdata2m) can message data byte 3 register m (cnmdata3m) can message data byte 45 register m (cnmdata45m) can message data byte 4 register m (cnmdata4m) can message data byte 5 register m (cnmdata5m) can message data byte 67 register m (cnmdata67m) can message data byte 6 register m (cnmdata6m) can message data byte 7 register m (cnmdata7m) can message data length register m (cnmdlcm)
751 chapter 18 afcan controller user?s manual u16580ee2v0ud00 remarks: 1. can global registers are identified by cngm . can module registers are identified by cn . message buffer registers are identified by cnm . 2. n = 0, 1 (number of channel) m = 0 to 31 (number of buffer) item register name message buffer registers can message register m (cnmconfm) can message id register m (cnmidlm, cnmidhm) can message control register m (cnmctrlm) table 18-18: list of can controller registers (2/2)
752 chapter 18 afcan controller user?s manual u16580ee2v0ud00 18.5.2 register access type note: offset of global register area is 000h. the actual register address is calculated as follows: remark: n = 0, 1 (number of channel) table 18-19: can global register access types offset address note register name symbol r/w bit manipulation units default value 1816 00h can global control register cngmctrl r/w ? ? 0000h 02h can global clock selection register cngmcs r/w ? ?0fh 04h can global configuration register cngmconf r ? 19h 06h can global automatic block transmission control register cngmabt r/w ? ? 0000h 08h can global automatic block transmission delay register cngmabtd r/w ? ? 00h register address = peripheral programmable area address (bpc) (01ffc000h, when recommended bpc value is set) + channel offset (refer to table 18-1 ) + global register area offset (= 000h) + offset address as listed in table 18-19 above
753 chapter 18 afcan controller user?s manual u16580ee2v0ud00 note: offset of can module register area is 040h. the actual register address is calculated as follows: remark: n = 0, 1 (number of channel) table 18-20: can module register access types offset address note register name symbol r/w bit manipulation units default value 1816 00h can module mask 1 register cnmask1l r/w ? ? undefined 02h cnmask1h 04h can module mask 2 register cnmask2l r/w ? ? undefined 06h cnmask2h 08h can module mask 3 register cnmask3l r/w ? ? undefined 0ah cnmask3h 0ch can module mask 4 register cnmask4l r/w ? ? undefined 0eh cnmask4h 10h can module control register cnctrl r/w ? ? 0000h 12h can module last error code register cnlec r/w ? ?00h 13h can module information register cninfo r ? ?00h 14h can module error counter register cnerc r ? ? 0000h 16h can module interrupt enable register cnie r/w ? ? 0000h 18h can module interrupt status register cnints r/w ? ? 0000h 1ah can module bit rate prescaler register cnbrp r/w ? ?ffh 1ch can module bit rate register cnbtr r/w ? ? 370fh 1eh can module last in-pointer register cnlipt r ? ? undefined 20h can module receive history list register cnrgpt r/w ? ? xx02h 22h can module last out-pointer register cnlopt r ? ? undefined 24h can module transmit history list register cntgpt r/w ? ? xx02h 26h can module time stamp register cnts r/w ? ? 0000h register address = peripheral programmable area address (bpc) (01ffc000h, when recommended bpc value is set) + channel offset (ref. to table 18-1 ) + can module register area offset (= 040h) + offset address as listed in table 18-20 above
754 chapter 18 afcan controller user?s manual u16580ee2v0ud00 note: offset of message buffer area is 100h. the actual register address is calculated as follows: remark: n = 0, 1 (number of channel) m = 0 to 31 (number of buffer) table 18-21: message buffer access types offset address note register name symbol r/w bit manipulation units default value 1816 00h can message data byte 01 register m cnmdata01m r/w ? ? undefined 00h can message data byte 0 register m cnmdata0m r/w ? ? undefined 01h can message data byte 1 register m cnmdata1m r/w ? ? undefined 02h can message data byte 23 register m cnmdata23m r/w ? ? undefined 02h can message data byte 2 register m cnmdata2m r/w ? ? undefined 03h can message data byte 3 register m cnmdata3m r/w ? ? undefined 04h can message data byte 45 register m cnmdata45m r/w ? ? undefined 04h can message data byte 4 register m cnmdata4m r/w ? ? undefined 05h can message data byte 5 register m cnmdata5m r/w ? ? undefined 06h can message data byte 67 register m cnmdata67m r/w ? ? undefined 06h can message data byte 6 register m cnmdata6m r/w ? ? undefined 07h can message data byte 7 register m cnmdata7m r/w ? ? undefined 08h can message data length register m cnmdlcm r/w ? ? 0000xxxxb 09h can message configuration register m cnmconfm r/w ? ? undefined 0ah can message id register m cnmidlm r/w ? ? undefined 0ch cnmidhm 0eh can message control register m cnmctrlm r/w ? ? 00x00000 000xx000b register address = peripheral programmable area address (bpc) (01ffc000h, when recommended bpc value is set) + channel offset (ref. to table 18-1 ) + message buffer area offset (= 100h) + message buffer offset (= m 020h) + offset address as listed in table 18-21 above
755 chapter 18 afcan controller user?s manual u16580ee2v0ud00 18.5.3 register bit configuration remark: n = 0, 1 (number of channel) m = 0 to 31 (number of buffer) table 18-22: bit configuration of can global registers offset address symbol bit 7/15 bit 6/14 bit 5/13 bit 4/12 bit 3/11 bit 2/10 bit 1/9 bit 0/8 00hcngmctrl (w)0000000clear gom 01h 000000set efsd set gom 00hcngmctrl (r)000000efsdgom 01h mbon0000000 02h cngmcs 0 0 0 0 ccp3 ccp2 ccp1 ccp0 04h cngmconf undefined (reserved for future use) gconf5 gconf4 gconf3 gconf2 gconf1 gconf0 06hcngmabt (w)0000000clear abttrg 07h 000000set abtclr set abttrg 06hcngmabt (r)000000abtclrabttrg 07h 00000000 08h cngmabtd 0 0 0 0 abtd3 abtd2 abtd1 abtd0
756 chapter 18 afcan controller user?s manual u16580ee2v0ud00 table 18-23: bit configuration of can module registers (1/2) offset address symbol bit 7/15 bit 6/14 bit 5/13 bit 4/ 12 bit 3/11 bit 2/10 bit 1/9 bit 0/8 00h cnmask1l cm1id [7:0] 01h cm1id [15:8] 02h cnmask1h cm1id [23:16] 03h 0 0 0 cm1id [28:24] 04h cnmask2l cm2id [7:0] 05h cm2id [15:8] 06h cnmask2h cm2id [23:16] 07h 0 0 0 cm2id [28:24] 08h cnmask3l cm3id [7:0] 09h cm3id [15:8] 0ah cnmask3h cm3id [23:16] 0bh 0 0 0 cm3id [28:24] 0ch cnmask4l cm4id [7:0] 0dh cm4id [15:8] 0eh cnmask4h cm4id [23:16] 0fh 0 0 0 cm4id [23:16] 10h cnctrl (w) 0 clear al clear valid clear psmode1 clear psmode0 clear opmode2 clear opmode1 clear opmode0 11h set ccerc set al 0 set psmode1 set psmode0 set opmode2 set opmode1 set opmode0 10h cnctrl (r) ccerc al valid psmode1 psmode0 opmode2 opmode1 opmode0 11h 000000rstattstat 12hcnlec (w) 00000000 12h cnlec (r) 0 0 0 0 0 lec2 lec1 lec0 13h cninfo 0 0 0 boff tecs1 tecs0 recs1 recs0 14h cnerc tec[7:0] 15h reps rec[6:0] 16h cnie (w) 0 0 clear cie5 clear cie4 clear cie3 clear cie2 clear cie1 clear cie0 17h 0 0 set cie5 set cie4 set ci e3 set cie2 set cie1 set cie0 16h cnie (r) 0 0 cie5 cie4 cie3 cie2 cie1 cie0 17h 00000000 18h cnints (w) 0 0 clear cints5 clear cints4 clear cints3 clear cints2 clear cints1 clear cints0 19h 00000000 18h cnints (r) 0 0 cints5 cints4 cints3 cints2 cints1 cints0 19h 00000000 1ah cnbrp tqprs[7:0] 1bh ? access prohibited (reserved for future use) 1ch cnbtr 0 0 0 0 tseg1[3:0] 1dh 0 0 sjw[1:0] 0 tseg2[2:0]
757 chapter 18 afcan controller user?s manual u16580ee2v0ud00 remark: n = 0, 1 (number of channel) 1eh cnlipt lipt[7:0] 1fh ? access prohibited (reserved for future use) 20hcnrgpt (w)0000000clear rovf 21h 00000000 20hcnrgpt (r) 000000rhpmrovf 21h rgpt[7:0] 22h cnlopt lopt[7:0] 23h ? access prohibited (reserved for future use) 24hcntgpt (w)0000000clear tovf 25h 00000000 24hcntgpt (r) 000000thpmtovf 25h tgpt[7:0] 26h cnts (w) 0 0 0 0 0 clear tslock clear tssel clear tsen 27h 00000set tslock set tssel set tsen 26h cnts (r) 0 0 0 0 0 tslock tssel tsen 27h 00000000 28h- 3fh ? access prohibited (reserved for future use) table 18-23: bit configuration of can module registers (2/2) offset address symbol bit 7/15 bit 6/14 bit 5/13 bit 4/12 bit 3/11 bit 2/10 bit 1/9 bit 0/8
758 chapter 18 afcan controller user?s manual u16580ee2v0ud00 remark: n = 0, 1 (number of channel) m = 0 to 31 (number of buffer) table 18-24: bit configuration of message buffer registers offset address symbol bit 7/15 bit 6/14 bit 5/13 bit 4/ 12 bit 3/11 bit 2/10 bit 1/9 bit 0/8 00h cnmdata01m message data (byte0) 01h message data (byte1) 00h cnmdata0m message data (byte 0) 01h cnmdata1m message data (byte 1) 02h cnmdata23m message data (byte 2) 03h message data (byte 3) 02h cnmdata2m message data (byte 2) 03h cnmdata3m message data (byte 3) 04h cnmdata45m message data (byte 4) 05h message data (byte 5) 04h cnmdata4m message data (byte 4) 05h cnmdata5m message data (byte 5) 06h cnmdata67m message data (byte 6) 07h message data (byte 7) 06h cnmdata6m message data (byte 6) 07h cnmdata7m message data (byte 7) 08h cnmdlcm 0 mdlc3 mdlc2 mdlc1 mdlc0 09h cnmconfm ows rtr mt2 mt1 mt0 0 0 ma0 0ah cnmidlm id7 id6 id5 id4 id3 id2 id1 id0 0bh id15 id14 id13 id12 id11 id10 id9 id8 0ch cnmidhm id23 id22 id21 id20 id19 id18 id17 id16 0dh ide 0 0 id28 id27 id26 id25 id24 0eh cnmctrlm (w) 0 0 0 clear mow clear ie clear dn clear trq clear rdy 0fh 0 0 0 0 set ie 0 set trq set rdy 0eh cnmctrlm (r) 000mowiedntrqrdy 0fh 00muc00000 10-1fh ? access prohibited (reserved for future)
759 chapter 18 afcan controller user?s manual u16580ee2v0ud00 18.6 control registers 18.6.1 can global control register (cngmctrl) the cngmctrl register is a 16-bit register used to control the operation of the can module. this register can be read in 16-bit, 8-bit or 1-bit units. write operation can be performed by a special bit set/clear function as described in 18.7 bit set/clear function . reset input clears this register to 0000h. figure 18-23: can global control register (cngmctrl) (1/2) (a) read operation cautions: 1. while the mbon bit is cleared (to 0), software access to the message buffers (cnmdata0m to cnmdata7m, cnmdata01m, cnmdata23m, cnmdata45m, cnmdata67m, cnmdlcm, cnmconfm, cnmidlm, cnmidhm, and cnmctrlm), or registers related to transmit history or receive history (cnlopt, cntgpt, cnlipt, and cnrgpt) is disabled. 2. the mbon bit is read-only. even if 1 is written to mbon while it is 0, the value of mbon does not change, and access to the message buffer registers, or registers related to transmit history or receive history remains disabled. caution: to request forced shut down, the gom bit must be cleared to 0 immediately after the efsd bit has been set to 1. if access to another register (including reading the cngmctrl register) is executed without clearing the gom bit immediately after the efsd bit has been set to 1, the efsd bit is forcibly cleared to 0, and the forced shut down request is invalid. after reset: 0000h read offset address: 000h 15 14 13 12 11 10 9 8 cngmctrlmbon0000000 (n = 0, 1) 76543210 000000efsdgom mbon bit enabling access to me ssage buffer register, transmit/receive history list registers 0 write access and read access to the message buffer register and the transmit/receive history list registers is disabled. 1 write access and read access to the message buffer register and the transmit/receive history list registers is enabled. ? mbon bit is cleared (to 0) when the can module enters can sleep mode/can stop mode or gom bit is cleared (to 0). ? mbon bit is set (to 1) when the can slee p mode/the can stop mode is released or gom bit is set (to 1). efsd bit enabling forced shut down 0 forced shut down by gom = 0 disabled. 1 forced shut down by gom = 0 enabled.
760 chapter 18 afcan controller user?s manual u16580ee2v0ud00 figure 18-23: can global control register (cngmctrl) (2/2) caution: the gom bit can be cleared only in the initialization mode or immediately after efsd bit is set (to 1). (b) write operation remark: n = 0, 1 gom global operation mode bit 0 can module is disabled from operating. 1 can module is enabled to operate. after reset: ? write offset address: 000h 15 14 13 12 11 10 9 8 cngmctrl000000 set efsd set gom (n = 0, 1) 76543210 0000000 clear gom set efsd efsd bit setting 0 no change in esfd bit 1 efsd bit set to 1 set gom clear gom gom bit setting 0 1 gom bit cleared to 0 1 0 gom bit set to 1 other than above no change in gom bit
761 chapter 18 afcan controller user?s manual u16580ee2v0ud00 18.6.2 can global clock sel ection register (cngmcs) the cngmcs register is an 8-bit register used to select the can module system clock. this register can be read or written in 8-bit or 1-bit units. reset input clears this register to 0fh. figure 18-24: can global clock se lection register (cngmcs) remarks: 1. f can = clock supply to can = f xx /4 2. n = 0, 1 after reset: 0fh r/w offset address: 002h 76543210 cngmcs0000ccp3ccp2ccp1ccp0 (n = 0, 1) ccp3 ccp2 ccp1 ccp1 can module system clock (f canmod ) 0000 f can /1 0001 f can /2 0010 f can /3 0011 f can /4 0100 f can /5 0101 f can /6 0110 f can /7 0111 f can /8 1000 f can /9 1001 f can /10 1010 f can /11 1011 f can 12 1100 f can /13 1101 f can /14 1110 f can /15 1111 f can /16 (default value)
762 chapter 18 afcan controller user?s manual u16580ee2v0ud00 18.6.3 can global automatic block transmission control register (cngmabt) the cngmabt register is a 16-bit register used to control the automatic block transmission (abt) operation. this register can be read in 16-bit, 8-bit or 1-bit uni ts. write operation can be performed by a special bit set/clear function as described in 18.7 bit set/clear function . reset input clears this register to 0000h. figure 18-25: can global automatic block tran smission control register (cngmabt) (1/2) (a) read operation remark: n = 0, 1 after reset: 0000h read offset address: 006h 15 14 13 12 11 10 9 8 cngmabt00000000 (n = 0, 1) 76543210 000000abtclrabttrg abtclr automatic block transmission engine clear status bit 0 clearing the automatic transmission engine is completed 1 the automatic transmission engine is being cleared. ? set the abtclr bit to 1 while the abttrg bit is cleared (0). the operation is not guaranteed if the abtcl r bit is set to 1 while the abttrg bit is set to 1. ? when the automatic block transmission engine is cleared by setting the abtclr bit to 1, the abtclr bit is automatically cleared to 0 as soon as the requested clearing processing is complete. abttrg automatic block transmission status bit 0 automatic block transmission is stopped. 1 automatic block transmission is under execution.
763 chapter 18 afcan controller user?s manual u16580ee2v0ud00 figure 18-25: can global automatic block transmission control register (cngmabt) (2/2) (b) write operation cautions: 1. before changing the normal operation mode with abt to the initialization mode, be sure to set the cngmabt register to the default value (00h). 2. do not set the abttrg bit (abttrg = 1) in the initialization mode. if the abttrg bit is set in the initialization mode, the operation is not guaranteed after the can module has entered the normal operation mode with abt. remark: n = 0, 1 after reset: ? write offset address: 006h 15 14 13 12 11 10 9 8 cngmabt000000 set abtclr set abttrg (n = 0, 1) 76543210 0000000 clear abttrg set abtclr automatic block transmission engine clear request bit 0 the automatic block transmission engine is in idle state or under operation. 1 request to clear the automatic block transmission engine. after the auto- matic block transmission engine has been cleared, automatic block trans- mission is started from message buffer 0 by setting the abttrg bit to 1. set abttrg clear abttrg automatic block transmission start bit 0 1 request to stop automatic block transmission. 1 0 request to start automatic block transmission. other than above no change in abttrg bit.
764 chapter 18 afcan controller user?s manual u16580ee2v0ud00 18.6.4 can global configur ation register (cngmconf) the cngmconf register a 16-bit register that provides the configuration information of the can module. this register can be read only in 16-bit, 8-bit or 1-bit units. reset input clears this register to 0011h. figure 18-26: can global configuration register (cngmconf) notes: 1. undefined (reserved for future use) 2. this is not the number of the channels of the device. remark: n = 0, 1 after reset: 0011h read offset address: 004h 15 14 13 12 11 10 9 8 cngmconf note 1 gconf8 (n = 0, 1) 76543210 note 1 gconf5 gconf4 gconf3 gconf2 gconf1 gconf0 gconf8 mirror function for diag macro 0 no mirror function is implemented 1 mirror function is implemented gconf5 gconf4 gconf3 number of message buffers 0 0 1 16 message buffers 0 1 0 32 message buffers 0 1 1 48 message buffers other than above reserved gconf2 gconf1 gconf0 number of can interface channels note 2 0 0 1 1 can interface channels other than above reserved
765 chapter 18 afcan controller user?s manual u16580ee2v0ud00 18.6.5 can global automatic block transmission delay register (cngmabtd) the cngmabtd register is an 8-bit register used to set the interval at which the data of the message buffer assigned to abt is to be transmitted in the normal operation mode with abt. this register can be read or written in 8-bit or 1-bit units. reset input clears this register to 00h. figure 18-27: can global automatic block transmission delay register (cngmabtd) cautions: 1. do not change the contents of the cngmabtd register while the abttrg bit is set to 1. 2. the timing at which the abt message is actually transmitted onto the can bus differs depending on the status of transmission from the other station or how a request to transmit a message other than an abt message (message buffers 8 to m max ?1) is made. remark: n = 0, 1 m max = 32 after reset: 00h r/w offset address: 008h 76543210 cngmabt0000abtd3abtd2abtd1abtd0 (n = 0, 1) abtd3 abtd2 abtd1 abtd0 data frame interval during automatic block transmission (unit: data bit time (dbt)) 0000 0 dbt (default value) 0001 2 5 dbt 0010 2 6 dbt 0011 2 7 dbt 0100 2 8 dbt 0101 2 9 dbt 0110 2 10 dbt 0111 2 11 dbt 1000 2 12 dbt other than above setting prohibited
766 chapter 18 afcan controller user?s manual u16580ee2v0ud00 18.6.6 can module mask control registers (cnmaskml, cnmaskmh) the cnmaskml and cnmaskmh regist ers are 16-bit regi sters used to exte nd the number of receivable messages into the same message buffer by masking part of the id comparison of a message and invalidating the id of the masked part. these registers can be read and written in 16-bit, 8-bit or 1-bit units. after reset input the registers are undefined. figure 18-28: can module n mask 1 registers l, h (cnmask1l, cnmask1h) remarks: 1. masking is always defined by an id length of 29 bits. if a mask is assigned to a message with a standard id, cmid17 to cmid0 are ignored. therefore, only cmid28 to cmid18 of the received id are masked. the same mask can be used for both the standard and extended ids. 2. n = 0, 1 m = 1 to 4 x = 0 to 28 after reset: undefined r/w offset address: 000h 15 14 13 12 11 10 9 8 cnmask1l cmid15 cmid14 cmid13 cmi d12 cmid11 cmid10 cmid9 cmid8 (n = 0, 1) 76543210 cmid7 cmid6 cmid5 cmid4 cmid3 cmid2 cmid1 cmid0 after reset: undefined r/w offset address: 002h 15 14 13 12 11 10 9 8 cnmask1h 0 0 0 cmid28 cmid27 cmid26 cmid25 cmid24 (n = 0, 1) 76543210 cmid23 cmid22 cmid21 cmid20 cmid19 cmid18 cmid17 cmid16 cmidx sets mask pattern of id bit. 0 the id bit x of the message buffer is co mpared with the id bit x of the received message frame 1 the id bit x of the message buffer is not compared with the id bit x of the received message frame (id bit x is masked).
767 chapter 18 afcan controller user?s manual u16580ee2v0ud00 figure 18-29: can module n mask 2 regist ers l. h (cnmask2l, cnmask2h) remarks: 1. masking is always defined by an id length of 29 bits. if a mask is assigned to a message with a standard id, cmid17 to cmid0 are ignored. therefore, only cmid28 to cmid18 of the received id are masked. the same mask can be used for both the standard and extended ids. 2. n = 0, 1 x = 0 to 28 after reset: undefined r/w offset address: 004h 15 14 13 12 11 10 9 8 cnmask2l cmid15 cmid14 cmid13 cmi d12 cmid11 cmid10 cmid9 cmid8 (n = 0, 1) 76543210 cmid7 cmid6 cmid5 cmid4 cmid3 cmid2 cmid1 cmid0 after reset: undefined r/w offset address: 006h 15 14 13 12 11 10 9 8 cnmask2h 0 0 0 cmid28 cmid27 cmid26 cmid25 cmid24 (n = 0, 1) 76543210 cmid23 cmid22 cmid21 cmid20 cmid19 cmid18 cmid17 cmid16 cmidx sets mask pattern of id bit. 0 the id bit x of the message buffer is compared with the id bit x of the received message frame 1 the id bit x of the message buffer is not compared with the id bit x of the received message frame (id bit x is masked).
768 chapter 18 afcan controller user?s manual u16580ee2v0ud00 figure 18-30: can module n mask 3 registers (cnmask3l, cnmask3h)) remarks: 1. masking is always defined by an id length of 29 bits. if a mask is assigned to a message with a standard id, cmid17 to cmid0 are ignored. therefore, only cmid28 to cmid18 of the received id are masked. the same mask can be used for both the standard and extended ids. 2. n = 0, 1 x = 0 to 28 after reset: undefined r/w offset address: 008h 15 14 13 12 11 10 9 8 cnmask3l cmid15 cmid14 cmid13 cmi d12 cmid11 cmid10 cmid9 cmid8 (n = 0, 1) 76543210 cmid7 cmid6 cmid5 cmid4 cmid3 cmid2 cmid1 cmid0 after reset: undefined r/w offset address: 00ah 15 14 13 12 11 10 9 8 cnmask3h 0 0 0 cmid28 cmid27 cmid26 cmid25 cmid24 (n = 0, 1) 76543210 cmid23 cmid22 cmid21 cmid20 cmid19 cmid18 cmid17 cmid16 cmidx sets mask pattern of id bit. 0 the id bit x of the message buffer is co mpared with the id bit x of the received message frame 1 the id bit x of the message buffer is not compared with the id bit x of the received message frame (id bit x is masked).
769 chapter 18 afcan controller user?s manual u16580ee2v0ud00 figure 18-31: can module n mask 4 registers (cnmask4 l, cnmask4h)) remarks: 1. masking is always defined by an id length of 29 bits. if a mask is assigned to a message with a standard id, cmid17 to cmid0 are ignored. therefore, only cmid28 to cmid18 of the received id are masked. the same mask can be used for both the standard and extended ids. 2. n = 0, 1 x = 0 to 28 after reset: undefined r/w offset address: 00ch 15 14 13 12 11 10 9 8 cnmask4l cmid15 cmid14 cmid13 cmi d12 cmid11 cmid10 cmid9 cmid8 (n = 0, 1) 76543210 cmid7 cmid6 cmid5 cmid4 cmid3 cmid2 cmid1 cmid0 after reset: undefined r/w offset address: 00eh 15 14 13 12 11 10 9 8 cnmask4h 0 0 0 cmid28 cmid27 cmid26 cmid25 cmid24 (n = 0, 1) 76543210 cmid23 cmid22 cmid21 cmid20 cmid19 cmid18 cmid17 cmid16 cmidx sets mask pattern of id bit. 0 the id bit x of the message buffer is compared with the id bit x of the received message frame 1 the id bit x of the message buffer is not compared with the id bit x of the received message frame (id bit x is masked).
770 chapter 18 afcan controller user?s manual u16580ee2v0ud00 18.6.7 can module control register (cnctrl) the cnctrl register is a 16-bit register that controls the operation mode of the can module. this register can be read in 16-bit, 8-bit or 1-bit uni ts. write operation can be performed by a special bit set/clear function as described in 18.7 ?bit set/clear function? on page 801 . reset input clears this register to 0000h. figure 18-32: can module n control register (cnctrl) (1/4) (a) read operation remark: n = 0, 1 after reset: 0000h read offset address: 010h 15 14 13 12 11 10 9 8 cnctrl 0 00000rstattstat (n = 0, 1) 76543210 ccerc al valid psmode1 psmode0 opmode2 opmode1 opmode0 rstat reception status bit 0 reception is stopped 1 reception is in progress the rstat bit is set to 1 under the following conditions (timing) ? the sof bit of a receive frame is detected ? on occurrence of arbitration loss during a transmit frame ? the rstat bit is cleared to 0 under the following conditions (timing) ? when a recessive level is detected at the second bit of the interframe space ? on transition to the initialization mode at the first bit of the interframe space tstat transmission status bit 0 transmission is stopped. 1 transmission is in progress the tstat bit is set to 1 under the following conditions (timing): ? the sof bit of a transmit frame is detected ? the first bit of an error flag is detected during a transmit frame ? the tstat bit is cleared to 0 under the following conditions (timing) ? during transition to bus-off state ? on occurrence of arbitration loss in transmit frame ? on detection of recessive level at th e second bit of the interframe space ? on transition to the initialization mode at the first bit of the interframe space
771 chapter 18 afcan controller user?s manual u16580ee2v0ud00 figure 18-32: cann module control register (cnctrl) format (2/4) caution: transition to and from the can stop mode must be made via can sleep mode. a request for direct transition to and from the can stop mode is ignored. remark: n = 0, 1 ccerc error counter clear bit 0 the cnerc and cninfo registers are not cleared in the initialization mode. 1 the cnerc and cninfo registers are cleared in the initialization mode ? the ccerc bit is used to clear the cnerc an d cninfo registers for re-initialization or forced recovery from the bus-off stat e. this bit can be set to 1 only in the initialization mode. ? when the cnerc and cninfo registers have been cleared, the ccerc bit is also cleared to 0 automatically. ? the ccerc bit can be set to 1 at the sa me time as a request to change the initialization mode to an operation mode is made.4. the ccerc bit is read-only in the can sleep mode or can stop mode. ? the receive data may be broken in case of setting the ccerc bit to (1) immediately after entering the init mode. al bit to set operation in case of arbitration loss 0 re-transmission is not executed in case of an arbitration loss in the single-shot mode 1 re-transmission is executed in case of an arbitration loss in the single-shot mode the al bit is valid only in the single-shot mode. valid valid receive message frame detection bit 0 a valid message frame has not been received since the valid bit was last cleared to 0 1 a valid message frame has been received since the valid bit was last cleared to 0 ? detection of a valid receive message fr ame is not dependent upon storage in the receive message buffer (data frame) or transmit message buffer (remote frame). ? clear the valid bit (0) before changing the initialization mode to an operation mode. ? if only two can nodes are connected to the can bus with one transmitting a message frame in the normal mode and the other in the reception mode, the valid bit is not set to 1 before the transmitting node enters the error passive state. ? in order to clear the valid bit, set the clear valid bit to 1 first and confirm that the valid bit is cleared. if it is not cl eared, perform clearing processing again. psmode1 psmode0 power save mode 0 0 no power save mode is selected 0 1 can sleep mode 1 0 setting prohibited 1 1 can stop mode
772 chapter 18 afcan controller user?s manual u16580ee2v0ud00 figure 18-32: cann module control re gister (cnctrl) format (3/4) (b) write operation remark: n = 0, 1 psmode1 psmode0 power save mode 0 0 no power save mode is selected 0 1 can sleep mode 1 0 setting prohibited 1 1 can stop mode opmode2 opmode1 opmode0 operation mode 0 0 0 no operation mode is selected (can module is in the initialization mode) 0 0 1 normal operating mode 0 1 0 normal operation mode with automatic block transmis- sion function (normal operation mode with abt) 0 1 1 receive-only mode 1 0 0 single-shot mode 1 0 1 self-test mode other than above setting prohibited. the opmode0 to opmode2 bits are read-only in the can sleep mode or can stop mode. after reset: ? write offset address: 010h 15 14 13 12 11 10 9 8 cnctrl set ccerc set al 0 set psmode1 set psmode0 set opmode2 set opmode1 set opmode0 (n = 0, 1) 76543210 0 clear al clear valid clear psmode1 clear psmode0 clear opmode2 clear opmode1 clear opmode0 set ccerc setting of ccerc bit 0 ccerc bit is not changed 1 ccerc bit is set to 1 set al clear al setting of al bit 0 1 al bit is cleared to 0 1 0 al bit is set to 1 1 0 setting prohibited 1 1 can stop mode
773 chapter 18 afcan controller user?s manual u16580ee2v0ud00 figure 18-32: can module n control register (cnctrl) (4/4) remark: n = 0, 1 clear valid setting of ccerc bit 0 valid bit is not changed 1 valid bit is cleared to 0 set psmode0 clear psmode0 setting of psmode0 bit 0 1 psmode0 bit is cleared to 0 1 0 psmode bit is set to 1 other than above psmode0 bit is not changed set psmode1 clear psmode1 setting of psmode1 bit 0 1 psmode1 bit is cleared to 0 1 0 psmode1 bit is set to 1 other than above psmode1 bit is not changed set opmode0 clear opmode0 setting of opmode0 bit 0 1 opmode0 bit is cleared to 0 1 0 opmode0 bit is set to 1 other than above opmode0 bit is not changed set opmode1 clear opmode1 setting of opmode1 bit 0 1 opmode1 bit is cleared to 0 1 0 opmode1 bit is set to 1 other than above opmode1 bit is not changed set opmode2 clear opmode2 setting of opmode2 bit 0 1 opmode2 bit is cleared to 0 1 0 opmode2 bit is set to 1 other than above opmode2 bit is not changed
774 chapter 18 afcan controller user?s manual u16580ee2v0ud00 18.6.8 can module last error code register (cnlec) the cnlec register provides the error information of the can protocol. figure 18-33: can module n last error code register (cnlec) remarks: 1. the contents of the cnlec register are not cleared when the can module changes from an operation mode to the initialization mode. 2. if an attempt is made to write a value other than 00h to the cnlec register by software, the access is ignored. 3. n = 0, 1 after reset: 00h r/w offset address: 012h 76543210 cnlec 0 0 0 0 0 lec2 lec1 lec0 (n = 0, 1) lec2 lec1 lec0 last can protocol error information 000no error 001stuff error 010form error 011ack error 100bit error (the can module tried to transmit a recessive- level bit as part of a transmit message (except the arbitration field), but the value on the can bus is a dominant-level bit.) 1 0 1 bit error (the can module tried to transmit a dominant- level bit as part of a transmit message, ack bit, error frame, or overload frame, but the value on the can bus is a recessive-level bit.) 110crc error 111undefined
775 chapter 18 afcan controller user?s manual u16580ee2v0ud00 18.6.9 can module information register (cninfo) the cninfo register indicates the status of the can module. figure 18-34: can module n information register (cninfo) remark: n = 0, 1 after reset: 00h read offset address: 013h 76543210 cninfo 0 0 0 boff tec1 tec0 rec1 rec0 (n = 0, 1) boff bus-off state bit 0 not bus-off state (transmit error counter 255) (the value of the transmit counter is less than 256) 1 bus-off state (transmit error counter > 255) (the value of the transmit counter is 256 or more) tecs1 tecs0 transmission error counter status bit 0 0 the value of the transmission erro r counter is less than that of the warning level (<96) 0 1 the value of the transmission erro r counter is in the range of the warning level (96 to 127) 10undefined 1 1 the value of the transmission erro r counter is in the range of the error passive or bus-off state ( 128 recs1 recs0 reception error counter status bit 0 0 the value of the reception error counter is less than that of the warning level (<96) 0 1 the value of the reception error counter is in the range of the warning level (96 to 127) 10undefined 1 1 the value of the reception error counter is in the error passive range ( 128)
776 chapter 18 afcan controller user?s manual u16580ee2v0ud00 18.6.10 can module error counter register (cnerc) the cnerc register indicates the count value of the transmission/reception error counter. figure 18-35: can module n error counter register (cnerc) remark: n = 0, 1 after reset: 0000h read offset address: 014h 15 14 13 12 11 10 9 8 cnerc reps rec6 rec5 rec4 rec3 rec 2 rec 1 rec 0 (n = 0, 1) 76543210 tec7 tec6 tec5 tec4 tec3 tec 2 tec 1 tec 0 reps reception error passive status bit 0 the reception error counter is not in the error passive range (< 128) 1 the reception error counter is in the error passive range ( 128) rec6 to rec0 reception error counter bit 0 to 127 number of reception errors. t hese bits reflect the status of the reception error counter. the number of errors is defined by the can protocol. rec6 to rec0 bits of the reception error counter are invalid in the reception error passive state (recs1, recs0 = 11b) tec7 to tec0 transmission error counter bit 0 to 255 number of transmission errors. these bits reflect the status of the transmission error counter. the number of errors is defined by the can protocol. tec7 to tec0 bits of the transmission erro r counter are invalid in the bus-off state (boff = 1).
777 chapter 18 afcan controller user?s manual u16580ee2v0ud00 18.6.11 can module interrupt enable register (cnie) the cnie register is used to enable or disable the interrupts of the can module. figure 18-36: can module n interrupt enable register (cnie) (1/2) (a) read operation remark: n = 0, 1 m = 0 to 5 after reset: 0000h read offset address: 016h 15 14 13 12 11 10 9 8 cnie 00000000 (n = 0, 1) 76543210 0 0 cie5 cie4 cie3 cie 2 cie 1 cie 0 ciem can module interrupt m enable bit 0 can module interrupt m corresponding to interrupt status register cintsm is disabled 1 can module interrupt m corresponding to interrupt status register cintsm is enabled.
778 chapter 18 afcan controller user?s manual u16580ee2v0ud00 figure 18-36: cann module interrupt enable register (cnie) format (2/2) (b) write operation remark: n = 0, 1 m = 0 to 5 after reset: ? write offset address: 016h 15 14 13 12 11 10 9 8 cnie 0 0 set cie5 set ci e4 set cie3 set cie 2 set cie 1 set cie 0 (n = 0, 1) 76543210 0 0 clear cie5 clear cie4 clear cie3 clear cie 2 clear cie 1 clear cie 0 set ciem clear ciem setting of ciem bit 0 1 ciem bit is cleared to 0 1 0 ciem bit is set to 1 other than above ciem bit is not changed
779 chapter 18 afcan controller user?s manual u16580ee2v0ud00 18.6.12 can module interrupt status register (cnints) the cnints register indicates the interrupt status of the can module. figure 18-37: can module n interrupt status register (cnints) (1/2) (a) read operation after reset: 0000h read offset address: 018h 15 14 13 12 11 10 9 8 cnints00000000 (n = 0, 1) 76543210 0 0 cints5 cints4 cints3 cints 2 cints 1 cints 0 cints5 status bit of wakeup interrupt from can sleep mode 0 no wakeup interrupt from can sleep mode is pending 1 wakeup interrupt from can sleep mode is pending the cints5 bit is set only when the can module is woken up from the can sleep mode by a can bus operation. the cints5 bit is not set when the can sleep mode has been released by software. cints4 status bit of arbitration loss interrupt 0 no arbitration loss interrupt is pending 1 arbitration loss interrupt is pending cints3 status bit of can protocol error interrupt 0 no can protocol error interrupt is pending 1 can protocol error interrupt is pending cints2 status bit of can error status interrupt 0 no can error status interrupt is pending 1 can error status interrupt is pending cints1 status bit of interrupt on reception completion 0 no interrupt on completion of reception of valid message frame to message buffer is pending 1 interrupt on completion of reception of valid message frame to message buffer is pending cints1 status bit of interrupt on transmission completion 0 no interrupt on normal completion of transmission of message frame from message buffer is pending 1 interrupt on normal completion of transmission of message frame from message buffer is pending
780 chapter 18 afcan controller user?s manual u16580ee2v0ud00 figure 18-37: can module interrupt status register (cnints) format (2/2) (b) write operation remark: n = 0, 1 m = 0 to 5 after reset: ? write offset address: 018h 15 14 13 12 11 10 9 8 cnints00000000 (n = 0, 1) 76543210 00 clear cints5 clear cints4 clear cints3 clear cints 2 clear cints 1 clear cints 0 clear cintsm setting of ciem bit 1 cintsm bit is cleared to 0 0 cintsm bit is set to 1
781 chapter 18 afcan controller user?s manual u16580ee2v0ud00 18.6.13 can module bit rate prescaler register (cnbrp) the cnbrp register is used to select the can protocol layer basic clock (f tq ). the communication baud rate is set to the cnbtr register. caution: the cnbrp register can be write-accessed only in the initialization mode. figure 18-38: can module n bit rate prescaler register (cnbrp) (a) register format (b) clock supply of can module remarks: 1. f can : clock supplied to can (f can = f xx /4) f canmod : can module system clock f tq : can protocol layer basic system clock 2. n = 0, 1 after reset: ffh r/w offset address: 01ah 76543210 cnbrp tqprs7 tqprs6 tqprs5 tqprs4 tqprs3 tqprs2 tqprs1 tqprs0 (n = 0, 1) tqprs7 to tqprs0 can protocol layer basic system clock (f tq ) 0f canmod /1 1f canmod /2 ... ... nf canmod /(n+1) ... ... 255 f canmod /256 (default value) ccp 3 ccp2 prescaler can module bit-rate prescaler register (cnbrp) can module clock selection register (cngmcs) baud rate generator can bit-rate register (cnbtr) ccp1 ccp0 tqprs0 f can f canmod f tq 0 0 0 0 tqprs1 tqprs2 tqprs3 tqprs4 tqprs5 tqprs6 tqprs7
782 chapter 18 afcan controller user?s manual u16580ee2v0ud00 18.6.14 can module bit rate register (cnbtr) the cnbtr register is used to control the data bit time of the communication baud rate. figure 18-39: can module n bit rate register (cnbtr) (1/2) (a) register format remark: n = 0, 1 after reset: 370fh r/w offset address: 01ch 15 14 13 12 11 10 9 8 cnbtr 0 0 sjw1 sjw0 0 tseg22 tseg21 tseg20 (n = 0, 1) 76543210 0 0 0 0 tseg13 tseg12 tseg11 tseg10 sjw1 sjw0 length of synchronization jump width 00 1tq 01 2tq 10 3tq 1 1 4tq (default value) tseg22 tseg21 tseg20 length of time segment 2 000 1tq 001 2tq 010 3tq 011 4tq 100 5tq 101 6tq 110 7tq 1 1 1 8tq (default value)
783 chapter 18 afcan controller user?s manual u16580ee2v0ud00 figure 18-39: can module n bit rate register (cnbtr) (2/2) note: this setting must not be made when the cnbrp register = 00h. remarks: 1. tq = 1/f tq (f tq : can protocol layer basic system clock) 2. n = 0, 1 (b) definition of data bit time tseg13 tseg12 tseg11 tseg10 le ngth of time segment 1 0000 setting prohibited. 0001 2tq note 0010 3tq note 0011 4tq 0100 5tq 0101 6tq 0110 7tq 0111 8tq 1000 9tq 1001 10tq 1010 11tq 1011 12tq 1100 13tq 1101 14tq 1110 15tq 1111 16tq (default value) data bit time (dbt) time segment 1 (tseg1) phase segment 2 phase segment 1 sample point(spt) prop segment sync segment time segment 2 (tseg2)
784 chapter 18 afcan controller user?s manual u16580ee2v0ud00 18.6.15 can module last in-pointer register (cnlipt) the cnlipt register indicates the number of the message buffer in which a data frame or a remote frame was last stored. figure 18-40: can module n last in-pointer register (cnlipt) note: m max = 32 (maximum number of message buffer) values greater than (m max ?1) are prohibited. remarks: 1. the read value of the cnlipt register is undefined if a data frame or a remote frame has never been stored in the message buffer. if the rhpm bit of the cnrgpt register is set to 1 after the can module has changed from the initialization mode to an operation mode, therefore, the read value of the cnlipt register is undefined. 2. n = 0, 1 after reset: undefined r/w offset address: 01eh 76543210 cnlipt lipt7 lipt6 lipt5 lip t4 lipt3 lipt2 lipt1 lipt0 (n = 0, 1) lipt7 to lipt0 last in-pointer register (cnlipt) 0 to (m max ?1) note when the cnlipt register is r ead, the contents of the element indexed by the last in-pointer (lipt) of the receive history list are read. these contents indicate the nu mber of the message buffer in which a data frame or a remote frame was last stored
785 chapter 18 afcan controller user?s manual u16580ee2v0ud00 18.6.16 can module receive history list register (cnrgpt) the cnrgpt register is used to read the receive history list. figure 18-41: can module n receive histor y list register (cnrgpt) (1/2) (a) read operation notes: 1. m max = 32 (maximum number of message buffer) values greater than (m max ?1) are prohibited. 2. the receive history list will be updated, but the lipt pointer will not be incremented. always the position the lipt pointer -1 is pointing to is overwritten. remark: n = 0, 1 after reset: xx02h rea d offset address: 020h 15 14 13 12 11 10 9 8 cnrgpt rgpt7 rgpt6 rgpt5 rgp t4 rgpt3 rgpt2 rgpt1 rgpt0 (n = 0, 1) 76543210 000000rhpmrovf rgpt7 to rgpt0 receive history list get pointer 0 to (m max ?1) note 1 when the cnrgpt register is r ead, the contents of the element indexed by the receive history list get pointer (rgpt) of the receive history list are read. these conten ts indicate the number of the message buffer in which a data frame or a remote frame has been stored. remark: the read value of rgpt0 to 7 is invalid when rhpm = 1. rhpm receive history list pointer match 0 the receive history list has at least o ne message buffer number that has not been read. 1 the receive history list has no message buffer numbers that has not been read. rovf receive history list overflow bit 0 all the message buffer numbers that have not been read are preserved. all the numbers of the message buffer in which a new data frame or remote frame has been received and stored are recorded to the receive history list (the receive history list has a vacant element). 1 at least 23 entries have been stored sinc e the host processor has serviced the rhl last time (i.e. read cnrgpt). thus the sequence of receptions can not be recovered completely now. the first 22 entries are sequentially stored while the last entry can have been overwritten by newly received messages multiple times because all buffer numbers are stored at position lipt-1 when rovf bit is set. note 2
786 chapter 18 afcan controller user?s manual u16580ee2v0ud00 figure 18-41: can module n receive history list register (cnrgpt) (2/2) (b) write operation remark: n = 0, 1 after reset: ? write offset address: 020h 15 14 13 12 11 10 9 8 cnrgpt00000000 (n = 0, 1) 76543210 0000000 clear rovf clear rovf setting of rovf bit 0 rovf bit is not changed 1 rovf bit is cleared to 0
787 chapter 18 afcan controller user?s manual u16580ee2v0ud00 18.6.17 can module last out-pointer register (cnlopt) the cnlopt register indicates the number of the message buffer to which a data frame or a remote frame was transmitted last. figure 18-42: can module n last out-pointer register (cnlopt) note: m max = 32 remarks: 1. the value read from the cnlopt register is undefined if a data frame or remote frame has never been transmitted from a message buffer. if the thpm bit is set to 1 after the can module has changed from the initialization mode to an operation mode, therefore, the read value of the cnlopt register is undefined. 2. n = 0, 1 after reset: undefined read offset address: 022h 76543210 cnlopt lopt7 lopt6 lopt5 lopt4 lopt3 lopt2 lopt1 lopt0 (n = 0, 1) lopt7 to lopt0 last out-pointer of transmit history list (lopt) 0 to (m max ?1) note when the cnlopt register is read , the contents of the element indexed by the last out-pointer (lopt) of the receive history list are read. these contents indicate the nu mber of the message buffer to which a data frame or a remote frame was transmitted last.
788 chapter 18 afcan controller user?s manual u16580ee2v0ud00 18.6.18 can module transmit history list register (cntgpt) the cntgpt register is used to read the transmit history list. figure 18-43: can module n transmit history list register (cntgpt) (1/2) (a) read operation notes: 1. m max = 32 2. the thl will be updated, but the lopt pointer will not be in cremented. always the position the lopt pointer -1 is pointing to is overwritten. remarks: 1. transmission from message buffer 0 to 7 is not recorded to the transmit history list in the normal operation mode with abt. 2. n = 0, 1 after reset: xx02h read offset address: 024h 15 14 13 12 11 10 9 8 cntgpt tgpt7 tgpt6 tgpt5 tgpt4 tgpt3 tgpt2 tgpt1 tgpt0 (n = 0, 1) 76543210 000000thpmtovf tgpt7 to tgpt0 transmit history list read pointer 0 to (m max ?1) note 1 when the cntgpt register is r ead, the contents of the element indexed by the read pointer (tgpt) of the transmit history list are read. these contents indicate the number of the message buffer to which a data frame or a remote frame was transmitted last. remark: the read value of tgpt0 to tgpt7 is invalid when thpm = 1. thpm transmit history pointer match 0 the transmit history list has at leas t one message buffer number that has not been read. 1 the transmit history list has no message buffer number that has not been read. tovf transmit history list overflow bit 0 all the message buffer numbers that ha ve not been read are preserved.all the numbers of the message buffers to which a new data frame or remote frame has been transmitted are recorded to t he transmit history list (the transmit history list has a vacant element) 1 at least 7 entries have been stored since the host processor has serviced the thl last time (i.e. read cntgpt). th us the sequence of transmissions can not be recovered completely now. the first 6 entries are sequentially stored while the last entry can have been overwritten by newly transmitted messages multiple times because all buffer numbers are stored at position lopt-1 when tovf bit is set. note 3
789 chapter 18 afcan controller user?s manual u16580ee2v0ud00 figure 18-43: can module n transmit hist ory list register (cntgpt) (2/2) (b) write operation remark: n = 0, 1 after reset: ? write offset address: 024h 15 14 13 12 11 10 9 8 cntgpt00000000 (n = 0, 1) 76543210 0000000 clear tovf clear tovf setting of tovf bit 0 tovf bit is not changed 1 tovf bit is cleared to 0
790 chapter 18 afcan controller user?s manual u16580ee2v0ud00 18.6.19 can module time stamp register (cnts) the cnts register is used to control the time stamp function. figure 18-44: can module time stamp register (cnts) (1/2) (a) read operation remarks: 1. the displayed cnts register provides only the necessary bits for the basic time stamp function. the advanced time stamp function requires a modified hardware. 2. the lock function of the time stamp function must not be used when the can module is in the normal operation mode with abt 3. n = 0, 1 after reset: 0000h read offset address: 026h 15 14 13 12 11 10 9 8 cnts00000000 (n = 0, 1) 76543210 0 0 0 0 0 tslock tssel tsen tslock time stamp lock function enable bit 0 time stamp lock function stopped. the tsout signal is toggled each time the selected time stamp capture event occurs. 1 time stamp lock function enabled. the tsout signal is toggled each time the selected time stamp capture event occurs. however, the tsout output signal is locked when a data frame has been correctly received to message buffer 0. ? when tslock is set (1) and a data frame has been correctly received to message buffer 0, the tsout output signal is locked. ? when the tsout output signal is locked the tsen bit is cleared (0) automatically. tssel time stamp capture event selection bit 0 the time capture event is sof 1 the time stamp capture event is the last bit of eof tsen tsout operation setting bit 0 disable tsout toggle operation 1 enable tsout toggle operation when the tsen bit is set (1) the tsout signal is toggled each time the selected time stamp capture event occurs.
791 chapter 18 afcan controller user?s manual u16580ee2v0ud00 figure 18-44: can module time stamp register (cnts) (2/2) (b) write operation remark: n = 0, 1 after reset: ? write offset address: 026h 15 14 13 12 11 10 9 8 cnts00000 set tslock set tssel set tsen (n = 0, 1) 76543210 00000 clear tslock clear tssel clear tsen set tslock clear tslock setting of tslock bit 0 1 tslock bit is cleared to 0 1 0 tslock bit is set to 1 other than above tslock bit is not changed set tssel clear tssel setting of tssel bit 0 1 tssel bit is cleared to 0 1 0 tssel bit is set to 1 other than above tssel bit is not changed set tsen clear tsen setting of tsen bit 0 1 tsen bit is cleared to 0 1 0 tsen bit is set to 1 other than above tsen bit is not changed
792 chapter 18 afcan controller user?s manual u16580ee2v0ud00 18.6.20 can message data byte register (cnmdataxm) (x = 0 to 7), (cnmdatazm) (z = 01, 23, 45, 67) the cnmdataxm, cnmdatazm registers are used to store the data of a transmit/receive message. the cnmdatazm registers can access the cnmdataxm registers in 16-bit units. figure 18-45: can message data byte register (1/2) (a) (cnmdataxm) (x = 0 to 7) remark: n = 0, 1; m = 0 to 31 after reset: undefined r/w offset address: 000h 76543210 cnmdata0m mdata07 mdata06 mdata05 mdata04 mdata03 mdata02 mdata01 mdata00 (n = 0, 1) after reset: undefined r/w offset address: 001h 76543210 cnmdata1m mdata17 mdata16 mdata15 mdata14 mdata13 mdata12 mdata11 mdata10 (n = 0, 1) after reset: undefined r/w offset address: 002h 76543210 cnmdata2m mdata27 mdata26 mdata25 mdata24 mdata23 mdata22 mdata21 mdata20 (n = 0, 1) after reset: undefined r/w offset address: 003h 76543210 cnmdata3m mdata37 mdata36 mdata35 mdata34 mdata33 mdata32 mdata31 mdata30 (n = 0, 1) after reset: undefined r/w offset address: 004h 76543210 cnmdata4m mdata47 mdata46 mdata45 mdata44 mdata43 mdata42 mdata41 mdata40 (n = 0, 1) after reset: undefined r/w offset address: 005h 76543210 cnmdata5m mdata57 mdata56 mdata55 mdata54 mdata53 mdata52 mdata51 mdata50 (n = 0, 1) after reset: undefined r/w offset address: 006h 76543210 cnmdata6m mdata67 mdata66 mdata65 mdata64 mdata63 mdata62 mdata61 mdata60 (n = 0, 1) after reset: undefined r/w offset address: 007h 76543210 cnmdata7m mdata77 mdata76 mdata75 mdata74 mdata73 mdata72 mdata71 mdata70 (n = 0, 1)
793 chapter 18 afcan controller user?s manual u16580ee2v0ud00 figure 18-45: can message da ta byte register (2/2) (b) (cnmdatazm) (z = 01, 23, 45, 67) remark: n = 0, 1 m = 0 to 31 after reset: undefined r/w offset address: 000h 15 14 13 12 11 10 9 8 cnmdata01m mdata0115 mdata0114 mdata0113 mdata0112 mdata0111 mdata0110 mdata019 mdata018 (n = 0, 1) 76543210 mdata017 mdata016 mdata015 mdata014 mdata013 mdata012 mdata011 mdata010 after reset: undefined r/w offset address: 002h 15 14 13 12 11 10 9 8 cnmdata23m mdata2315 mdata2314 mdata2313 mdata2312 mdata2311 mdata2310 mdata239 mdata238 (n = 0, 1) 76543210 mdata237 mdata236 mdata235 mdata234 mdata233 mdata232 mdata231 mdata230 after reset: undefined r/w offset address: 004h 15 14 13 12 11 10 9 8 cnmdata45m mdata4515 mdata4514 mdata4513 mdata4512 mdata4511 mdata4510 mdata459 mdata458 (n = 0, 1) 76543210 mdata457 mdata456 mdata455 mdata454 mdata453 mdata452 mdata451 mdata450 after reset: undefined r/w offset address: 006h 15 14 13 12 11 10 9 8 cnmdata67m mdata6715 mdata6714 mdata6713 mdata6712 mdata6711 mdata6710 mdata679 mdata678 (n = 0, 1) 76543210 mdata677 mdata676 mdata675 mdata674 mdata673 mdata672 mdata671 mdata670
794 chapter 18 afcan controller user?s manual u16580ee2v0ud00 18.6.21 can message data length register m (cnmdlcm) the cnmdlcm register is used to set the number of bytes of the data field of a message buffer. cautions: 1. be sure to set bits 7 to 4 to 0000b. 2. receive data is stored in as many cnmdatax as the number of bytes (however, the upper limit is 8) corresponding to dlc. cnmdatax in which no data is stored is undefined. figure 18-46: can message data length register m (cnmdlcm) note: the data and dlc value actually transmitted to can bus are as follows: remark: n = 0, 1 m = 0 to 31 after reset: undefined r/w offset address: 008h 76543210 cnmdlcm 0 0 0 0 mdlc3 mdlc2 mdlc1^ mdlc0 (n = 0, 1) mdlc3 mdlc2 mdlc1 mdlc0 data length of transmit/receive message 00000 byte 00011 byte 00102 bytes 00113 bytes 01004 bytes 01015 bytes 01106 bytes 01117 bytes 10008 bytes other than above setting prohibited (if these bits are set during transmission, 8-byte data is transmitted regardless of the set dlc value when a data frame is transmitted. however, the dlc actually transmitted to the can bus is the dlc value set to this register.) note type of transmit frame length of transmit data dlc transmitted data frame number of bytes specified by dlc (however, 8 bytes if dlc 8) mdlc[3:0] remote frame 0 bytes
795 chapter 18 afcan controller user?s manual u16580ee2v0ud00 18.6.22 can message configuration register (cnmconfm) the cnmconfm register is used to specify the type of the message buffer and to set a mask. caution: be sure to write 0 to bits 2 and 1 of the cnconfm register. figure 18-47: can message configur ation register (cnmconfm) remark: n = 0, 1 after reset: undefined r/w offset address: 009h 76543210 cnmconfm ows rtr mt2 mt1 mt0 0 0 ma0 (n = 0, 1) ows overwrite select bit 0 the message buffer that has already received a data frame note is not overwritten by a newly received data fram e. the newly received data frame is discarded 1 the message buffer that has already received a data frame note is overwritten by a newly received data frame a remote frame is received and stored, regardless of the setting of bits ows and dn. a remote frame that satisfies the other conditions (id matches, rtr = 0, trq = 0) is always received and stored in the corresponding me ssage buffer (interrupt generated, dn flag set, mdlc0 to mdlc3 bits updated, and recorded to the receive history list). note: the ?message buffer that has already received a data frame? is a receive message buffer whose dn bit has been set to 1. rtr remote frame request bit 0 transmit a data frame 1 transmit a remote frame the rtr bit specifies the type of message fram e that is transmitted from a message buffer defined as a transmit message buffer.even if a valid remote frame has been received, rtr of the transmit message buffer that has received the frame remains cleared to 0.even if a remote frame whose id matches has been received from the can bus with the rtr bit of the transmit message buffer set to 1 to transm it a remote frame, that remote frame is not received or stored (interrupt generated, dn flag set, mdlc 0 to mdlc3 bits updated, and recorded to the receive history list).
796 chapter 18 afcan controller user?s manual u16580ee2v0ud00 figure 18-47: can message configurat ion register (cnmconfm) (2/2) remark: n = 0, 1 mt2 mt1 mt0 message buffer type setting bit 0 0 0 transmit message buffer 0 0 1 receive message buffer (no mask setting) 0 1 0 receive message buffer (mask 1 set) 0 1 1 receive message buffer (mask 2 set) 1 0 0 receive message buffer (mask 3 set) 1 0 1 receive message buffer (mask 4 set) other than above setting prohibited. ma0 message buffer assignment bit 0 message buffer not used 1 message buffer used
797 chapter 18 afcan controller user?s manual u16580ee2v0ud00 18.6.23 can message id register m (cnmidlm, cnmidhm) the cnmidlm and cnmidhm registers are used to set an identifier (id). caution: be sure to write 0 to bits 14 and 13 of the cnmidhm register. figure 18-48: can message id regi ster m (cnmidlm, cnmidhm) remark: n = 0, 1 m = 0 to 31 after reset: undefined r/w offset address: 00ah 15 14 13 12 11 10 9 8 cnmidlm id15 id14 id13 id12 id11 id10 id9 id8 (n = 0, 1) 76543210 id7 id6 id5 id4 id3 id2 id1 id0 after reset: undefined r/w offset address: 00ch 15 14 13 12 11 10 9 8 cnmidhm ide 0 0 id28 id27 id26 id25 id24 (n = 0, 1) 76543210 id23 id22 id21 id20 id19 id18 id17 id16 ide format mode specification bit 0 standard format mode (id28 to id18: 11 bits) note 1 extended format mode (id28 to id0: 29 bits) note: the id17 to id0 bits are not used. id28 to id0 message id id28 to id18 standard id value of 11 bits (when ide = 0) id28 to id0 extended id value of 29 bits (when ide = 1)
798 chapter 18 afcan controller user?s manual u16580ee2v0ud00 18.6.24 can message control register m (cnmctrlm) the cnmctrlm register is used to control the operation of the message buffer. figure 18-49: can message control register m (cnmctrlm) (1/3) (a) read operation remark: n = 0, 1 m = 0 to 31 after reset: undefined read offset address: 00eh 15 14 13 12 11 10 9 8 cnmctrlm00muc00000 (n = 0, 1) 76543210 000mowiedntrqrdy muc message buffer data updating bit 0 the can module is not updating the message buffer (reception and storage) 1 the can module is updating the message buffer (reception and storage) the muc bit is undefined until the firs t reception and storage is performed mow message buffer overwrite status bit 0 the message buffer is not overwritten by a newly received data frame 1 the message buffer is overwritten by a newly received data frame mow is not set to 1 even if a remote frame is received and stored in the transmit message buffer with dn bit = 1. ie message buffer interrupt request enable bit 0 receive message buffer: valid message reception completion interrupt disabled. transmit message buffer: normal message transmission completion interrupt disabled. 1 receive message buffer: valid message reception completion interrupt enabled. transmit message buffer: normal message transmission completion interrupt enabled. dn message buffer data updating bit 0 a data frame or remote frame is not stored in the message buffer 1 a data frame or remote frame is stored in the message buffer
799 chapter 18 afcan controller user?s manual u16580ee2v0ud00 figure 18-49: can message control register m (cnmctrlm) (2/3) (b) write operation remark: n = 0, 1 m = 0 to 31 trq message buffer transmission request bit 0 no message frame transmitting request t hat is pending or being transmitted is in the message buffer. 1 the message buffer is holding transmission of a message frame pending or is transmitting a message frame. rdy message buffer ready bit 0 the message buffer can be written by software. the can module cannot write to the message buffer 1 writing the message buffer by software is ignored (except a write access to the rdy, trq, dn, and mow bits). the can module can write to the message buffer caution: do not clear the rdy bit (0) du ring message transmission. follow the transmission abort process about clea ring the rdy bit (0) for redefinition of the message buffer. after reset: ? write offset address: 00eh 15 14 13 12 11 10 9 8 cnmctrlm0000set ie0set trqset rdy (n = 0, 1) 76543210 000 clear mow clear ie clear dn clear trq clear rdy clear mow mow bit setting 0 mow bit is not changed 1 mow bit is cleared to 0 set ie clear ie setting of ie bit 0 1 ie bit is cleared to 0 1 0 ie bit is set to 1 other than above ie bit is not changed clear dn setting of dn bit 1 dn bit is cleared to 0 0 dn bit is not changed caution: do not set the dn bit to 1 by software. be sure to write 0 to bit 10
800 chapter 18 afcan controller user?s manual u16580ee2v0ud00 figure 18-49: cann message control re gister m (cnmctrl m) format (3/3) remark: n = 0, 1 m = 0 to 31 set trq clear trq setting of trq bit 0 1 trq bit is cleared to 0 1 0 trq bit is set to 1 other than above trq bit is not changed set rdy clear rdy setting of rdy bit 0 1 rdy bit is cleared to 0 1 0 rdy bit is set to 1 other than above rdy bit is not changed
801 chapter 18 afcan controller user?s manual u16580ee2v0ud00 18.7 bit set/clear function the can control registers include registers whose bi ts can be set or cleared via the cpu and via the can interface. an operation error occurs if the follo wing registers are written directly. do not write any values directly via bit manipulation, read/modify /write, or direct writing of target values. ? can global control register (cngmctrl) ? can global automatic block transmission control register (cngmabt) ? can module control register (cnctrl) ? can module interrupt enable register (cnie) ? can module interrupt status register (cnints) ? can module receive history list register (cnrgpt) ? can module transmit history list register (cntgpt) ? can module time stamp register (cnts) ? can message control register (cnmctrlm) remark: n: 0 - 4 = number of channel m: 0 - 31 = message buffer number all the 16 bits in the above registers can be read via the usual method. use the procedure described in figure 18-50 below to set or clear the lower 8 bits in these registers. setting or clearing of lower 8 bits in the above registers is performed in combination with the higher 8 bits (refer to the 16-bit data after a write operation in figure 18-51). figure 18-50 shows how the values of set bits or clear bits relate to set/clea r/no change operations in the corresponding register. figure 18-50: example of bit setting/clearing operations 0000000011010001 0000101111011000 set00001011 0000000000000011 clear 11011000 set set no change no change clear no change clear clear bit status register?s current values write values register?s value after write operations
802 chapter 18 afcan controller user?s manual u16580ee2v0ud00 figure 18-51: 16-bit data during write operation remark: n = 0 to 7 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 set 7 set 6 set 5 set 4 set 3 set 2 set 1 set 0 clear 7 clear 6 clear 5 clear 4 clear 3 clear 2 clear 1 clear 0 set n clear n status of bit n after bit set/clear operation 0 0 no change 01 0 10 1 1 1 no change
803 chapter 18 afcan controller user?s manual u16580ee2v0ud00 18.8 can controller initialization 18.8.1 initialization of can module before the can module operation is enabled, the can module system clock needs to be determined by setting the ccp0 to ccp3 bits of the cngmcs register by software. do not change the setting of the can module system clock after can module operation is enabled. the can module is enabled by setting the gom bit of the cngmctrl register. for the procedure of initializ ing the can module, refer to 18.16 ?operation of can controller? on page 837 . 18.8.2 initialization of message buffer after the can module is enabled, the message buffers contain undefined values. a minimum initialization for all the message buffers, even for those not used in the application, is necessary before switching the can module from the initialization mode to one of the operation modes. - clear the rdy, trq, and dn bits of the cnmctrlm register to 0. - clear the ma0 bit of the cnmconfm register to 0. 18.8.3 redefinition of message buffer redefining a message buffer means changing the id and control information of the message buffer while a message is being received or transmitted, without affecting other transmission/reception operations. (1) to redefine message buffer in initialization mode place the can module in the initialization mode once and then change the id and control information of the message buffer in the initia lization mode. after changing the id and control information, set the can modu le in an operation mode. (2) to redefine message buffer during reception perform redefinition as shown in figure 18-64, ?message buffer redefinition,? on page 840 . (3) to redefine message buffer during transmission to rewrite the contents of a transmit message buffer to which a transmission request has been set, perform transmission abort processing (refer to 18.10.4 (1)?transmission abort in normal oper- ation mode? on page 818 and 18.10.4 (3)?transmission abort in normal operation mode with automatic block transmission (abt)? on page 818 ). confirm that transmission has been aborted or completed, and then redefine the message buffer. after redefining the transmit message buffer, set a transmission request using the procedure described below. when setting a transmission request to a message buffer that has been redefined without aborting the transmission in progress, however, the 1-bit wait time is not necessary.
804 chapter 18 afcan controller user?s manual u16580ee2v0ud00 figure 18-52: setting transmission request (trq) to transmit message buffer after redefining cautions: 1. when a message is received, reception filtering is performed in accordance with the id and mask set to each receive message buffer. if the procedure in figure figure 18-64, ?message buffer redefinition,? on page 840 is not observed, the contents of the message buffer after it has been redefined may contradict the result of reception (result of reception filtering). if this happens, check that the id and ide received first and stored in the message buffer following redefinition are those stored after the message buffer has been redefined. if no id and ide are stored after redefinition, redefine the message buffer again. 2. when a message is transmitted, the transmission priority is checked in accordance with the id, ide, and rtr bits set to each transmit message buffer to which a transmission request was set. the transmit message buffer having the highest priority is selected for transmission. if the procedure in figure 18-52 is not observed, a message with an id not having the highest priority may be transmitted after redefinition. redefinition completed wait for 1 bit of can data. execute transmission? set trq bit set trq bit = 1 clear trq bit = 0 end no yes
805 chapter 18 afcan controller user?s manual u16580ee2v0ud00 18.8.4 transition from initialization mode to operation mode the can module can be switched to the following operation modes: - normal operation mode - normal operation mode with abt - receive-only mode - single-shot mode - self-test mode figure 18-53: transition to operation modes the transition from the initialization mode to an operation mode is controlled by the bit string opmode2 to opmode0 in the cnctrl register. changing from one operation mode into another requires shifting to the initialization mode in between. do not change one operatio n mode to another directly; otherwis e the operation will not be guaranteed. requests for transition from the operation mode to the initialization mode are held pending when the can bus is not in the interframe space (i.e., frame reception or transmission is in progress), and the can module enters the initialization mode at the first bit in the interframe space (the value of opmod2 to opmode0 bits are changed to 00h). after issuing a request to change the mode to the initialization mode, read the opmode2 to oipmode0 bits until their value becomes 000b to confirm that the module has entered the initialization mode (refer to figure 18-62, ?re-initialization,? on page 838 ). 18.8.5 resetting error c ounter cnerc of can module if it is necessary to reset the can module er ror counter cnerc and the can module information register cninfo when re-initialization or forced recovery from the bus-off state is made, set the ccerc bit of the cnctrl register to 1 in the initialization mode. wh en this bit is set to 1, the can module error counter cnerc and the can module information register cninfo are cleared to their default values. can module channel invalid [receive-only mode] opmode[2:0]=03h opmode[2:0] = 00h and can bus is busy. opmode[2:0] = 03h [single-shot mode] opmode[2:0]=04h opmode[2:0] = 04h opmode[2:0] = 05h init mode opmode[2:0] = 00h efsd = 1 and gom = 0 all can modules are in init mode and gom = 0 gom = 1 reset reset released [normal operation mode with abt] opmode[2:0]=02h opmode[2:0] = 00h and can bus is busy. opmode[2:0] = 00h and interframe space opmode[2:0] = 02h opmode[2:0] = 01h opmode[2:0] = 00h and can bus is busy. [normal operation mode] opmode[2:0]=01h opmode[2:0] = 00h and can bus is busy. opmode[2:0] = 00h and interframe space opmode[2:0] = 00h and interframe space opmode[2:0] = 00h and interframe space opmode[2:0] = 00h and interframe space opmode[2:0] = 00h and can bus is busy. [self-test mode] opmode[2:0]=05h
806 chapter 18 afcan controller user?s manual u16580ee2v0ud00 18.9 message reception 18.9.1 message reception in all the operation modes, the complete message buffer area is analyzed to find a suitable buffer to store a newly received message. all message buffers satisfying the following conditions are included in that evaluation (rx-search process). ? used as a message buffer (ma0 bit of cnmconfm register set to 1b.) ? set as a receive message buffer (mt2 to mt0 bits of cnmconfm register set to 001b, 010b, 011b, 100b, or 101b.) ? ready for reception (rdy bit of cnmctrlm register set to 1.) when two or more message buffers of the can module receive a message, the message is stored according to the priority explained below. the message is always stored in the message buffer with the highest priority, not in a message buffer with a low priority. for example, when an unmasked receive message buffer and a receive message buffer linked to mask 1 have the same id, the received message is not stored in the message buffer linked to mask 1, even if that message buffer has not received a message and a message has already been received in the unmasked receive message buffer. in other words, when a condition has been set to store a message in two or more message buffers with different priorities, the message buffer with the highest priority always stores the message; the message is not stored in message buffers with a lower priority. this also applies when the message buffer with the highest priority is unable to receive and store a message (i.e., when dn = 1 indicating that a message has already been received, but rewrit ing is disabled because ows = 0). in this case, the message is not actually received and stored in the candidate message buffer with the highest priority, but neither is it stored in a message buffer with a lower priority. table 18-25: message reception priority storing condition if same id is set 1 (high) unmasked message buffer dn = 0 dn = 1 and ows = 1 2 message buffer linked to mask 1 dn = 0 dn = 1 and ows = 1 3 message buffer linked to mask 2 dn = 0 dn = 1 and ows = 1 4 message buffer linked to mask 3 dn = 0 dn = 1 and ows = 1 5 (low) message buffer linked to mask 4 dn = 0 dn = 1 and ows = 1
807 chapter 18 afcan controller user?s manual u16580ee2v0ud00 18.9.2 receive history list function the receive history list (rhl) function records in the receive history list the number of the receive message buffer in which each data frame or remote frame was received and stored. the rhl consists of storage elements equivalent to up to 23 messages, the last in-message pointer (lipt) with the corresponding cnlipt register and the receive history list get pointer (rgpt) with the corresponding cnrgpt register. the rhl is undefined immediately after the transition of the can module from the initialization mode to one of the operation modes. the cnlipt register holds the contents of the rhl element indicated by the value of the lipt pointer minus 1. by reading the cnlipt register, therefore, the number of the message buffer that received and stored a data frame or remo te frame first can be checked. the lipt pointer is utilized as a write pointer that indicates to what part of the rhl a message buffer number is recorded. any time a data frame or remote frame is received and stored, the corresponding message buffer number is recorded to the rhl element indicated by the lipt pointer. each time recording to the rhl has been completed, the lipt pointer is automatically incremented. in this way, the number of the message buffer that has received and stored a frame will be re corded chronologically. the rgpt pointer is utilized as a read pointer that reads a recorded message buff er number from the rhl. this pointer indicates the first rhl element that the cpu has not read yet. by reading the cnrgpt register by software, the number of a message buffer that has received and stored a data frame or remote frame can be read. each time a message buffer number is read from the cnrgpt register, the rgpt pointer is automatically incremented. if the value of the rgpt pointer matches the value of the lipt pointer, the rhpm bit (receive history list pointer match) of the cnrgpt register is set to 1. this indicates that no message buffer number that has not been read remains in the rhl. if a new message buffer number is recorded, the lipt pointer is incremented and because its value no longer matches the value of the rgpt pointer, the rhpm bit is cleared. in other words, the numbers of the unread message buffers exist in the rhl. if the lipt pointer is incremented and matches the value of the rgpt pointer minus 1, the rovf bit (receive history list overflow) of the cnrgpt register is set to 1. this indicates that the rhl is full of numbers of message buffers that have not been read. when further message reception and storing occur, the last recorded message buffer number is overwritten by the number of the message buffer that received and stored the new message. in this case, after the rovf bit has been set (1), the recorded message buffer numbers in the rhl do not completely reflect the chronological order. however the non-recovered receptio ns in the rhl are still recoverabl e. therefore the application needs to browse all rx-buffer and check the dn bits.
808 chapter 18 afcan controller user?s manual u16580ee2v0ud00 as long as the rhl contains 23 or less entries the sequence of occurrence is maintained. if more receptions occur without reading the rhl by the host processor, complete sequence of receptions can not be recovered. figure 18-54: receive history list 23 1 2 3 4 5 6 7 receive history list (rhl) 23 1 2 3 4 5 6 7 receive history list(rhl) last in-message pointer(lipt) 23 0 1 2 3 4 5 6 7 23 1 2 3 4 5 6 7 0 : : : : : : : : : 22 0 0 22 22 22 message buffer 7 message buffer 2 message buffer 9 message buffer 6 message buffer 8 message buffer 4 message buffer 3 receive history list get pointer (rgpt) receive history list(rhl) message buffer 1 message buffer 5 message buffer 8 message buffer 4 message buffer 3 message buffer 10 message buffer 6 message buffer 11 message buffer 9 receive history list get pointer (rgpt) last in-message pointer(lipt) rovf = 1 lipt is blocked. receive history list get pointer (rgpt) receive history list get pointer (rgpt) last in-message pointer(lipt) message buffer 1 message buffer 9 message buffer 10 message buffer 5 message buffer 3 message buffer 4 message buffer 8 message buffer 11 receive history list (rhl) last in-message pointer(lipt) rovf = 1 lipt is blocked. message buffer 15 event: - message buffer 6, 9, 2 and 7 are read by host processor. - newly received messages are stored in message buffer 3, 4 and 8. event: - reception in message buffer 13, 14 and 15 occurs. - overflow situation occurs. event: - 20 other messages are received. message buffer 6 carries last received message. - upon reception in message buffer 6, rhl is full. - rovf is set. rovf = 1 defines that lipt equals rgpt - 1 while message buffer number stored to element indicated by lipt - 1.
809 chapter 18 afcan controller user?s manual u16580ee2v0ud00 18.9.3 mask function it can be defined whether masking of the identifier that is set to a message buffer is linked with another message buffer. by using the mask function, the identifier of a message received from the can bus can be compared with the identifier set to a message buffer in advance. regardless of whether the masked id is set to "0" or "1", the received message can be stored in the defined message buffer. while the mask function is in effect, an identifier bit that is defined to be "1" by a mask in the received message is not compared with the corresponding identifier bit in the message buffer. however, this comparison is performed for any bit whose value is defined as "0" by the mask. for example, let us assume that all messages that have a standard-format id, in which bits id27 to id25 are "0" and bits id24 and id22 are "1", are to be stored in message buffer 14. the procedure for this example is shown below. figure 18-55: mask function identifier examples (1/2) (a) identifier to be stored in message buffer remark: x = don?t care (b) identifier to be configured in message buffer 14 (example) (using cann message id registers l14 and h14 (cnmidl14 and cnmidh14)) id with id27 to id25 cleared to "0" and id24 and id22 set to "1" is registered (initialized) to message buffer 14. remark: message buffer 14 is set as a standard format identifier that is linked to mask 1 (mt2 to mt0 bits of cnmconf14 register are set to 010b). id28 id27 id26 id25 id24 id23 id22 id21 id20 id19 id18 x0001x1xxxx id28 id27 id26 id25 id24 id23 id22 id21 id20 id19 id18 x0001x1xxxx id17 id16 id15 id14 id13 id12 id11 id10 id9 id8 id7 xxxxxxxxxxx id6 id5 id4 id3 id2 id1 id0 xxxxxxx
810 chapter 18 afcan controller user?s manual u16580ee2v0ud00 figure 18-55: mask function identifier examples (2/2) (c) mask setting for can module 1 (mask 1) (example) (using can1 address mask 1 register s l and h (c1maskl1 and c1maskh1)) remark: 1: not compared (masked) 0: compared the cmid27 to cmid24 and cmid22 bits are cleared to "0", and cmid28, cmid23, and cmid21 to cmid0 bits are set to "1". cmid2 8 cmid2 7 cmid2 6 cmid2 5 cmid2 4 cmid2 3 cmid2 2 cmid2 1 cmid2 0 cmid1 9 cmid1 8 10000101111 cmid1 7 cmid1 6 cmid1 5 cmid1 4 cmid1 3 cmid1 2 cmid1 1 cmid1 0 cmid9 cmid8 cmid7 11111111111 cmid6 cmid5 cmid4 cmid3 cmid2 cmid1 cmid0 1111111
811 chapter 18 afcan controller user?s manual u16580ee2v0ud00 18.9.4 multi buffer receive block function the multi buffer receive block (mbrb) function is used to store a block of data in two or more message buffers sequentially with no cpu intera ction, by setting the same id to two or more message buffers with the same message buffer type. these message buffers can be allocated anywhere in the message buffer memory, they do not even have to follow each other adjacently. suppose, for example, the same message buffer type is set to 10 message buffers, message buffers 10 to 19, and the same id is set to each message buffer. if the first message whose id matches the id of the message buffers is received, it is stored in message buffer 10. at this point, the dn bit of message buffer 10 is set, prohibiting overwriting the message buffer when subsequent messages are received. if the next message with a matching id is received, it is received and stored in message buffer 11. each time a message with a matching id is received, it is sequentially (in the ascending order) stored in message buffers 12, 13, and so on. even when a data block consisting of multiple messages is received, the messages can be stored and received without overwriting the previously received matching-id data. whether a data block has been received and stored can be checked by setting the ie bit of the cnmctrlm register of each message buffer. for example, if a data block consists of k messages, k message buffers are initialized for reception of the data block. the ie bit in message buffers 0 to (k-2) is cleared to 0 (interrupts disabled), and the ie bit in message buffer k-1 is set to 1 (interrupts enabled). in this case, a reception completion interrupt occurs when a message has been received and stored in message buffer k-1, indicating that mbrb has become full. alternatively, by clearing the ie bit of message buffers 0 to (k-3) and setting the ie bit of message buffer k-2, a warning that mbrb is about to overflow can be issued. the basic conditions of storing receive data in each message buffer for the mbrb are the same as the conditions of storing data in a single message buffer. cautions: 1. mbrb can be configured for each of the same message buffer types. therefore, even if a message buffer of another mbrb whose id matches but whose message buffer type is different has a vacancy, the received message is not stored in that message buffer, but instead discarded. 2. mbrb does not have a ring buffer structure. therefore, after a message is stored in the message buffer having the highest number in the mbrb configuration, a newly received message will not be stored in the message buffer having the lowest message buffer number. 3. mbrb operates based on the reception and storage conditions; there are no settings dedicated to mbrb, such as f unction enable bits. by setting the same message buffer type and id to two or more message buffers, mbrb is automatically configured. 4. with mbrb, "matching id" means "matching id after mask". even if the id set to each message buffer is not the same, if the id that is masked by the mask register matches, it is considered a matching id and the buffer that has this id is treated as the storage destination of a message. 5. the priority between mbrbs is mentioned in the table 18-25, ?message recep- tion,? on page 806.
812 chapter 18 afcan controller user?s manual u16580ee2v0ud00 18.9.5 remote frame reception in all the operation modes, when a remote frame is received, the message buffer that is to store the remote frame is searched from all the message buffers satisfying the following conditions. ? used as a message buffer (ma0 bit of cnmconfm register set to 1b.) ? set as a transmit message buffer (mt2 to mt0 bits in cnmconfm register set to 000b) ? ready for reception (rdy bit of cnmctrlm register set to 1.) ? set to transmit message (rtr bit of cnmconfm register is cleared to 0.) ? transmission request is not set. (trq bit of cnmctrlm register is cleared to 1.) upon acceptance of a remote frame, the following actions are executed if the id of the received remote frame matches the id of a message buffer that satisfies the above conditions. ? the dlc3 to dlc0 bit string in the cnmdlcm register stores the received dlc value. ? cnmdata0m to cnmdata7m in the data area are not updated (data before reception is saved). ? the dn bit of the cnmctrlm register is set to 1. ? the cints1 bit of the cnints register is set to 1 (if the ie bit in the cnmctrlm register of the message buffer that receives and stores the frame is set to 1). ? the reception completion interr upt (intcnrec) is output (if the ie bit in the cnmctrlm register of the message buffer that receives and stores the frame is set to 1 and if the cie1 bit of the cnie register is set to 1). ? the message buffer number is recorded to the receive history list. caution: when a message buffer is searched for receiving and storing a remote frame, overwrite control by the ows bit of the cnmconfm register of the message buffer and the dn bit of the cnmctrlm register are not affected. if more than one transmit message buffer has the same id and the id of the received remote frame matches that id, the remote frame is stored in the transmit message buffer with the lowest message buffer number.
813 chapter 18 afcan controller user?s manual u16580ee2v0ud00 18.10 message transmission 18.10.1 message transmission a message buffer with its trq bit set to 1 participates in the search for the most high-prioritized message when the following condition s are fulfilled. this behaviour is valid for all operational modes. ? used as a message buffer (ma0 bit of cnmconfm register set to 1b.) ? set as a transmit message buffer (mt2 to mt0 bits of cnmconfm register set to 000b.) ? ready for transmission (rdy bit of cnmctrlm register set to 1.) the can system is a multi-master communication syst em. in a system like this, the priority of message transmission is determined based on message identifiers (ids). to fa cilitate transmission processing by software when there are several messages awaiting transmission, the can module uses hardware to check the id of the message with the highest priority and automatically identifies that message. this eliminates the need for software-based priority control. transmission priority is cont rolled by the identifier (id). figure 18-56: message processing example after the transmit message search, the transmit message with the highest priority of the transmit message buffers that have a pending transmission request (message buffers with the trq bit set to 1 in advance) is transmitted. if a new transmission request is set, the transmit message buffer with the new transmission request is compared with the transmit message buffer with a pending transmission request. if the new transmission request has a higher priority, it is transmitted, unless transmission of a message with a low priority has already started. if transmission of a message with a low priority has already started, however, the new transmission request is transmitted later. the highest priority is determined according to the following rules. message no. the can module transmits messages in the following sequence. message waiting to be transmitted id = 120h id = 229h id = 223h id = 023h id = 123h 0 1 2 3 4 5 6 7 8 9 1. message 6 2. message 1 3. message 8 4. message 5 5. message 2
814 chapter 18 afcan controller user?s manual u16580ee2v0ud00 remark: if automatic block transmission request bit abttrg is set to 1 in the normal operation mode with abt, the trq bit is set to 1 only for one message buffer in the abt message buffer group. if the abt mode was triggered by abttrg (1), one trq is set to 1 in the abt area (buffer 0 through 7). beyond this trq, the application can request transmissions (set trq to 1) for other tx-message buffers that do not belong to the abt area. in that case an interval arbitration process (tx-search) evaluates all tx-message buffers with trq set to 1 and chooses the message buffer that contains the highest prioritized identifier for the next transmission. if there are 2 or more identifiers that have the highest priority (i.e. identical identifiers), the message located at the lowest message buffer number is transmitted at first. upon successful transmission of a message frame, the following operations are performed. ? the trq flag of the corresponding transmit message buffer is automatically cleared to 0. ? the transmission completion status bit cints0 of the cnints register is set to 1 (if the interrupt enable bit (ie) of the corresponding transmit message buffer is set to 1). ? an interrupt request signal intcntrx is output (if the cie0 bit of the cnie register is set to 1 and if the interrupt enable bit (ie) of the corresponding transmit message buffer is set to 1). table 18-26: message transmission priority conditions description 1 (high) value of first 11 bits of id [id28 to id18]: the message frame with the lowest value represented by the first 11 bits of the id is transmitted first. if the value of an 11-bit standard id is equal to or smaller than the first 11 bits of a 29-bit extended id, the 11-bit standard id has a higher priority than message frame with the 29-bit extended id. 2 frame type a data frame with an 11-bit standard id (rtr bit is cleared to 0) has a higher priority than a remote frame with a standard id and a message frame with an extended id. 3 id type a message frame with a standard id (ide bit is cleared to 0) has a higher priority than a message frame with an extended id. 4 value of lower 18 bits of id [id17 to id0]: if more than one transmission-pending extended id message frame have equal values in the first 11 bits of the id and the same frame type (equal rtr bit values), the message frame with the lowest value in the lower 18 bits of its extended id is transmitted first. 5 (low) message buffer number if two or more mess age buffers request transmission of message frames with the same id, the message from the message buffer with the lowest message buffer number is transmitted first.
815 chapter 18 afcan controller user?s manual u16580ee2v0ud00 18.10.2 transmit history list function the transmit history list (thl) function records in the transmit history list the number of the transmit message buffer from which data or remote frames have been were sent. the thl consists of storage elements equivalent to up to seven messages, the last out-message pointer (lopt) with the corresponding cnlopt register, and the transmit history list get pointer (tgpt) with the corresponding cntgpt register. the thl is undefined immediately after the transition of the can module from the initialization mode to one of the operation modes. the cnlopt register holds the contents of the thl element indicated by the value of the lopt pointer minus 1. by reading the cnlopt register, therefore, the number of the message buffer that transmitted a data frame or remote frame first can be checked. the lopt pointer is utilized as a write pointer that indicates to what part of the thl a message buffer number is recorded. any time a data frame or remote frame is transmitted, the corresponding message buffer number is recorded to the thl element indicated by the lopt pointer. each time recording to the thl has been completed, the lopt pointer is automatically incremented. in this way, the number of the message buffer that has received and stored a frame will be re corded chronologically. the tgpt pointer is utilized as a read pointer that reads a recorded messa ge buffer number from the thl. this pointer indicates the first thl element that the cpu has not yet read. by reading the cntgpt register by software, the number of a message buffer that has completed transmission can be read. each time a message buffer number is read from the cntgpt register, the tgpt pointer is automatically incremented. if the value of the tgpt pointer matches the value of the lopt pointer, the thpm bit (transmit history list pointer match) of the cntgpt register is set to 1. this indicates that no message buffer numbers that have not been read remain in the thl. if a new message buffer number is recorded, the lopt pointer is incremented and because its value no longer matches the value of the tgpt pointer, the thpm bit is cleared. in other words, the numbers of the unread message buffers exist in the thl. if the lopt pointer is incremented and matches the value of the tgpt pointer minus 1, the tovf bit (transmit history list overflow) of the cntgpt register is set to 1. this indicates that the thl is full of message buffer numbers that have not been read. if a new message is received and stored, the message buffer number recorded last is overwritten by the number of the message buffer that transmitted its message afterwards. after the tovf bit has been set (1), therefore, the recorded message buffer numbers in the thl do not completely reflect the chronological order. however the other transmitted messages can be found by a cpu search applied to all transmit message buffers unless the cpu has not overwritten a transmit object in one of these buffers beforehand. in total up to six transmission completions can occur without overflowing the thl.
816 chapter 18 afcan controller user?s manual u16580ee2v0ud00 figure 18-57: transmit history list 18.10.3 automatic block transmission (abt) the automatic block transmission (abt) function is used to transmit two or more data frames successively with no cpu interaction. the maximum number of transmit message buffers assigned to the abt function is eight (message buffer numbers 0 to 7). by setting opmode2 to opmode0 bits of the cnctrl register to 010b, ?normal operation mode with automatic block transmission function? (hereafter referred to as abt mode) can be selected. to issue an abt transmission request, define the message buffers by software first. set the ma0 bit (1) in all the message buffers used for abt, and define all the buffers as transmit message buffers by setting mt2 to mt0 bits to 000b. be sure to set the same id for each message buffer for atb even when that id is being used for all the message buffers. to use two or more ids, set the id of each message buffer by using the cnmidlm and cnmidhm registers. set the cnmdlcm and cnmdata0m to cnmdata7m registers before issuing a transmission request for the abt function. after initialization of message buffers for abt is finished, the rdy bit needs to be set (1). in the abt mode, the trq bit does not have to be manipulated by software. after the data for the abt message buffers has been prepared, set the abttrg bit to 1. automatic block transmission is then started. when abt is started, the trq bit in the first message buffer (message buffer 0) is automatically set to 1. after transmission of the data of message buffer 0 has finished, trq of the next message buffer, message buffer 1, is set automatically. in this way, transmission is executed successively. a delay time can be inserted by program in the interval in which the transmission request (trq) is automatically set while successive transmission is being executed. the delay time to be inserted is defined by the cngmabtd register. the unit of the delay time is dbt (data bit time). dbt depends on the setting of the cnbrp and cnbtr registers. among transmit objects within the abt-area, the priority of the transmission id is not evaluated. the data of message buffers 0 to 7 are sequentially transmitted. when transmission of the data frame from message buffer 7 has been completed, the abttrg bit is automatically cleared to 0 and the abt operation is finished. 1 2 3 4 5 6 7 transmit history list(thl) 1 2 3 4 5 6 7 1 2 3 4 5 6 7 1 2 3 4 5 6 7 event: - message buffer 8, 5, 6 and 10 completes transmission - thl is full - tovf is set 0 0 0 0 last out-message pointer(lopt) message buffer 7 message buffer 2 message buffer 9 message buffer 6 transmit history list get pointer(tgpt) transmit history list(thl) message buffer 4 message buffer 3 message buffer 7 transmit history list get pointer(tgpt) transmit history list(thl) transmit history list get pointer(tgpt) last out-message pointer(lopt) tovf = 1 lopt is blocked transmit history list get pointer (tgpt) transmit history list(thl) last out-message pointer(lopt) message buffer 5 message buffer 8 message buffer 4 message buffer 3 message buffer 7 message buffer 14 message buffer 5 message buffer 8 message buffer 4 message buffer 3 message buffer 7 message buffer 10 message buffer 6 message buffer 6 tovf = 1 lopt is blocked event: - cpu confirms tx completion of message buffer 6, 9 and 2 - tx completion of message buffer 3 and 4 last out- message pointer (lopt) event: - message buffer 11, 13 and 14 completes transmission. - overflow situation occurs. tovf = 1 defines that lopt equals topt - 1 while message buffer number stored to element indicated by lopt - 1.
817 chapter 18 afcan controller user?s manual u16580ee2v0ud00 if the rdy bit of an abt message buffer is cleared during abt, no data frame is transmitted from that buffer, abt is stopped, and the abttrg bit is cleared. after that, transmission can be resumed from the message buffer where abt stopped, by setting the rdy and abttrg bits to 1 by software. to not resume transmission from the message buffer where abt stopped, the internal abt engine can be reset by setting the abtclr bit to 1 while abt mode is stopped and abttrg is cleared to 0. in this case, transmission is started from message buffer 0 if the abtclr bit is cleared to 0 and then the abttrg bit is set to 1. an interrupt can be used to check if data frames have been transmitted from all the message buffers for abt. to do so, the ie bit of the cnmctrlm register of each message buffer except the last message buffer needs to be cleared (0). if a transmit message buffer other than those used by the abt function (message buffer 8 to m max - 1 note ) is assigned to a transmit message buffer, the priority of the message to be transmitted is determined by the priority of the transmission message buffer id of the abt message buffer whose transmission is curren tly held pending and the transmission id of the message buffers other than those used by the abt function. transmission of a data frame from an abt message buffer is not recorded in the transmit history list (thl). cautions: 1. set the abtclr bit to 1 while the abttrg bit is cleared to 0 in order to resume abt operation at buffer no.0 . if the abtclr bit is set to 1 while the abttrg bit is set to 1, the subsequent operation is not guaranteed. 2. if the automatic block transmission engine is cleared by setting the abtclr bit to 1, the abtclr bit is automatically cleared immediately after the processing of the clearing request is completed. 3. do not set the abttrg bit in the initiali zation mode. if the abttrg bit is set in the initialization mode, the proper operation is not guaranteed after the mode is changed from the initialization mode to the abt mode. 4. do not set trq of the abt message buffers to 1 by software in the normal operation mode with abt. otherwise, the operation is not guaranteed. 5. the cngmabtd register is used to set the delay time that is inserted in the period from completion of the preceding abt message to setting of the trq bit for the next abt message when the transmission requests are set in the order of message numbers for each message for abt that is successively transmitted in the abt mode. the timing at which the messages are actually transmitted onto the can bus varies depending on the status of transmission from other stations and the status of the setting of the transmission request for messages other than the abt messages (message buffer 8 to m max - 1 note ). 6. if a transmission request is made for a message other than an abt message and if no delay time is inserted in the interval in which transmission requests for abt are automatically set (cngmabtd = 00h), messages other than abt messages may be transmitted not depending on their priority compared to the priority of the abt message. 7. do not clear the rdy bit to 0 when abttrg = 1. 8. if a message is received from another node while normal operation mode with abt is active, the tx-message from the abt-area may be transmitted with delay of one frame although cngmabtd register was set up with 00h. note: m max = 32
818 chapter 18 afcan controller user?s manual u16580ee2v0ud00 18.10.4 transmission abort process (1) transmission abort in normal operation mode the user can clear the trq bit of the cnmctrlm register to 0 to abort a transmission request. the trq bit will be cleared immedi ately if the abort was succe ssful. whether th e transmission was successfully aborted or not can be checked using the tstat bit of the cnctrl register and the cntgpt register, which indicate the transmission status on the can bus (for details, refer to the processing in figure 18-71, ?transmission abort processing (except normal operation mode with abt),? on page 847 ). (2) transmission abort process except for abt transmission in normal operation mode with automatic block transmission (abt) the user can clear the abttrg bit of the cngmabt register to 0 to abort a transmission request. after checking the abttrg bit of the cngmabt register = 0, clear the trq bit of the cnmctrlm register to 0. the trq bit will be clear ed immediately if the abort was successful. whether the transmission was successfully aborted or not can be checked using the tstat bit of the cnctrl register and the cntgpt register, which indicate the transmission status on the can bus (for details, refer to the processing). (3) transmission abort in normal operation m ode with automatic block transmission (abt) to abort abt that is already started, clear the abttrg bit of the cngmabt register to 0. in this case, the abttrg bit remains 1 if an abt message is currently being transmitted and until the transmission is completed (successfully or not), and is cleared to 0 as soon as transmission is finished. this aborts abt. if the last transmission (before abt) was successful, the normal operation mode with abt is left with the internal abt pointer pointing to the next message buffer to be transmitted. in the case of an erroneous transmission, the position of the internal abt pointer depends on the status of the trq bit in the last transmitted message buffer. if the trq bit is set to 1 when clearing the abttrg bit is requested, the internal abt pointer points to the last transmitted message buffer (for details, refer to the process in figure 18-72, ?transmission abort processing except for abt transmission (normal oper ation mode with abt),? on page 848 ). if the trq bit is cleared to 0 when clearing the abttrg bit is requ ested, the internal abt pointer is incremented (+1) and points to the next message buffer in the abt area. caution: be sure to abort abt by clearing abttr g to 0. the operation is not guaranteed if aborting transmission is requested by clearing rdy.
819 chapter 18 afcan controller user?s manual u16580ee2v0ud00 when the normal operation mode with abt is resumed after abt has been aborted and abttrg is set to 1, the next abt message buffer to be transmitted can be determined from the following table. note: the above resumption operation can be performed only if a message buffer ready for abt exists in the abt area. for example, an abort request that is issued while abt of message buffer 7 is in progress is regarded as completion of abt, rather than abort, if transmission of message buffer 7 has been successfully completed, even if abttrg is cleared to 0. if the rdy bit in the next message buffer in the abt area is cleared to 0, the internal abt pointer is retained, but the resumption operation is not performed even if abttrg is set to 1, and abt ends immediately. 18.10.5 remote frame transmission remote frames can be transmitted only from transmit message buffers. set whether a data frame or remote frame is transmitted via the rtr bit of the cnmconfm register. setting (1) the rtr bit sets remote frame transmission. table 18-27: transmission abort status of trq of abt message buffer abort after successful transmissi on abort after erroneous transmission set (1) next message buffer in the abt area note same message buffer in the abt area cleared (0) next message buffer in the abt area note next message buffer in the abt area note
820 chapter 18 afcan controller user?s manual u16580ee2v0ud00 18.11 power save modes 18.11.1 can sleep mode the can sleep mode can be used to set the can controller to standby mode in order to reduce power consumption. the can module can enter the can sleep mode from all operation modes. release of the can sleep mode returns the can module to exactly the same operation mode from which the can sleep mode was entered. in the can sleep mode, the can module does not transmit messages, even when transmission requests are issued or pending. (1) entering can sleep mode the cpu issues a can sleep mode transition request by writing 01b to the psmode1, psmode0 bits of the cnctrl register. this transition request is only ackno wledged only under the following conditions. ? the can module is already in one of the following operation modes - normal operation mode - normal operation mode with abt - receive-only mode - single-shot mode - self-test mode - can stop mode in all the above operation modes ? the can bus state is bus idle (the 4th bi t in the interframe space is recessive) note ? no transmission request is pending note: if the can bus is fixed to dominant, the request for transition to the can sleep mode is held pending. if any of the conditions mentio ned above is not met, the can module will operate as follows: ? if the can sleep mode is requested from the in itialization mode, the can sleep mode transition request is ignored and the can module remains in the initialization mode. ? if the can bus state is not bus idle (i.e., the can bus state is either transmitting or receiving) when the can sleep mode is requested in one of the operation modes, immediate transition to the can sleep mode is not possible. in this case , the can sleep mode transition request is held pending until the can bus state becomes bus idle (the 4th bit in the interframe space is recessive). in the time from the can sleep mode request to successful transition, the psmode1, psmode0 bits remain 00b. when the module has entered the can sleep mode, psmode1, psmode0 bits are set to 01b. ? if a request for transition to the initialization mode and a request for transition to the can sleep are made at the same time while the can module is in one of the operation modes, the request for the initialization mode is enabled. the can module enters the initialization mode at a predetermined timing. at this time, the can sl eep mode request is not held pending and is ignored. ? even when initialization mode and sleep mode are requested simultaneously (i.e. the first request has not been granted while the second request is made), the request for initialization has priority over the sleep mode request. the sleep mode request is cancelled when the initialization mode is requested. when a pending request for initialization mode is present, a subsequent request for sleep mode request is cancelled right at the point in time where it was submitted.
821 chapter 18 afcan controller user?s manual u16580ee2v0ud00 (2) status in can sleep mode the can module is in one of the following states after it enters the can sleep mode: ? the internal operating clock is stopped and the power consumption is minimized. ? the function to detect the falling edge of the can reception pin (crxdn) remains in effect to wake up the can module from the can bus. ? to wake up the can module from the cpu, data can be written to psmode1, psmode0 bits of the can module control register (cnctrl), but nothing can be written to other can module registers or bits. ? the can module registers can be read, except for cnlipt, cnrgpt, cnlopt, and cntgpt. ? the can message buffer registers cannot be written or read. ? a request for transition to the initialization mode is not acknowledged and is ignored. (3) releasing can sleep mode the can sleep mode is released by the following events: ? when the cpu writes 00b to the psmode1, psmode0 bits of the cnctrl register ? a falling edge at the can reception pin (crxdn) (i .e. the can bus level shifts from recessive to dominant) caution: even if the falling edge belongs to the sof of a receive message, this message will not be received and stored. if the cpu has turned off the clock to the can while the can was in sleep mode, even subsequently the can sleep mode will not be released and psmode1, psmode0 bits will continue to be 01b unless the clock to the can is supplied again. in addition to this, the receive message will not be received after that. after releasing the sleep mode, the can module returns to the operation mode from which the can sleep mode was requested and the psmode1, psmode0bits of the cnctrl register are reset to 00b. if the can sleep mode is released by a change in the can bus state, the cints5 bit of the cnints register is set to 1, regardless of the cie bit of the cnie register. after the can module is released from the can sleep mode , it participates in the can bus again by automatically detecting 11 consecutive recessive-level bits on the can bus. when a request for transition to the initialization mode is made while the can module is in the can sleep mode, that request is ignored; the cpu has to be released from sleep mode by software first before enteri ng the initialization mode.
822 chapter 18 afcan controller user?s manual u16580ee2v0ud00 18.11.2 can stop mode the can stop mode can be used to set the can controller to standby mode to reduce power consumption. the can module can enter the can stop mode only from the can sleep mode. release of the can stop mode puts the ca n module in the can sleep mode. the can stop mode can only be released (entering can sleep mode) by writing 01b to the psmode1, psmode0 bits of the cnctrl register and not by a change in the can bus state. no message is transmitted even when transmission requests are issued or pending. (1) entering can stop mode a can stop mode transition request is issued by writing 11b to the psmode1, psmode0 bits of the cnctrl register. a can stop mode request is only acknowledged when the can module is in the can sleep mode. in all other modes, the request is ignored. caution: to set the can module to the can stop mode, the module must be in the can sleep mode. to confirm that the module is in the sleep mode, check that psmode1, psmode0 = 01b, and then request the can stop mode. if a bus change occurs at the can reception pin (crxd) while this process is being performed, the can sleep mode is automatically released. in this case, the can stop mode transition request cannot be acknowledged. (2) status in can stop mode the can module is in one of the following states after it enters the can stop mode: ? the internal operating clock is stopped and the power consumption is minimized. ? to wake up the can module from the cpu, data can be written to psmode1, psmode0 of the can module control register (cnctrl), but nothing can be written to other can module registers or bits. ? the can module registers can be read, except for cnlipt, cnrgpt, cnlopt, and cntgpt. ? the can message buffer registers cannot be written or read. ? an initialization mode transition request is not acknowledged and is ignored. (3) releasing can stop mode the can stop mode can only be released by writing 01b to the psmode1, psmode0 bits of the cnctrl register. after releasing the can stop mode, the can module enters the can sleep mode. when the initialization mode is requested while the can module is in the can stop mode, that request is ignored; the cpu has to release the stop mode and subsequently can sleep mode before entering the initialization mode. it is impossible to enter the other operation mode directly from the can stop mode not entering the can sleep mode, that request is ignored.
823 chapter 18 afcan controller user?s manual u16580ee2v0ud00 18.11.3 example of using power saving modes in some application systems, it may be necessary to place the cpu in a power saving mode to reduce the power consumption. by using the power saving mode specific to the can module and the power saving mode specific to the cpu in combination, the cpu can be woken up from the power saving status by the can bus. here is an example of using the power saving modes. first, put the can module in the can sleep mode (psmode = 01b). next, put the cpu in the power saving mode. if an edge transition from recessive to dominant is detected at the can reception pin (crxdn) in this status, the cints5 bit in the can module is set to 1. if the cie5 bit of the cnctrl register is set to 1, a wakeup interrupt (intcnwup) is generated. the can module is automatically released from the can sleep mode (psmode = 00b) and returns to the normal operation mode. the cpu, in response to intcnwup, can release its own power saving mode and return to the normal operation mode. to further reduce the power consumption of the cpu, the internal clocks, including that of the can module, may be stopped. in this case, the operating clock supplied to the can module is stopped after the can module is put in the can sleep mode. then the cpu enters a power saving mode in which the clock supplied to the cpu is stopped. if an edge transiti on from recessive to dominant is detected at the can reception pin (crxdn) in this status, the can module can set the cints5 bit to 1 and generate the wakeup interrupt (intcnwup) even if it is not supplied with the clock. the other functions, however, do not operate because clock supply to the can module is stopped, and the module remains in the can sleep mode. the cpu, in response to intcnwup, releases its power saving mode, resumes supply of the internal clocks, including the clock to the can module, after the oscillation stabi- lisation time has elapsed, and starts instruction ex ecution. the can module is immediately released from the can sleep mode when clock supply is resumed, and returns to the normal operation mode (psmode = 00b).
824 chapter 18 afcan controller user?s manual u16580ee2v0ud00 18.12 interrupt function 18.12.1 interrupts generated by can module the can module provides 6 different interrupt sources. the occurrence of these interrupt sources is stored in interrupt status registers. four separate interrupt request signals are generated from the six interrupt sources. when an interrupt request signal that corresponds to two or more interrupt sources is generated, the interrupt sources can be identified by using an interrupt status register. after an interrupt source has occurred, the corresponding interrupt status bit must be cleared to 0 by software. notes: 1. the ie bit (message buffer interrupt enable bit) in the cnmctrl register of the corresponding message buffer has to be set to 1 for that message buffer to participate in the interrupt generation process. 2. this interrupt is generated when the transmission/reception error counter is at the warning level, or in the error passive or bus-off state. 3. this interrupt is generated when a stuff error, form error, ack error, bit error, or crc error occurs. 4. this interrupt is generated when the can module is woken up from the can sleep mode because a falling edge is detect ed at the can reception pin (can bus transition from recessive to dominant). remark: n = 0, 1 table 18-28: list of can module interrupt sources no interrupt status bit interrupt enable bit interrupt request signal interrupt source description name register name register 1 cints0 note 1 cnints cie0 note 1 cnie intcntrx message frame successfully transmitted from message buffer m 2 cints1 note 1 cnints cie1 note 1 cnie intcnrec valid message frame reception in message buffer m 3 cints2 cnints cie2 cnie intcnerr can module erro r state interrupt note 2 4 cints3 cnints cie3 cnie can module protoc ol error interrupt note 3 5 cints4 cnints cie4 cnie can module arbitration loss interrupt 6 cints5 cnints cie5 cnie intcnwup can module wakeup interrupt from can sleep mode note 4
825 chapter 18 afcan controller user?s manual u16580ee2v0ud00 18.13 diagnosis functions and special operational modes the can module provides a receive-only mode, single-shot mode, and self-test mode to support can bus diagnosis functions or the operation of specific can communication methods. 18.13.1 receive-only mode the receive-only mode is used to monitor receive messages without causing any interference on the can bus and can be used for can bus analysis nodes. for example, this mode can be used for automatic baud-rate detection. the baud rate in the can module is changed until "valid reception" is detected, so that the baud rates in the module match ("valid reception" means a message frame has been received in the can protocol layer without occurrence of an error and with an appropriate ack between nodes connected to the can bus). a valid reception does not require message frames to be stored in a receive message buffer (data frames) or transmit message buffer (remote frames). the event of valid reception is indicated by setting the valid bit of the cnctrl register (1). figure 18-58: can module terminal co nnection in receive-only mode in the receive-only mode, no message frames can be transmitted from the can module to the can bus. transmit requests issued for message buffers defined as transmit message buffers are held pending. in the receive-only mode, the can transmission pin (ctxdn) in the can module is fixed to the recessive level. therefore, no active error flag can be transmitted from the can module to the can bus even when a can bus error is detected while receiv ing a message frame. since no transmission can be issued from the can module, the transmission error counter tec is never updated. therefore, a can module in the receive-only mode does not enter the bus-off state. can macro rx tx ctxdn crxdn fixed to the recessive level
826 chapter 18 afcan controller user?s manual u16580ee2v0ud00 furthermore, ack is not returned to the can bus in this mode upon the valid reception of a message frame. internally, the local node recognizes that it has transmitted ack. an overload frame cannot be transmitted to the can bus. caution: if only two can nodes are connected to th e can bus and one of them is operating in the receive-only mode, there is no ack on the can bus. due to the missing ack, the transmitting node will transmit an active error flag, and repeat transmitting a message frame. the transmitting node becomes error passive after transmitting the message frame 16 times (assuming that the error counter was 0 in the beginning and no other errors have occurred). after the message frame for the 17th time is transmitted, the transmitting node generates a passive error flag. the receiving node in the receive-only mode detects the first valid message frame at this point, and the valid bit is set to 1 for the first time. 18.13.2 single-shot mode in the single-shot mode, automatic re-transmission as defined in the can protocol is switched off. (according to the can protocol, a message frame transmission that has been aborted by either arbitration loss or error occurrence has to be repeated without control by software.) all other behaviour of single shot mode is identical to normal operat ion mode. features of single shot mode can not be used in combination with normal mode with abt. the single-shot mode disables the re-transmission of an aborted message frame transmission according to the setting of the al bit of the cnctrl register. when the al bit is cleared to 0, re-transmission upon arbitration loss and upon error occu rrence is disabled. if the al bit is set to 1, re- transmission upon error occurrence is disabled, but re-transmission upon arbitration loss is enabled. as a consequence, the trq bit in a message buffer defined as a transmit message buffer is cleared to 0 by the following events: ? successful transmission of the message frame ? arbitration loss while sending the message frame ? error occurrence while sending the message frame the events arbitration loss and error occurrence can be distinguished by checking the cints4 and cints3 bits of the cnints register respectively, and the type of the error can be identified by reading the lec2 to lec0 bits of the cnlec register. upon successful transmission of the message fram e, the transmit completion interrupt bit cints0 of the cnints register is set to 1. if the cie0 bit of the cnie register is set to 1 at this time, an interrupt request signal is output. the single-shot mode can be used when emulating time-triggered communication methods (e.g. ttcan level 1). caution: the al bit is only valid in single-shot mode. it does not influence the operation of re- transmission upon arbitration loss in the other operation modes.
827 chapter 18 afcan controller user?s manual u16580ee2v0ud00 18.13.3 self-test mode in the self-test mode, message frame transmission and message frame reception can be tested without connecting the can node to the can bus or without affecting the can bus. in the self-test mode, the can module is completely disconnected from the can bus, but transmission and reception are internally looped back. the can tr ansmission pin (ctxdn) is fixed to the recessive level. if the falling edge on the can reception pin (crxdn) is detected after the ca n module has entered the can sleep mode from the self-test mode, however, the module is released from the can sleep mode in the same manner as the other operation modes. to keep the module in the can sleep mode, use the can reception pin (crxdn) as a port pin. figure 18-59: can module terminal connection in self-test mode can macro rx tx ctxdn crxdn fixed to the recessive level
828 chapter 18 afcan controller user?s manual u16580ee2v0ud00 18.14 time stamp function can is an asynchronous, serial protocol. all nodes connected to the can bus have a local, autonomous clock. as a consequence, the clocks of the nodes have no relation (i.e., the clocks are asynchronous and may have different frequencies). in some applications, however, a common time base over the network (= global time base) is needed. in order to build up a global time base, a time stamp function is used. the essential mechanism of a time stamp function is the capture of timer values triggered by signals on the can bus. the can controller supports the capturing of timer va lues triggered by a spec ific frame. an on-chip 16-bit capture timer unit in a microcontroller system is used in addition to the can controller. the 16-bit capture timer unit captures the timer value according to a trigger signal (tsout) for capturing that is output when a data frame is received from the can controller. the cpu can retrieve the time of occurrence of the capture event, i.e., the time stamp of the message received from the can bus, by reading the captured value. tsout can be selected from the following two event sources and is specified by the tssel bit of the cnts register: ? sof event (start of frame) (tssel = 0) ? eof event (last bit of end of frame) (tssel = 1) the tsout signal is enabled by setting the tsen bit of the cnts register to 1. figure 18-60: timing diagram of capture signal tsout tsout toggles its level upon occurrence of the selected event during data frame reception (in the above timing diagram, the sof is used as the trigger event source). to capture a timer value by using tsout, the capture timer unit must detect the capt ure signal at both the rising edge and falling edge. this time stamp function is controlled by the tslock bit of the cnts register. when tslock is cleared to 0, tsout toggles upon occurrence of the selected event. if tslock is set to 1, tsout toggles upon occurrence of the selected event, but the toggle is stopped as the tsen bit is automatically cleared to 0 when a data frame starts to be received and stored in message buffer 0. this suppresses the subsequent toggle o ccurrence by tsout, so that the time stamp value toggled last (= captured last) can be saved as the time stamp value of the time at which the data frame was received in message buffer 0. caution: the time stamp function using tslock is to stop toggle of tsout by receiving a data frame in message buffer 0. therefore, message buffer 0 must be set as a receive message buffer. since a receive message buffer cannot receive a remote frame, toggle of tsout cannot be stopped by reception of a remote frame. toggle of tsout does not stop when a data frame is received in a message buffer other than message buffer 0. for these reasons, a data frame cannot be received in message buffer 0 when the can module is in the normal operation mode with abt, because message buffer 0 must be set as a transmit message buffer. in this operation mode, therefore, the function to stop toggle of tsout by tslock cannot be used. t tsout sof sof sof sof
829 chapter 18 afcan controller user?s manual u16580ee2v0ud00 18.15 baud rate settings make sure that the settings are within the range of limit values for ensuring correct operation of the can controller, as follows. (a) 5tq spt (sampling point) 17 tq spt = tseg1 + 1 (b) 8 tq dbt (data bit time) 25 tq dbt = tseg1 + tseg2 + 1tq = tseg2 + spt (c) 1 tq sjw (synchronization jump width) 4tq sjw dbt ? spt (d) 4 tseg1 16 [3 (setting value of tseg1[3:0] 15] (e) 1 tseg2 8 [0 (setting value of tseg2[2:0] 7] remark: tq = 1/f tq (f tq : can protocol layer basic system clock) tseg1[3:0] (bits 3 to 0 of cann bit rate register (cnbtr)) tseg2[2:0] (bits 10 to 8 of cann bit rate register (cnbtr))
830 chapter 18 afcan controller user?s manual u16580ee2v0ud00 table 18-29 shows the combinations of bit rates that satisfy the above conditions. table 18-29: settable bit rate combinations (1/3) valid bit rate setting cnbtr register setting value sampling point (unit,%) dbt length sync segment prop segment phase segment 1 phase segment 2 tseg1[3:0] tseg2[2:0] 251888111111168.0 241788111011166.7 241977111111070.8 231688110111165.2 231877111011069.6 23 1 10 6 6 1111 101 73.9 221588110011163.6 221777110111068.2 221966111010172.7 22 1 11 5 5 1111 100 77.3 211488101111161.9 211677110011066.7 211866110110171.4 21 1 10 5 5 1110 100 76.2 21 1 12 4 4 1111 011 81.0 201388101011160.0 201577101111065.0 201766110010170.0 201955110110075.0 20 1 11 4 4 1110 011 80.0 20 1 13 3 3 1111 010 85.0 191288100111157.9 191477101011063.2 191666101110168.4 191855110010073.7 19 1 10 4 4 1101 011 78.9 19 1 12 3 3 1110 010 84.2 19 1 14 2 2 1111 001 89.5 181188100011155.6 181377100111061.1 181566101010166.7 181755101110072.2 181944110001177.8 18 1 11 3 3 1101 010 83.3 18 1 13 2 2 1110 001 88.9 18 1 15 1 1 1111 000 94.4 171277100011058.8
831 chapter 18 afcan controller user?s manual u16580ee2v0ud00 171466 1001 101 64.7 171655 1010 100 70.6 171844 1011 011 76.5 17 1 10 3 3 1100 010 82.4 17 1 12 2 2 1101 001 88.2 17 1 14 1 1 1110 000 94.1 161177 0111 110 56.3 161366 1000 101 62.5 161555 1001 100 68.8 161744 1010 011 75.0 161933 1011 010 81.3 16 1 11 2 2 1100 001 87.5 16 1 13 1 1 1101 000 93.8 151266 0111 101 60.0 151455 1000 100 66.7 151644 1001 011 73.3 151833 1010 010 80.0 15 1 10 2 2 1011 001 86.7 15 1 12 1 1 1100 000 93.3 141166 0110 101 57.1 141355 0111 100 64.3 141544 1000 011 71.4 141733 1001 010 78.6 141922 1010 001 85.7 14 1 11 1 1 1011 000 92.9 131255 0110 100 61.5 131444 0111 011 69.2 131633 1000 010 76.9 131822 1001 001 84.6 13 1 10 1 1 1010 000 92.3 121155 0101 100 58.3 121344 0110 011 66.7 121533 0111 010 75.0 121722 1000 001 83.3 121911 1001 000 91.7 111244 0101 011 63.6 111433 0110 010 72.7 111622 0111 001 81.8 111811 1000 000 90.9 table 18-29: settable bit rate combinations (2/3) valid bit rate setting cnbtr register setting value sampling point (unit,%) dbt length sync segment prop segment phase segment 1 phase segment 2 tseg1[3:0] tseg2[2:0]
832 chapter 18 afcan controller user?s manual u16580ee2v0ud00 note: setting with a dbt value of 7 or less is valid only when the value of the cnbrp register is other than 00h. caution: the values in table 18-29 do not guarantee the operation of the network system. thoroughly check the effect on the network system, taking into consideration oscillation errors and delays of the can bus and can transceiver. 101144010001160.0 101333010101070.0 101522011000180.0 101711011100090.0 91233010001066.7 91422010100177.8 91611011000088.9 81133001101062.5 81322010000175.0 81511010100087.5 7 note 1222001100171.4 7 note 1411010000085.7 6 note 1122001000166.7 6 note 1311001100083.3 5 note 1211001000080.0 4 note 1111000100075.0 table 18-29: settable bit rate combinations (3/3) valid bit rate setting cnbtr register setting value sampling point (unit,%) dbt length sync segment prop segment phase segment 1 phase segment 2 tseg1[3:0] tseg2[2:0]
833 chapter 18 afcan controller user?s manual u16580ee2v0ud00 18.15.1 representative examples of baud rate settings ta bl e s 18-30 and 18-31 show representative examples of baud rate setting. table 18-30: representative examples of baud rate settings (f canmod = 8 mhz) (1/2) set baud rate value (unit:kbps) division ratio of cnbrp cnbrp register set value valid bit rate setting (unit: kbps) cnbtr register setting value sampling point (unit:%) length of dbt sync segment prop segment phase segment 1 phase segment 2 tseg1 [3:0] tseg2 [2:0] 1000 1 00000000 8 1 1 3 3 0011 010 62.5 1000 1 00000000 8 1 3 2 2 0100 001 75.0 1000 1 00000000 8 1 5 1 1 0101 000 87.5 500 1 00000000 16 1 1 7 7 0111 110 56.3 500 1 00000000 16 1 3 6 6 1000 101 62.5 500 1 00000000 16 1 5 5 5 1001 100 68.8 500 1 00000000 16 1 7 4 4 1010 011 75.0 500 1 00000000 16 1 9 3 3 1011 010 81.3 500 1 00000000 16 1 11 2 2 1100 001 87.5 500 1 00000000 16 1 13 1 1 1101 000 93.8 500 2 00000001 8 1 1 3 3 0011 010 62.5 500 2 00000001 8 1 3 2 2 0100 001 75.0 500 2 00000001 8 1 5 1 1 0101 000 87.5 250 2 00000001 16 1 1 7 7 0111 110 56.3 250 2 00000001 16 1 3 6 6 1000 101 62.5 250 2 00000001 16 1 5 5 5 1001 100 68.8 250 2 00000001 16 1 7 4 4 1010 011 75.0 250 2 00000001 16 1 9 3 3 1011 010 81.3 250 2 00000001 16 1 11 2 2 1100 001 87.5 250 2 00000001 16 1 13 1 1 1101 000 93.8 250 4 00000011 8 1 3 2 2 0100 001 75.0 250 4 00000011 8 1 5 1 1 0101 000 87.5 125 4 00000011 16 1 1 7 7 0111 110 56.3 125 4 00000011 16 1 3 6 6 1000 101 62.5 125 4 00000011 16 1 5 5 5 1001 100 68.8 125 4 00000011 16 1 7 4 4 1010 011 75.0 125 4 00000011 16 1 9 3 3 1011 010 81.3 125 4 00000011 16 1 11 2 2 1100 001 87.5 125 4 00000011 16 1 13 1 1 1101 000 93.8 125 8 00000111 8 1 3 2 2 0100 001 75.0 125 8 00000111 8 1 5 1 1 0101 000 87.5 100 4 00000011 20 1 7 6 6 1100 101 70.0 100 4 00000011 20 1 9 5 5 1101 100 75.0 100 5 00000100 16 1 7 4 4 1010 011 75.0 100 5 00000100 16 1 9 3 3 1011 010 81.3
834 chapter 18 afcan controller user?s manual u16580ee2v0ud00 caution: the values in table 18-30 do not guarantee the operation of the network system. thoroughly check the effect on the network system, taking into consideration oscillation errors and delays of the can bus and can transceiver. 100 8 00000111 10 1 3 3 3 0101 010 70.0 100 8 00000111 10 1 5 2 2 0110 001 80.0 100 10 00001001 8 1 3 2 2 0100 001 75.0 100 10 00001001 8 1 5 1 1 0101 000 87.5 83.3 4 00000011 24 1 7 8 8 1110 111 66.7 83.3 4 00000011 24 1 9 7 7 1111 110 70.8 83.3 6 00000101 16 1 5 5 5 1001 100 68.8 83.3 6 00000101 16 1 7 4 4 1010 011 75.0 83.3 6 00000101 16 1 9 3 3 1011 010 81.3 83.3 6 00000101 16 1 11 2 2 1100 001 87.5 83.3 8 00000111 12 1 5 3 3 0111 010 75.0 83.3 8 00000111 12 1 7 2 2 1000 001 83.3 83.3 12 00001011 8 1 3 2 2 0100 001 75.0 83.3 12 00001011 8 1 5 1 1 0101 000 87.5 33.3 10 00001001 24 1 7 8 8 1110 111 66.7 33.3 10 00001001 24 1 9 7 7 1111 110 70.8 33.3 12 00001011 20 1 7 6 6 1100 101 70.0 33.3 12 00001011 20 1 9 5 5 1101 100 75.0 33.3 15 00001110 16 1 7 4 4 1010 011 75.0 33.3 15 00001110 16 1 9 3 3 1011 010 81.3 33.3 16 00001111 15 1 6 4 4 1001 011 73.3 33.3 16 00001111 15 1 8 3 3 1010 010 80.0 33.3 20 00010011 12 1 5 3 3 0111 010 75.0 33.3 20 00010011 12 1 7 2 2 1000 001 83.3 33.3 24 00010111 10 1 3 3 3 0101 010 70.0 33.3 24 00010111 10 1 5 2 2 0110 001 80.0 33.3 30 00011101 8 1 3 2 2 0100 001 75.0 33.3 30 00011101 8 1 5 1 1 0101 000 87.5 table 18-30: representative examples of baud rate settings (f canmod = 8 mhz) (2/2) set baud rate value (unit:kbps) division ratio of cnbrp cnbrp register set value valid bit rate setting (unit: kbps) cnbtr register setting value sampling point (unit:%) length of dbt sync segment prop segment phase segment 1 phase segment 2 tseg1 [3:0] tseg2 [2:0]
835 chapter 18 afcan controller user?s manual u16580ee2v0ud00 table 18-31: representative examples of baud rate settings (f canmod = 16 mhz) (1/2) set baud rate value (unit:kbps) division ratio of cnbrp cnbrp register set value valid bit rate setting (unit: kbps) cnbtr register setting value sampling point (unit:%) length of dbt sync segment prop segment phase segment 1 phase segment 2 tseg1 [3:0] tseg2 [2:0] 1000 1 00000000 16 1 1 7 7 0111 110 56.3 1000 1 00000000 16 1 3 6 6 1000 101 62.5 1000 1 00000000 16 1 5 5 5 1001 100 68.8 1000 1 00000000 16 1 7 4 4 1010 011 75.0 1000 1 00000000 16 1 9 3 3 1011 010 81.3 1000 1 00000000 16 1 11 2 2 1100 001 87.5 1000 1 00000000 16 1 13 1 1 1101 000 93.8 1000 2 00000001 8 1 3 2 2 0100 001 75.0 1000 2 00000001 8 1 5 1 1 0101 000 87.5 500 2 00000001 16 1 1 7 7 0111 110 56.3 500 2 00000001 16 1 3 6 6 1000 101 62.5 500 2 00000001 16 1 5 5 5 1001 100 68.8 500 2 00000001 16 1 7 4 4 1010 011 75.0 500 2 00000001 16 1 9 3 3 1011 010 81.3 500 2 00000001 16 1 11 2 2 1100 001 87.5 500 2 00000001 16 1 13 1 1 1101 000 93.8 500 4 00000011 8 1 3 2 2 0100 001 75.0 500 4 00000011 8 1 5 1 1 0101 000 87.5 250 4 00000011 16 1 3 6 6 1000 101 62.5 250 4 00000011 16 1 5 5 5 1001 100 68.8 250 4 00000011 16 1 7 4 4 1010 011 75.0 250 4 00000011 16 1 9 3 3 1011 010 81.3 250 4 00000011 16 1 11 2 2 1100 001 87.5 250 8 00000111 8 1 3 2 2 0100 001 75.0 250 8 00000111 8 1 5 1 1 0101 000 87.5 125 8 00000111 16 1 3 6 6 1000 101 62.5 125 8 00000111 16 1 7 4 4 1010 011 75.0 125 8 00000111 16 1 9 3 3 1011 010 81.3 125 8 00000111 16 1 11 2 2 1100 001 87.5 125 16 00001111 8 1 3 2 2 0100 001 75.0 125 16 00001111 8 1 5 1 1 0101 000 87.5 100 8 00000111 20 1 9 5 5 1101 100 75.0 100 8 00000111 20 1 11 4 4 1110 011 80.0 100 10 00001001 16 1 7 4 4 1010 011 75.0 100 10 00001001 16 1 9 3 3 1011 010 81.3 100 16 00001111 10 1 3 3 3 0101 010 70.0 100 16 00001111 10 1 5 2 2 0110 001 80.0 100 20 00010011 8 1 3 2 2 0100 001 75.0
836 chapter 18 afcan controller user?s manual u16580ee2v0ud00 caution: the values in table 18-31 do not guarantee the operation of the network system. thoroughly check the effect on the network system, taking into consideration oscillation errors and delays of the can bus and can transceiver. 83.3 8 00000111 24 1 7 8 8 1110 111 66.7 83.3 8 00000111 24 1 9 7 7 1111 110 70.8 83.3 12 00001011 16 1 7 4 4 1010 011 75.0 83.3 12 00001011 16 1 9 3 3 1011 010 81.3 83.3 12 00001011 16 1 11 2 2 1100 001 87.5 83.3 16 00001111 12 1 5 3 3 0111 010 75.0 83.3 16 00001111 12 1 7 2 2 1000 001 83.3 83.3 24 00010111 8 1 3 2 2 0100 001 75.0 83.3 24 00010111 8 1 5 1 1 0101 000 87.5 33.3 30 00011101 24 1 7 8 8 1110 111 66.7 33.3 30 00011101 24 1 9 7 7 1111 110 70.8 33.3 24 00010111 20 1 9 5 5 1101 100 75.0 33.3 24 00010111 20 1 11 4 4 1110 011 80.0 33.3 30 00011101 16 1 7 4 4 1010 011 75.0 33.3 30 00011101 16 1 9 3 3 1011 010 81.3 33.3 32 00011111 15 1 8 3 3 1010 010 80.0 33.3 32 00011111 15 1 10 2 2 1011 001 86.7 33.3 37 00100100 13 1 6 3 3 1000 010 76.9 33.3 37 00100100 13 1 8 2 2 1001 001 84.6 33.3 40 00100111 12 1 5 3 3 0111 010 75.0 33.3 40 00100111 12 1 7 2 2 1000 001 83.3 33.3 48 00101111 10 1 3 3 3 0101 010 70.0 33.3 48 00101111 10 1 5 2 2 0110 001 80.0 33.3 60 00111011 8 1 3 2 2 0100 001 75.0 33.3 60 00111011 8 1 5 1 1 0101 000 87.5 table 18-31: representative examples of baud rate settings (f canmod = 16 mhz) (2/2) set baud rate value (unit:kbps) division ratio of cnbrp cnbrp register set value valid bit rate setting (unit: kbps) cnbtr register setting value sampling point (unit:%) length of dbt sync segment prop segment phase segment 1 phase segment 2 tseg1 [3:0] tseg2 [2:0]
837 chapter 18 afcan controller user?s manual u16580ee2v0ud00 18.16 operation of can controller figure 18-61: initialization remark: opmode: normal operation mode, normal operation mode with abt, receive-only mode, single-shot mode, self-test mode start set cngmcs register set gom = 1 set cnbrp register cnbtr register set cnie register set cnmask register initialization message buffers set opmode end set cngmcs register set cngmcs register
838 chapter 18 afcan controller user?s manual u16580ee2v0ud00 figure 18-62: re-initialization caution: after setting the can module to the initialization mode, avoid setting the module to another operation mode immediately after. if it is necessary to immediately set the module to another operation mode, be sure to access registers other than the cnctrl and cngmctrl registers (e.g. set a message buffer). remark: opmode: normal operation mode, normal operation mode with abt, receive-only mode, single-shot mode, self-test mode start set cnbrp register, cnbtr register set cnie register set cnmask register set cnctrl register (set opmode) end clear opmode init mode? no yes set ccerc bit cnctrl.set_ccerc = 1 yes no initialize message buffers cnerc and cninfo register clear?
839 chapter 18 afcan controller user?s manual u16580ee2v0ud00 figure 18-63: message buffer initialization cautions: 1. before a message buffer is initialized, the rdy bit must be cleared. 2. make the following settings for message buffers not used by the application: - clear the rdy, trq, and dn bits of the cnmctrlm register to 0. - clear the ma0 bit of the cnmconfm register to 0. start set cnmconfm register end rdy = 1? no yes clear rdy bit set rdy bit = 0 clear rdy bit = 1 rdy = 0? set cnmidhm register, cnmidlm register transmit message buffer? clear cnmdatam register set cnmctrlm register set rdy bit set rdy bit = 1 clear rdy bit = 0 set cnmdlcm register no no yes yes
840 chapter 18 afcan controller user?s manual u16580ee2v0ud00 figure 18-64 shows the processing for a receive message buffer (mt2 to mt0 bits of cnmconfm register = 001b to 101b). figure 18-64: message buffer redefinition note: confirm that a message is being received because rdy bit must be set after a message is completely received. start set message buffers end rdy = 1? no yes clear rdy bit cnmctrlm.set_rdy = 0 cnmctrlm.clear_rdy = 1 rdy = 0? rstat = 0 or valid = 1? note no clear valid bit set rdy bit cnmctrlm.set_rdy = 1 cnmctrlm.clear_rdy = 0 yes yes no wait for 4 can data bits
841 chapter 18 afcan controller user?s manual u16580ee2v0ud00 figure 18-65 shows the processing for a transmit message buffer during transmission (mt2 to mt0 bits of cnmconfm register = 00b) figure 18-65: message buffer redefinition during transmission start end rdy = 0? no yes data frame or remote frame? set rdy bit set cnmdataxm register set cnmdlcm register clear rtr bit of cnmconfm register set cnmidlm and cnmidhm registers set cnmdlcm register set rtr bit of cnmconfm register set cnmidlm and cnmidhm registers remote frame data frame transmit abort process clear rdy bit cnmctrlm.set_rdy = 0 transmit? set trq bit yes wait for 1can data bits no cnmctrlm.clear_rdy = 1 cnmctrlm.set_rdy = 1 cnmctrlm.clear_rdy = 0 cnmctrlm.set_trq = 1 cnmctrlm.clear_trq = 0
842 chapter 18 afcan controller user?s manual u16580ee2v0ud00 figure 18-66 shows the processing for a transmit message buffer (mt2 to mt0 bits of cnmconfm register = 000b). figure 18-66: message transmit processing caution: the trq bit should be set after the rdy bit is set. the rdy bit and trq bit should not be set at the same time. start end trq = 0? yes clear rdy bit cnmctrlm.set_rdy = 0 rdy = 0? data frame or remote frame? set rdy bit yes no set cnmdataxm register set cnmdlcm register clear rtr bit of cnmconfm register set cnmidlm and cnmidhm registers set cnmdlcm register set rtr bit of cnmconfm register set cnmidlm and cnmidhm registers set trq bit remote frame data frame cnmctrlm.clear_rdy = 1 cnmctrlm.set_rdy = 1 cnmctrlm.clear_rdy = 0 cnmctrlm.set_trq = 1 cnmctrlm.clear_trq = 0 no
843 chapter 18 afcan controller user?s manual u16580ee2v0ud00 figure 18-67 shows the processing for a transmit message buffer (mt2 to mt0 bits of cnmconfm register = 000b). figure 18-67: message transmit processing (normal operation mode with abt) remark: this processing (normal operation mode with abs) can only be applied to message buffers 0 to 7. for message buffers other than the abt message buffers, refer to figure 18-66. caution: the abttrg bit should be set to 1 after the tstat bit is cleared to 0. checking the tstat bit and setting the abttrg bit to 1 must be processed continuously. start set cnmdataxm register set cnmdlcm register clear rtr bit of cnmconfm register set cnmidlm and cnmidhm registers end abttrg = 0? no yes clear rdy bit rdy = 0? set rdy bit yes no set abttrg bit set all abt transmit messages? tstat = 0? yes no yes no cnmctrlm.set_rdy = 0 cnmctrlm.clear_rdy = 1 cnmctrlm.set_rdy = 1 cnmctrlm.clear_rdy = 0 cngmabt.set_abttrg = 1 cngmabt.clear_abttrg = 0
844 chapter 18 afcan controller user?s manual u16580ee2v0ud00 figure 18-68: transmission via in terrupt (using cnlopt register) caution: the trq bit should be set after the rdy bit is set. the rdy bit and trq bit should not be set at the same time. start end clear rdy bit rdy = 0? data frame or remote frame? set rdy bit yes no set cnmdataxm register set cnmdlcm register, clear rtr bit of cnmconfm register. set cnmidlm and cnmidhm registers set cnmdlcm register set rtr bit of cnmconfm register. set cnmidlm and cnmidhm registers set trq bit remote frame data frame transmit completion interrupt processing transmit completion interrupt processing read cnlopt register cnmctrlm.set_rdy = 0 cnmctrlm.clear_rdy = 1 cnmctrlm.set_rdy = 1 cnmctrlm.clear_rdy = 0 cnmctrlm.set_trq = 1 cnmctrlm.clear_trq = 0
845 chapter 18 afcan controller user?s manual u16580ee2v0ud00 figure 18-69: transmit via interrupt (using cntgpt register) caution: the trq bit should be set after the rdy bit is set. the rdy bit and trq bit should not be set at the same time start end tovf = 1? data frame or remote frame? set rdy bit yes no set cnmdataxm register set cnmdlcm register clear rtr bit of cnmconfm register set cnmidlm and cnmidhm registers set cnmdlcm register set rtr bit of cnmconfm register set cnmidlm and cnmidhm registers set trq bit remote frame data frame transmit completion interrupt processing read cntgpt register clear tovf bit clear tovf = 1 clear rdy bit rdy = 0? thpm = 1? no yes no yes cnmctrlm.set_trq = 1 cnmctrlm.clear_trq = 0 cnmctrlm.set_rdy = 1 cnmctrlm.clear_rdy = 0 cnmctrlm.set_rdy = 0 cnmctrlm.clear_rdy = 1
846 chapter 18 afcan controller user?s manual u16580ee2v0ud00 figure 18-70: transmission via software polling caution: the trq bit should be set after the rdy bit is set. the rdy bit and trq bit should not be set at the same time. start end tovf = 1? data frame or remote frame? set rdy bit yes no set cnmdataxm register set cnmdlcm register clear rtr bit of cnmconfm register. set cnmidlm and cnmidhm registers set cnmdlcm register set rtr bit of cnmconfm set cnmidlm and cnmidhm registers set trq bit remote frame data frame read cntgpt register clear tovf bit cntgpt.clear_tovf = 1 clear rdy bit rdy = 0? thpm = 1? no yes no yes cints0 = 1? no clear cints0 bit cnints.clear_cints0 = 1 cnmctrlm.set_rdy = 0 cnmctrlm.clear_rdy = 1 cnmctrlm.set_rdy = 1 cnmctrlm.clear_rdy = 0 cnmctrlm.set_trq = 1 cnmctrlm.clear_trq = 0
847 chapter 18 afcan controller user?s manual u16580ee2v0ud00 figure 18-71: transmission abort processing (except normal operation mode with abt) cautions: 1. execute transmission request abort processing by clearing the trq bit, not the rdy bit. 2. before making a sleep mode transition request, confirm that there is no transmission request left using this processing. 3. the tstat bit can be periodically ch ecked by a user application or can be checked after the transmit completion interrupt. 4. do not execute the new transmission request including in the other message buffers while transmission abort processing is in progress. start read cnlopt register end no yes clear trq bit tstat = 0? message buffer to be aborted matches cnlopt register? no wait for 11 can data bits transmission successful transmit abort request was successful yes cnmctrlm.set_trq = 0 cnmctrlm.clear_trq = 1
848 chapter 18 afcan controller user?s manual u16580ee2v0ud00 figure 18-72: transmission abort processing except for abt transmission (normal operation mode with abt) cautions: 1. execute transmission request abort processing by clearing the trq bit, not the rdy bit. 2. before making a sleep mode transition request, confirm that there is no transmission request left using this processing. 3. the tstat bit can be periodically checked by a user application or can be checked after the transmit completion interrupt. 4. do not execute the new transmission request including in the other message buffers while transmission abort processing is in progress. start read cnlopt register end no yes clear trq bit tstat = 0? message buffer to be aborted matches cnlopt register? no wait for 11 can data bits transmission successful transmit abort request was successful yes no abttrg = 0? clear abttrg bit yes cngmabt.set_abttrg = 0 cngmabt.clear_abttrg = 1 cnmctrlm.set_trq = 0 cnmctrlm.clear_trq = 1
849 chapter 18 afcan controller user?s manual u16580ee2v0ud00 figure 18-73 shows the processing not to skip resumption of transmitting a message that was stopped when transmission of an abt message buffer was aborted. figure 18-73: abt transmission abort processing (normal operation mode with abt) cautions: 1. do not set any transmission requests while abt transmission abort processing is in progress. 2. make a can sleep mode/can stop mode transition request after abttrg is cleared (after abt mode is aborted) following the procedure shown in figure 18-73 or 18-74. when clearing a transmission request in an area other than the abt area, follow the procedure shown in figure 18-71. start end no clear abttrg bit abttrg = 0? transmission start no clear trq bit of message buffer whose transmission was aborted transmit abort yes set abtclr bit yes no tstat = 0? yes cngmabt.set_abttrg = 0 cngmabt.clear_abttrg = 1 cngmabt.set_abtclr = 1 cngmabt.clear_abtclr = 0
850 chapter 18 afcan controller user?s manual u16580ee2v0ud00 figure 18-74 shows the processing to skip resumption of transmitting a message that was stopped when transmission of an abt message buffer was aborted. figure 18-74: abt transmission request abort processing (normal operation mode with abt) cautions: 1. do not set any transmission requests while abt transmission abort processing is in progress. 2. make a can sleep mode/can stop mode request after abttrg is cleared (after abt mode is stopped) following the procedure shown in figures 18-73 or 18-74. when clearing a transmission request in an area other than the abt area, follow the procedure shown in figure 18-71. start end no clear abttrg bit abttrg = 0? transmission start pointer clear? no transmit abort yes set abtclr bit yes clear trq bit of message buffer undergoing transmission cngmabt.set_abttrg = 0 cngmabt.clear_abttrg = 1 cngmabt.set_abtclr = 1 cngmabt.clear_abtclr = 0
851 chapter 18 afcan controller user?s manual u16580ee2v0ud00 figure 18-75: reception via interrupt (using cnlipt register) note: check the muc and dn bits using one read access. start clear cints1 bit cnints.clear_cints1 = 1 end no read cnmdataxm, cnmdlcm, cnmidlm, and cnmidhm registers dn = 0 and muc = 0 read cnlipt register yes generation of receipt completion interrupt clear dn bit cnmctrlm.clear_dn = 1 note
852 chapter 18 afcan controller user?s manual u16580ee2v0ud00 figure 18-76: reception via interrupt (using cnrgpt register) note: check the muc and dn bits using one read access start clear rovf bit cnrgpt.clear_rovf = 1 no rovf = 1? read cnrgpt register yes receive completion interrupt clear dn bit cnmctrlm.clear_dn = 1 read cnmdataxm, cnmdlcm, cnmidlm, cnmidhm registers dn = 0 and muc = 0 note dn = 0 and muc = 0 note rhpm = 1? end yes no yes no
853 chapter 18 afcan controller user?s manual u16580ee2v0ud00 figure 18-77: reception via software polling note: check the muc and dn bits using one read access start clear rovf bit no rovf = 1? read cnrgpt register yes clear dn bit read cnmdataxm, cnmdlcm, cnmidlm, cnmidhm registers dn = 0 and muc = 0 note dn = 0 and muc = 0 note rhpm = 1? end yes no yes no cints1 = 1? yes no clear cints1 bit cnints.clear_cints1 = 1 cnrgpt.clear_rovf = 1 cnctrlm.clear_dn = 1
854 chapter 18 afcan controller user?s manual u16580ee2v0ud00 figure 18-78: setting can sleep mode/stop mode cautions: 1. to abort transmission before m aking a request for the can sleep mode, perform processing according to figures 18-71 and 18-72. 2. if the host cpu wants to enter a power save mode as well, the interrupt processing needs to be disabled before the cpu validates that sleep mode has been entered. if the interrupt processing can not be disabled, the host cpu will never wakeup by can bus activity when the can sleep mode is released between validation of the sleep state and execut ion of the i.e. cpu halt instruction. start (when psmode[1:0] = 00b) psmode0 = 1? set psmode0 bit cnctrl.set_psmode1 = 1 can sleep mode end yes no set psmode1 bit psmode1 = 1? can stop mode request can sleep mode again? clear cints5 bit cnints.clear_cints5 = 1 yes no yes no clear opmode init mode? yes no access to registers other than the cnctrl and cngmctrl registers set cnctrl register (set opmode) cnctrl.clear_psmode1 = 0 cnctrl.set_psmode1 = 0 cnctrl.clear_psmode1 = 1
855 chapter 18 afcan controller user?s manual u16580ee2v0ud00 figure 18-79: clear can sleep/stop mode start can sleep mode end clear psmode1 bit can stop mode clear psmode0 bit releasing can sleep mode by user releasing can sleep mode by can bus active bus activity = 0 psmode0 = 0 cints5 = 1 u d0 clear cints5 bit cnints.clear_cints5 = 1 cnctrl.set_psmode1 = 0 cnctrl.clear_psmode1 = 1 cnctrl.set_psmode0 = 0 cnctrl.clear_psmode0 = 1
856 chapter 18 afcan controller user?s manual u16580ee2v0ud00 figure 18-80: bus-off recovery start access to registers other than cnctrl and cngmctrl registers set cnctrl register (clear opmode) forced recovery from bus off? end boff = 1? yes no set ccerc bit cnctrl.set_ccerc = 1 set cnctrl register (set opmode) wait for recovery from bus off set cnctrl register (set opmode) yes no
857 chapter 18 afcan controller user?s manual u16580ee2v0ud00 figure 18-81: normal shutdown process figure 18-82: forced shutdown process caution: do not read- or write-access any registers by software between setting the efsd bit and clearing the gom bit. remark: opmode: normal operation mode, normal operation mode with abt, receive-only mode, single-shot mode, self-test mode start gom = 0? clear gom bit cngmctrl.set_gom = 0 end yes no init mode shutdown successful gom = 0, efsd = 0 cngmctrl.clear_gom = 1 start gom = 0? clear gom bit end yes no shutdown successful gom = 0, efsd = 0 set efsd bit must be a continuous write cngmctrl.set_gom = 0 cngmctrl.clear_gom = 1 cngmctrl.set_efsd = 1
858 chapter 18 afcan controller user?s manual u16580ee2v0ud00 figure 18-83: error handling start clear cints2 bit cnints.clear_cints2 = 1 cints2 = 1? cints3 = 1? end yes check can protocol error state (read cnlec register) no yes no error interrupt check can module state (read cninfo register) clear cints3 bit cints4 = 1? clear cints4 bit no yes cnints.clear_cints3 = 1 cnints.clear_cints4 = 1
859 chapter 18 afcan controller user?s manual u16580ee2v0ud00 figure 18-84: setting cpu standby (from can sleep mode) start psmode0 = 1? psmode = 01b? end yes set cpu standby mode no yes no can sleep mode enable interrupts set psmode0 bit cnctrl.set_psmode0 = 1 disable interrupts cnctrl.clear_psmode0 = 0
860 chapter 18 afcan controller user?s manual u16580ee2v0ud00 figure 18-85: setting cpu standby (from can stop mode) note: during wakeup interrupts caution: the can stop mode can only be release d by writing 01b to the psmode1, psmode0 bits of the cnctrl register and not by a change in the can bus state. start psmode0 = 1? psmode = 11b? end yes set cpu standby mode no yes can sleep mode clear cints5 bit cnints.clear_cints5 = 1 note set psmode0 bit no set psmode1 bit can stop mode psmode1 = 1? cnctrl.set_psmode0 = 1 cnctrl.clear_psmode0 = 0 cnctrl.set_psmode1 = 1 cnctrl.clear_psmode1 = 0
861 user?s manual u16580ee2v0ud00 chapter 19 random number generator v850e/ph2 incorporates a hardware random number generator (rng). 19.1 features ? random number sequence passing fips and maurer test ? random number format: 16 bits ? seed generated by hardware 19.2 configuration (1) random number register (rng) the rng register is a 16-bit register that holds the random number. after read access to this register a certain time is required to generate the next random number. if a consecutive read access takes place before the new random number has been generated, the read access will be delayed. the rng register is read-only, in 16-bit units. reset input causes an undefined register content. figure 19-1: random number register (rng) after reset: undefined r address: fffff700h 1514131211109876543210 rng
862 chapter 19 random number generator user?s manual u16580ee2v0ud00 19.3 operation 19.3.1 access timing after read access to the rng register it needs a certain time to generate the next random number. moreover, when a consecutive read access take s place before the new random number has been generated, the read access will be delayed. the access timing to the rng register is as follows. single read access to rng register (when vswc register = 13h): consecutive read access to rng register: t single 102,5 f xx 1 ? ? = t consecutive t single 1024 f xx 1 ? ? () + =
863 user?s manual u16580ee2v0ud00 chapter 20 port functions 20.1 features ? input-only ports: 5 i/o ports: 136 ? input/output direction can be specified in 1.bit units ? noise removal circuit provided for external interrupts and timer inputs ? edge detect function for external in terrupts (rising-, falling-, both edges) ? security features for port 5 and 6 shared as 3-phase pwm timer outputs - emergency shut off feature - software protection feature
864 chapter 20 port functions user?s manual u16580ee2v0ud00 20.2 port configuration the v850e/ph2 incorporates a total of 141 input/output ports (including 5 input-only ports) labelled port 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, al, ah, dh, dl, cs, cm, ct, and cd. the port configuration is shown in figure 20-1 below. figure 20-1: port configuration port 0 port 1 port 3 port 4 p00 p04 p10 p17 p20 p27 p30 p37 p40 p45 port 2 port 5 port 6 p50 p57 p60 p67 p70 p75 p80 p86 port 7 port 8 p96 port 9 p90 port 10 port al port ah port dl port dh port cs port cm port ct port cd p100 p102 pal0 pal15 pah0 pah5 pdl0 pdl15 pdh0 pdh15 pcs4 pcm0 pct4 pct5 pcd2 pcd5 pcs0 pcs1 pcs3 pcm1 pcm6 pcm7
865 chapter 20 port functions user?s manual u16580ee2v0ud00 20.2.1 function of each port the port functions of v850e/ph2 are shown in the table below. the port type can vary for each individual bit of a port. in addition to their port functions, these pins are also shared with on-chip peripheral i/o pins in control mode. for the port types of each port, refer to table 20-1 below. table 20-1: port type and function overview port name pin name port function function in control mode port type port 0 p00 to p04 5-bit input only external interrupt input external a/d conversion start trigger input emergency shut-off input 3, 15, 15a port 1 p10 to p17 8-bit i/o port ti mer i/o (tmp0, tmp1, tmp2, tmp3) 6 port 2 p20 to p27 8-bit i/o port ti mer i/o (tmp4, tmp5, tmp6, tmp7) 6 port 3 p30 to p37 8-bit i/o port seri al interface i/o (uartc0, uartc1, afcan0, afcan1) 1s, 2, 9 port 4 p40 to p45 6-bit i/o port serial interface i/o (csib0, csib1) 1e, 2, 4c port 5 p50 to p57 8-bit i/o port timer output (tmr0) 11, 13 port 6 p60 to p67 8-bit i/o port timer i/o (tmr1) 12, 13, 14 port 7 p70 to p75 6-bit i/o port timer i/o (tmt0, tmt1) 6, 8 port 8 p80 to p86 7-bit i/o port serial interface i/o (csi30) 1s, 2, 4, 5, 7 port 9 p90 to p96 7-bit i/o port serial interface i/o (csi31) 1s, 2, 4, 5, 7 port 10 p100 to p102 3-bit i/o port timer i/o (tenc1, tmp8, tmr0, tmr1) 6, 10 port al pal0 to pal15 16-bit i/o port external address bus (a0-a15) 1 port ah pah0 to pah5 6-bit i/o port external address bus (a16-a21) 1 port dl pdl0 to pdl15 16-bit /io port external data bus (d0-d15) 4c port dh pdh0 to pdh15 16-bit i/o port external data bus (d16-d31) 4c port cs pcs0, pcs1, pcs3, pcs4 4-bit i/o port external bus interface control signal output (cs0 , cs1 , cs3 , cs4 ) 1 port cm pcm0, pcm1, pcm6, pcm7 4-bit i/o port external bus interface control signal i/o (wait , bclk, stst, stnxt) 1, 2c port ct pct4, pct5 2-bit i/o port external bus interface control signal output (rd , wr ) 1 port cd pcd2 to pcd5 4-bit i/o port external bus interface control signal output (ben0 -ben3 ) 1
866 chapter 20 port functions user?s manual u16580ee2v0ud00 20.2.2 port types (1) port type 1 port type 1 provides a general purpose i/o port with peripheral output function. figure 20-2: port type 1 remark: m: port number n: port bit number selector selector selector peripheral output function address npb pmn pmn pmmn pmcmn wr pmc wr pm wr port rd in
867 chapter 20 port functions user?s manual u16580ee2v0ud00 (2) port type 1s port type 1s provides a general purpose i/o port with peripheral output function. this type is similar to port type 1, but features a schmitt trigger input buffer characteristic. figure 20-3: port type 1s remark: m: port number n: port bit number selector selector selector peripheral output function address npb pmn pnm pmnm pmcnm wr pmc wr pm wr port rd in
868 chapter 20 port functions user?s manual u16580ee2v0ud00 (3) port type 1e port type 1e provides a general purpose i/o port with peripheral output function. in peripheral function mode a control signal is provided to enable or disable the output. figure 20-4: port type 1e remark: m: port number n: port bit number selector selector selector peripheral output function selector peripheral output function enable 1 = enabled 0 = hi-z address npb pmn pmn pmmn pmcmn wr pmc wr pm wr port rd in
869 chapter 20 port functions user?s manual u16580ee2v0ud00 (4) port type 2 port type 2 provides a general purpose i/o port with peripheral input function. figure 20-5: port type 2 remark: m: port number n: port bit number selector selector address peripheral input function npb pmn pmmn pmcmn wr pmc wr pm wr port rd in pmn
870 chapter 20 port functions user?s manual u16580ee2v0ud00 (5) port type 2a port type 2a provides a general purpose i/o port with peripheral input function. this type is similar as port type 2, but in port mode the peripheral input function is forced to high level. figure 20-6: port type 2a remark: m: port number n: port bit number selector selector address peripheral input function npb pmn pmmn pmcmn wr pmc wr pm wr port rd in pmn
871 chapter 20 port functions user?s manual u16580ee2v0ud00 (6) port type 2c port type 2c provides a general purpose i/o port with peripheral input function. this type is similar to type 2, but features cmos input buffer characteristic. figure 20-7: port type 2c remark: m: port number n: port bit number selector selector address peripheral input function npb pmn pmmn pmcmn wr pmc wr pm wr port rd in pmn
872 chapter 20 port functions user?s manual u16580ee2v0ud00 (7) port type 3 port type 3 provides a general purpose input port with nmi interrupt input function. figure 20-8: port type 3 filter edge detection nmi esn0 esn1 address selector npb p00 wr intm rd in rd intm
873 chapter 20 port functions user?s manual u16580ee2v0ud00 (8) port type 4 port type 4 provides a general purpose i/o port with peripheral i/o function. peripheral output enable is controlled by the corresponding peripheral function. figure 20-9: port type 4 remark: m: port number n: port bit number address peripheral function output control peripheral output function peripheral input function selector selector selector npb pmn pmmn pmcmn wr pmc wr pm wr port rd in pmn
874 chapter 20 port functions user?s manual u16580ee2v0ud00 (9) port type 4c port type 4 provides a general purpose i/o port with peripheral i/o function. peripheral output enable is controlled by the corresponding peripheral function. figure 20-10: port type 4c remark: m: port number n: port bit number address peripheral function output control peripheral output function peripheral input function selector selector selector npb pmn pmmn pmcmn wr pmc wr pm wr port rd in pmn
875 chapter 20 port functions user?s manual u16580ee2v0ud00 (10) port type 5 port type 5 provides a general purpose i/o port with peripheral i/o function. if the peripheral input function is disabled, the value of the peripheral input signal is fixed to low level. figure 20-11: port type 5 remark: m: port number n: port bit number address peripheral output function peripheral input function selector selector selector npb pmn pmmn pmcmn wr pmc wr pm wr port rd in pmn
876 chapter 20 port functions user?s manual u16580ee2v0ud00 (11) port type 6 port type 6 provides a general purpose i/o port with peripheral output function and digitally filtered peripheral input function. figure 20-12: port type 6 remark: m: port number n: port bit number address peripheral output function peripheral input function selector selector selector filter clk npb pmn pmmn pmcmn wr pmc wr pm wr port rd in pmn
877 chapter 20 port functions user?s manual u16580ee2v0ud00 (12) port type 7 port type 7 provides a general purpose i/o port with peripheral output function and external interrupt input capability. figure 20-13: port type 7 remark: m: port number n: port bit number x: external interrupt number address peripheral output function selector selector selector filter edge detection intx esx0 esx1 address selector npb pmn pmmn pmcmn wr pmc wr pm wr intm wr port rd in rd intm pmn
878 chapter 20 port functions user?s manual u16580ee2v0ud00 (13) port type 8 port type 8 provides a general purpose i/o port with digitally filtered peripheral input function and external interrupt input capability. figure 20-14: port type 8 remark: m: port number n: port bit number x: external interrupt number selector selector address peripheral input function filter edge detection esx0 esx1 address selector clk intx npb pmn pmmn pmcmn wr pmc wr pm wr intm wr port rd in rd intm pmn
879 chapter 20 port functions user?s manual u16580ee2v0ud00 (14) port type 9 port type 9 provides a general purpose i/o port with peripheral input function and external interrupt input capability. this type is similar to th e port type 8, but input noise filter is bypassed for peripheral input function. remark: the peripheral input signal provided by port type 9 is fixed to high level, if peripheral input function is disabled. figure 20-15: port type 9 remark: m: port number n: port bit number x: external interrupt number selector selector address peripheral input function edge detection esx0 esx1 address selector intx npb pmn pmmn pmcmn wr pmc wr pm wr intm wr port rd in rd intm pmn filter
880 chapter 20 port functions user?s manual u16580ee2v0ud00 (15) port type 10 port type10 provides a general purpose i/o port with digitally filtered peripheral input function. figure 20-16: port type 10 remark: m: port number n: port bit number selector selector address peripheral input function filter clk npb pmn pmmn pmcmn wr pmc wr pm wr port rd in pmn
881 chapter 20 port functions user?s manual u16580ee2v0ud00 (16) port type 11 port type 11 provides a general purpose i/o port with peripheral output function. this type is similar to the port type 6, but all port registers are write protected against unintended change due to system or software malfunction. writing to the port registers of type 11 is only possible immediately after a write access to the prcmd register. figure 20-17: port type 11 remark: m: port number n: port bit number selector selector selector peripheral output function address prcmd npb pmn pmmn pmcmn wr pmc wr pm wr port rd in pmn
882 chapter 20 port functions user?s manual u16580ee2v0ud00 (17) port type 12 port type 12 provides a general purpose i/o port with digitally filtered peripheral input function and peripheral output function. this type is similar to the port logic type 1s, but all port registers are write protected against unintended change due to system or software malfunction. writing to the port registers of type 12 is only possible immediately after a write access to the prcmd register. figure 20-18: port type 12 remark: m: port number n: port bit number address peripheral output function peripheral input function selector selector selector filter clk prcmd npb wr pmc wr pm wr port rd in pmn pmn pmmn pmcmn
883 chapter 20 port functions user?s manual u16580ee2v0ud00 (18) port type 13 port type 13 provides a general purpose i/o port with peripheral output function. this type is similar to the port logic type 11, but the output driver can be shut down immediately by the esox input signal (x = 0, 1). all port registers ar e write protected against unintended change due to system or software malfunction. writing to the port registers of type 13 is only possible immediately after a write access to the prcmd register.
884 chapter 20 port functions user?s manual u16580ee2v0ud00 figure 20-19: port type 13 remark: m: port number n: port bit number x: index of eso signal (x = 0, 1) wr pmc wr pm wr port rd in peripheral output function selector selector selector address pmmn pmcmn pmn pmn npb analog filter esox analog delay 10 ns esoxed0 esoxed1 esoxen esoxst prcmd wr pescn wr esostn "1"set request by active level "1"set request by active edge (pulse width 10ns)
885 chapter 20 port functions user?s manual u16580ee2v0ud00 (19) port type 14 port type 14 provides a general purpose i/o port with digitally filtered peripheral input function and peripheral output function. this type is similar to the port type 12, but the output driver can be shut down immediately by the esox input signal (x = 0, 1). all port registers are write protected against unintended change due to system or software malfunction. writing to the port registers of type 13 is only possible immediately after a write access to the prcmd register.
886 chapter 20 port functions user?s manual u16580ee2v0ud00 figure 20-20: port type 14 remark: m: port number n: port bit number x: index of eso signal (x = 0, 1) peripheral input function prcmd wr pmc wr pm wr port rd in peripheral output function pmn address selector selector selector filter clk pmn pmmn pmcmn np b analog filter esox analog delay 10 ns "1"set request by active level "1"set request by active edge (pulse width 10ns) esoxed0 esoxed1 esoxen esoxst prcmd wr pescn wr esostn
887 chapter 20 port functions user?s manual u16580ee2v0ud00 (20) port type 15 port type 15 provides a general purpose input port with external interrupt input function. this type is similar as port type 3. difference is the addi tional filtered peripheral input function support. figure 20-21: port type 15 remark: m: port number n: port bit number x: external interrupt number edge detection intx esx0 esx1 address selector npb pnm wr intm rd in rd intm clk peripheral input function filter
888 chapter 20 port functions user?s manual u16580ee2v0ud00 (21) port type 15a port type 15a provides a general purpose input port with external interrupt input function. this type is similar as port type 15. difference is the analog filter instead of digital filter. figure 20-22: port type 15a remark: m: port number n: port bit number x: external interrupt number edge detection intx esx0 esx1 address selector npb pnm wr intm rd in rd intm peripheral input function analog filter
889 chapter 20 port functions user?s manual u16580ee2v0ud00 20.2.3 peripheral registers of i/o ports the following table lists the peripheral registers related to i/o ports. table 20-2: peripheral registers of i/o ports (1/3) address function register name symbol bit units for manipulation after reset 1 bit 8 bits 16 bits 0xfffff000 port register port al low byte pall r/w r/w - 0x00 0xfffff000 port register port al pal - - r/w 0x0000 0xfffff001 port register port al high byte palh r/w r/w - 0x00 0xfffff002 port register port ah pah r/w r/w - 0x00 0xfffff004 port register port dl low byte pdll r/w r/w - 0x00 0xfffff004 port register port dl pdl - - r/w 0x0000 0xfffff005 port register port dl high byte pdlh r/w r/w - 0x00 0xfffff006 port register port dh low byte pdhl r/w r/w - 0x00 0xfffff006 port register port dh pdh - - r/w 0x0000 0xfffff007 port register port dh high byte pdhh r/w r/w - 0x00 0xfffff008 port register port cs pcs r/w r/w - 0x00 0xfffff00a port register port ct pct r/w r/w - 0x00 0xfffff00c port register port cm pcm r/w r/w - 0x00 0xfffff00e port register port cd pcd r/w r/w - 0x00 0xfffff020 port mode register port mode al low byte pmall r/w r/w - 0xff 0xfffff020 port mode register port mode al pmal - - r/w 0xffff 0xfffff021 port mode register port mode al high byte pmalh r/w r/w - 0xff 0xfffff022 port mode register port mode ah pmah r/w r/w - 0xff 0xfffff024 port mode register port mode dl low byte pmdll r/w r/w - 0xff 0xfffff024 port mode register port mode dl pmdl - - r/w 0xffff 0xfffff025 port mode register port mode dl high byte pmdlh r/w r/w - 0xff 0xfffff026 port mode register po rt mode dh low byte pmdhl r/w r/w - 0xff 0xfffff026 port mode register port mode dh pmdh - - r/w 0xffff 0xfffff027 port mode register port mode dh high byte pmdhh r/w r/w - 0xff 0xfffff028 port mode register port mode cs pmcs r/w r/w - 0xff 0xfffff02a port mode register port mode ct pmct r/w r/w - 0xff 0xfffff02c port mode register port mode cm pmcm r/w r/w - 0xff 0xfffff02e port mode register port mode cd pmcd r/w r/w - 0xff 0xfffff040 port mode cont rol register port mode control al low byte pmcall r/w r/w - 0x00 0xfffff040 port mode cont rol register port mode control al pmcal - - r/w 0x0000 0xfffff041 port mode cont rol register port mode control al high byte pmcalh r/w r/w - 0x00 0xfffff042 port mode cont rol register port mode control ah pmcah r/w r/w - 0x00 0xfffff044 port mode cont rol register port mode control dl low byte pmcdll r/w r/w - 0x00
890 chapter 20 port functions user?s manual u16580ee2v0ud00 0xfffff044 port mode control register port mode control dl pmcdl - - r/w 0x0000 0xfffff045 port mode control register port mode control dl high byte pmcdlh r/w r/w - 0x00 0xfffff046 port mode control register port mode control dh low byte pmcdhl r/w r/w - 0x00 0xfffff046 port mode control register port mode control dh pmcdh - - r/w 0x0000 0xfffff047 port mode control register port mode control dh high byte pmcdhh r/w r/w - 0x00 0xfffff048 port mode control register port mode control cs pmccs r/w r/w - 0x00 0xfffff04a port mode control register port mode control ct pmcct r/w r/w - 0x00 0xfffff04c port mode control register port mode control cm pmccm r/w r/w - 0x00 0xfffff04e port mode control register port mode control cd pmccd r/w r/w - 0x00 0xfffff400 port register port 0 p0 r r - undef. 0xfffff402 port register port 1 p1 r/w r/w - undef. 0xfffff404 port register port 2 p2 r/w r/w - undef. 0xfffff406 port register port 3 p3 r/w r/w - undef. 0xfffff408 port register port 4 p4 r/w r/w - undef. 0xfffff40a port register port 5 p5 r/w r/w - undef. 0xfffff40c port register port 6 p6 r/w r/w - undef. 0xfffff40e port register port 7 p7 r/w r/w - undef. 0xfffff410 port register port 8 p8 r/w r/w - undef. 0xfffff412 port register port 9 p9 r/w r/w - undef. 0xfffff414 port register port 10 p10 r/w r/w - undef. 0xfffff422 port mode register port 1 pm1 r/w r/w - 0xff 0xfffff424 port mode register port 2 pm2 r/w r/w - 0xff 0xfffff426 port mode register port 3 pm3 r/w r/w - 0xff 0xfffff428 port mode register port 4 pm4 r/w r/w - ffh 0xfffff42a port mode register port 5 pm5 r/w r/w - 0xff 0xfffff42c port mode register port 6 pm6 r/w r/w - 0xff 0xfffff42e port mode register port 7 pm7 r/w r/w - ffh 0xfffff430 port mode register port 8 pm8 r/w r/w - 0xff 0xfffff432 port mode register port 9 pm9 r/w r/w - ffh 0xfffff434 port mode register port 10 pm10 r/w r/w - ffh 0xfffff442 port mode control register port 1 pmc1 r/w r/w - 0x00 0xfffff444 port mode control register port 2 pmc2 r/w r/w - 0x00 0xfffff446 port mode control register port 3 pmc3 r/w r/w - 0x00 0xfffff448 port mode control register port 4 pmc4 r/w r/w - 0x00 table 20-2: peripheral registers of i/o ports (2/3) address function register name symbol bit units for manipulation after reset 1 bit 8 bits 16 bits
891 chapter 20 port functions user?s manual u16580ee2v0ud00 0xfffff44a port mode control register port 5 pmc5 r/w r/w - 0x00 0xfffff44c port mode control register port 6 pmc6 r/w r/w - 0x00 0xfffff44e port mode control register port 7 pmc7 r/w r/w - 0x00 0xfffff450 port mode control register port 8 pmc8 r/w r/w - 0x00 0xfffff452 port mode control register port 9 pmc9 r/w r/w - 0x00 0xfffff454 port mode control r egister port 10 pmc10 r/w r/w - 0x00 table 20-2: peripheral registers of i/o ports (3/3) address function register name symbol bit units for manipulation after reset 1 bit 8 bits 16 bits
892 chapter 20 port functions user?s manual u16580ee2v0ud00 20.2.4 peripheral registers of valid edge control the following table lists the peripheral registers related to valid edge control. table 20-3: peripheral registers of valid edge control address function register name symbol bit units for manipulation after reset 1 bit 8 bits 16 bits 0xfffff880 interrupt mode register 0 intm0 r/w r/w - 0x00 0xfffff882 interrupt mode register 1 intm1 r/w r/w - 0x00 0xfffff884 interrupt mode register 2 intm2 r/w r/w - 0x00 0xfffff886 interrupt mode register 3 intm3 r/w r/w - 0x00 0xfffff888 port 5 emergency shut off control register pesc5 r/w r/w - 0x00 0xfffff88a port 5 emergency shut o ff control register esost5 r/w r/w - 0x00 0xfffff88c port 6 emergency shut off status register pesc6 r/w r/w - 0x00 0xfffff88e port 6 emergency shut o ff status register esost6 r/w r/w - 0x00
893 chapter 20 port functions user?s manual u16580ee2v0ud00 20.3 port pin functions 20.3.1 port 0 port 0 is a 5-bit input only port. (1) functions ? input data can be read in 1-bit units by using the port register 0 (p0). ? the alternate functions shared with the input port functionality of port 0 are always enabled. table 20-4: alternate function pins and port types of port 0 (2) control registers (a) port register 0 (p0) the port register 0 (p0) is an 8-bit register that reflects the input levels of port pins p00 to p04. this register is read-only in 8-bit or 1-bit units. reset input causes an undefined register content. figure 20-23: port register 0 (p0) remark: n = 0 to 4 port alternate function remark port type port 0 p00 nmi non maskable interrupt 3 p01 intp0, eso0 external interrupt request input, emergency output shut off input (tmr0) 15a p02 intp1, eso1 external interrupt request input, emergency output shut off input (tmr1) p03 intp2, adtrg0 external interrupt request input, external a/d conversion start trigger (adc0) 15 p04 intp3, adtrg1 external interrupt request input, external a/d conversion start trigger (adc1) after reset: undefined r address: fffff400h 76543210 p0 0 0 0 p04 p03 p02 p01 p00 p0n input data control of pin p0n 0 low level is input 1 high level is input
894 chapter 20 port functions user?s manual u16580ee2v0ud00 20.3.2 port 1 port 1 is an 8-bit i/o port that can be set to input or output mode in 1-bit units. (1) functions ? input/output data can be specified in 1-bit units by using the port register 1 (p1). ? input or output mode can be set in 1-bit units by using the port mode register 1 (pm1). ? port mode or control mode (for alternate functi on) can be specified in 1-bit units by using the port mode control register 1 (pmc1). table 20-5: alternate function pins and port types of port 1 port alternate function remark port type port 1 p10 tip00, tevtp1, top00 timer input (tmp0/tmp1) timer output (tmp0) 6 p11 tip01, ttrgp1, top01 timer input (tmp0/tmp1) timer output (tmp0) p12 tip10, ttrgp0, top10 timer input (tmp0/tmp1) timer output (tmp1) p13 tip11, tevtp0, top11 timer input (tmp0/tmp1) timer output (tmp1) p14 tip20, tevtp3, top20 timer input (tmp2/tmp3) timer output (tmp2) p15 tip21, ttrgp3, top21 timer input (tmp2/tmp3) timer output (tmp2) p16 tip30, ttrgp2, top30 timer input (tmp2/tmp3) timer output (tmp3) p17 tip31, tevtp2, top31 timer input (tmp2/tmp3) timer output (tmp3)
895 chapter 20 port functions user?s manual u16580ee2v0ud00 (2) control registers (a) port register 1 (p1) the p1 register 1 is an 8-bit register that controls reading the pin levels and writing the output levels of port pins p10 to p17. this register can be read or written in 8-bit or 1-bit units. reset input causes an undefined register content. figure 20-24: port register 1 (p1) remark: n = 0 to 7 (b) port mode register 1 (pm1) the pm1 register is an 8-bit register that specifies the input or output mode. this register can be read or written in 8-bit or 1-bit units. reset input sets this register to ffh. figure 20-25: port mode register 1 (pm1) remark: n = 0 to 7 after reset: undefined r/w address: fffff402h 76543210 p1 p17 p16 p15 p14 p13 p12 p11 p10 p1n input/output data control of pin p1n 0 input mode: low level is input output mode: low level is output 1 input mode: high level is input output mode: high level is output after reset: ffh r/w address: fffff422h 76543210 pm1 pm17pm16pm15pm14pm13pm12pm11pm10 pm1n input/output mode control of pin p1n (in port mode) 0 output mode 1 input mode
896 chapter 20 port functions user?s manual u16580ee2v0ud00 (c) port mode control register 1 (pmc1) the pmc1 register is an 8-bit register that specifies the port mode or control mode (alternate function). this register can be read or written in 8-bit or 1-bit units. reset input sets this register to 00h. figure 20-26: port mode control register 1 (pmc1) (1/2) after reset: 00h r/w address: fffff442h 76543210 pmc1 pmc17 pmc16 pmc15 pmc14 pmc13 pmc12 pmc11 pmc10 pmc17 port/control mode specification of pin p17 0 i/o port mode 1 control mode (alternate function) pmc16 port/control mode specification of pin p16 0 i/o port mode 1 control mode (alternate function) pmc15 port/control mode specification of pin p15 0 i/o port mode 1 control mode (alternate function) pmc14 port/control mode specification of pin p14 0 i/o port mode 1 control mode (alternate function) pm17 function 0 top31 output mode 1 tip31, tevtp2 input mode pm16 function 0 top30 output mode 1 tip30, ttrgp2 input mode pm15 function 0 top21 output mode 1 tip21, ttrgp3 input mode pm14 function 0 top20 output mode 1 tip20, tevtp3 input mode
897 chapter 20 port functions user?s manual u16580ee2v0ud00 figure 20-26: port mode control register 1 (pmc1) (2/2) pmc13 port/control mode specification of pin p13 0 i/o port mode 1 control mode (alternate function) pmc12 port/control mode specification of pin p12 0 i/o port mode 1 control mode (alternate function) pmc11 port/control mode specification of pin p11 0 i/o port mode 1 control mode (alternate function) pmc10 port/control mode specification of pin p10 0 i/o port mode 1 control mode (alternate function) pm13 function 0 top11 output mode 1 tip11, tevtp0 input mode pm12 function 0 top10 output mode 1 tip10, ttrgp0 input mode pm11 function 0 top01 output mode 1 tip01, ttrgp1 input mode pm10 function 0 top00 output mode 1 tip00, tevtp1 input mode
898 chapter 20 port functions user?s manual u16580ee2v0ud00 20.3.3 port 2 port 2 is an 8-bit i/o port that can be set to input or output mode in 1-bit units. (1) functions ? input/output data can be specified in 1-bit units by using the port register 2 (p2). ? input or output mode can be set in 1-bit units by using the port mode register 2 (pm2). ? port mode or control mode (for alternate functi on) can be specified in 1-bit units by using the port mode control register 2 (pmc2). table 20-6: alternate function pins and port types of port 2 port alternate function remark port type port 2 p20 tip40, tevtp5, top40 timer input (tmp4/tmp5) timer output (tmp4 output) 6 p21 tip41, ttrgp5, top41 timer input (tmp4/tmp5) timer output (tmp4 output) p22 tip50, ttrgp4, top50 timer input (tmp4/tmp5) timer output (tmp5 output) p23 tip51, tevtp4, top51 timer input (tmp4/tmp5) timer output (tmp5 output) p24 tip60, tevtp7, top60 timer input (tmp6/tmp7) timer output (tmp6 output) p25 tip61, ttrgp7, top61 timer input (tmp6/tmp7) timer output (tmp6 output) p26 tip70, ttrgp6, top70 timer input (tmp6tmp7) timer output (tmp7 output) p27 tip71, tevtp6, top71 timer input (tmp6/tmp7) timer output (tmp7 output)
899 chapter 20 port functions user?s manual u16580ee2v0ud00 (2) control registers (a) port register 2 (p2) the p2 register is an 8-bit register that controls reading the pin levels and writing the output levels of port pins p20 to p27. this register can be read or written in 8-bit or 1-bit units. reset input causes an undefined register content. figure 20-27: port register 2 (p2) remark: n = 0 to 7 (b) port mode register 2 (pm2) the pm2 register is an 8-bit register that specifies the input or output mode. this register can be read or written in 8-bit or 1-bit units. reset input sets this register to ffh. figure 20-28: port mode register 2 (pm2) remark: n = 0 to 7 pm2 is an 8 bit read/write register. it is the port mode register of port 2. pm2 determines the input or output direction of the respective port pin. after reset: undefined r/w address: fffff404h 76543210 p2 p27 p26 p25 p24 p23 p22 p21 p20 p2n input/output data control of pin p2n 0 input mode: low level is input output mode: low level is output 1 input mode: high level is input output mode: high level is output after reset: ffh r/w address: fffff424h 76543210 pm2 pm27pm26pm25pm24pm23pm22pm21pm20 pm2n input/output mode control of pin p2n (in port mode) 0 output mode 1 input mode
900 chapter 20 port functions user?s manual u16580ee2v0ud00 (c) port mode control register 2 (pmc2) the pmc2 register is an 8-bit register that specifies the port mode or control mode (alternate function). this register can be read or written in 8-bit or 1-bit units. reset input sets this register to 00h. figure 20-29: port mode control register 2 (pmc2) (1/2) after reset: 00h r/w address: fffff444h 76543210 pmc2 pmc27 pmc26 pmc25 pmc24 pmc23 pmc22 pmc21 pmc20 pmc27 port/control mode specification of pin p27 0 i/o port mode 1 control mode (alternate function) pmc26 port/control mode specification of pin p26 0 i/o port mode 1 control mode (alternate function) pmc25 port/control mode specification of pin p25 0 i/o port mode 1 control mode (alternate function) pmc24 port/control mode specification of pin p24 0 i/o port mode 1 control mode (alternate function) pm27 function 0 top71 output mode 1 tip71, tevtp6 input mode pm26 function 0 top70 output mode 1 tip70, ttrgp6 input mode pm25 function 0 top61 output mode 1 tip61, ttrgp7 input mode pm24 function 0 top60 output mode 1 tip60, tevtp7 input mode
901 chapter 20 port functions user?s manual u16580ee2v0ud00 figure 20-29: port mode control register 1 (pmc2) (2/2) pmc23 port/control mode specification of pin p23 0 i/o port mode 1 control mode (alternate function) pmc22 port/control mode specification of pin p22 0 i/o port mode 1 control mode (alternate function) pmc21 port/control mode specification of pin p21 0 i/o port mode 1 control mode (alternate function) pmc20 port/control mode specification of pin p20 0 i/o port mode 1 control mode (alternate function) pm23 function 0 top51 output mode 1 tip51, tevtp4 input mode pm22 function 0 top50 output mode 1 tip50, ttrgp4 input mode pm21 function 0 top41 output mode 1 tip41, ttrgp5 input mode pm20 function 0 top40 output mode 1 tip40, tevtp5 input mode
902 chapter 20 port functions user?s manual u16580ee2v0ud00 20.3.4 port 3 port 3 is an 8-bit i/o port that can be set to input or output mode in 1-bit units. (1) functions ? input/output data can be specified in 1-bit units by using the port register 3 (p3). ? input or output mode can be set in 1-bit units by using the port mode register 3 (pm3). ? port mode or control mode (for alternate functi on) can be specified in 1-bit units by using the port mode control register 3 (pmc3). ? the external interrupt request inputs shared with the input port functionality of port 3 are always enabled in input port mode. table 20-7: alternate function pins and port types of port 3 port alternate function remark port type port 3 p30 rxdc0, intp4 serial interface (uartc0) input external interrupt request input 9 p31 txdc0 serial interface (uartc0) output 1s p32 rxdc1, intp5 serial interface (uartc1) input external interrupt request input 9 p33 txdc1 serial interface (uartc1) output 1s p34 fcrxd0 fcan0 input 2a p35 fctxd0 fcan0 output 1s p36 fcrxd1 fcan1 input 2a p37 fctxd1 fcan1 output 1s
903 chapter 20 port functions user?s manual u16580ee2v0ud00 (2) control registers (a) port register 3 (p3) the p3 register is an 8-bit register that controls reading the pin levels and writing the output levels of port pins p30 to p37. this register can be read or written in 8-bit or 1-bit units. reset input causes an undefined register content. figure 20-30: port register 3 (p3) (b) port mode register 3 (pm3) the pm3 register is an 8-bit register that specifies the input or output mode. this register can be read or written in 8-bit or 1-bit units. reset input sets this register to ffh. figure 20-31: port mode register 3 (pm3) remark: n = 0 to 7 after reset: undefined r/w address: fffff406h 76543210 p3 p37 p36 p35 p34 p33 p32 p31 p30 p3n input/output data control of pin p3n 0 input mode: low level is input output mode: low level is output 1 input mode: high level is input output mode: high level is output after reset: ffh r/w address: fffff426h 76543210 pm3 pm37pm36pm35pm34pm33pm32pm31pm30 pm3n input/output mode control of pin p3n (in port mode) 0 output mode 1 input mode
904 chapter 20 port functions user?s manual u16580ee2v0ud00 (c) port mode control register 3 (pmc3) the pmc3 register is an 8-bit register that specifies the port mode or control mode (alternate function). this register can be read or written in 8-bit or 1-bit units. reset input sets this register to 00h. figure 20-32: port mode control register 3 (pmc3) (1/2) note: if this pin is set to port mode, the corresponding peripheral input signal (alternate function) is forced to high level internally. after reset: 00h r/w address: fffff446h 76543210 pmc3 pmc37 pmc36 pmc35 pmc34 pmc33 pmc32 pmc31 pmc30 pmc37 port/control mode specification of pin p37 0 i/o port mode 1 fctxd1 output mode pmc36 port/control mode specification of pin p36 0 i/o port mode note 1 fcrxd1 input mode pmc35 port/control mode specification of pin p35 0 i/o port mode 1 fctxd0 output mode pmc34 port/control mode specification of pin p34 0 i/o port mode note 1 fcrxd0 input mode pmc33 port/control mode specification 0 i/o port mode 1 txdc1 output mode
905 chapter 20 port functions user?s manual u16580ee2v0ud00 figure 20-32: port mode control register 3 (pmc3) (2/2) note: if this pin is set to port mode, the corresponding peripheral input signal (alternate function) is forced to high level internally. pmc33 port/control mode specification of pin p33 0 i/o port mode 1 txdc1 output mode pmc32 port/control mode specification of pin p32 0 i/o port mode note 1 rxdc1 input mode, external interrupt request input mode (intp5) pmc31 port/control mode specification of pin p31 0 i/o port mode 1 txdc0 output mode pmc30 port/control mode specification of pin p30 0 i/o port mode note 1 rxdc0 input mode, external interrupt request input mode (intp4) pm32 function 0 output mode 1 input mode, external interrupt request input mode (intp5) pm30 function 0 output mode 1 input mode, external interrupt request input mode (intp4)
906 chapter 20 port functions user?s manual u16580ee2v0ud00 20.3.5 port 4 port 4 is a 6-bit i/o port that can be set to input or output mode in 1-bit units. (1) functions ? input/output data can be specified in 1-bit units by using the port register 4 (p4). ? input or output mode can be set in 1-bit units by using the port mode register 4 (pm4). ? port mode or control mode (for alternate functi on) can be specified in 1-bit units by using the port mode control register 4 (pmc4). table 20-8: alternate function pins and port types of port 4 port alternate function remark port type port 4 p40 sib0 serial interface (csib0) input 2 p41 sob0 serial interface (csib0) output 1e p42 sckb0 serial interface (csib0) i/o 4c p43 sib1 serial interface (csib1) input 2 p44 sob1 serial interface (csib1) output 1e p45 sckb1 serial interface (csib1 i/o 4c
907 chapter 20 port functions user?s manual u16580ee2v0ud00 (2) control registers (a) port register 4 (p4) the p4 register is an 8-bit register that controls reading the pin levels and writing the output levels of port pins p40 to p45. this register can be read or written in 8-bit or 1-bit units. reset input causes an undefined register content. figure 20-33: port register 4 (p4) (b) port mode register 4 (pm4) the pm4 register is an 8-bit register that specifies the input or output mode. this register can be read or written in 8-bit or 1-bit units. reset input sets this register to ffh. figure 20-34: port mode register 4 (pm4) remark: n = 0 to 5 after reset: undefined r/w address: fffff408h 76543210 p4 0 0 p45 p44 p43 p42 p41 p40 p4n input/output data control of pin p4n 0 input mode: low level is input output mode: low level is output 1 input mode: high level is input output mode: high level is output after reset: ffh r/w address: fffff428h 76543210 pm4 1 1 pm45 pm44 pm43 pm42 pm41 pm40 pm4n input/output mode control of pin p4n (in port mode) 0 output mode 1 input mode
908 chapter 20 port functions user?s manual u16580ee2v0ud00 (c) port mode control register 4 (pmc4) the pmc4 register is an 8-bit register that specifies the port mode or control mode (alternate function). this register can be read or written in 8-bit or 1-bit units. reset input sets this register to 00h. figure 20-35: port mode control register 4 (pmc4) after reset: 00h r/w address: fffff448h 76543210 pmc4 0 0 pmc45 pmc44 pmc43 pmc42 pmc41 pmc40 pmc45 port/control mode specification of pin p45 0 i/o port mode 1 sckb1 i/o mode (input or output mode controlled by csib1) pmc44 port/control mode specification of pin p44 0 i/o port mode 1 sob1 output mode pmc43 port/control mode specification of pin p43 0 i/o port mode 1 sib1input mode pmc42 port/control mode specification of pin p42 0 i/o port mode 1 sckb0 i/o mode (input or output mode controlled by csib0) pmc41 port/control mode specification of pin p41 0 i/o port mode 1 sob0 output mode pmc40 port/control mode specification of pin p40 0 i/o port mode 1 sib0 input mode
909 chapter 20 port functions user?s manual u16580ee2v0ud00 20.3.6 port 5 port 5 is an 8-bit i/o port that can be set to input or output mode in 1-bit units. (1) functions ? input/output data can be specified in 1-bit units by using the port register 5 (p5). ? input or output mode can be set in 1-bit units by using the port mode register 5 (pm5). ? port mode or control mode (for alternate function) can be specified in 1-bit units by using the port mode control register 5 (pmc5). ? emergency shut off by es0 input signal of output buffers p51 to p56 can be controlled by port emergency shut off control register 5 (pesc5) and emergency shut off status register 5 (esost5). ? security feature to protect the timer output signals of tmr0 from unintended cpu interference. registers p5, pm5, pmc5, pesc5 and esost5 c an only be written in a special sequence. table 20-9: alternate function pins and port types of port 5 port alternate function remark port type port 5 p50 tor00 timer output (tmr0) 11 p51 tor01 13 p52 tor02 p53 tor03 p54 tor04 p55 tor05 p56 tor06 p57 tor07 11
910 chapter 20 port functions user?s manual u16580ee2v0ud00 (2) control registers (a) port register 5 (p5) the p5 register is an 8-bit register that controls reading the pin levels and writing the output levels of port pins p50 to p57. writing to the p5 register is only possible in a specific sequence, where a write access to the command register (prcmd) must be made before a write access to the p5 register is accepted. a read operation in between the two write operations is allowed, i.e. read-modify-write is possible on register p5. for details refer to 3.4.8 specific registers . this register can be read or written in 8-bit or 1-bit units. reset input causes an undefined register content. figure 20-36: port register 5 (p5) (b) port mode register 5 (pm5) the pm5 register is an 8-bit register that specifies the input or output mode. writing to the pm5 register is only possible in a specific sequence, where a write access to the command register (prcmd) must be made before a write access to the pm5 register is accepted. a read operation in between the two write operations is allowed, i.e. read-modify-write is possible on register pm5. for details refer to 3.4.8 specific registers . this register can be read or written in 8-bit or 1-bit units. reset input sets this register to ffh. figure 20-37: port mode register 5 (pm5) remark: n = 0 to 7 after reset: undefined r/w address: fffff40ah 76543210 p5 p57 p56 p55 p54 p53 p52 p51 p50 p5n input/output data control of pin p5n 0 input mode: low level is input output mode: low level is output 1 input mode: high level is input output mode: high level is output after reset: ffh r/w address: fffff42ah 76543210 pm5 pm57 pm56 pm55 pm54 pm53 pm52 pm51 pm50 pm5n input/output mode control of pin p5n (in port mode) 0 output mode 1 input mode
911 chapter 20 port functions user?s manual u16580ee2v0ud00 (c) port mode control register 5 (pmc5) the pmc5 register is an 8-bit register that specifies the port mode or control mode (alternate function). writing to the pmc5 register is only possible in a specific seque nce, where a write access to the command register (prcmd) must be made before a write access to the pmc5 register is accepted. a read operation in between the two write operations is allowed, i.e. read-modify-write is possible on register pmc5. for details refer to 3.4.8 ?specific registers? on page 127 . this register can be read or written in 8-bit or 1-bit units. reset input sets this register to 00h. figure 20-38: port mode control register 5 (pmc5)) remark: n = 0 to 7 after reset: 00h r/ w address: fffff44ah 76543210 pmc5 pmc57 pmc56 pmc55 pmc54 pmc53 pmc52 pmc51 pmc50 pmc5n port/control mode specification of pin p5n 0 i/o port mode 1 tor0n output mode
912 chapter 20 port functions user?s manual u16580ee2v0ud00 (d) port emergency shut off control register 5 (pesc5) the pesc5 register is an 8-bit re gister that controls the emergency shut of f behaviour of output buffers of ports p51 to p56. writing to the pesc5 register is only possible in a specific sequence, wher e a write access to the command register (prcmd) must be made befo re a write access to the pesc5 register is accepted. a read operation in between the two write operations is allowed, i.e. read-modify-write is possible on register pesc5. for details refer to 3.4.8 ?specific registers? on page 127 . this register can be read or written in 8-bit or 1-bit units. reset input sets this register to 00h. figure 20-39: port emergency shut off control register 5 (pesc5) caution: state of the edge detection control bits eso0ed1 and eso0ed0 must not be changed while eso0en is set (1). otherwise the output shut off function may be unintentionally triggered or a trigger event may be lost. remarks: 1. the output buffers of ports p51 to p56 are forcibly disabled (high impedance output) as long as eso0en and eso0st are set to 1. 2. setup of the emergency shut off function must be performed in the following sequence. otherwise the output shut off function may be unintentionally triggered or a trigger event may be lost. <1> power on (all registers are reset) <2> prcmd write (write protect released) <3> clear eso0en bit to 0 <4> prcmd write (write protect released) <5> clear eso0st bit of esost5 register to 0 <6> prcmd write (write protect released) <7> set eso0ed0, eso0ed1 bits <8> prcmd write (write protect released) <9> set eso0en bit to 1 after reset: 00h r/w address: fffff888h 76543210 pesc5 0 0 0 0 eso0en 0 eso0ed1 eso0edo0 eso0en emergency output shut off enable control 0 emergency shut off control by eso0 input disabled 1 emergency shut off control by eso0 input enabled eso0ed1 eso0ed0 valid edge specificatio n of emergency shut off input (eso0) 0 0 falling edge 0 1 rising edge 1 0 low level 1 1 high level
913 chapter 20 port functions user?s manual u16580ee2v0ud00 (e) port emergency shut off status register 5 (esost5) the esost5 register is an 8-bit register that indicates the emergency status control mode (alternate function). writing to the esost5 register is only possible in a specific sequence, where a write access to the command register (prcmd) must be made before a write access to the esost5 register is accepted. a read operation in between the two write operations is allowed, i.e. read-modify-write is possible on register esost5. for details refer to 3.4.8 specific registers . this register can be read or written in 8-bit or 1-bit units. reset input sets this register to 00h. figure 20-40: port emergency shut off status register 5 (esost5)) remarks: 1. writing the emergency shut off status flag (eso0st) is only possible, if the es0en bit of the pesc5 register is cleared (0). 2. the eso0st flag can only be cleared by cpu to 0. setting the eso0st flag to 1 is not possible. 3. the output buffers of p51 to p56 are forcibly disabled as long as eso0en and eso0st of the pesc5 register are set to 1. after reset: 00h r/ w address: fffff88ah 76543210 esost 5 eso0st0000000 eso0st emergency shut off status 0 no emergency shut off was triggered 1 emergency shut off of output ports p51 to p56 triggered by eso0 input
914 chapter 20 port functions user?s manual u16580ee2v0ud00 20.3.7 port 6 port 6 is an 8-bit i/o port that can be set to input or output mode in 1-bit units. (1) functions ? input/output data can be specified in 1-bit units by using the port register 6 (p6). ? input or output mode can be set in 1-bit units by using the port mode register 6 (pm6). ? port mode or control mode (for alternate functi on) can be specified in 1-bit units by using the port mode control register 6 (pmc6). ? emergency shut off by es0 input signal of output buffers p61 to p66 can be controlled by port emergency shut off control regi ster 6 (pesc6) and emergency shut off status register 6 (esost6). ? security feature to protect the timer output signals of tmr0 from unintended cpu interference. registers p6, pm6, pmc6, pesc6 and esost6 can only be written in a special sequence. table 20-10: alternate function pins and port types of port 6 port alternate function remark port type port 6 p60 tor10, ttrgr1 timer i/o (tmr1) 12 p61 tor11, tir10 14 p62 tor12, tir11 p63 tor13, tir12 p64 tor14, tir13 p65 tor15 timer output (tmr1) 13 p66 tor16 p67 tor17, tevtr1 timer i/o (tmr1) 12
915 chapter 20 port functions user?s manual u16580ee2v0ud00 (2) control registers (a) port register 6 (p6) the p6 register is an 8-bit register that controls reading the pin levels and writing the output levels of port pins p60 to p67. writing to the p6 register is only possible in a specific sequence, where a write access to the command register (prcmd) must be made before a write access to the p6 register is accepted. a read operation in between the two write operations is allowed, i.e. read-modify-write is possible on register p6. for details refer to 3.4.8 specific registers . this register can be read or written in 8-bit or 1-bit units. reset input causes an undefined register content. figure 20-41: port register 6 (p6) (b) port mode register 6 (pm6) the pm6 register is an 8-bit register that specifies the input or output mode. writing to the pm6 register is only possible in a specific sequence, where a write access to the command register (prcmd) must be made before a write access to the pm6 register is accepted. a read operation in between the two write operations is allowed, i.e. read-modify-write is possible on register pm6. for details refer to 3.4.8 specific registers . this register can be read or written in 8-bit or 1-bit units. reset input sets this register to ffh. figure 20-42: port mode register 6 (pm6) remark: n = 0 to 7 after reset: undefined r/w address: fffff40ch 76543210 p6 p67 p66 p65 p64 p63 p62 p61 p60 p6n input/output data control of pin p6n 0 input mode: low level is input output mode: low level is output 1 input mode: high level is input output mode: high level is output after reset: ffh r/w address: fffff42ch 76543210 pm6 pm67pm66pm65pm64pm63pm62pm61pm60 pm6n input/output mode control of pin p6n (in port mode) 0 output mode 1 input mode
916 chapter 20 port functions user?s manual u16580ee2v0ud00 (c) port mode control register 6 (pmc6) the pmc6 register is an 8-bit register that specifies the port mode or control mode (alternate function). writing to the pmc6 register is only possible in a specific sequence, where a write access to the command register (prcmd) must be made before a write access to the pmc6 register is accepted. a read operation in between the two write operations is allowed, i.e. read-modify-write is possible on register pmc6. for details refer to 3.4.8 specific registers . this register can be read or written in 8-bit or 1-bit units. reset input sets this register to 00h. figure 20-43: port mode control register 6 (pmc6) (1/2) after reset: 00h r/w address: fffff44ch 76543210 pmc6 pmc67 pmc66 pmc65 pmc64 pmc63 pmc62 pmc61 pmc60 pmc67 port/control mode specification of pin p67 0 i/o port mode 1 control mode pmc66 port/control mode specification of pin p66 0 i/o port mode 1 tor16 output mode pmc65 port/control mode specification of pin p65 0 i/o port mode 1 tor15 output mode pmc64 port/control mode specification of pin p64 0 i/o port mode 1 control mode pm67 function 0 tor17 output mode 1 ttevtr1 input mode pm64 function 0 tor14 output mode 1 tir13 input mode
917 chapter 20 port functions user?s manual u16580ee2v0ud00 figure 20-43: port mode control register 6 (pmc6) (2/2) remark: n = 0 to 7 pmc63 port/control mode specification of pin p63 0 i/o port mode 1 control mode pmc62 port/control mode specification of pin p62 0 i/o port mode 1 control mode pmc61 port/control mode specification of pin p61 0 i/o port mode 1 control mode pmc60 port/control mode specification of pin p60 0 i/o port mode 1 control mode pm63 function 0 tor13 output mode 1 tir12 input mode pm62 function 0 tor12 output mode 1 tir11 input mode pm61 function 0 tor11 output mode 1 tir10 input mode pm63 function 0 tor10 output mode 1 ttrgr1 input mode
918 chapter 20 port functions user?s manual u16580ee2v0ud00 (d) port emergency shut off control register 6 (pesc6) the pesc6 register is an 8-bit re gister that controls the emergency shut of f behaviour of output buffers of ports p61 to p66. writing to the pesc6 register is only possible in a specific sequence, wher e a write access to the command register (prcmd) must be made befo re a write access to the pesc6 register is accepted. a read operation in between the two write operations is allowed, i.e. read-modify-write is possible on register pesc6. for details refer to 3.4.8 specific registers . this register can be read or written in 8-bit or 1-bit units. reset input sets this register to 00h. figure 20-44: port emergency shut off control register 6 (pesc6) caution: state of the edge detection control bits eso1ed1 and eso1ed0 must not be changed while eso1en is set (1). otherwise the output shut off function may be unintentionally triggered or a trigger event may be lost. remarks: 1. the output buffers of ports p61 to p66 are forcibly disabled (high impedance output) as long as eso1en and eso1st are set to 1. 2. setup of the emergency shut off function must be performed in the following sequence. otherwise the output shut off function may be unintentionally triggered or a trigger event may be lost. <1> power on (all registers are reset) <2> prcmd write (write protect released) <3> clear eso1en bit to 0 <4> prcmd write (write protect released) <5> clear eso1st bit of esost6 register to 0 <6> prcmd write (write protect released) <7> set eso1ed0, eso1ed1 bits <8> prcmd write (write protect released) <9> set eso1en bit to 1 after reset: 00h r/w address: fffff88ch 76543210 pesc6 0 0 0 0 eso0en 0 eso0ed1 eso0edo0 eso1en emergency output shut off enable control 0 emergency shut off control by eso1 input disabled 1 emergency shut off control by eso1 input enabled eso1ed1 eso1ed0 valid edge specificatio n of emergency shut off input (eso1) 0 0 falling edge 0 1 rising edge 1 0 low level 1 1 high level
919 chapter 20 port functions user?s manual u16580ee2v0ud00 (e) port emergency shut off status register 6 (esost6) the esost6 register is an 8-bit register that indicates the emergency status control mode (alternate function). writing to the esost6 register is only possible in a specific sequence, where a write access to the command register (prcmd) must be made before a write access to the esost6 register is accepted. a read operation in between the two write operations is allowed, i.e. read-modify-write is possible on register esost6. for details refer to 3.4.8 ?specific registers? on page 127 . this register can be read or written in 8-bit or 1-bit units. reset input sets this register to 00h. figure 20-45: port emergency shut off status register 6 (esost6)) remarks: 1. writing the emergency shut off status flag (eso1st) is only possible, if the es1en bit of the pesc6 register is cleared (0). 2. the eso1st flag can only be cleared by cpu to 0. setting the eso1st flag to 1 is not possible. 3. the output buffers of p61 to p66 are forcibly disabled as long as eso1en and eso1st of the pesc6 register are set to 1. after reset: 00h r/ w address: fffff88eh 76543210 esost6 eso1st0000000 eso1st emergency shut off status 0 no emergency shut off was triggered 1 emergency shut off of output ports p61 to p66 triggered by eso1 input
920 chapter 20 port functions user?s manual u16580ee2v0ud00 20.3.8 port 7 port 7 is an 8-bit i/o port that can be set to input or output mode in 1-bit units. (1) functions ? input/output data can be specified in 1-bit units by using the port register 7 (p7). ? input or output mode can be set in 1-bit units by using the port mode register 7 (pm7). ? port mode or control mode (for alternate functi on) can be specified in 1-bit units by using the port mode control register 7 (pmc7). ? the external interrupt request input shared with the input port functionality of port 7 is always enabled in input port mode. table 20-11: alternate function pins and port types of port 7 port alternate function remark port type port 7 p70 tit00, tevt1, tot00 timer input (tmt0, tmt1) timer output (tmt0) 6 p71 tit01, ttrgt1, tot01 timer input (tmt0, tmt1 timer output (tmt0) p72 tecrt0, intp12 timer input (tmt0), external interrupt request input 8 p73 tit10, ttrgt0, tot10 timer input (tmt0, tmt1) timer output (tmt1) 6 p74 tit11, tevt0, tot11 timer input (tmt0, tmt1 timer output (tmt1) p75 tecrt1, afo timer input (tmt1) auxiliary frequency output
921 chapter 20 port functions user?s manual u16580ee2v0ud00 (2) control registers (a) port register 7 (p7) the p7 register is an 8-bit register that controls reading the pin levels and writing the output levels of port pins p70 to p75. this register can be read or written in 8-bit or 1-bit units. reset input causes an undefined register content. figure 20-46: port register 7 (p7) (b) port mode register 4 (pm7) the pm7 register is an 8-bit register that specifies the input or output mode. this register can be read or written in 8-bit or 1-bit units. reset input sets this register to ffh. figure 20-47: port mode register 7 (pm7) remark: n = 0 to 5 after reset: undefined r/w address: fffff40eh 76543210 p7 0 0 p75 p74 p73 p72 p71 p70 p7n input/output data control of pin p7n 0 input mode: low level is input output mode: low level is output 1 input mode: high level is input output mode: high level is output after reset: ffh r/w address: fffff42eh 76543210 pm7 1 1 pm75 pm74 pm73 pm72 pm71 pm70 pm7n input/output mode control of pin p7n (in port mode) 0 output mode 1 input mode
922 chapter 20 port functions user?s manual u16580ee2v0ud00 (c) port mode control register 4 (pmc7) the pmc7 register is an 8-bit register that specifies the port mode or control mode (alternate function). this register can be read or written in 8-bit or 1-bit units. reset input sets this register to 00h. figure 20-48: port mode control register 7 (pmc7) (1/2) after reset: 00h r/w address: fffff44eh 76543210 pmc7 0 0 pmc75 pmc74 pmc73 pmc72 pmc71 pmc70 pmc75 port/control mode specification of pin p75 0 i/o port mode 1 control mode pmc74 port/control mode specification of pin p74 0 i/o port mode 1 control mode pmc73 port/control mode specification of pin p73 0 i/o port mode 1 control mode pm75 function 0 afo output mode 1 tecrt1 input mode pm74 function 0 tot11 output mode 1 tit11 input mode, tevtt0 input mode pm73 function 0 tot10 output mode 1 tit10 input mode, ttrgt0 input mode
923 chapter 20 port functions user?s manual u16580ee2v0ud00 figure 20-48: port mode control register 7 (pmc7) (2/2) pmc72 port/control mode specification of pin p72 0 i/o port mode 1 tecrt0 input mode external interrupt request input mode (intp12) pmc71 port/control mode specification of pin p71 0 i/o port mode 1 control mode pmc70 port/control mode specification of pin p70 0 i/o port mode 1 control mode pm72 function 0 output mode 1 input mode, external interrupt request input mode (intp12) pm71 function 0 tot01 output mode 1 tit01, ttrgt1 input mode pm70 function 0 tot00 output mode 1 tit00, tevtt1 input mode
924 chapter 20 port functions user?s manual u16580ee2v0ud00 20.3.9 port 8 port 8 is a 7-bit i/o port that can be set to input or output mode in 1-bit units. (1) functions ? input/output data can be specified in 1-bit units by using the port register 8 (p8). ? input or output mode can be set in 1-bit units by using the port mode register 8 (pm8). ? port mode or control mode (for alternate functi on) can be specified in 1-bit units by using the port mode control register 8 (pmc8). ? the external interrupt request inputs shared with the input port functionality of port 8 are always enabled in input port mode. table 20-12: alternate function pins and port types of port 8 port alternate function remark port type port 8 p80 si30 serial interface (csi30) input 2 p81 so30 serial interface (csi30) output 1s p82 sck30 serial interface (csi30) i/o 4 p83 scs300, intp6 serial interface (csi30) output, external interrupt request input 7 p84 scs301, intp7 serial interface (csi30) output, external interrupt request input p85 scs302, intp8 serial interface (csi30) output, external interrupt request input p86 scs303, ssb0 serial interface (csi30) output, serial interface (csib0) input 5
925 chapter 20 port functions user?s manual u16580ee2v0ud00 (2) control registers (a) port register 8 (p8) the p8 register is an 8-bit register that controls reading the pin levels and writing the output levels of port pins p80 to p86. this register can be read or written in 8-bit or 1-bit units. reset input causes an undefined register content. figure 20-49: port register 8 (p8) (b) port mode register 8 (pm8) the pm8 register is an 8-bit register that specifies the input or output mode. this register can be read or written in 8-bit or 1-bit units. reset input sets this register to ffh. figure 20-50: port mode register 8 (pm8) remark: n = 0 to 6 after reset: undefined r/w address: fffff410h 76543210 p8 0 p86 p85 p84 p83 p82 p81 p80 p8n input/output data control of pin p8n 0 input mode: low level is input output mode: low level is output 1 input mode: high level is input output mode: high level is output after reset: ffh r/w address: fffff430h 76543210 pm8 1 pm86 pm85 pm84 pm83 pm82 pm81 pm80 pm8n input/output mode control of pin p8n (in port mode) 0 output mode 1 input mode
926 chapter 20 port functions user?s manual u16580ee2v0ud00 (c) port mode control register 8 (pmc8) the pmc8 register is an 8-bit register that specifies the port mode or control mode (alternate function). this register can be read or written in 8-bit or 1-bit units. reset input sets this register to 00h. figure 20-51: port mode control register 8 (pmc8) (1/2) after reset: 00h r/w address: fffff450h 76543210 pmc8 0 pmc86 pmc85 pmc84 pmc83 pmc82 pmc81 pmc80 pmc86 port/control mode specification of pin p86 0 i/o port mode 1 control mode pmc85 port/control mode specification of pin p85 0 i/o port mode 1 control mode pmc84 port/control mode specification of pin p84 0 i/o port mode 1 control mode pm86 function 0 scs303 output mode 1 ssb0 input mode pm85 function 0 output mode 1 input mode, external interrupt request input mode (intp8) pm85 function 0 scs302 output mode 1 external interrupt request input mode (intp8) pm84 function 0 output mode 1 input mode, external interrupt request input mode (intp7) pm84 function 0 scs301 output mode 1 external interrupt request input mode (intp7)
927 chapter 20 port functions user?s manual u16580ee2v0ud00 figure 20-51: port mode control register 8 (pmc8) (2/2) pmc83 port/control mode specification of pin p83 0 i/o port mode 1 control mode pmc82 port/control mode specification of pin p82 0 i/o port mode 1 sck30 i/o mode pmc81 port/control mode specification of pin p81 0 i/o port mode 1 so30 output mode pmc80 port/control mode specification of pin p80 0 i/o port mode 1 si30 input mode pm83 function 0 output 1 input, external interrupt request input mode (intp6) pm83 function 0 scs300 output mode 1 external interrupt request input mode (intp6)
928 chapter 20 port functions user?s manual u16580ee2v0ud00 20.3.10 port 9 port 9 is a 7-bit i/o port that can be set to input or output mode in 1-bit units. (1) functions ? input/output data can be specified in 1-bit units by using the port register 9 (p9). ? input or output mode can be set in 1-bit units by using the port mode register 9 (pm9). ? port mode or control mode (for alternate functi on) can be specified in 1-bit units by using the port mode control register 9 (pmc9). ? the external interrupt request inputs shared with the input port functionality of port 9 are always enabled in input port mode. table 20-13: alternate function pins and port types of port 9 port alternate function remark port type port 9 p90 si31 serial interface (csi31) input 2 p91 so31 serial interface (csi31) output 1s p92 sck31 serial interface (csi31) i/o 4 p93 scs310, intp9 serial interface (csi31) output, external interrupt request input 7 p94 scs311, intp10 serial interface (csi31) output, external interrupt request input p95 scs312, intp11 serial interface (csi31) output, external interrupt request input p96 scs313, ssb1 serial interface (csi31) output, serial interface (csib1) input 5
929 chapter 20 port functions user?s manual u16580ee2v0ud00 (2) control registers (a) port register 9 (p9) the p9 register is an 8-bit register that controls reading the pin levels and writing the output levels of port pins p90 to p96. this register can be read or written in 8-bit or 1-bit units. reset input causes an undefined register content. figure 20-52: port register 9 (p9) (b) port mode register 9 (pm9) the pm9 register is an 8-bit register that specifies the input or output mode. this register can be read or written in 8-bit or 1-bit units. reset input sets this register to ffh. figure 20-53: port mode register 9 (pm9) remark: n = 0 to 6 after reset: undefined r/w address: fffff412h 76543210 p9 0 p96 p95 p94 p93 p92 p91 p90 p9n input/output data control of pin p9n 0 input mode: low level is input output mode: low level is output 1 input mode: high level is input output mode: high level is output after reset: ffh r/w address: fffff432h 76543210 pm9 1 pm96 pm95 pm94 pm93 pm92 pm91 pm90 pm9n input/output mode control of pin p9n (in port mode) 0 output mode 1 input mode
930 chapter 20 port functions user?s manual u16580ee2v0ud00 (c) port mode control register 9 (pmc9) the pmc9 register is an 8-bit register that specifies the port mode or control mode (alternate function). this register can be read or written in 8-bit or 1-bit units. reset input sets this register to 00h. figure 20-54: port mode control register 9 (pmc9) (1/2) after reset: 00h r/w address: fffff452h 76543210 pmc9 0 pmc96 pmc95 pmc94 pmc93 pmc92 pmc91 pmc90 pmc96 port/control mode specification of pin p96 0 i/o port mode 1 control mode pmc95 port/control mode specification of pin p95 0 i/o port mode 1 control mode pmc94 port/control mode specification of pin p94 0 i/o port mode 1 control mode pm96 function 0 scs313 output mode 1 ssb1 input mode pm95 function 0 output mode 1 input mode, external interrupt request input mode (intp11) pm95 function 0 scs312 output mode 1 external interrupt request input mode (intp11) pm94 function 0 output mode 1 input mode, external interrupt request input mode (intp10) pm94 function 0 scs311 output mode 1 external interrupt request input mode (intp10)
931 chapter 20 port functions user?s manual u16580ee2v0ud00 figure 20-54: port mode control register 9 (pmc9) (2/2) pmc93 port/control mode specification of pin p93 0 i/o port mode 1 control mode pmc92 port/control mode specification of pin p92 0 i/o port mode 1 sck31 i/o mode pmc91 port/control mode specification of pin p91 0 i/o port mode 1 so31 output mode pmc90 port/control mode specification of pin p90 0 i/o port mode 1 si31 input mode pm93 function 0 output mode 1 input mode, external interrupt request input mode (intp9) pm93 function 0 scs310 output mode 1 external interrupt request input mode (intp9
932 chapter 20 port functions user?s manual u16580ee2v0ud00 20.3.11 port 10 port 10 is a 3-bit i/o port that can be set to input or output mode in 1-bit units. (1) functions ? input/output data can be specified in 1-bit units by using the port register 10 (p10). ? input or output mode can be set in 1-bit units by using the port mode register 10 (pm10). ? port mode or control mode (for alternate functi on) can be specified in 1-bit units by using the port mode control register 10 (pmc10). table 20-14: alternate function pins and port types of port 10 port alternate function remark port type port 10 p100 tclr0, ticc00, top81 timer input (itenc0) timer output (tmp8) 6 p101 tcud0, ticc01 timer input (itenc0) 10 p102 tiud0, to1 timer input (itenc0), timer output (itenc0) 6
933 chapter 20 port functions user?s manual u16580ee2v0ud00 (2) control registers (a) port register 10 (p10) the p10 register is an 8-bit register that contro ls reading the pin levels and writing the output levels of port pins p100 to p105. this register can be read or written in 8-bit or 1-bit units. reset input causes an undefined register content. figure 20-55: port register 10 (p10) (b) port mode register 10 (pm10) the pm10 register is an 8-bit register that specifies the input or output mode. this register can be read or written in 8-bit or 1-bit units. reset input sets this register to ffh. figure 20-56: port mode register 10 (pm10) remark: n = 0 to 2 after reset: undefined r/w address: fffff414h 76543210 p10 00000p102p101p100 p10n input/output data control of pin p10n 0 input mode: low level is input output mode: low level is output 1 input mode: high level is input output mode: high level is output after reset: ffh r/w address: fffff434h 76543210 pm1011111pm102pm101pm100 pm10n input/output mode contro l of pin p10n (in port mode) 0 output mode 1 input mode
934 chapter 20 port functions user?s manual u16580ee2v0ud00 (c) port mode control register 10 (pmc10) the pmc10 register is an 8-bit register that specifies the port mode or control mode (alternate function). this register can be read or written in 8-bit or 1-bit units. reset input sets this register to 00h. figure 20-57: port mode control register 10 (pmc10) after reset: 00h r/w address: fffff454h 76543210 pmc10 0 0 0 0 0 pmc102 pmc101 pmc100 pmc102 port/control mode specification of pin p102 0 i/o port mode 1 control mode pmc101 port/control mode specification of pin p101 0 i/o port mode 1 tcud0 input mode, ticc01 input mode pmc100 port/control mode specification of pin p100 0 i/o port mode 1 control mode pm102 function 0 top81 output mode 1 tclr0 input mode, ticc0 input mode pm100 function 0 to1 output mode 1 tiud0 input mode
935 chapter 20 port functions user?s manual u16580ee2v0ud00 20.3.12 port al port al is a 16-bit i/o port that can be set to input or output mode in 1-bit units. when the higher 8 bits of port al are used as port alh (palh) and the lower 8 bits as port all (pall), port al becomes two 8-bit ports that can be set in the input or output mode in 1-bit units. (1) functions ? input/output data can be specified in 1-bit units by using the port register al (pal). ? input or output mode can be set in 1-bit units by using the port mode register al (pmal). ? port mode or control mode (for alternate function) can be specified in 1-bit units by using the port mode control register al (pmcal). table 20-15: alternate function pins and port types of port al caution: in single-chip mode 1 and in rom-less mode this port has external address bus function only. reprogramming of port al to port mode is not possible in these modes. reading and writing of the port register pal and port mode register pmal is possible but has no effect. reading of the port mode control register pmcal is possible and the result is always ffffh. writing of the port mode control register pmcal is not possible. port alternate function remark port type port al pal0 to pa l 1 5 a0 to a15 external address bus 1
936 chapter 20 port functions user?s manual u16580ee2v0ud00 (2) control registers (a) port register al (pal) the pal register is a 16-bit register that contro ls reading the pin levels and writing the output levels of port pins pal0 to pal15. this register can be read or written in 16-bit units. if the higher 8 bits of the pal register are used as palh register, and the lower 8 bits as the pall register, however, these registers can be read or written in 8-bit or 1-bit units. reset input causes an undefined register content. figure 20-58: port register al(pal) remark: n = 0 to 15 after reset: undefined r/w address: fffff000h 1514131211109876543210 pa l pal15 pal14 pal13 pal12 pal11 pal10 pal9 pal8 pal7 pal6 pal5 pal4 pal3 pal2 pal1 pal0 pa l h pa l l after reset: undefined r/w address: fffff000h 76543210 pa l l pa l 7 pa l 6 pa l 5 pa l 4 pa l 3 pa l 2 pa l 1 pa l 0 after reset: undefined r/w address: fffff001h 76543210 palh pal15 pal14 pal13 pal12 pal11 pal10 pal9 pal8 paln input/output data control of pin paln 0 input mode: low level is input output mode: low level is output 1 input mode: high level is input output mode: high level is output
937 chapter 20 port functions user?s manual u16580ee2v0ud00 (b) port mode register al (pmal) the pmal register is a 16-bit register that specifies the input or output mode of port pins pal0 to pal15. this register can be read or written in 16-bit units. if the higher 8 bits of the pmal register are used as pmalh register, and the lower 8 bits as the pmall register, however, these registers can be read or written in 8-bit or 1-bit units. reset input sets this register to ffffh. figure 20-59: port mode register al(pmal) remark: n = 0 to 15 after reset: ffffh r/w address: fffff020h 1514131211109876543210 pmal pmal 15 pmal 14 pmal 13 pmal 12 pmal 11 pmal 10 pmal 9 pmal 8 pmal 7 pmal 6 pmal 5 pmal 4 pmal 3 pmal 2 pmal 1 pmal 0 pmalh pmall after reset: ffh r/w address: fffff020h 76543210 pmall pmal7 pmal6 pmal5 pmal4 pmal3 pmal2 pmal1 pmal0 after reset: ffh r/w address: fffff021h 76543210 pmalh pmal15 pmal14 pmal13 pmal12 pmal11 pmal10 pmal9 pmal8 pmaln input/output mode control of pin paln (in port mode) 0 output mode 1 input mode
938 chapter 20 port functions user?s manual u16580ee2v0ud00 (c) port al mode control register the pmcal register is a 16-bit read/write register that specifies the port mode or control mode (alternate function) of port al. this register can be read or written in 16-bit units. if the higher 8 bits of the pmcal register are used as pmcalh register, and the lower 8 bits as the pmcall register, however, these registers can be read or written in 8-bit or 1-bit units. reset input sets this register to 0000h in single-chip mode 0, and to ffffh in rom-less mode and single-chip mode 1. figure 20-60: port mode control register al (pmcal) notes: 1. in single-chip mode 0: 0000h, or 00h respectively in single-chip mode 1 and rom-less mode: ffffh, or ffh respectively 2. in the single-chip mode 1 or in the rom-less mode, this register can not be written. reading is possible and returns ffffh, or ffh respectively. remark: n = 0 to 15 after reset note 1 : 0000h/ ffffh r/w note 2 address: fffff040h 1514131211109876543210 pmcal pmcal 15 pmcal 14 pmcal 13 pmcal 12 pmcal 11 pmcal 10 pmcal 9 pmcal 8 pmcal 7 pmcal 6 pmcal 5 pmcal 4 pmcal 3 pmcal 2 pmcal 1 pmca l0 pmcalh pmcall after reset note 1 :00h/ffh r/w note 2 address: fffff040h 76543210 pmcall pmcal7 pmcal6 pmcal5 pmcal4 pmcal3 pmcal2 pmcal1 pmcal0 after reset note 1 :00h/ffh r/w note 2 address: fffff041h 76543210 pmcalh pmcal15 pmcal14 pmcal13 pmcal12 pmcal11 pmcal10 pmcal9 pmcal8 pmcaln port/control mode specification of pin paln 0 i/o port mode 1 external address bus output mode (a15 to a0)
939 chapter 20 port functions user?s manual u16580ee2v0ud00 20.3.13 port ah port ah is a 6-bit i/o port that can be set to input or output mode in 1-bit units. (1) functions ? input/output data can be specified in 1-bit units by using the port register ah (pah). ? input or output mode can be set in 1-bit units by using the port mode register ah (pmah). ? port mode or control mode (for alternate function) can be specified in 1-bit units by using the port mode control register ah (pmcah). table 20-16: alternate function pins and port types of port ah caution: in single-chip mode 1 and in rom-less mode this port has external address bus function only. reprogramming of port ah to port mode is not possible in these modes. reading and writing of the port register pah and port mode register pmah is possible but has no effect. reading of the port mode control register pmcah is possible and the result is always 3fh. writing of the port mode control register pmcah is not possible. (2) control registers (a) port register ah (pah) the pah register is an 8-bit register that controls reading the pin levels and writing the output levels of port pins pah0 to pah5. this register can be read or written in 8-bit or 1-bit units. reset input causes an undefined register content. figure 20-61: port register ah (pah) remark: n = 0 to 5 port alternate function remark port type port ah pah0 to pa h 5 a16 to a21 external address bus 1 after reset: undefined r/w address: fffff002h 76543210 pah 0 0 pah5 pah4 pah3 pah2 pah1 pah0 pahn input/output data control of pin pahn 0 input mode: low level is input output mode: low level is output 1 input mode: high level is input output mode: high level is output
940 chapter 20 port functions user?s manual u16580ee2v0ud00 (b) port mode register ah (pmah) the pmah register is an 8-bit register that specif ies the input or output mode of port pins pal0 to pal15. this register can be read or written in 8-bit units. reset input sets this register to ffh. figure 20-62: port mode register ah (pmah) (c) port mode control register ah (pmcah) the pmcahl register is an 8-bit register that specifies the port mode or control mode (alternate function) of port al. this register can be read or written in 8-bit units. reset input sets this register to 00h in single-chip mode 0, and to 3fh in rom-less mode and single-chip mode 1. figure 20-63: port mode cont rol register ah (pmcah) notes: 1. in single-chip mode 0: 00h in single-chip mode 1 and rom-less mode: 3fh 2. in the single-chip mode 1 or in the rom-less mode, this register can not be written. reading is possible and returns 3fh. remark: n = 0 to 5 after reset: ffh r/w address: fffff022h 76543210 pmah 1 1 pmah5 pmah4 pmah3 pmah2 pmah1 pmah0 pmahn input/output mode control of pin pahn (in port mode) 0 output mode 1 input mode after reset note 1 :00h/3fh r/w note 2 address: fffff042h 76543210 pmcah 0 0 pmcah5 pmcah4 pmcah3 pmcah2 pmcah1 pmcah0 pmcahn port/control mode specification of pin pahn 0 i/o port mode 1 external memory address bus output mode (a21 to a16)
941 chapter 20 port functions user?s manual u16580ee2v0ud00 20.3.14 port dl port dl is a 16-bit i/o port that can be set to input or output mode in 1-bit units. when the higher 8 bits of port dl are used as port dlh (pdlh) and the lower 8 bits as port dll (pdll), port dl becomes two 8-bit ports that can be set in the input or output mode in 1-bit units. (1) functions ? input/output data can be specified in 1-bit units by using the port register dl (pdl). ? input or output mode can be set in 1-bit units by using the port mode register dl (pmdl). ? port mode or control mode (for alternate function) can be specified in 1-bit units by using the port mode control register dl (pmcdl). table 20-17: alternate function pins and port types of port dl caution: in single-chip mode 1 and in rom-less mode this port has external data bus function only. reprogramming of port dl to port mode is not possible in these modes. reading and writing of the port register pdl and port mode register pmdl is possible but has no effect. reading of the port mode control register pmcdl is possible and the result is always ffffh. writing of the port mode control register pmcdl is not possible. port alternate function remark port type port dl pdl0 to pdl15 d0 to d15 external data bus 4c
942 chapter 20 port functions user?s manual u16580ee2v0ud00 (2) control registers (a) port register dl (pdl) the pdl register is a 16-bit register that controls reading the pin levels and writing the output levels of port pins pdl0 to pdl15. this register can be read or written in 16-bit units. if the higher 8 bits of the pdl register are used as pdlh register, and the lower 8 bits as the pdll register, however, these registers can be read or written in 8-bit or 1-bit units. reset input causes an undefined register content. figure 20-64: port register dl(pdl) remark: n = 0 to 15 after reset: undefined r/w address: fffff004h 1514131211109876543210 pdl pdl15 pdl14 pdl13 pdl12 pdl11 pdl10 pdl9 pdl8 pdl7 pdl6 pdl5 pdl4 pdl3 pdl2 pdl1 pdl0 pdlh pdll after reset: undefined r/w address: fffff004h 76543210 pdll pdl7 pdl6 pdl5 pdl4 pdl3 pdl2 pdl1 pdl0 after reset: undefined r/w address: fffff005h 76543210 pdlh pdl15 pdl14 pdl13 pdl12 pdl11 pdl10 pdl9 pdl8 pdln input/output data control of pin pdln 0 input mode: low level is input output mode: low level is output 1 input mode: high level is input output mode: high level is output
943 chapter 20 port functions user?s manual u16580ee2v0ud00 (b) port mode register dl (pmdl) the pmdl register is a 16-bit register that specifies the input or output mode of port pins pdl0 to pdl15. this register can be read or written in 16-bit units. if the higher 8 bits of the pmdl register are us ed as pmdlh register, and the lower 8 bits as the pmdll register, however, these registers can be read or written in 8-bit or 1-bit units. reset input sets this register to ffffh. figure 20-65: port mode register dl(pmdl) remark: n = 0 to 15 after reset: ffffh r/w address: fffff024h 1514131211109876543210 pmdl pmdl 15 pmdl 14 pmdl 13 pmdl 12 pmdl 11 pmdl 10 pmdl 9 pmdl 8 pmdl 7 pmdl 6 pmdl 5 pmdl 4 pmdl 3 pmdl 2 pmdl 1 pmdl 0 pmdlh pmdll after reset: ffh r/w address: fffff024h 76543210 pmdll pmdl7 pmdl6 pmdl5 pmdl4 pmdl3 pmdl2 pmdl1 pmdl0 after reset: ffh r/w address: fffff025h 76543210 pmdlh pmdl15 pmdl14 pmdl13 pmdl12 pmdl11 pmdl10 pmdl9 pmdl8 pmdln input/output mode control of pin pdln (in port mode) 0 output mode 1 input mode
944 chapter 20 port functions user?s manual u16580ee2v0ud00 (c) port mode control register dl (pmcdl) the pmcdl register is a 16-bit read/write register that specifies the port mode or control mode (alternate function) of port dl. this register can be read or written in 16-bit units. if the higher 8 bits of the pmcdl register are us ed as pmcdlh register, and the lower 8 bits as the pmcdll register, however, these registers can be read or written in 8-bit or 1-bit units. reset input sets this register to 0000h in single-chip mode 0, and to ffffh in rom-less mode and single-chip mode 1. figure 20-66: port mode control register dl (pmcdl) notes: 1. in single-chip mode 0: 0000h, or 00h respectively in single-chip mode 1 and rom-less mode: ffffh, or ffh respectively 2. in the single-chip mode 1 or in the rom-less mode, this register can not be written. reading is possible and returns ffffh, or ffh respectively. remark: n = 0 to 15 after reset note 1 : 0000h/ ffffh r/w note 2 address: fffff044h 1514131211109876543210 pmcdl pmcdl 15 pmcdl 14 pmcdl 13 pmcdl 12 pmcdl 11 pmcdl 10 pmcdl 9 pmcdl 8 pmcdl 7 pmcdl 6 pmcdl 5 pmcdl 4 pmcdl 3 pmcdl 2 pmcdl 1 pmcd l0 pmcdlh pmcdll after reset note 1 :00h/ffh r/w note 2 address: fffff044h 76543210 pmcdll pmcdl7 pmcdl6 pmcdl5 pmcdl4 pmcdl3 pmcdl2 pmcdl1 pmcdl0 after reset note 1 :00h/ffh r/w note 2 address: fffff045h 76543210 pmcdlh pmcdl15 pmcdl14 pmcdl13 pmcdl12 pmcdl11 pmcdl10 pmcdl9 pmcdl8 pmcdln port/control mode specification of pin pdln 0 i/o port mode 1 external data bus output mode (d15 to d0)
945 chapter 20 port functions user?s manual u16580ee2v0ud00 20.3.15 port dh port dh is a 16-bit i/o port that can be set to input or output mode in 1-bit units. when the higher 8 bits of port dh are used as port dhh (pdhh) and the lower 8 bits as port dhl (pdhl), port dh becomes two 8-bit ports that can be set in the input or output mode in 1-bit units. (1) functions ? input/output data can be specified in 1-bit units by using the port register dh (pdh). ? input or output mode can be set in 1-bit units by using the port mode register dh (pmdh). ? port mode or control mode (for alternate function) can be specified in 1-bit units by using the port mode control register dh (pmcdh). table 20-18: alternate function pins and port types of port dh caution: in single-chip mode 1 and in rom-less mode this port has external data bus function only. reprogramming of port dh to port mode is not possible in these modes. reading and writing of the port register pdh and port mode register pmdh is possible but has no effect. reading of the port mode control register pmcdh is possible and the result is always ffffh. writing of the port mode control register pmcdh is not possible. port alternate function remark port type port dh pdh0 to pdh15 d16 to d31 external data bus 4c
946 chapter 20 port functions user?s manual u16580ee2v0ud00 (2) control registers (a) port register dh (pdh) the pdh register is a 16-bit register that controls reading the pin levels and writing the output levels of port pins pdh0 to pdh15. this register can be read or written in 16-bit units. if the higher 8 bits of the pdh register are used as pdhh register, and the lower 8 bits as the pdhl register, however, these registers can be read or written in 8-bit or 1-bit units. reset input causes an undefined register content. figure 20-67: port register dh(pdh) remark: n = 0 to 15 after reset: undefined r/w address: fffff006h 1514131211109876543210 pdh pdh15 pdh14 pdh13 pdh12 pdh11 pdh10 pdh9 pdh8 pdh7 pdh6 pdh5 pdh4 pdh3 pdh2 pdh1 pdh0 pdhh pdhl after reset: undefined r/w address: fffff006h 76543210 pdhl pdh7 pdh6 pdh5 pdh4 pdh3 pdh2 pdh1 pdh0 after reset: undefined r/w address: fffff007h 76543210 pdhh pdh15 pdh14 pdh13 pdh12 pdh11 pdh10 pdh9 pdh8 pdhn input/output data control of pin pdhn 0 input mode: low level is input output mode: low level is output 1 input mode: high level is input output mode: high level is output
947 chapter 20 port functions user?s manual u16580ee2v0ud00 (b) port mode register dh (pmdh) the pmdh register is a 16-bit register that specif ies the input or output mode of port pins pdh0 to pdh15. this register can be read or written in 16-bit units. if the higher 8 bits of the pmdh register are us ed as pmdhh register, and the lower 8 bits as the pmdhl register, however, these registers can be read or written in 8-bit or 1-bit units. reset input sets this register to ffffh. figure 20-68: port mode register dh(pmdh) remark: n = 0 to 15 after reset: ffffh r/w address: fffff026h 1514131211109876543210 pmdh pmdh 15 pmdh 14 pmdh 13 pmdh 12 pmdh 11 pmdh 10 pmdh 9 pmdh 8 pmdh 7 pmdh 6 pmdh 5 pmdh 4 pmdh 3 pmdh 2 pmdh 1 pmdh 0 pmdhh pmdhl after reset: ffh r/w address: fffff026h 76543210 pmdhl pmdh7 pmdh6 pmdh5 pmdh4 pmdh3 pmdh2 pmdh1 pmdh0 after reset: ffh r/w address: fffff027h 76543210 pmdhh pmdh15 pmdh14 pmdh13 pmdh12 pmdh11 pmdh10 pmdh9 pmdh8 pmdhn input/output mode control of pin pdhn (in port mode) 0 output mode 1 input mode
948 chapter 20 port functions user?s manual u16580ee2v0ud00 (c) port mode control register dh (pmcdh) the pmcdh register is a 16-bit read/write register that specifies the port mode or control mode (alternate function) of port dh. this register can be read or written in 16-bit units. if the higher 8 bits of the pmcdh register are used as pmcdhh register, and the lower 8 bits as the pmcdhl register, however, these registers can be read or written in 8-bit or 1-bit units. reset input sets this register to 0000h in single-chip mode 0, and to ffffh in rom-less mode and single-chip mode 1. figure 20-69: port mode contro l register dh (pmcdh) notes: 1. in single-chip mode 0: 0000h, or 00h respectively in single-chip mode 1 and rom-less mode: ffffh, or ffh respectively 2. in the single-chip mode 1 or in the rom-less mode, this register can not be written. reading is possible and returns ffffh, or ffh respectively. remark: n = 0 to 15 after reset note 1 : 0000h/ ffffh r/w note 2 address: fffff046h 1514131211109876543210 pmcdh pmcd h15 pmcd h14 pmcd h13 pmcd h12 pmcd h11 pmcd h10 pmcd h9 pmcd h8 pmcd h7 pmcd h6 pmcd h5 pmcd h4 pmcd h3 pmcd h2 pmcd h1 pmcd h0 pmcdhh pmcdhl after reset note 1 :00h/ffh r/w note 2 address: fffff046h 76543210 pmcdhl pmcdh7 pmcdh6 pmcdh5 pmcdh4 pmcdh3 pmcdh2 pmcdh1 pmcdh0 after reset note 1 :00h/ffh r/w note 2 address: fffff047h 76543210 pmcdhh pmcdh15 pmcdh14 pmcdh13 pmcdh12 pmcdh11 pmcdh10 pmcdh9 pmcdh8 pmcdhn port/control mode specification of pin pdhn 0 i/o port mode 1 external memory address bus output mode (d31 to d16)
949 chapter 20 port functions user?s manual u16580ee2v0ud00 20.3.16 port cs port cs is a 4-bit i/o port that can be set to input or output mode in 1-bit units. (1) functions ? input/output data can be specified in 1-bit units by using the port register cs (pcs). ? input or output mode can be set in 1-bit units by using the port mode register cs (pmcs). ? port mode or control mode (for alternate function) can be specified in 1-bit units by using the port mode control register cs (pmccs). table 20-19: alternate function pins and port types of port cs caution: in single-chip mode 1 and in rom-less mode this port has external control bus function only. reprogramming of port cs to port mode is not possible in these modes. reading and writing of the port register pcs and port mode register pmcs is possible but has no effect. reading of the port mode control register pmccs is possible and the result is always 1bh. writing of the port mode control register pmccs is not possible. (2) control registers (a) port register cs (pcs) the pcs register is an 8-bit register that controls reading the pin levels and writing the output levels of port pins pcs0, pcs1, pcs3 and pcs4. this register can be read or written in 8-bit or 1-bit units. reset input causes an undefined register content. figure 20-70: port register cs (pcs) remark: n = 0, 1, 3, 4 port alternate function remark port type port cs pcs0 to pcs5 cs0 chip select signal output 1 cs1 cs3 cs4 after reset: undefined r/w address: fffff008h 76543210 pcs 0 0 0 pcs4 pcs3 0 pcs1 pcs0 pcsn input/output data control of pin pcsn 0 input mode: low level is input output mode: low level is output 1 input mode: high level is input output mode: high level is output
950 chapter 20 port functions user?s manual u16580ee2v0ud00 (b) port mode register cs (pmcs) the pmcs register is an 8-bit register that specifies the input or output mode of port pins pcs0, pcs1, pcs3 and pcs4. this register can be read or written in 8-bit units. reset input sets this register to ffh. figure 20-71: port mode register cs (pmcs) (c) port mode control register cs (pmccs) the pmccsl register is an 8-bit register that specifies the port mode or control mode (alternate function) of port pins pc s0, pcs1, pcs3 and pcs4. this register can be read or written in 8-bit units. reset input sets this register to 00h in single-chip mode 0, and to 1bh in rom-less mode and single-chip mode 1. figure 20-72: port mode control register cs (pmccs) notes: 1. in single-chip mode 0: 00h in single-chip mode 1 and rom-less mode: 1bh 2. in the single-chip mode 1 or in the rom-less mode, this register can not be written. reading is possible and returns 1bh. remark: n = 0, 1, 3, 4 after reset: ffh r/w address: fffff028h 76543210 pmcs 1 1 1 pmcs4 pmcs3 1 pmcs1 pmcs0 pmcsn input/output mode control of pin pcsn (in port mode) 0 output mode 1 input mode after reset note 1 :00h/3fh r/w note 2 address: fffff048h 76543210 pmccs 0 0 0 pmccs4 pmccs3 0 pmccs1 pmccs0 pmccsn port/control mode specification of pin pcsn 0 i/o port mode 1 chip select signal output mode (csn )
951 chapter 20 port functions user?s manual u16580ee2v0ud00 20.3.17 port ct port ct is a 2-bit i/o port that can be set to input or output mode in 1-bit units. (1) functions ? input/output data can be specified in 1-bit units by using the port register ct (pct). ? input or output mode can be set in 1-bit units by using the port mode register ct (pmct). ? port mode or control mode (for alternate function) can be specified in 1-bit units by using the port mode control register ct (pmcct). table 20-20: alternate function pins and port types of port ct caution: in single-chip mode 1 and in rom-less mode this port has external control bus function only. reprogramming of port ct to port mode is not possible in these modes. reading and writing of the port register pct and port mode register pmct is possible but has no effect. reading of the port mode control register pmcct is possible and the result is always 30h. writing of the port mode control register pmcct is not possible. (2) control registers (a) port register ct (pct) the pct register is an 8-bit register that controls reading the pin levels and writing the output levels of port pins pct4 and pct5. this register can be read or written in 8-bit or 1-bit units. reset input causes an undefined register content. figure 20-73: port register ct (pct) remark: n = 4, 5 port alternate function remark port type port ct pct4 rd read strobe signal output 1 pct5 wr write strobe signal output after reset: undefined r/w address: fffff00ah 76543210 pct 00pct5pct40000 pctn input/output data control of pin pctn 0 input mode: low level is input output mode: low level is output 1 input mode: high level is input output mode: high level is output
952 chapter 20 port functions user?s manual u16580ee2v0ud00 (b) port mode register ct (pmct) the pmct register is an 8-bit register that specifies the input or output mode of port pins pct4 and pct5. this register can be read or written in 8-bit or 1-bit units. reset input sets this register to ffh. figure 20-74: port mode register ct (pmct) (c) port mode control register ct (pmcct) the pmcctl register is an 8-bit register that specifies the port mode or control mode (alternate function) of port pins pct4 and pct5. this register can be read or written in 8-bit or 1-bit units. reset input sets this register to 00h in single-chip mode 0, and to 30h in rom-less mode and single-chip mode 1. figure 20-75: port mode control register ct (pmcct) notes: 1. in single-chip mode 0: 00h in single-chip mode 1 and rom-less mode: 30h 2. in the single-chip mode 1 or in the rom-less mode, this register can not be written. reading is possible and returns 30h. remark: n = 4, 5 after reset: ffh r/w address: fffff02ah 76543210 pmct11pmct5pmct41111 pmctn input/output mode control of pin pctn (in port mode) 0 output mode 1 input mode after reset note 1 :00h/3fh r/w note 2 address: fffff04ah 76543210 pmcct00pmcct5pmcct40000 pmcct5 port/control mode specification of pin pct5 0 i/o port mode 1 write strobe signal output mode (wr ) pmcct4 port/control mode specification of pin pct4 0 i/o port mode 1 read strobe signal output mode (rd )
953 chapter 20 port functions user?s manual u16580ee2v0ud00 20.3.18 port cm port cm is a 4-bit i/o port that can be set to input or output mode in 1-bit units. (1) functions ? input/output data can be specified in 1-bit units by using the port register cm (pcm). ? input or output mode can be set in 1-bit units by using the port mode register cm (pmcm). ? port mode or control mode (for alternate function) can be specified in 1-bit units by using the port mode control register cm (pmccm). table 20-21: alternate function pins and port types of port cm caution: in single-chip mode 1 and in rom-less mode this port has external control bus function only. reprogramming of port cm to port mode is not possible in these modes. reading and writing of the port register pcm and port mode register pmcm is possible but has no effect. reading of the port mode control register pmccm is possible and the result is always 01h. writing of the port mode control register pmccm is not possible. (2) control registers (a) port register cm (pcm) the pcm register is an 8-bit register that controls reading the pin levels and writing the output levels of port pins pcm0, pcm1, pcm6 and pcm7. this register can be read or written in 8-bit or 1-bit units. reset input causes an undefined register content. figure 20-76: port register cm (pcm) remark: n = 0, 1, 6, 7 port alternate function remark port type port cm pcm0 wait wait insertion signal input 2c pcm1 - 1 pcm6 - pcm7 - after reset: undefined r/w address: fffff00ch 76543210 pcmpcm7pcm60000pcm1pcm0 pcmn input/output data control of pin pcmn 0 input mode: low level is input output mode: low level is output 1 input mode: high level is input output mode: high level is output
954 chapter 20 port functions user?s manual u16580ee2v0ud00 (b) port mode register cm (pmcm) the pmcm register is an 8-bit register that specifies the input or output mode of port pins pcm0, pcm1, pcm6 and pcm7. this register can be read or written in 8-bit or 1-bit units. reset input sets this register to ffh. figure 20-77: port mode register cm (pmcm) remark: n = 0, 1, 6, 7 after reset: ffh r/w address: fffff02ch 76543210 pmcmpmcm7pmcm61111pmcm1pmcm0 pmcmn input/output mode control of pin pcmn (in port mode) 0 output mode 1 input mode
955 chapter 20 port functions user?s manual u16580ee2v0ud00 (c) port mode control register cm (pmccm) the pmccml register is an 8-bit register that specifies the port mode or control mode (alternate function) of port pins pcm0, pcm1, pcm6 and pcm7. this register can be read or written in 8-bit or 1-bit units. reset input sets this register to 00h in single-chip mode 0, and to 01h in rom-less mode and single-chip mode 1. figure 20-78: port mode control register cm (pmccm) notes: 1. in single-chip mode 0: 00h in single-chip mode 1 and rom-less mode: 01h 2. in the single-chip mode 1 or in the rom-less mode, this register can not be written. reading is possible and returns 01h. after reset note 1 : 00h/01h r/w note 2 address: fffff04ch 76543210 pmccm0000000pmccm0 pmccm0 port/control mode specification of pin pcm0 0 i/o port mode 1 wait insertion signal input mode (wait )
956 chapter 20 port functions user?s manual u16580ee2v0ud00 20.3.19 port cd port cd is a 4-bit i/o port that can be set to input or output mode in 1-bit units. (1) functions ? input/output data can be specified in 1-bit units by using the port register cd (pcd). ? input or output mode can be set in 1-bit units by using the port mode register cd (pmcd). ? port mode or control mode (for alternate functi on) can be specified in 1-bit units by using the port mode control register cd (pmccd). table 20-22: alternate function pins and port types of port cd caution: in single-chip mode 1 and in rom-less mode this port has external control bus function only. reprogramming of port cd to port mode is not possible in these modes. reading and writing of the port regi ster pcd and port mode register pmcd is possible but has no effect. reading of the port mode control register pmccd is possible and the result is always 3ch. writing of the port mode control register pmccd is not possible. (2) control registers (a) port register cd (pcd) the pcd register is an 8-bit register that controls reading the pin levels and writing the output levels of port pins pcd2 to pcd5. this register can be read or written in 8-bit or 1-bit units. reset input causes an undefined register content. figure 20-79: port register cd (pcd) remark: n = 2 to 5 port alternate function remark port type port cd pcd2 ben0 byte enable signal output 1 pcd3 ben1 pcd4 ben2 pcd5 ben3 after reset: undefined r/w address: fffff00eh 76543210 pcd 0 0 pcd5 pcd4 pcd3 pcd2 0 0 pcdn input/output data control of pin pcdn 0 input mode: low level is input output mode: low level is output 1 input mode: high level is input output mode: high level is output
957 chapter 20 port functions user?s manual u16580ee2v0ud00 (b) port mode register cd (pmcd) the pmcd register is an 8-bit register that specif ies the input or output mode of port pins pcd2 to pcd5. this register can be read or written in 8-bit or 1-bit units. reset input sets this register to ffh. figure 20-80: port mode register cd (pmcd) remark: n = 2 to 5 after reset: ffh r/w address: fffff02eh 76543210 pmcd 1 1 pmcd5 pmcd4 pmcd3 pmcd2 1 1 pmcdn input/output mode control of pin pcdn (in port mode) 0 output mode 1 input mode
958 chapter 20 port functions user?s manual u16580ee2v0ud00 (c) port mode control register cd (pmccd) the pmccdl register is an 8-bit re gister that specifies the port mode or co ntrol mode (alternate function) of port pins pcd2 to pcd5. this register can be read or written in 8-bit or 1-bit units. reset input sets this register to 00h in single-chip mode 0, and to 3ch in rom-less mode and single-chip mode 1. figure 20-81: port mode cont rol register cd (pmccd) notes: 1. in single-chip mode 0: 00h in single-chip mode 1 and rom-less mode: 3ch 2. in the single-chip mode 1 or in the rom-less mode, this register can not be written. reading is possible and returns 3ch. after reset note 1 :00h/3fh r/w note 2 address: fffff04eh 76543210 pmccd 0 0 pmccd5 pmccd4 pmccd3 pmccd2 0 0 pmccd5 port/control mode specification of pin pcd5 0 i/o port mode 1 bus enable signal output mode (ben3 ) pmccd4 port/control mode specification of pin pcd4 0 i/o port mode 1 bus enable signal output mode (ben2 ) pmccd3 port/control mode specification of pin pcd3 0 i/o port mode 1 bus enable signal output mode (ben1 ) pmccd2 port/control mode specification of pin pcd2 0 i/o port mode 1 bus enable signal output mode (ben0 )
959 chapter 20 port functions user?s manual u16580ee2v0ud00 20.4 noise elimination a timing controller used to secure the noise elimination time is provided for the pins shown in table 20-23 below. input signals that change within the noise elimination time are not internally acknowledged. table 20-23: noise elimination (1/2) unit pin delay ty p e noise elimination time sampling clock reset reset analog delay several 10 ns (typ.) on-chip debug drst non-maskable interrupt p00/nmi digital delay 4 to 5 clocks f xx /16 (250 ns @ f xx =64 mhz) f xx /64 (1 s @ f xx =64 mhz) ? maskable interrupt ? forced output stop function (tmr) ? a/d converter (adc) p01/intp0/eso0 p02/intp1/eso1 analog delay 60 ns to 200 ns p03/intp2/adtrg0 p04/intp3/adtrg1 digital delay 4 to 5 clocks f xx /16 (250 ns @ f xx =64 mhz) f xx /64 (1 s @ f xx =64 mhz) ? maskable interrupt ? asynchronous serial interface (uart c) p30/rxdc0/intp4 p32/rxdc1/intp5 ? maskable interrupt ? clocked serial interface 3 (csi3) p83/scs300/intp6 p84/scs301/intp7 p85/scs302/intp8 p93/scs300/intp9 p94/scs301/intp10 p95/scs302/intp11 timer enc (tmnec10) p100/tclr0/ticc00/top81 p101/tcud0/ticc01 p102/tiud0/to1
960 chapter 20 port functions user?s manual u16580ee2v0ud00 caution: the noise elimination function is valid only in the control mode. timer p (tmp) p10/tip00/tevtp1/top00 p11/tip01/ttrgp1/top01 p12/tip10/ttrgp0/top10 p13/tip11/tevtp0/top11 p14/tip20/tevtp3/top20 p15/tip21/ttrgp3/top21 p16/tip30/ttrgp2/top30 p17/tip31/tevtp2/top31 p20/tip40/tevtp5/top40 p21/tip41/ttrgp5/top41 p22/tip50/ttrgp4/top50 p23/tip51/tevtp4/top51 p24/tip60/tevtp7/top60 p25/tip61/ttrgp7/top61 p26/tip70/ttrgp6/top70 p27/tip71/tevtp6/top71 digital delay 4 to 5 clocks f xx /16 (250 ns @ f xx = 64 mhz) f xx /64 (1 s @ f xx = 64 mhz) timer r (tmr) p60/tor10/ttrgr1 p61/tor11/tir10 p62/tor12/tir11 p63/tor13/tir12 p64/tor14/tir13 p67/tor17/tevtr1 timer t (tmt) p70/ti t00/tevtt1/tot00 p71/tit01/ttrgt1/tot01 p72/tecrt0/intp12 p73/tit10/ttrgt0/tot10 p74/tit11/t evtt0/tot11 p75/tecrt1/afo table 20-23: noise elimination (2/2) unit pin delay ty p e noise elimination time sampling clock
961 chapter 20 port functions user?s manual u16580ee2v0ud00 (1) noise elimination control register (nrc) the nrc register is an 8-bit register that specifies the sampling clock that is used to eliminate digital noise of input pins. this register can be read or written in 8-bit or 1-bit units. reset input sets this register to 00h. figure 20-82: noise elimination control register (nrc) (1/2) note: pin group 3: p10/tip00/tevtp1/top00, p11/tip01/ttrgp1/top01, p12/tip10/ttrgp0/top10, p13/tip11/tevtp0/top11 pin group 4: p14/tip20/tevtp3/top20, p15/tip21/ttrgp3/top21, p16/tip30/ttrgp2/top30, p17/tip31/tevtp2/top31 pin group 5: p20/tip40/tevtp5/top40, p21/tip41/ttrgp5/top41, p22/tip50/ttrgp4/top50, p23/tip51/tevtp4/top51 pin group 6: p24/tip60/tevtp7/top60, p25/tip61/ttrgp7/top61, p26/tip70/ttrgp6/top70, p27/tip71/tevtp6/top71 pin group 7: p60/tor10/ttrgr1, p61/tor11/tir10, p62/tor12/tir11, p63/tor13/tir12, p64/tor14/tir13, p67/tor17/tevtr1 after reset: 00h r/w address: fffffta0h 76543210 nrc nrc7 nrc6 nrc5 nrc4 nrc3 nrc2 nrc1 nrc0 nrc7 noise elimination clock setting for pin group 7 note 0f xx /16 (250 ns @ f xx = 64 mhz) 1f xx /64 (1 s @ f xx =64 mhz) nrc6 noise elimination clock setting for pin group 6 note 0f xx /16 (250 ns @ f xx = 64 mhz) 1f xx /64 (1 s @ f xx =64 mhz) nrc5 noise elimination clock setting for pin group 5 note 0f xx /16 (250 ns @ f xx = 64 mhz) 1f xx /64 (1 s @ f xx =64 mhz) nrc4 noise elimination clock setting for pin group 4 note 0f xx /16 (250 ns @ f xx = 64 mhz) 1f xx /64 (1 s @ f xx =64 mhz) nrc3 noise elimination clock setting for pin group 3 note 0f xx /16 (250 ns @ f xx = 64 mhz) 1f xx /64 (1 s @ f xx =64 mhz)
962 chapter 20 port functions user?s manual u16580ee2v0ud00 figure 20-82: noise elimination control register (nrc) (2/2) note: pin group 1: p03/intp2/adtrg0, p04/intp3/adtrg1, p30/rxdc0/intp4, p32/rxdc1/intp5, p83/scs300/intp6, p84/scs301/intp7, p85/scs302/intp8, p93/scs300/intp9, p94/scs301/intp10, p95/scs302/intp11 pin group 2: p100/tclr0/ticc00/top81, p101/tcud0/ticc01, p102/tiud0/to1, p70/tit00/tevtt1/tot00, p71/tit01/ ttrgt1/tot01, p72/tecrt0/intp12, p73/tit10/ttrgt0/tot10, p74/tit1 1/tevtt0/tot11, p75/tecrt1/afo cautions: 1. if the input pulse lasts for the duration of 4 to 5 clocks, it is undefined whether the pulse is detected as a valid edge or eliminated as noise. so that the pulse is actually detected as a valid edge, the same pulse level must be input for the duration of 5 clocks or more. 2. if noise is generated in synchronizat ion with the sampling clock, eliminate the noise by attaching a filter to the input pin. 3. noise is not eliminated if the corresponding pin is used as normal input port pin. nrc2 noise elimination clock setting for pin group 2 note 0f xx /16 (250 ns @ f xx =64 mhz) 1f xx /64 (1 s @ f xx =64 mhz) nrc1 noise elimination clock setting for pin group 1 note 0f xx /16 (250 ns @ f xx =64 mhz) 1f xx /64 (1 s @ f xx =64 mhz) nrc0 noise elimination clock setting for p00/nmi pin 0f xx /16 (250 ns @ f xx =64 mhz) 1f xx /64 (1 s @ f xx =64 mhz)
963 user?s manual u16580ee2v0ud00 chapter 21 reset function 21.1 features ? reset function by reset input ? forced reset function by dcu (refer to chapter 23 ?on-chip debug function (ocd)? on page 969 ) ? reset generator (rg) elimin ates noise from the reset pin. 21.2 configuration during a system reset, most pins (all except the dck, drst , dms, ddi, ddo, reset , x2, v dd10 to v dd15 , v ss10 to v ss15 , v dd30 to v dd37 , v ss30 to v ss37 , cv dd , cv ss , av dd , av ref0 , av ref1 , av ss0 and av ss1 pins) enter the high-impedance state. therefore, if an external device always requires a defined input level (e.g. external memory) a pull-up (or pull-down) resistor must be connected to each concerned output pin to prevent signal lines from floating. if no resistor is connected, the external device may be destroyed when these pins enter the high-impedance state.
964 chapter 21 reset function user?s manual u16580ee2v0ud00 21.3 operation when a low-level signal is input to the reset pin, a system reset is effected and each on-chip hardware is initialized. when the reset pin level changes from low to high, the os cillation stabilization ti me counter (ostc) is started after analog delay by the reset generator. at that time the ostc elapses, the pll circuit will be enabled and the internal pll stab ilization time counter (pstc) is started using the oscillator output clock (f x ). after 2 14 oscillator clocks (f x ) the pll output clock becomes the system clock (f xx ) and the internal system reset is released synchronously to the system clock. figure 21-1: reset timing remarks: 1. if no clock is supplied to v850e/ph2 (i.e. the oscillator does not work) the internal system reset will not be released independently from in put level of the external reset pin. 2. the on-chip debug function can force the ac tivation of the system reset independently from input level of the reset pin. reset system reset system clock (f ) xx ostc pstc x1 (f ) x pll analog delay cpu starts up oscillation stabilization time pll lock up time (2 / f ) 14 x
965 user?s manual u16580ee2v0ud00 chapter 22 internal ra m parity check function the v850e/ph2 microcontroller is provided with a pari ty check function for the internal ram (iram). 22.1 features ? maskable interrupt (intperr) on detection of parity error ? indication of internal ram address of detected parity error ? indication of erroneous byte within 32-bit word 22.2 operation each byte of data stored in the internal ram is checked by its parity bit. a maskable interrupt (intperr) is generated, if a parity mismatch is detected on iram read operation. in this case the address of the erroneous data is latched in the rampadd register and the erroneous byte(s) are indicated in the ramerr register. caution: ensure that all internal ram data is initialized on a word (32-bit) base by a write operation before first read access is made. it is important to initialize the whole memory word, even if only byte or half word is used. otherwise a parity fail may be indicated mistakenly.
966 chapter 22 internal ram parity check function user?s manual u16580ee2v0ud00 22.3 control registers (1) internal ram parity error status register (ramerr) the ramerr register is an 8-bit register that reflects the parity error flags of the four bytes of one word (32 bits) in the internal ram. the correspond ing error flag (bits rae0 to rae3) is set and a maskable interrupt (intperr) is generated, if a parity error is detected during read access. this register can be read or written in 8-bit or 1-bit units. reset input clears this register to 00h. figure 22-1: internal ram parity error status register (ramerr) after reset: 00h r/w address: fffff4c0h 76543210 ramerr 0 0 0 0 rae3 rae2 rae1 rae0 raen internal ram parity error flag 0 no parity error detected in internal ram. 1 parity error detected in internal ram for byte position n. remark: the raen bit can be both read and written, but it can only be cleared by writing 0 to it, and it cannot be set by writing 1 to it. n bit name function 0 rae0 parity error caused by bits 0 to 7 1 rae1 parity error caused by bits 8 to 15 2 rae2 parity error caused by bits 16 to 23 3 rae3 parity error caused by bits 24 to 31
967 chapter 22 internal ram parity check function user?s manual u16580ee2v0ud00 (2) internal ram parity error address register (rampadd) the rampad register is a 16-bit register that latches the internal ram address causing the first parity error after hardware reset was released or ramerr register was cleared. this register can be read or written in 16-bit units. reset input clears this register to 8000h. caution: do not read the ramp add register, when all internal ram parity error flags raen (n = 0 to 3) are cleared. if a parity error is detected and the rampadd register is read before the respective raen flag is set, the read value might be invalid. figure 22-2: internal ram parity er ror address regist er (rampadd) after reset: 8000h r/w address: fffff4c2h 1514131211109876543210 rampadd 1 rampa dd14 rampa dd13 rampa dd12 rampa dd11 rampa dd10 rampa dd9 rampa dd8 rampa dd7 rampa dd6 rampa dd5 rampa dd4 rampa dd3 rampa dd2 00 rampad14 to rampadd2 internal ram parity error address internal ram address of the 32-bit word causing the parity error. caution: bit 15 of the rampadd register is always 1. this does not reflect the correct address bit 15 of the intern al ram, which starts at location fff0000h. remark: bits 0 and 1 of the rampadd register are always 0, because the parity check function is aligned on 32-bit words.
968 user?s manual u16580ee2v0ud00 [memo]
969 user?s manual u16580ee2v0ud00 chapter 23 on-chip debug function (ocd) an on-chip debug unit is provided in the v850e/ph 2 microcontroller and realizes stand-alone on-chip debugging of the v850e/ph2 microcontroller by connecting a n-wire type emulator. caution: the debug function explained in this chapter is the function that can be realized by using the v850e/ph2 microcontroller, the nec electronics' ie-v850e1-cd-nw (n-wire type emulator). when using a third-party n-wire type emulator, refer to the manual for the debugger used. 23.1 function overview 23.1.1 on-chip debug unit type the on-chip debug unit incorporat ed in the v850e/ph2 microcontro ller is rcu1 (run control unit 1). the on-chip unit incorporated differs depending on the microcontroller, and also features different func- tions. 23.1.2 debug function for details of the debug function, refer to the corresponding debugger operation user's manual. (1) debug interface this interface establishes communication with the host machine by using the drst , dck, dms, ddi, and ddo signals, via a n-wire type emulator. the communication specifications of n-wire are used for this interface. it does not support a boundary scan function. (2) on-chip debug on-chip debugging can be performed by providing wiring and connectors for debugging on the target system. connect a n-wire type emulator to the emulator connector. (3) forced reset function the v850e/ph2 can be forcibly reset. (4) break reset function the cpu can be started in the debug mode immediately after resetting the cpu has been cleared. (5) forced break function execution of the user program can be forcibly stopped (however, the handler of the illegal instruction code exception (first address: 00000060h) cannot be used). (6) hardware break function two common instruction fetch/access breakpoints can be used. by using the instruction breakpoint, program execution can be suspended at an arbitrary address. by using the access breakpoint, program execution can be suspended by data-accessing an arbitrary address.
970 chapter 23 on-chip debug function (ocd) user?s manual u16580ee2v0ud00 (7) software break function in addition to the hardware break function, a software break function is available. up to eight software breakpoints can be set in the internal rom area. the number of software breakpoints that can be set in the internal ram area differs depending on the debugger used. (8) debug monitor function during debugging, a memory space for debugging that differs from the user memory space is used (background monitor format). the user program can be executed starting from any address. while execution of the user program is stopped, the user resources (such as memory and i/o) can be read or written, and the user program can be downloaded. (9) mask function reset , wait , nmi and all maskable interrupt request signals can be masked. (10) timer function the execution time of the user program can be measured.
971 chapter 23 on-chip debug function (ocd) user?s manual u16580ee2v0ud00 23.2 connection with n-wire type emulator to connect a n-wire type emulator, it is necessary to mount an emulator connector and circuit for connection on the target system. select either the kel connector, mictor connector (part number: 2-767004-2, distributor: tyco electronics amp k.k.), or 2.54 mm pitch 20-pin general-purpose connector as the emulator connector. connectors other than the kel connector may not be supported, depending on the emulator, so when using a connector, refer to the manual of the emulator used. 23.2.1 kel connector when the ie-v850e1-cd-nw is used, use of the following connector is recommended. part number ? 8830e-026-170s: straight type ? 8830e-026-170l: right-angle type figure 23-1: connecting n-wire type emulator (ie-v850e1-cd-nw (n-wire card)) host machine pcmcia card slot target system ie-v850e1-cd-nw connector for emulator 8830e-026-170s
972 chapter 23 on-chip debug function (ocd) user?s manual u16580ee2v0ud00 (1) pin configuration figure 23-2 shows the pin configuration of the em ulator connector (target system side), and table 23-1 shows the pin functions. figure 23-2: pin configuration of emulator connector (on target system side) caution: design the board based on the dimensio ns of the connector when actually mounting the connector on the board. board edge (top view) b12 a12 b2 a2 b13 a13 b1 a1
973 chapter 23 on-chip debug function (ocd) user?s manual u16580ee2v0ud00 (2) pin functions the following table shows the pin functions of the emulator connector (on the target system side). table 23-1: pin functions of connector for ie-v850e1-cd-nw (on target system side) cautions: 1. the processing of the pins not incorporated in the v850e/ph2 or unused pins depends on the emulator used. 2. the pattern on the target board must satisfy the following conditions. ? keep the pattern length to within 100 mm. ? shield the clock signal with gnd. remark: input/output is as viewed from the device side. pin no. pin name i/o pin function a1 (reserved 1) - (connect to gnd) a2 (reserved 2) - (connect to gnd) a3 (reserved 3) - (connect to gnd) a4 (reserved 4) - (connect to gnd) a5 (reserved 5) - (connect to gnd) a6 (reserved 6) - (connect to gnd) a7 ddi input data input for n-wire interface a8 dck input clock input for n-wire interface a9 dms input transfer mode select input for n-wire interface a10 ddo output data output for n-wire interface a11 drst input on-chip debug unit reset input a12 (reserved 7) - (leave open) a13 flmd0 input control signal for flash memory downloading b1 gnd - - b2 gnd - - b3 gnd - - b4 gnd - - b5 gnd - - b6 gnd - - b7 gnd - - b8 gnd - - b9 gnd - - b10 gnd - - b11 (reserved 8) - (connect to gnd) b12 (reserved 9) - (connect to gnd) b13 vdd - 3.3 v input (for monitoring power application to target)
974 chapter 23 on-chip debug function (ocd) user?s manual u16580ee2v0ud00 (3) recommended circuit example the following figure shows an example of the recommended circuit of the emulator connector (on the target system side). figure 23-3: example of recommended emulator connection of v850e/ph2 notes: 1. keep the pattern length to within 100 mm. 2. shield the dck signal with gnd. 3. for detecting power supply to the target board. connect to the n-wire interface voltage. 4. when drst pin is high level: on-chip debug mode when drst pin is low level or open: normal operation mode drst pin is connected to v ss3 via an internal pull-down resistor cautions: 1. the ddo signal is 3.3 v output, and the input level of the ddi, dck, dms, and drst signals is ttl level. 2. a 3.3 v interface may not be supported, so a level shifter may be required by some n-wire type emulators. refer to the manual of the emulator used. note that the ie-v850e1-cd-nw supports a 5 v interface. v850e/ph2 flmd0 (reserved 1) (reserved 2) (reserved 3) (reserved 4) (reserved 5) (reserved 6) ddi dck dms ddo drst (reserved 7) flmd0 v dd note 3 gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd (reserved 8) (reserved 9) note 1 note 1 note 1 note 1 note 1 (open) note 2 3.3 v 3.3 v a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 a12 a13 b13 b1 b2 b3 b4 b5 b6 b7 b8 b9 b10 b11 b12 ddi dck dms ddo drst note 4 kel connector 8830e-026-170s 22 4 4.7 k 50 k
975 chapter 23 on-chip debug function (ocd) user?s manual u16580ee2v0ud00 23.3 precautions <1> the flash memory of the device used in debugging is rewritten during debugging, so the number of flash memory rewrites cannot be guaranteed. therefore, do not use the device used in debugging for a mass production product. <2> if a reset (reset signal input from the target system or reset input by an internal reset source) occurs during run (program execution), the break function may malfunction. <3> even if reset is masked by using the mask function, the i/o buffers (port pins, etc.) are set to the reset state when the reset signal is input. <4> reset signal input during a break is masked.
976 user?s manual u16580ee2v0ud00 [memo]
977 user?s manual u16580ee2v0ud00 chapter 24 flash memory the v850e/ph2 and has a 512 kb on-chip flash memory configured as 128 blocks of 4 kb block size. 24.1 features ? 4-byte/1-clock access (when instruction is fetched) ? capacity: 512 kb ? block size: 128 blocks of 4 kb ? write voltage: erase/write with single voltage ? rewriting method - rewriting by communication with dedicated flash programmer via serial interface (on-board/off- board programming) - rewriting flash memory by user program (self-programming) ? 64 kb boot block cluster with write prohibit function supported (protection function) ? interrupts can be acknowledged during self programming.
978 chapter 24 flash memory user?s manual u16580ee2v0ud00 24.2 memory configuration the 512 kb internal flash memory area is divided into 128 blocks and can be programmed/erased in block units. all the blocks can also be erased at once. figure 24-1: flash memory mapping note: blocks 0 to 15 (64 kb): boot block cluster 400 0000h 3ff ffffh 100 0000h 0ff ffffh 010 0000h 00f ffffh 020 0000h 01f ffffh 000 0000h external memory area (14 mb) use prohibited external memory area (1 mb) internal flash memory area (512 kb) use prohibited note internal ram area (32 kb) on-chip peripheral i/o area (4 kb) block 14 (4 kb) block 15 (4 kb) block 16 (4 kb) block 13 (4 kb) 0000 d000h 0000 cfffh 0000 e000h 0000 dfffh 0000 f000h 0000 efffh 0001 0000h 0000 ffffh 0001 1000h 0001 0fffh block 122 (4 kb) block 121 (4 kb) block 123 (4 kb) block 124 (4 kb) block 125 (4 kb) block 127 (4 kb) block 126 (4 kb) 0007 f000h 0007 efffh 0007 e000h 0007 dfffh 0007 d000h 0007 cfffh 0007 c000h 0007 bfffh 0007 b000h 0007 afffh 0007 a000h 0007 9fffh 0007 9000h 0007 8fffh 0007 ffffh block 0 (4 kb) block 1 (4 kb) block 2 (4 kb) block 3 (4 kb) 0000 2000h 0000 1fffh 0000 3000h 0000 2fffh 0000 4000h 0000 3fffh 0000 1000h 0000 0fffh 0000 0000h 3ff 0000h 3fe ffffh 3ff 8000h 3ff 7fffh 3ff f000h 3ff efffh on-chip peripheral i/o area mirror use prohibited use prohibited (28 kb) note 3 internal ram area mirror fff ffffh fff 8000h fff 7fffh fff efffh fff f000h ffe ffffh fff 0000h
979 chapter 24 flash memory user?s manual u16580ee2v0ud00 24.3 functional outline the internal flash memory of the v850e/ph2 can be rewritten by using the rewrite function of the dedi- cated flash programmer, regardless of whether the v850e/ph2 has already been mounted on the tar- get system or not (off-board/on-board programming). in addition, different functions are implemented to protect unwanted flash access via the programmer interface and to protect the boot area from any unwanted modification the rewrite function using the user program (self programming) is ideal for an application where it is assumed that the program is changed or extended during or after production/shipment of the target system. interrupt servicing is supported during self programming, so that the flash memory can be rewritten under various conditions, such as while communicating with an external device. remark: the fa series is a product of naito densei machida mfg. co., ltd. table 24-1: rewrite method rewrite method functional outline operation mode off-board programming flash memory can be rewritten before the device is mounted on the target syst em, by using a dedicated flash programmer and a dedicated program adapter board (e.g. fa series). flash memory programming mode on-board programming flash memory can be rewritten after the device is mounted on the target syst em, by using a dedicated flash programmer. self-programming flash memory can be rewritten by executing a user program that has been written to the flash memory in advance by means of off-board/on-board programming. (during self-programming, instructions cannot be fetched from or data access cannot be made to the internal flash memory area. therefore, the rewrite program must be transferred to the internal ram or external memory in advance). parts of the self-programming program normal operation mode
980 chapter 24 flash memory user?s manual u16580ee2v0ud00 the following table 24-3 lists the protection functions. after shipment no protection feature is set on the device. furthermore, after chip erase by a dedicated programmer (pg-fp4) the protection is reset. each protection function can be used in combination with the others at the same time. table 24-2: basic functions function functional outline support by on-board/off-board programming self programming block erasure the contents of specified memory blocks are erased. yes yes chip erasure the contents of the entire memory area are erased all at once. yes no write writing to specified addresses, and a verify check to see if write level is secured are performed. yes yes verify/check sum data read from the flash memory is compared with data transferred from the flash programmer. yes no (can be read by user program) blank check the erasure status of the entire memory is checked. yes yes read the content of specified addresses can be read. yes yes protection setting setting of protection flags to prohibit programming interface commands (write, block erase, chip erase and read) and to prohibit boot block cluster modification via self-programming yes yes
981 chapter 24 flash memory user?s manual u16580ee2v0ud00 remark: : operation prohibited : operation executable table 24-3: protection functions function functional outline operation on-board/off-board programming self-programming block erase command prohibit execution of a block erase command on all blocks is prohibited. setting of prohibition can be initialized by execution of a chip erase command. block erase command: chip erase command: program command: can always be read or rewritten regardless of protection function setting chip erase command prohibit execution of block erase and chip erase commands on all the blocks is prohibited. once prohibition is set, setting of prohibition cannot be initialized because the chip erase command cannot be executed. block erase command: chip erase command: program command: program command prohibit write and block erase commands on all the blocks are prohibited. setting of prohibition can be initialized by execution of the chip erase command. block erase command: chip erase command: program command: read command prohibit read of memory content is prohibited. read command:
982 chapter 24 flash memory user?s manual u16580ee2v0ud00 24.4 rewriting by dedicated flash programmer the flash memory can be rewritten by using a dedicated flash programmer after the v850e/ph2 is mounted on the target system (on-board programming). the flash memory can also be rewritten before the device is mounted on the target system (off-board programming) by using a dedicated program adapter (fa series). 24.4.1 programming environment the following shows the environment required for writing programs to the flash memory of the v850e/ph2: figure 24-2: environment required for writing programs to flash memory a host machine is required for contro lling the dedicated flash programmer. uartc0 or csib0 is used for the interface between the dedicated flash programmer and the v850e/ph2 to perform writing, erasing, etc. a dedicated program adapter (fa series) is required for off- board writing. remark: the fa series is a product of naito densei machida mfg. co., ltd. host machine rs-232c dedicated flash programmer v850e/ph2 flmd1 v,v dd1 dd3 v,v ss1 ss3 reset uarta0/csib0 pg-fp4 ( f l a s h p r o 4 ) cxxxxxx bxxxxx axxxx xxx y yy xx x x x x x xx x x xx x x xx xx yyyy status flmd0 usb
983 chapter 24 flash memory user?s manual u16580ee2v0ud00 24.4.2 communication mode communication between the dedicated flash programmer and the v850e/ph2 is performed by serial communication using the uartc0 or csib0 interfaces of the v850e/ph2. (1) uarta0 transfer rate: 9,600 to 153,600 bps figure 24-3: communication with de dicated flash programmer (uartc0) (2) csib0 serial clock: 2.4 khz to 2.5 mhz (msb first) figure 24-4: communication with de dicated flash programmer (csib0) dedicated flash programmer pg-fp4 ( f l a s h p r o 4 ) cxxxxxx bxxxxx axxxx xxx yyy x x x x x x x x x x x x x x x xxxx yyyy status v dd1 v dd3 v ss1 ,v ss3 reset txdc0 rxdc0 flmd1 flmd1 v dd2 v dd gnd reset rxd txd flmd0 flmd0 v850e/ph2 dedicated flash programmer pg-fp4 (f l a s h p r o 4 ) cxxxxxx bxxxxx axxxx xxx yyy x x x x x x x x x x x x x x x xxxx yyyy status v850e/ph2 v dd1 v dd3 v,v ss1 ss3 reset sob0 sib0 sckb0 flmd1 flmd1 v dd2 v dd gnd reset si so sck flmd0 flmd0
984 chapter 24 flash memory user?s manual u16580ee2v0ud00 (3) csib0 + hs serial clock: 2.4 khz to 2.5 mhz (msb first) figure 24-5: communication with dedicated flash programmer (csib0 + hs) the dedicated flash programmer outputs the transfer clock, and the v850e/ph2 operates as a slave. when the pg-fp4 is used as the dedicated flash programmer, it generates the following signals to the v850e/ph2. for details, refer to the pg-fp4 user?s manual (u15260e). dedicated flash programmer pg-fp4 ( f l a s h p r o 4 ) cxxxxxx bxxxxx axxxx xxx yyy x x x x x x x x x x x x x x x xxxx yyyy status v dd1 v dd3 v,v ss1 ss3 reset sob0 sib0 sckb0 pcm0 flmd1 flmd1 v dd2 v dd gnd reset si so hs sck flmd0 flmd0 v850e/ph2
985 chapter 24 flash memory user?s manual u16580ee2v0ud00 notes: 1. connect to gnd via pull-down resistor. 2. connect these pins to supply power from the pg-fp4. when power is supplied externally to the target board, the voltage is monitored by pg-fp4. 3. connect these pins to supply power from the pg-fp4, or supply power externally to the target board. 4. clock supply is provided by an oscillator on th e target board. clock supply from pg-fp4 is not supported for v850e/ph2. remark: : must be connected. : do not need to be connected. table 24-4: signal connections of dedicated flash programmer (pg-fp4) pg-fp4 v850e/ph2 proce ssing for connection signal name i/o pin function pin name uartc0 csib0 csib0 + hs flmd0 output write enable/disable flmd0 flmd1 output write enable/disable flmd1 note 1 note 1 note 1 vdd ? v dd voltage generation/ voltage monitor vdd3x note 2 note 2 note 2 vdd2 ? v dd2 voltage generation vdd1x note 3 note 2 note 2 gnd ? ground vss1x, vss3x clk output clock output x1, x2 note 4 note 3 note 3 reset output reset signal reset si/rxd input receive signal sib0/rxdc0 so/txd output transmit signal sob0/txdc0 sck output transfer clock sckb0 hs input handshake signal pcm0
986 chapter 24 flash memory user?s manual u16580ee2v0ud00 24.4.3 flash memory control the following shows the procedure for manipulating the flash memory. figure 24-6: procedure for manipulating flash memory start select communication system manipulate flash memory end? ye s supplies flmd0 pulse no end switch to flash memory programming mode
987 chapter 24 flash memory user?s manual u16580ee2v0ud00 24.4.4 selection of communication mode in the v850e/ph2, the communication mode is select ed by inputting pulses (11 pulses max.) to the flmd0 pin after switching to the flash memory programming mode. the flmd0 pulse is generated by the dedicated flash programmer. the following shows the relationship between the number of pulses and the communication mode. figure 24-7: selection of communication mode note: the number of clocks is as follows depending on the communication mode. caution: when uartc0 is selected, the receive clock is calculated based on the reset command sent from the dedicated flash programmer after receiving the flmd0 pulse. number of flmd0 pulses communication mode remarks 0 uartc0 communication rate: 9,600 bps (after reset), lsb first 8 csib0 v850e/ph2 performs slave operation, msb first 11 csib0 + hs others rfu setting prohibited v dd1 ,v dd3 v dd1x ,v dd3x reset (input) flmd1 (input) flmd0 (input) rxda0 (input) txda0 (output) v ss1 ,v ss3 v dd3 v ss3 v dd3 v ss3 v dd3 v ss3 v dd3 v ss3 v dd3 v ss3 (note) power on reset released oscillation stabilized communication mode selected flash control command communication (erasure, write, etc.)
988 chapter 24 flash memory user?s manual u16580ee2v0ud00 24.4.5 communication commands the v850e/ph2 communicates with the dedicated fl ash programmer by means of commands. the sig- nals sent from the dedicated flash programmer to the v850e/ph2 are called ?commands?. the response signals sent from the v850e/ph2 to t he dedicated flash programmer are called ?response commands?. figure 24-8: communication commands the following shows the commands for flash memory control in the v850e/ph2. all of these commands are issued from the dedicated flash programmer, and the v850e/ph2 performs the processing corre- sponding to the commands. remark: : operation not supported : operation supported table 24-5: communication commands classification command name support function uartc0 csi0 csi0 + hs blank check block blank check command checks if the contents of the memory in the specified block have been correctly erased. erase chip erase command erases the conten ts of the entire memory. block erase command erases the contents of the memory of the specified block. write write command writes the specified address range, and executes a contents verify check. verify verify command compares the contents of memory in the specified address range with data transferred from the flash programmer. checksum command reads the checksum in the specified address range. read read command reads the specified address range. system setting, control silicon signature command reads silicon signature information. protection setting command disables the chip erase command, enables the block erase command, and disables the write command. dedicated flash programmer v850e/ph2 command response command pg-fp4 (f l a sh p r o 4 ) cxxxxxx bxxxxx axxxx xxx yyy x x x x x x x x x x x x x x x xxxx yyyy statve
989 chapter 24 flash memory user?s manual u16580ee2v0ud00 24.4.6 pin connection when performing on-board writing, mount a connector on the target system to connect to the dedicated flash programmer. also, incorporate a function on-board to switch from the normal operation mode to the flash memory programming mode. in the flash memory programming mode, all the pins not used for flash memory programming become the same status as that immediately after reset. therefore, pin handling is required when the external device does not acknowledge the status immediately after a reset. (1) flmd0 pin in the normal operation mode, input a voltage of v ss3 level to the flmd0 pin. in the flash memory programming mode, supply a write voltage of v dd3 level to the flmd0 pin. because the flmd0 pin serves as a write protection pin in the self programming mode, a voltage of v dd3 level must be supplied to the flmd0 pin via port control, etc., before writing to the flash memory. for details, refer to the self-programming application note (u16929e). figure 24-9: flmd0 pin connection example v850e/ph2 flmd0 dedicated flash programmer connection pin pull-down resistor (r ) flmd0
990 chapter 24 flash memory user?s manual u16580ee2v0ud00 (2) flmd1 pin when 0 v is input to the flmd0 pin, the flmd1 pin does not function. when v dd3 is supplied to the flmd0 pin, the flash memory programming mode is entered, so 0 v must be input to the flmd1 pin. the following shows an example of the connection of the flmd1 pin. figure 24-10: flmd1 pin connection example caution: if the v dd3 signal is input to the flmd1 pin from another device during on-board writing and immediately after reset, isolate this signal. table 24-6: relationship between flmd0 and flmd1 pins and operation mode when reset is released flmd0 flmd1 operation mode 0 don?t care normal operation mode v dd3 0 flash memory programming mode v dd3 v dd3 setting prohibited flmd1 pull-down resistor (r ) flmd1 other device v850e/ph2
991 chapter 24 flash memory user?s manual u16580ee2v0ud00 (3) serial interface pin the following shows the pins used by each serial interface. when connecting a dedicated flash programmer to a serial interface pin that is connected to another device on-board, care should be taken to avoid conflict of signals and malfunction of the other device. (a) conflict of signals when the dedicated flash programmer (output) is connected to a serial interface pin (input) that is connected to another device (output), a conflict of signals occurs. to avoid the conflict of signals, isolate the connection to the other device or set the other device to the output high-impedance status. figure 24-11: conflict of signals (serial interface input pin) table 24-7: pins used by serial interfaces serial interface used pins uartc0 txdc0, rxdc0 csib0 sob0, sib0, sckb0 csib0 + hs sob0, sib0, sckb0 , pcm0 input pin conflict of signals dedicated flash programmer connection pins other device output pin in the flash memory programming mode, the signal that the dedicated flash programmer sends out conflicts with signals another device outputs. therefore, isolate the signals on the other device side. v850e/ph2
992 chapter 24 flash memory user?s manual u16580ee2v0ud00 (b) malfunction of other device when the dedicated flash programmer (output or input) is connected to a serial interface pin (input or output) that is connected to another device (input), the signal is output to the other device, causing the device to malfunction. to avoid this, isolate the connection to the other device. figure 24-12: malfunction of other device pin dedicated flash programmer connection pin other device input pin in the flash memory programming mode, if the signal the v850e/ph2 outputs affects the other device, isolate the signal on the other device side. pin dedicated flash programmer connection pin other device input pin in the flash memory programming mode, if the signal the dedicated flash programmer outputs affects the other device, isolate the signal on the other device side. v850e/ph2 v850e/ph2
993 chapter 24 flash memory user?s manual u16580ee2v0ud00 (4) reset pin when the reset signals of the dedicated flash programme r are connecte d to the reset pin that is connected to the reset signal generator on-board, a conflict of signals occurs. to avoid the conflict of signals, isolate the connection to the reset signal generator. when a reset signal is input from the user system in the flash memory programming mode, the programming operation will not be performed correctl y. therefore, do not input si gnals other than the reset signals from the dedicated flash programmer. figure 24-13: conflict of signals (reset pin) (5) port pins (including nmi) when the system shifts to the flash memory programming mode, all the pins that are not used for flash memory programming are in the same status as that immediately after reset. if the external device connected to each port does not recognize the status of the port immediately after reset, pins require appropriate processing, such as connecting to v dd3 via a resistor or connecting to v ss3 via a resistor. (6) other signal pins connect x1 and x2 in the same status as that in the normal operation mode. during flash memory programming, input a low level to the drst pin or leave it open. do not input a high level. (7) power supply supply the same power (v dd1 , v ss1 , v dd3 , v ss3 , cv dd , cv ss , av dd , av ss , av ref0 , av ref1 ) as in normal operation mode. v850e/ph2 reset dedicated flash programmer connection pin reset signal generator conflict of signals output pin in the flash memory programming mode, the signal the reset signal generator outputs conflicts with the signal the dedicated flash programmer outputs. therefore, isolate the signals on the reset signal generator side.
994 chapter 24 flash memory user?s manual u16580ee2v0ud00 24.5 rewriting by self programming 24.5.1 overview the v850e/ph2 supports a flash macro service that allows the user program to rewrite the internal flash memory by itself. by using this interface and a self-programming library that is used to rewrite the flash memory with a user application program, the flash memory can be rewritten by a user application transferred in advance to the internal ram or external memory. consequently, the user program can be upgraded and constant data can be rewritten in the field. figure 24-14: concept of self programming for further details, refer to the self-programming application note (u16929e). application program self programming library flash macro service flash memory flash function execution flash information erase, write
995 chapter 24 flash memory user?s manual u16580ee2v0ud00 24.5.2 features (1) secure self-programming (boot swap function) the v850e/ph2 supports a boot swap function that can exchange the physical memory of blocks 0 to 15 with the physical memory of blocks 16 to 31. by writing the start program to be rewritten to blocks 16 to 31 in advance and then swapping the physical memory, the entire area can be safely rewritten even if a power failure occurs during rewriting because the correct user program always exists in blocks 0 to 15. figure 24-15: rewriting entire memory area (boot swap) (2) interrupt support instructions cannot be fetched from the flash memory during self programming. conventionally, therefore, a user handler written to the flash memory could not be used even if an interrupt occurred. with the v850e/ph2, a user handler can be registered to an entry ram area by using a library function, so that interrupt servicing can be performed by internal ram or external memory execution. rewriting blocks 8 to 15 boot swap block 32 block 127 block 31 block 0 block 15 block 16 block 32 block 127 block 31 block 0 block 15 block 16 block 32 block 127 block 31 block 0 block 15 block 16
996 user?s manual u16580ee2v0ud00 [memo]
997 user?s manual u16580ee2v0ud00 chapter 25 electric al specifications 25.1 absolute maximum ratings table 25-1: absolute maximum ratings (t a = 25c, v ss1 note 1 = 0 v) notes: 1. v ss1 applied to v ss10 to v ss15 pins. 2. v dd1 applied to v dd10 to v dd15 pins. 3. v ss3 applied to v ss30 to v ss37 pins. 4. v dd3 applied to v dd30 to v dd37 pins. 5. av ss applied to av ss0 to av ss1 pins. cautions: 1. do not directly connect output (or i/o) pins of ic products to each other, or to v dd , v ss , and gnd. 2. product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. that is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. the ratings and conditions shown below for dc characteristics and ac characteristics are within the range for normal operation and quality assurance. parameter symbol conditions ratings unit supply voltage v dd1 note 2 -0.5 to +2.0 v v dd3 note 4 -0.5 to +4.6 v cv dd -0.5 to +2.0 v av dd v dd3 - 0.5 v < av dd < v dd3 + 0.5 v -0.5 to +4.6 v v ss1 note 1 -0.5 to +0.5 v v ss3 note 3 -0.5 to +0.5 v cv ss -0.5 to +0.5 v av ss note 5 -0.5 to +0.5 v input voltage v i1 all pins except x1 pin, ani00 to ani19 pins v i1 < v dd3 + 0.3 v -0.5 to +4.6 v v i2 x1 pin v i2 < cv dd + 0.5 v -0.5 to +2.0 v analog input voltage v ian ani00 to ani19 pins av dd = 3.0 v to 3.6 v -0.3 to av dd + 0.3 v analog reference input voltage av ref0, av ref1 -0.3 to av dd + 0.3 v output current, low i ol per pin 4.0 ma total of all pins 100 ma output current, high i oh per pin -4.0 ma total of all pins -100 ma operating temperature t a pd70f3187 -40 to +85 c pd70f3187(a1) -40 to +110 c pd70f3187(a2) -40 to +125 c storage temperature t stg -65 to +150 c
998 chapter 25 electrical specifications user?s manual u16580ee2v0ud00 25.2 general characteristics unless specified otherwise, the follo wing conditions are assumed for a ll characteristics in this chapter. v dd3x = av dd = 3.0 v to 3.6 v v dd1x = cv dd = 1.35 v to 1.65 v v ss1x = cv ss = v ss3x = av ssx = 0 v pd70f3187: t a = -40 c to +85 c pd70f3187(a1): t a = -40 c to +110 c pd70f3187(a2): t a = -40 c to +125 c 25.2.1 capacitance table 25-2: capacitance 25.2.2 operating conditions table 25-3: operating conditions (t a = 25c, v dd1x = cv dd = v dd3x = av dd = v ss1x = cv ss = v ss3x = av ssx = 0 v) parameter symbol conditions min. typ. max. unit input capacitance c i f c = 1 mhz un-measured pins returned to 0 v. 15 pf output capacitance c o 15 pf i/o capacitance c io 15 pf parameter symbol conditions min. typ. max. unit internal system clock frequency f xx f osc = 16 mhz 64 mhz
999 chapter 25 electrical specifications user?s manual u16580ee2v0ud00 25.2.3 oscillator characteristics figure 25-1: oscillator recommendations remark: values of capacitors c1?, c2? and r? depend on used crystal or resonator and must be specified in cooperation with the manufacturer. cautions: 1. external clock input is prohibited. 2. wire as follows in the area enclosed by the broken lines in the above figure to avoid an adverse effect from wiring capacitance. ? keep the wiring length as short as possible. ? do not cross the wiring with the other signal lines. ? do not route the wiring near a signal line through which a high fluctuating current flows. ? always make the ground point of the oscillator capacitor the same potential as cv ss . ? do not ground the capacitor to a ground pattern through which a high current flows. ? do not fetch signals from the oscillator. table 25-4: oscillator characteristics parameter symbol conditions min. typ. max. unit oscillation frequency f osc 16 mhz oscillation stabilization time t ost f osc = 16 mhz 4.096 ms x2 x1 c2' c1' r' qu
1000 chapter 25 electrical specifications user?s manual u16580ee2v0ud00 25.3 dc characteristics unless specified otherwise, the follo wing conditions are assumed for a ll characteristics in this chapter. v dd3x = av dd = 3.0 v to 3.6 v v dd1x = cv dd = 1.35 v to 1.65 v v ss1x = cv ss = v ss3x = av ssx = 0 v pd70f3187: t a = -40 c to +85 c pd70f3187(a1): t a = -40 c to +110 c pd70f3187(a2): t a = -40 c to +125 c notes: 1. pins other than analog input pins ani00 to ani19 2. analog input pins ani00 to ani19 3. no external loads considered (c l = 0pf). external loads cause additional pin currents. pin current for each pin can be calculated according to following formula: i[a] = 3.63 c l [pf] f [mhz] where c l is external load capacitance and f is the average pin toggle frequency. load dependent pin currents must be summed up and added to i dd3 . table 25-5: dc characteristics parameter symbol conditions min. typ. max. unit input voltage, high v ih1 pa l 0 t o pa l 1 5 , pa h 0 t o pa h 5 , p d l 0 to pdl15, pdh0 to pdh15, pcs0, pcs1, pcs3, pcs4, pcd2 to pcd5, pct4, pct5, pcm0, pcm1, pcm6, pcm7, dck, dms, ddi, ddo 0.7 v dd3 v dd3 + 0.3 v v ih3 p00 to p04, p10 to p17, p20 to p27, p30 to p37, p40 to p45, p50 to p57, p60 to p67, p70 to p75, p80 to p86, p90 to p96, p100 to p102, reset , mode0 to mode2, drst input voltage, low v il1 pa l 0 t o pa l 1 5 , pa h 0 t o pa h 5 , p d l 0 to pdl15, pdh0 to pdh15, pcs0, pcs1, pcs3, pcs4, pcd2 to pcd5, pct4, pct5, pcm0, pcm1, pcm6, pcm7, dck, dms, ddi, ddo -0.5 0.3 v dd3 v v il3 p00 to p04, p10 to p17, p20 to p27, p30 to p37, p40 to p45, p50 to p57, p60 to p67, p70 to p75, p80 to p86, p90 to p96, p100 to p102, reset , mode0 to mode2, drst output voltage, high v oh1 i oh = -2.5 ma v dd3 - 1.0 v i oh = -100 a v dd3 - 0.4 v output voltage, low v ol1 i ol = 2.5 ma 0.8 v i ol = 100 a 0.4 v input leakage current, high i lih v ih = v dd3 , note 1 10 a v ih = av dd , note 2 3a input leakage current, low i lil v il = 0 v, note 1 -10 a v il = 0 v, note 2 -3 a power supply current i dd1 v dd1 + cv dd 200 ma i dd3 v dd3 , note 3 50 ma
1001 chapter 25 electrical specifications user?s manual u16580ee2v0ud00 25.4 ac characteristics unless specified otherwise, the follo wing conditions are assumed for all characteristics in this chapter. v dd3x = av dd = 3.0 v to 3.6 v v dd1x = cv dd = 1.35 v to 1.65 v v ss1x = cv ss = v ss3x = av ssx = 0 v pd70f3187: t a = -40 c to +85 c pd70f3187(a1): t a = -40 c to +110 c pd70f3187(a2): t a = -40 c to +125 c output pin load capacitance: c l = 35 pf figure 25-2: ac test input/output waveform figure 25-3: ac test load condition test points 0.8 v dd5x 0.2 v dd5x v dd5x 0 v test points 0.8 v dd3x 0.2 v dd3x v dd3x 0 v dut load on test c l = 50 pf
1002 chapter 25 electrical specifications user?s manual u16580ee2v0ud00 25.4.1 external asynchronous memory access read timing table 25-6: external asynchronous memory access read timing remarks: 1. t: 2/f xx 2. i: number of idle states specified by bcc register 3. w as : number of waits specified by asc register 4. w d : number of waits specified by dwc1, dwc2 register; w d 1 5. w: number of waits due to external wait signal (wait) 6. n = 0, 1, 3, 4 parameter symbol min. max. unit data input set up time (vs. address) <10> t said (2 + w as + w d + w) t - 30 ns data input set up time (vs. rd )<11>t srdid (1.5 + w d + w) t - 30 ns rd low level width <12> t wrdl (1.5 + w d + w) t - 15 ns rd high level width <13> t wrdh (0.5 + w as + i) t - 15 ns address, csn rd delay time <14> t dard (0.5 + w as ) t - 20 ns rd address delay time <15> t drda it - 2 ns data input hold time (vs. rd ) <16> t hrdid 0ns rd data output delay time <17> t drdod (1 + i) t - 15 ns wait set up time (vs. address) < 31 > t saw (1 + w as ) t- 30 ns wait high level width <32> t wwh t - 2 ns
1003 chapter 25 electrical specifications user?s manual u16580ee2v0ud00 figure 25-4: external asynchronous memory access read timing csn a0 to a21 rd <16> <13> <12> <15> <17> <10> <11> (output) (output) (in/out) (output) <14> wait (input) <31> <32> ben0 to ben3 wr d0 to d31
1004 chapter 25 electrical specifications user?s manual u16580ee2v0ud00 25.4.2 external asynchronous memory access write timing table 25-7: external asynchronous memory access write timing remarks: 1. t: 2/f xx 2. i: number of idle states specified by bcc register 3. w as : number of waits specified by asc register 4. w d : number of waits specified by dwc1, dwc2 register; w d 1 5. w: number of waits due to external wait signal (wait) 6. n = 0, 1, 3, 4 parameter symbol min. max. unit address, csn wr delay time <20> t dawr (1 + w as )t - 20 ns address set up (vs. wr ) <21> t sawr (1.5 + w as + w d + w) t - 10 ns wr address delay time <22> t dwra (0.5 + i) t - 5 ns wr high level width <23> t wwrh (1.5 + i + w as ) t - 15 ns wr low level width <24> t wwrl (0.5 + w + w d ) t - 12 ns data output set up time (vs. wr ) <25> t sodwr (0.5 + w as + w d + w) t - 15 ns data output hold time (vs. wr ) <26> t hwrod (0.5 + i) t - 15 ns wait set up time (vs. address) <31> t saw (1 + w as )t - 30 ns wait high level width <32> t wwh t - 2 ns
1005 chapter 25 electrical specifications user?s manual u16580ee2v0ud00 figure 25-5: external asynchronous memory access write timing <23> <21> <22> <20> <24> <25> <26> (in/output) read write (output) (output) (output) (in/output) write write rd csn wait (input) <31> <32> a0 to a21 ben0 to ben3 wr d0 to d31 d0 to d31
1006 chapter 25 electrical specifications user?s manual u16580ee2v0ud00 25.4.3 reset timing (power up/down sequence) table 25-8: reset timing figure 25-6: reset timing caution: ensure that a valid reset signal (low active) is applied to the reset pin at any time if the voltage power of v dd1x is below its operating condition range. parameter symbol min. max. unit reset high-level width t wrsh 500 ns reset low-level width t wrsl 500 ns v dd3x ? v dd1x power up delay t dvr 0ns v dd3x ? v dd1x power down delay t dvf 0ns reset hold time t dvrr 1s reset setup time t dvrf 0ns t wrsh t wrsl reset dd3 reset t dvf t dvrf t dvrr v dd1 v dd3 v dd1 v t dvr
1007 chapter 25 electrical specifications user?s manual u16580ee2v0ud00 25.4.4 interrupt timing table 25-9: interrupt timing figure 25-7: interrupt timing parameter symbol condition min. max. unit nmi high-level width t wnih nrc0 bit = 0 96 t + 10 ns nrc0 bit = 1 384 t + 10 ns nmi low-level width t wnil nrc0 bit = 0 96 t + 10 ns nrc0 bit = 1 384 t + 10 ns intpx high-level width t with nrc1 bit = 0 96 t + 10 ns nrc1 bit = 1 384 t + 10 ns intpx low-level width t witl nrc1 bit = 0 96 t + 10 ns nrc1 bit = 1 384 t + 10 ns intp0, intp1 high-level width t wtih 500 ns intp0, intp1 low-level width t wtil 500 ns t wnih t wnil nmi t with t witl intpx, intpi
1008 chapter 25 electrical specifications user?s manual u16580ee2v0ud00 25.5 peripheral characteristics unless specified otherwise, the follo wing conditions are assumed for a ll characteristics in this chapter. v dd3x = av dd = 3.0 v to 3.6 v v dd1x = cv dd = 1.35 v to 1.65 v v ss1x = cv ss = v ss3x = av ssx = 0 v pd70f3187: t a = -40 c to +85 c pd70f3187(a1): t a = -40 c to +110 c pd70f3187(a2): t a = -40 c to +125 c 25.5.1 timer characteristics table 25-10: timer p characteristics figure 25-8: timer p characteristics remark: m = 0 to 7 n = 0 to 1 x = 3 to 6 (depending on the pin group the tipmn belongs to, refer to 20.4 ?noise elimina- tion? on page 959). parameter symbol condition min. max. unit tipmn input high-level width t wtiph nrcx bit = 0 96 t + 10 ns nrcx bit = 1 384 t + 10 ns tipmn input low-level width t wtipl nrcx bit = 0 96 t + 10 ns nrcx bit = 1 384 t + 10 ns t wtiph t wtipl tipmn
1009 chapter 25 electrical specifications user?s manual u16580ee2v0ud00 table 25-11: timer r characteristics figure 25-9: timer r characteristics remark: m = 0, 1 n = 0 to 3 x = 0 to 7, y = 0 to 7, x y parameter symbol condition min. max. unit tir1n input high-level width t wtirh nrc7 bit = 0 96 t + 10 ns nrc7 bit = 1 384 t + 10 ns tir1n input low-level width t wtirl nrc7 bit = 0 96 t + 10 ns nrc7 bit = 1 384 t + 10 ns tormx to tormy output delay t dtortor 15 ns t wtirh t wtirl tirmn tormx tormy t dtortor t dtortor
1010 chapter 25 electrical specifications user?s manual u16580ee2v0ud00 table 25-12: timer t characteristics figure 25-10: timer t characteristics remark: m = 0, 1 n = 0, 1 parameter symbol condition min. max. unit titmn input high-level width t wtith nrc2 bit = 0 96 t + 10 ns nrc2 bit = 1 384 t + 10 ns titmn input low-level width t wtitl nrc2 bit = 0 96 t + 10 ns nrc2 bit = 1 384 t + 10 ns t wtiph t wtipl tipmn
1011 chapter 25 electrical specifications user?s manual u16580ee2v0ud00 25.5.2 serial interface characteristics (1) clocked serial interface b (csib) characteristics table 25-13: csib characteristics (master mode) table 25-14: csib characteristics (slave mode) remark: n = 0, 1 cbnsck2 to cbnsck0 111b parameter symbol min. max. unit sckbn output clock cycle time t cyskm 125 ns sckbn output high level width t wskhm 0.5 t cyskm - 10 ns sckbn output low level width t wsklm 0.5 t cyskm - 10 ns sibn input setup time (vs. sckbn )t ssiskm 20 ns sibn input hold time (vs. sckbn )t hsksim 10 ns sobn output delay (vs. sckbn ) t dsksom 10 ns sobn output hold time (vs. sckbn )t hsksom 0.5 t cyskm - 10 ns cbnsck2 to cbnsck0 = 111b parameter symbol min. max. unit sckbn input clock cycle time t cysks 125 ns sckbn input high level width t wskhs 0.5 t cysks - 10 ns sckbn input low level width t wskls 0.5 t cysks - 10 ns sibn input setup time (vs. sckbn )t ssisks 5ns sibn input hold time (vs. sckbn )t hsksis 10 ns sobn output delay (vs. sckbn ) t dsksos 25 ns sobn output hold time (vs. sckbn )t hsksos 0.5 t cysks - 10 ns
1012 chapter 25 electrical specifications user?s manual u16580ee2v0ud00 figure 25-11: csib timing in master mode (ckp, dap bits = 00b or 11b) figure 25-12: csib timing in master mode (ckp, dap bits = 01b or 10b) t cyskm t wsklm t dsksom t hsksom t ssiskm t hsksim t wskhm sckbn sobn sibn t cyskm t wskhm t dsksom t hsksom t ssiskm t hsksim t wsklm sckbn sobn sibn
1013 chapter 25 electrical specifications user?s manual u16580ee2v0ud00 figure 25-13: csib timing in slave mode (ckp, dap bits = 00b or 11b) figure 25-14: csib timing in slave mode (ckp, dap bits = 01b or 10b) t cysks t wskls t dsksos t hsksos t ssisks t hsksis t wskhs sckbn sobn sibn t cysks t wskhs t dsksos t hsksos t ssisks t hsksis t wskls sckbn sobn sibn
1014 chapter 25 electrical specifications user?s manual u16580ee2v0ud00 (2) clocked serial interface 3 (csi3) timing table 25-15: csi3 characteristics (master mode) table 25-16: csi3 characteristics (slave mode) remark: n = 0, 1 m = 0 to 3 cks3n2 to cks3n0 111b parameter symbol min. max. unit csi3 operation clock cycle time t cyk 15.625 ns sck3n clock cycle time t cyskm 125 ns sck3n high level width t wskhm 0.5 t cyskm - 10 ns sck3n low level width t wsklm 0.5 t cyskm - 10 ns si3n setup time (vs. sck3n )t ssiskm 20 ns si3n hold time (vs. sck3n )t hsksim 10 ns so3n output delay (vs. sck3n ) t dsksom 10 ns so3n output hold time (vs. sck3n )t hsksom 0.5 t cyskm - 10 ns scs3nm inactive width t wskcsb 0.5 t cyskm - 10 ns scs3nm setup time (vs. sck3n ) t scszck0 t cyk - 10 ns t scszck1 t cyskm + t cyk - 10 ns t scszck2 t cyskm - t cyk - 10 ns scs3nm hold time (vs. sck3n )t hskcsz0 t cyk - 10 ns t hskcsz1 0.5 t cyskm - 10 ns cks3n2 to cks3n0 = 111b parameter symbol min. max. unit csi3 operation clock cycle time t cyk 15.625 ns sck3n clock cycle time t cysks 125 ns sck3n high level width t wskhs 0.5 t cysks - 10 ns sck3n low level width t wskls 0.5 t cysks - 10 ns si3n setup time (vs. sck3n )t ssisks 5ns si3n hold time (vs. sck3n )t hsksis 1.5 t cyk + 10 ns so3n output delay (vs. sck3n ) t dsksos 25 ns so3n output hold time (vs. sck3n )t hsksos 0.5 t cysks - 10 ns
1015 chapter 25 electrical specifications user?s manual u16580ee2v0ud00 figure 25-15: csi3 timing in master mode (ckp, dap bits = 00b or 11b) figure 25-16: csi3 timing in master mode (ckp, dap bits = 01b or 10b) t cyk t cyskm t wsklm t dsksom t hsksom t ssiskm t hsksim t wskhm clock sck3n so3n si3n t cyk t cyskm t wskhm t dsksom t hsksom t ssiskm t hsksim t wsklm clock sck3n so3n si3n
1016 chapter 25 electrical specifications user?s manual u16580ee2v0ud00 figure 25-17: csi3 timing in slave mode (ckp, dap bits = 00b or 11b) figure 25-18: csi3 timing in slave mode (ckp, dap bits = 01b or 10b) t cyk t cysks t wskls t dsksos t hsksos t ssisks t hsksis t wskhs clock sck3n so3n si3n t cyk t cysks t wskhs t dsksos t hsksos t ssisks t hsksis t wskls clock sck3n so3n si3n
1017 chapter 25 electrical specifications user?s manual u16580ee2v0ud00 figure 25-19: csi3 chip select timing (master mode only) (csit = 0, cswe = 0, csmd = 0) figure 25-20: csi3 chip select timing (master mode only) (csit = 0, cswe = 1, csmd = 0) t hskcsz0 t scszck0 sck3n scs3n0 to scs3n3 continous transmission start (so3n output timing) intcsi3n t hskcsz0 t scszck1 sck3n scs3n0 to scs3n3 continous transmission start (so3n output timing) intcsi3n
1018 chapter 25 electrical specifications user?s manual u16580ee2v0ud00 figure 25-21: csi3 chip select timing (maste r mode only) (csit = 0, cswe = 1, csmd = 1) figure 25-22: csi3 chip select timing (maste r mode only) (csit = 1, cswe = 0, csmd = 0) t hskcsz0 t wskcsb t scszck0 sck3n scs3n0 to scs3n3 continous transmission start (so3n output timing) intcsi3n t hskcsz1 t scszck0 sck3n scs3n0 to scs3n3 continous transmission start (so3n output timing) intcsi3n
1019 chapter 25 electrical specifications user?s manual u16580ee2v0ud00 figure 25-23: csi3 chip select timing (master mode only) (csit = 1, cswe = 1, csmd = 0) figure 25-24: csi3 chip select timing (master mode only) (csit = 1, cswe = 1, csmd = 1) t hskcsz1 t scszck1 sck3n scs3n0 to scs3n3 continous transmission start (so3n output timing) intcsi3n t hskcsz1 t wskcsb t scszck2 sck3n scs3n0 to scs3n3 continous transmission start (so3n output timing) intcsi3n
1020 chapter 25 electrical specifications user?s manual u16580ee2v0ud00 25.5.3 a/d converter characteristics table 25-17: a/d converter characteristics parameter symbol min. typ. max. unit resolution - 10 bit overall error - 4lsb conversion time t conv 28s sampling time t sam 0.375 1.5 s analog input voltage v ian av ss av dd v analog supply current i avdd 2.4 ma reference voltage av ref av dd av dd v
1021 chapter 25 electrical specifications user?s manual u16580ee2v0ud00 25.6 flash programming characteristics unless specified otherwise, the follo wing conditions are assumed for all characteristics in this chapter. v dd3x = av dd = 3.0 v to 3.6 v v dd1x = cv dd = 1.35 v to 1.65 v v ss1x = cv ss = v ss3x = av ssx = 0 v table 25-18: flash memory basic characteristics parameter condition symbol min. typ. max. unit number of rewrites c wrt 100 times/ block ambient programming temperature t aprg -40 +85 c data retention time 6000 h key-on time 15 years table 25-19: flash memory programming characteristics parameter symbol min. typ. max. unit write time 30 300 s/ word erase time 0.2 2 s
1022 chapter 25 electrical specifications user?s manual u16580ee2v0ud00 figure 25-25: serial write operation characteristics table 25-20: serial write operation characteristics parameter symbol min. typ. max. unit v dd setup time to flmd0 t drpsr 0ns v dd setup time to reset t drrr 2ms flmd0 setup time to reset t psrrf 2ms flmd0 count start time from reset t rfcf 10 ms flmd0 count time t count 10 ms flmd0 counter high-level width/low-level width t ch /t cl 10 s flmd0 reset (input) v dd3 0 v v dd3 0 v 0 v v dd1 v dd1x t cl t count t ch t rfcf t psrrf t drpsr t drrr 0 v v dd3 v dd3x
1023 user?s manual u16580ee2v0ud00 chapter 26 package drawings figure 26-1: 208-pin plastic qfp (fine pitch) (28 x 28) item millimeters f g 1.25 1.25 b c 28.0 0.2 28.0 0.2 h 0.22 i 0.10 s 3.8 max. k 1.3 0.2 l 0.5 0.2 m 0.17 n 0.10 p 3.2 0.1 + 0.05 ? 0.04 j 0.5 (t.p.) p208gd-50-lml, mml, sml, wml-7 + 0.03 ? 0.07 r5 5 j i ns s detail of lead end q 0.4 0.1 m note each lead centerline is located within 0.10 mm of its true position (t.p.) at maximum material condition. 1 208 52 53 156 157 105 104 c a b q r h k m l d p g f s a 30.6 0.2 d 30.6 0.2
1024 chapter 26 package drawings user?s manual u16580ee2v0ud00 figure 26-2: 256-pin plastic bga (fine pitch) (21 x 21) s y1 s a a1 a2 s y e s x bab m ze 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 zd b a s wb s wa index mark d e ywv u t rp nm l k j hgf e dcb a item dimensions d e w e a a1 a2 b x y y1 zd ze 21.00 0.10 21.00 0.10 1.33 0.30 1.83 0.17 1.00 0.50 0.10 (unit:mm) 0.60 0.10 0.15 0.15 0.35 1.00 1.00 p256f1-100-jn4 256-pin plastic bga (21x21)
1025 user?s manual u16580ee2v0ud00 chapter 27 recommended soldering conditions solder this product under the following recommended conditions. for details of the recommended soldering conditions, refer to information document semiconductor device: mounting technology manual (c10535e). for soldering methods and conditions other than those recommended please consult nec. note: after that, prebaking is necessary at tbd c for tbd hours. the number of days refers to storage at 25c, 65% rh max after the dry pack has been opened. caution: do not use two or more soldering methods in combination (except partial heating method). table 27-1: soldering conditions soldering method soldering condition symbol of recommended soldering condition infrared reflow package peak temperature: tbd c, time: tbd seconds max. (tbd c min.), number of times: tbd max., number of days: tbd note tbd vps package peak temperature: tbd c, time: tbd seconds ma x. (tbdc min.), number of times: tbd max., number of days: tbd note tbd partial heating pin temperature: tbd c max., time: tbd seconds max. (per side of device) -
1026 user?s manual u16580ee2v0ud00 [memo]
1027 user?s manual u16580ee2v0ud00 appendix a index a a/d conversion result register n for dma . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 568 a/d conversion result registers n0 to n9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 565 a/d conversion result registers n0h to n9h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 565 a/d converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 operation in a/d trigger mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 575 operation in external trigger mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .586 operation in timer trigger mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 580 a/d converter n mode register 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 560 a/d converter n mode register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 561 a/d converter n mode register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 563 a/d converter n trigger source select register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 564 adcrn0 to adcrn9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 565 adcrn0h to adcrn9h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 565 addman . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 568 address wait control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 admn0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 560 admn1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 561 admn2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 563 adtrseln . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 564 anytime rewrite tmp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 262 tmr . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 331, 333 anytime write tmt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 469 awc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 b batch rewrite tmp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 265 tmr . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 331, 338 tmt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 471 baud rate generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 baud rate generator 3n . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 677 bcc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 bct0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 bct1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 bec . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 bpc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 brg3n . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 677 bsc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 bus clock dividing control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166 bus control unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42, 133 bus cycle configuration registers 0, 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 bus cycle control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 bus size configuration register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 byte access (8 bits) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 c callt base pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 callt execution status saving registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 can global automatic block transmission control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 762 can global automatic block transmission delay register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 765 can global clock selection register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 761 can global configuration register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 764
1028 appendix a index user?s manual u16580ee2v0ud00 can global control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 759 can message configuration register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 795 can message control register m . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 798 can message data byte register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 792 can message data length register m . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .794 can message id register m . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 797 can module bit rate prescaler register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .781 can module bit rate register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 782 can module control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 770 can module error counter register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 776 can module information register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 775 can module interrupt enable register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 777 can module interrupt status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 779 can module last error code register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 774 can module last in-pointer register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 784 can module last out-pointer register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 787 can module mask control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 766 can module receive history list register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .785 can module time stamp register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 790 can module transmit history list register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .788 capture/compare control register 10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 532 capture/compare register 100 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 527 capture/compare register 101 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 528 cbnctl0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 633 cbnctl1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 635 cbnctl2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 636 cbnrx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 631 cbnrxl . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 631 cbnstr . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 638 cbntx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 632 cc100 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 527 cc101 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 528 ccr10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 532 cg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243 chip area selection control registers 0, 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 chip select csi buffer register 3n . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 670 clock generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43, 243 clocked serial interface clock select register 3n . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 666 clocked serial interface mode registers 3n . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 664 cm100 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 525 cm101 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 526 cnbrp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 781 cnbtr . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 782 cnctrl . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 770 cnerc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 776 cngmabtd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 765 cngmconf . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 764 cngmcs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 761 cngmctr . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 759 cnie . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 777 cninfo . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 775 cnints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 779 cnlec . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 774 cnlipt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 784 cnlopt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 787 cnmask1h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 766 cnmask1l . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 766 cnmask2h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 767
1029 appendix a index user?s manual u16580ee2v0ud00 cnmask2l . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 767 cnmask3h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 768 cnmask3l . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 768 cnmask4h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 769 cnmask4l . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 769 cnmconfm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 795 cnmctrlm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 798 cnmdataxm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 792 cnmdatazm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 792 cnmdlcm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 794 cnmidhm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 797 cnmidlm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 797 cnrgpt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 785 cntgpt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 788 cnts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 790 compare register 100 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 525 compare register 101 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 526 cpu . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42, 77 cpu address space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 cpu register set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 csc0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 csc1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 csib transmit data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 632 csibn control register 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 633 csibn control register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 635 csibn control register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 636 csibn receive data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 631 csibn status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 638 csibuf status register 3n . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 672 csic3n . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 666 csil3n . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 675 csim3n . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 664 ctbp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 ctpc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 ctpsw . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 d data space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 data wait control registers 0, 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 dbpc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 dbpsw . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 debug control unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 dma controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181 dma controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 dma data size control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186 dma mode control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185 dma status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185 dma transfer a/d converter result registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188 forcible termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204 pwm timer reload . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192 serial data reception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196 serial data transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 dma transfer count registers 0 to 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184 dma transfer memory start address registers 0 to 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182 dma transfer sfr start address registers 2, 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .183 dma trigger factor registers 4 to 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187 dma wait control registers 0 and 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130, 131
1030 appendix a index user?s manual u16580ee2v0ud00 dmac . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181 dmamc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185 dmas . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185 dmawc0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130, 131 dmawc1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130, 131 dmdsc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186 dtcr0 to dtcr7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184 dtfr4 to dtfr7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187 dvc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166 dwc0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 dwc1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 e ecr . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 ect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 edge detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216 efg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 eipc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 eipsw . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 endian configuration register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 ep . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239 exception cause register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 exception status flag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239 exception trap . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240 exception/debug trap status saving registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 external bus interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 f fepc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 fepsw . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 flash memory programming mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 floating point arithmetic control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 floating point arithmetic status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 floating point arithmetic unit register set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 g general-purpose registers (r0 to r31) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 h halfword access (16 bits) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 halt mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245 release . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246 i id . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231 imr0 to imr6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228 in-service priority register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230 intc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207 internal ram area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 internal rom area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 interrupt control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224 interrupt controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42, 207 interrupt mask registers 0 to 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228 interrupt mode register 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216, 233 interrupt mode register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234 interrupt mode register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235 interrupt mode register 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236 interrupt status saving registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 intm0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216, 233
1031 appendix a index user?s manual u16580ee2v0ud00 intm1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234 intm2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235 intm3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236 intucnr . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 609 intucnre . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 609 intucnt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 609 ispr . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230 m mar0 to mar7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182 maskable interrupt status flag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231 maskable interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217 priorities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220 restore . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219 memory controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 n nmi edge detection specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216 nmi status saving registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 noise removal time control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 non-maskable interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212 restore . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215 non-maskable interrupt status flag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216 non-port pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 normal operating mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 np . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216 nrc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 o on-chip peripheral i/o area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 p pc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 peripheral area selection control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 phs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 picn . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224 pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 pin functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45, 56 pin identification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 port pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 prcmd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 prescaler compare registers 0 and 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 659 prescaler compare registers 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 555 prescaler mode register 10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 535 prescaler mode register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 554 prescaler mode registers 0 and 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 658 prm10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 535 processor command register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 program counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 program register set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 program space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 program status word . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 programmable peripheral i/o area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 prscm0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 659 prscm1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 659 prscm2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 555
1032 appendix a index user?s manual u16580ee2v0ud00 prsm0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 658 prsm1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 658 prsm2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 554 psw . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83, 216, 231, 239 r ram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 random number generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 real-time pulse unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 receive data buffer register 3n . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 669 reload tmp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 265 tmt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 471 reload mode tmr . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 331 rom . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 rom-less mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 s sar2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183 sar3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183 serial interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 sesa10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 533 sfa3n . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 672 sfcs3n . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 670 sfcs3nl . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 670 sfdb3n . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 671 sfdb3nh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 671 sfdb3nl . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 671 sfn3n . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 676 sfr area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 signal edge selection register 10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 533 single-chip modes 0, 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 sirb3n . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 669 sirb3nh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 669 sirb3nl . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 669 software exception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237 specific registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 sram connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170 status register 10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 537 status10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 537 system register set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 system status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 system wait control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130, 131 t timer control register 10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 530 timer enc10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 523 timer unit mode register 10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 529 tmc10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 530 tmenc10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 523 tmp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259 tmp input control register 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259 tmp input control register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260 tmp input control register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261 tmpn capture/compare register 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249 tmpn capture/compare register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250 tmpn control register 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252 tmpn control register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253
1033 appendix a index user?s manual u16580ee2v0ud00 tmpn counter register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251 tmpn i/o control register 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255 tmpn i/o control register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 256 tmpn i/o control register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257 tmpn option register 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 258 tmr1 i/o control register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 315 tmr1 i/o control register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 316 tmrn capture/compare register 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 302 tmrn capture/compare register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 303 tmrn capture/compare register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 304 tmrn capture/compare register 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 305 tmrn compare register 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 306 tmrn compare register 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 307 tmrn control register 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 310 tmrn control register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 312 tmrn counter read register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 308 tmrn dead time setting register 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 309 tmrn dead time setting register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 309 tmrn i/o control register 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 314 tmrn i/o control register 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 317 tmrn i/o control register 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 318 tmrn option register 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 319 tmrn option register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 321 tmrn option register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 323 tmrn option register 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 325 tmrn option register 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 327 tmrn option register 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 328 tmrn sub-counter read register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 308 tmtn capture/compare register 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 447 tmtn capture/compare register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 448 tmtn control register 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 451 tmtn control register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 453 tmtn control register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 455 tmtn counter read buffer register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 450 tmtn counter write buffer register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 450 tmtn i/o control register 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 457 tmtn i/o control register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 458 tmtn i/o control register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 459 tmtn i/o control register 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 460 tmtn option register 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 462 tmtn option register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 463 tmtn option register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 465 tpic0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259 tpic1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260 tpic2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261 tpnccr0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249 tpnccr1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250 tpncnt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251 tpnctl0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252 tpnctl1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253 tpnioc0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255 tpnioc1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 256 tpnioc2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257 tpnopt0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 258 tr1ioc1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 315 tr1ioc2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 316 transfer data length select register 3n . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 675 transfer data number specification register 3n . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .676
1034 appendix a index user?s manual u16580ee2v0ud00 transmit data csi buffer register 3n . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 671 trnccr0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 302 trnccr1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 303 trnccr2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 304 trnccr3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 305 trnccr4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 306 trnccr5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 307 trncnt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 308 trnctl0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 310 trnctl1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 312 trndtc0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 309 trndtc1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 309 trnioc0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 314 trnioc3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 317 trnioc4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 318 trnopt0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 319 trnopt1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 321 trnopt2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 323 trnopt3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 325 trnopt6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 327 trnopt7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 328 trnsbc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 308 ttnccr0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 447 ttnccr1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 448 ttncnt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 450 ttnctl0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 451 ttnctl1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 453 ttnctl2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 455 ttnioc0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 457 ttnioc1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 458 ttnioc2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 459 ttnioc3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 460 ttnopt0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 462 ttnopt1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 463 ttnopt2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 465 ttntcw . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 450 tum10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 529 u uartcn receive error interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 609 transmission enable interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 609 uartcn control register 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 596 uartcn control register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 598 uartcn control register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 599 uartcn option control register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 602 uartcn receive data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 607 uartcn status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 604 uartcn status register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 606 uartcn transmit data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 608 ucnctl0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 596 ucnctl1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 598 ucnctl2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 599 ucnopt1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 602 ucnrx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 607 ucnrxl . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 607 ucnstr . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 604 ucnstr1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 606
1035 appendix a index user?s manual u16580ee2v0ud00 ucntx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 608 ucntxl . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 608 v vswc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130, 131 w word access (32 bits) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
1036 user?s manual u16580ee2v0ud00 [memo]
1037 user?s manual u16580ee2v0ud00 appendix b revision history the following shows the revision history up to present. application portions signifies the chapter of each edition. (1/4) edition no. major items revised revised sections ee2 due to the new guideline of wording and terminology, the nickname ?phoenix-f? removed throughout the um whole user?s manual ?burst flash memory? removed throughout the um whole user?s manual bclk (burst clock output), stst and stnxt ((burst control output) removed whole user?s manual 1.4 ?ordering information?, note deleted 1.4, p.35 figure 1-1 ?pin configuration 208-pin plastic lqfp? changed 1.5, p. 36 table 1-1 ?256-pin plastic bga? changed 1.5, p.38 section ?pin identification? changed 1.5, p.40 figure 1-3 ?internal block diagram? changed 1.6.1, p.41 table 2-1 ?port pins? changed 2.1, p.48 table 2-2 ?non-port pins? changed 2.1, p.50, p.52 table 3-5 ?peripheral i/o registers? changed 3.4.6, p.101, 104, 107 figure 3-20 ?programmable peripheral area control register bpc? bits 13 and 12 changed 3.4.7 (1), p.112 3.4.8 (1), setting data to specific registers changed, caution 2 added 3.4.8 (1), p.127 3.4.10, dma wait control register 0 (dmawc0) set value changed 3.4.10, p.130 figure 4-11 ?bus clock dividing control register (dvc)? address value changed 4.7 (2), p.166 table 3-5 ?peripheral i/o registers? changed 3.4.6, p.101, 104, 107 chapter 5.2 ?burst mode flash? removed 5.2, p.180 6.1 ?features of the dma? added 6.1, p.181 figure 6-1 ?dma transfer memory start address registers 0 to 7 (mar0 to mar7)?, caution 2 added 6.2 (1), p.182 figure 6-2 ?dma transfer sfr star t address registers 2, 3 (sar2, sar3)?, caution added 6.2 (2), p.183 figure 6-3 ?dma transfer count registers 0 to 7 (dtcr0 to dtcr7)?, caution 3 deleted 6.2 (3), p.184 figure 6-8 ?initialization of dma transfer for a/d conversion result? changed 6.4.1, p.189 figure 6-9 ?operation of dma channel 0/1? added 6.4.1, p.190 figure 6-10 ?dma channel 0 and 1 trigger signal timing?, added 6.4.1, p.191 6.4.2 ?dma transfer of pwm timer reload (tmr0, tmr1)?, dma trigger count changed 6.4.2, p.192 figure 6-11 ?initialization of dma transfer for tmrn compare registers?, changed 6.4.2, p.193 figure 6-12 ?operation of dma channel 2/3?, added 6.4.2, p.194 figure 6-13 ?dma channel 2 and 3 trigger signal timing?, added 6.4.2, p.195 table 6-2 ?dma configuration of serial data reception?, dma trigger factor changed 6.4.3 (1), p.196
1038 appendix b revision history user?s manual u16580ee2v0ud00 ee2 figure 6-14 ?initialization of dma transfer for serial data reception? added 6.4.3 (1), p.197 figure 6-15 ?operation of dma ch annel 4/5?, added 6.4.3 (1), p.198 figure 6-16 ?dma channel 4 and 5 trigger signal timing? added 6.4.3 (1), p.199 table 6-3 ?dma configuration of serial data transmission?, dma trigger factor changed 6.4.3 (2), p. 200 figure 6-17 ?initialization of dma transfer for serial data transmission? added 6.4.3 (2), p. 201 figure 6-18 ?dma channel 6 and 7 trigger signal timing?, added 6.4.3 (2), p.202 figure 6-19 ?operation of dma channe l 6/7? added 6.4.3 (2), p.203 figure 6-20 ?cpu and dma controller processing of dma transfer termi- nation (example)? added 6.4.4, p.204 table 6-4 ?relations between dma trigger factors and dma completion interrupts?, dma trigger factor changed 6.5, p. 205 figure 6-21 ?correlation between serial i/o interface interrupts and dma completion interrupts? added 6.5, p.206 figure 7-10 ?interrupt control register (picn)?, value after reset and man bit description changed 7.3.4, p.224 figure 7-13 ?interrupt service priority regi ster (ispr)?, r/w changed to r 7.3.6, p.230 figure 7-15 ?interrupt m ode register 0 (intm0)?, description of bits esn1 and esn0 added 7.3.8 (1), p.233 figure 9-10 ?tmpn option register 0 (tpnopt0)?, description of tpnovf flag changed 9.4 (6), p.258 figure 9-27 ?basic operation timing in pwm mode?, remark 2 changed 9.5.6, p.283, 284 10.3 (7) ?tmrn i/o control register 4 (trnioc 4)?, description changed 10.3 (7), p.318 figure 10-19 ?tmrn option register 0 (trnopt0)? changed 10.3 (8), p.320 10.3 (11) ?tmrn option register 3 (trn opt3)? caution changed 10.3(11), p.325 figure 10-35 ?a/d conversion trigger output controller?, changed 10.8, p.362 figure 10-56 ?high-accuracy t-pwm mode block diagram?, changed 10.10.9 (1), p.405 10.10.9 (2) (d) ?interrupts? changed , notes added 10.10.9 (2) (d), p.406 10.10.9 (7) ?caution on timer output in high-accuracy t-pwm mode?, changed 10.10.9 (7), p.414-416 table 10-1 ?positive phase operation condition list? changed 10.10.9 (8), p.417 table 10-2 ?negative phase operation c ondition list? changed 10.10.9 (8), p.417 10.10.9 (8) ?timer output change after compar e register updating?, added 10.10.9 (8), p.417-429 10.10.9 (9) ?dead time control in high-accuracy t-pwm mode?, changed 10.10.9 (9), p.430 10.10.9 (10) ?cautions on dead time control in high-accuracy t-pwm mode?, added 10.10.9 (10), p.431 10.10.9 (11) ?cau tion on rewriting cycles in high-accuracy t-pwm mode?, changed 10.10.9 (11), p.432 10.10.9 (12) ?error interrupt (inttr ner) in high-accuracy t-pwm mode?, changed 10.10.9 (12), p.433 figure 10-72 ?block diagram in pwm mode with dead time?, changed 10.10.10 (1), p.434 10.10.10 (3) (e) ?reload thinning out function setting?, changed 10.10.10 (3) (e), p.437 table 11-3 ?capture/compare functions in each mode? changed 11.3 (1), p.447 table 11-4 ?capture/compare functions in each mode? changed 11.3 (2), p.449 (2/4) edition no. major items revised revised sections
1039 appendix b revision history user?s manual u16580ee2v0ud00 ee2 figure 11-6 ?tmtn control register 0 (ttnctl0)?, changed 11.4 (1), p.452 figure 11-7 ?tmtn control register 1 (ttnctl1)?, changed 11.4 (2), p.453 figure 11-8 ?tmtn control register 2 (ttnctl2)?, changed 11.4 (3), p.455-456 figure 11-9 ?tmtn i/o co ntrol register 0 (ttnioc0)?, changed 11.4 (4), p.457 figure 11-11 ?tmtn i/o control regist er 2 (ttnioc2)?, changed 11.4 (6), p.459 figure 11-12 ?tmtn i/o control register 3 (ttnioc3)?, changed 11.4 (7), p.460, 461 figure 11-13 ?tmtn option register 0 (ttnopt0)?, changed 11.4 (8), p.462 figure 11-14 ?tmtn option register 1 (ttnopt1)? changed 11.4 (9), p.464 table 11-6 ?counter clear oper ation? changed 11.5.1 (2), p.467 table 11-7 ?capture/compare rewrite method s in each mode? changed 11.5.2 82), p.472 11.6.9 ?encoder count func tion? changed 11.6.9, p.499-500 11.6.9 (6) (a) removed 11.6.9 (6), p.512 figure 11-37 (a) removed, ((c) changed, (i) and (j) removed 11.6.9 (6), p. 512-518 figure 11-38 ?basic timing in offset tr igger generation mode? changed 11.6.10, p.517 figure 14-1 ?block diagram of a/d converter (adcn)?, changed 14.2, p.559 figure 14-5 ?a/d converter n trigger source select register (adtrseln)?, changed 14.3 (4), p.564 14.4.2 (1) (b) ?timer trigger mode?, bit names changed 14.4.2 (1) (b), p.570 14.6 ?operation in timer trigger mode?, timer event signals?s names changed 14.6, p.580 14.6.1 (1) ?1-buffer mode operation (timer trigger select: 1 buffer)?, timer event signals?s names changed 14.6.1 (1), p.580 table 14-6 ?correspondence between analog input pins and adcrnm register (1-buffer mode (timer trigger select: 1 buffer)?, changed 14.6.1, p.581 figure 14-15 ?example of 1-buffer mode operation (timer trigger select: 1 buffer) (anin1)?, changed 14.6.1, p.581 14.6.1 (2) ?4-buffer mode operation (timer trigger select: 4 buffers)?, timer event signals?s names changed 14.6.1 (2), p.582 table 14-7 ?correspondence between analog input pins and adcrnm register (4-buffer mode (timer trigger select: 4 buffers)?, changed 14.6.1, p.582 figure 14-16 ?example of 4-buffer mode operation (timer trigger select: 4 buffers) (anin3)?, changed 14.6.1, p.583 table 14-8 ?correspondence between analog input pins and adcrnm register (scan mode (timer trigger scan))?, changed 14.6.2, p.584 figure 14-17 ?example of scan mode operation (timer trigger scan) (anin0 to anin4)?, changed 14.6.2, p.585 figure 15-4 ?uartcn control register 2 (ucnctl2)?, changed 15.3 (3), p.599 figure 16-28 ?prescaler compare registers 0 and 1 (prscm0, prscm1)?, changed 16.7.2 (2), p.659 figure 17-20 ?delay control of transmission/reception completion interrupt (intc3n)?, changed 17.5.14, p.692 figure 17-21 ?transfer wait function? (3/3), csitn bit value changed from 0 to 1 17.5.15, p.695 figure 18-24 ?can global clock selection register (cngmcs)?, bit 7 changed, remark 1 changed 18.6.2, p.761 table 20-1 ?port type and function overview?, port cd changed 20.2.1, p.865 (3/4) edition no. major items revised revised sections
1040 appendix b revision history user?s manual u16580ee2v0ud00 ee2 table 20-2 ?peripheral registers of i/o ports?, value after reset changed 20.2.3, p.890 figure 20-32 ?port mode control register 3 (pmc3)?, bit pmc32 description changed 20.3.4 (2) (c), p.905 figure 20-34 ?port mode register 4 (pm4)?, bits 7 and 6 values changed from ?0? to ?1? 20.3.5 (2) (b), p.907 figure 20-47 ?port mode register 7 (pm7)?, bits 7 and 6 values changed from ?0? to ?1? 20.3.8 (2) (b), p.921 figure 20-50 ?port mode register 8 (pm8)?, bit 7 value changed from ?0? to ?1? 20.3.9 (2) (b), p.925 figure 20-53 ?port mode register 9 (pm9)?, bit 7 value changed from ?0? to ?1? 20.3.10 (2) (b), p.929 figure 20-56 ?port mode register 10 (pm10)?, bits 7 to 3 values changed from ?0? to ?1?, register address changed 20.3.11 (2) (b), p.933 figure 20-57 ?port mode control register 10 (pmc10)?, register address changed 20.3.11 (2) (c), p.934 figure 23-3 ?example of recommended emulator connection of v850e/ph2?, cautions, voltage changed from 5 v to 3.3 v 23.2.1 (3), p.974 table 25-1 ?absolute maximum ratings?, v ss1 added, operating temperature conditions changed 25.1, p.997 25.2.3 ?oscillator characteristics?, remark, r1 changed to r 25.2.3, p.999 table 25-5 ?dc characteristics?, changed, notes 1 and 2 added 25.3, p.1000 table 25-6 ?external asynchronous memory access read timing?, values changed, remark 6 added 25.4.1, p.1002 figure 25-4 ?external asynchronous memory access read timing?, changed 25.4.1, p.1003 table 25-7 ?external asynchronous memory access write timing?, parameters and values changed, remark 6 added 25.4.2, p.1004 figure 25-5 ?external asynchronous memory access write timing?, changed 25.4.2, p.1005 table 25-8 ?reset timing?, reset high level width deleted 25.4.3, p.1006 figure 25-6 ?reset timing?, changed 25.4.3, p.1006 table 25-15 ?csi3 characteristics (master mode )?, minimum value changed 25.5.2 (2), p.1014 table 25-17 ?a/d converter characteristics? changed 25.5.3, p.1020 section 25.6 ?flash programming characteristics? added 25.6, p.1021 figure 26-2 ?256-pin plastic bga (fine pitch) (21 x 21)?, added 26, p.1024 (4/4) edition no. major items revised revised sections

▲Up To Search▲

Price & Availability of UPD70F3187GDA1-64-LML

	To Download UPD70F3187GDA1-64-LML Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .