m906-02 datasheet rev 0.7 revised 30jul2004 integrated circuit systems, inc. networking & communications www.icst.com tel (508) 852-5400 m906-02 vcso b ased c lock g enerator integrated circuit systems, inc. preliminary information g eneral d escription the m906-02 is a pll (phase locked loop) based clock generator that uses an internal vcso (voltage controlled saw oscillator) to produce a very low jitter output clock. from the m906-02-155.5200 , an output clock frequency of 155.52 or 77.76 mhz is provided from six lvpecl clock output pairs. (other frequencies are available; consult factory.) the accuracy of the output frequency is assured by the internal pll that phase-locks the internal vcso to the reference input frequency ( 19.44 mhz for the m906-02-155.5200 ). the input reference can either be an external cr ystal, utilizing the internal crystal oscillator, or a stab le external clock source such as a packaged crystal oscillator. f eatures output clock frequency range 75mhz to 175mhz ( consult factory for frequency availability) selectable divider chooses one of two frequencies six identical lvpecl output pairs (same frequency) jitter 0.7ps rms (at 155.52mhz, over 12khz-20mhz), typ. ideal for oc-48/stm-16 clock reference output-to-output skew < 100 ps external xtal or lvcmos reference input selectable external fe ed-through clock input stop clock control (logic 1 stops output clocks) integrated saw (surface acoustic wave) delay line single 3.3v power supply small 9 x 9 mm smt (surface mount) package p in a ssignment (9 x 9 mm smt) figure 1: pin assignment s implified b lock d iagram figure 2: simplified block diagram example output frequency configurations ( m906-02-155.5200 ) ref clock frequency (mhz) vcso frequency (mhz) p divider value output frequency (mhz) 19.44 155.52 1 155.52 2 77.76 table 1: example output frequency configurations m906-02 (top view) 1 2 3 4 5 6 7 8 9 xtal_1 / ref_in gnd stop ext_clk en_ext_clk fout_sel nfout3 fout3 vcc nfout2 fout2 nfout1 fout1 gnd nfout0 fout0 vcc gnd xtal_2 fout4 nfout4 fout5 nfout5 vcc dnc dnc dnc nop_in op_out vc nvc nop_out op_in gnd gnd gnd 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 18 17 16 15 14 13 12 11 10 m906-02-155.52 (other frequencies available) o 1 divider select external crystal or reference clock input (19.44mhz) lvpecl output clock pairs (155.52 or 77.76mhz) frequency multiplying pll divider external clock input external clock select output clock stop control external loop filter vsco xtal osc m906-02 vcso based clock generator
m906-02 datasheet rev 0.7 2 of 8 revised 30jul2004 integrated circuit systems, inc. networking & communications www.icst.com tel (508) 852-5400 integrated circuit systems, inc. m906-02 vcso b ased c lock g enerator preliminary information d etailed b lock d iagram figure 3: detailed block diagram p in d escriptions number name i/o configuration description 1, 2, 3, 10, 14, 26 gnd ground power supply ground connections. 4 9 op_in nop_in input external loop filter connections. see figure 5. 5 8 nop_out op_out output 6 7 nvc vc input 11, 19, 33 vcc power power supply connection, connect to + 3.3 v. 12, 13 fout0, nfout0 output no internal terminator clock output pairs, differential lvpecl output ( 155.52 or 77.76 mhz for the m906-02-155.5200 ) 15, 16 fout1, nfout1 17, 18 fout2, nfout2 20, 21 fout3, nfout3 29, 30 fout4, nfout4 31, 32 fout5, nfout5 22 fout_sel input determines post-pll divider value: when fout_sel = 1 , p = 1 when fout_sel = 0 , p = 2 23 en_ext_clk input internal pull-down resistor 1 note 1: for typical value of in ternal pull-down resistor, see dc characteristics , pull-down on pg. 6 for typical value. logic 1 enables the ext_clk input. use logic 0 for normal operation. 24 ext_clk input external clock feed-through: 0 to 200 mhz 25 stop input internal pull-down resistor 1 logic 1 stops clock outputs. use logic 0 for normal operation. 27 xtal_1 / ref_in input external crystal connection. also accepts lvcmos/lvttl compatible clock source. 28 xtal_2 input external crystal connection. leave unconnected when driving pin 27 with external clock reference. 34, 35, 36 dnc do not connect. internal nodes. connection to these pins can cause erratic device operation. table 2: pin descriptions vcso m906-02 saw delay line phase shifter vcso c post c post vc nvc r post nop_out op_out r post r loop r loop c loop c loop r in r in op_in nop_in phase detector loop filter amplifier external loop filter components xtal_2 xtal_1 / ref_in xtal osc m divider m = 8 o 1 ext_clk en_ext_clk stop fout2 nfout2 fout4 nfout4 fout3 nfout3 fout5 nfout5 fout0 nfout0 fout1 nfout1 p divider p = 1 or 2 fout_sel phase locked loop (pll)
m906-02 datasheet rev 0.7 3 of 8 revised 30jul2004 integrated circuit systems, inc. networking & communications www.icst.com tel (508) 852-5400 m906-02 vcso b ased c lock g enerator preliminary information integrated circuit systems, inc. f unctional d escription the m906-02 is a pll (phase locked loop) based clock generator that generates output clocks synchronized to an input reference clock. the m906-02 combines th e flexibility of a vcso (voltage controlled saw oscill ator) with the stability of a crystal oscillator. input reference the 19.44 mhz input reference can either be an external, discrete crystal device or a stable external clock source such as a packaged crystal oscillator: ? if an external crystal is used with the on-chip crystal oscillator circuit (xtal osc), the external crystal should be a parallel-resonant, fundamental mode crystal. apply it to the xtal_1 / ref_in and xtal_2 input pins. external crystal load capacitors are also required. ? if an external lvcmos/lvttl clock source is used, apply it to the xtal_1 / ref_in input pin. in either case, the reference clock is supplied directly to the phase detector of the pll. the ex_clk pin is available for a clock feed-through mode for testing. see ?external clock feed-through? on pg. 3. the pll the pll (phase locked loop) includes the phase detector, the vcso, and a feedback divider (labeled ?m divider?). the feedback divider is a digi tal circuit that divides the vcso output frequency by a numerical value ?m? in order to match the input reference frequency. by controlling the frequency and phase of the vcso, the phase detector precisely locks the frequency and phase of the feedback divider output to that of the input reference. this creates an output frequency that is a multiple of the reference frequency (which is output from the vcso). the relationship between the vcso output frequency, the m divider, and the input reference frequency is defined as follows: for the m906-02-155.5200 (see ?ordering information? on pg. 8): ? vcso output frequency = 155.52 mhz ? m = 8 ? input reference frequency = 19.44 mhz therefore, for the m906-02-155.5200 : 155.52 mhz = 8 19.44 mhz the vcso center output frequency of 155.52 mhz enables the product of to fall within the lock range of the vcso. post-pll divider the m906-02 also features a post-pll divider (labeled ?p divider?) for selecting one of two output frequencies (e.g., 155.52 or 77.76 mhz). the fout_sel pin determines the p divider value: ? when fout_sel = 1 , p = 1 . ? when fout_sel = 0 , p = 2 . external clock feed-through the ext_clk pin provides an input for an external single-ended clock that directly drives the lvpecl clock outputs. this pin is intended for system debugging and performance evaluation.. stop clock the stop pin puts the output clock into a static condition. fvcso m fxtal = en_ext_clk logic 1 enables the ext_clk input. use logic 0 for normal operation. ext_clk apply an external lvcmos/lvttl clock source for 0 to 200 mhz feed-through operation. leave inactive for normal operation. 1 note 1: in applications where ext_clk is active while the saw pll signal path is enabled, it is necessary to gate the ext_clk to minimize jitter in the lvpecl output pairs. see the pcb design guidelines for ics saw plls application note at www.icst.com/products/appnote s/m000-an-001.pcbdesign.pdf logic 1 output clocks are static logic 0 output clocks enabled for normal operation m input crystal frequency
m906-02 datasheet rev 0.7 4 of 8 revised 30jul2004 integrated circuit systems, inc. networking & communications www.icst.com tel (508) 852-5400 integrated circuit systems, inc. m906-02 vcso b ased c lock g enerator preliminary information a pplication i nformation this section includes information on the optional external crystal and on the external loop filter. the subsections on the loop filter provide example component values and also briefly describe the saw pll simulator tool and additional application information available at www.icst.com. external crystal specifications if an external crystal is used with the on-chip crystal oscillator circuit (xtal osc), the external crystal should have the following general specifications: the external crystal will be applied to the xtal_1 / ref_in and xtal_2 input pins. external crystal load capacitors are also required. recommended external crystal configuration figure 4: recommended extern al crystal configuration xtal load capacitance specification = 18 pf c1 = 27 pf c2 = 33 pf external load capacitors c1 and c2 present a load of 15 pf to the crystal (they are seen in series by the crystal through the common ground connection). with the additional of pcb trace capacitance and m906-02 input capacitance, the total load to the crystal is about 18 pf. external loop filter to provide stable pll operation, and thereby a low jitter output clock, the m906-02 requires the use of an external loop filter. this is provided via the provided filter pins (see figure 5 ). figure 5: external loop filter the loop filter is implemented as a differential circuit to minimize system noise interference. due to the differential signal path design, the implementation requires two identical complementary rc filters as shown here. see table 4, example external loop filter component values, below. refer to the m906-02 product web page at www.icst.com/products/summary/m906-02.htm for additional product information. pll simulator tool available a free pc software utility is available on the ics website (www.icst.com). the m2000 timing modules pll simulator is a downloadable application that simulates pll jitter and wander transfer characteristics. this enables the user to set appropriate external loop component values in a given application. refer to the saw pll simulator software web page at www.icst.com/products/calcul ators/m2000filterswdesc.htm for additional information. crystal specifications parameter min typ max unit crystal type at-cut quartz mode of oscillation fundamental f 0 frequency range 16 40 mhz esr equivalent series resistance 50 ? spurious response (non-harmonic) - 40 dbc c l load capacitance, parallel load resonant 16 32 pf p 0 drive level 0.1 1.0 mw table 3: crystal specifications xtal_2 xtal xtal osc m9xx-0x xtal_1 / ref_in c1 c2 m906-02 example external loop filter component values pll bandwidth ( khz ) damping factor r loop ( k ? ) c loop ( f ) r post ( k ? ) c post ( pf ) 0.395 2.0 1.5 4.70 20 3300 1.2 2.9 4.7 1.00 20 1000 10 1 note 1: recommended for minimum output jitter when using a crystal or crystal oscillator reference. 2.4 39.0 0.01 20 240 table 4: example external loop filter component values c post c post vc nvc r post nop_out op_out r post r loop r loop c loop c loop op_in nop_in 6 7 5 49 8
m906-02 datasheet rev 0.7 5 of 8 revised 30jul2004 integrated circuit systems, inc. networking & communications www.icst.com tel (508) 852-5400 m906-02 vcso b ased c lock g enerator preliminary information integrated circuit systems, inc. saw pll application notes available the ics web site (www.icst.com) also has application notes on: ? pcb layout guidelines (including special detailed instructions for preventing issues such as external reference crosstalk) ? any new special device application details that may become available ? instructions for using pll simulator software ? guidelines for pcb fabrication (including recom- mended pcb footprint, solder mask, and furnace profile) refer to the saw pll application notes web page at www.icst.com/products/appnotes/sawpllappnotes.htm for application notes and any additional product information that may become available. a bsolute m aximum r atings 1 note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these ratings are stress sp ecifications only. functional operati on of product at these conditions or any conditions beyond those listed in recommended conditions of operation, dc characteristics, or ac characteristics is not implied. exposure to absolute maximum rating condi tions for extended periods may affect product reliability . symbol parameter rating unit v i inputs - 0.5 to v cc + 0.5 v v o outputs - 0.5 to v cc + 0.5 v v cc power supply voltage 4.6 v t s storage temperature - 45 to + 100 o c table 5: absolute maximum ratings r ecommended c onditions of o peration symbol parameter min typ max unit v cc positive supply voltage 3.135 3.3 3.465 v t a ambient operating temperature commercial 0 + 70 o c industrial -40 + 85 o c table 6: recommended conditions of operation
m906-02 datasheet rev 0.7 6 of 8 revised 30jul2004 integrated circuit systems, inc. networking & communications www.icst.com tel (508) 852-5400 integrated circuit systems, inc. m906-02 vcso b ased c lock g enerator preliminary information e lectrical s pecifications dc characteristics unless stated otherwise, v cc = 3.3 v + 5 %,t a = 0 o c to + 70 o c (commercial), t a = -40 o c to + 85 o c (industrial), f vcso = 155.52mhz , 1 lvpecl outputs terminated with 50 ? to v cc - 2v symbol parameter min typ max unit power supply v cc positive supply voltage 3.135 3.3 3.465 v i cc power supply current 350 ma logic inputs v ih input high voltage fout_sel, en_ext_clk, ext_clk, stop 2 v cc + 0.3 v v il input low voltage - 0.3 0.8 v i ih input high current 150 a i il input low current - 5.0 a reference clock input v ih input high voltage xtal_1 / ref_in (xtal_2 disconnected) (v cc / 2 ) + 0.5 v cc + 0.3 v v il input low voltage - 0.3 (v cc / 2 ) + 0.5 v i ih input high current 150 a i il input low current - 5.0 a all inputs c in input capacitance, all inputs fout_sel, en_ext_clk, ext_clk, stop, xtal_1 / ref_in 4 pf pull-down r pulldown internal pull-down resistor en_ext_clk, stop 51 k ? differential output v oh output high voltage fout, nfout (0-5) v cc - 1.4 v cc - 1.0 v v ol output low voltage v cc - 2.0 v cc - 1.7 v v p - p peak to peak output voltage 0.6 0. 85 v table 7: dc characteristics note 1: for other vcso cent er frequencies, contact ics ac characteristics unless implied otherwise, v cc = 3.3 v + 5 %,t a = 0 o c to + 70 o c (commercial), t a = -40 o c to + 85 o c (industrial), f vcso = 155.52mhz , 1 lvpecl outputs terminated with 50 ? to v cc - 2v symbol parameter min typ max unit test conditions f out output frequency range 75 175 mhz fout_sel = 1 1 f in nominal input frequency, xtal_1 / ref_in 19.44 mhz apr vcso pull-range + 100 + 150 ppm n single side band phase noise @ 155.52 mhz 1 khz offset - 100 dbc/hz 10 khz offset - 110 dbc/hz 100 khz offset - 134 dbc/hz j(t) jitter (rms) 0.7 1.0 ps 12 khz to 20 mhz t dc output duty cycle, high time 45 50 55 % t r output rise time fout, nfout (0-5) 350 450 550 ps 20 % to 80 % t f output fall time fout, nfout (0-5) 350 450 550 ps 20 % to 80 % t s output skew between any pair 100 ps ext_clk frequency ext_clk 0 200 mhz table 8: ac characteristics note 1: for other vcso cent er frequencies, contact ics
m906-02 datasheet rev 0.7 7 of 8 revised 30jul2004 integrated circuit systems, inc. networking & communications www.icst.com tel (508) 852-5400 m906-02 vcso b ased c lock g enerator preliminary information integrated circuit systems, inc. d evice p ackage - 9 x 9mm c eramic l eadless c hip c arrier mechanical dimensions: figure 6: device package - 9 x 9mm ceramic leadless chip carrier refer to the saw pll application notes web page at www.icst.com/products/appnotes/sawpllappnotes.htm for application notes, including recommended pcb footprint, solder mask, and furnace profile.
m906-02 datasheet rev 0.7 8 of 8 revised 30jul2004 integrated circuit systems, inc. networking & communications www.icst.com tel (508) 852-5400 integrated circuit systems, inc. while the information presented herein has been checked for both accuracy and reliability, integrated circuit systems (ics) assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which wou ld result from its use. no other circuits, patents, or licenses are implied. this product is intended for use in normal commercial applications. any other applications such as those requiring ex tended temperature range, high reliability, or other extraordina ry environmental requirements are not recommended without additional processing by ics. ics reserves the right to change any circuitry or specifications without notice. ics does not authorize or warrant any ics product for use in life support devices o r critical medical instruments. m906-02 vcso b ased c lock g enerator preliminary information o rdering i nformation part numbering scheme figure 7: part numbering scheme consult ics for the availa bility of vcso frequencies part number: m906-02 - xxx.x x vcso frequency (mhz) ? - ? = 0 to + 70 o c (commercial) i = - 40 to + 85 o c (industrial) temperature device number see table 9 for example part numbers. consult ics for the availability of vcso frequencies. example part numbers for output frequencies (mhz) temperature order part number 155.52 (and 77.76) commercial m906-02 -155.5200 industrial m906-02 i 155.5200 150 to 175 (and 75 to 87.5) commercial m906-02 -xxx.xxxx industrial m906-02 i xxx.xxxx table 9: example part numbers
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