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publication number 26829 revision a amendment 0 issue date october 25, 2002 july 2003 the following document specifies spansion memory products that are now offered by both advanced micro devices and fujitsu. although the document is marked with the name of the company that originally developed the specifi- cation, these products will be offered to customers of both amd and fujitsu. continuity of specifications there is no change to this datasheet as a result of offering the device as a spansion product. any changes that have been made are the result of normal datasheet improvement and are noted in the document revision summary, where supported. future routine revisions will occur when appropriate, and changes will be noted in a revision sum- mary. continuity of ordering part numbers amd and fujitsu continue to support existing part numbers beginning with am and mbm. to order these prod- ucts, please use only the ordering part numbers listed in this document. for more information please contact your local amd or fujitsu sales office for additional information about spansion memory solutions. mbm29lv016t -80/-90/-12 mbm29lv016b -80/-90/-12 data sheet
ds05-20855-5e fujitsu semiconductor data sheet flash memory cmos 16m (2m 8) bit mbm29lv016t -80/-90/-12 /mbm29lv016b -80/-90/-12 n n n n description the mbm29lv016t/b is a 16m-bit, 3.0 v-only flash memory organized as 2m bytes of 8 bits each. the mbm29lv016t/b is offered in a 40-pin tsop packages. the device is designed to be programmed in-system with the standard system 3.0 v v cc supply. 12.0 v v pp and 5.0 v v cc are not required for write or erase operations. the device can also be reprogrammed in standard eprom programmers. the standard mbm29lv016t/b offers access times of 80 ns and 120 ns, allowing operation of high-speed microprocessors without wait states. to eliminate bus contention the device has separate chip enable (ce ), write enable (we ), and output enable (oe ) controls. (continued) n n n n product line up n n n n packages part no. mbm29lv016t/mbm29lv016b ordering part no. v cc = 3.0 v -80 v cc = 3.0 v -90-12 max address access time (ns) 80 90 120 max ce access time (ns) 80 90 120 max oe access time (ns) 30 35 50 40-pin plastic tsop (1) 40-pin plastic tsop (1) (fpt-40p-m06) (fpt-40p-m07) +0.3 v C0.3 v +0.6 v C0.3 v marking side marking side
mbm29lv016t -80/-90/-12 /mbm29lv016b -80/-90/-12 2 (continued) the mbm29lv016t/b is pin and command set compatible with jedec standard e 2 proms. commands are written to the command register using standard microprocessor write timings. register contents serve as input to an internal state-machine which controls the erase and programming circuitry. write cycles also internally latch addresses and data needed for the programming and erase operations. reading data out of the device is similar to reading from 5.0 v and 12.0 v flash or eprom devices. the mbm29lv016t/b is programmed by executing the program command sequence. this will invoke the embedded program algorithm which is an internal algorithm that automatically times the program pulse widths and verifies proper cell margins. typically, each sector can be programmed and verified in about 0.5 seconds. erase is accomplished by executing the erase command sequence. this will invoke the embedded erase algorithm which is an internal algorithm that automatically preprograms the array if it is not already programmed before executing the erase operation. during erase, the device automatically times the erase pulse widths and verifies proper cell margins. any individual sector is typically erased and verified in 1.0 second. (if already preprogrammed.) the device also features a sector erase architecture. the sector mode allows each sector to be erased and reprogrammed without affecting other sectors. the mbm29lv016t/b is erased when shipped from the factory. the device features single 3.0 v power supply operation for both read and write functions. internally generated and regulated voltages are provided for the program and erase operations. a low v cc detector automatically inhibits write operations on the loss of power. the end of program or erase is detected by data polling of dq 7 , by the toggle bit feature on dq 6 , or the ry/by output pin. once the end of a program or erase cycle has been comleted, the device internally resets to the read mode. the mbm29lv016t/b also has a hardware reset pin. when this pin is driven low, execution of any embedded program algorithm or embedded erase algorithm is terminated. the internal state machine is then reset to the read mode. the reset pin may be tied to the system reset circuitry. therefore, if a system reset occurs during the embedded program algorithm or embedded erase algorithm, the device is automatically reset to the read mode and will have erroneous data stored in the address locations being programmed or erased. these locations need re-writing after the reset. resetting the device enables the systems microprocessor to read the boot-up firmware from the flash memory. fujitsus flash technology combines years of flash memory manufacturing experience to produce the highest levels of quality, reliability, and cost effectiveness. the mbm29lv016t/b memory electrically erases all bits within a sector simultaneously via fowler-nordhiem tunneling. the bytes are programmed one byte at a time using the eprom programming mechanism of hot electron injection.
mbm29lv016t -80/-90/-12 /mbm29lv016b -80/-90/-12 3 n n n n features ? single 3.0 v read, program and erase minimizes system level power requirements ? compatible with jedec-standard commands uses same software commands as e 2 proms ? compatible with jedec-standard world-wide pinouts 40-pin tsop (1) (package suffix: ptn-normal bend type, ptr-reversed bend type) ? minimum 100,000 program/erase cycles ? high performance 80 ns maximum access time ? sector erase architecture one 16k byte, two 8k bytes, one 32k byte, and thirty-one 64k byte sectors in byte mode any combination of sectors can be concurrently erased. also supports full chip erase ? boot code sector architecture t = top sector b = bottom sector ? embedded erase tm * algorithms automatically pre-programs and erases the chip or any sector ? embedded program tm * algorithms automatically programs and verifies data at specified address ?data polling and toggle bit feature for detection of program or erase cycle completion ? ready/busy output (ry/by ) hardware method for detection of program or erase cycle completion ? automatic sleep mode when addresses remain stable, automatically switches themselves to low power mode ?low v cc write inhibit 2.5 v ? erase suspend/resume suspends the erase operation to allow a read data and/or program in another sector within the same device ? sector protection hardware method disables any combination of sectors from program or erase operations ? sector protection set function by extended sector protect command ? temporary sector unprotection temporary sector unprotection via the reset pin ? in accordance with cfi (c ommon f lash memory i nterface) * : embedded erase tm and embedded program tm are trademarks of advanced micro devices, inc.
mbm29lv016t -80/-90/-12 /mbm29lv016b -80/-90/-12 4 n n n n pin assignments a 16 a 15 a 14 a 13 a 12 a 11 ry/by a 18 a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 19 dq 7 dq 6 dq 5 dq 4 dq 3 dq 2 dq 1 dq 0 a 10 ce a 0 a 1 a 2 a 3 a 4 a 8 a 12 a 13 a 15 reset we a 14 a 11 a 9 a 5 a 6 a 7 a 0 ce v ss oe dq 0 dq 1 dq 2 n.c. dq 3 dq 4 dq 5 dq 6 dq 7 a 20 v ss a 19 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 33 34 35 36 21 22 23 24 25 26 27 28 29 30 31 32 mbm29lv016t/mbm29lv016b mbm29lv016t/mbm29lv016b tsop (1) (fpt-40p-m06) (fpt-40p-m07) (marking side) (marking side) a 9 a 8 we reset n.c. 17 18 19 20 36 35 34 33 40 39 38 37 v cc a 20 a 18 ry/by n.c. a 16 20 19 18 17 37 38 39 40 v cc v cc a 10 a 17 v ss a 17 v cc n.c. oe v ss normal bend reverse bend
mbm29lv016t -80/-90/-12 /mbm29lv016b -80/-90/-12 5 n n n n pin description pin name function a 20 to a 0 address inputs dq 7 to dq 0 data inputs/outputs ce chip enable oe output enable we write enable ry/by ready-busy output reset hardware reset pin/temporary sector unprotection n.c. pin not connected internally v ss device ground v cc device power supply
mbm29lv016t -80/-90/-12 /mbm29lv016b -80/-90/-12 6 n n n n block diagram v ss v cc we ce a 20 to a 0 oe erase voltage generator dq 7 to dq 0 state control command register program voltage generator low v cc detector address latch x-decoder y-decoder cell matrix y-gating chip enable output enable logic data latch input/output buffers stb stb timer for reset ry/by buffer ry/by program/erase
mbm29lv016t -80/-90/-12 /mbm29lv016b -80/-90/-12 7 n n n n logic symbol 21 a 20 to a 0 we ry/by oe ce dq 7 to dq 0 8 reset
mbm29lv016t -80/-90/-12 /mbm29lv016b -80/-90/-12 8 n n n n device bus operation mbm29lv016t/b user bus operation table legend: l = v il , h = v ih , x = v il or v ih . = pulse input. see n dc characteristics for voltage levels. *1 : manufacturer and device codes may also be accessed via a command register write sequence. see mbm29lv016t/b standard command definitions. *2 : refer to the section on sector protection. *3 : w e can be v il if oe is v il , oe at v ih initiates the write operations. *4 : v cc = 3.3 v 10% *5 : it is also used for the extended sector protection. operation ce oe we a 0 a 1 a 6 a 9 a 10 dq 7 to dq 0 reset auto-select manufacture code * 1 llhlllv id l code h auto-select device code * 1 llhhllv id l code h read * 3 llha 0 a 1 a 6 a 9 a 10 d out h standby hxxxxxxx high-z h output disable lhhxxxxx high-z h write (program/erase) l h l a 0 a 1 a 6 a 9 a 10 d in h enable sector protection * 2, * 4 lv id lhlv id xx h verify sector protection * 2, * 4 llhlhlv id l code h temporary sector unprotection * 5 xxxxxxxx x v id reset (hardware)/standby xxxxxxxx high-z l
mbm29lv016t -80/-90/-12 /mbm29lv016b -80/-90/-12 9 mbm29lv016t/b standard command definitions table *1 : address bits a 20 to a 11 = x = h or l for all address commands except or program address (pa) and sector address (sa). *2 : bus operations are defined in mbm29lv016t/b user bus operation. *3 : ra = address of the memory location to be read. pa = address of the memory location to be programmed. addresses are latched on the falling edge of the we pulse. sa = address of the sector to be erased. the combination of a 20 , a 19 , a 18 , a 17 , a 16 , a 15 , a 14 , and a 13 will uniquely select any sector. *4 : rd = data read from location ra during read operation. pd = data to be programmed at location pa. data is latched on the rising edge of we . *5 : both read/reset commands are functionally equivalent, resetting the device to the read mode. *6 : the fourth bus cycle is only for read. note : the command combinations not described in mbm29lv016t/b standard command definitions are illegal. mbm29lv016t/b extended command definitions table spa : sector address to be protected. set sector address (sa) and (a 6 , a 1 , a 0 ) = (0, 1, 0). sd : sector protection verify data. output 01h at protected sector addresses and output 00h at unprotected sector addresses. *1 : this command is valid while fast mode. *2 : addresses from system set to a 6 to a 0 . the other address are dont cares. *3 : the data 00h is also acceptable. command sequence* 1, * 2, * 3 bus write cycles req'd first bus write cycle second bus write cycle third bus write cycle fourth bus read/write cycle fifth bus write cycle sixth bus write cycle addr data addr data addr data addr data addr data addr data read/reset * 5 1 xxxhf0h read/reset * 5 3 555h aah 2aah 55h 555h f0h ra* 6 rd* 6 autoselect 3 555h aah 2aah 55h 555h 90h byte program * 3, * 4 4 555h aah 2aah 55h 555h a0h pa pd chip erase 6 555h aah 2aah 55h 555h 80h 555h aah 2aah 55h 555h 10h sector erase* 3 6 555h aah 2aah 55h 555h 80h 555h aah 2aah 55h sa 30h sector erase suspend1 xxxhb0h sector erase resume 1 xxxh30h command sequence bus write cycles req'd first bus write cycle second bus write cycle third bus write cycle fourth bus read cycle addr data addr data addr data addr data fast mode set 3 555h aah 2aah 55h 555h 20h fast program * 1 2 xxxh a0h pa pd fast mode reset 2 xxxh 90h xxxh f0h * 3 cfi * 2 255h98h extended sector protection 4 xxxh 60h spa 60h spa 40h spa sd
mbm29lv016t -80/-90/-12 /mbm29lv016b -80/-90/-12 10 mbm29lv016t/b sector protection verify autoselect code tbale * : outputs 01h at protected sector addresses and outputs 00h at unprotected sector addresses. expanded autoselect code table type a 20 to a 13 a 10 a 6 a 1 a 0 code (hex) manufactures code x v il v il v il v il 04h device code mbm29lv016t x v il v il v il v ih c7h mbm29lv016b x v il v il v il v ih 4ch sector protection sector addresses v il v il v ih v il 01h* type code dq 7 dq 6 dq 5 dq 4 dq 3 dq 2 dq 1 dq 0 manufactures code 04h00000100 device code mbm29lv016tc7h11000111 mbm29lv016b4ch01001100 sector protection 01h00000001
mbm29lv016t -80/-90/-12 /mbm29lv016b -80/-90/-12 11 n flexible sector-erase architecture ? one 16k byte, two 8k bytes, one 32k byte, and thirty-one 64k bytes sectors. ? individual-sector, multiple-sector, or bulk-erase capability. ? individual or multiple-sector protection is user definable. mbm29lv016t top boot sector architecture table sector sector size ( 8) address range sa0 64 kbytes 00000h to 0ffffh sa1 64 kbytes 10000h to 1ffffh sa2 64 kbytes 20000h to 2ffffh sa3 64 kbytes 30000h to 3ffffh sa4 64 kbytes 40000h to 4ffffh sa5 64 kbytes 50000h to 5ffffh sa6 64 kbytes 60000h to 6ffffh sa7 64 kbytes 70000h to 7ffffh sa8 64 kbytes 80000h to 8ffffh sa9 64 kbytes 90000h to 9ffffh sa10 64 kbytes a0000h to affffh sa11 64 kbytes b0000h to bffffh sa12 64 kbytes c0000h to cffffh sa13 64 kbytes d0000h to dffffh sa14 64 kbytes e0000h to effffh sa15 64 kbytes f0000h to fffffh sa16 64 kbytes 100000h to 10ffffh sa17 64 kbytes 110000h to 11ffffh sa18 64 kbytes 120000h to 12ffffh sa19 64 kbytes 130000h to 13ffffh sa20 64 kbytes 140000h to 14ffffh sa21 64 kbytes 150000h to 15ffffh sa22 64 kbytes 160000h to 16ffffh sa23 64 kbytes 170000h to 17ffffh sa24 64 kbytes 180000h to 18ffffh sa25 64 kbytes 190000h to 19ffffh sa26 64 kbytes 1a0000h to 1affffh sa27 64 kbytes 1b0000h to 1bffffh sa28 64 kbytes 1c0000h to 1cffffh sa29 64 kbytes 1d0000h to 1dffffh sa30 64 kbytes 1e0000h to 1effffh sa31 32 kbytes 1f0000h to 1f7fffh sa32 8 kbytes 1f8000h to 1f9fffh sa33 8 kbytes 1fa000h to 1fbfffh sa34 16 kbytes 1fc000h to 1fffffh
mbm29lv016t -80/-90/-12 /mbm29lv016b -80/-90/-12 12 mbm29lv016b bottom boot sector architecture table sector sector size ( 8) address range sa0 16 kbytes 00000h to 03fffh sa1 8 kbytes 04000h to 05fffh sa2 8 kbytes 06000h to 07fffh sa3 32 kbytes 08000h to 0ffffh sa4 64 kbytes 10000h to 1ffffh sa5 64 kbytes 20000h to 2ffffh sa6 64 kbytes 30000h to 3ffffh sa7 64 kbytes 40000h to 4ffffh sa8 64 kbytes 50000h to 5ffffh sa9 64 kbytes 60000h to 6ffffh sa10 64 kbytes 70000h to 7ffffh sa11 64 kbytes 80000h to 8ffffh sa12 64 kbytes 90000h to 9ffffh sa13 64 kbytes a0000h to affffh sa14 64 kbytes b0000h to bffffh sa15 64 kbytes c0000h to cffffh sa16 64 kbytes d0000h to dffffh sa17 64 kbytes e0000h to effffh sa18 64 kbytes f0000h to fffffh sa19 64 kbytes 100000h to 10ffffh sa20 64 kbytes 110000h to 11ffffh sa21 64 kbytes 120000h to 12ffffh sa22 64 kbytes 130000h to 13ffffh sa23 64 kbytes 140000h to 14ffffh sa24 64 kbytes 150000h to 15ffffh sa25 64 kbytes 160000h to 16ffffh sa26 64 kbytes 170000h to 17ffffh sa27 64 kbytes 180000h to 18ffffh sa28 64 kbytes 190000h to 19ffffh sa29 64 kbytes 1a0000h to 1affffh sa30 64 kbytes 1b0000h to 1bffffh sa31 64 kbytes 1c0000h to 1cffffh sa32 64 kbytes 1d0000h to 1dffffh sa33 64 kbytes 1e0000h to 1effffh sa34 64 kbytes 1f0000h to 1fffffh
mbm29lv016t -80/-90/-12 /mbm29lv016b -80/-90/-12 13 sector address table (mbm29lv016t) sector address a 20 a 19 a 18 a 17 a 16 a 15 a 14 a 13 ( 8) address range sa000000xxx00 000h to 0ffffh sa100001xxx10 000h to 1ffffh sa200010xxx20 000h to 2ffffh sa300011xxx30 000h to 3ffffh sa400100xxx40 000h to 4ffffh sa500101xxx50 000h to 5ffffh sa600110xxx60 000h to 6ffffh sa700111xxx70 000h to 7ffffh sa801000xxx80 000h to 8ffffh sa901001xxx90 000h to 9ffffh sa1001010xxxa0 000h to affffh sa1101011xxxb0 000h to bffffh sa1201100xxxc0 000h to cffffh sa1301101xxxd0 000h to dffffh sa1401110xxxe0 000h to effffh sa1501111xxxf0 000h to fffffh sa1610000xxx100 000h to 10ffffh sa1710001xxx110 000h to 11ffffh sa1810010xxx120 000h to 12ffffh sa1910011xxx130 000h to 13ffffh sa2010100xxx140 000h to 14ffffh sa2110101xxx150 000h to 15ffffh sa2210110xxx160 000h to 16ffffh sa2310111xxx170 000h to 17ffffh sa2411000xxx180 000h to 18ffffh sa2511001xxx190 000h to 19ffffh sa2611010xxx1a0 000h to 1affffh sa2711011xxx1b0 000h to 1bffffh sa2811100xxx1c0000h to 1cffffh sa2911101xxx1d0000h to 1dffffh sa3011110xxx1e0 000h to 1effffh sa31111110xx1f0 000h to 1f7fffh sa32111111001f8 000h to 1f9fffh sa33111111011fa 000h to 1fbfffh sa341111111x1fc000h to 1fffffh
mbm29lv016t -80/-90/-12 /mbm29lv016b -80/-90/-12 14 sector address table (mbm29lv016b) sector address a 20 a 19 a 18 a 17 a 16 a 15 a 14 a 13 ( 8) address range sa00000000x00 000h to 03fffh sa10000001004 000h to 05fffh sa20000001106 000h to 07fffh sa30000010x08 000h to 0ffffh sa400001xxx10 000h to 1ffffh sa500010xxx20 000h to 2ffffh sa600011xxx30 000h to 3ffffh sa700100xxx40 000h to 4ffffh sa800101xxx50 000h to 5ffffh sa900110xxx60 000h to 6ffffh sa1000111xxx70 000h to 7ffffh sa1101000xxx80 000h to 8ffffh sa1201001xxx90 000h to 9ffffh sa1301010xxxa0 000h to affffh sa1401011xxxb0 000h to bffffh sa1501100xxxc0 000h to cffffh sa1601101xxxd0 000h to dffffh sa1701110xxxe0 000h to effffh sa1801111xxxf0 000h to fffffh sa1910000xxx 100000h to 1fffffh sa2010001xxx110 000h to 11ffffh sa2110010xxx120 000h to 12ffffh sa2210011xxx130 000h to 13ffffh sa2310100xxx140 000h to 14ffffh sa2410101xxx150 000h to 15ffffh sa2510110xxx160 000h to 16ffffh sa2610111xxx170 000h to 17ffffh sa2711000xxx180 000h to 18ffffh sa2811001xxx190 000h to 19ffffh sa2911010xxx1a0 000h to 1affffh sa3011011xxx1b0 000h to 1bffffh sa3111100xxx1c0000h to 1cffffh sa3211101xxx1d0000h to 1dffffh sa3311110xxx1e0 000h to 1effffh sa3411111xxx1f0000h to 1fffffh
mbm29lv016t -80/-90/-12 /mbm29lv016b -80/-90/-12 15 mbm29lv016t/b common flash interface code table description a 6 to a 0 dq 7 to dq 0 description a 6 to a 0 dq 7 to dq 0 query-unique ascii string qry 10h 51h erase block region 1 information bit15 to bit0 : y = number of sectors (y + 1) bit31 to bit16 : z = size z 256 bytes 2dh 00h 11h 52h 2eh 00h 12h 59h 2fh 40h primary oem command set 02h:amd/fj standard type 13h 02h 30h 00h 14h 00h erase block region 2 information 31h 01h address for primary extended table 15h 40h 32h 00h 16h 00h 33h 20h alternate oem command set (00h = not applicable) 17h 00h 34h 00h 18h 00h erase block region 3 information 35h 00h address for alternate oem extended table 19h 00h 36h 00h 1ah 00h 37h 80h v cc min v oltage (w r ite/e r ase) dq 7 to dq 4 :1 v dq 3 to dq 0 :100 mv 1bh 27h 38h 00h erase block region 4 information 39h 1eh 3ah 00h v cc max voltage (w r ite/e r ase) dq 7 to dq 4 : 1 v dq 3 to dq 0 : 100 mv 1ch 36h 3bh 00h 3ch 01h query-unique ascii string pri 40h 50h v pp min voltage 1dh 00h 41h 52h v pp max voltage 1eh 00h 42h 49h typical time-out per single byte/word write 2 n m s 1fh 04h major version number, ascii 43h 31h typical time-out for min size buffer write 2 n m s 20h 00h minor version number, ascii 44h 30h typical time-out per individual sector erase 2 n ms 21h 0ah address sensitive unlock 00h = required 45h 00h typical time-out for full chip erase 2 n ms 22h 00h erase suspend 02h = to read & write 46h 02h max time-out for byte/word write 2 n times typical 23h 05h max time-out for buffer write 2 n times typical 24h 00h sector protection 00h = not supported x = number of sectors in per group 47h 01h max time-out per individual sector erase 2 n times typical 25h 04h max time-out for full chip erase 2 n times typical 26h 00h sector temporary unprotection 01h = supported 48h 01h device size = 2 n byte 27h 15h flash device interface description 00h : 8 28h 00h reserve 49h xxh 29h 00h 4ah xxh max number of byte in multi-byte write = 2 n 2ah 00h 4bh xxh 2bh 00h 4ch xxh number of erase block regions within device 2ch 04h
mbm29lv016t -80/-90/-12 /mbm29lv016b -80/-90/-12 16 n n n n functional description read mode the mbm29lv016t/b have two control functions which must be satisfied in order to obtain data at the outputs. ce is the power control and should be used for a device selection. oe is the output control and should be used to gate data to the output pins if a device is selected. address access time (t acc ) is equal to the delay from stable addresses to valid output data. the chip enable access time (t ce ) is the delay from stable addresses and stable ce to valid data at the output pins. the output enable access time is the delay from the falling edge of oe to valid data at the output pins. (assuming the addresses have been stable for at least t acc - t ce time.) see ac waveforms for read operations in n timing diagram for timing specifications. standby mode there are two ways to implement the standby mode on the mbm29lv016t/b devices, one using both the ce and reset pins; the other via the reset pin only. when using both pins, a cmos standby mode is achieved with ce and reset inputs both held at v cc 0.3 v. under this condition the current consumed is less than 5 m a max. during embedded algorithm operation, v cc active current (i cc2 ) is required even ce = h. the device can be read with standard access time (t ce ) from either of these standby modes. when using the reset pin only, a cmos standby mode is achieved with reset input held at v ss 0.3 v (ce = h or l). under this condition the current is consumed is less than 5 m a max. once the reset pin is taken high, the device requires t rh of wake up time before outputs are valid for read access. in the standby mode the outputs are in the high impedance state, independent of the oe input. automatic sleep mode there is a function called automatic sleep mode to restrain power consumption during read-out of mbm29lv016t/b data. this mode can be used effectively with an application requested low power consumption such as handy terminals. to activate this mode, mbm29lv016t/b automatically switch itself to low power mode when mbm29lv016t/b addresses remain stably during access time of 150 ns. it is not necessary to control ce , we , and oe on the mode. under the mode, the current consumed is typically 1 m a (cmos level). standard address access timings provide new data when addresses are changed. while in sleep mode, output data is latched and always available to the system. output disable with the oe input at a logic high level (v ih ), output from the device is disabled. this will cause the output pins to be in a high impedance state. autoselect the autoselect mode allows the reading out of a binary code from the device and will identify its manufacturer and type. this mode is intended for use by programming equipment for the purpose of automatically matching the device to be programmed with its corresponding programming algorithm. this mode is functional over the entire temperature range of the device. to activate this mode, the programming equipment must force v id (11.5 v to 12.5 v) on address pin a 9 . two identifier bytes may then be sequenced from the device outputs by toggling address a 0 from v il to v ih . all addresses are dont cares except a 0 , a 1 , a 6 , and a 10 . (see mbm29lv016t/b sector protection verify autoselect code in n device bus operation.)
mbm29lv016t -80/-90/-12 /mbm29lv016b -80/-90/-12 17 the manufacturer and device codes may also be read via the command register, for instances when the mbm29lv016t/b are erased or programmed in a system without access to high voltage on the a 9 pin. the command sequence is illustrated in mbm29lv016t/b standard command definitions in n device bus operation. (refer to autoselect command section.) byte 0 (a 0 = v il ) represents the manufactures code (fujitsu = 04h) and a 0 = v ih represents the device identifier code (mbm29lv016t = c7h, mbm29lv016b = 4ch). all identifiers for manufactures and device will exhibit odd parity with dq 7 defined as the parity bit. in order to read the proper device codes when executing the autoselect, a 1 must be v il . (see mbm29lv016t/b sector protection verify autoselect code and expanded autoselect code table in n device bus operation.) the device code is c7h (for top boot block) or 4ch (for bottom boot block). in order to determine which sectors are write protected, a 1 must be at v ih while running through the sector addresses; if the selected sector is protected, a logical 1 will be output on dq 0 (dq 0 = 1). write device erasure and programming are accomplished via the command register. the contents of the register serve as inputs to the internal state machine. the state machine outputs dictate the function of the device. the command register itself does not occupy any addressable memory location. the register is a latch used to store the commands, along with the address and data information needed to execute the command. the command register is written by bringing we to v il , while ce is at v il and oe is at v ih . addresses are latched on the falling edge of we or ce , whichever happens later; while data is latched on the rising edge of we or ce , whichever happens first. standard microprocessor write timings are used. refer to ac write characteristics and the erase/programming waveforms for specific timing parameters. sector protection the mbm29lv016t/b feature hardware sector protection. this feature will disable both program and erase operations in any number of sectors (0 through 34). the sector protection feature is enabled using programming equipment at the users site. the device is shipped with all sectors unprotected. to activate this mode, the programming equipment must force v id on address pin a 9 and control pin oe , (suggest v id = 11.5 v), ce = v il , a 0 = a 6 = v il , and a 1 = v ih . the sector addresses (a 20 , a 19 , a 18 , a 17 , a 16 , a 15 , a 14 , and a 13 ) should be set to the sector to be protected. sector address tables (mbm29lv016t) and sector address tables (mbm29lv016b) in n flexible sector-erase architecture define the sector address for each of the thirty five (35) individual sectors. programming of the protection circuitry begins on the falling edge of the we pulse and is terminated with the rising edge of the same. sector addresses must be held constant during the we pulse. see figures 13 and 21 for sector protection waveforms and algorithm. to verify programming of the protection circuitry, the programming equipment must force v id on address pin a 9 with ce and oe at v il and we at v ih . scanning the sector addresses (a 20 , a 19 , a 18 , a 17 , a 16 , a 15 , a 14 , and a 13 ) while (a 10 , a 6 , a 1 , a 0 ) = (0, 0, 1, 0) will produce a logical 1 code at device output dq 0 for a protected sector. otherwise the devices will read 00h for unprotected sector. in this mode, the lower order addresses, except for a 0 , a 1 , a 6 , and a 10 are dont cares. address locations with a 1 = v il are reserved for autoselect manufacturer and device codes. it is also possible to determine if a sector is protected in the system by writing an autoselect command. performing a read operation at the address location xx02h, where the higher order addresses (a 20 , a 19 , a 18 , a 17 , a 16 , a 15 , a 14 , and a 13 ) are the sector address will produce a logical 1 at dq 0 for a protected sector. see mbm29lv016t/ b sector protection verify autoselect code and expanded autoselect code table in n device bus operation for autoselect codes.
mbm29lv016t -80/-90/-12 /mbm29lv016b -80/-90/-12 18 temporary sector unprotection this feature allows temporary unprotection of previously protected sectors of the mbm29lv016t/b devices in order to change data. the sector unprotection mode is activated by setting the reset pin to high voltage (12 v). during this mode, formerly protected sectors can be programmed or erased by selecting the sector addresses. once the 12 v is taken away from the reset pin, all the previously protected sectors will be protected again. see figure 15 and 22. command definitions device operations are selected by writing specific address and data sequences into the command register. writing incorrect address and data values or writing them in the improper sequence will reset the devices to read mode. mbm29lv016t/b standard command definitions in n device bus operation defines the valid register command sequences. note that the erase suspend (b0h) and erase resume (30h) commands are valid only while the sector erase operation is in progress. moreover, both read/reset commands are functionally equivalent, resetting the device to the read mode. please note that commands are always written at dq 7 to dq 0 bits are ignored. read/reset command the read or reset operation is initiated by writing the read/reset command sequence into the command register. microprocessor read cycles retrieve array data from the memory. the device remains enabled for reads until the command register contents are altered. the devices will automatically power-up in the read/reset state. in this case, a command sequence is not required to read data. standard microprocessor read cycles will retrieve array data. this default value ensures that no spurious alteration of the memory content occurs during the power transition. refer to the ac read characteristics and waveforms for the specific timing parameters.(see ac waveforms for read operations and ac waveforms for hardware reset/read operations in n timing diagram.) autoselect command flash memories are intended for use in applications where the local cpu alters memory contents. as such, manufacture and device codes must be accessible while the device resides in the target system. prom programmers typically access the signature codes by raising a 9 to a high voltage. however, multiplexing high voltage onto the address lines is not generally desired system design practice. the device contains an autoselect command operation to supplement traditional prom programming methodology. the operation is initiated by writing the autoselect command sequence into the command register. following the command write, a read cycle from address xx00h retrieves the manufacture code of 04h. a read cycle from address x001h returns the device code (mbm29lv016t = c7h, mbm29lv016b = 4ch). (see mbm29lv016t/b sector protection verify autoselect code and expanded autoselect code table in n device bus operation.) all manufacturer and device codes will exhibit odd parity with the msb (dq 7 ) defined as the parity bit. sector state (protection or unprotection) will be informed address x0002h. scanning the sector addresses (a 20 , a 19 , a 18 , a 17 , a 16 , a 15 , a 14 , a 13 ) while (a 10 , a 6 , a 1 , a 0 ) = (0, 0, 1, 0) will produce a logical 1 at device output dq 0 for a protected sector. the programming verification should be perform margin mode on the protected sector. (see mbm29lv016t/b user bus operation in n device bus operation.) to terminate the operation, it is necessary to write the read/reset command sequence into the register, and also to write the autoselect command during the operation, execute it after writing read/reset command sequence.
mbm29lv016t -80/-90/-12 /mbm29lv016b -80/-90/-12 19 byte programming the device is programmed on a byte-by-byte basis. programming is a four bus cycle operation. there are two unlock write cycles. these are followed by the program set-up command and data write cycles. addresses are latched on the falling edge of ce or we , whichever happens later and the data is latched on the rising edge of ce or we , whichever happens first. the rising edge of ce or we (whichever happens first) begins programming. upon executing the embedded program algorithm command sequence, the system is not required to provide further controls or timings. the device will automatically provide adequate internally generated program pulses and verify the programmed cell margin. the automatic programming operation is completed when the data on dq 7 is equivalent to data written to this bit at which time the device returns to the read mode and addresses are no longer latched. (see hardware sequence flags.) therefore, the device requires that a valid address to the device be supplied by the system at this particular instance of time. hence, data polling must be performed at the memory location which is being programmed. any commands written to the chip during this period will be ignored. if hardware reset occurs during the programming operation, it is impossible to guarantee the data are being written. programming is allowed in any sequence and across sector boundaries. beware that a data 0 cannot be programmed back to a 1. attempting to do so may either hang up the device (exceed timing limits), or result in an apparent success according to the data polling algorithm but a read from read/reset mode will show that the data is still 0. only erase operations can convert 0s to 1s. embedded program tm algorithm in n flow chart illustrates the embedded program tm algorithm using typical command strings and bus operations. chip erase chip erase is a six bus cycle operation. there are two unlock write cycles. these are followed by writing the set-up command. two more unlock write cycles are then followed by the chip erase command. chip erase does not require the user to program the device prior to erase. upon executing the embedded erase algorithm command sequence the device will automatically program and verify the entire memory for an all zero data pattern prior to electrical erase. the system is not required to provide any controls or timings during these operations. the automatic erase begins on the rising edge of the last we pulse in the command sequence and terminates when the data on dq 7 is 1 (see write operation status section.) at which time the device returns to read the mode. embedded erase tm algorithm in n flow chart illustrates the embedded erase tm algorithm using typical command strings and bus operations. sector erase sector erase is a six bus cycle operation. there are two unlock write cycles. these are followed by writing the set-up command. two more unlock write cycles are then followed by the sector erase command. the sector address (any address location within the desired sector) is latched on the falling edge of we , while the command (data = 30h) is latched on the rising edge of we . after time-out of 50 m s from the rising edge of the last sector erase command, the sector erase operation will begin. multiple sectors may be erased concurrently by writing the six bus cycle operations on mbm29lv016t/b standard command definitions in n device bus operation. this sequence is followed with writes of the sector erase command to addresses in other sectors desired to be concurrently erased. the time between writes must be less than 50 s, otherwise that command will not be accepted and erasure will start. it is recommended that processor interrupts be disabled during this time to guarantee this condition. the interrupts can be re-enabled after the last sector erase command is written. a time-out of 50 m s from the rising edge of
mbm29lv016t -80/-90/-12 /mbm29lv016b -80/-90/-12 20 the last we will initiate the execution of the sector erase command(s). if another falling edge of the we occurs within the 50 s time-out window the timer is reset. (monitor dq 3 to determine if the sector erase timer window is still open, see section dq 3 , sector erase timer.) any command other than sector erase or erase suspend during this time-out period will reset the devices to the read mode, ignoring the previous command string. resetting the devices once execution has begun will corrupt the data in that sector. in that case, restart the erase on those sectors and allow them to complete. (refer to the write operation status section for sector erase timer operation.) loading the sector erase buffer may be done in any sequence and with any number of sectors (0 to 34). sector erase does not require the user to program the devices prior to erase. the device automatically programs all memory locations in the sector(s) to be erased prior to electrical erase. when erasing a sector or sectors the remaining unselected sectors are not affected. the system is not required to provide any controls or timings during these operations. the automatic sector erase begins after the 50 s time out from the rising edge of the we pulse for the last sector erase command pulse and terminates when the data on dq 7 is 1 (see write operation status section) at which time the device returns to the read mode. data polling must be performed at an address within any of the sectors being erased. multiple sector erase time; [sector program time (preprogramming) + sector erase time] number of sector erase. embedded erase tm algorithm in n flow chart illustrates the embedded erase tm algorithm using typical command strings and bus operations. erase suspend/resume the erase suspend command allows the user to interrupt a sector erase operation and then perform data reads from or program to a sector not being erased. this command is applicable only during the sector erase operation which includes the time-out period for sector erase. the erase suspend command will be ignored if written during the chip erase operation or embedded program algorithm. writting the erase suspend command during the sector erase time-out results in immediate termination of the time-out period and suspension of the erase operation. writing the erase resume command resumes the erase operation. the addresses are dont cares when writing the erase suspend or erase resume commands. when the erase suspend command is written during the sector erase operation, the device will take a maximum of 20 m s to suspend the erase operation. when the devices have entered the erase-suspended mode, the ry/ by output pin and the dq 7 bit will be at logic 1, and dq 6 will stop toggling. the user must use the address of the erasing sector for reading dq 6 and dq 7 to determine if the erase operation has been suspended. further writes of the erase suspend command are ignored. when the erase operation has been suspended, the device defaults to the erase-suspend-read mode. reading data in this mode is the same as reading from the standard read mode except that the data must be read from sectors that have not been erase-suspended. successively reading from the erase-suspended sector while the device is in the erase-suspend-read mode will cause dq 2 to toggle. (see the section on dq 2 .) after entering the erase-suspend-read mode, the user can program the device by writing the appropriate com- mand sequence for program. this program mode is known as the erase-suspend-program mode. again, pro- gramming in this mode is the same as programming in the regular program mode except that the data must be programmed to sectors that are not erase-suspended. successively reading from the erase-suspended sector while the devices are in the erase-suspend-program mode will cause dq 2 to toggle. the end of the erase- suspended program operation is detected by the ry/by output pin, data polling of dq 7 , or the toggle bit (dq 6 ) which is the same as the regular program operation. note that dq 7 must be read from the program address while dq 6 can be read from any address. to resume the operation of sector erase, the resume command (30h) should be written. any further writes of the resume command at this point will be ignored. another erase suspend command can be written after the chip has resumed erasing.
mbm29lv016t -80/-90/-12 /mbm29lv016b -80/-90/-12 21 extended command (1) fast mode mbm29lv016t/b has fast mode function. this mode dispenses with the initial two unlock cycles required in the standard program command sequence by writing fast mode command into the command register. in this mode, the required bus cycle for programming is two cycles instead of four bus cycles in normal command. (do not write erase command in this mode.) the read operation is also executed after exiting this mode. to exit this mode, it is necessary to write fast mode reset command into the command register. (refer to the embedded program tm algorithm for fast mode in n flow chart extended algorithm.) the v cc active current is required even ce = v ih during fast mode. (2) fast programming during fast mode, the programming can be executed with two bus cycles operation. the embedded program algorithm is executed by writing program setup command (a0h) and data write cycles (pa/pd). (refer to the embedded program tm algorithm for fast mode in n flow chart extended algorithm.) (3) cfi (c ommon f lash memory i nterface) the cfi (common flash memory interface) specification outlines device and host system software interrogation handshake which allows specific vender-specified software algorithms to be used for entire families of device. this allows device-independent, jedec id-independent, and forward- and backward-compatible software support for the specified flash device families. refer to cfi specification in detail. the operation is initiated by writing the query command (98h) into the command register. following the command write, a read cycle from specific address retrives device information. refer to the cfi code table. to terminate operation, it is necessary to write the read/reset command sequence into the register. (4) extended sector protection in addition to normal sector protection, the mbm29lv016t/b has extended sector protection as extended function. this function enable to protect sector by forcing v id on reset pin and write a command sequence. unlike conventional procedure, it is not necessary to force v id and control timing for control pins. the only reset pin requires v id for sector protection in this mode. the extended sector protect requires v id on reset pin. with this condition, the operation is initated by writing the setup command (60h) into the command register. then, the sector addresses pins (a 20 , a 19 , a 18 , a 17 , a 16 , a 15 , a 14 , and a 13 ) and (a 10 , a 6 , a 1 , a 0 ) = (0, 0, 1, 0) should be set to the sector to be protected (recommend to set v il for the other addresses pins), and write extended sector protect command (60h). a sector is typically protected in 150 m s. to verify programming of the protection cicuitry, the sector addresses pins (a 20 , a 19 , a 18 , a 17 , a 16 , a 15 , a 14 , and a 13 ) and (a 10 , a 6 , a 1 , a 0 ) = (0, 0, 1, 0) should be set and write a command (40h). following the command write, a logical 1 at device output dq 0 will produce for protected sector in the read operation. if the output data is logical 0, please repeat to write extended sector protect command (60h) again. to terminate the opetation, it is necessary to set reset pin to v ih .
mbm29lv016t -80/-90/-12 /mbm29lv016b -80/-90/-12 22 write operation status hardware sequence flags table *1 : performing successive read operations from any address will cause dq 6 to toggle. *2 : reading the byte address being programmed while in the erase-suspend program mode will indicate logic 1 at the dq 2 bit. however, successive reads from the erase-suspended sector will cause dq 2 to toggle. notes : dq 0 and dq 1 are reserve pins for future use. dq 4 is fujitsu internal use only. dq 7 data polling the mbm29lv016t/b devices feature data polling as a method to indicate to the host that the embedded algorithms are in progress or completed. during the embedded program algorithm, an attempt to read the device will produce the complement of the data last written to dq 7 . upon completion of the embedded program algorithm, an attempt to read the device will produce the true data last written to dq 7 . during the embedded erase algorithm, an attempt to read the device will produce a 0 at the dq 7 output. upon completion of the embedded erase algorithm an attempt to read the device will produce a 1 at the dq 7 output. the flowchart for data polling (dq 7 ) is shown in data polling algorithm in n flow chart. for chip erase and sector erase, the data polling is valid after the rising edge of the sixth we pulse in the six write pulse sequence. data polling must be performed at sector address within any of the sectors being erased and not a protected sector. otherwise, the status may not be valid. once the embedded algorithm operation is close to being completed, the mbm29lv016t/b data pins (dq 7 ) may change asynchronously while the output enable (oe ) is asserted low. this means that the device is driving status information on dq 7 at one instant of time and then that bytes valid data at the next instant of time. depending on when the system samples the dq 7 output, it may read the status or valid data. even if the device has completed the embedded algorithm operation and dq 7 has a valid data, the data outputs on dq 6 to dq 0 may be still invalid. the valid data on dq 7 to dq 0 will be read on the successive read attempts. the data polling feature is only active during the embedded programming algorithm, embedded erase algorithm, or sector erase time-out. (see hardware sequence flags.) see ac waveforms for data polling during embedded algorithm operations in n timing diagram for the data polling timing specifications and diagrams. status dq 7 dq 6 dq 5 dq 3 dq 2 in progress embedded program algorithm dq 7 toggle 0 0 1 embedded/erase algorithm 0 toggle 0 1 toggle erase suspend mode erase suspend read erase suspended sector) 1100toggle erase suspend read (non-erase suspended sector) data data data data data erase suspend program (non-erase suspended sector) dq 7 toggle* 1 00 1* 2 exceeded time limits embedded program algorithm dq 7 toggle 1 0 1 embedded/erase algorithm 0 toggle 1 1 n/a erase suspend program (non-erase suspended sector) dq 7 toggle 1 0 n/a
mbm29lv016t -80/-90/-12 /mbm29lv016b -80/-90/-12 23 dq 6 toggle bit i the mbm29lv016t/b also feature the toggle bit i as a method to indicate to the host system that the embedded algorithms are in progress or completed. during an embedded program or erase algorithm cycle, successive attempts to read (oe toggling) data from the devices will result in dq 6 toggling between one and zero. once the embedded program or erase algorithm cycle is completed, dq 6 will stop toggling and valid data will be read on the next successive attempts. during programming, the toggle bit i is valid after the rising edge of the fourth we pulse in the four write pulse sequence. for chip erase and sector erase, the toggle bit i is valid after the rising edge of the sixth we pulse in the six write pulse sequence. the toggle bit i is active during the sector time out. in programming, if the sector being written to is protected, the toggle bit will toggle for about 2 s and then stop toggling without the data having changed. in erase, the device will erase all the selected sectors except for the ones that are protected. if all selected sectors are protected, the chip will toggle the toggle bit for about 50 s and then drop back into read mode, having changed none of the data. either ce or oe toggling will cause the dq 6 to toggle. in addition, an erase suspend/resume command will cause the dq 6 to toggle. see ac waveforms for toggle bit i during embedded algorithm operations in n timing diagram and toggle bit algorithm in n flow chart for the toggle bit i timing specifications and diagrams. dq 5 exceeded timing limits dq 5 will indicate if the program or erase time has exceeded the specified limits (internal pulse count). under these conditions dq 5 will produce a 1. this is a failure condition which indicates that the program or erase cycle was not successfully completed. data polling dq 7 , dq 6 is the only operating function of the device under this condition. the ce circuit will partially power down the device under these conditions (to approximately 2 ma). the oe and we pins will control the output disable functions as described in mbm29lv016t/b user bus operation in n device bus operation. the dq 5 failure condition may also appear if a user tries to program a non blank location without erasing. in this case the device locks out and never completes the embedded algorithm operation. hence, the system never reads a valid data on dq 7 bit and dq 6 never stops toggling. once the device has exceeded timing limits, the dq 5 bit will indicate a 1 please note that this is not a device failure condition since the device was incorrectly used. if this occurs, reset the device with command sequence. dq 3 sector erase timer after the completion of the initial sector erase command sequence the sector erase time-out will begin. dq 3 will remain low until the time-out is complete. data polling and toggle bit are valid after the initial sector erase command sequence. if data polling or the toggle bit i indicates the device has been written with a valid erase command, dq 3 may be used to determine if the sector erase timer window is still open. if dq 3 is high (1) the internally controlled erase cycle has begun; attempts to write subsequent commands to the device will be ignored until the erase operation is completed as indicated by data polling or toggle bit i. if dq 3 is low (0), the device will accept additional sector erase commands. to insure the command has been accepted, the system software should check the status of dq 3 prior to and following each subsequent sector erase command. if dq 3 were high on the second status check, the command may not have been accepted. see hardware sequence flags.
mbm29lv016t -80/-90/-12 /mbm29lv016b -80/-90/-12 24 dq 2 toggle bit ii this toggle bit ii, along with dq 6 , can be used to determine whether the devices are in the embedded erase algorithm or in erase suspend. successive reads from the erasing sector will cause dq 2 to toggle during the embedded erase algorithm. if the devices are in the erase-suspended-read mode, successive reads from the erase-suspended sector will cause dq 2 to toggle. when the devices are in the erase-suspended-program mode, successive reads from the byte address of the non-erase suspended sector will indicate a logic 1 at the dq 2 bit. dq 6 is different from dq 2 in that dq 6 toggles only when the standard program or erase, or erase suspend program operation is in progress. for example, dq 2 and dq 6 can be used together to determine the erase-suspend-read mode. (dq 2 toggles while dq 6 does not.) see also above toggle bit status and dq 2 vs. dq 6 in n timing diagram. furthermore, dq 2 can also be used to determine which sector is being erased. when the devices are in the erase mode, dq 2 toggles if this bit is read from the erasing sector. toggle bit status table *1 : performing successive read operations from any address will cause dq 6 to toggle. *2 : reading the address being programmed while in the erase-suspend program mode will indicate logic 1 at the dq 2 bit. however, successive reads from the erase-suspended sector will cause dq 2 to toggle. ry/by ready/busy pin the mbm29lv016t/b provide a ry/by open-drain output pin as a way to indicate to the host system that the embedded algorithms are either in progress or has been completed. if the output is low, the device is busy with either a program or erase operation. if the output is high, the device is ready to accept any read/write or erase operation. when the ry/by pin is low, the device will not accept any additional program or erase commands with the exception of the erase suspend command. if the mbm29lv016t/b are placed in an erase suspend mode, the ry/by output will be high, by means of connecting with a pull up resistor to v cc . during programming, the ry/by pin is driven low after the rising edge of the fourth we pulse. during an erase operation, the ry/by pin is driven low after the rising edge of the sixth we pulse. the ry/by pin will indicate a busy condition during the reset pulse. see ry/by timing diagram during program/erase operations and reset , ry/by timing diagram in n timing diagram for a detailed timing diagram. the ry/by pin is pulled high in stadby mode. since this is an open-drain output, ry/by pins can be tied together in parallel with a pull-up resistor to v cc . mode dq 7 dq 6 dq 2 program dq 7 toggle 1 erase 0 toggle toggle erase-suspend read (erase-suspended sector) * 1 11toggle erase-suspend program dq 7 toggle * 1 1 * 2
mbm29lv016t -80/-90/-12 /mbm29lv016b -80/-90/-12 25 reset hardware reset pin the mbm29lv016t/b devices may be reset by driving the reset pin to v il . the reset pin has a pulse requirement and has to be kept low (v il ) for at least 500 ns in order to properly reset the internal state machine. any operation in the process of being executed will be terminated and the internal state machine will be reset to the read mode t ready after the reset pin is driven low. furthermore, once the reset pin goes high, the devices requires an additional t rh before it will allow read access. when the reset pin is low, the device will be in the standby mode for the duration of the pulse and all the data output pins will be tri-stated. if a hardware reset occurs during a program or erase operation, the data at that particular location will be corrupted. please note that the ry/by output signal should be ignored during the reset pulse. see reset , ry/by timing diagram in n timing diagram for the timing diagram. refer to temporary sector unprotection for additional functionality. if hardware reset occurs during embedded erase algorithm, there is a possibility that the erasing sector(s) cannot be used. data protection the mbm29lv016t/b are designed to offer protection against accidental erasure or programming caused by spurious system level signals that may exist during power transitions. during power up the device automatically resets the internal state machine in the read mode. also, with its control register architecture, alteration of the memory contents only occurs after successful completion of specific multi-bus cycle command sequences. the devices also incorporates several features to prevent inadvertent write cycles resulting form v cc power-up and power-down transitions or system noise. low v cc write inhibit to avoid initiation of a write cycle during v cc power-up and power-down, a write cycle is locked out for v cc less than 2.3 v (typically 2.4 v). if v cc < v lko , the command register is disabled and all internal program/erase circuits are disabled. under this condition the device will reset to the read mode. subsequent writes will be ignored until the v cc level is greater than v lko . it is the users responsibility to ensure that the control pins are logically correct to prevent unintentional writes when v cc is above 2.3 v. if embedded erase algorithm is interrupted, there is possibility that the erasing sector(s) cannot be used. write pulse glitch protection noise pulses of less than 5 ns (typical) on oe , ce , or we will not initiate a write cycle. logical inhibit writing is inhibited by holding any one of oe = v il , ce = v ih , or we = v ih . to initiate a write cycle ce and we must be a logical zero while oe is a logical one. power-up write inhibit power-up of the device with we = ce = v il and oe = v ih will not accept commands on the rising edge of we . the internal state machine is automatically reset to the read mode on power-up.
mbm29lv016t -80/-90/-12 /mbm29lv016b -80/-90/-12 26 n n n n absolute maximum ratings *1 : voltage is defined on the basis of v ss = gnd = 0 v. *2 : minimum dc voltage on input or l/o pins is C0.5 v. during voltage transitions, input or i/o pins may undershoot v ss to C2.0 v for periods of up to 20 ns. maximum dc voltage on output and l/o pins is v cc +0.5 v. during voltage transitions, input or i/o pins may overshoot to v cc +2.0 v for periods of up to 20 ns. *3 : minimum dc input voltage on a 9 , oe , and reset pins is C0.5 v. during voltage transitions, a 9 , oe , and reset pins may undershoot v ss to C2.0 v for periods of up to 20 ns. voltage difference between input and supply voltage (v in - v cc ) does not exceed +9.0 v. maximum dc input voltage on a 9 , oe , and reset pins is +13.0 v which may overshoot to +14.0 v for periods of up to 20 ns. warning: semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. do not exceed these ratings. n n n n recommended operating conditions * : voltage is defined on the basis of v ss = gnd = 0 v. note : operating ranges define those limits between which the functionality of the device is quaranteed. warning: the recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. all of the devices electrical characteristics are warranted when the device is operated within these ranges. always use semiconductor devices within their recommended operating condition ranges. operation outside these ranges may adversely affect reliability and could result in device failure. no warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. users considering application outside the listed conditions are advised to contact their fujitsu representatives beforehand. parameter symbol rating unit min max storage temperature tstg C55 +125 c ambient temperature with power applied t a C40 +85 c voltage with respect to ground all pins except a 9 , oe , and reset * 1, * 2 v in, v out C0.5 v cc +0.5 v power supply voltage * 1 v cc C0.5 +5.5 v a 9 , oe , and reset * 1, * 3 v in C0.5 +13.0 v parameter symbol condition value unit min max ambient temperature t a -80 C20 +70 c -90/-12 C40 +85 supply voltages* v cc -80 +3.0 +3.6 v -90/-12 +2.7 +3.6
mbm29lv016t -80/-90/-12 /mbm29lv016b -80/-90/-12 27 n n n n maximum overshoot / maximum undershoot maximum undershoot waveform +0.6 v C0.5 v 20 ns C2.0 v 20 ns 20 ns maximum overshoot waveform 1 +2.0 v v cc +0.5 v 20 ns v cc +2.0 v 20 ns 20 ns maximum overshoot waveform 2 v cc +0.5 v +13.0 v 20 ns +14.0 v 20 ns 20 ns note : this waveform is applied for a 9 , oe , and reset .
mbm29lv016t -80/-90/-12 /mbm29lv016b -80/-90/-12 28 n n n n dc characteristics *1 : the l cc current listed includes both the dc operating current and the frequency dependent component. *2 : l cc active while embedded erase or embedded program is in progress. *3 : automatic sleep mode enables the low power mode when address remain stable for 150 ns. *4 : (v id - v cc ) do not exceed 9 v. parameter symbol test conditions value unit min max input leakage current i li v in = v ss to v cc , v cc = v cc max C1.0 +1.0 a output leakage current i lo v out = v ss to v cc , v cc = v cc max C1.0 +1.0 a a 9 , oe , reset inputs leakage current i lit v cc = v cc max, a 9 , oe , reset = 12.5 v 35a v cc active current * 1 i cc1 ce = v il , oe = v ih , f = 10 mhz 30 ma ce = v il , oe = v ih , f = 5 mhz 15 ma v cc active current * 2 i cc2 ce = v il , oe = v ih 35ma v cc current (standby) i cc3 v cc = v cc max, ce = v cc 0.3 v, reset = v cc 0.3 v 5a v cc current during reset (standby, reset ) i cc4 v cc = v cc max, reset = v ss 0.3 v 5a v cc current (automatic sleep mode) * 3 i cc5 v cc = v cc max, reset = v cc 0.3 v, ce = v ss 0.3 v, v in = v cc 0.3 v or v ss 0.3 v 5a input low level v il C0.50.6v input high level v ih 2.0v cc + 0.3 v voltage for autoselect, sector protection and temporary sector unprotection (a 9 , oe , reset ) * 4 v id 11.512.5v output low voltage level v ol i ol = 4.0 ma, v cc = v cc min 0.45 v output high voltage level v oh1 i oh = C2.0 ma, v cc = v cc min 2.4 v v oh2 i oh = C100 a v cc C 0.4 v low v cc lock-out voltage v lko 2.32.5v
mbm29lv016t -80/-90/-12 /mbm29lv016b -80/-90/-12 29 n ac characteristics ? read only operations characteristics * : test conditions: output load:1 ttl gate and 30 pf (mbm29lv016t/b-80/-90) 1 ttl gate and 100 pf (mbm29lv016t/b-12) input rise and fall times: 5 ns input pulse levels: 0.0 v or 3.0 v timing measurement reference level input: 1.5 v output: 1.5 v parameter symbol test setup value* unit -80 -90 -12 jedec standard min max min max min max read cycle time t avav t rc 80 ? 90 ? 120 ? ns address to output delay t avqv t acc ce = v il oe = v il ? 80 ? 90 ? 120 ns chip enable to output delay t elqv t ce oe = v il ? 80 ? 90 ? 120 ns output enable to output delay t glqv t oe ? 30 ? 35 ? 50 ns chip enable to output high-z t ehqz t df ? 25 ? 30 ? 30 ns output enable to output high-z t ghqz t df ? 25 ? 30 ? 30 ns output hold time from address, ce or oe , whichever occurs first t axqx t oh 0 ? 0 ? 0 ? ns reset pin low to read mode t ready ? 20 ? 20 ? 20 m s test conditions c l 3.3 v diode = 1n3064 or equivalent 2.7 k w device under test diode = 1n3064 or equivalent 6.2 k w notes : c l = 30 pf including jig capacitance (mbm29lv016t/b-80/-90) c l = 100 pf including jig capacitance (mbm29lv016t/b-12)
mbm29lv016t -80/-90/-12 /mbm29lv016b -80/-90/-12 30 ? write (erase/program) operations (continued) parameter symbol value unit -80 -90 -12 jedec standard min typ max min typ max min typ max write cycle time t avav t wc 80 ?? 90 ?? 120 ?? ns address setup time t avwl t as 0 ?? 0 ?? 0 ?? ns address hold time t wlax t ah 45 ?? 45 ?? 50 ?? ns data setup time t dvwh t ds 35 ?? 45 ?? 50 ?? ns data hold time t whdx t dh 0 ?? 0 ?? 0 ?? ns output enable setup time t oes 0 ?? 0 ?? 0 ?? ns output enable hold time read t oeh 0 ?? 0 ?? 0 ?? ns toggle and data polling 10 ?? 10 ?? 10 ?? ns read recover time before write (oe high to we low) t ghwl t ghwl 0 ?? 0 ?? 0 ?? ns read recover time before write (oe high to ce low) t ghel t ghel 0 ?? 0 ?? 0 ?? ns ce setup time t elwl t cs 0 ?? 0 ?? 0 ?? ns we setup time t wlel t ws 0 ?? 0 ?? 0 ?? ns ce hold time t wheh t ch 0 ?? 0 ?? 0 ?? ns we hold time t ehwh t wh 0 ?? 0 ?? 0 ?? ns write pulse width t wlwh t wp 35 ?? 45 ?? 50 ?? ns ce pulse width t eleh t cp 35 ?? 45 ?? 50 ?? ns write pulse width high t whwl t wph 25 ?? 25 ?? 30 ?? ns ce pulse width high t ehel t cph 25 ?? 25 ?? 30 ?? ns programming operation t whwh1 t whwh1 ? 8 ?? 8 ?? 8 ? s sector erase operation * 1 t whwh2 t whwh2 ? 1 ?? 1 ?? 1 ? s delay time from embedded output enable t eoe ?? 30 ?? 35 ?? 50 ns v cc setup time t vcs 50 ?? 50 ?? 50 ?? s voltage transition time * 2 t vlht 4 ?? 4 ?? 4 ?? s write pulse width * 2 t wpp 100 ?? 100 ?? 100 ?? s oe setup time to we active * 2 t oesp 4 ?? 4 ?? 4 ?? s ce setup time to we active * 2 t csp 4 ?? 4 ?? 4 ?? s recover time from ry/by t rb 0 ?? 0 ?? 0 ?? ns reset hold time before read t rh 200 ?? 200 ?? 200 ?? ns
mbm29lv016t -80/-90/-12 /mbm29lv016b -80/-90/-12 31 (continued) *1 : this does not include the preprogramming time. *2 : this timing is for sector protection operation. parameter symbol value unit -80 -90 -12 jedec standard min typ max min typ max min typ max program/erase valid to ry/by delay t busy ?? 80 ?? 90 ?? 90 ns rise time to v id * 2 t vidr 500 ?? 500 ?? 500 ?? ns reset pulse width t rp 500 ?? 500 ?? 500 ?? ns
mbm29lv016t -80/-90/-12 /mbm29lv016b -80/-90/-12 32 n n n n erase and programming performance n tsop (1) pin capacitance note : test conditions t a = + 25c, f = 1.0 mhz parameter limits unit comments min typ max sector erase time 1 10 s excludes programming time prior to erasure byte programming time 8 300 s excludes system-level overhead chip programming time 16.8 50 s excludes system-level overhead erase/program cycle 100,000 cycle parameter symbol test setup value unit typ max input capacitance c in v in = 0 7.5 9.5 pf output capacitance c out v out = 0 8 10 pf control pin capacitance c in2 v in = 0 10 13 pf
mbm29lv016t -80/-90/-12 /mbm29lv016b -80/-90/-12 33 n timing diagram ? key to switching waveforms ac waveforms for read operations waveform inputs outputs must be steady may change from h to l may change from l to h h or l: any change permitted does not apply will be steady will be change from h to l will be change from l to h changing, state unknown center line is high- impedance off state we oe ce t df t ce t oe outputs address address stable high-z output valid high-z t oeh t acc t rc t oh
mbm29lv016t -80/-90/-12 /mbm29lv016b -80/-90/-12 34 ac waveforms for hardware reset/read operations reset t acc t oh outputs t rc address address stable high-z output valid t rh
mbm29lv016t -80/-90/-12 /mbm29lv016b -80/-90/-12 35 notes : pa is address of the memory location to be programmed. pd is data to be programmed at byte address. d q 7 is the output of the complement of the data written to the device. d out is the output of the data written to the device. figure indicates last two bus cycles out of four bus cycle sequence. ac waveforms for alternate we controlled program operations t ch t wp t whwh1 t wc t ah ce oe t rc address data t as t oe t wph t ghwl t dh dq 7 pd a0h d out we 555h pa pa t oh data polling 3rd bus cycle t cs t ce t ds d out t df
mbm29lv016t -80/-90/-12 /mbm29lv016b -80/-90/-12 36 ac waveforms for alternate ce controlled program operations notes : pa is address of the memory location to be programmed. pd is data to be programmed at byte address. d q 7 is the output of the complement of the data written to the device. d out is the output of the data written to the device. figure indicates last two bus cycles out of four bus cycle sequence. t cp t ds t whwh1 t wc t ah we oe address data t as t cph t dh dq 7 a0h d out ce 555h pa pa data polling 3rd bus cycle t ws t wh t ghel pd
mbm29lv016t -80/-90/-12 /mbm29lv016b -80/-90/-12 37 ac waveforms for chip/sector erase operations * : sa is the sector address for sector erase. addresses = 555h for chip erase. v cc ce oe address data we 555h 2aah 555h 555h 2aah sa* t ds t ch t as t ah t cs t wph t dh t ghwl t vcs t wc t wp aah 55h 80h aah 55h 10h/ 10h for chip erase 30h
mbm29lv016t -80/-90/-12 /mbm29lv016b -80/-90/-12 38 ac waveforms for data polling during embedded algorithm operations *: dq 7 = valid data (the device has completed the embedded operation.) t oeh t oe t whwh1 or 2 ce oe we data t df t ch t ce dq 7 = valid data dq 7 * data dq 6 to dq 0 = output flag t eoe dq 6 to dq 0 valid data high-z high-z dq 7 dq 6 to dq 0 * ac waveforms for toggle bit i during embedded algorithm operations * : dq 6 stops toggling. (the device has completed the embedded operation.) ce we oe data dq 6 = toggle dq 6 = stop toggling dq 7 to dq 0 data valid t oe dq 6 = toggle t oeh t oes t dh dq 6
mbm29lv016t -80/-90/-12 /mbm29lv016b -80/-90/-12 39 ry/by timing diagram during program/erase operations rising edge of the last we signal ce ry/by we t busy entire programming or erase operations reset , ry/by timing diagram t rp reset t ready ry/by we t rb
mbm29lv016t -80/-90/-12 /mbm29lv016b -80/-90/-12 40 ac waveforms for sector protection timing diagram sax : sector address for initial sector say : sector address for next sector t vlht sax say a 0 a 6 a 9 12 v 3 v oe 12 v 3 v t vlht t oesp t wpp t csp we ce t oe 01h data a 1 a 20 , a 19 , a 18 t vlht a 17 , a 16 , a 15 a 14 , a 13 t vlht t vlht v cc
mbm29lv016t -80/-90/-12 /mbm29lv016b -80/-90/-12 41 extended sector protection timing diagram spax : sector address to be protected spay : next sector address to be protected time-out : time-out window = 150 m s (min) spay reset a 6 oe we ce data a 1 v cc a 0 add spax spax 60h 01h 40h 60h 60h time-out t vcs t vlht t vidr t oe
mbm29lv016t -80/-90/-12 /mbm29lv016b -80/-90/-12 42 3 v reset v cc ce we ry/by t vlht program or erase command sequence 3 v t vlht t vcs t vidr v id t vlht unprotection period temporary sector unprotection timing diagram dq 2 vs. dq 6 * : dq 2 is read from the erase-suspended sector. dq 2 * dq 6 we erase erase suspend enter embedded erasing erase suspend read enter erase suspend program erase suspend program erase suspend read erase resume erase erase complete toggle dq 2 and dq 6 with oe or ce
mbm29lv016t -80/-90/-12 /mbm29lv016b -80/-90/-12 43 n n n n flow chart embedded program tm algorithm embedded program tm algorithm no yes start program command sequence (address/command): 555h/aah 2aah/55h 555h/a0h write program command sequence (see below) data polling device increment address verify byte ? program address/program data programming completed last address ? yes no
mbm29lv016t -80/-90/-12 /mbm29lv016b -80/-90/-12 44 embedded erase tm algorithm embedded program tm algorithm 555h/aah 2aah/55h 555h/aah 555h/80h 555h/10h 2aah/55h 555h/aah 2aah/55h 555h/aah 555h/80h 2aah/55h additional sector erase commands are optional. write erase command sequece (see below) data polling or toggle bit from device erasure completed chip erase command sequence (address/command): individual sector/multiple sector erase command sequence (address/command): sector address/30h sector address/30h sector address/30h start data = ffh no yes ?
mbm29lv016t -80/-90/-12 /mbm29lv016b -80/-90/-12 45 data polling algorithm * : dq 7 is rechecked even if dq 5 = 1 because dq 7 may change simultaneously with dq 5 . va = address for programming = any of the sector addresses within the sector being erased during sector erase or multiple erases operation. = any of the sector addresses within the sector not being protected during sector erase or multiple sector erases operation. fail dq 7 = data? no no dq 7 = data? dq 5 = 1? pass yes yes no start read byte (dq 7 to dq 0 ) addr. = va read byte (dq 7 to dq 0 ) addr. = va yes *
mbm29lv016t -80/-90/-12 /mbm29lv016b -80/-90/-12 46 toggle bit algorithm *1 : read toggle bit twice to determine whether it is toggling. *2 : dq 6 is rechecked even if dq 5 = 1 because dq 6 may stop toggling at the same time as dq 5 changing to 1. fail dq 6 = toggle ? yes no dq 6 = toggle dq 5 = 1? pass yes no yes start read ? (dq 7 to dq 0 ) addr. = h or l no read (dq 7 to dq 0 ) addr. = h or l read (dq 7 to dq 0 ) addr. = h or l *1, *2 read (dq 7 to dq 0 ) addr. = h or l *1 *1, *2 *1
mbm29lv016t -80/-90/-12 /mbm29lv016b -80/-90/-12 47 sector protection algorithm setup sector addr. activate we pulse we = v ih , ce = oe = v il (a 9 should remain v id ) yes no no plscnt = 1 time out 100 m s read from sector increment plscnt no yes protect another sector? start sector protection data = 01h? plscnt = 25? device failed remove v id from a 9 completed remove v id from a 9 write reset command ( a 1 = v ih , a 0 = v il , oe = v id , a 9 = v id a 6 = ce = v il , reset = v ih ( a 20, a 19 , a 18 , a 17, write reset command addr. = sa, a 6 = v il ) a 0 = v il , a 1 = v ih a 16 , a 15 , a 14 , a 13 )
mbm29lv016t -80/-90/-12 /mbm29lv016b -80/-90/-12 48 temporary sector unprotection algorithm *1 : all protected sectors are unprotected. *2 : all previously protected sectors are protected once again. reset = v id *1 perform erase or program operations reset = v ih start temporary sector unprotection completed *2
mbm29lv016t -80/-90/-12 /mbm29lv016b -80/-90/-12 49 embedded program tm algorithm for fast mode fast mode algorithm start 555h/aah 2aah/55h xxxh/a0h 555h/20h verify byte? no program address/program data data polling device last address ? programming completed xxxh/90h xxxh/f0h increment address no yes yes set fast mode in fast program reset fast mode
mbm29lv016t -80/-90/-12 /mbm29lv016b -80/-90/-12 50 extended sector protection algorithm to sector protection yes no no plscnt = 1 no yes protect other sector start sector protection extended sector plscnt = 25? device failed remove v id from reset completed remove v id from reset write reset command write reset command reset = v id wait to 4 m s protection entry? to setup sector protection write xxxh/60h write 60h to sector address (a 0 = v il , a 1 = v ih , a 6 = v il ) wait to 150 m s to verify sector protection write 40h to sector address (a 0 = v il , a 1 = v ih , a 6 = v il ) data = 01h? ? device is operating in temporary sector read from sector address (a 0 = v il , a 1 = v ih , a 6 = v il ) increment plscnt setup next sector address no yes yes unprotection mode
mbm29lv016t -80/-90/-12 /mbm29lv016b -80/-90/-12 51 n n n n ordering information part no. package access time sector architecture mbm29lv016t-80ptn mbm29lv016t-90ptn mbm29lv016t-12ptn 40-pin plastic tsop (1) (fpt-40p-m06) (normal bend) 80 90 120 top sector mbm29lv016t-80ptr mbm29lv016t-90ptr mbm29lv016t-12ptr 40-pin plastic tsop (1) (fpt-40p-m07) (reverse bend) 80 90 120 mbm29lv016b-80ptn mbm29lv016b-90ptn mbm29lv016b-12ptn 40-pin plastic tsop (1) (fpt-40p-m06) (normal bend) 80 90 120 bottom sector mbm29lv016b-80ptr mbm29lv016b-90ptr mbm29lv016b-12ptr 40-pin plastic tsop (1) (fpt-40p-m07) (reverse bend) 80 90 120 mbm29lv016 t -80 ptn device number/description mbm29lv016 16 mega-bit (2m 8-bit) cmos flash memory 3.0 v-only read, write, and erase pa c k a g e t y p e ptn = 40-pin thin small outline package (tsop (1) ) normal bend ptr = 40-pin thin small outline package (tsop (1) ) reverse bend speed option see product selector guide boot code sector architecture t = top sector b = bottom sector
mbm29lv016t -80/-90/-12 /mbm29lv016b -80/-90/-12 52 n n n n package dimensions (continued) 40-pin plastic tsop(1) (fpt-40p-m06) note 1) * : resin protrusion. (each side : + 0.15 (.006) max) . note 2) pins width and pins thickness include plating thickness. note 3) pins width do not include tie bar cutting remainder. dimensions in mm (inches) . note : the values in parentheses are reference values. .007 C .003 +.001 C 0.08 +0.03 0.17 "a" 0.10(.004) (mounting height) 1.10 +0.10 C 0.05 +.004 C .002 .043 (stand off) 0.10 0.05(.004 .002) (.394 .008) *10.00 0.20 0.10(.004) m (.009 .002) 0.22 0.05 (.724 .008) *18.40 0.20 (.787 .008) 20.00 0.20 lead no. index 21 20 40 1 2003 fujitsu limited f40007s-c-3-4 c 0~8 ? 0.25(.010) 0.60 0.15 (.024 .006) details of "a" part 0.50(.020)
mbm29lv016t -80/-90/-12 /mbm29lv016b -80/-90/-12 53 (continued) 40-pin plastic tsop(1) (fpt-40p-m07) note 1) * : resin protrusion. (each side : + 0.15 (.006) max) . note 2) pins width and pins thickness include plating thickness. note 3) pins width do not include tie bar cutting remainder. dimensions in mm (inches) . note : the values in parentheses are reference values. C .003 +.001 .007 C 0.08 +0.03 0.17 "a" 0.10(.004) (mounting height) 1.10 +0.10 C 0.05 +.004 C .002 .043 (stand off) 0.10 0.05(.004 .002) 0.10(.004) m (.009 .002) 0.22 0.05 (.394 .008) *10.00 0.20 (.724 .008) *18.40 0.20 (.787 .008) 20.00 0.20 lead no. index 21 20 40 1 2003 fujitsu limited f40008s-c-3-4 c 0~8 ? 0.25(.010) 0.60 0.15 (.024 .006) details of "a" part 0.50(.020)
mbm29lv016t -80/-90/-12 /mbm29lv016b -80/-90/-12 fujitsu limited all rights reserved. the contents of this document are subject to change without notice. customers are advised to consult with fujitsu sales representatives before ordering. the information, such as descriptions of function and application circuit examples, in this document are presented solely for the purpose of reference to show examples of operations and uses of fujitsu semiconductor device; fujitsu does not warrant proper operation of the device with respect to use based on such information. when you develop equipment incorporating the device based on such information, you must assume any responsibility arising out of such use of the information. fujitsu assumes no liability for any damages whatsoever arising out of the use of the information. any information in this document, including descriptions of function and schematic diagrams, shall not be construed as license of the use or exercise of any intellectual property right, such as patent right or copyright, or any other right of fujitsu or any third party or does fujitsu warrant non-infringement of any third-partys intellectual property right or other right by using such information. fujitsu assumes no liability for any infringement of the intellectual property rights or other rights of third parties which would result from the use of information contained herein. the products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for use requiring extremely high reliability (i.e., submersible repeater and artificial satellite). please note that fujitsu will not be liable against you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. any semiconductor devices have an inherent chance of failure. you must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. if any products described in this document represent goods or technologies subject to certain restrictions on export under the foreign exchange and foreign trade law of japan, the prior authorization by japanese government will be required for export of those products from japan. f0306 ? fujitsu limited printed in japan

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