design and specifications a r e subject to change without notice. ask facto r y for technical specifications befo r e pu r chase and/or use. whenever a doubt about safety issues arises f r om this p r oduct, please info r m us immediately for technical consultation. digital dbs unit t ype qf2, qf3 high performance qpsk channel decode r . suitable for multimedia application. features compact size, best fit on set t op box and pc- a t boa r d easy inte r face with t ransport decoder recommended applications dbs / cs digital set t op box, pc- a t boa r d performance specifications, summary block diagram t ype : pa r t no.: qf2 qf3 ena6 1 . input signal analog i and q baseband 2 . input signal level digital dbs t uner (dc7) output compatible 3 . output signal 8 bits parallel fec deco r ded 4 . output level cmos (3.3 v) level 5. t ransmission rate 4 to 60 m bps. 6 . host inte r face bus i 2 c (r) 7 . power supply + 3.3 v : tbd + 5 v : tbd + 12 v : tbd 8 . modulation method qpsk qf2 qf3 bs-if fec output ch_sel nim_cnt stat err cnd mrst a / d, qpsk, fec 1 chip lsi mpeg if i 2 c if i 2 c pc dc7 qf2 bs-if fec output a / d, qpsk, fec 1 chip lsi mpeg if i 2 c if dc7 qf3 qf2 qf3
design and specifications a r e subject to change without notice. ask facto r y for technical specifications befo r e pu r chase and/or use. whenever a doubt about safety issues arises f r om this p r oduct, please info r m us immediately for technical consultation. + 5 v 9 agc scl afc v dc (a) v dc (d) sda nreset sd in gn d 17 13 15 16 14 11 12 10 + 12 v + 3.3 v q in terminal supply voltage gnd terminal name v dc (a) i in v dc (a) gnd v dc (d) gnd no. 4 7 8 5 6 2 3 1 supply voltage + 5 v + 3.3 v 64.77 26 chd0 chd5 chd1 chd2 chd3 chd4 chd6 chd7 enabl e 34 30 32 33 31 28 29 27 sybclk fsync gnd gnd noerr psync den oclk 21 24 25 22 23 19 20 18 clock data 35 36 4. 0 3.81pich 1.8 1 2.0 64.77 66.8 72.8 2.0 0.4 1.2 2.5 3.25 3.25 2.6 1.81 3.81 pic h 4.0 3.0 3.6 0.3 45.0 10.0 digital dbs unit dimensions in mm (not to scale) qf2 qf3 5.2 3.6 47.8 46.6 0.0 7.2 9.2 11.2 13.2 15.2 17.2 19.2 21.2 23.2 25.2 27.2 29.2 31.2 40.2 13.0 39.7 0.5 11.4 5.2 2.0 3. 0 3.0 28 - 0.5 1 2 28 27 terminal supply voltage 11 supply voltage + 3.3 v +12.0 v + 3.3 v + 5.0 v + 3.3 v + 5.0 v 2 6 8 10 9 7 4 5 3 terminal nam e no. 1 v dc ( digital ) v dc ( analog ) chd6 noerr chd4 chd5 chd2 chd1 chd7 chd3 oclk chdo dataen fsync dvb sel psync v dc ( digital ) sybclk v dc ( analog ) nreset i in scl ( i 2 c ) q in sda ( i 2 c ) v dc ( analog ) agc gnd afc 17 12 14 16 15 13 18 24 19 21 23 22 20 25 27 28 26
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