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april 2002 preliminary copyright ? alliance semiconductor. all rights reserved. ? as7c33256pfd32a as7c33256pfd36a 3.3v 256k 32/36 pipeline burs t synchronous sram 4/15/02; v.1.8 alliance semiconductor p. 1 of 14 features ? organization: 262,144 words 32 or 36 bits fast clock speeds to 166 mhz in lvttl/lvcmos fast clock to data access: 3.5/3.8/4.0/5.0 ns fast oe access time: 3.5/3.8/4.0/5.0 ns fully synchronous regist er-to-register operation single register ?f low-through? option dual-cycle deselect - single-cycle deselect also available (as7c33256pfs32a/ as7c33256pfs36a) available in both 2 chip enable and 3 chip enable - 2 ce part number is as7c33256pfd32a2 or as7c33256pfd36a2 pentium ? 1 compatible architecture and timing asynchronous output enable control available in 100-pin tqfp and 119-pin bga packages byte write enables 3.3v core power supply 2.5v or 3.3v i/o operation with separate v ddq 30 mw typical standby power in power down mode ntd? 1 pipeline architecture available (as7c33256ntd32a/ as7c33256ntd36a) 1 * pentium ? is a registered trademark of intel corporation. ntd? is a trademark of alliance semiconductor corporation. all trademarks mentioned in this document are the property of their respective owners logic block diagram q0 q1 256k 32/36 memory array burst logic clk clr ce address dq ce clk dq d clk dq byte write registers register dq c clk dq byte write registers dq b clk dq byte write registers dq a clk dq byte write registers enable clk dq register enable clk dq delay register ce output registers input registers power down 4 36/32 18 16 18 18 gwe bwe bw d adv adsc adsp clk ce0 ce1 ce2 bw c bw b bw a oe a [17:0] zz lbo oe ft clk clk 36/32 2 2 36/32 dq[a;d] selection guide ?166 ?150 ?133 ?100 units minimum cycle time 6 6.6 7.5 10 ns maximum pipelined clock frequency 166 150 133 100 mhz maximum pipelined clock access time 3.5 3.8 4 5 ns maximum operating current 475 450 425 325 ma maximum standby current 130 110 100 90 ma maximum cmos standby current (dc) 30 30 30 30 ma
4/15/02; v.1.8 alliance semiconductor p. 2 of 14 as7c33256pfd32a as7c33256pfd36a ? dqp c /nc dq c dq c v ddq v ssq dq c dq c dq c dq c v ssq v ddq dq c dq c ft v dd nc v ss dq d dq d v ddq v ssq dq d dq d dq d dq d v ssq v ddq dq d dq d dqp d /nc 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 dqp b /nc dq b dq b v ddq v ssq dq b dq b dq b dq b v ssq v ddq dq b dq b v ss zz dq a dq a v ddq v ssq dq a dq a dq a dq a v ssq v ddq dq a dq a dqp a /nc lbo a5 a4 a3 a2 a1 a0 nc nc v ss v dd nc a17 a10 a11 a12 a13 a14 a15 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 a6 a7 ce0 ce1 bw d bw c bw b bw a ce2 v dd v ss clk gwe bwe oe adsc adsp adv a8 a9 nc vdd a16 note: pins 1, 30, 51, 80 are nc for 32 tqfp 14 20 mm pin arrangment for tqfp 3 chip enable dqp c /nc dq c dq c v ddq v ssq dq c dq c dq c dq c v ssq v ddq dq c dq c ft v dd nc v ss dq d dq d v ddq v ssq dq d dq d dq d dq d v ssq v ddq dq d dq d dqp d /nc 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 dqp b /nc dq b dq b v ddq v ssq dq b dq b dq b dq b v ssq v ddq dq b dq b v ss zz dq a dq a v ddq v ssq dq a dq a dq a dq a v ssq v ddq dq a dq a dqp a /nc lbo a5 a4 a3 a2 a1 a0 nc nc v ss v dd nc nc a10 a11 a12 a13 a14 a15 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 a6 a7 ce0 ce1 bw d bw c bw b bw a a17 v dd v ss clk gwe bwe oe adsc adsp adv a8 a9 nc vdd a16 note: pins 1, 30, 51, 80 are nc for 32 tqfp 14 20 mm pin arrangment for tqfp 2 chip enable
4/15/02; v.1.8 alliance semiconductor p. 3 of 14 as7c33256pfd32a as7c33256pfd36a ? ball assignment for 119-ball bga 1 1 note 2d, 2p, 6d and 6p are nc for x32 1 2 3 4 5 6 7 a v ddq aaadsp aav ddq b nc ce1 a adsc aanc c nc a a v dd aanc d dq c dqpc v ss nc v ss dqpb dqb e dq c dqc v ss ce0 v ss dqb dqb f v ddq dqc v ss oe v ss dqb v ddq g dq c dqc bwc adv bwb dqb dqb h dq c dqc v ss gwe v ss dqb dqb j v ddq v dd nc v dd nc v dd v ddq k dqd dqd v ss clk v ss dqa dqa l dqd dqd bwd nc bwa dqa dqa m v ddq dqd v ss bwe v ss dqa v ddq n dqd dqd v ss a1 2 2 a0 and a1 are the two least significant bits (lsb) of the address field and set the internal burst counter if burst is desired. v ss dqa dqa p dqd dqpd v ss a0 2 v ss dqpa dqa r nc a lbo v dd ft anc t nc nc a a a nc zz u v ddq nc nc nc nc nc v ddq
4/15/02; v.1.8 alliance semiconductor p. 4 of 14 as7c33256pfd32a as7c33256pfd36a ? functional description the as7c33256pfd32a and 7c33256pfd36a are high-p erformance cmos 8-mbit synchronous static random access memory (sram) devices organized as 262,144 words 32 or 36 bi ts, and incorporate a two-stage register -register pipeline for highest frequenc y on any given technology. timing for these devices is co mpatible with existing pentium ? synchronous cache specifications. this architecture is suited for asic, dsp (tms320c6x), and powerpc ? 1 -based systems in computing, datacomm, instru mentation, and telecommunications systems. fast cycle times of 6/6.6/7.5/ 10 ns with clock access times (t cd ) of 3.5/3.8/4.0/5.0 ns enable 166, 150, 133 and 100 mhz bus frequencies. two-chip enable and three-chip enable (ce ) inputs permit easy memory expansion. burst operation is initiated in one of two ways: the controller address strobe (adsc ), or the processor address strobe (adsp ). the burst advance pin (adv ) allows subsequent internally generated burst addresses. read cycles are initiated with adsp (regardless of we and adsc ) using the new external address cloc ked into the on-chip address register when adsp is sampled low, the chip enables are sampled active, and the output buffer is enabled with oe . in a read operation the data accessed by the current address, registered in the address registers by the positive edge of clk, are ca rried to the data-out registers and driven on the output pins on the next po sitive edge of clk. adv is ignored on the clock edge that samples adsp asserted, but is sampled on all subsequent clock edges. address is incremented internally for the next access of the burst when adv is sampled low, and both address strobes are high. burst mode is selectable with the lbo input. with lbo unconnected or driven high, burst operations use a pentium ? count sequence. with lbo driven low, the device uses a linear count sequence suitable for powerpc ? and many other applications. write cycles are performed by disabling the output buffers with oe and asserting a write command. a global write enable gwe writes all 32/ 36 bits regardless of the state of individual bw[a:d] inputs. alternately, when gwe is high, one or more bytes may be written by asserting bwe and the appropriate individual byte bwn signal(s). bwn is ignored on the clock edge that samples adsp low, but is sampled on all subsequent clock edges. output buffers are disabled when bwn is sampled low (regardless of oe ). data is clocked into the data input register when bwn is sampled low. address is incremented internally to the next burst address if bwn and adv are sampled low. read or write cycles may also be initiated with adsc instead of adsp . the differences between cycles initiated with adsc and adsp follow. adsp must be sampled high when adsc is sampled low to initiate a cycle with adsc . we signals are sampled on the clock edge that samples adsc low (and adsp high). master chip enable ce0 blocks adsp , but not adsc . as7c33256pfd32a and as7c33256pfd36a family operates from a core 3.3v power supply. i/os use a separate power supply that can op erate at 2.5v or 3.3v. these devices are available in 100-pi n 14 20 mm tqfp package and 119-pin 14 x 20 mm bga package. x = don?t care, l = low, h = high, t = true, f = false; *= valid read; n = a, b, c, d; we , wen = internal write signal. 1powerpc ? is a trademark international business machines corporation. capacitance parameter symbol signals test conditions max unit input capacitance c in address and control pins v in = 0v 5 pf i/o capacitance c i/o i/o pins v in = v out = 0v 7 pf write enable truth table (per byte) gwe bwe bwn wen lxx t hl l t hhx f* hlh f * burst order table interleaved burst order lbo =1 linear burst order lbo =0 starting address 00 01 10 11 starting address 00 01 10 11 first increment 01 00 11 10 first increment 01 10 11 00 second increment 10 11 00 01 second increment 10 11 00 01 third increment 11 10 01 00 third increment 11 00 01 10
4/15/02; v.1.8 alliance semiconductor p. 5 of 14 as7c33256pfd32a as7c33256pfd36a ? stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions outside those indicated in the operational sections of this specification is not im plied. exposure to absolute maximum rating conditions may affect reliability. signal descriptions signal i/o properties description clk i clock clock. all inputs except oe , ft , zz, lbo are synchronous to this clock. a0?a17 i sync address. sampled when all chip enables are active and adsc or adsp are asserted. dq[a,b,c,d] i/o sync data. driven as output when the chip is enabled and oe is active. ce0 isync master chip enable. sampled on clock edges when adsp or adsc is active. when ce0 is inactive, adsp is blocked. refer to the synchronous truth table for more information. ce1, ce2 isync synchronous chip enables. active high and active low, respectively. sampled on clock edges when adsc is active or when ce0 and adsp are active. adsp isync address strobe processor. asserted low to load a new bus address or to enter standby mode. adsc i sync address strobe controller. asserted low to load a new address or to enter standby mode. adv i sync advance. asserted low to continue burst read/write. gwe isync global write enable. asserted low to write all 32/36 bits. when high, bwe and bw[a:d] control write enable. bwe i sync byte write enable. asserted low with gwe = high to enable effect of bw[a:d] inputs. bw[a,b,c,d] isync write enables. used to control write of individual bytes when gwe = high and bwe = low. if any of bw[a:d] is active with gwe = high and bwe = low the cycle is a write cycle. if all bw[a:d] are inactive the cycle is a read cycle. oe iasync asynchronous output enable. i/o pins are driven when oe is active and the chip is in read mode. lbo istatic count mode. when driven high, count sequence follows intel xor convention. when driven low, count sequence follows linear convention. this signal is internally pulled high. ft istatic flow-through mode.when low, enables single register flow-through mode. connect to v dd if unused or for pipelined operation. zz i async snooze. places device in low power mode ; data is retained. connect to gnd if unused. absolute maximum ratings parameter symbol min max unit power supply voltage relative to gnd v dd , v ddq ?0.5 +4.6 v input voltage relative to gnd (input pins) v in ?0.5 v dd + 0.5 v input voltage relative to gnd (i/o pins) v in ?0.5 v ddq + 0.5 v power dissipation p d ?1.8w dc output current i out ?50ma storage temperature (plastic) t stg ?65 +150 o c temperature under bias t bias ?65 +135 o c
4/15/02; v.1.8 alliance semiconductor p. 6 of 14 as7c33256pfd32a as7c33256pfd36a ? key: x = don?t care, l = low, h = high. synchronous truth table ce0 ce1 ce2 adsp adsc adv wen 1 1 see ?write enable truth table?on page 4 for more information. oe address accessed clk operation dq h x x x l x x x na l to h deselect hi ? z l l x l x x x x na l to h deselect hi ? z l l x h l x x x na l to h deselect hi ? z l x h l x x x x na l to h deselect hi ? z l x h h l x x x na l to h deselect hi ? z lhl lxxxl external l to hbegin readhi ? z 2 2 q in ?flow through? mode lhl lxxxh external l to hbegin readhi ? z lhlhlxfl external l to hbegin readhi ? z 2 lhlhlxfh external l to hbegin readhi ? z xxxhhlfl next l to h cont. read q xxxhhlfh next l to h cont. readhi ? z x x x h h h f l current l to h suspend read q xxxhhhfh current l to hsuspend readhi ? z hxxxhlfl next l to h cont. read q hxxxhlfh next l to h cont. readhi ? z hxxxhhfl current l to hsuspend readq hxxxhhfh current l to hsuspend readhi ? z lhlhlxtx external l to hbegin writed 3 3 for write operation following a read, oe must be high before the input data set up time and held high throughout the input hold time. xxxhhltx next l to hcont. writed hxxxhltx next l to hcont. writed x x x h h h t x current l to h suspend write d h x x x h h t x current l to h suspend write d recommended operating conditions parameter symbol min nominal max unit supply voltage v dd 3.135 3.3 3.465 v v ss 0.0 0.0 0.0 3.3v i/o supply voltage v ddq 3.135 3.3 3.465 v v ssq 0.0 0.0 0.0 2.5v i/o supply voltage v ddq 2.35 2.5 2.9 v v ssq 0.0 0.0 0.0 input voltages 1 1 input voltage ranges apply to 3.3v i/o operation. for 2.5v i/o operation, contact factory for input specifications. address and control pins v ih 2.0 ? v dd + 0.3 v v il ?0.5 2 2 v il min = ?2.0v for pulse width less than 0.2 t rc . ?0.8 i/o pins v ih 2.0 ? v ddq + 0.3 v v il ?0.5 2 ?0.8 ambient operating temperature t a 0?70 c
4/15/02; v.1.8 alliance semiconductor p. 7 of 14 as7c33256pfd32a as7c33256pfd36a ? tqfp thermal resistance description conditions symbol ty p i c a l thermal resistance (junction to ambient) 1 1 this parameter is sampled. test conditions follow standard test methods and procedures for measuring thermal impedance, per eia/jesd51 1?layer ja 40 4?layer ja 22 thermal resistance (junction to top of case) 1 jc 8 dc electrical characteristics parameter symbol test conditions ?166 ?150 ?133 ?100 unit min max min max min max min max input leakage current 1 1 lbo pin has an internal pull-up and input leakage = 10 a. |i li |v dd = max, v in = gnd to v dd ?2?2?2?2a output leakage current |i lo | oe v ih , v dd = max, v out = gnd to v dd ?2?2?2?2a operating power supply current i cc 2 (pipelined) 2 i cc given with no output loading. i cc increases with faster cycles times and greater output loading. ce0 = v il , ce1 = v ih , ce2 = v il , f = f max , i out = 0 ma ? 475 ? 450 ? 425 ? 325 ma operating power supply current i cc 2 (flow- through) ce0 = v il , ce1 = v ih , ce2 = v il , f = f max , i out = 0 ma ? 325 ? 325 ? 300 ? 300 ma standby power supply current i sb deselected, f = f max , zz v il ? 130 ? 110 ? 100 ? 90 ma i sb1 deselected, f = 0, zz 0.2v all v in 0.2v or v dd ? 0.2v ?30?30?30?30 i sb2 deselected, f = f max , zz v dd ? 0.2v all v in v il or v ih ?30?30?30?30 output voltage v ol i ol = 8 ma, v ddq = 3.465v ? 0.4 ? 0.4 ? 0.4 ? 0.4 v v oh i oh = ?4 ma, v ddq = 3.135v 2.4 ? 2.4 ? 2.4 ? 2.4 ? dc electrical characteristics for 2.5v i/o operation parameter symbol test conditions ?166 ?150 ?133 ?100 unit min max min max min max min max output leakage current |i lo | oe v ih , v dd = max, v out = gnd to v dd ?1 1 ?1 1 ?1 1 ?1 1 a output voltage v ol i ol = 2 ma, v ddq = 2.65v ? 0.7 ? 0.7 ? 0.7 ? 0.7 v v oh i oh = ?2 ma, v ddq = 2.35v 1.7 ? 1.7 ? 1.7 ? 1.7 ?
4/15/02; v.1.8 alliance semiconductor p. 8 of 14 as7c33256pfd32a as7c33256pfd36a ? timing characteristics over operating range parameter symbol ?166 ?150 ?133 ?100 unit notes 1 1 see ?notes? on page 12 min max min max min max min max clock frequency f max ? 166 ? 150 ? 133 ? 100 mhz cycle time (pipelined mode) t cyc 6 ? 6.6 ? 7.5 ? 10 ? ns cycle time (flow-through mode) t cycf 10 ? 10 ? 12 ? 12 ? ns clock access time (pipelined mode)- 3.3v vddq t cd 3.3v- 3.5 -3.8-4.0-5.0ns clock access time (pipelined mode)- 2.5v vddq t cd 2.5v- 4.0 -4.3-4.5-5.0ns clock access time (flow-through mode) t cdf ? 9 ?10?10?12ns output enable low to data valid t oe ? 3.5 ?3.8?4.0?5.0ns clock high to output low z t lzc 0 ? 0 ? 0 ? 0 ? ns 2,3,4 data output invalid from clock high t oh 1.5 ? 1.5 ? 1.5 ? 1.5 ? ns 2 output enable low to output low z t lzoe 0 ? 0 ? 0 ? 0 ? ns 2,3,4 output enable high to output high z t hzoe ? 3.5 ? 3.8 ? 4.0 ? 4.5 ns 2,3,4 clock high to output high z t hzc ? 3.5 ? 3.8 ? 4.0 ? 5.0 ns 2,3,4 output enable high to invalid output t ohoe 0 ? 0?0?0?ns clock high pulse width t ch 2.4 ? 2.5 ? 2.5 ? 3.5 ? ns 5 clock low pulse width t cl 2.4 ? 2.5 ? 2.5 ? 3.5 ? ns 5 address setup to clock high t as 1.5 ? 1.5 ? 1.5 ? 2.0 ? ns 6 data setup to clock high t ds 1.5 ? 1.5 ? 1.5 ? 2.0 ? ns 6 write setup to clock high t ws 1.5 ? 1.5 ? 1.5 ? 2.0 ? ns 6,7 chip select setup to clock high t css 1.5 ? 1.5 ? 1.5 ? 2.0 ? ns 6,8 address hold from clock high t ah 0.5 ? 0.5 ? 0.5 ? 0.5 ? ns 6 data hold from clock high t dh 0.5 ? 0.5 ? 0.5 ? 0.5 ? ns 6 write hold from clock high t wh 0.5 ? 0.5 ? 0.5 ? 0.5 ? ns 6,7 chip select hold from clock high t csh 0.5 ? 0.5 ? 0.5 ? 0.5 ? ns 6,8 adv setup to clock high t advs 1.5 ? 1.5 ? 1.5 ? 2.0 ? ns 6 adsp setup to clock high t adsps 1.5 ? 1.5 ? 1.5 ? 2.0 ? ns 6 adsc setup to clock high t adscs 1.5 ? 1.5 ? 1.5 ? 2.0 ? ns 6 adv hold from clock high t advh 0.5 ? 0.5 ? 0.5 ? 0.5 ? ns 6 adsp hold from clock high t adsph 0.5 ? 0.5 ? 0.5 ? 0.5 ? ns 6 adsc hold from clock high t adsch 0.5 ? 0.5 ? 0.5 ? 0.5 ? ns 6
4/15/02; v.1.8 alliance semiconductor p. 9 of 14 as7c33256pfd32a as7c33256pfd36a ? timing waveform of read cycle note: y = xor when lbo = high/no connect; y = add when lbo = low. bw[a:d] is don?t care. key to switching waveforms undefined/don?t care falling input rising input t cyc t ch t cl t adsps t adsph t as t ah t ws t advs t oh clk adsp adsc address gwe , bwe ce0 , ce2 adv oe d out t css t csh t cd t wh t advh t hzoe t adscs t adsch load new address adv inserts wait states q(a2y10) q(a2y11) q(a3) q(a2) q(a2y01) q(a3y01) q(a3y10) q(a1) a2 a1 a3 ce1 (pipelined mode) d out q(a2y10) q(a2y11) q(a3) q(a2y01) q(a3y01) q(a3y10) q(a3y11) q(a1) (flow-through mode) t hzc t oe t lzoe q(a3y11) t hzc
4/15/02; v.1.8 alliance semiconductor p. 10 of 14 as7c33256pfd32a as7c33256pfd36a ? timing waveform of write cycle note: y = xor when lbo = high/no connect; y = add when lbo = low. t cyc t cl t adsps t adsph t adscs t adsch t as t ah t ws t wh t css t advs t ds t dh clk adsp adsc address bwe ce0 , ce2 adv oe data in t csh t advh d(a2y01) d(a2y10) d(a3) d(a2) d(a2y01) d(a3y01) d(a3y10) d(a1) d(a2y11) adv suspends burst adsc loads new address a1 a2 a3 t ch ce1 bw[a:d]
4/15/02; v.1.8 alliance semiconductor p. 11 of 14 as7c33256pfd32a as7c33256pfd36a ? timing waveform of read/write cycle note: y = xor when lbo = high/no connect; y = add when lbo = low. t ch t cyc t cl t adsps t adsph t as t ah t ws t wh t advs t ds t dh t oh clk adsp address gwe ce0 , ce2 adv oe d in d out t lzc t advh t lzoe t oe t cd q(a1) q(a3y01) d(a2) q(a3) q(a3y10) q(a3y11) a1 a2 a3 ce1 t hzoe (pipeline mode) d out q(a1) q(a3y01) q(a3y10) (flow-through mode) t cdf q(a3y11)
4/15/02; v.1.8 alliance semiconductor p. 12 of 14 as7c33256pfd32a as7c33256pfd36a ? ac test conditions notes 1 for test conditions, see ac test conditions , figures a, b, c. 2 this parameter measured with outp ut load condition in figure c. 3 this parameter is sampled, but not 100% tested. 4t hzoe is less than t lzoe ; and t hzc is less than t lzc at any given temperature and voltage. 5 tch measured as high above vih and tcl measured as low below vil. 6 this is a synchronous device. all addresses must meet the specif ied setup and hold times for all rising edges of clk. all othe r synchronous inputs must meet the setup and hold times for all rising edges of clk when chip is enabled. 7 write refers to gwe , bwe , bw[a:d]. 8 chip select refers to ce0 , ce1, ce2 . 353 ?/1538? 5 pf* 319 ?/1667? d out gnd figure c: output load(b) *including scope and jig capacitance z 0 = 50 ? d out 50 ? figure b: output load (a) 30 pf* figure a: input waveform 10% 90% gnd 90% 10% +3.0v output load: see figure b, except for t lzc , t lzoe , t hzoe , t hzc , see figure c. input pulse level: gnd to 3v. see figure a. input rise and fall time (measured at 0.3v and 2.7v): 2 ns. see figure a. input and output timing reference levels: 1.5v. v l = 1.5v for 3.3v i/o; = v ddq /2 for 2.5v i/o thevenin equivalent: +3.3v for 3.3v i/o; /+2.5v for 2.5v i/o
4/15/02; v.1.8 alliance semiconductor p. 13 of 14 as7c33256pfd32a as7c33256pfd36a ? package dimensions 100-pin quad flat pack (tqfp) tqfp min max a1 0.05 0.15 a2 1.35 1.45 b 0.22 0.38 c 0.09 0.20 d 13.90 14.10 e 19.90 20.10 e 0.65 nominal hd 15.90 16.10 he 21.90 22.10 l 0.45 0.75 l1 1.00 nominal 0 7 dimensions in millimeters he e hd d b e a1 a2 l1 l c all measurements are in mm. min ty p max a -1.27- b 13.90 14.00 14.10 b1 -7.62- c 21.90 22.00 22.10 c1 - 20.32 - d 0.60 0.75 0.90 e --1.70 e1 -0.56- e2 0.50 0.60 0.70 119-ball bga (ball grid array)
? copyright alliance semiconductor corporation. all rights reserve d. our three-point logo, our name and intelliwatt are tradema rks or registered trademarks of alliance. all other brand and product names may be the trademarks of their respective companies. alliance reserves the right to make changes to this document and its products at any time without notice. alliance assumes no respons ibility for any errors that may appear in this document. the data contained herein represen ts alliance?s best data and/or estimates at the time of issuance. alliance reserves the right to change or correct this data at a ny time, without notice. if the product described herein is under development, significant changes to these specifications are possible. the information in this product data sheet is i ntended to be general descriptive information for pot ential customers and users, and is not intended to operate as, or provide, any guarantee or warrantee to any user or customer. alliance does not assume any responsibility or liab ility arising out of the application or use of a ny product described herein, and disclaims any express or implied warranties related to the sale and/or use of alliance products including lia bility or warranties related to fitness for a particular purpose, merchantability, or infringement of any intellectual property rights, except as express agreed to in alliance?s terms and conditions of sale (which are available fr om alliance). all sales of alliance product s are made exclusively according to alliance?s terms and conditions of sale. the purchase of products from alliance does not convey a licens e under any patent rights, copyrights, mask works rights, trademarks, or any oth er intellectual property rights of alliance or third par ties. alliance does not authorize its products for use as critical components in life-supporting systems where a malfunction or failure may reasona bly be expected to result i n significant injury to the user, and the inclusion of alliance products in such life-supporting systems implies that the manufacturer assumes all risk of such use and agrees to indemnify alliance against all claims arising from such use. 4/15/02; v.1.8 alliance semiconductor p. 14 of 14 as7c33256pfd32a as7c33256pfd36a ? 1.alliance semiconductor sram prefix 2.operating voltage: 33=3.3v 3.organization: 256=256k 4.pipeline-flowthrough (each device has both options) 5.deselect: d=dual cycle deselect 6.organization: 32=x32; 36=x36 7.production version: a=first production version 8. blank = the default:3 ce (chip enable), 2 = 2 ce (2 chip enable) 9.clock speed (mhz) 10.package type: tq=tqfp, b=bga 11.operating temperatur e: c=commercial ( 0 c to 70 c); i=industrial ( -40 c to 85 c) ordering information packages ?166 mhz ?150 mhz ?133 mhz ?100 mhz x32 tqfp as7c33256pfd32a- 166tqc as7c33256pfd32a- 150tqc as7c33256pfd32a- 133tqc as7c33256pfd32a- 100tqc x32 bga as7c33256pfd32a2- 166bc as7c33256pfd32a2- 150bc as7c33256pfd32a2- 133bc as7c33256pfd32a2- 100bc x32 tqfp as7c33256pfd32a- 166tqi as7c33256pfd32a- 150tqi as7c33256pfd32a- 133tqi as7c33256pfd32a- 100tqi x32 bga as7c33256pfd32a2- 166bi as7c33256pfd32a2- 150bi as7c33256pfd32a2- 133bi as7c33256pfd32a2- 100bi x36 tqfp as7c33256pfd36a- 166tqc as7c33256pfd36a- 150tqc as7c33256pfd36a- 133tqc as7c33256pfd36a- 100tqc x36 bga as7c33256pfd36a2- 166bc as7c33256pfd36a2- 150bc as7c33256pfd36a2- 133bc as7c33256pfd36a2- 100bc x36 tqfp as7c33256pfd36a- 166tqi as7c33256pfd36a- 150tqi as7c33256pfd36a- 133tqi as7c33256pfd36a- 100tqi x36 bga as7c33256pfd36a2- 166bi as7c33256pfd36a2- 150bi as7c33256pfd36a2- 133bi as7c33256pfd36a2- 100bi x32 tqfp (2 ce) as7c33256pfd32a2- 166tqc as7c33256pfd32a2- 150tqc as7c33256pfd32a2- 133tqc as7c33256pfd32a2- 100tqc x32 tqfp (2 ce) as7c33256pfd32a2- 166tqi as7c33256pfd32a2- 150tqi as7c33256pfd32a2- 133tqi as7c33256pfd32a2- 100tqi x36 tqfp (2 ce) as7c33256pfd36a2- 166tqc as7c33256pfd36a2- 150tqc as7c33256pfd36a2- 133tqc as7c33256pfd36a2- 100tqc x36 tqfp (2 ce) as7c33256pfd36a2- 166tqi as7c33256pfd36a2- 150tqi as7c33256pfd36a2- 133tqi as7c33256pfd36a2- 100tqi part numbering guide as7c 33 256 pf d 32/36 a blank or 2 ?xxx tq or b c/i 1 23 4 5 67 8 910 11

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