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hcpl-5120, hcpl-5121 and 5962-04204 2.0fampfoutputfcurrentfigbtfgatefdrivef f hermeticallyfsealedfoptocoupler data sheet description the hcpl-5 20 contains a gaasp led optically coupled to an integrated circuit with a power output stage. the device is ideally suited for driving power igbts and mosfets used in motor control inverter applications. the high operating voltage range of the output stage provides the drive voltages required by gate controlled devices. the voltage and current supplied by this opto - coupler makes it ideally suited for directly driving igbts with ratings up to 200 v/ 00 a. for igbts with higher ratings, the hcpl-5 20 can be used to drive a discrete power stage, which drives the igbt gate. the products are capable of operation and storage over the full military temperature range and can be purchased as either commercial products, with full mil-prf-38534 class h testing, or from defense supply center columbus (dscc) standard microcircuit drawing (smd) 5962-04204. all devices are manufactured and tested on a mil-prf-38534 certifed line and are includ - ed in the dscc qualifed manufacturers list, qml-38534 for hybrid microcircuits. schematic diagram applications ? industrial and military environments ? high reliability systems high reliability systems ? harsh industrial environments harsh industrial environments ? transportation, medical, and life critical systems transportation, medical, and life critical systems ? ? ninterruptible power supplies (?ps) ? ninterruptible power supplies (?ps) ? isolated igbt/mosfet gate drive isolated igbt/mosfet gate drive ? ac and brushless dc motor drives ac and brushless dc motor drives ? industrial inverters industrial inverters ? switch mode power supplies (smps) switch mode power supplies (smps) features ? performance guaranteed over full military performance guaranteed over full military temperature range: -55 c to + 25 c ? manufactured and tested on a mil-prf-38534 certifed line ? hermetically sealed packages ? dual marked with device part number and dscc drawing number qml-38534 ? hcpl-3 20 function compatibility ? 2.0 a minimum peak output current ? 0.5v maximum low level output voltage (v ol ) : eliminates need for negative gate drive ? 0 kv/ s minimum common mode rejection (cmr) at v cm = 000v ? i cc = 5 ma maximum supply current ? ? nder voltage lock-out protection (? vlo) with hysteresis ? wide operating v cc range: 5 to 30 volts ? 500 ns maximum propagation delay ? 0.35 s maximun delay between devices caution: it is advised that normal static precautions be taken in handling and assembly of this component to prevent damage and/or degradation which may be induced by esd. 1 3 shield 2 4 8 6 7 5 n/c cathode anode n/c v cc v o v o v ee
2 led v cc - v ee v cc - v ee v o positive going (i.e., turn-on) negative going (i.e., turn-off) off 0f-f30fv 0f-f30fv low on 0f-f11fv 0f-f9.5fv low on 11f-f13.5fv 9.5f-f12fv transition on 13.5f-f30fv 12f-f30fv high a 0. f bypass capacitor must be connected between pins 5 and 8. truth table avago technologies part number and options commercial hcpl-5120 mil-prf-38534,fclassfh hcpl-5121 standardfleadffinish goldfplate solderfdippedf* optionf-f200 buttfcut/goldfplate optionf-f100 gullfwing/solderedf* optionf-f300 smd part number prescriptfforfallfbelow 5962- eitherfgoldforfsolder 0420401hpx goldfplate 0420401hpc solderfdippedf* 0420401hpa buttfcut/goldfplate 0420401hyc buttfcut/solderedf* 0420401hya gullfwing/solderedf* 0420401hxa selection guide: lead confguration options device marking compliance indicator,* date code, suffix (if needed) a hcpl-512x 5962-04204 01hxx 50434 country of mfr. avago cage code* avago designator dscc smd* pin one/ esd ident avago p/n dscc smd* * qualified parts only sgp qyywwz outline drawing 3.81 (0.150) min. 4.32 (0.170) max. 9.40 (0.370) 9.91 (0.390) 0.51 (0.020) max. 2.29 (0.090) 2.79 (0.110) 0.51 (0.020) min. 0.76 (0.030) 1.27 (0.050) 8.13 (0.320) max. 7.36 (0.290) 7.87 (0.310) 0.20 (0.008) 0.33 (0.013) 7.16 (0.282) 7.57 (0.298) note: dimensions in millimeters (inches). * solder contains lead
3 option description 100 surfacefmountablefhermeticfoptocouplerfwithfleadsftrimmedfforfbuttfjointfassembly.fthisfoptionfisfavailablefonfcommercialfandfhi-relf productf(seefdrawingsfbelowfforfdetails). 200 leadffnishfisfsolderfdippedfratherfthanfgoldfplated.fthisfoptionfisfavailablefonfcommercialfandfhi-relfproduct.fdsccfdrawingfpartfnumbersf containfprovisionsfforfleadffnish. 300 surfacefmountablefhermeticfoptocouplerfwithfleadsfcutfandfbentfforfgullfwingfassembly.fthisfoptionfisfavailablefonfcommercialfandfhi-relf productf(seefdrawingsfbelowfforfdetails).fthisfoptionfhasfsolderfdippedfleads. 1.14 (0.045) 1.40 (0.055) 4.32 (0.170) max. 0.51 (0.020) max. 2.29 (0.090) 2.79 (0.110) 0.51 (0.020) min. 7.36 (0.290) 7.87 (0.310) 0.20 (0.008) 0.33 (0.013) note: dimensions in millimeters (inches). 0.51 (0.020) min. 4.57 (0.180) max. 0.51 (0.020) max. 2.29 (0.090) 2.79 (0.110) 1.40 (0.055) 1.65 (0.065) 9.65 (0.380) 9.91 (0.390) 5 max. 4.57 (0.180) max. 0.20 (0.008) 0.33 (0.013) note: dimensions in millimeters (inches). hermetic optocoupler options * solder contains lead
4 parameter symbol min. max. units note storageftemperature t s -65 +150 c operatingftemperature t a -55 +125 c caseftemperature t c +145 c junctionftemperature t j +150 c leadfsolderftemperature 260fforf10s c averagefinputfcurrent i ffavg 25 ma 1 peakftransientfinputfcurrentf (<1f sfpulsefwidth,f300fpps) i ffpk 1.0 a reversefinputfvoltage v r 5 v highfpeakfoutputfcurrent i ohf(peak) 2.5 a 2 lowfpeakfoutputfcurrent i olf(peak) 2.5 a 2 supplyfvoltage (v cc -v ee ) 0 35 v outputfvoltage v of(peak) 0 vcc v emitterfpowerfdissipation p e 45 mw 1 outputfpowerfdissipation p o 250 mw 3 totalfpowerfdissipation p t 295 mw 4 notes: . no derating required for typical case-to-ambient thermal resistance ( ca =40 c/w). refer to figure 35. 2. maximum pulse width = 0 s, maximum duty cycle = 0.2%. this value is intended to allow for component tolerances for designs with i o peak minimum = 2.0a. see applications section for additional details on limiting i oh peak. 3. derate linearly above 02 c free air temperature at a rate of 6mw/ c for typical case-to-ambient thermal resistance ( ca =40 c/w). refer to figure 36. 4. derate linearly above 02 c free air temperature at a rate of 6mw/ c for typical case-to-ambient thermal resistance ( ca =40 c/w). refer to figure 35 and 36. absolute maximum ratings mil-std-883, method 30 5 ( ), class esd classifcation recommended operating conditions parameter symbol min. max. units powerfsupplyfvoltage (v ccf Cfv ee ) 15 30 volts inputfcurrentf(on) i ff(on) 10 18 ma inputfvoltagef(off) v ff(off) -3.0 0.8 volts operatingftemperature t a -55 125 c
5 parameter symbol test conditions group a subgroups (13) limits units fig note min. typ. * max. highflevelf outputffcurrent i oh v o f=f(v cc f-f4fv) 1,f2,f3 0.5 1.5 a 2,f3,f17 2 v o f=f(vccf-f15fv) 2.0 a 1 lowflevelf outputffcurrent i ol v o f=f(v ee f+f2.5fv) 1,f2,f3 0.5 2.0 a 5,f6,f18 2 v o f=f(v ee f+f15fv) 2.0 a 1 highflevelf outputfvoltage v oh i o f=f-100fma 1,f2,f3 f(v cc f-f4) (v cc f-f3) v 1,f3,f19 3,f4 lowflevelf outputfvoltage v ol i o f=f100fma 1,f2,f3 0.1 0.5 v 4,f6,f20 highflevel supplyfcurrent i cch outputfopen,f i f f=f10ftof18fma 1,f2,f3 2.5 5.0 ma 7,f8 lowflevelf supplyfcurrent i ccl outputfopen,f v f f=f-3.0ftof+0.8v 1,f2,f3 2.5 5.0 ma thresholdfinputf f currentflowftofhigh i flh i o f=f0fma,f v o f>f5fv 1,f2,f3 3.5 9.0 ma 9,f15,f21 thresholdfinputf f voltagefhighftoflow v fhl 1,f2,f3 f0.8 v inputfforwardf voltage v f i f f=f10fma 1,f2,f3 f1.2 1.5 1.8 v 16 temperaturefcoefcientf offforwardffvoltage d v f / d t a i f f=f10fma -1.6 mv/ c inputfreversef f breakdownfvoltage bv r i r f=f10f a 1,f2,f3 f5 v inputf capacitance c in ff=f1fmhz,fv f f=f0fv 80 pf uvlofthreshold v uvlo+ v o f>f5fv,f i f f=f10fma 1,f2,f3 11.0 12.3 13.5 v 22,f37 v uvlo- 1,f2,f3 f9.5 10.7 12.0 uvlofhysteresis uvlo hys 1.6 electrical specifcations (dc) over recommended operating conditions (t a = -55 to + 25 c, i f(on) = 0 to 8 ma, v f(off) = -3.0 to 0.8v, v cc = 5 to 30 v, v ee = ground), unless otherwise specifed. *all typical values at t a = 25 c and v cc - v ee = 30 v, unless otherwise noted.
6 switching specifcations (ac) over recommended operating conditions (t a = -55 to + 25 c, i f(on) = 0 to 8 ma, v f(off) = -3.0 to 0.8v, v cc = 5 to 30 v, v ee = ground), unless otherwise specifed. parameter symbol test conditions group a subgroups (13) limits units fig note min. typ. * max. propagationfdelayftimef f tofhighfoutputflevel t plh rgf=f10f ? ,f cgf=f10fnf,ffff=f10fkhz,f dutyfcyclef=f50% 9,f10,f11 0.10 0.30 0.50 s 10,f11,f 12,f13,f 14,f23 11 propagationfdelayftimef f toflowfoutputflevel t phl 9,f10,f11 0.10 0.30 0.50 s pulsefwidthfdistortion pwd 9,f10,f11 0.3 s 12 propagationfdelayfdiferencef betweenfanyftwofparts pdd (t phl f-ft plh ) 9,f10,f11 -0.35 0.35 s 33,f34 7 riseftime t r 0.1 s 23 fallftime t f 0.1 s uvlofturnfonfdelay t uvlofon v o f>f5fv,ffi f f=f10fma 0.8 s 22 uvlofturnfoffdelay t uvlofoff v o f package characteristics over recommended operating conditions (t a = -55 to + 25 c) unless otherwise specifed. parameter symbol test conditions group a subgroups (13) limits units fig note min. typ.* max. input-outputf leakageffcurrent i i-o v i-o f=f1500vdc,frhf f65%,f tf=f5fsec.,ft a f=f25 c 1 1.0 a 5,f6 resistancef (input-output) r i-o v i-o f=f500fv dc 10 10 ? 6 capacitancef (input-output) c i-o ff=f1fmhz 2.5 pf 6 *all typicals at t a = 25 c. notes: . maximum pulse width = 0 s, maximum duty cycle = 0.2%. this value is intended to allow for component tolerances for designs with i o peak minimum = 2.0 a. see applications section for additional details on limiting i oh peak. 2. maximum pulse width = 50 s, maximum duty cycle = 0.5%. 3. in this test v oh is measured with a dc load current. when driving capacitive loads v oh will approach v cc as i oh approaches zero amps. 4. maximum pulse width = ms, maximum duty cycle = 20%. 5. this is a momentary withstand test, not an operating condition. 6. device considered a two-terminal device: pins on input side shorted together and pins on output side shorted together. . the diference between t phl and t plh between any two hcpl-5 20 parts under the same test condition. 8. pins and 4 need to be connected to led common. 9. common mode transient immunity in the high state is the maximum tolerable dv cm /dt of the common mode pulse, v cm , to assure that the output will remain in the high state (i.e., v o > 5.0 v). 0. common mode transient immunity in a low state is the maximum tolerable dv cm /dt of the common mode pulse, v cm , to assure that the output will remain in a low state (i.e., v o < .0 v). . this load condition approximates the gate load of a 200 v/ 5a igbt. 2. pulse width distortion (pwd) is defned as |t phl -t plh | for any given device. 3. standard parts receive 00% testing at 25 c (subgroups and 9). smd and class h parts receive 00% testing at 25, 25, and -55 c (sub groups and 9, 2 and 0, 3 and , respectively). 4. parameters are tested as part of device initial characterization and after design and process changes. parameters are guaranteed to limits specifed for all lots not specifcally tested.
8 i f = 10ma to 18m a i out = -100m a v cc = 15 to 30v v ee = 0v 4 3 2 1 0 (v oh - v cc ) - high ou tp ut voltage dr op - v -5 5 - 35 -1 5 5 25 45 65 85 105 125 t a - te m per at ure - o c i oh - output high curr ent - a i f = 10ma to 18m a v out = (v cc - 4v) v cc = 15 to 30v v ee = 0v t a - te m per at ure - o c 1. 4 1. 6 1. 8 2. 0 2. 2 2. 4 -5 5 - 35 -1 5 5 25 45 65 85 105 125 -6 -5 -4 -3 -2 -1 0. 0 0 .5 1. 0 1 .5 2. 0 2 .5 i oh - ou tp ut high current - a (v oh - v cc ) - output high voltage dro p - v i f = 10 to 18m a v cc = 15 to 30v v ee = 0v 125 o c 25 o c -5 o c 0.00 0.05 0.10 0.15 0.20 0.25 0.30 -55 -35 -15 5 2 5 4 5 6 5 8 5 105 125 t a - temperature - o c v ol - output low voltage - v v f(off) = -3.0 to 0.8v i out = 100ma v cc = 15 to 30v v ee = 0v 0 1 2 3 4 -3 5 5 25 4 5 6 5 8 5 10 5 1 25 t a - temperature - o c i low - output low current - a -5 5 -1 5 v f(off) = -3.0 to 0.8v v out = 2.5v v cc = 15 to 30v v ee = 0v 0 1 2 3 4 5 6 7 8 0. 0 0. 5 1 .0 1. 5 2 .0 2. 5 i ol - ou tp ut lo w current - a v ol - ou tp ut lo w vo lta ge - v v f(off) = -3 .0 to 0. 8v v cc = 15 to 30v v ee = 0v 125 o c 25 o c -5 o c 1. 5 2. 0 2. 5 3. 0 3. 5 4. 0 -5 5 - 35 -1 5 5 25 45 65 85 105 125 t a - tem per at ure - o c i cc - supply current - ma v cc = 30v v ee = 0v i f = 10ma for i cch i f = 0ma for i ccl i cch i ccl 1. 5 2. 0 2. 5 3. 0 3. 5 4. 0 15 20 25 30 v cc - suppl y vo lta ge - v i cc - supply current - ma i f = 10ma for i cch i f = 0ma for i ccl t a = 25 o c v ee = 0v i cch i ccl 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 -55 -35 5 2 5 4 5 6 5 8 5 125 -15 105 t a - temperature - o c i flh - low to high current threshold - ma v cc = 15 to 30v v ee = 0v output = open figure 1. v oh vs. temperature figure 2. i oh vs. temperature figure 3. v oh vs. i oh figure 4. v ol vs. temperature figure 5. i ol vs. temperature figure 6. v ol vs. i ol figure 7. i cc vs. temperature figure 8. i cc vs. v cc figure 9. i flh vs. temperature
9 100 200 300 400 500 15 20 25 30 v cc - suppl y vo lta ge - v t p - pr op ag at io n de la y - ns i f = 10m a v cc = 30v, v ee = 0v rg = 10 ? , cg = 10 nf duty cycle = 50% t a = 25 o c, f = 10khz t pl h t ph l 100 200 300 400 500 6 8 10 12 14 16 18 20 22 24 26 i f - fo rw a rd le d current - ma t p - pr op ag at ion de la y - ns v cc = 30v, v ee = 0v rg = 10 ? , cg = 10 nf t a = 25 o c duty cycle = 50% f = 10khz t pl h t ph l 100 200 300 400 500 -5 5 - 35 -1 5 5 25 45 65 85 105 125 t a - tem per at ure - o c t p - pr op ag at io n de la y- ns i f = 10m a v cc = 30v, v ee = 0v rg = 10 ? , cg = 10 nf duty cycle = 50% f = 10khz t pl h t ph l 0 1 0 2 0 3 0 4 0 5 0 100 200 300 400 500 tp - pr op ag at ion de la y -n s rg - seri es lo ad r esi st a nce - ? v cc = 30v, v ee = 0v t a = 25 o c, i f = 10m a cg = 10 nf duty cycle = 50% f = 10khz t pl h t ph l cg - lo ad ca pa ci ta nce - nf t p - pr op ag at ion de la y -n s 100 200 300 400 500 0 2 0 4 0 6 0 8 0 100 t pl h t ph l v cc = 30v, v ee = 0v t a = 25 o c, i f = 10m a rg = 10 ? duty cycle = 50% f = 10khz 0 5 10 15 20 25 30 0 1 2 3 4 5 i f - forward led current - ma v o - output voltage - v t a = 25 o c 0.001 0.01 0.1 1 10 100 1000 1.20 1.30 1.40 1.50 1.60 v f - forward voltage - v 1.10 i f - forward current - ma t a = 25 o c figure 10. propagation delay vs. v cc figure 11. propagation delay vs. i f figure 12. propagation delay vs. temperature figure 13. propagation delay vs. rg figure 14. propagation delay vs. cg figure 15. transfer characteristics figure 16. input current vs. forward voltage
0 0.1 f v cc = 15 to 30 v 1 3 + 2 4 8 6 7 5 + 4 v i oh i f = 10 to 18 ma _ _ 0.1 f v cc = 15 to 30 v 1 3 + 2 4 8 6 7 5 2.5 v i ol + _ _ 0.1 f v cc = 15 to 30 v 1 3 i f = 10 to 18 ma + 2 4 8 6 7 5 100 ma v oh _ 0.1 f v cc = 15 to 30 v 1 3 + 2 4 8 6 7 5 100 ma v ol _ 0.1 f v cc = 15 to 30 v 1 3 i f + 2 4 8 6 7 5 v o > 5 v _ 0.1 f v cc 1 3 i f = 10 ma + 2 4 8 6 7 5 v o > 5 v _ figure 17. i oh test circuit figure 18. i ol test circuit figure 19. v oh test circuit figure 20. v ol test circuit figure 21. i flh test circuit figure 22. uvlo test circuit
0.1 f v cc = 15 to 30 v 10 ? 1 3 i f = 10 to 18 ma v o + + 2 4 8 6 7 5 10 khz 50% duty cycle 500 ? 10 nf i f v out t phl t plh t f t r 10% 50% 90% t r = t f < 10 ns _ _ _ 0.1 f v cc = 30 v 1 3 i f v o + + 2 4 8 6 7 5 a + b v cm = 1000 v 5 v v cm ? t 0 v v o switch at b: i f = 0 ma v o switch at a: i f = 10 ma v ol v oh ? t v cm v t = _ _ _ figure 23. t plh , t phl , and t f test circuit and waveforms figure 24. cmr test circuit and waveforms
2 applications information eliminating negative igbt gate drive to keep the igbt frmly of, the hcpl-5 20 has a very low maximum v ol specifcation of 0.5 v. the hcpl-5 20 realizes this very low v ol by using a dmos transistor with ? (typical) on resistance in its pull down circuit. when the hcpl-5 20 is in the low state, the igbt gate is shorted to the emitter by r g + ? . minimizing rg and the lead inductance from the hcpl-5 20 to the igbt gate and emitter (possibly by mounting the hcpl-5 20 on a small pc board directly above the igbt) can elimi - nate the need for negative igbt gate drive in many ap - plications as shown in figure 25. care should be taken with such a pc board design to avoid routing the igbt collector or emitter traces close to the hcpl-5 20 input as this can result in unwanted coupling of transient sig - nals into the hcpl-5 20 and degrade performance. (if the igbt drain must be routed near the hcpl-5 20 in - put, then the led should be reverse-biased when in the of state, to prevent the transient signals coupled from the igbt drain from turning on the hcpl-5 20.) selecting the gate resistor (r g ) to minimize igbt switching losses. step 1: calculate r g minimum from the i ol peak spec - ifcation. the igbt and r g in figure 26 can be analyzed as a simple rc circuit with a voltage supplied by the hcpl-5 20. (v cc - v ee - v ol ) r g = CCCCCCCCCCCCCCCCC i olpeak (v cc C v ee C 2v) = CCCCCCCCCCCCCCCCCC i olpeak (15 v + 5 v C 2v) = CCCCCCCCCCCCCCCCCCC 2.5 a = 7.2 ? 8 ? the v ol value of 2 v in the previous equation is a con - servative value of v ol at the peak current of 2.5a (see figure 6). at lower rg values the voltage supplied by the hcpl-5 20 is not an ideal voltage step. this results in lower peak currents (more margin) than predicted by this analysis. when negative gate drive is not used v ee in the previous equation is equal to zero volts step 2: check the hcpl-5120 power dissipation and increase r g if necessary. the hcpl-5 20 total power dissipation (p t ) is equal to the sum of the emitter power (p e ) and the output power (p o ): p t = p e + p o p e = i f ? v f ? duty cycle p o = p o(bias) + p o (switching) = i cc ? (v cc - v ee ) + esw(r g , q g ) ? f for the circuit in figure 26 with i f (worst case) = 8 ma, r g = 8 ? , max duty cycle = 80%, q g = 500 nc, f = 20 khz and t a max = 25 c: p e = 18 ma ? 1.8 v ? 0.8 = 26 mw p o = 4.25 ma ? 20 v + 1.0 j ? 20 khz = 85 mw + 20 mw = 105 mw < 112 mw (p o(max) @ 125 c = 250 mw - 23 c ? 6 mw/ c) the value of 4.25 ma for i cc in the previous equation was obtained by derating the i cc max of 5 ma (which occurs at -55 c) to i cc max at 25 c. since p o for this case is less than p o(max) , r g of 8 ? is ap - propriate. + hvdc 3-phase ac - hvdc 0.1 f v cc = 18 v 1 3 + 2 4 8 6 7 5 270 ? control input rg q1 q2 74xxx open collector _ +5 v figure 25. recommended led drive and application circuit
3 + hvdc 3-phase ac - hvdc 0.1 f v cc = 15 v 1 3 + 2 4 8 6 7 5 rg q1 q2 v ee = -5 v + 270 ? +5 v control input 74xxx ope n collecto r _ _ figure 26. typical application circuit with negative igbt gate drive p e parameter description i f ledfcurrent v f ledfonfvoltage dutyfcycle maximumfledf dutyfcycle p o parameter description i cc supplyfcurrent v cc positivefsupplyfvoltage v ee negativefsupplyfvoltage e sw f(rg,fqg) energyfdissipationfinfthefhcpl-5120fforfeachf igbtfswitchingfcyclef(seeffiguref27) f switchingffrequency led drive circuit considerations for ultra high cmr perfor - mance. without a detector shield, the dominant cause of op - tocoupler cmr failure is capacitive coupling from the input side of the optocoupler, through the package, to the detector ic as shown in figure 28. the hcpl-5 20 improves cmr performance by using a detector ic with an optically transparent faraday shield, which diverts the capacitively coupled current away from the sensitive ic circuitry. however, this shield does not eliminate the capacitive coupling between the led and optocoupler pins 5-8 as shown in figure 29. this capacitive coupling causes perturbations in the led current during common mode transients and becomes the major source of cmr failures for a shielded optocoupler. the main design ob - jective of a high cmr led drive circuit becomes keeping the led in the proper state (on or of ) during common mode transients. for example, the recommended ap - plication circuit (figure 25), can achieve 0 kv/ s cmr while minimizing component complexity. techniques to keep the led in the proper state are discussed in the next two sections. esw - energy per switching cycle - j 0 0 rg - gate resistance - ? 100 3 20 7 40 2 60 80 6 qg = 100 nc qg = 250 nc qg = 500 nc 5 4 1 v cc = 19 v v ee = -9 v 1 3 2 4 8 6 7 5 c ledp c ledn 1 3 2 4 8 6 7 5 c ledp c ledn shield c ledo1 c ledo2 figure 27. energy dissipated in the hcpl-5120 for each igbt switching cycle figure 28. optocoupler input to output capacitance model for unshielded optocouplers. figure 29. optocoupler input to output capacitance model for shielded optocouplers.
4 cmr with the led on (cmr h ). a high cmr led drive circuit must keep the led on dur - ing common mode transients. this is achieved by over - driving the led current beyond the input threshold so that it is not pulled below the threshold during a tran - sient. a minimum led current of 0 ma provides ade - quate margin over the maximum i flh of ma to achieve 0 kv/ s cmr. rg 1 3 v sat 2 4 8 6 7 5 + v cm i ledp c ledp c ledn shield * the arrows indicate the direction of current flow during ? dv cm /dt +5 v + v cc = 18 v * * * 0.1 f + _ _ * * * _ 1 3 2 4 8 6 7 5 c ledp c ledn shield +5 v q1 i ledn 1 3 2 4 8 6 7 5 c ledp c ledn shield +5 v figure 30. equivalent circuit for figure 25 during common mode transient. figure 31. not recommended open collector drive circuit figure 32. recommended led drive circuit for ultra-high cmr cmr with the led of (cmr l ). a high cmr led drive circuit must keep the led of (v f v f(off) ) during common mode transients. for example, during a -dv cm /dt transient in figure 30, the current fow - ing through c ledp also fows through the r sat and v sat of the logic gate. as long as the low state voltage devel - oped across the logic gate is less than v f(off) , the led will remain of and no common mode failure will occur. the open collector drive circuit, shown in figure 3 , can - not keep the led of during a +dv cm /dt transient, since all the current fowing through c ledn must be supplied by the led, and it is not recommended for applications requiring ultra high cmr l performance. figure 32 is an alternative drive circuit which, like the recommended application circuit (figure 25), does achieve ultra high cmr performance by shunting the led in the of state.
5 ipm dead time and propagation delay specifcations. the hcpl-5 20 includes a propagation delay diference (pdd) specifcation intended to help designers mini - mize dead time in their power inverter designs. dead time is the time period during which both the high and low side power transistors (q and q2 in figure 25) are of. any overlap in q and q2 conduction will result in large currents fowing through the power devices be - tween the high and low voltage motor rail. to minimize dead time in a given design, the turn on of led2 should be delayed (relative to the turn of of led ) so that under worst-case conditions, transistor q has just turned of when transistor q2 turns on, as shown in figure 33. the amount of delay necessary to achieve this conditions is equal to the maximum value of the propa - gation delay diference specifcation, pdd max , which is specifed to be 350 ns over the operating temperature range of -55 c to 25 c. delaying the led signal by the maximum propagation delay diference ensures that the minimum dead time is zero, but it does not tell a designer what the maximum dead time will be. the maximum dead time is equivalent to the diference between the maximum and minimum propagation delay diference specifcations as shown in figure 34. the maximum dead time for the hcpl-5 20 is 00 ns (= 350 ns - (-350 ns)) over an operating tempera - ture range of -55 c to 25 c. note that the propagation delays used to calculate pdd and dead time are taken at equal temperatures and test conditions since the optocouplers under consideration are typically mounted in close proximity to each other and are switching identical igbts. pdd* max = (t phl - t pl h ) max = t phl max - t plh mi n *pdd = propagation delay difference note: for pdd calculations the propagation delays are taken at the same temperature and test conditions. v out1 i led2 v out2 i led1 q1 on q2 off q1 of f q2 on t phl max t plh mi n maximum dead tim e (due to optocoupler) = (t phl max - t phl mi n ) + (t plh max - t plh mi n ) = (t phl max - t plh mi n ) - (t phl mi n - t plh max ) = pdd* max - pdd* mi n *pdd = propagation delay difference note: for dead time and pdd calculations all propagation delays are taken at the same temperature and test conditions. v out 1 i led 2 v out 2 i led 1 q1 on q2 off q1 off q2 on t phl max t phl mi n t plh mi n t plh max (t phl - t pl h ) max = pdd* max -5 5 - 25 5 3 5 9 5 1 25 p e - input power - mw 65 t a - ambient temperature - o c 50 30 20 10 0 40 = 70 o c/w = 140 o c/w = 210 o c/w case-to-ambient thermal resistance 0 50 10 0 15 0 20 0 25 0 30 0 -5 5 - 25 5 3 5 6 5 9 5 1 25 p o - output power - mw t a - ambient temperature - o c = 70 o c/w = 140 o c/w = 210 o c/w case-to-ambient thermal resistance figure 33. minimum led skew for zero dead time figure 34. waveforms for dead time calculations figure 35. input thermal derating curve, dependence of case-to-ambient thermal resistance figure 36. output thermal derating curve, dependence of case-to-ambient thermal resistance
forfproductfinformationfandfafcompleteflistfoffdistributors,fpleasefgoftofourfwebfsite:f www.avagotech.com avago,favagoftechnologies,fandfthefaflogofareftrademarksfoffavagoftechnologies,flimitedfinfthefunitedfstatesfandfotherfcountries. datafsubjectftofchange.fcopyrightf?f2006favagoftechnologiesflimited.fallfrightsfreserved. 5989-0942enf-faprilf4,f2007 under voltage lockout feature. the hcpl-5 20 contains an under voltage lockout (? vlo) feature that is designed to protect the igbt un - der fault conditions which cause the hcpl-5 20 supply voltage (equivalent to the fully-charged igbt gate volt - age) to drop below a level necessary to keep the igbt in a low resistance state. when the hcpl-5 20 output is in the high state and the supply voltage drops below the hcpl-5 20 v ? vloC threshold (9.5 < v ? vloC < 2.0) the opto - coupler output will go into the low state with a typical delay, ? vlo turn of delay, of 0.6 s. when the hcpl-5 20 output is in the low state and the supply voltage rises above the hcpl-5 20 v ? vlo+ thresh - old ( .0 < v ? vlo+ < 3.5) the optocoupler output will go into the high state (assuming led is on) with a typical delay, ? vlo turn on delay of 0.8 s. figure 37. under voltage lock out mil-prf-38534 class h and dscc smd test program avago technologies hi-rel optocouplers are in compli - ance with mil-prf-38534 class h. class h devices are also in compliance with dscc drawing 5962-04204. testing consists of 00% screening and quality confor - mance inspection to mil-prf-38534. v o - output voltage - v 0 0 (v cc - v ee ) - supply voltage - v 10 5 14 10 15 2 20 6 8 4 12 (12.3, 10.8) (10.7, 9.2) (10.7, 0.1) (12.3, 0.1)

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