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1 zarlink semiconductor inc. zarlink, zl and the zarlink semiconductor logo are trademarks of zarlink semiconductor inc. copyright 2002-2006, zarlink semiconductor inc. all rights reserved. features ? combined t1/e1/j1 framer and liu, with pll and 3 hdlcs ? in t1/j1 mode the liu can recover signals attenuated by up to 36 db (at 772 khz) ? in e1 mode the liu can recover signals attenuated by up to 40 db (at 1.024 mhz) ? low jitter digital pll (intrinsic jitter < 0.02ui) ? hdlcs can be assigned to any timeslot ? comprehensive alarm detection, performance monitoring and error insertion functions ? 2.048 mbit/s or 8.192 mbit/s st-bus streams ? support for inverse mux for atm (ima) ? support for v5.1 and v5.2 access networks ? 3.3 v operation with 5 v tolerant inputs ? intel or motorola non-multiplexed 8-bit microprocessor port ? jtag boundary scan applications ? t1/e1/j1 add/drop multiplexers ? access networks ? wireless base stations ? co and cpe equipment interfaces ? primary rate isdn nodes ? digital cross-connect systems (dcs) june 2006 ordering information mt9076bp 68 pin plcc tubes mt9076bb 80 pin lqfp trays mt9076bpr 68 pin plcc tape & reel mt9076bpr1 68 pin plcc* tape & reel mt9076bb1 80 pin lqfp* trays mt9076bp1 68 pin plcc* tubes *pb free matte tin -40 c to +85 c mt9076b t1/e1/j1 3.3 v single chip transceiver data sheet figure 1 - mt9076 functional block st-bus interface cas buffer st loop pl loop national dg loop alarm detection, 2 frame slip buffer st-bus interface microprocessor interface txao txb txa line driver ttip pulse generator clock,data recovery rx equalizer & data slicer osc1 osc2 rtip bs/ls csti dsti csto dsto exclk rring tring bit buffer f0b c4b rxmf /txfp los txmf transmit framing, error, test signal generation and slip buffer data link, hdlc0 hdlc1 receive framing, performance monitoring, rxdlclk rxdl txdl txdlclk r/w /wr cs ds /rd irq d7~d0 ac0 rxfp jitter attenuator & clock control ac4 rm loop mt loop tdi tdo tms tclk trst ieee 1149.1 s/fr
mt9076b data sheet 2 zarlink semiconductor inc. description the mt9076 is a highly featured single chip solution for term inating t1/e1/j1 trunks. it contains a long-haul liu, an advanced framer, a high performance pll and 3 hdlcs. in t1 mode, the mt9076 supports d4, esf and slc-96 fo rmats meeting the latest recommendations including at&t pub43801, tr-62411; ansi t1.102, t1.403 and t1.408; telcordia gr-303-core. in e1 mode, the mt9076 supports the latest itu-t re commendations including g.703, g.704, g.706, g.732, g.775, g.796, g.823, g.964 (v5.1), g.965 (v5.2) and i.431. it also supports etsi ets 300 011, ets 300 166, ets 300 233, ets 300 324 (v5.1) and ets 300 347 (v5.2).
mt9076b data sheet 3 zarlink semiconductor inc. figure 2 - pin connections 40 42 44 46 48 50 52 54 56 58 60 22 24 26 28 30 34 36 38 32 62 80 78 76 74 72 68 66 64 70 20 18 16 14 12 10 8 6 4 2 txao tc lk tms tdo tdi gndatx f0b c4b exclk nc tring ttip vddatx vdd2 vss2 ic1 rxfp nc trst nc bs/ls ac2 ac1 rxdl rxdlck txb txa vss1 vdd1 vdarx rtip rxmf /txfp txmf nc ac3 ac4 nc gndarx rring nc nc nc cs reset irq d0 d1 d2 d3 vss5 int/mot d6 r/w /wr ic4 vdd5 d4 d5 d7 nc ac0 60 txao cs 28 30 32 34 36 38 40 42 8 6 4 2 68 66 64 62 58 56 54 52 50 48 46 44 trst tclk tms tdo tdi gndatx tring ttip vddatx vdd2 rxfp f0b vss2 ic1 exclk reset irq d0 d1 d2 d3 vss5 ic4 int/mot vdd5 d4 d5 d6 d7 r/w /wr ac0 ds /rd dsti csti csto s/ fr /exclki dsto osc2 osc1 vss3 vdd3 txdl txdlck ic3 ic2 vss4 vdd4 los ac1 ac2 ac3 ac4 gndarx rtip rring vddarx bs/ ls txmf txa txb rxdclk rxdl rxmf /txfp vss1 10 12 14 16 18 20 22 24 26 c4b vdd1 nc tcdlck txdl s/ fr /exclki vdd3 vss3 osc1 osc2 vss4 vdd4 csto csti dsto dsti ds /rd nc nc ic3 ic2 los 80 pin lqfp 68 pin plcc
mt9076b data sheet 4 zarlink semiconductor inc. pin description pin # name description plcc lqfp 151osc1 oscillator (3 v input). this pin is either connected via a 20.000 mhz crystal to osc2 where a crystal is used, or is directly driven when a 20.000 mhz. oscillator is employed. 252osc2 oscillator (3 v output). connect a 20.0 mhz crystal between osc1 and osc2. not suitable for driving other devices. 353 v ss4 negative power supply. digital ground. 454 v dd4 positive power supply. digital supply (+3.3 v 5%). 555csto control st-bus (5 v tolerant output) . csto carries serial streams for cas and ccs respectively a 2.048 mbit/s st-bus status stream which contains the 30 receive signaling nibbles (abcdzzzz or zzzzabcd). t he most significant nibbles of each st- bus time slot are valid and t he least significant ni bbles of each st-bus time slot are tristated when control bit msn (page 01h, addres s 1ah, bit 1) is set to 1. if msn=0, the position of the valid and tristated nibbles are reversed. 656 csti control st-bus (5 v tolerant input) . csti carries serial streams for cas and ccs respectively a 2.048 mbit/s st-bus contro l stream which contains the 30 transmit signaling nibbles (abcdxxxx or xxxxabcd) when rpsig=0. when rpsig=1 this pin has no function. the most significant nibbl es of each st-bus time slot are valid and the least significant nibbles of each st-bus time slot are ignored when control bit msn (page 01h, address 1ah, bit 1) is set to 1. if msn=0, the position of the valid and ignored nibbles is reversed. 757dsto data st-bus (5 v tolerant output). a 2.048 mbit/s serial stream which contains the 24/30 pcm(t1/e1) or data channels received on the pcm 24/30 (t1/e1) line. 858 dsti data st-bus (5 v tolerant input). a 2.048 mbit/s serial stream which contains the 24/30 (t1/e1) pcm or data channels to be transmitted on the pcm 24/30 (t1/e1) line. 959ds /rd data/read strobe (5 v tolerant input) . in motorola mode (ds ), this input is the active low data strobe of the processor interface. in intel mode (rd ), this input is the active low read strobe of the processor interface. 10 63 cs chip select (5 v tolerant input) . this active low input enables the non-multiplexed parallel microprocessor inte rface of the mt9076. when cs is set to high, the microprocessor interface is idle and all bus i/o pins will be in a high impedance state. 11 64 reset reset (5 v tolerant input). this active low input puts the mt9076 in a reset condition. reset should be set to high for normal operat ion. the mt9076 should be reset after power-up. the reset pin must be held low for a minimum of 1 sec. to reset the device properly. 12 65 irq interrupt request (5 v tolerant output). a low on this output pin indicates that an interrupt request is presented. irq is an open drain output that should be connected to v dd through a pull-up resistor. an active low cs signal is not required for this pin to function. 13 - 16 66-69 d0 - d3 data 0 to data 3 (5 v tolerant three-state i/o) . these signals combined with d4-d7 form the bidirectional data bus of the parallel processor interface (d0 is the least significant bit).
mt9076b data sheet 5 zarlink semiconductor inc. 17 70 vss5 negative power supply. digital ground. 18 71 ic4 internal connection (3 v input). tie to v ss (ground) for normal operation. 19 72 int/mot intel/motorola mode selection (5 v tolerant input) . a high on this pin configures the processor interface for the intel parallel non- multiplexed bus type. a low configures the processor interface for the motorola parallel non-multiplexed type. 20 73 vdd5 positive power supply. digital supply (+3.3 v 5%). 21 - 24 74-77 d4 - d7 data 4 to data 7 (5 v tolerant three-state i/o). these signals combined with d0-d3 form the bidirectional data bus of the parallel processor interface (d7 is the most significant bit). 25 78 r/w /wr read/write/write strobe (5 v tolerant input). in motorola mode (r/w), this input controls the direction of the data bus d[0: 7] during a microproce ssor access. when r/w is high, the parallel processor is reading data from the mt9076. when low, the parallel processor is writing data to the mt9076. for intel mode (wr ), this active low write strobe configures the dat a bus lines as output. 26 - 30 79, 2-5 ac0 - ac4 address/control 0 to 4 (5 v tolerant inputs). address and control inputs for the non-multiplexed parallel processor interface. ac0 is the least significant input. 31 6 gndarx receive analog ground. analog ground for the liu receiver. 32 33 7 8 rtip rring receive tip and ring (3 v input). differential inputs for the receive line signal - must be transformer coupled (see figure 5 on p age 24). in digital framer mode these pins accept digital 3 volt signals fr om a physical layer device. they may accept a split phase unipolar signal (rtip and rring employed) or an nrz signal (rtip only used). 34 9 vddarx receive analog power supply. analog supply for the liu receiver (+3.3 v 5%). 35 10 vdd1 positive power supply. digital supply (+3.3 v 5%). 36 11 vss1 negative power supply. digital ground. 37 12 txa transmit a (5 v tolerant output). when the internal liu is disabled (digital framer only mode), if control bit nrz=1, an nrz out put data is clocked out on pin txa with the rising edge of exclk (txb has no function when nrz format is selected). if nrz=0, pins txa and txb are a complementary pair of si gnals that output digital dual-rail data clocked out with the rising edge of exclk. 38 13 txb transmit b (5 v tolerant output). when the internal liu is disabled and control bit nrz=0, pins txa and txb are a complementary pa ir of signals that output digital dual- rail data clocked out with the rising edge of exclk. 39 14 rxdlclk data link clock (5 v tolerant output) . a gapped clock signal derived from the extracted line clock, available for an external device to clock in rxdl data (at 4, 8, 12, 16 or 20 khz) on the rising edge. 40 15 rxdl receive data link (5 v tolerant output) . a serial bit stream containing received line data after zero code suppression. this data is clocked out with the rising edge of exclk. 41 16 txmf transmit multiframe boundary (5 v tolerant input). an active low input used to set the transmit multiframe boundary (cas or crc multiframe). the mt9076 will generate its own multiframe if this pin is held high. this input is usually pulled high for most applications. pin description (continued) pin # name description plcc lqfp
mt9076b data sheet 6 zarlink semiconductor inc. 42 17 rxmf /txf p receive multiframe boundary / transmit frame boundary (5 v tolerant output). if the control bit tx8ken (page 02h address 10h bit 2) is low, this negative output pulse delimits the received multiframe boundary. th e next frame output on the data stream (dsto) is basic frame zero on the t1 or pcm 30 link. in e1 mode this receive multiframe signal can be related to either the receive crc multiframe (page 01h, address 17h, bit 6, mfsel=1) or the receive signaling multiframe (mfsel=0). if the control bit tx8ken is set high, this positi ve output pulse delimits the frame boundary (the first bit transmit in the frame) for the digital output stream on pins txa and txb. 43 18 bs/ls bus/line synchronization mode selection (5 v tolerant input) . if high, c4b and f0b will be inputs; if low, c4b and f0b will be outputs. 44 22 exclk 2.048 mhz in e1 mode or 1.544 mhz in t1 mode, extracted clock (5 v tolerant output). the clock extracted from the received signal and used internally to clock in data received on rtip and rring. 45 23 c4b 4.096 mhz system clock (5 v tolerant input/output). c4b is the clock for the st- bus sections and transmit serial pcm data of the mt9076. in the free-run (s/fr /exclki=0) or line synchronous mode (s/fr /exclki=1 and bs/ls =0) this signal is an output, while in bus synchronous mode (s/fr /exclki=1 and bs/ls =1) this signal is an input clock. 46 24 f0b frame pulse (5 v tolerant input/output). this is the st-bus frame synchronization signal, which delimits the 32 channel frame of csti, csto, dsti, dsto and the pcm30 link. in the free-run (s/fr /exclki=0) or line synchronous mode (s/fr /exclki=1 and bs/ls =0) this signal is an output, while in bus synchronous mode (s/fr /exclki=1 and bs/ls =1) this signal is an input. 47 25 rxfp receive frame pulse/receive ccs clock (5 v tolerant output). an 8khz pulse signal, which is low for one extracted clock pe riod. this signal is synchronized to the receive ds1 or pcm 30 basic frame boundary. 48 26 ic1 internal connection. must be left open for normal operation. 49 27 v ss2 negative power supply. digital ground. 50 28 v dd2 positive power supply. digital supply (+3.3 v 5%). 51 29 vdd atx transmit analog power supply. analog supply for the li u transmitter (+3.3 v 5%). 52 53 30 31 ttip tring transmit tip and ring(output). differential outputs for the transmit line signal - must be transformer coupled (see figure 5 on page 24). 54 32 gnd atx transmit analog ground. analog ground for the liu transmitter. 55 33 tdi ieee 1149.1a test data input (3 v input). if not used, this pin should be pulled high. 56 34 tdo ieee 1149.1a test data output (5 v tolerant output). if not used, this pin should be left unconnected. 57 35 tms ieee 1149.1a test mode selection (3 v input) . if not used, this pin should be pulled high. 58 36 tclk ieee 1149.1a test clock signal (3 v input). if not used, this pin should be pulled high. 59 37 trst ieee 1149.1a reset signal (3 v input). if not used, this pin should be held low. pin description (continued) pin # name description plcc lqfp
mt9076b data sheet 7 zarlink semiconductor inc. device overview the mt9076 is a t1/e1/j1 single chip transceiver that incorporates an advanced framer, a long-haul liu (line interface unit), a low jitter pll (phase locked loop) and 3 hdlcs (high-level data link controller). the t1, e1 and j1 operating modes are selectable under software control. standards compliance in t1 mode, the mt9076 meets or supports the latest recommendations including telcordia gr-303-core, at&t pub43801, tr-62411, ansi t1.102, t1.403 and t1.408. in t1 esf mode the crc-6 calculation and yellow alarm can be configured to meet the re quirements of a j1 interface. in e1 mode, the mt9076 meets or supports the latest itu-t recommendations for pcm 30 and isdn primary rate including g.703, g.704, g.706, g.732, g.775, g.796, g.823, g.964 (v5.1), g.965 (v5,2) and i.431. it also meets or supports etsi ets 300 011, ets 300 166, ets 3 00 233, ets 300 324 (v5.1) and ets 300 347 (v5.2). 60 38 txao transmit all ones (input). high - ttip, tring will transmit data normally. low - ttip, tring will transmit an all ones signal. 61 43 los loss of signal or synchronization (5 v tolerant output). when high, and los/lof (page 0, this signal indicates that the re ceive portion of the mt9076 is either not detecting an incoming signal (bit llos on page 03h address 16h is one) or is detecting a loss of basic frame alignment condition (bit tsync (t1), sync (e1) on page 03h address 10h is one). if los/lo f=1, a high on this pin indicates a loss of signal condition. 62 44 ic2 internal connection (3 v input). tie to v ss (ground) for normal operation. 63 45 ic3 internal connection (3 v input). tie to v ss (ground) for normal operation. 64 46 txdlclk transmit data link clock (5 v tolerant output). a gapped clock signal derived from a gated 2.048 mbit/s clock for transmit data link at 4, 8, 12, 16 or 20 khz. the transmit data link data (txdl) is clocked in on the rising edge of txdlclk. txdlclk can also be used to clock dl data out of an external serial controller. 65 47 txdl transmit data link (5 v tolerant input) . an input serial stream of transmit data link data at 4, 8, 12, 16 or 20 kbit/s. 66 48 s/fr/ excl ki synchronization/ freerun / extracted clock (5 v tolerant input). if low, and the internal liu is enabled, the mt9076 is in free run mode. pins 45 c4b and 46 f0b are outputs generating sys tem clocks. slips will occur in the re ceive slip buffer as a result of any deviation between the mt9076's internal pll (which is free - running) and the frequency of the incoming line data. if high, and the internal liu is enabled, the mt9076 is in bus or line synchronization mode depending on the bs/ls pin. if the internal liu is disabled, in digital framer mode, this pin (exclki) takes an input clock 1.544 mhz (t1)/ 2.048 mhz (e1) that clocks in the received digital data on pins rxa and rxb with its rising edge. 67 49 vdd3 positive power supply. digital supply (+3.3 v 5%) . 68 50 vss3 negative power supply. digital ground. pin description (continued) pin # name description plcc lqfp
mt9076b data sheet 8 zarlink semiconductor inc. microprocessor port the mt9076 registers are a ccessible via an 8-bit parallel motorola or intel non-multiplexed microprocessor interface. liu the mt9076 liu interfaces the digital framer function s to either the ds1 (t1 mode) or pcm 30 (e1 mode) transformer-isolated four wire line. in t1 mode, the liu can pre-equaliz e the transmit signal to meet the t1.403 and t1.102 pulse templates after attenuation by 0 - 655 feet of 22 awg pic cable, alternativ ely it can provide line build outs of 7.5 db, 15 db and 22.5 db. in t1 mode the receiver can recover signals attenuated by up to 36 db at 772 khz. in e1 mode, the liu transmits signals that meet the g.703 2.048 mbit/s pulse template and the receiver can recover signals attenuated by up to 40 db at 1024 khz. digital framer only mode to accommodate some special applications, the mt9076 sup ports a digital framer only mode that provides direct access to the transmit and receive data in digital format, i.e., by-passing the analog liu front-end. in digital framer only mode, the mt9076 supports uni polar non-return to zero or bipolar return to zero data. pll and slip buffers the mt9076 pll attenuates jitter from 2.5 hz with a roll-off of 20 db/decade. the intrinsic jitter is less than 0.02 ui. the device can operate in one of three timing modes: system bus synchronous mode, line synchronous mode, or free-run mode. in all three timing modes the low jitter output of the pll provides timing to the transmit side of the liu. in t1 mode, the receive and transmit paths both include tw o-frame slip buffers. the transmit slip buffer features programmable delay and serves as a jitt er attenuator (ja) fifo and a rate converter between the st-bus and the 1.544 mbit/s t1 line rate. in e1 mode, the receive path includes a two-frame slip buffer and the transmit path contains a 128 bit jitter attenuator (ja) fifo with programmable depth. interface to the system backplane on the system side the mt9076 framers can interface to a 2.048 mbit/s or 8.192 mbit/s st-bus backplane. there is an asynchronous mode for inverse mux for atm (ima ) applications, this enables the framer to interface to a 1.544 mbit/s (t1) or 2.048 mbit/s (e1) serial bus with asynchr onous transmit and receive timing. framing modes the mt9076 framers operate in termination mode or trans parent mode. in the receive transparent mode, the received line data is channelled to the dsto pin with ar bitrary frame alignment. in the transmit transparent mode, no framing or signaling is imposed on the data transmitted from the dsti pin onto the line. in t1 mode, the framers operate in any of the followi ng framing modes: d4, extended superframe (esf) or slc- 96. in e1 mode, the framers run three fr aming algorithms: basic frame alignment , signaling multiframe alignment and crc-4 multiframe alignment. the remote alarm indication (rai ) bit is automatically controlled by an internal state machine.
mt9076b data sheet 9 zarlink semiconductor inc. access to the maintenance channel the t1 esf facility data link (fdl) bits can be accessed in the following three ways: through the data link pins txdl, rxdl, rxdlc and txdlc; through internal re gisters for bit oriented messages; through an embedded hdlc. in e1 mode, the sa bits (bits 4-8 of the non-frame al ignment signal) can be accesse d in four ways: through data link pins txdl, rxdl, rxdlc and txdlc, through single byte transmit and receive registers; through five byte transmit and receive national bit buffers; through an embedded hdlc. robbed bit signaling/channel associated signaling robbed bit signaling and channel associated signaling info rmation can be accessed two ways: via the microport; via the csti and csto pins. signaling informatio n is frozen upon loss of multiframe alignment. in t1 mode, the mt9076 supports ab and abcd robbed bi t signaling. robbed bit signaling can be enabled on a channel by channel basis. in e1 mode the mt9076 supports channel associated signaling (cas) multiframing. hdlcs the mt9076 provides three embedded hdlcs with 128 byte deep transmit and receive fifos. in t1 mode, the embedded hdlcs can be assigned to any c hannel and can operate at 56 kbit/s or 64 kbit/s. in t1 esf mode, hdlco can be assigned to the 4 kbit/s fdl. in e1 mode, the embedded hdlcs can be assigned to any timeslot and can operate at 64 kbit/s. hdlco can be assigned to timeslot 0 sa bits (bits 4-8 of the non-frame alignment signal) and can oper ate at 4,8,12,16 or 20 kbit/s. performance monitoring and debugging the mt9076 has a comprehensive suite of performance monitoring and debugging features. these include error counters, loopbacks, deliberate error insertion and a 2 15 ?1 qrs/prbs generator/detector. interrupts the mt9076 provides a comprehensive set of maskable interr upts. interrupt sources consist of synchronization status, alarm status, counter indicati on and overflow, timer status, slip in dication, maintenance functions and receive signaling bit changes.
mt9076b data sheet 10 zarlink semiconductor inc. mt9076 detailed feature list standards compliance and support line interface unit (liu) ? t1 and e1 modes use the same 1:1 transmit and receive transformers ? internal register allows termination impe dance to be changed under software control. ? programmable pulse shapes and pulse amplitudes ? automatic or manual receiver equalization ? receive signal peak amplitude is reported with 8-bit resolution ? output pin to indicate loss of signal/ loss of frame synchronization ? liu output is disabled at power-up until enabled by software ? input pin to force transmission of ais t1/j1 mode e1 mode ansi: t1.102,t1.231, t1.403, t1.408 at&t: tr 62411, pub43801 telcordia: gr-303-core ttc: jt-g703, jt-g704, jt-g706 etsi: ets 300 011, ets 300 166, ets 300 233, ets 300 324, ets 300 347 itu: g.703, g.704, g.706, g.732 g.775, g.796, g.823, i.431, g.964, g.965 t1/j1 mode e1 mode ? reliably recovers signals with cable attenuation up to 36 db @ 772 khz ? reliably recovers signals with cable attenuation up to 40 db @ 1024 khz ? transmit pulse meets t1.403 and t1.102 pulse templates ? transmit pulse meets g.703 pulse template ? indicates analog los of signal if the received signal is more than 20 db or 40 db below nominal for more than 1 ms ? indicates analog los of signal if the received signal is more than 20 db or 40 db below nominal for more than 1 ms ? receiver tolerates jitter as required by at&t tr62411 ? receiver tolerates jitter as required by etsi ets 300 011
mt9076b data sheet 11 zarlink semiconductor inc. digital framer mode ? the liu can be disabled and bypassed to allow the mt9076 to be used as a digital framer ? single phase nrz or two phase nrz modes are software selectable ? line coding is software selectable phase lock loop ? locks to a 4.096 mhz input clock, or to the 1.544 mhz / 2.048 mhz extracted clock ? ima mode locks to 1,544 mhz or 2,048 mhz external clock ? attenuates jitter from less than 2.5 hz with a roll off of 20 db/decade ? attenuates jitter in the transmit or receive direction ? intrinsic jitter less than 0.02 ui ? meets the jitter characteristics as specified in at&t tr62411 ? meets the jitter characteristics as specified in ets 300 011 ? can be operated in free-run, line synchronous or system bus synchronous modes access and control ? mt9076 registers can be accessed via an 8-bit non-multiplexed parallel microprocessor port ? the parallel port can be configured for motorola or intel style control signals backplane interfaces ? 2.048 mbit/s or 8.192 mbit/s st-bus ? ima mode, 1.544 mbit/s (t1) or 2.048 mbit/s (e1) se rial bus with asynchronous transmit and receive timing for inverse mux for atm (ima) applications. slip buffers are bypassed and signaling is disabled. ? csto/csti pins can be used to access the receive/transmit signaling data ? rxdl pin can be used to access the entire b8zs/h db3 decoded receive stream including framing bits ? txdl pin can be used to transmit data on the fdl (t1) or the sa bits (e1) ? transmit pre-equalization and line build out options: 0-133 feet 133-266 feet 266-399 feet 399-533 feet 533-655 feet -7.5 db -15 db -22.5 db t1/j1 mode e1 mode ? pcm-24 channels 1-24 are mapped to st- bus channels 0-23 respectively ? pcm-30 timeslots 0-31 are mapped to st- bus channels 0-31 respectively ? the framing-bit is mapped to st-bus channel 31 t1/j1 mode e1 mode
mt9076b data sheet 12 zarlink semiconductor inc. data link access and monitoring for national (sa) bits (e1 mode only) ? in addition to the datalink functions, the sa bits can be accessed using: ? single byte register ? five byte transmit and receive national bit buffers ? a maskable interrupt is generated on the change of state of any sa bit three embedded floating hdlcs (hdlc0, hdlc1, hdlc2) ? successive writes/reads can be made to the transmit/receive fifos at 160 ns or 80 ns intervals ? flag generation and frame check sequence (fcs) gener ation and detection, zero insertion and deletion ? continuous flags, or continuous 1s are transmitted between frames ? transmit frame-abort ? transmit end-of-packet after a programmable number of bytes (up to 65,536 bytes) ? invalid frame handling: ? frames yielding an incorrect fcs are tagged as bad packets ? frames with fewer than 25 bits are ignored ? frames with fewer than 32 bits between flags are tagged as bad packets ? frames interrupted by a frame-abort sequence remain in the fifo and an interrupt is generated ? access is provided to the receive fcs ? fcs generation can be inhibited for terminal adaptation ? recognizes single byte, dual byte and all call addresses ? independent, 16-128 byte deep transmit and receive fifos ? receive fifo maskable interrupts for near full (programmable levels) and overflow conditions ? transmit fifo maskable interrupts for nearly empty (programmable levels) and underflow conditions ? maskable interrupts for transmit end-of-packet and receive end-of-packet ? maskable interrupts for receive bad-frame (includes frame abort) ? transmit-to-receive and receive-to-transmit loopbacks are provided ? transmit and receive bit rates and enables are independent t1/j1 mode e1 mode ? three methods are provided to access the datalink: 1. txdl and rxdl pins support transmit and receive datalinks 2. bit oriented messages are supported via internal registers 3. an internal hdlc can be assigned to transmit/receive over the fdl in esf mode ? two methods are provided to access the datalink: 1. txdl and rxdl pins support transmit and receive datalinks over the sa4~sa8 bits 2 . an internal hdlc can be assigned to transmit/receive data via the sa4~sa8 bits ? in transparent mode, if the sa4 bit is used for an intermediate datalink, the crc-4 remainder can be updated to reflect changes to the sa4 bit
mt9076b data sheet 13 zarlink semiconductor inc. ? frame aborts can be sent under software control and t hey are automatically transmitted in the event of a transmit fifo underrun slip buffers jitter attenuator fifo ? a jitter attenuator fifo is available on the transmit si de in e1 mode and in ima mode. the depth of the ja fifo can be configured to be from16 bits deep to 128 bits deep in 16 bit increments inverse mux for atm (ima) mode t1/j1 mode e1 mode hdlc0 ? assignable to the esf facility data link or any channel hdlc0 ? assigned to timeslot-0, bits sa4~sa8 or any other timeslot ? operates at 4 kbps, 56 kbps or 64 kbps hdlc1, hdlc2 ? assignable to any channel ? operates at 56 kbps or 64 kbps ? operates at 4, 8, 12, 16 or 20 kbps depending on which sa bits are selected for hdlc0 use hdlc1, hdlc2 ? assigned to any timeslot except timeslot-0 ? operates at 64 kbps t1/j1 mode e1 mode transmit slip buffer ? two-frame slip buffer capable of performing a controlled slip receive slip buffer ? two-frame slip buffer capable of performing a controlled slip ? intended for rate conversion and jitter attenuation in the transmit direction ? wander tolerance of 208 ui peak-to-peak ? programmable delay ? indica tion of slip direction ? transmit slips are independent of receive slips ? indication of slip direction receive slip buffer ? two-frame slip buffer capable of performing a controlled slip ? wander tolerance of 142 ui (92 s) peak ? indication of slip direction t1/j1 mode e1 mode ? transmit and receive datastreams are independently timed ? transmit and receive datastreams are independently timed ? the transmit clock synchronizes to a 1.544 mhz clock ? receive slip buffer is bypassed ? cas and hdlcs are disabled
mt9076b data sheet 14 zarlink semiconductor inc. framing algorithm line coding ? transmit and receive slip buffers are bypassed ? robbed bit signaling and hdlcs are disabled t1/j1 mode e1 mode ? synchronizes with d4 or esf protocols ? supports slc-96 framing ? framing circuit is off-line ? transparent transmit and receive modes ? in d4 mode the fs bits can optionally be cross checked with the ft bits ? the start of the esf multiframe can be determined by the following methods: ? free-run ? software reset ? synchronized to the incoming multiframe ? an automatic reframe is initiated if the framing bit error density exceeds the programmed threshold ? in transparent mode, no reframing is forced by the device ? software can force a reframe at any time ? in esf mode the crc-6 bits can be optionally confirmed before forcing a new frame alignment ? during a reframe the signaling bits are frozen and error counting for ft, fs, esf framing pattern and crc-6 bits is suspended ? if j1 crc-6 is selected the fs bits are included in the crc-6 calculation ? j1 crc-6 and j1 yellow alarm can be independently selected ? supports robbed bit signaling ? mt9076 contains 3 distinct and independent framing algorithms 1. basic frame alignment 2. signaling multiframe alignment 3. crc-4 multiframe alignment ? transparent transmit and receive modes ? automatic interworking between interfaces with and without crc-4 processing capabilities is supported ? an automatic reframe is forced if 3 consecutive frame alignment patterns or three consecutive non-frame alignment bits are received in error ? in transparent mode, no reframing is forced by the device ? software can force a reframe at any time ? software can force a multiframe reframe at any time ? e-bits can optionally be set to zero until crc synchronization is achieved ? optional automatic rai ? supports cas multiframing ? optional automatic y-bit to indicate cas multiframe alignment t1/j1 mode e1 mode ? b8zs or ami line coding ? pulse density enforcement ? forced ones insertion ? hdb3 or ami line coding t1/j1 mode e1 mode
mt9076b data sheet 15 zarlink semiconductor inc. channel associated signaling alarms ? abcd or ab bits can be automatically inserted and extracted ? transmit abcd or ab bits can be passed via the microport or via the csti pin ? receive abcd or ab bits are accessible via the microport or via the csto pin ? most significant or least significant csti/csto nibbles can be selected to carry signaling bits ? unused nibble positions in the cs ti/csto bandwidth are tri-stated ? an interrupt is provided in the event of changes in any of the signaling bits ? receive signaling bits are frozen if signaling multiframe alignment is lost t1/j1 mode e1 mode ? signaling bits can be debounced by 6 ms ? signaling bits can be debounced by 14 ms t1/j1 mode e1 mode d4 yellow alarm, two types 1. bit position 2 is zero for virtually every ds0 over 48ms 2. two consecutive ones in the s-bit position of the twelfth frame esf yellow alarm, two types 1. reception of 000000001 1111111 in seven or more codewords out of ten (t1) 2. reception of 1111111111111111 in seven or more codewords out of ten (j1) alarm indication signal (ais) ? declared if fewer than six zeros are detected during a 3 ms interval loss of signal (los ) ? analog loss of signal is declared if the received signal is more than 20 db or 40 db below nominal for at least 1 ms ? digital loss of signal is declared if 192 or 32 consecutive zeros are received ? output pin indicates los and/or loss of frame alignment remote alarm indication (rai) ? bit 3 of the receive nfas alarm indication signal (ais ) ? unframed all ones signal for at least a double frame or two double frames timeslot 16 alarm indication signal ? all ones signal in timeslot 16 loss of signal (los) ? analog loss of signal is declared if the received signal is more than 20 db or 40 db below nominal for at least 1 ms ? digital loss of signal is declared if 192 or 32 consecutive zeros are received ? output pin indicates los and/or loss of frame alignment remote signaling multiframe alarm ? y-bit of the multiframe alignment signal
mt9076b data sheet 16 zarlink semiconductor inc. maskable interrupts t1/j1 mode e1 mode hdlc interrupts ? change of state of terminal synchronization ? change of state of multiframe synchronization ? change of received bit oriented message ? change of state of reception of ais ? change of state of reception of los ? reception of a severely errored frame ? transmit slip ? receive slip ? receive framing bit error ? receive crc-6 error ? receive yellow alarm ? change of receive frame alignment ? receive line code violation ? receive prbs error ? pulse density violation ? framing bit error counter overflow ? crc-6 error counter overflow ? out of frame alignment counter overflow ? change of frame alignment counter overflow ? line code violation counter overflow ? prbs error counter overflow ? prbs multiframe counter overflow ? multiframes out of alignment counter overflow ? loop code detected ? one second timer ? five second timer ? receive new bit oriented message (debounced) ? signaling (ab or abcd) bit change ? change of state of basic frame alignment ? change of state of multiframe synchronization ? change of state of crc-4 multiframe synchronization ? change of state of reception of ais ? change of state of reception of los ? reception of consecutively errored fass ? receive remote signaling multiframe alarm ?receive slip ? receive fas error ? receive crc-4 error ? receive e-bit ? receive ais in timeslot 16 ? line code violation ? receive prbs error ? receive auxiliary pattern ?receive rai ? fas error counter overflow ? crc-4 error counter overflow ? out of frame alignment counter overflow ? receive e-bit counter overflow ? line code violation counter overflow ? prbs error counter overflow ? prbs multiframe counter overflow ? change of state of any sa bit or sa nibble ? jitter attenuator within 4 bits of overflow/underflow ? one second timer ? two second timer ? signaling (cas) bit change ? go ahead pattern received ? end of packet received ? end of packet transmitted ? end of packet read from receive fifo ? transmit fifo low ? frame abort received ? transmit fifo underrun ? receive fifo full ? receive fifo overflow
mt9076b data sheet 17 zarlink semiconductor inc. error counters ? all counters can be preset or cleared under software control ? maskable occurrence interrupt ? maskable overflow interrupt ? counters can be latched on one second intervals error insertion loopbacks ? digital loopback ? remote loopback ? st-bus loopback ? payload loopback ? metallic loopback ? local timeslot loopback ? remote timeslot loopback per timeslot control the following features can be cont rolled on a per timeslot basis: ? clear channel capability (only used in t1/j1) ? choice of sourcing transmit signali ng bits from microport or csti pin ? remote timeslot loopback ? local timeslot loopback ? prbs insertion and reception ? digital milliwatt pattern insertion ? per channel inversion ? transmit message mode t1/j1 mode e1 mode ? prbs error counter (16-bit) ? crc multiframe counter (16-bit) ? framing bit error counter (8-bit) ? out of frame alignment counter (4-bit) ? change of frame alignment counter (4-bit) ? multiframes out of sync counter (8-bit) ? line code violation / excessive zeros counter (16-bit) ? crc-6 error counter (16-bit) ? errored fas counter (8-bit) ? e-bit counter (10-bit) ? line code violation / excessive zeros counter (16-bit) ? crc-4 error counter (16-bit) ? prbs error counter (8-bit) ? crc multiframe counter (8-bit) t1/j1 mode e1 mode ? bipolar violations ? crc-6 errors ? ft errors ? fs errors ? payload errors ? loss of signal error ? bipolar violations ? crc-4 errors ? fas errors ? nfas errors ? payload errors ? loss of signal error
mt9076b data sheet table of contents 18 zarlink semiconductor inc. 1.0 mt9076 line interface unit (liu) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 1.1 receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 1.2 transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 1.3 20 mhz clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 1.4 phase lock loop (pll) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 2.0 clock jitter attenuation modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 2.1 jitter attenuator fifo . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 2.2 ima mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 2.2.1 t1 mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 2.2.2 e1 mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 3.0 the digital interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 3.1 t1 digital interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 3.2 frame and superframe structure in t1 mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 3.2.1 multiframing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 3.3 e1 digital interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 3.3.1 basic frame alignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 3.3.2 crc-4 multiframing in e1 mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 3.3.3 cas signaling multiframing in e1 mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 4.0 mt9076 access and control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 4.1 the control port interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 4.2 control and status register access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 4.3 identification code. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 4.3.1 st-bus streams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 5.0 reset operation (initialization) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 6.0 transmit data all ones (txao) operati on. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 7.0 data link operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 7.1 data link operation in e1 mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 7.2 data link operation in t1 mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 7.2.1 external data link . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 7.2.2 bit - oriented messaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 8.0 floating hdlc channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 8.1 channel assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 8.2 hdlc description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 8.2.1 hdlc frame structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 8.2.2 data transparency (zero insertion/de letion). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 8.2.3 invalid frames . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 8.2.4 frame abort . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 8.2.5 interframe time fill and link channel states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 8.2.6 go-ahead. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 8.3 hdlc functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 8.3.1 hdlc transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 8.3.2 hdlc receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 9.0 slip buffers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 9.1 slip buffer in t1 mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 9.2 slip buffer in e1 mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 10.0 framing algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 10.1 frame alignment in t1 mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 10.2 frame alignment in e1 mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 10.2.1 notes for synchronization state diagram (figure 14) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 10.3 reframe. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 10.3.1 e1 mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
mt9076b data sheet table of contents 19 zarlink semiconductor inc. 10.3.2 t1 mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 11.0 mt9076 channel signaling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 11.1 channel signaling in t1 mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 11.2 channel signaling in e1 mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 12.0 loopbacks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 13.0 performance monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 13.1 error counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 13.2 t1 counters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 13.2.1 framing bit error counter (fc7-0). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 13.2.2 out of frame/change of frame alignment counter (oof3-0/cofa3-0) . . . . . . . . . . . . . . . . . . 55 13.2.3 multiframes out of sync counter (mfoof7-mfoof0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 13.2.4 crc-6 error counter (cc15-0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 13.2.5 line code violation erro r counter (lcv15-lcv0). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 6 13.2.6 prbs error counter (ps7-0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 13.2.7 crc multiframe counter for prbs (psm7-0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 6 13.3 e1 counters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 13.4 errored fas counter (efas7-efas0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 13.5 e-bit counter (ec15-0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 13.6 line code violation error counter (lcv15-lcv0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 13.7 crc-4 error counter (cc15-0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 13.8 prbs error counter (ps7-0). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 13.9 crc multiframe counter for prbs (psm7-0). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 14.0 error insertion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 15.0 per time slot control words . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 15.1 clear channel capability. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 15.2 microport signaling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 15.3 per time slot looping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 15.4 prbs testing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 15.5 digital milliwatt. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 15.6 per channel inversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 15.7 transmit message . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 16.0 alarms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 16.1 automatic alarms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 17.0 detected events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 17.1 t1 mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 17.1.1 severely errored frame event. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 17.1.2 loop code detect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 17.1.3 pulse density violation detect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 17.1.4 timer outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 17.2 e1 mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 17.2.1 consecutive frame alignment patterns (confap) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 17.2.2 receive frame alignment signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 17.2.3 receive non frame alignment signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 17.2.4 receive multiframe alignment signal s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 18.0 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 18.1 interrupts on t1 mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 18.2 interrupts on e1 mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 19.0 digital framer mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 19.1 t1 mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 19.2 e1 mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 20.0 control and status registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
mt9076b data sheet table of contents 20 zarlink semiconductor inc. 20.1 t1 mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 20.1.1 master control 1 (page 01h) (t1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 20.1.2 master control 2 (page 02h) (t1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 20.1.3 master status 1 (page03h) (t1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 20.1.4 master status 2 (page 04h) (t1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 20.1.5 per channel transmit signalling (pages 5 and 6) (t1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 20.2 per time slot control words (pages 7 and 8) (t1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 20.2.1 per channel receive signaling (t1 and e1 mode) (pages 9 and 0ah) . . . . . . . . . . . . . . . . . . . 100 20.3 e1 mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 20.3.1 master control 1 (page 01h) (e1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 20.4 master control 2 (page-2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 20.4.1 master control 2 (page 02h) (e1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 20.5 master status 1 (page 03h) (e1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 21.0 master status 2 (page-4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 21.1 master status 2 (page 04h) (e1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 21.2 per channel transmit signaling (pages 5 and 6) (e1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 21.3 per time slot control words (pages 7 and 8) (e1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 21.4 per channel receive signaling (pages 9 and 0ah) (e1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 22.0 hdlc control and status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 23.0 transmit national bit buffer (page 0eh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 24.0 receive national bit buffer (page 0fh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 25.0 ac/dc electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
mt9076b data sheet list of figures 21 zarlink semiconductor inc. figure 1 - mt9076 functional block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 figure 2 - pin connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 figure 3 - input jitter tolerance as recommended by tr-62411 (t1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 figure 4 - input jitter tolerance as recommended by g.823 and etsi 300 011 (e1) . . . . . . . . . . . . . . . . . . . . . 23 figure 5 - analog line interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 figure 6 - pulse template (t1.403)(t1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 figure 7 - pulse template (g.703)(e1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 figure 8 - clock oscillator circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 figure 9 - crystal oscillator circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 figure 10 - tr 62411 jitter attenuation curve. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 figure 11 - read and write pointers in the transmit slip buffers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 figure 12 - read and write pointers in the receive slip buffers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 figure 13 - read and write pointers in the slip buffers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 figure 14 - synchronization state diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 figure 15 - motorola microport timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 figure 16 - intel microport timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 figure 17 - jtag port timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 figure 18 - transmit data link timing diagram (t1 mode). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 figure 19 - transmit data link timing diagram (e1 mode). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 figure 20 - transmit data link functional timing (e1 mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 figure 21 - receive data link functional timing (t1 mode). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 figure 22 - receive data link diagram (t1 mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 figure 23 - receive data link functional timing (e1 mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 figure 24 - receive data link timing diagram (e1 mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 figure 25 - st-bus functional timing diagram - 2.048 mb/s mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 figure 26 - st-bus functional timing diagram - 8.192 mb/s mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 figure 27 - st-bus timing diagram (input clocks) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 figure 28 - st-bus timing diagram (output clocks) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 figure 29 - receive multiframe functional timing (t1 mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 figure 30 - receive multiframe functional timing (e1 mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 figure 31 - transmit multiframe functional timing (t1 mode or e1 mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 figure 32 - multiframe timing diagram (t1 mode or e1 mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 figure 33 - txa/txb functional timing (t1 mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 figure 34 - txa/txb functional timing (e1 mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 figure 35 - txa/txb timing diagram (t1 mode or e1 mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 figure 36 - tx ima functional timing (t1 mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166 figure 37 - rx ima functional timing (t1 mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166 figure 38 - tx ima functional timing (e1 mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 figure 39 - rx ima functional timing (e1 mode). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 figure 40 - tx ima timing diagram (t1 mode or e1 mode). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 figure 41 - rx ima timing diagram (t1 mode or e1 mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 figure 42 - d4 format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 figure 43 - pcm 30 format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 figure 44 - st-bus stream format - 2.048 mb/s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 figure 45 - st-bus stream format 8.192 mb/s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169
mt9076b data sheet 22 zarlink semiconductor inc. 1.0 mt9076 line interface unit (liu) 1.1 receiver the receiver portion of the mt9076 liu consists of an input signal peak detecto r, an optional equalizer with separate high pass sections, a smoothing filter, data and clock slicers and a clock extractor. receive equalization gain can be set manually (i.e., software) or it can be determined automatic ally by peak detectors. the output of the receive equalizer is conditioned by a smoo thing filter and is passed on to the clock and data slicer. the clock slicer output signal drives a phase locked loop, which generates an extracted clock (exclk). this extracted clock is used to sample the output of t he data comparator. in t1 mode, the receiver portion of the liu can recover cl ock and data from the line si gnal for loop lengths of 0 - 6000 ft. of 22 awg cable and tolerate jitter to t he maximum specified by at&t tr 62411(figure 3). the los output pin function is selectable to indicate any combination of loss of signal and/or loss of basic frame synchronization condition. the llos (loss of signal) status bit indicates when the receive signal level is lower than the analog threshold for at least 1 millisecond, or when the number of consecutive received zeros ex ceeds the digital loss threshold. in e1 mode, the analog threshold is either of -20 db or -40 db. the digital loss threshold is either 32 or 192. in t1 mode, the receive liu circuit re quires a terminating resistor of 100 ? across the device side of the receive 1:1 transformer. in e1 mode, the receive liu circuit requir es a terminating resistor of either 120 ? or 75 ? across the device side of the receive 1:1 transformer. the jitter tolerance of the clock extractor circuit exceeds the requirements of tr 62411 in t1 mode (see figure 3) and g.823 in e1 mode (see figure 4). figure 3 - input jitter tolerance as recommended by tr-62411 (t1) 138ui 0.4ui 1.0hz 10hz 1.0khz 10khz 100khz jitter frequency (log scale) peak to peak jitter amplitude (log scale) 28ui 1.0ui 10ui 100ui 0.1 hz 100 hz 4.9 hz
mt9076b data sheet 23 zarlink semiconductor inc. figure 4 - input jitter tolerance as recommended by g.823 and etsi 300 011 (e1) 1.2 transmitter the transmit portion of the mt9076 liu consists of a hi gh speed digital-to-analog converter and complementary line drivers. when a pulse is to be transmitted, a sequence of digital values (dependent on transmit equalization) are read out of a rom by a high speed clock. these values drive th e digital-to-analog converte r to produce an analog signal, which is passed to the complementary line drivers. the complementary line drivers are designed to drive a 1: 2.4 step-up transformer in t1 mode and either a 1:2 or 1:2.4 step-up transformer in e1 mode (see figure 5). a 0.47 uf capacitor is required between the ttip and the transmit transformer. resistors rt (as sh own in figure 5) are for termination fo r transmit return loss. the values of rt may be optimized for t1 mode, e1 120 ? lines, e1 75 ? lines or set at a compromise value to serve multiple applications. program the tx liu control word (page 02h, address 11h) to adjust the pulse amplitude accordingly. alternatively, the pulse level and shape may be discre tely programmed by writing to the custom pulse level registers (page 2, addresses 1ch to 1fh) and setting the custom transmit pulse bit high (bit 3 of the tx liu control word). in this case the output of each of the regi sters directly drives the d/a converter going to the line driver. table 1 and table 2 show recomme nded transmit pulse amplitude settings. in t1 mode, the template for the tr ansmitted pulse (the dsx-1 template) is shown in figure 6. the nominal peak voltage of a mark is 3 volts. the ratio of the amplit ude of the transmit pulses generated by ttip and tring lie between 0.95 and 1.05. in e1 mode, the template for the trans mitted pulse, as specified in g.703, is shown in figure 7. the nominal peak voltage of a mark is 3 volts for 120 ? twisted pair applications and 2.37 volts for 75 ? coax applications. the ratio of the amplitude of the transmit pulses generated by ttip and tring lie between 0.95 and 1.05. 18ui 1.5ui 0.2ui 1.667hz 20hz 2.4khz 18khz 100khz peak to peak jitter amplitude (log scale) jitter frequency (log scale) mt9076 tolerance
mt9076b data sheet 24 zarlink semiconductor inc. figure 5 - analog line interface notes : 1) protection circuitry (i.e., voltage clamps, line fuses, common mode choke etc.) depends on the application and is not shown. for a reference design, refer to the evaluation board schematic. 2) the transformer shown is a pulse engineering t1144. name functional description txl2-0 transmit line build out 2 - 0 . setting these bits shapes the transmit pulse as detailed in the table below: txl2 txl1 txl0 line build out 0 0 0 0 to 133 feet/ 0 db 0 0 1 133 to 266 feet 0 1 0 266 to 399 feet 0 1 1 399 to 533 feet 1 0 0 533 to 655 feet 1 0 1 -7.5 db 1 1 0 -15 db 1 1 1 -22.5 db after reset these bits are zero. table 1 - transmit line build out (t1) 0.47 uf 1:1 tring 1:2.4 rt rt 100 ? tx rx rtip rring 120 ? ttip r t : refer to datasheet 75 ?
mt9076b data sheet 25 zarlink semiconductor inc. table 2 - transmit pulse amplitude (e1) figure 6 - pulse te mplate (t1.403)(t1) name functional description wr winding ratio. set this pin low if a 1:2.4 transformer is used on the transmit side. set this pin high if a 1:2 transformer is used. tx2-0 transmit pulse amplitude. select the tx2 ?tx0 bits according to the line type, value of termination resistors (rt), and transformer turns ratio used. tx2 tx1 tx0 000 001 010 011 100 101 110 111 line impedance (ohms) 120 120 120 75 - 75 75 75 rt(ohms) 0 6.8 6.8 5.1 - 6 6 5.1 transformer ratio 1:2.4 1:2.4 1:2.4 1:2.4 - 1:2 1:2 1:2.4 wr (bit 7) 0 0 0 0 - 1 1 0 after reset, these bits are zero. normalized amplitude -0.39 -0.27 -0.23 0 0.15 0.23 0.34 0.46 0.61 0.77 0.93 0.27 1.16 1.20 1.05 0.90 0.95 0.80 0.50 0.05 0 -0.05 -0.45 -0.26 time, in unit intervals (ui) note: 1 unit interval = 648 nanoseconds --0.12 --0.15
mt9076b data sheet 26 zarlink semiconductor inc. figure 7 - pulse template (g.703)(e1) time (nanoseconds) -499 -253 -175 -175 -78 0 175 220 499 752 --- --- time u.i. -.77 -.39 -.27 -.27 -.12 0 .27 .34 .77 1.16 --- --- normalized amplitude .05 .05 .8 1.2 1.2 1.05 1.05 -.05 .05 .05 --- --- table 3 - maximum curve for figure 5 time (nanoseconds) -499 -149 -149 -97 0 97 149 149 298 395 603 752 time u.i. -.77 -.23 -.23 -.15 0 .15 .23 .23 .46 .61 .93 1.16 normalized amplitude -.05 -.05 .5 .9 .95 .9 .5 -.45 -.45 -.26 -.05 -.05 table 4 - minimum curve for figure 5 269 ns 244 ns 194 ns 219 ns 488 ns nominal pulse 120 110 90 100 80 50 20 0 -10 -20 percentage of nominal peak voltage
mt9076b data sheet 27 zarlink semiconductor inc. 1.3 20 mhz clock the mt9076 requires a 20 mhz clock. this may be provided by a 50 ppm oscillator as per figure 8. figure 8 - clock oscillator circuit alternatively, a crystal oscillator may be used. a complete oscillator circuit made up of a crystal, resistors and capacitors is shown in figure 9. the crystal specification is as follows. frequency: 20 mhz tolerance: 50 ppm oscillation mode: fundamental resonance mode: parallel load capacitance: 32 pf maximum series resistance: 35 ? approximate drive level: 1 mw figure 9 - crystal oscillator circuit 1.4 phase lock loop (pll) the mt9076 contains a pll, which can be locked to either an input 4.096 mhz clock or the extracted line clock. the pll will attenuate jitter from less than 2.5 hz and roll-off at a rate of 20 db/decade. its intrinsic jitter is less than 0.02 ui. the pll will meet the jitter transfer characteri stics as specified by at&t document tr 62411 and the relevant recommendations as shown in figure 3. osc1 osc2 (open) 20 mhz out vdd gnd +3.3 v .1 f osc1 osc2 20 mhz 1m ? 56 pf 39 pf 1 h* 100 ? note: the 1 h inductor is optional
mt9076b data sheet 28 zarlink semiconductor inc. figure 10 - tr 62411 jitter attenuation curve 2.0 clock jitter attenuation modes mt9076 has three basic jitter attenuation m odes of operation, se lected by the bs/ls and s/fr /exclki control pins. ? system bus synchronous mode ? line synchronous mode ? free-run mode depending on the mode selection above, th e pll can either attenuate transmit cl ock jitter or the receive clock jitter. table 5 shows the appropriate configur ation of each control pin to achi eve the appropriate mode and jitter attenuation capability of the mt9076. in system bus synchronous mode, pins c4b and f0b are always configured as inputs, while in the line synchronous and free-run modes c4b and f0b are configured as outputs. referring to the mode names given in table 5 the bas ic operation of the jitter attenuation modes are: ?in system bus synchronous mode an external clock is applied to c4b . the applied clock is dejittered by the internal pll before being used to synchronize the tr ansmitted data. the clock extracted (with no jitter attenuation performed) from the receive data can be monitored on pin exclk. mode name bs/ls s/fr /exclki note system bus synchronous 1 1 pll locked to c4b line synchronous 0 1 pll locked to exclk free-run x 0 pll free - running table 5 - selection of clock jitt er attenuation modes using the m/s and ms/fr pins db -0.5 0 19.5 jitter attenuation (db) 10 40 400 10 k -20 db/decade frequency (hz)
mt9076b data sheet 29 zarlink semiconductor inc. ?in line synchronous mode, the clock extracted from the receive data is dejittered using the internal pll and then output on pin c4b . pin exclk provides the extracted receiv e clock before it has been dejittered. the transmit data is synchronous to the clean receive clock. ?in free-run mode the transmit data is synchronized to the internally generated clock. the internal clock is output on pin c4b . the clock signal extracted from the receive dat a is not dejittered and is output directly on exclk. 2.1 jitter attenuator fifo in system bus synchronous operation, a data buffer is required between the jittere d input clock and the clean transmit clock. in normal t1 mode, t he transmit slip buffer performs this function. in t1 ima mode, the transmit slip buffer is unused, instead a jitter attenuator fifo is employed. in an e1 mode system bus synchronous configuration, the jitter atte nuator fifo is always used. in this case the c4b signal clocks the data into the fifo, the pll de-jitters the c4b clock and the resulting clean c4b signal clocks the data out of the fifo. the ja meets the jitter transfer characteristics as proposed by etsi ets 300 011, g.735 and the relevant recommendations as shown in figure 10. the ja fifo dept h can be selected to be from 16 to 128 words deep, in multiples of 16 (2-bit) words. its read pointer can be centered by changing the jfc bit (address 13h of page 02h) to provide maximum jitter tolerance. if t he read pointer should come within 4 bits of either end of the fifo, the read clock frequency will be increased or decreased by 0.0625 ui to correct the situation. the maximum time needed to centre is t max = 3904 ? depth ns, where depth is the selected ja fi fo depth. during this time the ja will not attenuate jitter. 2.2 ima mode 2.2.1 t1 mode in t1 ima mode, neither the transmit nor the receive slip buffers are activated. channel associated signaling (cas) and hdlc operation is not supported. the input pin c4b accepts a 1.544 mhz clock and it clocks incoming data from dsti into a jitter attenuator fifo. this clock is dejitt ered with the internal pll. the dejittered clock clocks data out of the fifo for transmission onto the line. receive clock (1.544 mhz) and data is extracted from the line and routed to pins exclk and dsto respectively. the receive clock exclk is not dejitter ed before being driven off chip. for operation in ima mode, the mt 9076 should be programmed in system bus synchronous mode (bs/ls and s/fr /exclki set high). 2.2.2 e1 mode in e1 ima mode neither the transmit nor the receiv e slip buffers are activated. the input pin c4b accepts a 2.048 mhz clock and it clocks incoming data from dsti into a jitter attenuator fifo. this clock is dejittered with the internal pll. the dejittered clock cl ocks data out of the fifo for tran smission onto the line. receive clock (2.048 mhz) and data is extracted from the line and routed to pins exclk and dsto respectively. the receive clock exclk is not dejittered before being driven off chip. fo r operation in ima mode, the mt9076 should be programmed in system bus synchronous mode (bs/ls and s/fr /exclki set high). 3.0 the digital interface 3.1 t1 digital interface in t1 mode, ds1 frames are 193 bits long and are transmitt ed at a frame repetition rate of 8000 hz, which results in an aggregate bit rate of 193 bits x 8000/sec= 1.544 mbits /sec. the actual bit rate is 1.544 mbits/sec +/-50 ppm optionally encoded in b8zs format. the zero suppression control register (page 1, address 15h,) selects either b8zs encoding, forced one stuffing or alternate mark in version (ami) encoding. basic frames are divided into 24 time slots numbered 1 to 24. each time slot is 8 bits in length and is transmitted most sign ificant bit first (numbered bit 1). this results in a single time slot data rate of 8 bits x 8000/sec. = 64 kbits/sec.
mt9076b data sheet 30 zarlink semiconductor inc. it should be noted that the zarlink st-bus has 32 channels numbered 0 to 31. when mapping to the ds1 payload only the first 24 time slots and the last (time slot 31, for the overhead bit) of an st-bus are used (see table 6). all unused channels are tristate. when signaling information is written to the mt9076 in t1 mode using st-bus control links (as opposed to direct writes by the microport to the on - board signaling regist ers), the csti channels corresponding to the selected dsti channels streams are used to transmit the signaling bits. since the maximum number of signaling bi ts associated with any channel is 4 (in the case of abcd), only half a csti channel is required for sourcing t he signaling bits. the choice of which half of the channel to use is selected by the control bit msn (page 01h address 14h). the same control bit selects which half of the csto channel will contain receive signaling information (t he other nibble in the channel being tristate). unused channels are tristate. the most significant bit of an eight bit st-bus channel is numbered bit 7 (s ee zarlink application note msan-126). therefore, st-bus bit 7 is synonymous with ds1 bit 1; bit 6 with bit 2: and so on. 3.2 frame and superframe structure in t1 mode 3.2.1 multiframing in t1 mode, ds1 trunks contain 24 bytes of serial voic e/data channels bundled with an overhead bit. the frame overhead bit contains a fixed repeat ing pattern used to enable ds1 rece ivers to deliniate frame boundaries. overhead bits are inserted once per frame at the beginni ng of the transmit frame boundary. the ds1 frames are further grouped in bundles of frames, generally 12 (for d4 applications) or 24 frames (for esf - extended superframe applicat ions) deep. table 7 and table 8 illustrate the d4 and esf fram e structures respectively. for d4 links the frame structure cont ains an alternating 101010... pattern inserted into every second overhead bit position. these bits are intended for determination of frame boundaries, and they are referred to as ft bits. a separate fixed pattern, repeating every superframe, is interleaved with the ft bits. this fixed pattern (001110), is used to deliniate the 12 frame superframe. these bits are re ferred to as the fs bits. in d4 frames # 6 and #12, the lsb of each channel byte may be replaced with a bit (fra me #6) and b bit (frame #12) signaling information. for esf links the 6 bit framing pattern 001011, inserted into every 4th overhead bit position, is used to deliniate both frame and superframe boundaries. frames #6, 12, 18 and 24 contain the a, b, c and d signaling bits, respectively. a 4 khz data link is embedded in the overhead bit position, interleaved betw een the framing pattern sequence (fps) and the transmit crc-6 remainder (from th e calculation done on the pr evious superframe), see table 8. the slc-96 frame structure is similar to the d4 fram e structure, except a faci lity management overlay is superimposed over the erstwhile fs bits, see table 9. the protocol appropriate for the application is sele cted via the framing mode selection word, address 10h of master control page 1. in t1 mode, mt9076 is capable of generating the overhead bi t framing pattern and (for esf links) the crc remainder for transmission onto the ds1 tr unk. the beginning of the tr ansmit multiframe may be determined by any of the following criteria: ds1 timeslots 12345678910111213141516 voice/data channels (dsti/o and csti/o) 0123456789101112131415 ds1 timeslots 1718192021222324------- - voice/data channels (dsti/o and csti/o) 16 17 18 19 20 21 22 23 24 x 25 x 26 x 27 x 28 x 29 x 30 x 31 sbit table 6 - st-bus vs. ds1 to channel relationship(t1)
mt9076b data sheet 31 zarlink semiconductor inc. (i) it may free - run with th e internal multiframe counters; (ii) the multiframe counters may be reset with the external hardware pin txmf . if this signal is not synchronous with the current transmit frame count it may cause the far end to go temporarily out of sync. (iii) under software control (by setting the txsync bit in page 01 address 12h) the transmit multiframe counters will be synchronized to the framing pattern pr esent in the overhead bits multiplexed into channel 31 bit 0 of the incoming 2.048 mb/s digital stream dsti . note that the overhead bits extracted from the receive signal are multiplexed into outgoing dsto channel 31 bit 0. (iv) in slc - 96 mode the transmit frame counters synchr onize to the framing pattern clocked in on the txdl input frame # ft fs signaling 11 20 30 40 51 61a 70 81 91 10 1 11 0 12 0 b table 7 - d4 superframe structure(t1) frame # fps fdl crc signaling 1x 2cb1 3x 40 5x 6cb2a 7x 80 9x 10 cb3 11 x 12 1 b 13 x 14 cb4 15 x 16 0 17 x 18 cb5 c 19 x 20 1 table 8 - esf superframe structure (t1)
mt9076b data sheet 32 zarlink semiconductor inc. 3.3 e1 digital interface pcm 30 (e1) basic frames are 256 bits long and are transmitted at a frame repe tition rate of 8000 hz, which results in an aggregate bit rate of 256 bits x 8000/sec = 2.048 m bits/sec. the actual bit rate is 2.048 mbits/sec +/-50 ppm encoded in hdb3 format. the hdb3 control bit (page 01 h, address 15h, bit 5) selects either hdb3 encoding or alternate mark inversion (ami) encoding. basic frames are divided into 32 time slots numbered 0 to 31, see figure 43 on page 168. each time slot is 8 bits in length and is transmitted most signific ant bit first (numbered bit 1). this results in a single time slot data rate of 8 bits x 8000/sec. = 64 kbits/sec. it should be noted that the zarlink st-bus also has 32 cha nnels numbered 0 to 31, but the most significant bit of an eight bit channel is numbered bit 7 (see zarlink applic ation note msan-126). therefore, st-bus bit 7 is synonymous with pcm 30 bit 1; bit 6 with bit 2: and so on (figure 44). pcm 30 time slot 0 is reserved for basi c frame alignment, crc-4 multiframe ali gnment and the communication of maintenance information. in most configurations time sl ot 16 is reserved for either channel associated signaling 21 x 22 cb6 23 x 24 1 d frame # ft fs notes frame # ft fs notes frame # ft fs notes 11 251 c491 2 0 r 26 x o 50 s s = spoiler bits 30 e270 n510 40s28xc52s 51 y291 e531 6 0 n 30 x n 54 c c = maintenance field bits 70 c310 t550 81h32xr56c 91 r331 a571 10 1 o 34 x t 58 c 11 0 n 35 0 o 59 0 12 1 i 36 x r 60 a a = alarm field bits 13 1 z 37 1 61 1 14 0 a 38 x f 62 a 15 0 t 39 0 i 63 0 16 0 i 40 x e 64 l l = line switch field bits 17 1 o 41 1 l 65 1 18 0 n 42 x d 66 l 19 0 43 0 67 0 20 1 d 44 x b 68 l 21 1 a 45 1 i 69 1 22 1 t 46 x t 70 l 23 0 a 47 0 s 71 0 24 1 48 s 72 s s = spoiler bits table 9 - slc-96 framing structure(t1) frame # fps fdl crc signaling table 8 - esf superframe structure (t1) (continued)
mt9076b data sheet 33 zarlink semiconductor inc. (cas or abcd bit signaling) or comm on channel signaling (ccs). the remain ing 30 time slots are called channels and carry either pcm encoded voice signals or digital data. channel alignment and bit numbering is consistent with time slot alignment and bit numbering. however, channels are numbered 1 to 30 and relate to time slots as per table 10. 3.3.1 basic frame alignment time slot 0 of every basic frame is reserved for basic frame alignment and contai ns either a frame alignment signal (fas) or a non-frame alignment signal (nfas). fas and nfas occur in time slot zero of consecutive basic frames as shown in table 10. bit two is used to disti nguish between fas (bit two = 0) and nfas (bit two = 1). basic frame alignment is initiated by a search for the bit sequence 0011011 which appears in the last seven bit positions of the fas, see t he frame algorithm section. bit position one of the fas can be either a crc-4 remainder bit or an international usage bit. bits four to eight of the nfas (i.e., s a4 - s a8 ) are additional spare bits which may be used as follows: ?s a4 to s a8 may be used in specific point-to-point applications (e.g., transcoder equipments conforming to g.761) ?s a4 may be used as a message-based data link for operations, maintenance and performance monitoring ?s a5 to s a8 are for national usage a maintenance channel or data link at 4,8,12,16,or 20 khz for selected s a bits is provided by the mt9076 in e1 mode to implement these functions . note that for simplicity all s a bits including s a4 are collectively called national bits throughout this document. bit three (designated as ?a?), the remote alarm indication (rai), is used to indicate the near end basic frame synchronization status to the far end of a link. under normal oper ation, the a (rai) bit should be set to 0, while in alarm condition, it is set to 1. bit position one of the nfas can be eit her a crc-4 multiframe alignment signal , an e-bit or an international usage bit. refer to an approvals laboratory and national standards bodies for specific requirements. pcm 30 timeslots 0 1,2,3. ..15 16 17,18,19,... 31 voice/data channels (dsti/o and csti/o) 0 1,2,3...15 16 17,18,19,... 31 table 10 - st-bus vs. pcm-30 to channel relationship(e1)
mt9076b data sheet 34 zarlink semiconductor inc. table 11 - fas and nfas structure 3.3.2 crc-4 multiframing in e1 mode the primary purpose for crc-4 multiframing is to provide a verification of the curr ent basic frame alignment, although it can also be used for other functions such as bit error rate esti mation. the crc-4 multiframe consists of 16 basic frames numbered 0 to 15, an d has a repetition rate of 16 frames x 125 microseconds/frame = 2 msec. crc-4 multiframe alignment is based on the 001011 bit seq uence, which appears in bit position one of the first six nfass of a crc-4 multiframe. the crc-4 multiframe is divided into two submultiframes , numbered 1 and 2, which are each eight basic frames or 2048 bits in length. the crc-4 frame alignment verification functions as follows. initially, the crc-4 operation must be activated and crc-4 multiframe alignment must be achiev ed at both ends of the link. at the loca l end of a link, all the bits of every transmit submultiframe are passed thr ough a crc-4 polynomial (multiplied by x 4 then divided by x 4 + x + 1), which generates a four bit remainder. this remainder is inserted in bit position one of the four fass of the following submultiframe before it is transmitted (see table 12). the submultiframe is then transmitted and, at the far end, the sa me process occurs. that is, a crc-4 remainder is generated for each received submultiframe. these bits are co mpared with the bits received in position one of the four fass of the next received submultiframe. this pr ocess takes place in both directions of transmission. when more than 914 crc-4 errors (out of a possible 1000) are counted in a one second interval, the framing algorithm will force a search for a new basic frame al ignment. see frame algorithm section for more details. the result of the comparison of the received crc-4 re mainder with the locally generated remainder will be transported to the far end by the e-bits. therefore, if e 1 = 0, a crc-4 error was discovered in a submultiframe 1 received at the far end; and if e 2 = 0, a crc-4 error was discovered in a submultiframe 2 received at the far end. crc crc frame/type pcm 30 channel zero 12345678 sub multi frame 1 0/fas c 1 0011011 1/nfas 01as a4 s a5 s a6 s a7 s a8 2/fas c 2 0011011 3/nfas 01as a4 s a5 s a6 s a7 s a8 4/fas c 3 0011011 5/nfas 11as a4 s a5 s a6 s a7 s a8 6/fas c 4 0011011 7/nfas 01as a4 s a5 s a6 s a7 s a8 sub multi frame 2 8/fas c 1 0011011 9/nfas 11as a4 s a5 s a6 s a7 s a8 10/fas c 2 0011011 11/nfas 11as a4 s a5 s a6 s a7 s a8 12/fas c 3 0011011 13/nfas e 1 1as a4 s a5 s a6 s a7 s a8 14/fas c 4 0011011 15/nfas e 2 1as a4 s a5 s a6 s a7 s a8 indicates position of crc-4 multiframe alignment sign a
mt9076b data sheet 35 zarlink semiconductor inc. no submultiframe sequence numbers or re-transmission capabilities are s upported with layer 1 pcm 30 protocol. see itu-t g.704 and g.706 for more details on the operation of crc-4 and e-bits. there are two crc multiframe alignment al gorithm options selected by the autc control bit (address 10h, page 01h). when autc is zero, automatic crc-to-non-crc in terworking is selected. when autc is one and arai is low, if crc-4 multiframe alignment is not found in 400 msec, the transmit rai will be continuously high until crc-4 multiframe alignment is achieved. the control bit for transmit e bits (te, address 11h of page 01h) will have the same function in both states of autc . that is, when crc-4 synchronization is not achieved the state of the transmit e-bits will be the same as the state of the te control bit. when crc-4 synchronization is achieved the transmit e-bits will function as per itu-t g.704. table 12 outlines the operation of the autc , arai and talm control bits of the mt9076. table 12 - operation of autc, arai and talm control bits (e1 mode) 3.3.3 cas signaling multiframing in e1 mode the purpose of the signaling multifra ming algorithm is to provide a scheme that will allow the association of a specific abcd signaling nibble with the appropriate pcm 30 channel. time slot 16 is reserved for the communication of channel associ ated signaling (cas) informat ion (i.e., abcd signaling bi ts for up to 30 channels). refer to itu-t g.704 and g.732 for more details on cas multiframing requirements. a cas signaling multiframe consists of 16 basic frames (numbered 0 to 15), which results in a multiframe repetition rate of 2 msec. it should be noted that the boundaries of the sign aling multiframe may be completely distinct from those of the crc-4 multiframe. cas multiframe alignment is based on a multiframe alignment signal (a 0000 bit sequence), which occurs in the most significant nibble of time slot 16 of basic frame 0 of the cas multiframe. bit 6 of this time slot is the multiframe alarm bit (usually designated y). w hen cas multiframing is acquired on the receive side, the transmit y-bit is zero; when cas multiframi ng is not acquired, the transmit y-bit is one. bits 5, 7 and 8 (usually designated x) are spare bi ts and are normally set to one if not used. autc arai talm description 0 0 x automatic crc-interworking is acti vated. if no valid crc mfas is being received, transmit rai will flicker high with every reframe (8 msec.), this cycle will continue for 400 msec., then transmit rai will be low co ntinuously. t he device will stop searching for crc mfas, continue to transmit crc-4 remainders, stop crc-4 processing, indicate crc-to-non- crc operation and transmit e-bits to be the same state as the te control bit (page 01h, address 16h). 0 1 0 automatic crc-interworking is activat ed. transmit rai is low continuously. 0 1 1 automatic crc-interworking is activated. transmit rai is high continuously. 1 0 x automatic crc-interworking is de-activ ated. if no valid crc mfas is being received, transmit rai flickers high with every reframe (8 msec.), this cycle continues for 400 msec, then transmit rai becomes high continuously. the device continues to search for crc mfas and transmit e-bits are the same state as the te control bit. when crcsyn = 0, the crc mfas search is terminated and the transmit rai goes low. 1 1 0 automatic crc-interworking is de-activat ed. transmit rai is low continuously. 1 1 1 automatic crc-interworking is de-activat ed. transmit rai is high continuously.
mt9076b data sheet 36 zarlink semiconductor inc. time slot 16 of the remaining 15 basic frames of the cas mu ltiframe (i.e., basic frames 1 to 15) are reserved for the abcd signaling bits for the 30 payload ch annels. the most significant nibble s are reserved for channels 1 to 15 and the least significant nibbles are reserved for channels 16 to 30. that is, time slot 16 of basic frame 1 has abcd for channel 1 and 16, time slot 16 of basi c frame 2 has abcd for channel 2 and 17 , through to time slot 16 of basic frame 15 has abcd for channel 15 and 30. 4.0 mt9076 access and control 4.1 the control port interface the control and status registers of the mt9076 are acce ssible through a non-multiplexed parallel microprocessor port. the parallel port may be configured for motoro la style control signals (by setting pin int/mot low) or intel style control signals (by setting pin int/mot high). 4.2 control and status register access the controlling microprocessor gains access to specif ic registers of the mt9076 through a two step process. first, writing to the command/address register (car) selects one of the 15 pages of control and status registers (car address: ac4 = 0, ac3-ac0 = don't ca re, car data d7 - d0 = page number). second, each page has a maximum of 16 registers that are addressed on a read or write to a non-car address (non-car: address ac4 = 1, ac3-ac0 = register address, d7-d0 = data). once a page of memory is selected, it is only necessary to write to the car when a different page is to be accessed. see the ac electrical characteristics section. table 13 - page summary please note that for micr oprocessors with read/write cycles less than 200 ns, a wait state or a dummy operation (for c programming) between two succes sive read/write operat ions to the hdlc fifo is required. table 13 associates the mt9076 control and stat us pages with access and page descriptions. page address d 7 - d 0 register description processor access st-bus access 00000001 (01h) master control r/w - - - 00000010 (02h) r/w 00000011 (03h) master status r - - - 00000100 (04h) r/w 00000101 (05h) per channel transmit signaling r/w csti 00000110 (06h) per channel transmit signaling r/w csti 00000111 (07h) per time slot control - - - 00001000 (08h) per time slot control r/w - - - 00001001 (09h) per channel receive signaling r/w csto 00001010 (0ah) per channel receive signaling r/w csto 00001011 (0bh) hdlc0 control and status r/w - - 00001011 (0ch) hdlc1 control and status r/w - - 00001011 (0dh) hdlc2 control and status r/w - - 00001011 (0eh) tx national bit buffer r/w - - 00001011 (0fh) rx national bit buffer r - -
mt9076b data sheet 37 zarlink semiconductor inc. 4.3 identification code the mt9076 shall be identified by the code 01111000, read from the identification code status register (page 03h, address 1fh). 4.3.1 st-bus streams in t1 mode, there is one control and one status st-bus stream that can be used to program / access channel associated signaling nibbles. csto contains the receiv ed channel associated signaling bits, and for those channels whose per time slot control word bit 1 ?rpsig? is set low, csti is used to control the transmit channel associated signaling. the dsti and dsto streams contain the transm it and receive voice and digital data. only 24 of the 32 st-bus channels are used for each of dsti, dsto, csti and csto. in each case individual channel mapping is as illustrated in table 6, ?st-bus vs. ds1 to channel relationship(t1),? on page 30. in e1 mode, st-bus streams can also be used to access c hannel associated signaling ni bbles. csto contains the received channel associated signaling bits (e.g., itu-t r1 and r2 signaling), and for those channels whose per time slot control word bit 1 ?rpsig? is set low, csti is used to control the transmit channel associated signaling. the dsti and dsto streams contain the transmit and receive voice and digital data. only 30 of the 32 st-bus channels are used for each of dsti, dsto, csti and csto. in each case individual channel mapping is as illustrated in table 10 time slot to chann el relationship. 5.0 reset operat ion (initialization) the mt9076 can be reset using the hardware reset pin (pin 11 in plcc, pin 64 in lqfp) or the software reset bit rst (page 1h, address 1ah). when the device emerges from its reset state it will begin to function with the default settings described in table 14 (t1) table 15 (e1). all cont rol registers are set to 00h. a reset operation takes 1 full frame (125 us) to complete. function status mode d4 loopbacks deactivated slc-96 deactivated zero coding deactivated line codes deactivated data link serial mode signaling cas registers ab/abcd bit debounce deactivated interrupts masked error insertion deactivated hdlcs deactivated counters cleared transmit data all ones table 14 - reset status(t1)
mt9076b data sheet 38 zarlink semiconductor inc. table 15 - reset status (e1) 6.0 transmit data all ones (txao ) operation the txao (transmit all ones) pin allows the pri interface to transmit an all ones signal under hardware control. 7.0 data link operation 7.1 data link operation in e1 mode in e1 mode, mt9076 has a user defined 4, 8, 12, 16 or 20 kbit/s data link for transport of maintenance and performance monitoring information across the pc m 30 link. this channel functions using the s a bits (s a4 ~s a8 ) of the pcm 30 timeslot zero non-frame alignment signal (nfas). since the nfas is transmitted every other frame - a periodicity of 250 microseconds - th e aggregate bit rate is a multiple of 4 kb/s. as there are five s a bits independently available for this data link, the bit rate wi ll be 4, 8, 12, 16 or 20 kb/s, depending on the bits selected for the data link (dl). the s a bits used for the dl are selected by setting the appropriate bits, s a4 ~s a8 , to one in the data link select word (page 01h, address 17h, bits 4-0). access to the dl is provided by pins txdlclk, txdl, rxdlclk and rxdl, which allow easy interfacing to an external controller. data to be transmit onto the line in the s a bit position is clocked in from th e txdl pin (pin 65 in plcc, pin 47 in lqfp) with the clock txdlclk (pin 64 in plcc, pin 46 pi n lqfp). although the aggregat e clock rate equals the bit rate, it has a nominal pulse width of 244 ns, and it clocks in the txdl as if it were a 2.048 mb/s data stream. the clock can only be active during bit times 4 to 0 of the stbus frame. the txdl input signal is clocked into the mt9076 by the rising edge of txdlclk. if bits are select ed to be a part of the dl, all other programmed functions for those s a bit positions are overridden. function status mode termination loopbacks deactivated transmit fas c n 0011011 transmit non-fas 1/s n 1111111 transmit mfas (cas) 00001111 data link deactivated crc interworking activated signaling cas registers abcd bit debounce deactivated interrupts masked rxmf output signaling multiframe error insertion deactivated hdlcs deactivated counters cleared transmit data all ones
mt9076b data sheet 39 zarlink semiconductor inc. the rxdlclk signal (pin 39 - plcc, pin 14 - lqfp) is deri ved from the receive extracted clock and is aligned with the receive data link output rxdl. the hdb3 decoded receive data, at 2.048 mbit/s, is cl ocked out of the device on pin rxdl (pin 40 in plcc, pin 15 in lq fp). in order to facilitate the attachment of this data stream to a data link controller, the clock signal rxdlclk consists of posit ive pulses, of nominal width of 244 ns, during the s a bit cell times that are selected for the data link.this selection is made by programming address 17h of master control page 01h. no dl data will be lost or re peated when a receive frame s lip occurs. see ac electr ical characteristics for timing requirements. 7.2 data link operation in t1 mode slc-96 and esf protocol allow for carrier messages to be embedded in the overhead bit position. the mt9076 provides 3 separate means of controlling these data link s. see data link control word - address 12h, page 1h. ? the data links (transmit and receive) may be sourced (sunk) from an external controller using dedicated pins on the mt9076 in t1 mode (enabled by setting the bit 7 - edl of the data link control word). ? bit oriented messages may be transmit and received via a dedicated txbom register (page 1h, address 13h) and a rxbom (page 3h, address 15h). transmissi on is enabled by setting bit 6 - biomen in the data link control word. bit - oriented messages may be periodically interrupted (up to once per second) for a duration of up to 100 milliseconds. this is to acco mmodate bursts of message - oriented protocols. see table 16 for message structure. table 16 - message oriented performance report structure (t1.403 and t1.408) octet #87654321content 1 f l a g 01111110 2 s a p i c / r ea 00111000 or 00111010 3 t e i ea 00000001 4 c o n t r o l 00000011 5 g3lvg4u1u2g5slg6 t 0 6 fe se lb g1 r g2 nm ni t 0 7 g3lvg4u1u2g5slg6 t 0 -1 8 fe se lb g1 r g2 nm ni t 0 -1 9 g3lvg4u1u2g5slg6 t 0 -2 10 fe se lb g1 r g2 nm ni t 0 -2 11 g3 lv g4 u1 u2 g5 sl g6 t 0 -3 12 fe se lb g1 r g2 nm ni t 0 -3 13 f c s variable 14
mt9076b data sheet 40 zarlink semiconductor inc. 7.2.1 external data link in t1 mode, mt9076 has two pairs of pins (txdl and txdlclk, rxdl and rxdlclk) dedicated to transmitting and receiving bits in the selected overhead bit positions . pins txdlclk and rxdlclk are clock outputs available for clocking data into the mt9076 (for transmit) or external device (for receive informat ion). each clock operates at 4 khz. in the slc-96 mode the optional se rial data link is multiplexed into t he fs bit position. in the esf mode, the serial data link is multiplexed into odd frames, i.e., the fdl bit positions. 7.2.2 bit - oriented messaging in t1 mode, mt9076 bit oriented messaging may be selected by setting bit 6 (biomen) in the data link control word (page 1h, address 12h). the transmit data link will contain the repeat ing serial data stream 111111110xxxxxx0 where the byte 0xxxxxx0 originates fr om the user programmed regi ster ?transmit bit oriented message? - page 1h address 13h. the receive biom register ?receive bit oriented message? - page 3h, address 15h, will contain the last received valid message (the 0xxxxxx0 portion of the incoming serial bit stream). to prevent spurious inputs from creating false messages, a new message must be present in 7 of the last 10 appropriate byte positions before being loaded into t he receive biom register. when a new message has been received, a maskable interrupt (maskable by setting bit 1 low in interrupt mask word three - page 1h, address 1eh) may occur. 8.0 floating hdlc channels mt9076 has three embedded hdlc controllers (hdlc0, hdlc1, hdlc2) each of which includes the following features: ? independent transmit and receive fifo's; ? receive fifo maskable interrupts for nearly full (pr ogrammable interrupt levels) and overflow conditions; ? transmit fifo maskable interrupts for nearly empty (programmable interrupt levels) and underflow conditions; ? maskable interrupts for transmit end-of-packet and receive end-of-packet; note: address interpretation 00111000 00111010 00000001 sapi = 14, c/r = 0 (ci) ea = 0 sapi = 14, c/r = 1(carrier) ea = 0 tei = 0, ea =1 control interpretation 00000011 unacknowledged information transfer one second report interpretation g1 = 1 g2 =1 g3 =1 g4 =1 g5 =1 g6 =1 se=1 fe-=1 lv=1 sl=1 lb=1 u1,u2=0 r=0 nmni=00,01,10,11 crc error event =1 1 < crc error event < 5 5 < crc error event < 10 10 < crc error event < 100 100 < crc error event < 319 crc error event > 320 severely - errored framing event >=1 frame synchronization bit error event >=1 line code violation event >=1 slip event >=1 payload loopback activated under study for sync. reserved - set to 0 one second module 4 counter fcs variable interpretation crc16 frame check sequence
mt9076b data sheet 41 zarlink semiconductor inc. ? maskable interrupts for receive bad-frame (includes frame abort); ? transmit end-of-packet and frame-abort functions. each controller may be attached to any of the active 64 kkb/ s channels (24 in the case of t1, 31 in the case of e1). hdlc0 may also be attached to the fdl in a t1 esf link by connecting it to phantom channel 31 when programming the hdlc select word. if hdlc0 is attached to channel 0 in e1 mode, only the activated sa bits (as per the multiframe and data selection word) will be transmit and received by the controller. 8.1 channel assignment in t1 mode, any ds1 channel can be connected to either of hdlc0,1 or 2, operating at 56 or 64 kb/s. setting control bit h1r64 (address 12 h on page 01h) high selects 64 kb/s operation for all hdlcs. setting this bit low selects 56 kb/s for all hdlc. interrupts from any of the hdlcs are masked when they are disconnected. in e1 mode, all pcm-30 channels except channel 0 can be connected to either of hdlc0,1 or 2. hdlc1 and hdlc2 operate at 64 kb/s. hdlc0 operat es at 64 kb/s when connected to any of channels 1 to 31. when connected to channel 0 hdlc0 operates at 4, 8, 12, 16 or 20 kb/s depending on the number of activated sa bits. hdlcs can be activated by programming the hdlc sele ct words (page 02h, addresses 19h, 1ah and 1bh for hdlc0, hdlc1 and hdlc2 respectively). 8.2 hdlc description the hdlc handles the bit oriented packet ized data transmission as per x.25 leve l two protocol defined by ccitt. it provides flag and abort sequence generation and detect ion, zero insertion and deletion, and frame check sequence (fcs) generation and detection. a single byte, dual byte and all call address in the received frame can be recognized. access to the receive fcs and inhibiting of transmit fcs for terminal adaptation are also provided. each hdlc controller has a 128 byte deep fifo associated with it. the status and interrupt flags are programmable for fifo depths that can vary from 16 to 128 bytes in steps of 16 bytes. these and other features are enabled through the hdlc cont rol registers on page 0bh and 0ch. 8.2.1 hdlc frame structure in t1 mode or e1 mode, a valid hdlc frame begins with an opening flag, contains at least 16 bits of address and control or information, and ends with a 16 bit fcs followed by a closing flag. data formatted in this manner is also referred to as a ?packet?. refer to table 17: hdlc frame format all hdlc frames start and end with a unique flag sequence ?0 1111110?. the transmitter generates these flags and appends them to the packet to be transmitted. the receiv er searches the incoming dat a stream for the flags on a bit- by-bit basis to establish frame synchronization. the data field consists of an address field, control field and information field. the address field consists of one or two bytes directly following the opening flag. the control fi eld consists of one byte directly following the address field. the information field immediately follows the control field and consists of n bytes of data. the hdlc does not distinguish between the control and info rmation fields and a packet does not ne ed to contain an information field to be valid. the fcs field, which precedes the clos ing flag, consists of two bytes. a cyclic red undancy check utilizing the crc-ccitt standard generator polynomial ?x 16 +x 12 +x 5 +1? produces the 16-bit fcs. in the transmitter the fcs is flag (7e) data field fcs flag (7e) one byte 01111110 n bytes n 2 two bytes one byte 01111110 table 17 - hdlc frame format
mt9076b data sheet 42 zarlink semiconductor inc. calculated on all bits of the address and data field. the comp lement of the fcs is transmi tted, most significant bit first, in the fcs field. the receiver calculates the fcs on the incoming packet address, data and fcs field and compares the result to ?f0b8?. if no transmission errors are detected and the packet betwe en the flags is at least 32 bits in length then the address and data are entered in to the receive fifo minus the fcs which is discarded. 8.2.2 data transparency (zero insertion/deletion) transparency ensures that the contents of a data pack et do not imitate a flag, go-ahead, frame abort or idle channel. the contents of a transmitted frame, between the flags, is examined on a bit-by-bit basis and a 0 bit is inserted after all sequences of 5 contiguous 1 bits (includi ng the last five bits of the fcs). upon receiving five contiguous 1s within a frame the re ceiver deletes the following 0 bit. 8.2.3 invalid frames a frame is invalid if one of the following four condition s exists (inserted zeros are not part of a valid count): ? if the fcs pattern generated from the received data does not match the ?f0b8? pattern then the last data byte of the packet is written to the re ceived fifo with a ?bad packet? indication. ? a short frame exists if there are less than 25 bits betw een the flags. short frames are ignored by the receiver and nothing is written to the receive fifo. ? packets which are at least 25 bits in length but less than 32 bits between the flags are also invalid. in this case the data is written to the fifo but the la st byte is tagged with a ?bad packet? indication. ? if a frame abort sequence is detected the packet is invalid . some or all of the current packet will reside in the receive fifo, assuming the packet length before the abort sequence was at least 26 bits long. 8.2.4 frame abort the transmitter will abort a current pa cket by substituting a zero followed by seven contiguous 1s in place of the normal packet. the receiver will abor t upon reception of seven contiguous 1s occurring between the flags of a packet which contains at least 26 bits. note that should the last received by te before the frame abort end with cont iguous 1s, these are included in the seven 1s required for a receiver abort. this means that t he location of the abort sequence in the receiver may occur before the location of the abort sequenc e in the originally transmitted pack et. if this happens then the last data written to the receive fifo will no t correspond exactly with the last byte sent before the frame abort. 8.2.5 interframe time fill and link channel states when the hdlc transmitter is not sending pa ckets it will wait in one of two states ? interframe time fill state: this is a continuous seri es of flags occurring between frames indicating that the channel is active but that no data is being sent. ? idle state: an idle channel occurs when at least 15 contiguous 1s are transmitted or received. ? in both states the transmitter will exit the wait state when data is loaded into the transmitter fifo. 8.2.6 go-ahead a go ahead is defined as the pattern ?011111110? (contig uous 7fs) and is the occurrence of a frame abort sequence followed by a zero, outside of the boundaries of a normal packet. being able to distinguish a proper (in packet) frame abort sequence from one occurring outside of a packet allows a higher level of signaling protocol which is not part of the hdlc specifications.
mt9076b data sheet 43 zarlink semiconductor inc. 8.3 hdlc functional description the hdlc transceiver can be reset by either the power re set input signal or by the hrst control bit in the test control register (software reset). when reset, the hdlc c ontrol registers are cleared, re sulting in the transmitter and receiver being disabled. the receiver and tran smitter can be enabled independent of one another through control register 1. the transceiver in put and output are enabled when the enable control bits in control register 1 are set. transmit to receive loopback as well as a rece ive to transmit loopback are also supported. transmit and receive bit rates and enables can operate independently. in mt9076 the transceiver can operate at a continuous rate independent of rxcen and txcen (free run mode) by setting the frun bit of control register 1. received packets from the serial interface are sectioned into bytes by an hdlc receiver that detects flags, checks for go-ahead signals, removes inserted zeros, performs a cyclical redundancy check (crc) on incoming data, and monitors the address if required. pack et reception begins upon detection of an opening flag. the resulting bytes are concatenated with two status bits (rq9, rq8) and placed in a receiver first-in-first-out (rx fifo); a buffer register that generates status and interr upts for microprocessor read control. in conjunction with the control circuitry, the microprocessor writes data bytes into a tx buffer register (tx fifo) that generates status and interrupts. packet transmission begins when the microprocessor writes a byte to the tx fifo. two status bits are added to the tx fifo for transmitter c ontrol of frame aborts (fa) and end of packet (eop) flags. packets have flags appended, zeros inserted, and a crc, also referred to as frame checking sequence (fcs), added automatically during serial trans mission. when the tx fifo is empt y and finished sending a packet, interframe time fill bytes (continuous flags (7e hex)), or mark idle (conti nuous ones) are transmitted to indicate that the channel is idle. 8.3.1 hdlc transmitter following initialization and enabling, t he transmitter is in the idle channel state (mark idle), continuously sending ones. interframe time fill state (flag idle) is selected by setting the mark idle bit in control register 1 high 1 . the transmitter remains in either of these two states until dat a is written to the tx fifo. control register 1 bits eop (end of packet) and fa (frame abort) are set as status bits before the microprocessor loads 8 bits of data into the 10 bit wide fifo (8 bits data and 2 bits status). to chang e the tag bits being loaded in the fifo, control register 1 must be written to before writing to the fifo. however, eop and fa are rese t after writing to the tx fifo. the transmit byte count registers may also be used to tag an end of packet. the total packet size may be programmed to be up to 65,535 bytes. for a packet length of 1 to 255 bytes it is only necessary to write the packet size into the lower transmit byte count register. for a packet length of 256 to 65,535 bytes it is necessary to write the 16 bit binary count into the ex tended transmit byte count register (msbyte) and the lower transmit byte count register (lsbyte). note that the order of writing the upper byte before the lower byte must be observed even when the lower byte is all zero. inte rnal registers are load ed with the number of bytes in the packet and decremented after every write to the tx fifo. when a count of one is reached, the next byte written to the fifo is tagged as an end of packet. the register may be made to cycle through the same count if the packets are of the same length by setting control register 2 bit cycle. if the transmitter is in the idle channel state when data is written to the tx fifo, then an opening flag is sent and data from tx fifo follows. otherwise, data bytes are trans mitted as soon as the current flag byte has been sent. tx fifo data bytes are continuously transmitt ed until either the fifo is empty or an eop or fa status bit is read by the transmitter. after the last bit of the eop byte has been tr ansmitted, a 16-bit fcs is s ent followed by a closing flag. when multiple packets of data are loaded into tx fifo, only one flag is sent between packets. 1. if the mt9076 hdlc transmitter is set up in the mark -idle state (yf2 mi is 1) then it will occasionally (less than 1% of the time) fail to transmit the opening fl ag when it is changed from the disabled state to the enabled state (yf2 txen changed from 0 to 1). a missi ng opening flag will cause the packet to be lost at the receiving end. this problem only affects the first packet transmi tted after the hdlc transmitt er is enabled. subsequent packets ar unaffected.
mt9076b data sheet 44 zarlink semiconductor inc. frame aborts (the transmission of 7f he x), are transmitted by tagging a byte previously written to the tx fifo. when a byte has an fa tag, then an fa is sent instead of that tagged byte. that is, all bytes previous to but not including that byte are sent. after a frame abort, the trans mitter returns to the mark idle or interframe time fill state, depending on the state of the mark idle control bit. tx fifo underrun will occur if the fifo empties and the la st byte did not have either an eop or fa tag. a frame abort sequence will be sent when an underrun occurs. the following list is an example of the transmission of a th ree byte packet (?aa??03??77? hex) (interframe time fill). txcen can be enabled before or after this sequence. the transmitter may be enabled independently of the receiver. this is done by setting the txen bit of the control register. enabling happens immediately upon writing to th e register. disabling using txen will occur after the completion of the transmission of the present packet; the c ontents of the fifo are not cleared. disabling will consist of stopping the transmitter clock. t he status and interrupt r egisters may still be read a nd the fifo and control registers may be written to while the transmitter is dis abled. the transmitted fcs may be inhibited using the tcrci bit of control register 2. in this mode the opening fl ag followed by the data and closing flag is sent and zero insertion still included, but no crc. that is , the fcs is injected by the microprocess or as part of the data field. this is used in v.120 terminal adaptation for synchronous protocol sensitive ui frames. 8.3.2 hdlc receiver after initialization and enabling, the receiver clocks in serial data, continuously checking for go-aheads (0 1111 1110), flags (0111 1110), and idle channel states (at l east fifteen ones). when a flag is detected, the receiver synchronizes itself to the serial stream of data bits, automatically calculating the fcs . if the data length between flags after zero removal is less than 25 bits, then th e packet is ignored so no bytes are loaded into rx fifo. when the data length after zero removal is between 25 and 31 bits, a first byte and bad fcs code are loaded into the rx fifo (see definition of rq8 and rq9 below). for an error-free packet, the result in the crc register should match the hex pattern of?f0b8? when a closing flag is detected. if address recognition is required, the receiver addre ss recognition registers are loaded with the desired address and the adrec bit in the control register 1 is set high. bit 0 of the address registers is used as an enable bit for that byte, thus allowing either or both of the first two by tes to be compared to the expected values. bit 0 of the first byte of the address re ceived (address extension bit) w ill be monitored to determine if a single or dual byte address is being received. if this bit is 0 then a two byte address is being received and then only the first six bits of the first address byte are compared. an all call condition is also monitored for the second address byte; and if received the first address byte is ignored (not compared with mask by te). if the address extension bit is a 1 then a single byte address is being received. in this case, an all call condition is monitored for in the first byte as well as the mask byte written to the comparison r egister and the second byte is ignored. seven bits of address comparison can be realized on the first byte if this is a single byte address by setting the seven bit of control register 2. (a) write ?04?hex to control register 1 (b) write ?aa? hex to tx fifo (c) write ?03?hex to tx fifo (d) write ?34?hex to control register 1 (e) write ?77?hex to tx fifo -mark idle bit set -data byte -data byte -txen; eop; mark idle bits set -final data byte
mt9076b data sheet 45 zarlink semiconductor inc. the following two status register bits (rq8 and rq9) are appended to each data byte as it is written to the rx fifo. they indicate that a good packet has been rece ived (good fcs and no frame abort), or a bad packet with either incorrect fcs or frame abort. th e status and interrupt r egisters should be read bef ore reading the rx fifo since status and interrupt information correspond to the by te at the output of the fifo (i.e., the byte about to be read). the status register bits are encoded as follows: rq9 rq8 byte status 1 1 last byte (bad packet) 0 1 first byte 1 0 last byte (good packet) 0 0 packet byte the end-of-packet-detect (eopd) interrupt indicates that the last byte written to the rx fifo was an eop byte (last byte in a packet). the end-of-packet-read (eopr) interrup t indicates that the byte abo ut to be read from the rx fifo is an eop byte (last byte in a packet). the status re gister should be read to see if the packet is good or bad before the byte is read. a minimum size packet has an 8-bit address, an 8-bi t control byte, and a 16-bit fc s pattern between the opening and closing flags (see section 9.3.2). thus, the absence of a data transmission error and a frame length of at least 32 bits results in the receiver writing a valid packet code with the eop byte into rx fifo. the last 16 bits before the closing flag are regarded as the fcs pattern and will not be transferred to the receiver fifo. only data bytes (address, control, information) are loaded into the rx fifo. in the case of an rx fifo overflow, no clocking occurs until a new opening flag is received. in other words, the remainder of the packet is not clocked into the fifo. also, the top byte of the fifo will not be written over. if the fifo is read before the reception of the next packet then reception of that pack et will occur. if two beginning of packet conditions (rq9=0;rq8=1) are seen in the fifo , without an intermediate eop status, then overflow occurred for the first packet. the receiver may be enabled independently of the transmitte r. this is done by setting the rxen bit of control register 1. enabling happens immediately upon writing to the register. disabling using rxen will occur after the present packet has been completely loaded into the fifo. disabling can occur during a packet if no bytes have been written to the fifo yet. disabling will consist of di sabling the internal receive clock. the fifo, status, and interrupt registers may still be read while the receiver is disabled. note that the re ceiver requires a flag before processing a frame, thus if the receiver is enabled in the middle of an incoming packet it will ignore that packet and wait for the next complete one. the receive crc can be monitored in t he rx crc registers. these registers contain the ac tual crc sent by the other transmitter in its original form; that is, msb first and bits inverted. th ese registers are updated by each end of packet (closing flag) received and therefore should be read when an end of packet is received so that the next packet does not overwrite the registers. 9.0 slip buffers 9.1 slip buffer in t1 mode in t1 mode, mt9076 contains two slip buffers, one on the transmit side, and one on the receive side. both sides may perform a controlled slip. the mechanisms that gover n the slip function are a function of backplane timing and the mapping between the st-bus channels and the ds1 channels. the slip mechanisms are different for the transmit and receive slip buffers. the extracted 1.544 mhz clock (exclk) and the internally generated transmit 1.544 mhz clock are distinct. slips on the transmit side ar e independent from slips on the receive side. in ima mode neither the transmit nor receiv e slip buffer is activated.
mt9076b data sheet 46 zarlink semiconductor inc. the transmit slip buffer has data written to it from the near end 2.048 mb/s stream. the data is clocked out of the buffer using signals derived from the transmit 1.544 mhz clock. the tran smit 1.544 mhz clock is always phase locked to the dsti 2.048 mb/s stream. if the system 4.096 mhz clock (c4b ) is internally generated (pin bs/ls low), then it is hard locked to the 1.544 mhz clock. no phase drif t or wander can exist betwe en the two signals - therefore no slips will occur. t he delay through the transmit elas tic buffer is then fixed, and is a function of the relative mapping between the dsti channels and the ds1 timeslots. t hese delays vary with the position of the channel in the frame. for example, ds1 timeslot 1 sits in the elastic buffer for approximately 1 usec and ds1 timeslot 24 sits in the elastic buffer for approximately 32 usec. figure 11 - read and write pointe rs in the transmit slip buffers if the system 4.096 mhz clock (c4b ) is externally generated (pin bs/ls high), the transmit 1.544 mhz clock is phase locked to it, but the pll is designed to filter jitter present in the c4b clock. as a result phase drift will result between the two signals. the delay through the transmit elas tic buffer will vary in acco rdance with the input clock drift, as well as being a function of the relative mapp ing between the dsti channels and the ds1 timeslots. if the read pointers approach the write pointers (to within approximately 1 usec) or the delay through the transmit buffer exceeds 218 usecs a controlled slip w ill occur. the contents of a single fr ame of ds1 data will be skipped or repeated; a maskable interrupt (masked by setting bit 1 - txslpi high in interrupt mask word zero - page 1h, address 1bh) will be generated, and the status bit tsli p (page 3h, address 17h) of msb transmit slip buffer register will toggle. the dire ction of the slip is indicated by bit 6 of the same register (tslpd). the relative phase delay between the system frame boundary and the transm it elastic frame read boundar y is measured every frame and reported in the transmit slip buffer delay register - (page 3h, address 17h). in addition the relative offset between these frame boundaries may be programmed by writi ng to this register. every write to transmit elastic buffer set delay word resets the transmit elastic frame count bit txsbmsb (address 17h, page 3h). after a write the delay through the slip buffer is less than 1 frame in duration. each write operation will result in a disturbance of the transmit ds1 frame boundary, causing the far end to go out of sync. writing bc (hex) into the txsbdly register maximizes the wander tolerance before a controlled slip occurs. under normal operation no slips should occur in write pointer 221 us 4 us 188 us 62 us 129 us 512 bit elastic store 92 us 92 us wander tolerance read pointer read pointer read pointer read pointer 0 us frame 0 frame 1 frame 0 frame 1 frame 0 frame 1 write vectors read vectors minimum delay read vectors - maximum delay 96 us
mt9076b data sheet 47 zarlink semiconductor inc. the transmit path. slips will only occur if the input c4b clock has excess wander, or the transmit elastic buffer set delay word register is initialized too close to the slip pointers after system initialization. the two frame receive elastic buffer is attached betw een the 1.544 mbit/s ds1 receive side and the 2.048 mbit/s st-bus side of the mt9076. besides performing rate conversi on, this elastic buffer is configured as a slip buffer which absorbs wander and low frequency jitter in multi-trunk applications. the received ds1 data is clocked into the slip buffer with the exclk clock and is clocked out of the slip buffer with the system c4b clock. the exclk extracted clock is generated from, and is therefore phase-locked with, the receive ds1 data. in the case of internal mode (pin bs/ls set low) operation, the exclk clock may be phase-locked to the c4b clock by an internal phase locked loop (pll). therefore, in a single trunk system the receive data is in phase with the exclk clock, the c4b clock is phase locked to the e1.5o clock, and the read and writ e positions of the slip buffer track each other. in a multi-trunk slave or l oop-timed system (i.e., pabx application) a single trunk will be chosen as a network synchronizer, which will function as described in the previous par agraph. the remain ing trunks will use the system timing derived from the synchronizer to clock data out of their slip buffers . even though the ds1 signals from the network are synchronous to each other, due to multiplexi ng, transmission impairments and route diversity, these signals may jitter or wander with respect to the sy nchronizing trunk signal. therefore, the exclk clocks of non-synchronized trunks may wander with respect to the exclk clock of the synchronizer and the system bus. network standards state that, within limits, trunk interfaces must be able to receive error-free data in the presence of jitter and wander (refer to network requirements fo r jitter and wander tolerance). the mt9076 will allow 92 usec (140 ui, ds1 unit intervals) of wander and low frequ ency jitter before a fr ame slip will occur. when the c4b and the exclk clocks are not phase-locked, the rate at which data is being written into the slip buffer from the ds1 side may differ from the rate at which it is being read out onto the st-b us. if this situation persists, the delay limits stated in the previous paragraph will be violated and the slip bu ffer will perform a controlled frame slip. that is, the buffer pointers will be automatically adjust ed so that a full ds1 frame is either repeated or lost. all frame slips occur on frame boundaries. the minimum delay through the receive slip buffer is approximately 1 usec and the maximum delay is approximately 249 us. figure 12 illustrates the relationsh ip between the read and write pointers of the receive slip buffer (contiguous time slot mapping) . measuring clockwise from the write pointer, if the read page pointer comes within 8 usec of the write page pointer a frame slip will occu r, which will put the read page pointer 157 usec from the write page pointer. conversely, if the read page pointer moves more than 249 usec from the write page pointer, a slip will occur, which will put the read page pointer 124 u sec from the write page pointer . this provides a worst case hysteresis of 92 usec peak = 142 u.i.
mt9076b data sheet 48 zarlink semiconductor inc. figure 12 - read and write pointers in the receive slip buffers the rslip and rslpd status bits (page 3h, address 13h, bits 7 and 6 respectively) give indication of a receive slip occurrence and direction. a maskable interrupt rxsl pi (page 1h, address 1bh, bit 0 - set high to mask) is also provided. rslip changes state in the event of a slip. if rslpd=0, the slip buffer has overflowed and a frame was lost; if rslpd=1, a underflow cond ition occurred and a frame was repeated. 9.2 slip buffer in e1 mode in e1 mode, in addition to the elastic buffer in the jitter attenuator(ja), another elastic buffer (two frames deep) is present, attached between the receive side and the st-bus si de of the mt9076. this elas tic buffer is configured as a slip buffer which absorbs wander and low frequency jitter in multi-trunk applications. the received pcm 30 data is clocked into the slip buffer with the exclk clock an d is clocked out of the slip buffer with the c4b clock. the exclk extracted clock is generated from, and is therefore phase-locked with, the receive pcm 30 data. in normal operation, the c4b clock will be phase-locked to the exclk clock by a phase locked loop (pll). therefore, in a single trunk system the receive data is in phase with the exclk clock, the c4b clock is phase-locked to the exclk clock, and the read and write positions of the slip buffer will remain fixed wi th respect to each other. in a multi-trunk slave or l oop-timed system (i.e., pabx application) a single trunk will be chosen as a network synchronizer, which will function as described in the previous par agraph. the remain ing trunks will use the system timing derived from the synchronizer to clock data out of their slip buffers. even thou gh the pcm 30 signals from the network are synchronous to each other, due to multiplexi ng, transmission impairments and route diversity, these signals may jitter or wander with respect to t he synchronizing trunk si gnal. therefore, the exclk clocks of non-synchr onizer trunks may wander with respect to the exclk clock of the synchronizer and the system bus. write pointer 249 us 32 us 188 us 62 us 157 us 512 bit elastic store 92 us 92 us wander tolerance read pointer read pointer read pointer read pointer 0 us frame 0 frame 1 frame 0 frame 1 frame 0 frame 1 xxx xxx xxx xxx write vectors read vectors minimum delay read vectors - maximum delay 124 us
mt9076b data sheet 49 zarlink semiconductor inc. network standards state that, within limits, trunk interfaces must be able to receive error-free data in the presence of jitter and wander (refer to network requirements for jitter and wander tolerance). the mt9076 will allow a maximum of 26 channels (208 ui, unit in tervals) of wander and low frequency jit ter before a frame slip will occur. the minimum delay through the receive slip buffer is approximately two channels and the maximum delay is approximately 60 channels (see figure 13). when the c4b and the exclk clocks are not phase-locked, the rate at which data is being written into the slip buffer from the pcm 30 side may differ from the rate at whic h it is being read out onto t he st-bus. if this situation persists, the delay limits stated in the previous paragraph will be violated and the slip buffer will perform a controlled frame slip. that is, the buffer pointers will be automatically adjusted so that a full pcm 30 frame is either repeated or lost. all frame slips occur on pcm 30 frame boundaries. two status bits, rslip and rslpd (page03h, address13h) give indication of a slip occurrence and direction. rslip changes state in the event of a slip. if rslpd=0, the slip buffer has overflowed and a frame was lost; if rslpd=1, a underflow condition occurred and a frame was repeated. a maskable interrupt slpi (page 01h, address 1bh) is also provided. figure 13 illustrates the relationship between the read and write pointers of the receive slip buffer. measuring clockwise from the write pointer, if th e read pointer comes within two channels of the write pointer a frame slip will occur, which will put the read pointer 34 channels from the write pointer. conversely, if the read pointer moves more than 60 channels from the write pointer, a slip will occur, which will put the read pointer 28 c hannels from the write pointer. this provides a worst case hysteresis of 13 channels peak (26 chann els peak-to-peak) or a wander tolerance of 208 ui. figure 13 - read and write po inters in the slip buffers 10.0 framing algorithm 10.1 frame alignment in t1 mode in t1 mode, mt9076 will synchronize to ds1 lines formatted with either the d4 or esf protocol. in either mode the framer maintains a running 3 bit history of received dat a for each of the candidate bit positions. candidate bit positions whose incoming patterns fail to match the predict ed pattern (based on the 3 bi t history) are winnowed out. if, after a 10 bit history has been examined, only one candidat e bit position remains within the framing bit period, the receive side timebase is forced to align to that bit position. if no candidates remain after a 10 bit history, the process is re-initiated. if multiple candidates exist after a 24 bi t history timeout period, the fr amer forces the receive side write pointer 60 ch 2 ch 47 ch 15 ch 34 ch 28 ch 512 bit elastic store 13 ch -13 ch wander tolerance read pointer read pointer read pointer read pointer 26 channels
mt9076b data sheet 50 zarlink semiconductor inc. timebase to synchronize to the next in coming valid candidate bit pos ition. in the event of a reframe, the framer starts searching at the next bit position over. this pr events persistent locking to a mimic as the controller may initiate a software controlled reframe in the event of locking to a mimic. under software control the framing criteria may be tuned (see framing mo de select register, page 1h, address 10h). selecting d4 framing invites a fu rther decision whether or not to include a cross check of fs bits along with the ft bits. if fs bits are checked (by setting control bit cxc high - bit 5 of the framing mode select word, page 1h, address 10h), multiframe alignment is forced at the same time as terminal frame alignment. if only ft bits are checked, multiframe alignment is forced separately, upon detection of the fs bit histor y of 00111 (for normal d4 trunks) or 000111000111 (for slc-96 trunks). for d4 trun ks, a reframe on the multiframe alignment may be forced at any time without affecting terminal frame alignment. in esf mode, the circuit will optionally confirm the crc-6 bits before forcing a new frame alignment. this is programmed by setting control bit cxc high (bit 5 of the framing mode select word, page 1h, address 10h). a crc-6 confirmation adds a minimum of 6 milliseconds to the reframe time. if no crc-6 match is found after 16 attempts, the framer moves to the next valid candidate bi t position (assuming other bit positions contain a match to the framing pattern) or re-initiat es the whole framing procedure (assum ing no bit positions have been found to match the framing pattern). the framing circuit is off - line. during a reframe, the rest of the circuit oper ates synchronous with the last frame alignment. until such time as a new frame alignment is ac hieved, the signaling bits are frozen in their states at the time that frame alignment was lost, and error counting for ft, fs, esf framing pattern or crc-6 bits is suspended. 10.2 frame alignment in e1 mode in e1 mode, mt9076 contains three distinct framing al gorithms: basic frame alig nment, signaling multiframe alignment and crc-4 multiframe alignment. figure 14 is a state diagram that illustrates these algorithms and how they interact. after power-up, the basic frame alignm ent framer will search for a frame al ignment signal (fas) in the pcm 30 receive bit stream. once the fas is detected, the corres ponding bit 2 of the non-fram e alignment signal (nfas) is checked. if bit 2 of the nfas is zero a new search for basi c frame alignment is initiated. if bit 2 of the nfas is one and the next fas is correct, the algor ithm declares that basic frame sync hronization has been found (i.e., page 03h, address 10h, bit 7, sync is zero). once basic frame alignment is acqu ired the signalin g and crc-4 multiframe searches will be initiated. the signaling multiframe algorithm will align to the first mult iframe alignment signal pattern (mfas = 0000) it receives in the most significant nibble of channel 16 (page 3, address 10h, bit 6, mfsync = 0). signaling multiframing will be lost when two consecutive multiframes are received in error. the crc-4 multiframe alignment signal is a 001011 bit s equence that appears in pcm 30 bit position one of the nfas in frames 1, 3, 5, 7, 9 and 11 (see table 11). in order to achieve crc-4 sync hronization two consecutive crc-4 multiframe alignment signals must be received wi thout error (page 03h, address 10h crcsyn = 0). the e1 framing algorithm supports automatic interwor king of interfaces with and without crc-4 processing capabilities. that is, if an interf ace with crc-4 capability, achieves va lid basic frame alignment, but does not achieve crc-4 multiframe alignment by the end of a predefined period, the distant end is considered to be a non-crc-4 interface. when the distant end is a non-crc-4 interface, the near end automatically suspends receive crc-4 functions, continues to transmit crc-4 data to the distant end with its e-bits set to zero, and provides a status indication. naturally, if the distant end initially achi eves crc-4 synchron ization, crc-4 processing will be carried out by both ends. this featur e is selected when control bit autc (page 01h, address 10h) is set to zero.
mt9076b data sheet 51 zarlink semiconductor inc. figure 14 - synchronization state diagram >914 crc errors in one second no 3 consecutive incorrect frame alignment signals yes crc-to-non-crc interworking. maintain primary basic frame alignment. continue to send crc-4 data, but stop crc processing. e-bits set to ?0?. indicate crc-to-non-crc operation. note 7. search for primary basic frame alignment signal rai=1, es=0. out of synchronization verify bit 2 of non-frame alignment signal. parallel search for new basic frame alignment signal. notes 6 & 7. yes yes 400 msec timer expired no crc multiframe alignment * only if crc-4 synchronization is selected and automatic crc-4 interworking is de-selected. ** only if automatic crc-4 interworking is selected. 8 msec. timer expired** crc-to-crc interworking. re-align to new basic frame alignment. start crc-4 processing. e-bits set as per g.704 and i.431. indicate crc synchronization achieved. notes 7& 8. signalling multi-frame alignment primary basic frame synchronization acquired. enable traffic rai=0, e?s=0. start loss of primary basic frame alignment checking. notes 7 & 8. yes crc-4 multi-frame alignment yes verify second occurrence of frame alignment signal. start 8 msec timer. note 7. multiframe synchronization acquired as per g.732. note 7. find two crc frame alignment signals. note 7. check for two consecutive errored multiframe alignment signals. notes 7 & 8. start 400 msec timer. note 7. search for multiframe alignment signal. note 7. no no no yes basic frame alignment acquired no crc multiframe alignment. no crc multiframe alignment. 8 msec. timer expired* rai = 0
mt9076b data sheet 52 zarlink semiconductor inc. 10.2.1 notes for synchronization state diagram (figure 14) 1) the basic frame alignment, signaling multiframe al ignment, and crc-4 multiframe alignment functions operate in parallel and are independent. 2) the receive channel associated signaling bits and signaling multiframe alignment bit will be frozen when multiframe alignment is lost. 3) manual re-framing of the receive basic frame alignm ent and signaling multiframe alignment functions can be performed at any time. 4) the transmit rai bit will be one until basic frame alignment is established, then it will be zero. 5) e-bits can be optionally set to zero until the equi pment interworking relationship is established. when this has been determined one of the following will take place: a) crc-to-non-crc operation - e-bits = 0, b) crc-to-crc operation - e-bits as per g.704 and i.431. 6) all manual re-frames and new basic frame alignment s earches start after the current frame alignment signal position. 7) after basic frame alignment has been achieved, loss of frame alignment will occur any time three consecutive incorrect basic frame alignment signals are received. loss of basic frame alignment will reset the complete framing algorithm. 8) when crc-4 multiframing has been achieved, the pr imary basic frame alignment and resulting multiframe alignment will be adjusted to the basic frame alignment determined during crc-4 synchronization. therefore, the primary basic frame alignment will not be updated during the crc-4 multiframing search, but will be updated when the crc-4 multiframing search is complete. 10.3 reframe 10.3.1 e1 mode the mt9076 will automatically force a refr ame, if three consecutive frame ali gnment patterns or three consecutive non-frame alignment bits are in error. 10.3.2 t1 mode the mt9076 will automatically force a reframe if the fram ing bit error density exceeds the threshold programmed by control bits rs1-0 (framing mode select word page 1h , address 10h). rs1 = rs0 = 0 forces a reframe for 2 errors out of a sliding window of 4 framing bits. rs1 = 0, rs0 = 1 forces a reframe with 2 errors out of 5. rs1 = 1, rs0 = 0 forces a reframe with 2 errors out of 6. rs1 = rs0 = 1 disables the automatic reframe. in esf mode, all framing bits are checked. in d4 mode, eit her ft bits only (if control bit 2 - fsi - of framing mode select register is set low) or ft and fs bits are checked (fsi set high). if the d4 secondary yellow alarm is enabled (control bit 1 - d4secy of transmit alarm control word p age 1h, address 11h) then the fs bit of frame 12 is not verified for the loss of frame circuit. in e1 or t1 mode, receive transparent mode (selected when bit 3 page 1 address 12h is high) no reframing is forced by the device. the user may initiate a software reframe at any time by setting bit 1, page 1, address 10h high (refr). once the circuit has commenced reframing the signaling bits are fr ozen until multiframe synchronization has been achieved. 11.0 mt9076 channel signaling 11.1 channel signaling in t1 mode in t1 mode, when control bit rben (page 1h, address 14h) is low the mt 9076 will insert abcd or ab signaling bits into bit 8 of every transmit ds0 channel every 6th frame. the ab or abcd signaling bits from received frames 6
mt9076b data sheet 53 zarlink semiconductor inc. and 12 (ab) or from frames 6, 12, 18 and 24 (abcd) will be loaded into an internal storage ram. the transmit ab/ abcd signaling nibbles can be passed eit her via the micro-ports (f or channels with bit 1 set high in the per time slot control word - pages 7h and 8h) or through related channels of the csti serial links, see ?st-bus vs. ds1 to channel relationship(t1)? on page 30. the receive signal ing bits are always mapped to the equivalent st-bus channels on csto. memory pages five and six contain t he transmit ab or abcd nibbles and pages eight and nine the receive ab or abcd nibbles for micro-port cas access. the serial control streams that contain the transmit / rece ive signaling information (csti and csto respectively) are clocked at 2.048 mhz. the number of signaling bits to be transmit / received = 24 (timeslots) x 4 bits per timeslot (abcd) = 24 nibbles. this leaves many unused nibble po sitions in the 2.048 mhz csti / csto bandwidth. these unused nibble locations are tristated. the usage of the bit stream is as fo llows: the signaling bits are inserted / reported in the same csti / csto channels that correspond to the ds1 channels used in dsti / dsto - see table 6, ?st-bus vs. ds1 to channel relationship(t1),? on page 30. the control bit msn (signaling control word, page 01h, address 14h) allows for the abcd bit to use the most significant nibble of csti / csto (msn set high) or the least significant nibble (msn set low). unused nibbles and timeslots are tristate . in order to facilitate multiplexing on the csto control stream, an additional control bit cstoen (signaling control word, page 01h, address 14h) will tristate the whole stream when set low. this control bit is fo rced low with the reset pin. in the case of d4 trunks, only ab bits are reported. the control bits sm1-0 allow the user to program th e 2 unused bits reported on csto in the signaling nibble otherwise occupied by cd signaling bits in esf trunks. a receive signaling bit debounce of 6 msec. can be sele cted (dben set high - signaling control word, page 01h, address 14h). it should be noted that there may be as much as 3 msec. added to this duration because signaling equipment state changes are not synchr onous with the d4 or esf multiframe. if multi - frame synchronization is lost (page 3h, address 10h, bit 6 mfsync = 1) all receive signaling bits are frozen. they will become unfrozen when multi - frame syn chronization is acquired (this is the same as terminal frame synchronization for esf links). when the sigi interrupt is unmasked, irq will become active when a signaling state change is detected in any of the 24 receive channels. the sigi interrupt mask is loca ted on page 1, address 1eh, bit 0 (set high to enable interrupt); and the sigi interrupt vector is located on page 4, address 1eh. 11.2 channel signaling in e1 mode in e1 mode, when control bit txccs is set to one, the mt9076 is in common channel signaling (ccs) mode. when txccs is low it is in channel associated signaling mode (cas). the cas mode abcd signaling nibbles can be passed either via the micro-ports (when rpsig = 1) or through related channels of the csto and csti serial links (when rpsig = 0). memory pages 09h and 0ah contain the receive abcd nibbles and pages 05h and 06h the transmit abcd nibbles for micro-port cas access. in cas operation, an abcd signaling bit debounce of 14 msec. can be selected by writing a one to dbnce control bit. this is consistent with the sig naling recognition time of itu-t q.422. it should be noted that there may be as much as 2 msec. added to this duration because signaling equipment state changes are not synchronous with the pcm 30 multiframe. if multiframe synchronization is lost (page 03h, address 10h, when mfsync = 1) all receive cas signaling nibbles are frozen. receive cas nibbles wi ll become unfrozen when multifra me synchronization is acquired. when the cas signaling interrupt is unmask ed (page 01h, address 1eh, sigim=1), pin irq (pin 12 in plcc, 65 in lqfp) will become active when a signaling nibble state change is detected in any of the 30 receive channels. in ccs mode, the data transmitted on channel 16 is sourced from channel 16 data on dsti.
mt9076b data sheet 54 zarlink semiconductor inc. 12.0 loopbacks in order to meet pri layer 1 requirements and to assist in circuit fault sectioning, the mt9076 has six loopback functions. these are as follows: a) digital loopback (dsti to dsto at the framer/liu interface). bit dlbk = 0 normal; dlbk = 1 activate. b) remote loopback (rtip and rring to ttip and tring respectively at the line side). bit rlbk = 0 normal; rlbk = 1 activate. c) st-bus loopback (dsti to dsto at the system side). bit slbk = 0 normal; slbk = 1 activate. d) payload loopback (rtip and rring to ttip and tring respectively at the system side). bit plbk = 0 normal; plbk = 1 activate. the payload loopback is effectively a physical connection of dsto to dsti within the mt9076. sbit information and the dl originate at the point of loopback. e) metallic loopback. mlbk = 0 normal; mlbk = 1 acti vate, will isolate the external signals rtip and rring from the receiver and internally connect the analo g output ttip and tring to the receiver analog input. f) per time slot local and remote loopback. remote time slot loopback control bit rtsl = 0 normal; rtsl = 1 activate, will loop around transmit st-bus time slots to the dsto stream. local time slot loopback bits ltsl = 0 normal; ltsl = 1 activate, will loop around receive pcm 30 time slots towards the remote pcm 30 end. mt9076 tx dsti dsto system line mt9076 tx dsto system line rx mt9076 tx dsti dsto system line mt9076 tx dsti dsto system line rx mt9076 tx dsti dsto system line rx mt9076 tx dsti dsto system line rx
mt9076b data sheet 55 zarlink semiconductor inc. the digital, remote, st-bus, payload and metallic loopbacks are located on page 1, address 15h - coding and loopback control word. the remote and local time slot loopba cks are controlled through control bits 5 and 4 of the per time slot control words, pages 7h and 8h. 13.0 performance monitoring 13.1 error counters in t1 mode, mt9076 has eight error counters, which can be used for maintenance testing and ongoing measurement of the quality of a ds1 link and to assist t he designer in meeting specifications such as tr62411 and t1.403. all counters can be preset or cleared by writing to the appropriate locations. associated with each counter is a maskable event occurren ce interrupt and a maskable counter overflow interrupt. overflow interrupts are useful when cumulative error c ounts are being recorded. for example, every time the framing bit error counter overflow in terrupt (fero) occurs, 256 frame errors have been received since the last fero (page 04h, address 1dh)interrup t. all counters are cleared and held low by programming the counter clear bit -cntclr - high (bit 4 of the reset control word, page 1h, address 1ah). an alternative approach to event reporting is to mask error events and to enable the 1 se cond sample bit (sample - bit 3 of the reset control word). when this bit is set the counters for change of fram e alignment, loss of frame alignment, line code violation errors, crc errors, errored framing bits, and multiframes out of sync are updated on one second intervals coincident with the maskable one second interrupt timer. in e1 mode, mt9076 has six error counters, which can be used for maintenance testing, and ongoing measurement of the quality of a pcm 30 link and to assist the designer in meeting specifications such as itu-t i.431 and g.821. all counters can be preset or cl eared by writing to the appropriate locations. associated with each counter is a maskable event occurren ce interrupt and a maskable counter overflow interrupt. overflow interrupts are useful when cumu lative error counts are being recorded . for example, every time the frame error counter overflow (fero) interrupt occurs, 256 frame errors have been received since the last fero interrupt. all counters are cleared and held low by programming the counter clear bit (master control page 01h, address 1a, bit 4) high. counter overflows set bits in the counter overflow latch (page 04 h, address 1fh); this latch is cleared when read. the overflow reporting latch (page 04h, address 1fh) c ontains a register whose bits are set when individual counters overflow. these bits stay high until the register is read. 13.2 t1 counters 13.2.1 framing bit error counter (fc7-0) this eight bit counter counts errors in the framing pattern. in esf mode, an y error in the 001011 framing pattern increments the counter. in slc-96 mode any error in the ft bit position is counted. in d4 mode ft errors are always counted, fs bits (except for th e sbit in frame 12) may optionally be counted (if control bit fsi is set high - page 1h, address 10h, bit 2). the counter is located on page 4h, address 13h. there are two maskable interrupts associated with the fr aming bit error measurement. a single error may generate an interrupt (enable by setting feri high - bit 7 of the interrupt mask word one, page 1h, address 1ch). a counter overflow interrupt may be enabled by setting control bit feom high - bit 2 of interrupt mask word two (page 1h, address 1dh). 13.2.2 out of frame/change of frame alignment counter (oof3-0/cofa3-0) this register space is shared by two nibbles. one is the count of out of fram e events. the other independent counter is incremented when, after a resynchronization, the frame alignment has moved. this count is reported in page 4, address 13h.
mt9076b data sheet 56 zarlink semiconductor inc. there are two interrupts associated with the change of frame alignment counter. a single error may generate an interrupt (enable by setting cofai high - bit 4 of the interrupt mask word one, page 1h, address 1ch). a counter overflow interrupt may be enabled by setting control bit cofao high - bit 4 of interrupt mask word two (page 1h, address 1dh). there is one interrupt associated with the out of frame counter. a counter overflow interrupt may be enabled by setting control bit oofo high - bit 5 of interrupt mask word two (page 1h, address 1dh). 13.2.3 multiframes out of sync counter (mfoof7-mfoof0) this eight bit counter mfoof7 - mfoof0 is located on page 4 address 15h, and is incremented once per multiframe (1.5 ms for d4 and 3 ms for esf) during the time that the framer is out of terminal frame synchronization. there is a maskable interrupt associated with the meas urement. a counter overflow interrupt may be enabled by setting control bit mfoofo high - bit 1 of in terrupt mask word two (page 1h, address 1dh). 13.2.4 crc-6 error counter (cc15-0) crc-6 errors are recorded by this counter for esf links. this 16 bit counter is located on page 4, addresses 18h and 19h. there are two maskable interrupts associated with t he crc error measurement. a single error may generate an interrupt (enable by setting crci high - bit 6 of the inte rrupt mask word one, page 1h, address 1ch). a counter overflow interrupt may be ena bled by setting control bit crco high - bit 6 of interrupt mask word two (page 1h, address 1dh). 13.2.5 line code violation error counter (lcv15-lcv0) if the control bit exz (page 1 address 12h bit 5) is set low, the line code violation error counter will count bipolar violations that are not part of b8zs encoding. if the cont rol bit exz (page 1 address 12h bit 5) is set high, the line code violation error counter will count both bipolar viol ations that are not part of b8zs encoding and each occurrence of excess zeros (more than 7 successive zeros in a received b8zs encoded data stream and more than 15 successive zeros in a non-b8zs encoded stream). this counter lcv15-lcv0 is 16 bits long (page 4h, addresses 16h and 17h) and is incremented once for ev ery line code violation rece ived. it should be noted that when presetting or clearing the lcv e rror counter, the least significant lc v counter address should be written to before the most significant location. this counter will suspend operation when terminal frame synchronization is lost if the control bit oofp is set (bit 2, address 1ah - reset control word). there are two maskable interrupts associated with the li ne code violation error measur ement. a single error may generate an interrupt (enable by setti ng lcvi high - bit 3 of the interrupt mask word one, page 1h, address 1ch). a counter overflow interrupt may be enabled by setting c ontrol bit lcvo high - bit 3 of interrupt mask word two (page 1h, address 1dh). 13.2.6 prbs error counter (ps7-0) there are two 8 bit counters associated with prbs comparison ; one for errors and one for time. any errors that are detected in the receive prbs will increment the prbs error rate counter of page 04h, address 10h. writes to this counter will clear an 8 bi t counter, psm7-0 (page 01h, address 11h) which counts receive crc multiframes. a maskable prbs counter overflow (prbso) interrupt (pa ge 1, address 1dh) is associated with this counter. 13.2.7 crc multiframe counter for prbs (psm7-0) this eight bit counter counts receive crc multiframes. it can be directly loaded via the microport. the counter will also be automatically cleared in the even t that the prbs error counter is written to by the microport. this counter is located on page 04h, address 11h.
mt9076b data sheet 57 zarlink semiconductor inc. 13.3 e1 counters 13.4 errored fas counter (efas7-efas0) an eight bit frame alignment signal error counter efas7 - efas0 is located on page 04h address 13h, and is incremented once for every receive frame alignment signal that contains one or more errors. there are two maskable interrupts asso ciated with the frame alignment sig nal error measurement. feri (page 01h, address 1ch) is initiated when t he least significant bit of the errored frame alignment signal counter toggles, and ferro (page 01h, address 1dh) is initiated when the counter changes from ffh to 00h. 13.5 e-bit counter (ec15-0) e-bit errors are counted by the mt9076 in order to support compliance with it u-t requirements. this sixteen bit counter is located on page 04h, addresses 14h and 15h respec tively. it is incremented by single error events, with a maximum rate of twice per crc-4 multiframe. there are two maskable interrupts associated with th e e-bit error measurement. ebi (page 1, address 1ch) is initiated when the least significant bit of the counter toggles, and febeo (page 01h, address 1dh) is initiated when the counter overflows. 13.6 line code violat ion error counter (lcv15-lcv0) if the control bit exz (page 1 address 12h bit 5) is set low, the line code violation error counter will count bipolar violations that are not part of hdb3 en coding. if the control bit exz (page 1 address 12h bit 5) is set high, the line code violation error counter will co unt both bipolar violati ons that are not part of hdb3 encoding and each occurrence of excess zeros (more than 3 successive zeros in a received hdb3 encoded data stream and more than 15 successive zeros in a non-hdb3 encoded stream). this counter lcv15-lcv0 is 16 bits long (page 4h, addresses 16h and 17h) and is incremented once for ev ery line code violation rece ived. it should be noted that when presetting or clearing the lcv e rror counter, the least significant lc v counter address should be written to before the most significant location. this counter will suspend operation when terminal frame synchronization is lost if the control bit oofp is set (bit 2, address 1ah - reset control word). in e1 mode, there are two maskable interrupts associat ed with the line code violation error measurement. lcvi (page 01h, address 1ch) is initiated when the l significan t bit of the lcv error counter toggles. lcvo (page 01h, address 1dh) is initiated when the counter changes from ffffh to 0000h. 13.7 crc-4 error counter (cc15-0) crc-4 errors are counted by the mt9076 in order to sup port compliance with itu-t r equirements. this sixteen bit counter is located on page 04h, addresses 18h and 19h in e1 mode. it is incremented by single error events, which is a maximum rate of twice per crc-4 multiframe. there is a maskable interrupt associated with the crc error measurement. crcim (page 01h, address 1ch) is initiated when the least significant bi t of the counter toggles, and crcom (page 01h, address 1dh) is initiated when the counter overflows. 13.8 prbs error counter (ps7-0) there are two 8 bit counters associated with prbs comparison ; one for errors and one for time. any errors that are detected in the receive prbs will increment the prbs error rate counter of page 04h, address 10h. writes to this counter will clear an 8 bi t counter, psm7-0 (page 01h, address 11h) which counts receive crc multiframes. a maskable prbs counter overflow (prbso) interrupt (pa ge 1, address 1dh) is associated with this counter.
mt9076b data sheet 58 zarlink semiconductor inc. 13.9 crc multiframe counter for prbs (psm7-0) this eight bit counter counts receive crc-4 multiframes. it can be directly loaded via th e microport. the counter will also be automatically cleared in the even t that the prbs error counter is written to by the microport. this counter is located on page 04h, address 11h. 14.0 error insertion in t1 mode, six types of error conditions can be inserted into the transmit ds1 data stream through control bits, which are located on page 1, address 19h - error inserti on word. these error events include the bipolar violation errors (bpve), crc-6 errors (crce), ft errors (fte), fs errors (fse) , payload (perr) and a loss of signal condition (lose). the lose function overrides the b8zs encoding function. in e1 mode, six types of error conditions can be inserted into the transmit pcm 30 data stream through control bits, which are located on page 01h, address 19h. these error events include the bipolar violation errors (bpve), crc-4 errors (crce), fas errors (fase), nfas errors (nf se), payload (perr) and a lo ss of signal error (lose). the lose function overrides the hdb3 encoding function. 15.0 per time slot control words there are two per time slot control pages (addresses ah and bh) (t1/e1) occupying a total of 24 unique addresses in t1 mode or a total of 32 unique addresses in e1 mode. each address controls a matching timeslot on the 24 ds1 channels (t1) or 32 pcm-30 channels (e1) and the equi valent channel data on the receive (dsto) data. for example address 0 of the first per time slot control page contains program control for transmit timeslot 0 and dsto channel 0. e1 mode 15.1 clear channel capability in t1 mode, when bit zero (cc) in the pe r time slot control word is set no bit robbing for the purpose of signaling will occur in this channel. this bit is not used in e1 mode. 15.2 microport signaling when bit one (rpsig) is set, the transmit signaling fo r the addressed channel can only be programmed by writing to the transmit signaling page (pages 5h and 6h) via the mi croport. if zero, the transmit signaling information is constantly updated with the informati on from the equivalent channel on csti. per time slot control word bit 7 bit 0 t1 mode txmsg pci rtsl ltsl ttst rrst rpsig cc txmsg adi rtsl ltsl ttst rrst rpsig - - -
mt9076b data sheet 59 zarlink semiconductor inc. 15.3 per time slot looping any channel or combination of channels may be looped fr om transmit (sourced from dsti) to receive (output on dsto) stbus channels. when bit four (ltsl) in the per ti me slot control word is set the data from the equivalent transmit timeslot is looped back on to the equivalent receive channel. any channel or combination of channels may be looped from receive (sourced from the line data) to transmit (output onto the line) channels. when bit five (rtsl) in the per time slot control word is set the data from the equivalent receive timeslot is looped ba ck onto the equivalent transmit channel. remote timeslot loopback and local timeslot should not be simultaneously activated in the same timeslot. 15.4 prbs testing if the control bit adseq is zero (from master control page 1 - access control word), any channel or combination of transmit channels may be programmed to contain a generated pseudo random bit sequence (2 15 -1). the channels are selected by setting bit three (ttst) , in the per time slot control word. if the control bit adseq is zero, any combination of receive channels may be connected to the prbs decoder (2 15 -1). each error in the incoming sequence causes the pr bs error counter to increment. the receive channels are selected by setting bit 2 (rrst) in the per time slot control word. if prbs is performed during a metallic or external loop around, per time slot contro l words with ttst set should have rrst set as well. 15.5 digital milliwatt if the control bit adseq is one, a digi tal milliwatt sequence (table 18) in t1 mode or (table 19) in e1 mode may be transmitted on any combination of selected channels. the ch annels are selected by setting bit three (ttst), in the per time slot control word. under the same control condition (adseq equal to one), the same digital milliw att sequence is available to replace received data on any combination of dsto channels. this is accomplished by setting bit two (rrst) in the per time slot control word for the corresponding channel . bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 bit 8 00011110 00001011 00001011 00011110 10011110 10001011 10001011 10011110 table 18 - digital milliwatt pattern (t1)
mt9076b data sheet 60 zarlink semiconductor inc. table 19 - a-law digital milliwatt pattern (e1) 15.6 per channel inversion when bit six (pci) in the per time slot control word is set both transmit and receive data for the selected channel is inverted before going onto th e line / dsto respectively. 15.7 transmit message when bit seven (txmsg) in the per time slot control word is set the data transmit in the selected channel is sourced from the transmit message word in master control page 1. 16.0 alarms the following alarms are detected by the receiver in t1 mode. each may generate a maskable interrupt: ? d4 yellow alarm - in d4 mode there are two possible yell ow alarm signals. if control bit d4secy is set low, (page 1h, address 11h, bit 1) the criteria for a yellow al arm is an excess of?0?s (more than 285) in bit position 2 of incoming ds0 channels during an integration peri od of 1.5 milliseconds. it is cleared after more than 3?1?s are detected in bit position 2 of normal data in a 1.5 millisecond integration period. if d4secy is set high the secondary yellow alarm is selected. the detecti on criteria becomes 2 consecutive?1?s in the sbit position of the 12th frame. ? esf yellow alarm - in esf mode, there are two possible yellow alarm signals. if control bit jyel (page 1h, address 14h, bit 0) is set low the criteria for a yellow alarm is a pattern 00000000 11111111 in seven or more code words out of ten, if jyel is set high, the criteria for a yellow alarm is a pattern 11111111 11111111 in seven or more code words out of ten. ? all ones - this bit (page 3h, address 11h, bit 3) is set if less than six zeros are received on the incoming line data during a 3 ms interval ? loss of signal - a loss of signal condition occurs when the receive signal level is lower than 20 db or 40 db below the nominal signal level for at least a millisecond or when 32 or 192 (control bit l32z (page 01h, address 19h, bit 1) consecutive zeros have been received. a loss of signal condition will terminate when an average ones density of at least 12.5% has been rece ived over a period of 193 contiguous pulse positions starting with a pulse. the loss of signal is reported in the receive signal status word - (page 3, address 16h bit 4). the following alarms are detected by the receiver in e1 mode. each may generate a maskable interrupt: ? remote alarm indication (rai) - bit 3 (a) of the receive nfas; ? alarm indication signal (ais) - unframed all ones signal for at least a double frame (512 bits) or two double frames (1024 bits); ? channel 16 alarm indication signal - all ones signal in channel 16; bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 bit 8 00110100 00100001 00100001 00110100 10110100 10100001 10110001 10110100
mt9076b data sheet 61 zarlink semiconductor inc. ? auxiliary pattern - 101010... pattern for at least 512 bits; ? loss of signal - a loss of signal condition occurs when the receive signal level is lower than 20 db or 40 db (by setting the bit elos on page 02h, address 10h, bit 3) below the nominal signal level for more than a millisecond or when more than 32 or 192 (control bit l32z (page 01h, address 19h 9 bit 1) zeros have been received in a row. a loss of signal condition will terminate when an average ones density of at least 12.5% has been received over a period of 192 cont iguous pulse positions starting with a pulse. ? remote signaling multiframe alarm - (y-b it) of the multiframe alignment signal. the alarm reporting latch (page 04h, address 12h) contains a register whose bits are se t high for selected alarms. these bits stay high until the register is read. this allo ws the controller to record intermittent or sporadic alarm occurrences. 16.1 automatic alarms in e1 mode, the transmission of rai and signaling multif rame alarms can be made to function automatically from control bits arai and auty (page 01h, address 10h). when arai = 0 and basic frame synchronization is lost (sync = 1), the mt9076 will automatically transmit the rai al arm signal to the far end of the link. the transmission of this alarm signal will cease when basic frame alignment is acquired. when auty = 0 and signaling multiframe alignment is not acquired (mfsync = 1), the mt9076 will automatically transmit the multiframe alarm (y-bit) signal to the far en d of the link. this transmission will cease when signaling multiframe alignment is acquired. 17.0 detected events 17.1 t1 mode 17.1.1 severely errored frame event in t1 mode, bit 5 page 3h address 10h toggles whenever a sliding window detects 2 framing errors events (ft or esf) in a sliding window of 6. 17.1.2 loop code detect t1.403 defines sf mode line loopback activate and deac tivate codes. these codes are either a framed or un-framed repeating bit sequence of 00 001 for activation or 001 for deactivation. the standard goes on to say that these codes will persist for five seconds or more befor e the loopback action is taken. in t1 mode mt9076 will detect both framed and unframed line activate and de-activate codes even in the presence of a ber of 3 x 10-3. line loopback disable detect - lldd - in the alarm status word (bit 0 address 11h of page 3h) will be asserted when a repeating 001 patter n (either framed or unframed) has persisted for 48 milliseconds. li ne loopback enable detect lled in the alarm status word will be asserted w hen a repeating 00001 pattern (either framed or unframed) has persisted for 48 milliseconds. 17.1.3 pulse density violation detect in t1 mode, bit 2 of address 11h on page 3h (pdv) toggles if the receive data fails to meet ones density requirements. it will toggle upon detection of 16 consecutive zeros on the line data, or if there are less than n ones in a window of 8(n+1) bits - where n = 1 to 23. 17.1.4 timer outputs in t1 mode, mt9076 has a one second timer derived from the 20 mhz oscillator pins. the timer may be used to trigger interrupts for t1.403/408 performance messaging.
mt9076b data sheet 62 zarlink semiconductor inc. 17.2 e1 mode 17.2.1 consecutive fram e alignment patterns (confap) two consecutive frame alignment signals in error. 17.2.2 receive frame alignment signals these bits are received on the pcm 30 and link in bit posit ions two to eight of time sl ot 0 - frame alignment signal. these signals form the frame al ignment signal and should be 0011011. 17.2.3 receive non frame alignment signal this signal is received on the pcm 30 and link in bit posi tion two of time slot 0 - non frame alignment signal. 17.2.4 receive multiframe alignment signals these signal are received on the pcm 30 and link in bit posi tion one to four of time slot 16 of frame zero of every signaling multiframe. 18.0 interrupts the mt9076 has an extensive suite of maskable interrupts, which are divided into four categories based on the type of event that caused the interrupt. each inte rrupt has an associated mask and interrupt bit. when an unmasked interrupt event occurs, irq will go low and one or more bits of the appropriate interrupt register will go high(t1/e1). after each interrupt regist er is read it is automatically cleared. when all interrupt registers are cleared irq will return to a high impedance state. this function can also be accomplished by toggling the inta bit (page 01h, address 1ah, bit 5). all the interrupts of the mt9076 in t1 and e1 mode are maskable. this is accomplished through interrupt mask words zero to three, which are located on page 1, addresses 1bh to 1eh and the (optional) hdlc interrupt mask located at address 16 of page b. after a mt9076 reset (reset pin or rst control bit), all interrupts are masked. all interrupts may be suspended, without changing the in terrupt mask words, by ma king the spnd control bit of page 1, address 1ah high. all interrupts are cleared by forcing the pin txao low 18.1 interrupts on t1 mode interrupt word zero (page 4, address 1bh) bit 7 bit 0 tfsyni mfsyni tsai aisi losi sei txslpi rxslpi interrupt mask word zero (page 1, address 11bh) bit 7 bit 0 tfsynim mfsynim biomtim aisim losim sefim txslpim rxslpim interrupt word one (page 4, address 1ch) bit 7 bit 0 fei crci yeli cofai lcvi prbsi pdvi - - -
mt9076b data sheet 63 zarlink semiconductor inc. 18.2 interrupts on e1 mode interrupt mask word one (page 1, address 1ch) bit 7 bit 0 feim crcim yelim cofaim lcvim prbsim pdvim --- interrupt word two (page 4, address 1dh) bit 7 bit 0 feo crco oofo cofao lcvo prbso mfoofo - - - interrupt mask word two (page 1, address 1dh) bit 7 bit 0 feom crcom oofom cofaom lcvom prbsom prbsmfom mfoofom interrupt word three (page 4, address 1eh) bit 7 bit 0 hdlc0i hdlc1i hdlc2i lcdi 1seci 5seci biomi sigi interrupt mask word three (page 1, address 1eh) bit 7 bit 0 hdlc0im hdlc1im hdlc2im lcdim lsecim 5secim biomim sigim hdlc interrupt status regist er (page b,c, & d, address 17h) bit 7 bit 0 ga rxeop txeop rxfe txfl fatxunder rxff rxovf hdlc interrupt mask register (p age b, c, and d address 16h) bit 7 bit 0 gaim rxeopim txeopim rxfeim txflim fa:txunderim rxffim rxovfim interrupt word zero (page 4, address 1bh) in terrupt mask word zero (page 1, address 1bh) bit 7 bit 0 bit 7 bit 0 tfsyni mfsyni crcsyni aisi losi cefi y1 rxslpi synim mfsym csynim aisim losim cefim yim slpim interrupt word one (page 4, address 1ch) interrupt mask word one (page 1, address 1ch) bit 7 bit 0 bit 7 bit 0 ferri crcerri ebiti ais16i lcvi prbserri auxpi raii ferim crcim emim aisi6im lcvim prbsim auxpim raiim interrupt word two (page 4, address 1dh) interrupt mask word two (page 1, address 1dh) bit 7 bit 0 bit 7 bit 0 ferro crco --- febfo lcvo prbso prbsmfo sai feom crcoim --- eboim lcvcom prbsom prbsmfom saim
mt9076b data sheet 64 zarlink semiconductor inc. 19.0 digital framer mode 19.1 t1 mode setting bit 4 in the configuration c ontrol word (address 10h of master c ontrol page 2) disables the liu and converts the mt9076 into a digital t1 transceiver. the digital 2.048 mb/s st-bus backplane maps into transmit and receive digital 1.544 mb/s streams. the 1.544 mb/s transmit streams may be formatted for single phase nrz (by setting bit 7 of the liu control word - master page 1 high) or two phase nrz. the data rate conversion (between 2.048 mb/s and 1.544 mb/s) is done within the mt9076. the transmit 1.544 mhz clock is internally generated from a pll that locks onto the input c4b clock. this clock is then output on pin e1.5o/e xclk (plcc pin 44 - lqfp pin 22). the digital 1.544 mb/s transmit data is output on pi ns txa and txb (plcc pins 37,38 - lqfp pins 12, 13) with the rising edge of pin exclk. if th e control bit tx8ken is set high (page 2h address 10h bit 2) the pin rxmf /txfp will generate an 8 khz positiv e frame pulse synchronous with the sbit clocked out on txa/txb. receive digital data is clocked in on pins rring and rtip. this data is cl ocked in with the rising e dge of the input 1.544 mhz clock s/fr/exclki (plcc pin 66, lqfp pin 48). 19.2 e1 mode setting bit 4 in the configuration c ontrol word (address 10h of master c ontrol page 2) disables the liu and converts the mt9076 into a digital e1 transceiver. the digital 2.048 mb/s st-bus backplane maps into transmit and receive digital 2.048 mb/s streams. the 2.048 mb/s tr ansmit data streams may be formatted for single phase nrz (by setting bit 7 of the liu control word - master page 1 high) or two phase nrz. the transmit 2.048 mhz clock is derived from the input c4b clock. this clock is then output on pin exclk (pl cc pin 44 - lqfp pin 22). the digital 2.048 mb/s transmit data is output on pins txa and txb (p lcc pins 37,38 - lqfp pins 12, 13) with the rising edge of exclk. if the control bit tx8ken is set high (page 2h address 10h bit 2) the pin rxmf /txfp will generate an 8 khz positive frame pulse synchronous with the sbit clocke d out on txa/txb. receive digital data is clocked in on pins rring and rtip. this data is clocked in with the rising edge of the input 2.048 mhz clock s/fr/exclki (plcc pin 66, lqfp pin 48). interrupt word three (page 4, address 1eh) inte rrupt mask word three (page 1, address 1eh) bit 7 bit 0 bit 7 bit 0 hdlc0i hdlc1i hdlc2i jai 1seci 5seci rcri sigi hdlc0im hdlc1im hdlc2im lcdim lsecim 5secim biomim sigim hdlc interrupt status register (page b, c & d, address 17h) hdlc interrupt mask register (page b, c, & d, address 16h) bit 7 bit 0 bit 7 bit 0 ga rxeop txeop rxfe txfl fa:txunder rxff rx6vf gaim rxeopim txeopim rxfeim txflim fa:txunderim rxffim rxovfim
mt9076b data sheet 65 zarlink semiconductor inc. 20.0 control and status registers 20.1 t1 mode 20.1.1 master control 1 (page 01h) (t1) address (a 4 a 3 a 2 a 1 a 0 ) register function 10h (table 21) framing mode select esf, scl96, cxc, rs1-0, fsi, refr, mfrefr 11h (table 22) transmit alarm control word esfyel, txsecy, d4yel, txao , lua, lda, d4secy, so 12h (table 23) data link control word ed l, biomen, exz, txpdvs, txsync, trsp, jts, h1r64 13h (table 24) transmit bit oriented message biomtx7-0 14h (table 25) signaling control word dstoen, cstoen, rben, dben, msn, sm1-0, jyel 15h (table 26) coding and loopback control word rxb8zs, mlbk,txb8zs,fbs, dlbk, rlbk, slbk, plbk 16h reserved set all bits to zero for normal operation 17h (table 27) transmit elastic buffer set delay word txtsd7-0 18h (table 28) transmit message word txm7-0 19h (table 29) error insertion word bpve, crce, fte, fse, lose, perr, l32z, los/lof 1ah (table 30) reset control word rst, spnd, inta, cntclr, sample, oofp, d20 1bh (table 31) interrupt mask word zero tfsynim, mfsynim, biomtim, aisim, losim, sefim, txslpim, rxslpim 1ch (table 32) interrupt mask word one feim, crcim, yelim, lcvim, cofaim, prbsim, pdvim 1dh (table 33) interrupt mask word tw o feom, crcom, oofom, cofaom, lcvom, prbsom, prbsmfom,mfoofom 1eh (table 34) interrupt mask word three hdlc0im,hdlc1im,hdlc2im,lcdim, 1secim, 5secim, bioim, sigim 1fh (table 35) liu receiver word nrz, res, rxa1-0, rxeq2-0 table 20 - master control 1 (page 1) (t1)
mt9076b data sheet 66 zarlink semiconductor inc. bit name functional description 7 esf extended super frame . setting this bit enables transmission and reception of the 24 frame superframe ds1 protocol. 6 slc96 slc96 mode select . setting this bit enables input and output of the fs bit pattern on the txdl and rxdl pins. frame synchronization is the sa me as in the case of d4 operation. the transmitter will insert a and b bits every 6 frames after synchroniz ing to the fs pattern clocked into txdl. receive fs bits are not monitored for the framing bit error counter. 5cxc cross check . setting this bit in esf mode enables a cross check of the crc-6 remainder before the frame sync hronizer pulls into sync. this process adds at least 6 milliseconds to the frame synchronization time. setting this bit in d4 (not esf) mode enables a check of the fs bits in addition to the ft bi ts during frame synchronization 4 - 3 rs1- 0 reframe select 1 - 0 . these bits set the criteria for an automatic reframe in the event of framing bits errors. the combinations available are: rs1 - 0, rs0 - 0 = sliding window of 2 errors out of 4. rs1 - 0, rs0 - 1 = sliding window of 2 errors out of 5. rs1 - 1, rs0 - 0 = sliding window of 2 errors out of 6. rs1 - 1, rs0 - 1 = no reframes due to framing bit errors. 2fsi fs bit include . only applicable in d4 mode (not esf or slc96). setting this bit causes errored fs bits to be included as framing bit er rors. a bad fs bit will increment the framing error bit counter, and will potentially cause a refr ame (if it is the second bad framing bit out of 5). the fs bit of the receive frame 12 will only be included if d4secy is set. 1refr reframe . a low - to - high transition on this bit causes an automatic reframe. 0mfrefr multiframe reframe . only applicable in d4 or slc96 mode. a low - to - high transition on this bit causes an automatic multiframe reframe. th e signaling bits are frozen until multiframe synchronization is achieved. terminal frame synchronization is not affected. table 21 - framing mode select (t1) (page 1, address 10h)
mt9076b data sheet 67 zarlink semiconductor inc. bit name functional description 7 esfyel esf yellow alarm . setting this bit while in esf mode ca uses a repeating pattern of eight 1?s followed by eight 0?s to be inserted onto t he transmit fdl (japan telecom bit set low - see signalling control word) or sixteen 1?s (japan telecom bit set high). 6 txsecy transmit secondary d4 yellow alarm . setting this bit (in d4 mode) causes the s bit of transmit frame 12 to be set. 5 d4yel d4 yellow alarm . when set bit 2 of all ds0 channels are forced low. 4txao transmit all ones . when low, this control bit forces a framed or unframed (depending on the state of transmit alarm control bit 0) a ll ones to be transmit at ttip and tring. 3lua loop up activate . setting this bit forces transmission of a framed or unframed (depending on the state of transmit alarm contro l bit 0) repeating pattern of 00001. 2lda loop down activate . setting this bit forces transmiss ion of a framed or unframed (depending on the state of transmit alarm cont rol bit 0) repeating pattern of 001. 1 d4secy d4 secondary alarm . set this bit for trunks employing the secondary yellow alarm. the fs bit in the 12th frame will not be used for counting error ed framing bits. if a one is received in the fs bit position of the 12th frame a secondar y yellow alarm detect bit will be set. 0so overhead bits override . if set, this bit forces the overhead bits to be inserted as an overlay on any of the following alar m conditions: i) transmit all ones, ii) loop up code insertion, iii) loop down code insertion. table 22 - transmit alarm control word (t1) (page 1, address 11h)
mt9076b data sheet 68 zarlink semiconductor inc. bit name functional description 7edl enable data link . setting this bit multiplexes the serial stream clocked in on pin txdl into the fdl bit position (esf mode) or the fs position (d4 mode). 6 biomen bit oriented messaging enable . setting this bit enables transmission of bit - oriented messages on the esf facility data link. the actual message transmit at any one time is contained in the biomtx register (page 1, address 13h). the receive bit - oriented message register is always active, although the interrupt associated with it may be masked. 5 exz excess zeros. setting this bit causes each occurrence of received excess zeros to increment the line code violation counter. excess zeros ar e defined as 8 or more successive zeros for b8zs encoded data, or 16 or more successive zeros for non-b8zs encoded data. 4txpdvs transmit pulse density violation screen. setting this bit causes ones to be injected into the transmit data in the event that a violation of the ones density requirement is detected in the outgoing data. 3txsync transmit synchronization . setting this bit causes the transmit multiframe boundary to be internally synchronized to the incoming sbits on dsti channel 31 bit 0. 2trsp transparent mode . setting this bit causes unframed da ta to be transmit from dsti channels 0 to 23 and channel 31 bit 0 to be transmit transparently onto the ds1 line. unframed data received from the ds1 line is piped out on dsto channels 0 to 23 and channel 31 bit 0. 1jts japan telecom synchronization . setting this bit forces the inclusion of sbits in the crc-6 calculation. 0h1r64 hdlc rate select . setting this pin high while an hdlc is activated on a timeslot enables 64 kb/s operation. setting this pin low while an hdlc is activated enables 56 kb/s operation (this prevents data corruption due to forced bit stuffing). table 23 - data link control word (t1) (page 1, address 12h) bit name functional description 7 - 0 biomtx7-0 transmit bit oriented message . the contents of this regist er are concatenated with a sequence of eight 1?s and continuously transm it in the fdl bit position of esf trunks. normally the leading bit (bit 7) and last bit (bit 0) of this register are set to zero. table 24 - transmit bit oriented message (t1) (page 1, address 13h)
mt9076b data sheet 69 zarlink semiconductor inc. bit name functional description 7dstoen dsto enable . if zero pin dsto is tristate. if set the pin dsto is enabled. 6cstoen csto enable . if zero pin csto is tristate. if set the pin csto is enabled. 5 rben robbed bit signaling enable . setting this bit multiplexes the ab or abcd signaling bits into bit position 8 of all ds0 channels every 6th frame. 4 dben debounce enable . setting this bit causes incoming signaling bits to be debounced for a period of 6 to 9 milliseconds bef ore reporting on csto or in t he receive signaling bits page. 3msn most significant nibble . if set to one the most significant nibble of csti and csto are activated. the reporting stream csto contai ns the signaling information for the equivalent channel in the most significant ni bble, and least significant nibble is tristate. if set to zero the least significant nibble is active for csti and csto and the most significant nibble of csto is tristate. 2-1 sm1-0 signaling message . these two bits are used to fill the vacant bit positions available on csto when the 3vjet is operating on a d4 trunk. the first two bits of each reporting nibble of csto contain the ab signaling bits. the last two will contain sm1 and sm0 (in that order). when the 3vjet is connected to esf trunks four signaling bits (abcd) are reported and the bits sm1-0 become unused. 0 jyel japan yellow alarm set this bit high to selects a pattern of 16 ones (11111111 1111111) as the esf yellow alarm, both for the case when an esf yellow alarm is to be transmitted, or in recognizing a received yellow alarm. table 25 - signaling control word (t1) (page 1, address 14h)
mt9076b data sheet 70 zarlink semiconductor inc. bit name functional description 7rxb8zs receive b8zs enable . if one, receive b8zs decoding is enabled. 6mlbk metallic loopback . if one, then rrtip/rring are c onnected directly to ttip and tring respectively. if zero, then this feature is disabled. 5txb8zs transmit b8zs enable . if one, all zero octets are substituted with b8zs codes. 4fbs forced bit stuffing . if set any transmit ds0 channel containing all zeros has bit 7 forced high. 3dlbk digital loopback . if one, then the digital stream to the transmit liu is looped back in place of the digital output of the rece ive liu. data coming out of dsto will be a delayed version of dsti. if zero, this feature is disabled. 2rlbk remote loopback . if one, then all time slots received on rrtip/rring are connected to ttip/tring on the ds1 side of the 3vjet. if zero, then this feature is disabled. 1slbk st-bus loopback . if one, then all time slots of dsti are connected to dsto on the st-bus side of the 3vjet. if zero, then this feature is disabled. see loopbacks section. 0plbk payload loopback . if one, then all time slots received on rtip/rring are connected to ttip/tring on the st-bus side of the 3vjet. if zero, then this feature is disabled. table 26 - coding and loopback control word (t1) (page 1, address 15h) bit name functional description 7-0 txsd7-0 transmit set delay bits 7-0. writing to this register forces a one time setting of the delay through the transmit slip buffer. the delay is defi ned as the time interval between the write of the transmit stbus channel cont aining ds1 timeslot 1 and its subsequent read. the delay is modified by moving the pos ition of the internally g enerated ds1 frame boundary. the delay (when set) will always be less than 1 frame (125 us). this register must be programmed with a non - zero value. table 27 - transmit elastic buffer set delay word (t1) (page 1, address 17h) bit name functional description 7-0 txm7-0 transmit message bits 7 - 0. the contents of this register are transmit into those outgoing ds1 channels selected by the per time slot cont rol registers. table 28 - transmit message word (t1) (page 1, address 18h)
mt9076b data sheet 71 zarlink semiconductor inc. bit name functional description 7 bpve bipolar violation error insertion . a zero-to-one transition of this bit inserts a single bipolar violation error into the transmit ds1 data. a one, zero or one-to-zero transition has no function. 6crce crc-6 error insertion . a zero-to-one transition of this bi t inserts a single crc-6 error into the transmit esf ds1 data. a one, zero or one-to-zero trans ition has no function. 5fte terminal framing bit error insertion . a zero-to-one transition of this bit inserts a single error into the transmit d4 ft pattern or the tr ansmit esf framing bit pattern (in esf mode). a one, zero or one-to-zero transition has no function. 4fse signal framing bi t error insertion . a zero-to-one transition of this bit inserts a single error into the transmit fs bits (in d4 mode only). a one, zero or one-to-zero transition has no function. 3lose loss of signal error insertion . if one, the 3vjet transmits an all zeros signal (no pulses). zero code suppression is overridden. if zero, data is transmitted normally. 2 perr payload error insertion . a zero - to - one transition of this bit inserts a single bit error in the transmit payload. a one, zero or one-to-zero transiti on has no function. 1l32z digital loss of signal selection . if one, the threshold for digital loss of signal is 32 successive zeros. if zero, the threshold is set to 192 successive zeros. 0 los/lof loss of signal or loss of frame selection . if one, pin los will go high when a loss of signal state exits (criteria as per llos status bi t). if low, pin los will go high wh en either a loss of signal or a loss of frame alignment state exits. table 29 - error insertion word (t1) (page 1, address 19h)
mt9076b data sheet 72 zarlink semiconductor inc. bit name functional description 7rst software reset . setting this bit is equivalent to perf orming a hardware reset. all counters are cleared and the control registers are set to their de fault values. this control bit is internally cleared after the reset operation is complete. 6 spnd suspend interrupts . if one, the irq output will be in a high-impedance state and all interrupts will be ignored. if zero, the irq output will function normally. 5inta interrupt acknowledge . setting this pin clears all interrupts and forces the irq pin into high impedance. the control bit itself is then internally cleared. 4 cntclr counter clear . if one, all status error counters are cleared and held low. 3 sample one second sample . setting this bit causes the error co unters (change of fram e alignment, loss of frame alignment, lcv errors, crc errors, severely errored frame events and multiframes out of sync) to be updated on one second intervals coin cident with the one second timer (status page 3 address 12h bit 7). 2 oofp out of frame pause. if set high, this bit will suspend operation of the line code violation counter during an out - of - frame condition; up on achieving terminal frame synchronization the counter will resume normal operation. if set low, the line code violation counter will continue to count errors even if terminal frame synchronization is lost. 1-- reserved. set to zero for normal operation. 0d20 double20. set to zero for normal operation. set high to double clock speed in the hdlc, speeding up microport accesses from 160 ns between consecutive reads/writes to 80 ns between consecutive reads/writes. table 30 - reset control word (t1) (page 1, address 1ah)
mt9076b data sheet 73 zarlink semiconductor inc. bit name functional description 7 tfsynim terminal frame synchronization interrupt mask . when unmasked an interrupt is initiated whenever a change of state of loss of terminal frame synchronization condition exists. if 1 -unmasked, 0 - masked. 6mfsynim multiframe synchronization interrupt mask . when unmasked an interrupt is initiated whenever a change of state of loss of multifra me synchronization condition exist. if 1 - unmasked, 0 - masked 5 biomtim bit oriented message transition interrupt mask . when unmasked an interrupt is initiated whenever a new biom arrives or if the current biom stops transmission. if 1 - unmasked, 0 -masked. 4aisim alarm indication signal interrupt mask. when unmasked a change of state of received all ones condition will initiate an interrupt. if 1 - unmasked, 0 - masked. 3losim loss of signal interrupt mask . when unmasked an interrupt is initiated whenever a change of state of a loss of signal condition exists. if 1 - unmasked, 0 - masked. 2 sefim severely errored frame interrupt mask . when unmasked an interrupt is initiated when a sequence of 2 framing errors out of 6 occurs. if 1 - unmasked, 0 - masked. 1txslpim transmit slip interrupt mask. when unmasked an interrupt is initiated whenever a controlled frame slip occurs in the transmit elas tic buffer. if 1 - unmasked, 0 - masked. 0rxslpim receive slip interrupt mask . when unmasked an interrupt is initiated whenever a controlled frame slip occurs in the receive elastic buffer. if 1 - unmasked, 0 - masked. table 31 - interrupt mask word zero (t1) (page 1, address 1bh)
mt9076b data sheet 74 zarlink semiconductor inc. bit name functional description 7feim framing bit error interrupt mask . when unmasked an interrupt is initiated whenever an erroneous framing bit is detected (provided the circui t is in terminal frame sync). if 1 - unmasked, 0 - masked. 6 crcim crc-6 error interrupt mask . when unmasked an interrupt is initiated whenever a local crc-6 error occurs. if 1 - unmasked, 0 - masked. 5 yelim yellow alarm interrupt mask . when unmasked detection of a yellow alarm triggers an interrupt. if 1 - unmasked, 0 - masked. 4cofaim change of frame alignment interrupt mask . when unmasked an interrupt is initiated whenever a change of frame alignment occurs after a reframe. if 1 - unmasked, 0 - masked. 3lcvim line code violation interrupt mask . when unmasked an interrupt is initiated whenever a line code violation (excluding b8zs bi polar violations encodi ng) is encountered. if 1- unmasked, 0 - masked. 2 prbsim pseudo random bit sequence error interrupt mask . when unmasked an interrupt will be generated upon detection of an error with a channel selected for prbs testing. if 1 - unmasked, 0 - masked. 1pdvim pulse density violation interrupt mask . when unmasked an interrupt is triggered whenever a sequence excess consecutive zeros is received on the line. if 1 - unmasked, 0 - masked. 0- - - unused . table 32 - interrupt mask word one (t1) (page 1, address 1ch)
mt9076b data sheet 75 zarlink semiconductor inc. bit name functional description 7feom framing bit error counter overflow interrupt mask . when unmasked an interrupt is initiated whenever the framing bit error counter changes from ffh to 00h. if 1 - unmasked, 0 - masked. 6 crcom crc-6 error counter overflow interrupt mask. when unmasked an interrupt is initiated whenever the crc-6 error counter changes from ffh to 00h. if 1 - unmasked, 0 - masked. 5 oofom out of frame counter overflow interrupt mask . when unmasked an interrupt is initiated whenever the out of frame counter changes st ate from changes from ffh to 00h. if 1 - unmasked, 0 - masked. 4cofaom change of frame alignment co unter overflow interrupt mask . when unmasked an interrupt is initiated whenever the change of frame alignment counter changes from ffh to 00h. if 1 - unmasked, 0 - masked. 3lcvom line code violation counter overflow interrupt mask . when unmasked an interrupt is initiated whenever the line code violation counter changes from ffh to 00h. if 1- unmasked, 0 - masked. 2 prbsom pseudo random bit sequence error counter overflow interrupt mask . when unmasked an interrupt will be generated whenever the prbs error counter changes from ffh to 00h. if 1 - unmasked, 0 - masked. 1prbsmfom pseudo random bit sequence multiframe counter overflow interrupt mask . when unmasked an interrupt will be generated whenev er the multiframe counter attached to the prbs error counter overflows. ffh to 00h. if 1 - unmasked, 0 - masked. 0 mfoofom multiframes out of sync overflow interrupt mask. when unmasked an interrupt will be generated when the multiframes out of frame counter changes from ffh to 00h. if 1 - unmasked, 0 - masked. table 33 - interrupt mask word two (t1) (page 1, address 1dh)
mt9076b data sheet 76 zarlink semiconductor inc. bit name functional description 7 hdlc0im hdlc0 interrupt mask . when unmasked an interrupt is triggered by an unmasked event in hdlc0. if 1 - unmasked, 0 - masked. 6 hdlc1im hdlc1 interrupt mask . when unmasked an interrupt is triggered by an unmasked event in hdlc1. if 1 - unmasked, 0 - masked. 5 hdlc2im hdlc2 interrupt mask . when unmasked an interrupt is triggered by an unmasked event in hdlc2. if 1 - unmasked, 0 - masked. 4lcdim loop code detected interrupt mask . when unmasked an interrupt is triggered when either the loop up (00001) or loop down (001) code has been detected on the line for a period of 48 milliseconds. if 1 - unmasked, 0 - masked. 31secim one second status interrupt mask. when unmasked an interrupt is initiated when the 1sec status bit (page 3 address 12h bit 7) go es from low to high. if 1 - unmasked, 0 - masked. 25secim five second status interrupt mask . when unmasked an interrupt is initiated when the 5 sec status bit goes from low to hi gh. if 1 - unmasked, 0 - masked. 1 biomim bit oriented message interrupt mask . when unmasked an interrupt is initiated when a pattern 111111110xxxxxx0 has been received on the fdl that is different from the last message. the new message must persist for 8 out the last 10 message positions to be accepted as a valid new message. if 1- unmasked, 0 - masked. 0sigim signaling interrupt mask. when unmasked an interrupt will be initiated w hen a change of state (optionally debounced - see dben in the data link, signaling control word page 1 address 12h) is detected in the signaling bits (ab or abcd) pattern. if 1 - unmasked, 0 - masked. table 34 - interrupt mask word three (t1) (page 1, address 1eh)
mt9076b data sheet 77 zarlink semiconductor inc. bit name functional description 7 nrz nrz format selection . only used in the digital framer only mode (liu is disabled). a one sets the mt9076 to accept a unipolar nrz fo rmat input stream on rxa as the line input, and to transmit a unipolar nrz format stream on txb. a zero causes the mt9076 to accept a complementary pair of dual rail inputs on rxa/rxb and to transmit a complementary pair of dual rail outputs on txa/txb. 6- - - reserved . set this low for normal operation. 5res resistor . set this bit high to connect a 104 ohm internal resistor between rtip and rring. this is activated where an external 20.8 ohm terminating resistor is in use on a t1 line. 4 - 3 rxa1-0 automatic receive equalizer control . these bits should be programmed according to the table below: 00 equalization will be activated using the control bits rxeq2-0. 11 the receive equalizer is turned on and will compensate for loop length automatically. the control bi ts rxeq2-0 will be ignored. 01, 10 reserved for factory purposes. 2 - 0 rxeq2-0 receive equalization select . setting these pins forces a level of equalization of the incoming line data. res2 res1 res0 receive equalization 0 0 0 none 0 0 1 8 db 0 1 0 16 db 0 1 1 24 db 1 0 0 32 db 1 0 1 40 db 1 1 0 48 db 1 1 1 reserved these settings have no effect if either of rxa1 and rxa0 are set to one. table 35 - liu receiver word (t1) (page 1, address 1fh)
mt9076b data sheet 78 zarlink semiconductor inc. 20.1.2 master control 2 (page 02h) (t1) address (a 4 a 3 a 2 a 1 a 0 ) register names 10h (table 37) configuration cont rol word t1/e1, txen, liuen , elos, tx8ken, adseq 11h (table 38) liu tx word cpl, txlb2-0 12h reserved set all bits to zero for normal operation. 13h (table 39) jitter attenuator control word jfc, jfd2-jfd0, jacl 14h reserved set all bits to zero for normal operation. 15h reserved set all bits to zero for normal operation. 16h (table 40) equalizer high threshold eht7-0 17h (table 41) equalizer low threshold elt7-0 18h (table 42) serial config. word ima, t1dm, g.802, 8men, 8mts1-0 19h (table 43) hdlc0 select en, fdlsel , ch4-0 1ah (table 44) hdlc1 select en, ch4-0 1bh (table 45) hdlc2 select en, ch4-0 1ch (table 46) custom pulse word 1 cp6-0 1dh (table 47) custom pulse word 2 cp6-0 1eh (table 48) custom pulse word 3 cp6-0 1fh (table 49) custom pulse word 4 cp6-0 table 36 - master control 2 (page 02h) (t1)
mt9076b data sheet 79 zarlink semiconductor inc. bit name functional description 7t1/e1 t1/e1 mode selection. when this bit is zero, the device is in t1 mode. when set high, the device is in e1 mode. 6-- reserved. must be kept at 0 for normal operation. 5txen transmit enable. setting this bit low turns off the ttip and tring output line drivers. setting this bit high enables them. 4liuen liu enable. setting this bit low enables the internal li u front-end. setting this pin high disables the liu. digital inputs rxa and rx b are sampled by the rising edge of e1.5i (exclk) to strobe in the received line data. digital transmit data is cl ocked out of pins txa and txb with the rising edge of exclk 3elos elos enable . set this bit low to set the analog loss of signal threshold to 40 db below nominal. set this bit high to set the analog loss of signal threshold to 20 db below nominal. 2 tx8ken transmit 8 khz enable. if one, the pin rxmf /txfp transmits a positive 8 khz frame pulse synchronous with the serial data stream transmit on txa/txb. if zero, the pin rxmf /txfp transmits a negative frame pulse synchronous with the multiframe boundary of data coming out of dsto. 1adseq digital milliwatt or digital test sequence . if one, the a law digita l milliwatt analog test sequence will be selected for those channels with per time sl ot control bits ttst, rrst set. if zero, a prbs generator / detector will be connected to channe ls with ttst, rrst respectively. 0-- reserved. must be kept at 0 for normal operation. table 37 - configuration control word (page 2, address 10h) (t1)
mt9076b data sheet 80 zarlink semiconductor inc. bit name functional description 7-5 -- reserved. must be kept at 0 for normal operation. 4-- reserved. set low for normal operation. 3cpl custom pulse level. setting this bit low enables the internal rom values in generating the transmit pulses. the rom is coded for different line terminations or build out, as specified in the liu control word. setting this pi n high disables the pre-progra mmed pulse templates. each of the 4 phases that generate a mark derive their d/ a coefficients from the values programmed in the cpw registers. 2-0 txlb2-0 transmit line build out 2 - 0 . setting these bits shapes the tr ansmit pulse as detailed in the table below: tx22 txl1 txl0 line build out 0 0 0 0 to 133 feet/ 0 db 0 0 1 133 to 266 feet 0 1 0 266 to 399 feet 0 1 1 399 to 533 feet 1 0 0 533 to 655 feet 1 0 1 -7.5 db 1 1 0 -15db 1 1 1 -22.5 db after reset these bits are zero. table 38 - liu tx word (page 2, address 11h) (t1)
mt9076b data sheet 81 zarlink semiconductor inc. bit name functional description 7- - - unused. 6jfc jitter attenuator fifo centre. when this bit is toggled the read pointer on the jitter attenuator shall be centered. during this cent ering the jitter on the ja outputs is increased by 0.0625 u.i. this feature is only available when ima mode is activated. 5 - 3 jfd2-jfd0 jitter attenuator fifo depth control bits. these bits determine the depths of the jitter attenuator fifo as shown below: jfd2 jfd1 jfd0 depth 0 0 0 16 0 0 1 32 0 1 0 48 0 1 1 64 1 0 0 80 1 0 1 96 1 1 0 112 1 1 1 128 this feature is only available when ima mode is activated. 2jacl jitter attenuator fifo clear bit. if one, the jitter attenuator, it s fifo and status are reset. the status registers will identify the fifo as be ing empty. however, the actual bit values of the data in the ja fifo will not be reset. this feature is only availabl e when ima mode is activated. 1 - 0 - - - unused. table 39 - jitter attenuation control word (page 2, address 13h) (t1) bit name functional description 7-0 eht7-0 equalizer high threshold. these bits set the highest possible binary count tolerable coming out of the equalized signal peak det ector before a lower level of equalization is selected. this register is only used when a/d based automatic equalization is selected using the rx liu control word. recommended value to program is 10111011. table 40 - equalizer high threshold (page 2, address 16h) (t1) bit name functional description 7-0 elt7-0 equalizer low threshold. these bits set the lowest possi ble binary count tolerable coming out of the equalized signal peak detector before a higher level of equalization is selected. this register is only used when a/d based aut omatic equalization is selected using the rx liu control word. recommended value to program is 00110000. table 41 - equalizer low threshold (page 2, address 17h) (t1)
mt9076b data sheet 82 zarlink semiconductor inc. bit name functional description 7-6 -- reserved. must be kept at 0 for normal operation. 5ima inverse mux mode. setting this bit high the i/o ports to allow for easy connection to the zarlink mt90220. dsti becomes a serial 1.544 data stream. c4b becomes a 1.544 mhz clock that clocks dsti in on the falling edge. rxfp becomes a positive framing pulse that is high for the first bit (the frami ng bit) of the serial t1 stream coming from the pin dsto. this stream is clocked out on the rising edge of excl k. set this pin low for all other applications. 4-- reserved. must be set to 0 for normal operation. 3 g.802 g.802. must be kept at 0 for normal operation. set high for st-bus to dsi channel mapping as per g.802. 28men 8 mb/s bit rate select. setting this bit low enables a serial bit rate on dsti, csti and dsto, csto of 2.048 mb/s. setting this bit high enables a gapped serial bit rate of 8.192 mb/s on dsti, csti, dsto and csto. 1-0 8mts1-0 8 mb/s time slot select. these two bits select the active timeslots on the serial 8.192 mb/s channels. during the active timeslots incoming se rial data on dsti and csti is clocked into the device, and data is clocked out onto dsto and csto. during inactive timeslots dsto and csto are tristate. for all selections every f ourth 8 mb/s timeslot is active for the first 96 timeslots (24 x 8). the timeslot selection (t1 mode) is as follows: 8mts1 8mst0 active timeslots 0 0 0,4,8,12,16,20, 24,28,32,36,40,44,48,52,56, 60,64,68,72, 76,80,84,88,92 0 1 1,5,9,13,17,21,25, 29,33,37,41,45,49,53,57, 61,65,69,73, 77,81,85,89,93 1 0 2,6,10,14,18,22,26, 30,34,38,42,46,50,54, 58,62,66,70,74,78, 82,86,90,94 1 1 3,7,11,15,19,23,27,31,35,39,43,47, 51,55,59,63,67,71, 75,79,83,87,91,95 table 42 - serial config. word (page 2, address 18h) (t1) bit name functional description 7en enable. set high to attach the hdlc0 controller to the channel specified below. set low to disconnect the hdlc0. 6 fdlsel facility data link select. set this bit to 0 to attach hdlc0 to the 4 kb/s facility data link. set this bit to 1 to attach hdlc0 to a payload timeslot. 5-- reserved. must be kept at 0 for normal operation. 4-0 ch4-0 channel 4-0. this 5 bit number specifies the channel time hdlc0 will be attached to if enabled. channel 0 is the first channel in the fram e. channel 23 is the last channel available in a t1 frame. if enabled in a channel, hdlc data will be subs tituted for data from dsti on the transmit side. receive data is extracted fr om the incoming line data before the elastic buffer. table 43 - hdlc0 select (page 2, address 19h) (t1)
mt9076b data sheet 83 zarlink semiconductor inc. bit name functional description 7en enable. set high to attach the hdlc1 controller to the channel specified below. set low to disconnect the hdlc1. 6-5 -- reserved. must be kept at 0 for normal operation. 4-0 ch4-0 channel 4-0. this 5 bit number specifies the channel time hdlc1 will be attached to if enabled. channel 0 is the first channel in the fram e. channel 23 is the last channel available in a t1 frame. if enabled in a channel, hdlc data will be subs tituted for data from dsti on the transmit side. receive data is extracted fr om the incoming line data before the elastic buffer. table 44 - hdlc1 select (page 2, address 1ah) (t1) bit name functional description 7en enable. set high to attach the hdlc2 controller to the channel specified below. set low to disconnect the hdlc2. 6-5 - - reserved. must be kept at 0 for normal operation. 4-0 ch4-0 channel 4-0. this 5 bit number specifies the cha nnel time hdlc2 will be attached to if enabled. channel 0 is the first channel in the fr ame. channel 23 is the last channel available in a t1 frame. if enabled in a channel, hdlc data will be substituted for data from dsti on the transmit side. receive data is extracted from the incoming line data before the elastic buffer. table 45 - hdlc2 select (page 2, address 1bh) (t1) bit name functional description 7- - reserved. must be kept at 0 for normal operation. 6-0 cp6-0 custom pulse. these bits provide the capability fo r programming the magnitude setting for the ttip/tring line driver a/d converter dur ing the first phase of a mark. the greater the binary number loaded into the register, the greater the amplitude driven out. this feature is enabled when the control bit 3 - cpl of the cust om tx pulse enable register - address 11h of page 2 is set high. table 46 - custom pulse word 1 (page 2, address 1ch) (t1)
mt9076b data sheet 84 zarlink semiconductor inc. bit name functional description 7- reserved. must be kept at 0 for normal operation. 6-0 cp6-0 custom pulse. these bits provide the capability fo r programming the magnitude setting for the ttip/tring line driver a/d converte r during the second phase of a mark. the greater the binary number loaded into the register, the greater the amplitude driven out. this feature is enabled when the control bit 3 - cpl of the custom tx pulse enable register - address 11h of page 2 is set high. table 47 - custom pulse word 2 (page 2, address 1dh) (t1) bit name functional description 7- - reserved. must be kept at 0 for normal operation. 6-0 cp6-0 custom pulse. these bits provide the capability for programming the magnitude setting for the ttip/tring line driver a/d converter duri ng the third phase of a mark. the greater the binary number loaded into the register, the gr eater the amplitude driven out. this feature is enabled when the control bit 3 - cpl of the custom tx pulse enable register - address 11h of page 2 is set high. table 48 - custom pulse word 3 (page 2, address 1eh) (t1) bit name functional description 7- - reserved. must be kept at 0 for normal operation. 6-0 cp6-0 custom pulse. these bits provide the capability for programming the magnitude setting for the ttip/tring line driver a/d converter during the fourth phase of a mark. the greater the binary number loaded into the register, the gr eater the amplitude driven out. this feature is enabled when the control bit 3 - cpl of the custom tx pulse enable register - address 11h of page 2 is set high. cp6-0 breakdown cp[6] sign bit (0=neg, 1=pos) (only necessary for t1) cp[5:0] magnitude in binary (pulse amplitude = 0.1 * cp[5:0]v) table 49 - custom pulse word 4 (page 2, address 1fh) (t1)
mt9076b data sheet 85 zarlink semiconductor inc. 20.1.3 master status 1 (page03h) (t1) address (a 4 a 3 a 2 a 1 a 0 ) register function 10h (table 51) synchronization status word tfsync , mfsync , se, los 11h (table 52) alarm status word d4yalm, d4y48, secyel, esfyel, blue, pdv, lled, lldd 12h (table 53) timer status word 1sec, 2sec, 5sec 13h (table 54) most significant phase status word rslip, rslpd, rxfrm, rxft, rxsbd2-0 14h (table 55) least significant phase status word rxts4-0, rxbc2-0 15h (table 56) receive bit oriented message rxbom7-0 16h (table 57) receive signal status word llos 17h (table 58) msb transmit slip buffer tslip, tslpd, txsbmsb 18h (table 59) transmit slip buffer delay txts4-0, txbc2-0 19h - - - unused. 1ah - - - unused. 1bh - - - unused. 1ch - - - reserved. 1dh (table 60) analog peak detect ap7-0 1eh - - - reserved 1fh (table 61) identification word internally set to 01111000 table 50 - master status 1 (page 3) (t1)
mt9076b data sheet 86 zarlink semiconductor inc. bit name functional description 7 tfsync terminal frame synchronization . indicates the terminal frame synchronization status (1 - loss; 0 - acquired). for esf links termin al frame synchronization and multiframe synchronization are synonymous. 6 mfsync multiframe synchronization. indicates the multiframe synchronization status (1 - loss; 0 -acquired). for esf links multiframe synchron ization and terminal frame synchronization are synonymous. 5se severely errored frame . this bit toggles when 2 of the last 6 received framing bits are in error. the framing bits monitored are the esf framing bits for esf links, the ft bits for slc-96 links and a combination of ft and fs bits for d4 links (see framing mode selection word - page 1 address 10h). 4los digital loss of signal. this bit goes high after the detection of a string of consecutive zeros. it returns low when the incoming pulse density exceeds 12.5% over a 250 ms period. the threshold for this condition is set by the control bit l32z. if l32z is set high the threshold is 32 successive zeros. if l32z is set low the threshold is 192 successive zeros. 3 - 0 - - - unused . table 51 - synchronization status word (page 3, address 10h) (t1)
mt9076b data sheet 87 zarlink semiconductor inc. bit name functional description 7d4yalm d4 yellow alarm. this bit is set if bit position 2 of virtually every ds0 channel is a zero for a period of 600 millisec onds. the alarm is tolerant of errors by permitting up to 16 ones in a 48 millisecond integration period. the alarm clears in 200 milliseconds after being removed from the line. 6d4y48 d4 yellow alarm - 48 millisecond sample . this bit is set if bit position 2 of virtually every ds0 channel is a zero for a period of 48 millis econds. the alarm is tolerant of errors by permitting up to 16 ones in the integration per iod. this bit is updated every 48 milliseconds. 5 secyel secondary d4 yellow alarm . this bit is set if 2 consecutive?1?s are received in the sbit position of the 12th frame of the d4 superframe. 4 esfyel esf yellow alarm . this bit is set if the esf yellow alarm 000000001111 1111 is receive in seven or more codewords out of ten. 3blue blue alarm . this bit is set if less than 6 zero s are received in a 3 millisecond window. 2pdv pulse density violation . this bit toggles if the receive data fails to meet ones density requirements. if rxb8zs is set high it will toggle upon detection of 8 zeros. i rxb8zs is set low it will toggle upon detection of 16 consecutive zeros on the line data, or if there are less than n ones in a window of 8(n+1) bits - where n = 1 to 23. 1 lled line loopback enable detect. this bit will be set when a framed or unframed repeating pattern of 00001 has been detect ed during a 48 millisecond interval . up to fifteen errors are permitted per integration period. 0lldd line loopback disable detect . this bit will be set when a framed or unframed repeating pattern of 001 has been detect ed during a 48 millisecond interval . up to fifteen errors are permitted per integration period. table 52 - alarm status word (page 3, address 11h) (t1) bit name functional description 7 1sec one second timer status . this bit changes state once every 0.5 seconds. 6 2sec two second timer status. this bit changes state once every second and is synchronous with the 1sec timer. 5 5sec five second timer status . this bit changes state once every 2.5 seconds and is synchronous with the 1sec timer. 4-0 - - - unused. table 53 - timer status word (page 3, address 12h) (t1)
mt9076b data sheet 88 zarlink semiconductor inc. bit name functional description 7rslip receive slip . a change of state (i.e., 1-to-0 or 0- to-1) indicates that a receive controlled frame slip has occurred. 6 rslpd receive slip direction . if one, indicates that the last received frame slip resulted in a repeated frame, i.e., the system clock (c4b ) is faster than network clock (e2o). if zero, indicates that the last received frame slip resu lted in a lost frame, i.e., system clock slower than network clock. updated on an rslip occurrence basis. 5 rxfrm receive frame delay. the most significant bit of the receive slip buffer phase status word. if one, the delay through the receive elasti c buffer is greater than one frame in length; if zero, the delay through the receive elastic buffer is less than one frame in length. 4 - - - unused. 3 rxft receive frame toggle. this bit toggles on the falling edge of rxts4. it is a wink pulse. 2-0 rxsbd2-0 receive sub bit delay. the three least signifi cant bits of the receive slip buffer phase status word. they indicate the clock, half clock and one eighth cl ock cycle depth of the phase status word sample point (bits 2, 1,0 respectively). table 54 - most significant phase status word (page 3, address 13h) (t1) bit name functional description 7 - 3 rxts4 - 0 receive time slot . a five bit counter that indicates the number of time slots between the receive elastic buffer internal write fram e boundary and the st-bus read frame boundary. the count is updated every 250 us. 2 - 0 rxbc2 - 0 receive bit count . a three bit counter that indicates the number of stbus bit times there are between the receive elastic buffer inte rnal write frame boundary and the st-bus read frame boundary. the count is updated every 250 us. table 55 - least significant phase status word (page 3, address 14h) (t1) bit name functional description 7 - 0 rxbom7 - 0 received bit oriented message . this register contains the eight least significant bits of the esf bit oriented message codeword. the contents of this register is updated when a new bit - oriented message codeword has been detected in 8 out of the last ten codeword positions. table 56 - receive bit oriented message (page 3, address 15h) (t1)
mt9076b data sheet 89 zarlink semiconductor inc. bit name functional description 7 llos liu loss of signal indication . this bit will be high when the received signal is less than 40 db below the nominal value for a period of at least 1 msec. th is bit will be low for normal operation. 6-0 - - - unused. table 57 - receive signal status word (page 3, address 16h) (t1) bit name functional description 7tslip transmit slip . a change of state (i.e., 1-to-0 or 0-to-1 ) indicates that a transmit controlled frame slip has occurred. 6 tslpd transmit slip direction. if one, indicates that the last transmit frame slip resulted in a repeated frame, i.e., the internally generated 1.544 mhz. transmit clock is faster than the system clock (c4b ). if zero, indicates that the last trans mit frame slip resulted in a lost frame, i.e., the internally generated 1.544 mhz. trans mit clock is slower than network clock. updated on an tslip occurrence basis. 5 txsbmsb transmit slip buffer msb . the most significant bit of the phase status word. if one, the delay through the transmit elastic buffer is greate r than one frame in length; if zero, the delay through the receive elastic buffer is less than one frame in length. this bit is reset whenever page 1 address 17h - transmit slip buffer delay - is written to. 4 - 0 - - - unused . table 58 - msb transmit slip buffer (page 3, address 17h) (t1) bit name functional description 7 - 3 txts4 - 0 transmit time slot . a five bit counter that indicates the number of stbus time slots between the transmit elastic buffer stbus wr ite frame boundary and the internal transmit read frame boundary. the count is updated every 250 us. 2 - 0 txbc2 - 0 transmit bit count . a three bit counter that indica tes the number of stbus bit times there are between the transmit elastic buffer stbus write frame boundary and the internal read frame boundary. the count is updated every 250 us. table 59 - transmit slip buffer delay (page 3, address 18h) (t1) bit name functional description 7 - 0 ap7 - 0 analog peak . this status register gives the ou tput value of an 8 bit a/d converter connected to a peak detector on rtip/rring. table 60 - analog peak detect (page 3, address 1dh) (t1)
mt9076b data sheet 90 zarlink semiconductor inc. 20.1.4 master status 2 (page 04h) (t1) bit name functional description 7-0 id7-0 id number. contains device code 01111000 table 61 - identification word (page 3, address 1fh) (t1) address (a 4 a 3 a 2 a 1 a 0 ) register function 10h (table 63) prbs error counter ps7-0 11h (table 64) crc multiframe counter for prbs psm7-0 12h (table 65) alarm reporting latch d4yalml, d4y48l, secyell, esfyell, bluel, pdvl, lledl, llddl 13h (table 66) framing bit counter fc7-0 14h (table 67) out of frame / change of frame alignment counters oof3-0/cofa3-0 15h (table 68) multiframes out of sync counter mfoof7-0 16h (table 69) most significant line code violation error counter lcv15 - lcv8 17h (table 70) least significant line code violation error counter lcv7 - lcv0 18h (table 71) crc- 6 error counter (address 18h) cc15-cc8 19h (table 72) crc- 6 error counter (address 19h) cc7 - cc0 1ah unused. 1bh (table 73) interrupt word zero tfsyn i, mfsyni, biomti, aisi, losi, sei, txslpi, rxslpi 1ch (table 74) interrupt word one fei, crci, yeli, cofai, lcvi, prbsi, pdvi 1dh (table 75) interrupt word two feo, crco, oofo, cofao, lcvo, prbso, prbsmfo,mfoofo 1eh (table 76) interrupt word three hdlc0i, hdlc1i, hdlc2i, lcdi, 1seci, 5seci, biomi, sigi 1fh (table 77) overflow reporting latch feol, crcol, oofol, cofaol, lcvol, prbsol, prbsmfol, mfoofol table 62 - master status 2 (page 4) (t1)
mt9076b data sheet 91 zarlink semiconductor inc. bit name functional description 7 - 0 ps7-0 this counter is incremented for each prbs error detected on any of the receive channels connected to the prbs error detector. table 63 - prbs error counter (page 4, address 10h) (t1) bit name functional description 7 - 0 psm7-0 this counter is incremented for each receiv ed crc multiframe. it is cleared when the prbs error counter is written to. table 64 - crc multiframe counter for prbs (page 4, address 11h) (t1) bit name functional description 7 d4yalml d4 yellow alarm latch . this bit is set if a d4 yellow alarm is detected within a 600 millisecond integration period. it is cleared after a read. 6 d4y48l d4 yellow alarm (48 milliseconds) latch . this bit is set if a d4 yellow alarm is detected within a 48 millisecond integration period. it is cleared after a read. 5 secyell secondary d4 yellow alarm latch . this bit is set if an alternat e d4 (s bit in 12 the frame) is detected. it is cleared after a read. 4 esfyell esf yellow alarm latch . this bit is set upon receipt of a esf yellow alarm. it is cleared after a read. 3bluel blue alarm latch . this bit is set upon receipt of a blue alarm. it is cleared after a read. 2pdvl pulse density violation latch . this bit is set upon receipt of a pulse density violation. it is cleared after a read. 1 lledl line loopback enable detect latch . this bit is set upon receipt of a line loopback enable code. it is cleared after a read. 0 llddl line loopback disable detect latch . this bit is set upon receipt of a line loopback disable code. it is cleared after a read. table 65 - alarm reporting latch (page 4, address 12h) (t1) bit name functional description 7 - 0 fc7 - 0 framing bit counter . this eight bit counter will be incremented for each error in the received framing pattern. in esf mode the esf framing bits are monitored. in d4 mode fs bits may be monitored as well as ft bits. s ee - section 15.5 framing bit counter. the count is only active if the 3vjet is in synchronization. table 66 - framing bit counter (page 4, address 13h) (t1)
mt9076b data sheet 92 zarlink semiconductor inc. bit name functional description 7 - 4 oof3 - 0 out of frame counter . this four bit counter is increm ented with every loss of receive frame synchronization. 3 - 0 cofa3 - 0 change of frame alignment counter . this four bit counter is incremented if a resynchronization is done which results in a shift in the frame alignment position. table 67 - out of frame / change of frame alignment counter (page 4, address 14h) (t1) bit name functional description 7 - 0 mfoof7 - 0 multiframes out of synchronization counter . this eight bit counter will be incremented once for every multiframe (1.5 milliseconds in d4 mode, 3 milliseconds in esf mode) in which basic frame synchronization is lost. table 68 - multiframes out of sync counter (page 4, address 15h) (t1) bit name functional description 7 - 0 lcv15 - 8 most significant bits of the lcv counter. the most significant eight bits of a 16 bit counter that is incremented once for ev ery line code violat ion error received. a line code violation is define d as a bipolar violation that is not a part of b8zs encoding when the control bit exz is set low. a line code violation includes both bipolar violations and excess zeros when exz is set high. table 69 - most significant bits of the lcv counter (page 4, address 16h) (t1) bit name functional description 7 - 0 lcv7 - 0 least significant bits of the lcv counter . the least significant eight bits of a 16 bit counter that is incremented once for ever y line code violation error received. a line code violation is defined as a bipolar vi olation that is not a part of b8zs encoding when the control bit exz is set low. a line code violation includes both bipolar violations and excess zeros when exz is set high. table 70 - least significant bits of the lcv counter (page 4, address 17h) (t1) bit name functional description 7 - 0 cc15 - 8 crc-6 error counter bits fifteen to eight . these are the most signif icant eight bits of the crc-6 error counter. table 71 - crc-6 error counter (page 4, address 18h) (t1)
mt9076b data sheet 93 zarlink semiconductor inc. bit name functional description 7 - 0 cc7 - 0 crc-6 error counter bits seven to zero . these are the least signifi cant eight bits of the crc-6 error counter. table 72 - crc-6 error counter (page 4, address 19h) (t1) bit name functional description 7 tfsyni terminal frame synchronization interrupt . when unmasked this interrupt bit goes high whenever a change of state of terminal frame synchronization condition exists. reading this register clears this bit. 6mfsyni multiframe synchronization interrupt . when unmasked this interrupt bit goes high whenever a change of state of multiframe sy nchronization condition exists. reading this register clears this bit. 5 biomti bit oriented message transition interrupt . when unmasked, this interrupt goes high whenever a new biom arrives or if the current biom stops transmission. 4aisi alarm indication signal interrupt . when unmasked this interrupt bit goes high whenever a change of state of received all ones condition ex ists. reading this register clears this bit. 3losi loss of signal interrupt. when unmasked this interrupt bit goes high whenever a change of state of loss of signal (either analog - si gnal 40 db below nominal or digital - excess consecutive 0?s received) condition exists . reading this regist er clears this bit. 2 sei severely errored frame interrupt . when unmasked this interrupt bit goes high whenever a sequence of 2 framing errors out of 6 occurs . reading this register clears this bit. 1txslpi transmit slip interrupt . when unmasked this interrupt goes high whenever a controlled frame slip occurs in the transmit elastic buf fer. reading this register clears this bit. 0rxslpi receive slip interrupt . when unmasked this interrupt bit goes high whenever a controlled frame slip occurs in the receive elastic bu ffer. reading this regi ster clears this bit. table 73 - interrupt word zero (page 4, address 1bh) (t1)
mt9076b data sheet 94 zarlink semiconductor inc. bit name functional description 7fei framing bit error interrupt. when unmasked this interrupt bit goes high whenever an erroneous framing bit is detected (provided the circuit is in terminal frame sync). reading this register clears this bit. 6 crci crc-6 error interrupt . when unmasked this interrupt bit goes high whenever a local crc-6 error occurs. reading this register clears this bit. 5 yeli yellow alarm interrupt . when unmasked this interrupt bit goes high upon detection of a yellow alarm. reading this register clears this bit. 4cofai change of frame alignment interrupt . when unmasked this interrupt bit goes high whenever a change of frame alignment occurs afte r a reframe. reading this register clears this bit. 3lcvi line code violation interrupt . when unmasked this interrupt bit goes high whenever a line code violation (excluding b8zs encoding) is enc ountered. reading this re gister clears this bit. 2 prbsi psuedo random bit sequence error interrupt . when unmasked this interrupt bit goes high upon detection of an error with a channel select ed for prbs testing. reading this register clears this bit. 1pdvi pulse density violation interrupt . when unmasked this interrupt bit goes high whenever, in the absence of b8zs encoding, a sequence of 16 consecutive zeros is received on the line, or the incoming pulse density is less than n ones in a time frame of 8(n+1) where n = 1 to 23. in the case of b8zs coding, the interrupt is set upon detection of 8 consecutive zeros. reading this register clears this bit. 0- - - unused . table 74 - interrupt word one (page 4, address 1ch) (t1)
mt9076b data sheet 95 zarlink semiconductor inc. bit name functional description 7feo framing bit error counter overflow interrupt . when unmasked this interrupt bit goes high whenever the framing bit error counter changes from ffh to 00h. reading this register clears this bit. 6 crco crc-6 error counter overflow interrupt . when unmasked this interrupt bit goes high whenever the crc-6 error counter changes from ffh to 00h. reading th is register clears this bit. 5 oofo out of frame counter overflow interrupt . when unmasked this interrupt bit goes high whenever the out of frame counter changes st ate from changes from ffh to 00h. reading this register clears this bit. 4cofao change of frame alignment counter overflow interrupt . when unmasked this interrupt bit goes high whenever the change of frame ali gnment counter changes from ffh to 00h. reading this register clears this bit. 3lcvo line code violation counter overflow interrupt. when unmasked this interrupt bit goes high whenever the line code violation count er changes from ffh to 00h. reading this register clears this bit. 2 prbso psuedo random bit sequence error counter overflow interrupt . when unmasked this interrupt bit goes high whenever the prbs error counter changes from ffh to 00h. reading this register clears this bit. 1 prbsmfo psuedo random bit sequence multiframe counter overflow interrupt. when unmasked this interrupt bit goes high whenever the multiframe counter attached to the prbs error counter overflows. ffh to 00h. 1 - unmasked, 0 - masked. 0 mfoofo multiframes out of sync overflow interrupt . when unmasked this interrupt bit goes high whenever the multiframes out of frame counter changes from ffh to 00h. reading this register clears this bit. table 75 - interrupt word two (page 4, address 1dh) (t1)
mt9076b data sheet 96 zarlink semiconductor inc. bit name functional description 7hdlc0i hdlc0 interrupt. whenever an unmasked hdlc0 interrupt occurs this bit goes high. reading this register clears this bit. 6hdlc1i hdlc1 interrupt. whenever an unmasked hdlc1 interrupt occurs this bit goes high. reading this register clears this bit. 5hdlc2i hdlc2 interrupt. whenever an unmasked hdlc2 interrupt occurs this bit goes high. reading this register clears this bit. 4lcdi loop code detected interrupt . when unmasked this interrupt bit goes high whenever either the loop up (00001) or lo op down (001) code has been detected on the line for a period of 48 milliseconds . reading this regist er clears this bit. 3 1seci one second status interrupt. when unmasked this interrupt bit goes high whenever the 1sec status bit (page 3 address 12h bit 7) goes from low to high. reading this register clears this bit. 2 5seci five second status interrupt . when unmasked this interrupt bit goes high whenever the 5 sec status bit goes from low to high. reading this register clears this bit. 1 biomi bit oriented message interrupt . when unmasked this interrupt bit goes high whenever a pattern 111111110xxxxxx0 has been received on the fdl that is different from the last message. the new message must persist for 8 out the last 10 message positions to be accepted as a valid new message. read ing this register clears this bit. 0sigi signaling interrupt . when unmasked this interrupt bit goes high whenever a change of state (optionally debounced - see dben in the data link, signaling control word page 1 address 12h) is detected in the signaling bits (ab or abcd) pattern. reading this register clears this bit. table 76 - interrupt word three (page 4, address 1eh) (t1)
mt9076b data sheet 97 zarlink semiconductor inc. 20.1.5 per channel transmit signalling (pages 5 and 6) (t1) page 05h, addresses 10000 to 11111, and page 06h addresses 10000 to 10111 contain the transmit signaling control words for ds1 channels 1 to 16 and 17 to 24 respectively. table 78 illustrates the mapping between the addresses of these pages and the ds1 channel numbers. control of these bits for any one channel is through the processor or controller port when the per time slot contro l bit rpsig bit is high. table 79 describes bit allocation within each of these registers. bit name functional description 7feol framing bit error counter overflow latch . this bit is set when the framing bit counter overflows. it is cleared after being read. 6 crcol crc-6 error counter overflow latch . this bit is set when the crc error counter overflows. it is cleared after being read. 5 oofol out of frame counter overflow latch . this bit is set when the out of frame counter overflows. it is cleared after being read. 4cofaol change of frame alignment counter overflow latch . this bit is set when the change of frame alignment counter overfl ows. it is cleared after being read. 3lcvol line code violation counter overflow latch . this bit is set when the line code violation counter overflows. it is cleared after being read. 2 prbsol psuedo random bit sequence error counter overflow latch . this bit is set when the prbs error counter overflows. it is cleared after being read. 1 prbsmfol psuedo random bit sequence mult iframe counter overflow latch. this bit is set when the multiframe counter attached to the prbs error counter overflows. it is cleared after being read. 0 mfoofol multiframes out of sync overflow latch . this bit is set when the multiframes out of sync counter overflows. it is cleared after being read. table 77 - overflow reporting latch (page 4, address 1fh) (t1) page 5 address: 0123456789101112131415 equivalent ds1 channel 12345678910111213141516 page 6 address: 0123456789101112131415 equivalent ds1 channel 1718192021222324xxxxxxxx table 78 - pages 5 and 6 address mapping to ds1 channels (t1)
mt9076b data sheet 98 zarlink semiconductor inc. serial per channel transmit signaling control through csti is selected when the per time slot control bit rpsig bit is low. table 80 describes the bit allocation within each of the 24 active st-bus time slots of csti. 20.2 per time slot control words (pages 7 and 8) (t1) the control functions described by table 78 are repeated for each ds1 time slot. page 7 addresses 10000 to 11111 correspond to ds1 time slot 1 to 16, while page 8 addr esses 10000 to 10111 correspond to time slots 17 to 24. table 81 illustrates the mapping between the addre sses of these pages and the ds1 channel numbers. bit name functional description 7 - 4 - - - unused . 3a(n) transmit signaling bits a for channel n . where signaling is ena bled, these bits are transmitted in bit position 8 of the 6th ds1 fr ame (within the 12 frame superframe structure for d4 superframes and the 24 frame structure for esf superframes). 2b(n) transmit signaling bits b for channel n . where signaling is ena bled, these bits are transmitted in bit position 8 of the 12th ds1 frame (within the 12 frame superframe structure for d4 superframes and the 24 frame structure for esf superframes). 1c(n) transmit signaling bits c for channel n . where signaling is ena bled, these bits are transmitted in bit position 8 of the 18th ds 1 frame within the 24 fr ame structure for esf superframes. in d4 mode these bits are unused. 0d(n) transmit signaling bits d for channel n. where signaling is ena bled, these bits are transmitted in bit position 8 of the 24th ds 1 frame within the 24 fr ame structure for esf superframes. in d4 mode these bits are unused. table 79 - transmit channel associated signaling (t1) (pages 5 and 6) bit name functional description 7 - 4 a(n), b(n) c(n), d(n) transmit signaling bits for channel n . when control bit msn = 1 and rpsig = 1 this nibble is used. for esf links these 4 bits are transmitted on the associated ds1 channel (see table 8) in frames 6, 12, 18 and 24. for d4 links bits a are transmit on the associated ds1 channel of frame 6 and bits b are transmi t on the associated ds1 channel of frame 12. for d4 links bits c and d are unused. 3 - 0 a(n), b(n), c(n), d(n) transmit signaling bits for channel n . when control bit msn = 0 and rpsig = 1 this nibble is used. for esf links these 4 bits are transmitted on the associated ds1 channel (see table 8) in frames 6, 12, 18 and 24. for d4 links bits a are transmit on the associated ds1 channel of frame 6 and bits b are transmi t on the associated ds1 channel of frame 12. for d4 links bits c and d are unused. table 80 - t1 / transmit channels usage - csti note: this table illustrates bit mapping on the serial input stream - it does not refer to an internal register. page 7 address: 0123456789101112131415 equivalent ds1 channel 12345678910111213141516 table 81 - pages 7 and 8 address mapping to ds1 channels
mt9076b data sheet 99 zarlink semiconductor inc. page 8 address: 0123456789101112131415 equivalent ds1 channel 1718192021222324xxxxxxxx bit name functional description 7 txmsg transmit message mode. if high, the data contained in the transmit message register (address 18h, page 1) is transmitted in the co rresponding ds1 time slot. if zero, the data on dsti is transmitted on the corresponding ds1 time slot. 6pci per channel inversion. when set high the data for this channel sourced from dsti is inverted before being transmit onto the equiv alent ds1 channel; the data received from the incoming ds1 channel is inverted before it emerges from dsto. 5rtsl remote time slot loopback. if one, the corresponding ds1 receive time slot is looped to the corresponding ds1 transmit time slot. this received time slot will also be present on dsto. if zero, the loopback is disabled. 4ltsl local time slot loopback. if one, the corresponding transmit time slot is looped to the corresponding receive time slot. this transmit time slot will also be present on the transmit ds1 stream. if zero, this loopback is disabled. 3ttst transmit test. if one, a test signal, either digital milli watt (when control bit adseq is one) or prbs (2 15 -1) (adseq is zero), will be transmitted in the corresponding ds1 time slot. more than one time slot may be activa ted at once. if zero, the test signal will not be connected to the corresponding time slot. 2rtst receive test. if one, the corresponding dsto timeslot will be used for testing. if control bit adeq is one, a digital milliwatt will be trans mitted in the corresponding dsto channel. if control bit adseq is zero, the receive channel will be connected to the prbs detector (2 15 -1). 1 rpsig serial signaling enable. if set low, the transmit signaling buffer for the equivalent ds1 channel will be sourced from t he st-bus channel on csti associ ated with it. if set high the transmit signaling ram must be programmed via the microport. 0cc clear channel. when set high no robbed bit signaling is inserted in the equivalent transmit ds1 channel. when set low robbed bit signa ling is included in every 6th channel. table 82 - per time slot control words (pages 7 and 8) (t1) table 81 - pages 7 and 8 address mapping to ds1 channels
mt9076b data sheet 100 zarlink semiconductor inc. 20.2.1 per channel receive signaling (t1 and e1 mode) (pages 9 and 0ah) page 09h, addresses 10000 to 11111, and page 1ah addresses 10000 to 10111 contain the receive signaling control words for ds1 channels 1 to 16 and 17 to 24 respectively. table 83 illustrates the mapping between the addresses of these pages and the ds1 channel numbers. table 84 describes bit allocation within each of these registers. page 9 address: 0123456789101112131415 equivalent ds1 channel 12345678910111213141516 page a address: 0123456789101112131415 equivalent ds1 channel 1718192021222324xxxxxxxx table 83 - pages 9 and a address mapping to ds1 channels (t1) bit name functional description 7 - 4 - - - unused. 3a(n) receive signaling bits a for channel n . these bits are extracted from bit position 8 of every channel in received frame 6 (within the 12 frame superframe structure for d4 superframes and the 24 frame structure for esf superframes). the bits may be debounced for 6 to 9 milliseconds where control bit dbnce is set high. 2b(n) receive signaling bits b for channel n . these bits are extracted from bit position 8 of every channel in received frame 12 (within th e 12 frame superframe structure for d4 superframes and the 24 frame structure for esf superframes). the bits may be debounced for 6 to 9 milliseconds where control bit dbnce is set high. 1c(n) receive signaling bits c for channel n . these bits are extracted from bit position 8 of every channel in received frame 18 within the 24 frame structure for esf superframes. the bits reported may be de bounced for 6 to 9 milliseconds where control bit dbnce is set high. in d4 mode these bits are unused. 0 d(n) receive signaling bits d for channel n . these bits are extracted from bit position 8 of every channel in received frame 24 within the 24 frame structure for esf superframes. the bits reported may be de bounced for 6 to 9 milliseconds where control bit dbnce is set high. in d4 mode these bits are unused. table 84 - receive channel associated signaling (pages 9 and a) (t1)
mt9076b data sheet 101 zarlink semiconductor inc. 20.3 e1 mode 20.3.1 master control 1 (page 01h) (e1) address (a 4 a 3 a 2 a 1 a 0 ) register function 10h (table 86) mode selection control word asel, crcm, autc , arai , auty , csyn, refrm, mfrf 11h (table 87) transmit alarm control word te, tais16, txao, einv 12h (table 88) ts0 control word exz, saborni, rxtrsp, txtrsp, tiu1,tiu0 13h (table 89) transmit multiframe alignment signal tma1-4,x1,y, x2, x3 14h (table 90) interrupt and signaling control word dstoen, cstoen, txccs, dbnce, msn 15h (table 91) coding and loopback control word rxhdb3, mlbk, txhdb3, dlbk, rlbk, slbk, plbk 16h (table 92) non frame alignment control word talm, tnu4-8 17h (table 93) multiframe and data link selection mfsel, nbtb, sa4-sa8 18h (table 94) transmit message word txm7-0 19h (table 95) error insertion word bpve, crce, fase, nfse, lose, perr, l32z, los/lof 1ah (table 96) signaling control word rst, spnd, inta, cntclr, sample, oofp 1bh (table 97) interrupt mask word zero synim, mfsyim, csynim, aisim, losim, cefim, ymi, slpim 1ch (table 98) interrupt mask word on e ferim, crcim, ebim, ais16im, lcvim, prbsim, auxpim & raim 1dh (table 99) interrupt mask word two feom, crcom, eom, lcvom, prbsom, prbsmfom, saim 1eh (table 100) interrupt mask word three hdlc0im, hdlc1im, hdlc2im, jaim, 1secim, 5secim, rcrim, sigim 1fh (table 101) liu receiver word nrz, rxa1-0, rxeq2-0 table 85 - master control 1 (page 1) (e1)
mt9076b data sheet 102 zarlink semiconductor inc. bit name functional description 7 asel ais select. this bit selects the criteria on which the detection of a valid alarm indication signal (ais) is based. if zero, the criteria is less than three zeros in a two frame period (512 bits). if one, the criteria is less than thr ee zeros in each of two consecutive double-frame periods (512 bits per double frame). 6 crcm crc-4 modification. if one activates the crc-4 remainder modification function when the device is in transparent mode. the received crc -4 remainder is modified to reflect only the changes in the transmit dl. if zero, time slot zero data from dsti will not be modified in transparent mode. 5 autc automatic crc-interworking. if zero, automatic crc-interworki ng is activated. if one it is deactivated. see framing algori thm for a detailed description. 4 arai automatic remote alarm indication . if zero, the remote alarm indication bit (the a bit) will function automatically. that is, rai=1 when basic synchronization has been acquired. and, rai=0 when basic sy nchronization has not been acquired. if one, the remote alarm indicati on bit is controlled through the talm bit of the transmit non-frame alignment control word. 3 auty automatic y-bit operation. if zero, the y-bit of the transmit multiframe alig nment signal will report the multiframe alignment status to the far end i.e., zero - multiframe alignment acquired, one - lost. if one, the y-bit is under the manual cont rol of the transmit multiframe alignment control word. 2 csyn crc-4 synchronization. if zero, basic crc-4 synchronization processing is activated, and the tiu0 bit and the tiu1 bit programming wi ll be overwritten. if one, crc-4 synchronization is disabled, the first bits of channel 0 are used as international use bits and are programmed by the tiu0 and tiu1. 1 refrm reframe. if one for at least one frame, and then cleared, the device will initiate a search for a new basic frame position. reframing function is activated on the one to zero transition of the refrm bit. 0 mfrf multiframe reframe. if one, for at least one frame, and then cleared the 3vjet will initiate a search for a new signaling multif rame position. reframing functi on is activated on the one to zero transition of the mfrm bit. table 86 - mode selection control word (e1) (page 1, address 10h)
mt9076b data sheet 103 zarlink semiconductor inc. bit name functional description 7- - reserved. must be kept at 0 for normal operation. 6te transmit e bits. when zero and crc-4 synchronization is achieved, the e-bits transmit the received crc-4 comparison results to the distan t end of the link, as per g.703. that is, when zero and crc-4 synchronization is lost, the transmit e-bits will be zero. if one, and crc-4 synchronization is lost the transmit e-bits will be one. 5 tais16 transmit ais time slot 16 . if one, an all ones signal is transmitted in time slot 16. if zero, time slot functions normally. 4txao transmit all ones . when low, this control bit forces a framed or unframed (depending on the state of transmit alarm control bit 0) all ones to be transmit at ttip and tring. 3einv ebit error inversion . when zero, received ebits set to zero are counted in the ebit error counter and interrupt generator. when one, ebits set to one are counted in the ebit error counter and interrupt generator. 2-0 - - - unused. table 87 - transmit alarm control word (e1) (page 1, address 11h)
mt9076b data sheet 104 zarlink semiconductor inc. bit name functional description 7 - - - unused . 6 - - - unused . 5 exz excess zeros. setting this bit causes each occurrence of received excess zeros to increment the line code violation counter. excess zeros are defined as 4 or more successive zeros for hdb3 encoded data, or 16 or more successive zeros for non-hdb3 encoded data. 4 saborni sa bit or nibble . set this bit to determine the criteria for interrupts due to transitions of sa bits. if set to one, a change of state of any sa bit is the criteria. if set to zero, a change of state of an sa nibble is the crit eria. note that the selected event can only trigger an interrupt if the interrupt mask bit saim is set high in the interrupt mask word two - page 1 address 1dh bit 0. 3 rxtrsp receive transparent mode . when this bit is set to one, the framing function is disabled on the receive side. data coming from the receiv e line passes through the slip buffer and drives dsto with an arbitrary alignment. when zero, the receive framing function operates normally. 2 txtrsp transmit transparent mode . if one, the mt9076 is in transmit transparent mode. no framing or signaling is imposed on the data transmit from dsti onto the line. if zero, it is in termination mode. 1tiu1 transmit international use one . when crc-4 operation is disabled (csyn =1), this bit is transmit on the pcm 30 2048 kbit/sec. link in bit position one of time-slot zero of non-frame-alignment frames. it is reserved fo r international use and should normally be kept at one. if crc processing is used, i.e., csyn =0, this bit is ignored. 0tiu0 transmit international use zero . when crc-4 operation is disabled (csyn =1), this bit is transmit on the pcm 30 2048 kbit/sec. link in bit position one of time-slot zero of frame-alignment frames. it is reserved for in ternational use and should normally be kept at one. if crc processing is used, i.e., csyn =0, this bit is ignored. table 88 - ts0 control word (e1) (page 1, address 12h)
mt9076b data sheet 105 zarlink semiconductor inc. bit name functional description 7-4 tma1-4 transmit multiframe alignment bits one to four . these bits are transmitted on the pcm 30 2048 kbit/sec. link in bit positions one to four of time slot 16 of frame zero of every signaling multiframe. these bits are used by th e far end to identify specific frames of a signaling multiframe. tma1-4 = 0000 for normal operation. 3 x1 this bit is transmitted on the pcm 30 2048 kbit/s ec. link in bit position five of time slot 16 of frame zero of every multiframe. x1 is normally set to one. 2 y this bit is transmitted on the pcm 30 2048 kbit/s ec. link in bit position six of time slot 16 of frame zero of every multiframe. it is used to indi cate the loss of multiframe alignment to the remote end of the link. if one - loss of multifra me alignment; if zero - multiframe alignment acquired. this bit is ignored when auty is zero (page 01h, address 11h). 1, 0 x2, x3 these bits are transmitted on the pcm 30 2048 kbit/sec. link in bit positions seven and eight respectively, of time slot 16 of frame zero of every multiframe. x2 and x3 are normally set to one. table 89 - transmit multiframe alignment signal (e1) (page 1, address 13h) bit name functional description 7 dstoen dsto enable . if zero pin dsto is tristate. if set the pin dsto is enabled. 6 cstoen csto enable . if zero pin csto is tristate. if set the pin csto is enabled. 5 txccs transmit common channel signaling . if one, the transmit channel 16 of the device is in common channel signaling (ccs) mode. if zero, it is in channel associated signaling (cas) mode, data for channel 16 is sourced from the internal transmission abcd register. 4 dbnce debounce select . this bit selects the debounce period (1 for 14 msec.; 0 for no debounce). note: there may be as much as 2 msec. added to this duration because the state change of the signaling equipment is not synchronous with the pcm 30 signaling multiframe. 3 msn most significant signaling nibble . if one, the csto and csti channel associated signaling nibbles will be valid in the most significant por tion of each st-bus time slot. if zero, the csto and csti channel associated signaling nibb les will be valid in the least significant portion of each st-bus time slot. 2,1,0 - - - unused . table 90 - interrupt and signaling control word (e1) (page 1, address 14h)
mt9076b data sheet 106 zarlink semiconductor inc. bit name functional description 7 rxhdb3 high density bipolar 3 encoding . if one, hdb3 encoding is enabled in the receive direction. if zero, ami signal without hdb3 encoding is received. 6 mlbk metallic loopback . if one, then the external rrtip and rring signals are isolated from the receiver, and ttip and tring are internally connec ted to the receiver an alog input instead. if zero, metallic loopback is disabled. 5 txhdb3 high density bipolar 3 encoding . if one, hdb3 encoding is enabled in the transmit direction. if zero, ami signal without hdb3 en coding is transmitted. hdb3 is always decoded in the receive direction. 4 - - - unused . 3 dlbk digital loopback . if one, then the digital st ream to the transmit liu is looped back in place of the digital output of the receive liu. data co ming out of dsto will be a delayed version of dsti. if zero, this feature is disabled. 2 rlbk remote loopback . if one, then all bipolar data receiv ed on rrtip/rring ar e directly routed to ttip/tring on the pcm 30 side of the mt90 76. if zero, then this feature is disabled. 1 slbk st-bus loopback . if one, then all time slots of dsti are connected to dsto on the st-bus side of the mt9076. if zero, then this fe ature is disabled. see loopbacks section. 0 plbk payload loopback . if one, then all time slots rece ived on rtip/rring are connected to ttip/tring on the st-bus side of the mt9076 (thi s excludes time slot zero). if zero, then this feature is disabled. table 91 - coding and loopback control word (e1) (page 1, address 15h) bit name functional description 7 - 6 - - - unused. 5 talm transmit remote alarm . this bit is transmitted on the pcm 30 2048 kbit/sec. link in bit position three (a bit) of time slot zero of nfas frames. it is used to signal an alarm to the remote end of the pcm 30 link (one - alarm, ze ro - normal). this control bit is ignored when arai is zero (page 01h, address 10h). 4-0 tnu4-8 transmit national use four to eight (sa4 - sa8). these bits are transmitted on the pcm 30 2048 kbit/sec. link in bit positions four to eight of time slot zero of the nfa frame, if selected by sa4 - sa8 control bits of the dl selection word (page 01h, address 10h). table 92 - non frame alignment control word (e1) (page 1, address 16h)
mt9076b data sheet 107 zarlink semiconductor inc. bit name functional description 7 - - - unused. 6 mfsel multiframe select . this bit determines which receive mu ltiframe signal (crc-4 or signaling) the rxmf (pin 42 in plcc, 23 in mqfp) signal is aligned with. if zero, rxmf is aligned with the receive signaling multiframe. if one, rxmf is aligned with the receive crc-4 multiframe. 5 nbtb national bit transmit buffer. if one, the transmit nfas signal originates from the transmit national bit buffer page 0eh; if zero, the transmit nfas signal orig inates from the tnu4-8 bits of page 1 address 16h. 4-0 sa4-sa8 national bit data link select a one selects the corresponding sa bits of the nfa signal for 4, 8, 12, 16 or 20 kbits/sec. data link channel. data link (d l) selection will function in termination mode only; in transmit transparent mode sa4 is automatically selected - see txtrsp control bit of page 01h, address 11h. if zero, the corresponding bits of transmit non-frame alignment signal are programmed by the non-frame alignment control word (page 01h, address 12h). table 93 - multiframe and data link selection (e1) (page 1, address 17h) bit name functional description 7-0 txm7-0 transmit message bits 7 - 0. the contents of this register are transmit into those outgoing ds1 channels selected by the pe r time slot control registers. table 94 - transmit message word (e1) (page 1, address 18h)
mt9076b data sheet 108 zarlink semiconductor inc. bit name functional description 7 bpve bipolar violation error insertion . a zero to one transition of this bit inserts a single bipolar violation error into t he transmit pcm 30 data. a one, ze ro or one to zero transition has no function. 6 crce crc-4 error insertion . a zero to one transition of this bit inserts a single crc-4 error into the transmit pcm 30 data. a one, zero, or one to zero transition has no function. 5 fase frame alignment signal error insertion . a zero to one transition of this bit inserts a single error into the time slot zero frame alignment signal of the transmit pcm 30 data. a one, zero, or one to zero transition has no function. 4 nfse non-frame alignment signal error insertion . a zero to one transition of this bit inserts a single error into bit two of the time slot zero non-frame alignment signal of the transmit pcm 30 data. a one, zero, or one to zero transition has no function. 3 lose loss of signal error insertion . if one, the mt9076 transmits an all zeros signal (no pulses) in every pcm 30 time slot. when hdb 3 encoding is activated no violations are transmitted. if zero, data is transmitted normally. 2 perr payload error insertion . a zero to one transition of this bit inserts a single error in the transmit payload. a one, zero, or one to zero transition has no function. 1l32z digital loss of signal selection . if one, the threshold for digital loss of signal is 32 successive zeros. if zero, the threshold is set to 192 successive zeros. 0 los/lof loss of signal or loss of frame selection . if one, pin los (pin 61 in plcc, 57 in mqfp) will go high when a loss of signal state exits. a loss of signal is defined as either receipt of a signal attenuated below the an alog loss of signal thre shold (selectable as 20 db or 40 db below nominal) or receipt of 256 consecutive 0?s. if low, pin los will go high when either a loss of signal or a loss of basic frame alignment state exits (bit sync on page 03h address 10h is zero). table 95 - error insertion word (e1) (page 1, address 19h)
mt9076b data sheet 109 zarlink semiconductor inc. bit name functional description 7 rst reset . when this bit is c hanged from zero to one the device will reset to its default mode. see the reset operation sect ion for the default settings. 6 spnd suspend interrupts . if one, the irq output (pin 12 in plcc, 85 in mqfp) will be in a high-impedance state and all interrupts will be ig nored. if zero, the irq output will function normally. 5 inta interrupt acknowledge . a zero-to-one or one-to-zero tr ansition will clear any pending interrupt and make irq high. 4 cntclr counter clear . if one, all status counters are cl eared and held low. zero for normal operation. 3 sample one second sample . setting this bit causes the error counters (change of frame alignment, loss of frame alignment, lcv errors, crc errors , severely errored frame events and multiframes out of sync) to be updated on one second inte rvals coincident with the one second timer (status page 3 address 12h bit 7). 2 oofp out of frame pause. if set high, this bit will suspen d operation of the li ne code violation counter during an out - of - fr ame condition; upon achieving terminal frame synchronization the counter will resume normal operation. if se t low, the line code violation counter will continue to count errors even if te rminal frame synchronization is lost. 1 - - reserved. set low for normal operation. 0 d20 double 20. set low for normal operation. set high to double clock speed in the hdlc to speed up memory accesses from 160 ns between consecutive reads/writes to 80 ns between consecutive reads/writes. table 96 - signaling control word (e1) (page 1, address 1ah)
mt9076b data sheet 110 zarlink semiconductor inc. bit name functional description 7 synim synchronization interrupt mask. when unmasked (syni = 1) an interrupt is initiated whenever a change of state of loss of basic fr ame synchronization condition exists. if 1- unmasked, 0 - masked. 6 mfsyim multiframe synchronization interrupt mask . when unmasked (mfsyi = 1), an interrupt is initiated whenever a change of state of mult iframe synchronization exists. if 1- unmasked, 0 - masked. 5 csynim crc-4 multiframe synchronization interrupt mask . when unmasked (csyni = 1), an interrupt is initiated whenever a change of st ate of crc-4 multiframe synchronization exists. if 1- unmasked, 0 - masked. 4 aisim alarm indication signal interrupt mask. when unmasked (aisi = 1) a change of state of received ais will initiate an interrupt. if 1- unmasked, 0 - masked. 3 losim loss of signal interrupt mask . when unmasked this interrupt bit goes high whenever a change of state of loss of signal (either a nalog - received signal 20 or 40 db below nominal or digital - 256 consecutive 0?s received) condition exists. if 1- unmasked, 0 - masked. 2 cefim consecutively errored fass interrupt mask . when unmasked an interrupt is initiated when two consecutive errored frame alignment signals are received. if 1 - unmasked, 0 - masked. 1 yim remote signaling multifra me alarm interrupt mask . when unmasked (yi = 1), an interrupt is initiated whenever a change of state of when a remote signaling multiframe alarm signal is received. if 1- unmasked, 0 - masked. 0 slpim slip interrupt mask. when unmasked (slpi = 1), an interrupt is initiated when a controlled frame slip occurs. if 1- unmasked, 0 - masked. table 97 - interrupt mask word zero (e1) (page 1, address 1bh)
mt9076b data sheet 111 zarlink semiconductor inc. bit name functional description 7 ferim frame error interrupt mask . when unmasked (feri = 1), an interrupt is initiated when an error in the frame alignment signal occurs. if 1- unmasked, 0 - masked. 6 crcim crc-4 error interrupt mask . when unmasked an interrupt is initiated when a local crc-4 error occurs. if 1 - unmasked, 0 - masked. 5 ebim receive e-bit interrupt mask . when unmasked an interrupt is initiated when a receive e-bit indicates a remote crc-4 error. if 1 - unmasked, 0 - masked. 4 ais16im channel 16 alarm indication signal interrupt mask . when unmasked (ais16i = 1), a received ais16 will initiate an inte rrupt. if 1- unmasked, 0 - masked. 3 lcvim line code violation interrupt mask . when unmasked an interrupt is initiated when a line code violation error occurs. if 1 - unmasked, 0 - masked. 2 prbsim prbs interrupt mask. when unmasked (prbsi = 1), an interrupt is initiated on a single prbs detection error. if 1- unmasked, 0 - masked. 1 auxpim auxiliary pattern interrupt mask. when unmasked (auxpi = 1), an interrupt is initiated when the auxp status bit of page 03h, address 15h goes high. if 1- unmasked, 0 - masked. 0 raiim remote alarm indication interrupt mask . when unmasked (raii = 1) a received rai will initiate an interrupt. if 1- unmasked, 0 - masked. table 98 - interrupt mask word one (e1) (page 1, address 1ch)
mt9076b data sheet 112 zarlink semiconductor inc. bit name functional description 7 feom frame alignment signal error counter overflow interrupt mask . when unmasked an interrupt is initiated when the frame alignm ent signal error counter overflows. if 1 - unmasked, 0 - masked. 6 crcoim crc-4 error counter overflow interrupt mask . when unmasked an interrupt is initiated when the crc-4 error counter overflow s. if 1 - unmasked, 0 - masked. 5 - - - unused. 4 eboim receive e-bit counter overflow interrupt mask . when unmasked an interrupt is initiated when the e-bit error counter ov erflows. if 1 - unmasked, 0 - masked. 3 lcvcom line code violation counter overflow interrupt mask. when unmasked (lcvo = 1), an interrupt is initiated when the line code violation error counter changes form ffffh to 0h. if 1- unmasked 0 - masked. 2 prbsom prbs counter overflow interrupt mask . when unmasked (prbso = 1), an interrupt is initiated on overflow of prbs counter (page 04h, address 10h) from ffh to 0h. if 1- unmasked 0 - masked. 1 prbsmfom prbs multiframe counter overflow interrupt mask. when unmasked an interrupt will be generated whenever the multiframe co unter attached to t he prbs error counter overflows. if 1- unmasked 0 - masked. 0 saim sa bits interrupt masks . when unmasked an interrupt w ill be triggered by either a change of state of any of the received sa bits sa5, sa6, sa7 or sa8 (saborni = 1) or a change of state of any of the received sa nibbl es (saborni = 0). the control bit saborni is located in page 1 address 12h bit 4. if 1- unmasked 0 - masked. table 99 - interrupt mask word two (e1) (page 1, address 1dh)
mt9076b data sheet 113 zarlink semiconductor inc. bit name functional description 7 hdlc0im hdlc0 interrupt mask . when unmasked an interrupt is triggered by an unmasked event in hdlc0. if 1 - unmasked, 0 - masked. 6 hdlc1im hdlc1 interrupt mask . when unmasked an interrupt is triggered by an unmasked event in hdlc1. if 1 - unmasked, 0 - masked. 5 hdlc2im hdlc2 interrupt mask . when unmasked an interrupt is triggered by an unmasked event in hdlc2. if 1 - unmasked, 0 - masked. 4jaim jitter attenuation interrupt mask. when unmasked, an interrupt will be initiated when the jitter attenuator fifo comes within four bytes of an overflow or underflow condition. if 1 - unmasked, 0 - masked. 3 1secim one second status interrupt mask . when unmasked (1seci = 1), an interrupt is initiated when the 1sec status bit changes from zero to one. if 1- unmasked, 0 - masked. 2 5secim five second status interrupt mask . when unmasked (5seci = 1), an interrupt is initiated when the 5seci status bit changes from zero to one. if 1- unmasked, 0 - masked. 1rcrim rcri interrupt mask. whenever an unmasked (rcri=1), an interrupt is initiated when rcr (remote alarm & crc-4 error) status bit changes fr om zero to one. if 1- unmasked, 0 - masked. 0sigim signaling (cas) interrupt mask . when unmasked and any of the receive abcd bits of any channel changes state an interrupt is initiated. if 1 - unmasked, 0 - masked. table 100 - interrupt mask word three (e1) (page 1, address 1eh)
mt9076b data sheet 114 zarlink semiconductor inc. table 101 - liu receive word (e1) (page 1, address 1fh) bit name functional description 7nrz nrz format selection . only used in the digital framer only mode (liu is disabled). a one sets the mt9076 to ac cept a unipolar nrz format input stream on rxa as the line input, and to transmit a unipolar nrz format stream on txb. a zero causes the mt9076 to accept a complementary pair of dual rail inputs on rxa/rxa and to tr ansmit a complementary pair of dual rail outputs on txa/txb. 6 - 5 - - - reserved . set these bits low for normal operation. 4-3 rxa1-0 automatic receive equalizer control . these bits should be programmed according to the table below: 00 equalization will be activated using the control bits rxeq2-0 11 the receive equalizer is turned on and will compensate for loop length automatically. the control bits rxeq2-0 will be ignored. 01, 10 reserved for factory purposes. 2-0 rxeq2-0 receive equalization select . setting these pins forces a level of equalization of the incoming line data. res2 res1 res0 receive equalization 0 0 0 none 001 8 db 0 1 0 16 db 0 1 1 24 db 1 0 0 32 db 1 0 1 40 db 1 1 0 48 db 1 1 1 reserved these settings have no effect if eit her of rxa1 and rxa0 are set to one.
mt9076b data sheet 115 zarlink semiconductor inc. 20.4 master control 2 (page-2) 20.4.1 master control 2 (page 02h) (e1) address (a 4 a 3 a 2 a 1 a 0 ) register names 10h (table 103) configuration control word t1/e1, txen, liuen , elos, tx8ken, adseq 11h (table 104) liu tx word wr, pk2, pk1, cpl, txlb2-0 12h reserved set all bits to zero for normal operation. 13h (table 105) jitter attenuator control word jfc, jfd2-jfd0, jacl 14h reserved set all bits to zero for normal operation. 15h reserved set all bits to zero for normal operation. 16h (table 106) equalizer high threshold eht7-0 17h (table 107) equalizer low threshold elt7-0 18h (table 108) serial bit rate ima,8men,8mts1-0 19h (table 109) hdcl0 select en, sasel , ch4-0 1ah (table 110) hdcl1 select en, ch4-0 1bh (table 111) hdlc2 select en, ch4-0 1ch (table 112) custom pulse word 1 cp6-0 1dh (table 113) custom pulse word 2 cp6-0 1eh (table 114) custom pulse word 3 cp6-0 1fh (table 115) custom pulse word 4 cp6-0 table 102 - master control 2 (page 02h) (e1)
mt9076b data sheet 116 zarlink semiconductor inc. bit name functional description 7t1/e1 e1 mode selection. when this bit is one, the device is in e1 mode. 6- - reserved. must be kept at 0 for normal operation. 5txen transmit enable. setting this bit low turns off t he ttip and tring output line drivers. setting this bit high enables them. 4liuen liu enable. setting this bit low enables the internal liu front-end. setting this pin high disables the liu. digital inputs rxa and rxb are sampled by the rising edge of e2.0i (exclk) to strobe in the received line data. digital tr ansmit data is clocked out of pins txa and txb with the rising edge of c2.0o 3elos elos enable . set this bit low to set the analog loss of signal threshold to 40 db below nominal. set this bit high to set the analog loss of signal threshold to 20 db below nominal. 2 tx8ken transmit 8 khz enable. if one, the pin rxmf /txfp transmits a positive 8 khz frame pulse synchronous with the serial data stream tr ansmit on txa/txb. if zero, the pin rxmf /txfp transmits a negative frame pulse synchronous with the multiframe boundary of data coming out of dsto. 1 adseq digital milliwatt or digital test sequence . if one, the a-law digi tal milliwatt analog test sequence will be selected by the per time slot control bits ttst and rtst.if zero, a prbs generator / detector will be connected to channels with ttst, rrst respectively 0- - reserved. set this bit low for normal operation. table 103 - configuration control word (page 2, address 10h) (e1)
mt9076b data sheet 117 zarlink semiconductor inc. bit name functional description 7wr winding ratio. set this pin low if a 1:2.4 transformer is used on the transmit side. set this pin high if a 1:2 transformer is used. 6-4 - - reserved. must be kept at 0 for normal operation. 3cpl custom pulse level. setting this bit low enables the in ternal rom values in generating the transmit pulses. the rom is coded for different line terminations or build out, as specified in the liu control word. setting this pin high disables the pre-programmed pulse templates. each of the 4 phases that generate a mark derive their d/ a coefficients from the values programmed in the cpw registers. 2 - 0 tx2-0 transmit pulse amplitude. select the tx2 ?tx0 bits according to the line type, value of termination resistors (rt), and transformer turns ratio used. tx2 tx1 tx0 000 001 010 011 100 101 110 111 line impedance (ohms) 120 120 120 75 - 75 75 75 rt(ohms) 0 6.8 6.8 5.1 - 6 6 5.1 transformer ratio 1:2.4 1:2 1:2.4 1:2.4 - 1:2 1:2 1:2.4 wr (bit 7) 0 0 0 0 - 1 1 0 after reset, these bits are zero. table 104 - liu tx word (page 2, address 11h) (e1)
mt9076b data sheet 118 zarlink semiconductor inc. bit name functional description 7- - - unused. 6jfc jitter attenuator fifo centre. when this bit is toggled t he read pointer on the jitter attenuator shall be centered. du ring this centering the jitter on the ja outputs is increased by 0.0625 u.i. 5 - 3 jfd2-jfd0 jitter attenuator fifo depth control bits. these bits determine the depths of the jitter attenuator fifo as shown below: jfd2 jfd1 jfd0 depth 0 0 0 16 0 0 1 32 0 1 0 48 0 1 1 64 1 0 0 80 1 0 1 96 1 1 0 112 1 1 1 128 2jacl jitter attenuator fifo clear bit. if one, the jitter attenuator, its fifo and status are reset. the status registers will identify the fifo as be ing empty. however, the actual bit values of the data in the ja fifo will not be reset. 1 - 0 - - - unused. table 105 - jitter attenuation control word (page 2, address 13h) (e1) bit name functional description 7-0 eht7-0 equalizer high threshold. these bits set the highest possible binary count tolerable coming out of the equalized signal peak detector before a lower level of equalization is selected. this register is only used when a/d based automatic equalization is selected using the rx liu control word. the recommended value to program is 10111011. table 106 - equalizer high threshold (page 2, address 16h) (e1) bit name functional description 7-0 elt7-0 equalizer low threshold. these bits set the lowest possible binary count tolerable coming out of the equalized signal peak detector before a higher level of equalization is selected. this register is only used when a/d based aut omatic equalization is selected using the rx liu control word. the recommended value to program is 00110000. table 107 - equalizer low threshold (page 2, address 17h) (e1)
mt9076b data sheet 119 zarlink semiconductor inc. bit name functional description 7 - 6 - - reserved. must be kept at 0 for normal operation. 5ima inverse mux mode. setting this bit high the i/o ports to allow for easy connection to the zarlink mt90220. dsti becomes a serial 2.048 data stream. c4b becomes a 2.048 mhz clock that clocks dsti in on the falling edge. rx fp becomes a positive framing pulse that is high for the first bit of the serial e1 stream co ming from the pin dsto. the data from dsto is clocked out on the rising edge of exclk. set this pin low for all other applications. 4 - 3 - - reserved. must be kept at 0 for normal operation. 28men 8 mb/s bit rate select. setting this bit low enables a serial bit rate on dsti, csti and dsto,csto of 2.048 mb/s. setting this bit high enables a gapped serial bit rate of 8.192 mb/s on dsti, csti, dsto and csto. 1 - 0 8mts1- 0 8 mb/s time slot select. these two bits select the active timeslots on the serial 8.192 mb/s channels. during the active timeslots incoming serial data on dsti and csti is clocked into the device, and data is clocked out onto ds to and csto. during inactive timeslots dsto and csto are tristate. for all selections ev ery fourth 8 mb/s timeslot is active. the timeslot selection is as follows: 8mts1 8mst0 active timeslots 0 0 0,4,8,12,16,20,24,28,32,36,40,44, 48,52,56,60,64,68,72,76,80,84,88,92 96,100,104,108,112,116,120,124 0 1 1,5,9,13,17,21,25,29, 33,37,41,45,49,53,57, 61,65,69,73,77,81,85,89,93 97,101,105,109,113,117,121,125 1 0 2 ,6,10,14,18,22,26,30,34,38,42 ,46,50,54,58,62,66,70, 74,78,82,86, 90, 94, 98,102,106,110,114,118,122,126 1 1 3,7,11,15,19,23,27, 31,35,39,43,47,51,55,5 9,63,67,71,75,79,83, 87,91,95,99,103,107,111,115,119,123,127 table 108 - serial bit rate (page 2, address 18h) (e1) bit name functional description 7en enable. set high to attach the hdlc0 controller to the channel specified below. set low to disconnect the hdlc0. 6 sasel sa bits select. set this bit to 0 to attach hdlc0 to the sa bits. set this bit to 1 to attach hdlc0 to a payload timeslot. 5- - reserved. must be kept at 0 for normal operation. 4-0 ch4-0 channel 4-0. this 5 bit number specifies the channel time hdlc0 will be attached to if enabled. channel 0 is the first channe l in the frame. channel 31 is the last channel in an e1 frame. if enabled in a channel, hdlc data w ill be substituted for data from dsti on the transmit side. receiv e data is extracted from the incoming line data before the elastic buffer. table 109 - hdlc0 select (page 2, address 19h) (e1)
mt9076b data sheet 120 zarlink semiconductor inc. bit name functional description 7en enable. set high to attach the hdlc1 controller to the channel specified below. set low to disconnect the hdlc1. 6-5 - - reserved. must be kept at 0 for normal operation. 4-0 ch4-0 channel 4-0. this 5 bit number specifies the channel time hdlc1 will be attached to if enabled. channel 0 is the first channe l in the frame. channel 31 is the last channel in an e1 frame. if enabled in a channel, hdlc data w ill be substituted for data from dsti on the transmit side. receiv e data is extracted from the incoming line data before the elastic buffer. chann el 0 selection is unavailable to this controller. table 110 - hdlc1 select (page 2, address 1ah) (e1) bit name functional description 7en enable. set high to attach the hdlc2 controller to the channel specified below. set low to disconnect the hdlc2. 6-5 - - reserved. must be kept at 0 for normal operation. 4-0 ch4-0 channel 4-0. this 5 bit number specifies the channel time hdlc2 will be attached to if enabled. channel 0 is the first channel in the fr ame. channel 31 is the last channel in an e1 frame. if enabled in a channel, hdlc data will be substituted for dat a from dsti on the transmit side. receive data is extracted from the incoming line data before the elastic buffer. channel 0 selection is unavailable to this controller. table 111 - hdlc2 select (page 2, address 1bh) (e1) bit name functional description 7- - reserved. must be kept at 0 for normal operation. 6-0 cp6-0 custom pulse. these bits provide the capability for programming the magnitude setting for the ttip/tring line driver a/d converter during the first phase of a mark. the greater the binary number loaded into the register, the gr eater the amplitude driven out. this feature is enabled when the control bit 3 - cpl of the custom tx pulse enable register - address 11h of page 2 is set high table 112 - custom pulse word 1 (page 2, address 1ch) (e1)
mt9076b data sheet 121 zarlink semiconductor inc. bit name functional description 7- - reserved. must be kept at 0 for normal operation. 6-0 cp6-0 custom pulse. these bits provide the capability for programming the magnitude setting for the ttip/tring line driver a/d converter duri ng the second phase of a mark. the greater the binary number loaded into the register, the greater the amplitude driv en out. this feature is enabled when the control bit 3 - cpl of the custom tx pulse enable register - address 11h of page 2 is set high table 113 - custom pulse word 2 (page 2, address 1dh) (e1) bit name functional description 7- - reserved. must be kept at 0 for normal operation. 6-0 cp6-0 custom pulse. these bits provide the capability for programming the magnitude setting for the ttip/tring line driver a/d converter duri ng the third phase of a mark. the greater the binary number loaded into the register, the gr eater the amplitude driven out. this feature is enabled when the control bit 3 - cpl of the custom tx pulse enable register - address 11h of page 2 is set high table 114 - custom pulse word 3 (page 2, address 1eh) (e1) bit name functional description 7- - reserved. must be kept at 0 for normal operation. 6-0 cp6-0 custom pulse. these bits provide the capability for programming the magnitude setting for the ttip/tring line driver a/d converter during the fourth phase of a mark. the greater the binary number loaded into the register, the gr eater the amplitude driven out. this feature is enabled when the control bit 3 - cpl of the custom tx pulse enable register - address 11h of page 2 is set high table 115 - custom pulse word 4 (page 2, address 1fh) (e1)
mt9076b data sheet 122 zarlink semiconductor inc. 20.5 master status 1 (page 03h) (e1) address (a 4 a 3 a 2 a 1 a 0 ) register function 10h (table 117) synchronization status word sync mfsync crcsyn reb1 reb2 crcrf red crciwk 11h (table 118) alarm status word 1 crcs1 crcs2 rfail loss ais16s aiss rais rcrs 12h (table 119) timer status word 1sec, 2sec, 400t, 8t, caln, klve, t1,t2 13h (table 120) most significant phase status word rslip, rslpd, rxfrm, auxp, rxft, rxsbd2-0 14h (table 121) least significant phase status word rxts4-0, rxbc2-0 15h (table 122) receive frame alignment signal riu0 &rfa2-8 16h (table 123) receive signal status word llos 17h (table 124) jitter attenuator status word jacs, jacf, jae, jaf4, jafc, jae4, jaf 18h (table 125) receive non-frame alignment signal riu1, rnfab, ralm, &rnu4-8 19h (table 126) receive multiframe alignm ent signal rmai1-4, x1, y, x2, & x3 1ah (table 127) sa bits report word sa5, sa6nibble, c8sa6, csa6, rxsa3-0 1bh (table 128) alarm status word 2 rais, aiss, ais16s, loss, auxps, mfalms, slips 1ch --- reserved. 1dh (table 129) analog peak detector ap7-0 1eh --- reserved. 1fh (table 130) identification word set to 01111000 table 116 - master status 1 (page 3) (e1)
mt9076b data sheet 123 zarlink semiconductor inc. bit name functional description 7 sync receive basic frame alignment . sync indicates the basic frame alignment status (1 - loss; 0 - acquired). 6 mfsync receive multiframe alignment . mfsync indicates the multifra me alignment status (1 - loss; 0 -acquired). 5 crcsyn receive crc-4 synchronization . crcsyn indicates the crc-4 multiframe alignment status (1 - loss; 0 - acquired). 4 reb1 receive e-bit one status . reb1 indicates the status of t he received e1 bit of the last multiframe. 3 reb2 receive e-bit two status . reb2 indicates the status of the received e2 bit of the last multiframe. 2 crcrf crc-4 reframe. a one indicates that the receive crc- 4 multiframe synchronization could not be found within the time out period of 8 msec. after detecting basic frame synchronization. this will force a reframe wh en the maintenance op tion is selected and automatic crc-4 interwor king is de-selected. 1red red alarm . red goes high when basic frame alignment has been lost for at least 100 msec. this bit will be low when basic frame alignment is acquired (i.431). 0 crciwk crc-4 interworking . crciwk indicates the crc-4 interw orking status (1 - crc-to-crc; 0 - crc-to-non-crc). table 117 - synchronization status word (page 3, address 10h) (e1)
mt9076b data sheet 124 zarlink semiconductor inc. bit name functional description 7 crcs1 receive crc error status one . if one, the evaluation of th e last received submultiframe 1 resulted in an error. if zero, the last submultiframe 1 was error free. updated on a submultiframe 1 basis. 6 crcs2 receive crc error status two . if one, the evaluation of the last received submultiframe 2 resulted in an error. if zero, the last submultiframe 2 was error free. updated on a submultiframe 2 basis. 5 rfail remote crc-4 multiframe ge nerator/detector failure . if one, then each of the previous five seconds have an e-bit error count of greater than 989, and for this same period the receive rai bit was zero (no remote alarm), and for the same period the sync bit was equal to zero (basic frame alignment has been main tained). if zero, indi cates normal operation. 4 loss loss of signal status . if one, indicates the presence of a loss of signal condition. if zero, indicates normal operation. a lo ss of signal condition occurs when excess consecutive bit periods are zero. the threshold for this condition is set by the control bit l32z. if l32z is set high the threshold is 32 successive zeros. if l32z is set low the threshold is 192 successive zeros. a loss of signal condition terminates w hen an average ones density of at least 12.5% has been received over a period of 192 contig uous pulse positions starting with a pulse. 3 ais16s alarm indication signal 16 status . if one, indicates an all ones alarm is being received in channel 16. if zero, normal oper ation. updated on a frame basis. 2 aiss alarm indication status signal . if one, indicates that a valid ais or all ones signal is being received. if zero, indicates that a valid ais si gnal is not being received. the criteria for ais detection is determined by the control bit asel. 1 rais remote alarm indication status . if one, there is currently a remote alarm condition (i.e., received a bit is one). if zero, normal operation. updated on a non- frame alignment frame basis. 0 rcrs rai and continuous crc error status . if one, there is currently an rai and continuous crc error condition. if zero, normal oper ation. updated on a multiframe basis. table 118 - alarm status word 1 (page 3, address 11h) (continued) (e1)
mt9076b data sheet 125 zarlink semiconductor inc. bit name functional description 7 1sec one second timer status . this bit changes state once every 0.5 second and is synchronous with the 2sec timer. this feature is not av ailable when the device is operated in freerun mode. 6 2sec two second timer status . this bit changes state once every second and is synchronous with the 1sec timer.this feature is not availabl e when the device is operated in freerun mode. 5 400t 400 msec. timer status . this bit changes state when the 400 msec. crc-4 multiframe alignment timer expires. 4 8t 8 msec. timer status . this bit changes state when the 8 msec. crc-4 multiframe alignment timer expires. 3 caln crc-4 alignment. this bit changes state every millisecond. when crc-4 multiframe alignment has been achieved state changes of this bit are synchronous with the receive crc-4 synchronization signal. 2 klve keep alive. this bit is high when the ais status bit has been high for at least 100 msec. this bit will be low when ais goes low (i.431). 1 t1 timer one . this bit will be high upon loss of term inal frame synchroni zation persisting for 100 msec. this bit shall be low when t2 becom es high. refer to i.431 section 5.9.2.2.3. 0 t2 timer two. this bit will be high when the mt9076 ac quires terminal frame synchronization persisting for 10 msec. this bit shall be lo w when non-normal oper ational frames are received. i.431 section 5.9.2.2.3. table 119 - timer status word (page 3, address 12h) (e1)
mt9076b data sheet 126 zarlink semiconductor inc. bit name functional description 7 rslip receive slip . a change of state (i.e., 1-to-0 or 0-to -1) indicates that a receive controlled frame slip has occurred. 6 rslpd receive slip direction . if one, indicates that the last received frame slip resulted in a repeated frame, i.e., syst em clock is faster than network cl ock. if zero, indicates that the last received frame slip resulted in a lost fram e, i.e., system clock is slower than network clock. updated on an rslip occurrence basis. 5 rxfrm receive frame delay. the most significant bit of the receive slip buffer phase status word. if one, the delay through the receiv e elastic buffer is greater than one frame in length; if zero, the delay through the receive elas tic buffer is less than one frame in length. 4 auxp auxiliary pattern . this bit will go high when a cont inuous 101010.. . bit stream (auxiliary pattern) is received on the pcm 30 link for a pe riod of at least 512 bits. if zero, auxiliary pattern is not being received. this pattern will be decoded in the presence of a bit error rate of as much as 10-3. 3 rxft receiver frame toggle. this bit toggles on the falling edge of rxts4. 2-0 rxsbd2-0 receive sub bit delay. the three least significant bits of the receive slip buffer phase status word. they indicate the clock, half clock and one eight clock cycle depth of the phase status word sample point (bits 2, 1, o respectively). table 120 - most significant phase status word (page 3, address 13h) (e1) bit name functional description 7 - 3 rxts4 - 0 receive time slot . a five bit counter that indicates th e number of time slots between the receive elastic buffer internal write frame boundary and the st-bus read frame boundary. the count is updated every 250 us. 2 - 0 rxbc2 - 0 receive bit count . a three bit counter that indicates the number of stbus bit times there are between the receive elastic buffer intern al write frame boundary and the st-bus read frame boundary. the count is updated every 250 us. table 121 - least significant phase status word (page 3, address 14h) (e1) bit name functional description 7riu0 receive international use zero . this is the bit which is received on the pcm 30 2048 kbit/sec. link in bit position one of the fram e alignment signal. it is used for the crc-4 remainder or for international use. 6 - 0 rfa2-8 receive frame alignment signal bits 2 to 8 . these bit are received on the pcm 30 2048 kbit/sec. link in bit positions two to eight of frame alignment signal. these bits form the frame alignment signal and should be 0011011. table 122 - receive frame alignment signal (page 3, address 15h) (e1)
mt9076b data sheet 127 zarlink semiconductor inc. bit name functional description 7 lloss liu loss of signal indication . this bit will be high if t he received signal is below the threshold selected by elos (page 2, address 10 h) for a period of at least 1 msec. this bit will be low for normal operation. 6-0 - - - unused. table 123 - receive signal status word (page 3, address 16h) (e1) bit name functional description 7 jacs jitter attenuated clock slow . if one it indicates that the de jittered clock period is increased by 1/16 ui. if zero the clock is at normal speed. 6 jacf jitter attenuated clock fast . if one it indicates that the dejittered clock period is decreased by 1/16 ui. if zero the clock is at normal speed. 5 jae jitter attenuator fifo empty . if one it indicates that the ja fifo is empty. 4 jaf4 jitter attenuator fifo with 4 full locations . if one it indicates that the ja fifo has at least 4 full locations. 3 jafc jitter attenuator center full. if one it indicates that the ja fifo is at least half full. 2 jae4 jitter attenuator fifo with 4 empty locations . if one it indicates that the ja fifo has at most 4 empty locations. 1 jaf jitter attenuator fifo full . if one it indicates that the ja fifo is full. 0 - - - unused . table 124 - jitter attenuator status word (page 3, address 17h) (e1)
mt9076b data sheet 128 zarlink semiconductor inc. bit name functional description 7 riu1 receive international use 1. this bit is received on the pcm 30 2048 kbit/sec. link in bit position one of the non-frame al ignment signal. it is used for crc-4 multiframe alignment or international use. 6 rnfab receive non-frame alignment bit. this bit is received on the pcm 30 2048 kbit/sec. link in bit position two of the non-frame alignment signal. this bit should be one in order to differentiate between frame alignment frames and non-frame alignment frames. 5 ralm receive alarm . this bit is received on the pcm 30 2048 kbit/sec. link in bit position three (the a bit) of the non-frame a lignment signal. it is used as a remote alarm indication (rai) from the far end of the pcm 30 link (1 - alarm, 0 - normal). 4-0 rnu4-8 receive national use four to eight . these bits are received on the pcm 30 2048 kbit/sec. link in bit positions four to eight (the sa bits) of the non-frame alignment signal. table 125 - receive non-frame alignment signal (page 3, address 18h) (e1) bit name functional description 7-4 rmai1-4 receive multiframe alignment bits one to four . these bits are received on the pcm 30 2048 kbit/sec. link in bit positions one to four of time slot 16 of frame zero of every signaling multiframe. these bit should be 0000 fo r proper signaling mult iframe alignment. 3 x1 receive spare bit x1 . this bit is received on the pcm 30 2048 kbit/sec. link in bit position five of time slot 16 of frame ze ro of every signaling multiframe. 2 y receive y-bit. this bit is received on the pcm 30 2048 kb it/sec. link in bit position six of time slot 16 of frame zero of every signaling multiframe. the y bit may indicate loss of multiframe alignment at the remote end (1 -loss of mult iframe alignment; 0 - multiframe alignment acquired). 1-0 x2, x3 receive spare bits x2 and x3. these bits are received on the pcm 30 2048 kbit/sec. link in bit positions seven and eight respectively, of time slot 16 of frame zero of every signaling multiframe. table 126 - receive multiframe alignment signal (page 3, address 19h) (e1)
mt9076b data sheet 129 zarlink semiconductor inc. bit name functional description 7 sa5 sa 5 bit . the sa5 bit is latched and reported here upon receipt of the eighth of consecutive instance of a new sa6 nibble. 6 csa6nibble changed sa6 nibble . this bit changes state upon detection of a change of state of incoming sa6 nibbles. 5 c8sa6 changed eight sa6 bit . this bit toggles upon receipt of the eighth of consecutive instance of a new sa6 nibble. 4 csa6 changed sa6 bit . this bit toggles in the event of a change of state in the received sa6 bit. 3 - 0 rxsa 3-0 receive sa nibble three to zero . this register contains the contents of the last sa6 nibble received. it is updated upon receipt of the eighth of consecutive instance of a new sa6 nibble. table 127 - sa bits report word (page 3, address 1ah) (e1) bit name functional description 7 rais remote alarm i ndication status . if one, there is currently a remote alarm condition (i.e., received a bit is one). if zero, normal operatio n. updated on a non-frame alignment frame basis. 6 aiss alarm indication status signal . if one, indicates that a valid ai s or all ones signal is being received. if zero, indicates that a valid ais signa l is not being received. the criteria for ais detection is determined by the control bit asel. 5 ais16s alarm indication si gnal 16 status . if one, indicates an all ones alarm is being received in channel 16. if zero, normal operation. updated on a frame basis. 4 loss loss of signal status . if one, indicates the presence of a loss of signal condition. if zero, indicates normal operation. a loss of signal c ondition occurs when an excess consecutive bit periods are zero. the threshold for this condition is set by the control bit l32z. if l32z is set high the threshold is 32 successive zeros. if l32z is set low the threshold is 192 successive zeros. a loss of signal condition terminates when an average ones density of at least 12.5% has been received over a period of 192 conti guous pulse positions starting with a pulse. 3 auxps auxiliary pattern status . this bit goes on high when a continuous 101010... bit stream (auxiliary pattern) is received on the pcm 30 link for a period of at least 512 bits. if zero, auxiliary pattern is not being received. this pattern will be decoded in the presence of a bit error rate of as much as 10-3. 2 mfalms multiframe alarm status . this bit goes high in the event of receipt of a multiframe alarm. it goes low when the received multiframe alarm bit goes low. 1 rslips receive slip status . a change of state (i.e., 1-to-0 or 0-to-1) indicates that a receive controlled frame slip has occurred. 0 - - - unused . table 128 - alarm status word 2 (page 3, address 1bh) (e1)
mt9076b data sheet 130 zarlink semiconductor inc. bit name functional description 7 - 0 ap7-0 analog peak detector . this status register gives the ou tput value of a 8 bit a/d converter connected to a peak detector on rtip/rring. table 129 - analog peak detector (page 3, address 1dh) (e1) bit name functional description 7-0 id7-0 id number. contains device code 01111000 table 130 - identification word (page 3, address 1fh) (e1)
mt9076b data sheet 131 zarlink semiconductor inc. 21.0 master status 2 (page-4) 21.1 master status 2 (page 04h) (e1) address (a 4 a 3 a 2 a 1 a 0 ) register function 10h (table 132) prbs error counter ps7-0 11h (table 133) crc multiframe counter for prbs psm7-0 12h (table 134) alarm reporting latch rai, ais, ais16, los, auxp, mfalm, rslip 13h (table 135) errored frame alignment signal counter efas7-0 14h (table 136) e-bit error counter ebt ec15-ec8 15h (table 137) e-bit error counter ebt ec7-ec0 16h (table 138) most significant line code violation error counter lcv15 - lcv8 17h (table 139) least significant line code violation error counter lcv7 - lcv0 18h (table 140) crc- 4 error counter cet cc15-cc8 19h (table 141) crc- 6 error counter cet cc7 - cc0 1ah unused. 1bh (table 142) interrupt word zero tfsyni, mfsyni, crcsyni,aisi, losi, cefi,yi, rxslpi 1ch (table 143) interrupt word one ferri, crcerri, ebiti, ais16i, lcvi, prbserri, auxpi, raii, 1dh (table 144) interrupt word two ferro,crco,febeo,lcvo,prbso,prbs mfo, sai 1eh (table 145) interrupt word three hdlc0i,hdlc1i,hdlc2,jai,1seci,5seci,rc ri,sigi 1fh (table 146) overflow r eporting latch ferrol,crcol,febeol,lcvol, prbsol, prbsmfol table 131 - master status 2 (page 4) (e1) bit name functional description 7 - 0 ps7-0 this counter is incremented for each prbs error detected on any of the receive channels connected to the prbs error detector. table 132 - prbs error counter (page 4, address 10h) (e1)
mt9076b data sheet 132 zarlink semiconductor inc. bit name functional description 7 - 0 psm7-0 this counter is incremented for each re ceived crc multiframe. it is cleared when the prbs error counter is written to. table 133 - crc multiframe counter for prbs (page 4, address 11h) (e1) bit name functional description 7 rai remote alarm indication . this bit is set to one in the event of receipt of a remote alarm, i.e., a(rai) = 1. it is cleared when the register is read. 6 ais alarm indication signal. this bit is set to one in the event of receipt of an all ones alarm. it is cleared when the register is read. 5 ais16 ais time slot 16 alarm . this bit is set to one in the event of receipt of an all ones alarm in the time slot 16. it is cleared when the register is read. 4 los loss of signal . this bit is set to one in the event of loss of received signal. it is cleared when the register is read. 3 auxp auxiliary alarm. this bit is set to one in the event of receipt of the auxiliary alarm pattern. it is cleared when the register is read. 2 mfalm multiframe alarm . this bit is set to one in the event of receipt of a multiframe alarm. it is cleared when the r egister is read. 1 rslip received slip . this bit is set to one in the event of receive elastic buffer slip. it is cleared when the register is read. 0 - - - unused . table 134 - alarm reporting latch (page 4, address 12h) (e1) bit name functional description 7 - 0 efas7 - 0 errored fas counter . an 8 bit counter that is incremented once for every receive frame alignment signal that cont ains one or more errors. table 135 - errored frame alignment signal counter (page 4, address 13h) (e1) bit name functional description 1-0 ec15-8 e bit error counter. the most significant bits of the e bit error counter. table 136 - e-bit error counter (page 4, address 14h) (e1)
mt9076b data sheet 133 zarlink semiconductor inc. bit name functional description 7 - 0 ec7-0 e bit error counter. the least significant 8 bits of the e-bit error counter. table 137 - e-bit error counter (page 4, address 15h) (e1) bit name functional description 7 - 0 lcv15 - 8 most significant bits of the lcv counter. the most significant eight bits of a 16 bit counter that is incremented once for every li ne code violation received. a line code is defined as a bipolar violation that is not a part of hdb3 encoding where the control bit exz is set low. where exz is set high a violat ion is defined as either a non-hdb3 bipolar violation or an occurrence of excess zeros. table 138 - most significant bits of the lcv counter (page 4, address 16h) (e1) bit name functional description 7 - 0 lcv7 - 0 least significant bits of the lcv counter . the least significant eight bits of a 16 bit counter that is incremented once for every line code violation received. a line code is defined as a bipolar violation that is not a part of hdb3 encoding where the control bit exz is set low. where exz is set high a violat ion is defined as either a non-hdb3 bipolar violation or an occurrence of excess zeros. table 139 - least significant bits of the lcv counter (page 4, address 17h) (e1) bit name functional description 7-0 cc15 - 8 crc-4 error counter these are the most si gnificant eight bits of the crc-6 error counter. table 140 - crc-4 error counter cet (page 4, address 18h) (e1) bit name functional description 7 - 0 cc7 - 0 crc-6 error counter. these are the least significant eight bits of the crc-4 error counter. table 141 - crc-6 error counter cet (page 4, address 19h) (e1)
mt9076b data sheet 134 zarlink semiconductor inc. bit name functional description 7 tfsyni terminal frame synchronization interrupt . when unmasked this interrupt bit goes high whenever a change of state of terminal frame sy nchronization condition exists. reading this register clears this bit. 6 mfsyni multiframe synchronization interrupt . when unmasked this interrupt bit goes high whenever a change of state of multiframe sy nchronization condition exists. reading this register clears this bit. 5 crcsyni crc-4 synchroniza tion interrupt. when unmasked this interrupt bit goes high whenever change of state of crc-4 synchronization condit ion exists. reading this register clears this bit. 4aisi alarm indication signal interrupt . when unmasked this interrupt bit goes high whenever a change of state of received all ones condition exists. reading this register clears this bit. 3losi loss of signal interrupt . when unmasked this interrupt bit goes high whenever a loss of signal (either analog - received signal 20 or 40 db below nominal or digital - excess consecutive 0?s received) condition exists. 2cefi consecutively errored frame alignment interrupt . when unmasked this interrupt bit goes high whenever the last two frame alignment signals have errors. reading this register clears this bit. 1yi receive y-bit interrupt . when unmasked this interrupt goes high whenever loss of multiframe alignment occurs. reading this register clears this bit. 0rxslpi receive slip interrupt . when unmasked this interrupt bit goes high whenever a controlled frame slip occurs in the receive elastic buffe r. reading this register clears this bit. table 142 - interrupt word zero (page 4, address 1bh) (e1)
mt9076b data sheet 135 zarlink semiconductor inc. bit name functional description 7 ferri errored framing alignment signal interrupt. when unmasked this interrupt bit goes high whenever an erroneous bit in frame alignm ent signal is detected (provided the circuit is in terminal frame sync). readin g this register clears this bit. 6 crcerri crc-4 error interrupt . when unmasked this interrupt bit goes high whenever a local crc-4 error occurs. reading this register clears this bit. 5 ebiti receive e-bit error interrupt . when unmasked this interrupt bit goes high upon detection of a wrong e-bit in multiframe . reading this register clears this bit. 4ais16i alarm indication signal interrupt . when unmasked this interrupt bit goes high whenever all ones in time slot 16 occur.r eading this register clears this bit. 3lcvi bipolar violation interrupt . when unmasked this interrupt bit goes high whenever a line code violation (excluding hdb3 encoding) is encount ered. reading this register clears this bit. 2 prbserri pseudo random bit sequence error interrupt . when unmasked this interrupt bit goes high upon detection of an error with a chann el selected for prbs testing. reading this register clears this bit. 1 auxpi auxiliary pattern alarm interrupt . when unmasked this interrupt bit goes high whenever a sequence of 512 bit consecutive 101010. occur. reading this register clears this bit. 0raii remote alarm indication interrupt. when unmasked this interrupt bit goes high whenever the bit 3 of non-frame alignment signal is high. reading this register clears this bit. table 143 - interrupt word one (page 4, address 1ch) (e1)
mt9076b data sheet 136 zarlink semiconductor inc. bit name functional description 7 ferro errored framing alignment signal counter overflow interrupt . when unmasked this interrupt bit goes high whenever the errored frame alignment signal counter changes from ffh to 00h. reading this register clears this bit. 6 crco crc error counter overflow interrupt . when unmasked this interrupt bit goes high whenever the crc error counter changes from ffh to 00h. reading this register clears this bit. 5 - - - unused. 4 febeo e-bit counter overflow interrupt . when unmasked this interrupt bit goes high whenever the e-bit counter changes from ffh to 00h. reading this register clears this bit. 3lcvo line code violation counter overflow interrupt. when unmasked this interrupt bit goes high whenever the line code violation count er changes from ffh to 00h. reading this register clears this bit. 2 prbso pseudo random bit sequence error counter overflow interrupt . when unmasked this interrupt bit goes high whenever the prbs error counter changes from ffh to 00h. reading this register clears this bit. 1 prbsmfo pseudo random bit sequence multiframe counter overflow interrupt. when unmasked this interrupt bit goes high whenever the multiframe counter attached to the prbs error counter overflows. ffh to 00h. 1 - unmasked, 0 - masked. 0sai sa bit interrupt. when unmasked this interrupt goes high whenever either a change of state of any of the received sa bits sa5, s a6, sa7 or sa8 (saborni = 1) or a change of state of any of the received sa nibbles (saborni = 0). the control bit saborni is located in page 1 address 12h bit 4. table 144 - interrupt word two (page 4, address 1dh) (e1)
mt9076b data sheet 137 zarlink semiconductor inc. bit name functional description 7 hdlc0i hdlc0 interrupt. whenever an unmasked hdlc0 interrupt occurs, this bit goes high. reading this regist er clears this bit. 6 hdlc1i hdlc1 interrupt. whenever an unmasked hdlc1 interrupt occurs, this bit goes high. reading this regist er clears this bit. 5 hdlc2i hdlc2 interrupt. whenever an unmasked hdlc2 interrupt occurs, this bit goes high. reading this regist er clears this bit. 4jai jitter attenuator error interrupt . whenever an unmasked jai interrupt occurs. if jitter attenuator fifo comes within four byte s of an overflow or underflow, this bit goes high. reading this regist er clears this bit. 3 1seci one second status interrupt. when unmasked this interrupt bit goes high whenever the 1sec status bit (page 3 address 12h bit 7) goes from low to high. reading this register clears this bit. 2 5seci five second status interrupt . when unmasked this interrupt bit goes high whenever the 5 sec status bit goes from low to high. reading this regist er clears this bit. 1 rcri rcri interrupt. whenever an unmasked rcri interrupt occurs. if remote alarm and crc error occur this bit goes high. readi ng this register clears this bit. 0sigi signaling interrupt . when unmasked this interrupt bit goes high whenever a change of state (optionally debounced - see dben in the data link, signaling control word) is detected in the signaling bits (ab or abcd) patt ern. reading this register clears this bit. table 145 - interrupt word three (page 4, address 1eh) (e1)
mt9076b data sheet 138 zarlink semiconductor inc. 21.2 per channel transmit signaling (pages 5 and 6) (e1) page 05h, addresses 10000 to 11111, and page 06h addresses 10000 to 10111 contain the transmit signaling control words for channel associated signaling (cas) channels 2 to 16 and 18 to 32 respectively. table 147 illustrates the mapping between the addresses of these pages and the cas channel numbers. control of these bits for any one channel is through the processor or controller po rt when the per time slot control bit rpsig bit is high. table 148 describes bit allocation within each of these registers. bit name functional description 7 ferrol errored frame alignment signal counter overflow latch . this bit is set when the errored frame alignment si gnal counter overflows. it is cleared after being read. 6 crcol crc error counter overflow latch . this bit is set when the crc error counter overflows. it is cleared after being read. 5 febeol e bit counter overflow latch. this bit is set when e bit counter overflows. it is cleared after being read. 4 - - - 3lcvol line code violation counter overflow latch . this bit is set when the line code violation counter overflows. it is cleared after being read. 2 prbsol pseudo random bit sequence error counter overflow latch . this bit is set when the prbs error counter overflow s. it is cleared after being read. 1prbsmfol pseudo random bit sequence multiframe counter overflow latch. this bit is set when the multiframe counter attached to the prbs error counter overflows. it is cleared after being read 0- - - unused . table 146 - overflow reporting latch (page 4, address 1fh) (e1) page 5-6 address: 0123456789101112131415 equivalent cas channel 12345678910111213141516 page 6 address: 0123456789101112131415 equivalent cas channel 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 table 147 - page 5, 6 address mapping to cas signaling channels (e1)
mt9076b data sheet 139 zarlink semiconductor inc. serial per channel transmit signaling c ontrol through csti is selected when rpsig bit is zero. table 149 describes the function of csti time slots 1 to 30. if msn bit is high, csti time slots 17 to 31 are selected. if msn bit is low, csti time slots 1 to 15 are selected. 21.3 per time slot control words (pages 7 and 8) (e1) the control functions described by table 151 are re peated for each pcm-30 channel. page 07h addresses 10h to 1fh correspond to time slots 0 to 15, while page 08h addresses 10h to 1fh correspond to time slots 16 to 31. table 150 illustrates the mapping between the addr esses of these pages and the cept channel numbers. bit name functional description 7 - 4 - - - unused . 3 - 0 a(n) b(n) c(n) d(n) transmit signaling bits for channel n. these bits are transmitted on the pcm 30 2048 kbit/sec. link in bit positions one to four of time slot 16 in frame n (when n = 1 to 15), and are the a, b, c, d si gnaling bits associated with channel n. table 148 - transmit channel associated signalling (e1) (pages 5 and 6) bit name functional description 7 - 4 a(n), b(n), c(n), d(n) transmit signaling bits for channel n . these bits are transmitted on the pcm 30 2048 kbit/sec. link in bit positions one to four of time slot 16 in frame n (where n = 1 to 15), and are the a, b, c, d signaling bits associated with channel n. 3 - 0 a(n), b(n), c(n), d(n) transmit signaling bits for channel n . these bits are transmitted on the pcm 30 2048 kbit/sec. link in bit positions one to four of time slot 16 in frame n (where n = 1 to 15), and are the a, b, c, d signaling bits associated with channel n. table 149 - e1 / transmit channels usage - csti note: this table illustrates bit mapping on the serial input stream - it does not refer to an internal register. page 8h address: 0123456789101112131415 equivalent pcm 30 timeslots 0123456789101112131415 page 9h address: 0123456789101112131415 equivalent pcm 30 timeslots 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 table 150 - mapping between the addresses of these pages and the cept channel numbers
mt9076b data sheet 140 zarlink semiconductor inc. 21.4 per channel receive signaling (pages 9 and 0ah) (e1) page 09h, addresses 10001 to 11111, and page 0ah addresses 10001 to 11111 contain the receive signaling control words for cas channels 2 to 16 and 18 to 32. table 153 illustrates the mapping between the addresses of these pages and the cas channel number s. table 154 describes bit allocati on within each of these registers. bit name functional description 7txmsg transmit message mode. if high, the data from the co rresponding address location of tx message mode buffer is transmitted in the corresponding pcm 30 time slot. if zero, the data on dsti is transmitted on the corresponding pcm 30 time slot. 6adi alternate digit inversion. if one, the corresponding transmit time slot data on dsti has every second bit inverted. if zero, th is bit has no effect on channel data. 5rtsl remote time slot loopback. if one, the corresponding pcm 30 receive time slot is looped to the corresponding pcm 30 transmit time slot. this received time slot will also be present on dsto. if zero, the loopback is disabled. 4ltsl local time slot loopback. if one, the corresponding transmit time slot is looped to the corresponding receive time slot. this transmit time slot will al so be present on the transmit pcm 30 stream. if zero, this loopback is disabled. 3 ttst transmit test. if one, a test signal, ei ther digital milliwatt (when co ntrol bit adseq is one) or prbs (2 15 -1) (adseq is zero), will be transm itted in the corresponding pcm 30 time slot. more than one time slot may be activated at once. if zero, the test signal will not be connected to the corresponding time slot. 2rtst receive test. if one, the corres ponding dsto time slot will be us ed for testing. if control bit adseq is one, a digital milliwatt signal will be transmit onto the dsto channel. if adseq is zero the receive chann el will be connected to the prbs detector (2 15 -1). 1 rpsig serial signaling enable. if one, the transmit cas signaling will be controlled by programming page 05h. if zero, the transmit cas signaling will be controlled through the csti stream. 0- - - unused. table 151 - per time slot control words (pages 7 and 8) (e1) page 9 address: 0123456789101112131415 equivalent pcm 30 timeslots 0123456789101112131415 page a address: 0123456789101112131415 equivalent pcm 30 timeslots 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 table 152 - page 9 and a address mapping to cas channels (e1)
mt9076b data sheet 141 zarlink semiconductor inc. serial per channel receive signaling status bits appear on st-bus stream csto. table 157 describes the bit allocation within each of the 30 active st-bus time slot of csto. bit name functional description 7 - 4 - - - unused 3 - 0 a(n) b(n) c(n) d(n) receive signaling bits for channel n. these bits are received on the pcm 30 2048 kbit/sec. link in bit positions one to four of time slot 16 in frame n (where n = 1 to 30) and are the a, b, c, d signaling bits associated with channel n. table 153 - receive channel associated signaling (pages 9 and a) (e1) bit name functional description 7 - 4 a(n), b(n), c(n), d(n) transmit signaling bits for channel n . these bits are transmitted on the pcm 30 2048 kbit/sec. link in bit positions one to four of time slot 16 in frame n (where n = 1 to 15), and are the a, b, c, d si gnaling bits associated with channel n. 3 - 0 a(n), b(n), c(n), d(n) transmit signaling bits for channel n . these bits are transmitted on the pcm 30 2048 kbit/sec. link in bit positions one to four of time slot 16 in frame n (where n = 1 to 15), and are the a, b, c, d si gnaling bits associated with channel n. table 154 - receive cas channels (csto) (e1)
mt9076b data sheet 142 zarlink semiconductor inc. 22.0 hdlc control and status (page b for hdlc0, page c for hdlc1 and page d for hdlc2) address register function control (write/verify) status (read) 10h (table 156) address recognition 1 - -- adr16-10,a1en 11h (table 157) address recognition 2 - -- adr26-20, a2en 12h (table 158/table 159) tx fifo rx fifo bit7-0 13h (table 160) hdlc control 1 - -- adrec, rxen, txen, eop, fa, mark-idle, tr, frun 14h (table 161) - -- hdlc status intgen, idle-chan, rq9, rq8, txstat2, txstat1, rxstat2, rxstat1 15h (table 162) hdlc control 2 - -- intsel, cycle, txcrci, seven, rxfrst, txfrst 16h (table 163) interrupt mask - -- gaim, rxeopim, txeopim, rxfeim, txflim, fa:txunderim, rxffim, rxovfim 17h (table 164) - -- interrupt status (*) ga, rxeop, txeop, rxfe, txfl, fa:txunder, rxff, rxovf 18h (table 165) - -- rx crc msb crc15-crc8 19h (table 166) - -- rx crc lsb crc7-crc0 1ah (table 167) low tx byte count - -- txcnt7-0 1bh (table 168) test control - -- hrst, rtloop, crctst, ftst, artst, hloop 1ch (table 169) - -- test status rxclk, txclk, vcrc, vaddr 1dh (table 170) hdlc control 3 - -- rsv, rfd2-0,rsv, tfd2-0 1eh (table 171) hdlc control 4 - -- rsv, rffs2-0, rsv, tfls2-0 1fh (table 172) extended tx byte count - -- txcnt15-8 table 155 - hdlc0, hdlc1, hdlc2 control and status (pages b, c, and d)
mt9076b data sheet 143 zarlink semiconductor inc. bit name functional description 7 - 2 adr16-11 address 16 - 11. a six bit address used for comparison with the first byte of the received address. adr16 is msb. 1 adr10 address 10. this bit is used in address comparis on if a seven bit address is being checked for (control bit four of control register 2 is set). 0a1en first address comparison enable. when this bit is high, the above six (or seven) bit address is used in the comparison of the first address byte. if address recognition is enable d, any packet failing the addr ess comparison will not be stored in the rx fifo. a1en must be high for all-call (1111111) address recognition for single byte address. when this bit is low, this bit mask is ignored in address comparison table 156 - hdlc address recognition register 1 (pages b, c, and d, address 10h) bit name functional description 7 - 1 adr26-20 address 26 - 20. a seven bit address used for comparison with the second byte of the received address. adr26 is msb. this mask is ignored (as well as first byte mask) if all call address (1 111111) is received. 0a2en second address comparison enable. when this bit is set high, the above seven bit address is used in the comparison of the second address byte. if address recognition is enabl ed, any packet failing the ad dress comparis on will not be stored in the rx fifo. a2en must be high for all-call address recognition. when this bit is low, this bit mask is ignored in address comparison. table 157 - hdlc address recognition register 2 (pages b,c, and d, address 11h) bit name functional description 7 - 0 bit7-0 this eight bit word is tagged with the two st atus bits from the control register 1 (eop and fa), and the resulting 10 bit word is written to the tx fifo. the fifo status is not changed immediately after a write or read occurs. it is updated after the data has settled and the transfer to the last avail able position has finished. table 158 - tx fifo write register (pages b, c, and d, address 12h) bit name functional description 7 - 0 bit7-0 this is the received data byte read from the rx fifo. the status bits of this byte can be read from the status register. the fifo status is not changed immediately when a write or read occurs. it is updated after the data has settled and the transfer to the last available position has finished. table 159 - rx fifo read register (pages b, c, and d, address 12h)
mt9076b data sheet 144 zarlink semiconductor inc. bit name functional description 7 adrec address recognition. when high this bit will enable addr ess recognition. this forces the receiver to recognize only those packets having the unique address as programmed in the receive address recognition registers or if the address is an all call address. 6rxen receive enable. when low this bit will disable the hdlc receiver. the receiver will disable after the rest of the packet presently being rece ived is finished. the receiver internal clock is disabled. when high the receiver will be immediately enabled and will begin searching for flags, go-aheads etc. 5txen transmit enable. when low this bit will disable the hdl c transmitter. the transmitter will disable after the completion of the packet presently being transmitted. the transmitter internal clock is disabled. when high the transmitter will be immediately enabled and will begin tr ansmitting data, if any, or go to a mark idle or interframe time fill state. 4eop end of packet. forms a tag on the next byte written the tx fifo, and when set will indicate an end of packet byte to the transmi tter, which will transmit an fcs following this byte. this facilitates loading of multiple packets into tx fifo. reset automatically after a write to the tx fifo occurs. 3fa frame abort. forms a tag on the next byte written to the tx fifo, and when set will indicate to the transmitter that it should abort the packet in which that byte is being transmitted. reset automatically after a write to the tx fifo. 2mark-idle mark - idle. when low, the transmitter will be in an idle state. when high it is in an interframe time fill state. these two states will only occur when the tx fifo is empty. 1tr transparent mode. when high this bit will enable transparent mode. this will perform the parallel to serial conversion with out inserting or deleting zero s. no crc bytes are sent or monitored nor are flags or abor ts. a falling edge of txen for transmit and a falling edge of rxen for receive is necessary to initialize tr ansparent mode. this will also synchronize the data to the transmit and receive channel stru cture. also, the transmitter must be enabled through control register 1 befor e transparent mode is entered. 0 frun freerun. when high the hdlc tx and rx are continuously enabled providing the rxen and txen bits are set . table 160 - hdlc control register 1 (pages b, c, and d, address 13h)
mt9076b data sheet 145 zarlink semiconductor inc. bit name functional description 7 intgen interrupt generated. set to 1 when an in terrupt (in conjunction with the interrupt mask register) has been generated by the hdlc. this is an asynchronous event. it is reset when the interrupt register is read. 6 idle chan idle channel. set to a 1 when an idle channel state (15 or more ones) has been detected at the receiver. this is an asynchronous event. on power reset, this may be 1 if the clock (rxc) was not operating. status becomes valid after the first 15 bits or the first zero is received. 5 - 4 rq9, rq8 byte status bits from rx fifo. these bits determine the status of the byte to be read from rx fifo as follows: rq9 rq8 byte status 0 0 packet byte 0 1 first byte 1 0 last byte of a good packet. 1 1 last byte of a bad packet. 3 - 2 txstat2-1 these bits determine the status of the tx fifo as follows: txstat2 txstat1 tx fifo status 0 0 tx fi fo full up to the selected status level or more. 0 1 the number of bytes in the tx fifo has reached or exceeded the selected interrupt threshold level. 1 0 tx fifo empty. 1 1 the number of bytes in the tx fifo is less than the selected interrupt threshold level. 1 - 0 rxstat2 - 1 these bits determine the status of the rx fifo as follows: rxstat2 rxstat1 rx fifo status 0 0 rx fifo empty 0 1 the number of bytes in the rx fifo is less than the in terrupt threshold level. 1 0 rx fifo full. 1 1 the number of bytes in the rx fifo has reached or exceeded the interrupt threshold level. table 161 - hdlc status register (pages b, c, and d address 14h)
mt9076b data sheet 146 zarlink semiconductor inc. bit name functional description 7 intsel interrupt selection. when high, this bit will cause bit 2 of the interrupt regi ster to reflect a tx fifo underrun (txunder). when low, this interrupt will reflect a frame abort (fa). 6cycle cycle. when high, this bit will cause the transmi t byte count to reload one minus the value initially loaded into the tr ansmit byte count register. 5 txcrci transmit crc inhibited. when high, this bit will inhibit tr ansmission of the crc. that is, the transmitter will not insert the computed crc onto the bit stream after seeing the eop tag byte. this is used in v.120 terminal adaptati on for synchronous protocol sensitive ui frames. 4 seven seven bit address recognition. when high, this bit will enable seven bits of address recognition in the first address byte. the received address byte must have bit 0 equal to 1 which indicates a single address byte is being received. 3- - reserved , must be zero for normal operation. 2- - reserved , must be zero for normal operation. 1rxfrst rx fifo reset. when high, the rx fifo will be reset. this causes the receiver to be disabled until the next reception of a flag. the status register will identify the fifo as being empty. however, the actual bit values in the rx fifo will not be reset. 0txfrst tx fifo reset. when high, the tx fifo will be reset. the status register will identify the fifo as being empty. this bit will be reset wh en data is written to the tx fifo. however, the actual bit values of data in the tx fifo will no t be reset. it is cleared by the next write to the tx fifo. table 162 - hdlc control register 2 (pages b, c, and d, address 15h) bit name functional description 7-0 gaim rxeopim txeopim rxfeim txflim fa:txunderrim rxffim rxovfim this register is used with t he interrupt register to mask out the interrupts that are not required by the microprocessor. interrupt s that are masked out will not drive the pin irq low; however, they will set the appropr iate bit in the interrupt register. an interrupt is disabled when the microprocessor writes a 0 to a bit in this register. this register is cleared on power reset. table 163 - hdlc interrupt mask register (pages b, c, and d, address 16h)
mt9076b data sheet 147 zarlink semiconductor inc. bit name functional description 7ga go ahead. indicates a go-ahead pattern was detected by the hdlc receiver. this bit is reset after a read. 6rxeop end of packet detected. this bit is set when an end of packet (eop) byte was written into the rx fifo by the hdlc receiver. this can be in the form of a flag, an abort sequence or as an invalid packet. this bit is reset after a read. 5txeop transmit end of packet. this bit is set when the transmitter has finished sending the closing flag of a packet or after a packet has been aborted. this bit is reset after read. 4rxfe end of packet read. this bit is set when the byte about to be read from the rx fifo is the last byte of the packet. it is also set if the rx fifo is read and there is no data in it. this bit is reset after a read. 3txfl tx fifo low. this bit is set when the tx fifo is emptied below the selected low threshold level. this bit is reset after a read. 2fa: txunder frame abort/tx fifo underrun. when intsel bit of control register 2 is low, this bit (fa) is set when a frame abort is received during packet reception. it must be received after a minimum number of bits have been receiv ed (26) otherwise it is ignored. when intsel bit of control register 2 is high, this bit is set for a tx fifo underrun indication. if high it indicates that a read by the transmitter was attempted on an empty tx fifo. this bit is reset after a read. 1rxff rx fifo full. this bit is set when the rx fifo is filled above the selected full threshold level. this bit is reset after a read. 0rxovf rx fifo overflow. indicates that the 128 byte rx fifo overflowed (i.e., an attempt to write to a 128 byte full rx fifo). the hdlc will al ways disable the receiver once the receive overflow has been detected. the receiver will be re-enabled upon detection of the next flag, but will overflow again unless the rx fifo is read. this bit is reset after a read. table 164 - hdlc interrupt status register (pages b, c, and d, address 17h) bit name functional description 7-0 crc15-8 the msb byte of the crc received from the transmitter . these bits are as the transmitter sent them; that is, most significant bit first and in verted. this register is updated at the end of each received packet and ther efore should be read when end of packet is detected. table 165 - receive crc msb register (pages b, c, and d, address 18h)
mt9076b data sheet 148 zarlink semiconductor inc. bit name functional description 7-0 crc7-0 the lsb byte of the crc received from the transmitter . these bits are as the transmitter sent them; that is, most significant bit first and inverted. this register is updated at the end of each received packet and therefore should be read when end of packet is detected. table 166 - receive crc lsb register (pages b, c, and d, address 19h) bit name functional description 7-0 txcnt7-0 low transmit byte count register. this register, along with the extended transmit byte count register indicates the length of the packet about to be transmitted. for a packet size of 255 or less it is only necessary to write this register. when this register reaches the count of one, the next write to the tx fifo will be tagged as an end of packet byte. the counter decrements at the end of the write to the tx fifo. if the cycle bit of c ontrol register 2 is se t high, the counter will cycle through the programmed value continuously. table 167 - low transmit byte count register (pages b, c, and d, address 1ah)
mt9076b data sheet 149 zarlink semiconductor inc. bit name functional description 7hrst hdlc reset. when this bit is set to one, the hdlc will be reset. this is similar to reset being applied , the only differ ence being that this bit w ill not be reset. this bit can only be reset by writing a zero twice to this location or applying reset. 6 rtloop rt loopback. when this bit is high, receive to transmit hdlc loopback will be activated. receive data, including end of pa cket indication, but no t including flags or crc, will be written to the tx fifo as well as the rx fifo. when the transmitter is enabled, this data will be transmitted as t hough written by the microprocessor. both good and bad packets will be looped back. receive to transmit loopback may also be accomplished by reading the rx fifo using the microprocessor and writing these bytes, with appropriate tags, into the tx fifo. 5- - reserved . must be set to 0 for normal operation. 4- - reserved . must be set to 0 for normal operation. 3 crctst crc remainder test. this bit allows direct ac cess to the crc comparison register in the receiver thro ugh the serial interface. afte r testing is enabled, serial data is clocked in until the data aligns wi th the internal comparison (16 rxc clock cycles) and then the clock is stopped. the expected pattern is f0b8 hex. each bit of the crc can be corrupted to allow more efficient testing. 2ftst fifo test. this bit allows the writing to the rx fifo and reading of the tx fifo through the microprocessor to allow more efficient testing of the fifo status/interrupt functionality. this is done by making a tx fifo write become a rx fifo write and a rx fifo read become a tx fifo read. in addition, eop/fa and rq8/rq9 are re-defined to be accessible (i .e., rx write causes eop/fa to go to rx fifo input; tx read looks at output of tx fifo through rq8/rq9 bits). 1artst address recognition test. this bit allows direct access to the address recognition registers in the receiver th rough the serial interface to allow more efficient testing. after address testing is enabled, serial data is clocked in until the data aligns with the internal address co mparison (16 rxc clock cycles) and then clock is stopped. 0 hloop tr loopback. when high, trans mit to receive hdlc loopb ack will be activated. the packetized transmit data will be looped back to the receive input. rxen and txen bits must also be enabled. table 168 - hdlc test control register (pages b, c, and d, address 1bh)
mt9076b data sheet 150 zarlink semiconductor inc. bit name functional description 7-4 - - these bits are reserved. 3rxclk receive clock. this bit represents the receiver clock generated after the rxen control bit, but before zero deletion is considered. 2txclk transmit clock. this bit represents the transmi t clock generated after the txen control bit, but before zero insertion is considered. 1 vcrc valid crc. this is the crc recognition status bit for the receiver. data is clocked into the register and then this bit is m onitored to see if co mparison was successful (bit will be high). 0 vaddr valid address. this is the address recognition status bit for the receiver. data is clocked into the address rec ognition register and then th is bit is monitored to see if comparison was successf ul (bit will be high). table 169 - hdlc test status register (pages b, c, and d, address 1ch)
mt9076b data sheet 151 zarlink semiconductor inc. bit name functional description 7 - -- unused. 6-4 rfd2-0 these bits select the rx fifo full status level: rfd2 rfd1 rfd0 full status level 000 16 001 32 010 48 011 64 100 80 101 96 110 112 111 128 3 - -- unused. 2-0 tfd2-0 these bits select the tx hdlc fifo full status level: tfd2 tfd1 tfd0 full status level 000 16 001 32 010 48 011 64 100 80 101 96 110 112 111 128 table 170 - hdlc control register 3 (pages b, c, and d, address 1dh)
mt9076b data sheet 152 zarlink semiconductor inc. bit name functional description 7 - -- unused. 6-4 rffs2-0 these bits select the rxff (rx fifo full) interrupt threshold level: rffs2 rffs1 rffs0 rx fifo full interrupt threshold level. 000 64 001 72 010 80 011 88 100 96 101 104 110 112 111 120 3 - -- unused. 2-0 tfls2-0 these bits select the txfl (tx fifo low) interrupt threshold level: tfls2 tfls1 tfls0 tx fifo low interrupt threshold level. 000 8 001 16 010 24 011 32 100 40 101 48 110 56 111 64 table 171 - hdlc control register 4 (pages b, c, and d, address 1eh)
mt9076b data sheet 153 zarlink semiconductor inc. 23.0 transmit nation al bit buffer (page 0eh) page 0eh, address 10h to 14h contain the five byte s of the transmit national bit buffer (tnbb0 - tnbb4 respectively). this feature is functional only when control bit nbtb (page 01h, address 17h) is one. 24.0 receive national bit buffer (page 0fh) page 0fh, addresses 10h to 14h contain the five bytes of the receive national bit buffer (rnbb0 - rnbb4 respectively). bit name functional description 7-0 txcnt15-8 extended transmit byte count register. this register, along with the transmit byte count register indicates t he length of the packet about to be transmitted. values programmed into this register are not inter nally updated until the next write to the low transmit byte count register. when the in ternal counter decrements to one, the next write to the tx fifo will be tagged as an end of packet byte. the counter decrements at the end of the write to the tx fifo. if the c ycle bit of control register 2 is set high, the counter will cycle th rough the programmed value continuously. table 172 - extended transmit byte count register (pages b,c, and d, address 1fh) bit name functional description 7 - 0 tnbbn.f1 - tnbbn.f15 transmit s a n+4 bits frames 1 to 15. this byte contai ns the bits transmitt ed in bit position n+4 of channel zero of frames 1, 3, 5, 7, 9, 11, 13 and 15 when crc-4 multiframe alignment is used, or of cons ecutive odd frames when crc-4 multiframe alignment is not used. n = 0 to 4 inclusive and corresponds to a byte of the receive national bit buffer. table 173 - transmit national bit buffer bytes zero to four (page 0eh) bit name functional description 7 - 0 rnbbn.f1 - rnbbn.f15 receive s a n+4 bits frames 1 to 15. this byte contai ns the bits received in bit position n+4 of channel zero of frames 1, 3, 5, 7, 9, 11, 13 and 15 when crc-4 multiframe alignment is used, or of consecutive odd fr ames when crc-4 multiframe alignment is not used. n = 0 to 4 inclusive and corresponds to a byte of the receive national bit buffer. table 174 - receive national bit buffer bytes zero to four (page 0fh)
mt9076b data sheet 154 zarlink semiconductor inc. 25.0 ac/dc electrical characteristics * exceeding these values may cause permanent damage. functional operation under these conditions is not implied. ? typical figures are at 25c and are for design aid only: not guaranteed and not subject to production testing. ? characteristics are for clocked operation over the ranges of recommended operating temperature and supply voltage. ? typical figures are at 25c and are for design aid only: not guaranteed and not subject to production testing. 30 a for inputs of boundary scan test port: osc1,tdi, tms, tclk and trst . absolute maximum ratings* - voltages are with respect to ground (v ss ) unless otherwise stated. parameter symbol min. max. units 1 supply voltage v dd -0.3 7 v 2 voltage at digital inputs v i -0.3 v dd + 0.3 v 3 current at digital inputs i i 30 ma 4 voltage at digital outputs v o -0.3 v dd + 0.3 v 5 current at digital outputs i o 30 ma 6 storage temperature t st -65 150 c recommended operating conditions - voltages are with respect to ground (v ss ) unless otherwise stated. characteristics sym. min. typ. ? max. units test conditions 1 operating temperature t op -40 85 c 2 supply voltage v dd 3.0 3.3 3.6 v dc electrical ch aracteristics ? - voltages are with respect to ground (v ss ) unless otherwise stated. characteristics sym. min. typ. ? max. units test conditions 1 supply current i dd 85 98 ma outputs unloaded. transmitting an all 1?s signal. 2 input high voltage (digital inputs) v ih 2.0 v dd v 3 input low voltage (digital inputs) v il 00.8v 4 input leakage (digital inputs) i il 112* av i = 0 to v dd 5 output high voltage (digital outputs) v oh 0.8v dd v dd vi oh = 7 ma, v oh = 2.4 v 6 output low voltage (digital outputs) v ol v ss 0.4 v i ol = 2 ma, v ol = 0.4 v 7 high impedance leakage (digital i/o) i oz 112 av o = 0 to v dd
mt9076b data sheet 155 zarlink semiconductor inc. ? characteristics are for clocked operation over the ranges of recommended operating temperature and supply voltage. ? typical figures are at 25c and are for design aid only: not guaranteed and not subject to production testing. figure 15 - motorola microport timing ac electrical ch aracteristics ? - motorola microprocessor timing characteristics sym. min. typ. ? max. units test conditions 1ds low t dsl 70 ns 2ds high t dsh 60 ns 3cs setup t css 0ns 4r/w setup t rws 1ns 5 address setup t ads 4ns 6cs hold t csh 0ns 7r/w hold t rwh 7ns 8 address hold t adh 4ns 9 data delay read t ddr 75 ns c l =50 pf 10 data hold read t dhr 75 ns c l =50 pf 11 data active to high z delay t daz 75 ns 12 data setup write t dsw 7ns 13 data hold write t dhw 9ns note: ds and cs may be connected together. ds cs r/w a0-a4 d0-d7 read d0-d7 write t css t rws t ads t csh t rwh t adh valid data t dsw t dhr t ddr t dhw valid data t dsh t dsl t daz t cyc v tt v tt v tt v tt v tt, v ct v tt
mt9076b data sheet 156 zarlink semiconductor inc. ? typical figures are at 25c and are for design aid only: not guaranteed and not subject to production testing. figure 16 - intel microport timing ac electrical ch aracteristics ? - intel microprocessor timing characteristics sym. min. typ. ? max. units test conditions 1 rd low t rdl 70 ns 2 rd high t rdh 60 ns 3cs setup t css 0ns 4cs hold t csh 0ns 5 address setup t ads 4ns 6 address hold t adh 4ns 7 data delay read t ddr 75 ns c l =50 pf 8 data active to high z delay t daz 75 ns 9 data setup write t dsw 7ns 10 data hold write t dhw 9ns rd cs wr a0-a4 d0-d7 read d0-d7 write t css t ads t csh t csh t adh valid data t ddr t rdl t daz t adh t cyc v tt v tt v tt v tt v tt t rdh t dsw t dhw valid data v tt
mt9076b data sheet 157 zarlink semiconductor inc. figure 17 - jtag port timing ac electrical characteristi cs - jtag port timing characteristic sym. min. typ. max. units test conditions 1 tck period width t tclk 100 ns bsdl spec?s 12 mhz 2 tck period width low t tclkl 40 ns 3 tck period width high t tclkh 40 ns tdi setup time to tck rising t disu 12 tdi hold time after tck rising t dih 12 tms setup time to tck rising t mssu 12 tms hold time after tck rising t msh 12 tdo delay from tck falling t dod 50 trst pulse width t trst 25 t mssu tdi tdo tms tck t disu t msh t dih t dod t tclkh t tclkl t tclk trst t trst
mt9076b data sheet 158 zarlink semiconductor inc. figure 18 - transmit data link timing diagram (t1 mode) figure 19 - transmit data link timing diagram (e1 mode) ac electrical charact eristics - transmit data link timing (t1 mode) characteristic sym. min. typ. max. units test conditions 1 data link clock pulse width t dw 324 ns 150 pf 2 data link setup t tds 35 ns 3 data link hold t tdh 35 ns ac electrical charact eristics - transmit data link timing (e1 mode) characteristic sym. min. typ. max. units test conditions 1 data link clock output delay t tdc 72 ns 150 pf 2 data link setup t tds 35 ns 3 data link hold t tdh 35 ns txdl t dlh t dls txdlclk t dw v tt, v ct v tt c4b txdl t tdc t dlh t dls txdlclk v tt v tt, v ct v tt
mt9076b data sheet 159 zarlink semiconductor inc. figure 20 - transmit data link functional timing (e1 mode) figure 21 - receive data link functional timing (t1 mode) ac electrical charact eristics - receive data link timing (t1 mode) characteristic sym. min. typ. max. units test conditions 1 data link clock output delay t rdc 160 ns 50 pf 2 data link output delay t rdd 45 ns 50 pf 3rxfp output delay t rfd 45 ns 50 pf f0b txdlclk time slot 0 bits 4,3,2,1,0 txdl txdlclk txdl example a - 20 kb/s example b - 12 kb/s rxfp rxdlclk rxdl
mt9076b data sheet 160 zarlink semiconductor inc. figure 22 - receive data link diagram (t1 mode) figure 23 - receive data link functional timing (e1 mode) ac electrical charact eristics - receive data link timing (e1 mode) characteristic sym. min. typ. max. units test conditions 1 data link clock output delay t rdc 160 ns 50 pf 2 data link output delay t rdd 45 ns 50 pf 3rxfp output delay t rfd 45 ns 50 pf e1.5o rxdl t rdc t rdd rxdlclk v tt, v ct v tt, v ct v tt t rdc t rfd t rfd rxfp v tt, v ct rxfp rxdlclk time slot 0 bits 4,3,2,1,0 rxdl rxdlclk rxdl example a - 20 kb/s example b - 12 kb/s
mt9076b data sheet 161 zarlink semiconductor inc. figure 24 - receive data link timing diagram (e1 mode) figure 25 - st-bus functional timing diagram - 2.048 mb/s mode ac electrical char acteristics - st-bus timing (e1 or t1 mode) characteristic sym. min. typ. max. units test conditions 1c4b clock width high or low t 4w 80 122 150 ns 2.048 mb/s mode 2c4b clock width high or low t fps 25 30.5 35 ns 8.192 mb/s mode 3 frame pulse hold t fph 10 ns 4 frame pulse setup t fps 10 ns 2.048 mb/s mode 5 frame pulse low t fpl 75 ns 6 serial input setup t sis 10 ns 7 serial input hold t sih 10 ns 8 serial output delay t sod 75 ns 150 pf 9 frame pulse delay t fdd 75 ns e2o rxdl t rdc t rdd rxdlclk t rdc v tt v tt, v ct v tt, v ct f0b c4b st-bus bit cells channel 31 bit 0 channel 0 bit 7 channel 0 bit 6 channel 0 bit 5
mt9076b data sheet 162 zarlink semiconductor inc. figure 26 - st-bus functional timing diagram - 8.192 mb/s mode figure 27 - st-bus timing diagram (input clocks) f0b c4b st-bus bit cells channel 127 bit 0 channel 0 bit 7 channel 0 bit 6 channel 0 bit 5 f0b st-bus bit stream all input streams all output streams c4b (input) bit cell bit cell bit cell t sih t fph t fps t sis t sod t 4wi t 4wi v tt v tt v tt v tt, v ct (input) t fpl
mt9076b data sheet 163 zarlink semiconductor inc. figure 28 - st-bus timing diagram (output clocks) figure 29 - receive multiframe functional timing (t1 mode) ac electrical charact eristics - multiframe timing (t1 or e1 mode) characteristic sym. min. typ. max. units test conditions 1 receive multiframe output delay t mod 50 ns 150 pf 2 transmit multiframe setup t ms 50 ns 3 transmit multiframe hold t mh 50 * ns * 256 c2 periods -100 nsec f0b st-bus bit stream all input bit cell bit cell bit cell t sih t sis streams t sod all output streams t 4wo c4b (output) (output) t 4wo t fpd t fpd v tt v tt v tt v tt, v ct dsto bit cells f0b bit 7 bit 6 bit 5 bit 4 bit 0 bit 7 bit 6 bit 5 bit 4 bit 0 bit 7 frame 0 frame 12 or 24 rxmf c4b (4.096 mhz)
mt9076b data sheet 164 zarlink semiconductor inc. figure 30 - receive multiframe functional timing (e1 mode) figure 31 - transmit multiframe functional timing (t1 mode or e1 mode) figure 32 - multiframe timing diagram (t1 mode or e1 mode) dsto bit cells f0b bit 7 bit 6 bit 5 bit 4 bit 0 bit 7 bit 6 bit 5 bit 4 bit 0 bit 7 frame 0 frame 15 rxmf c4b (4.096 mhz) (tx8ken = 0) f0b txmf dsti bit cells bit 7 bit 6 bit 5 bit 4 bit 0 bit 7 bit 6 bit 5 bit 4 bit 0 bit 7 frame 0 frame n c4b (4.096 mhz) note (1) : these two signals do not have a defined phase relationship note (2): control bit tx8ken set low. c4b rxmf (1,2) txmf (1) t mod t mod t mh t ms t mh2 f0b v tt v tt, v ct v tt v tt
mt9076b data sheet 165 zarlink semiconductor inc. figure 33 - txa/txb functional timing (t1 mode) figure 34 - txa/txb functional timing (e1 mode) figure 35 - txa/txb timing diagram (t1 mode or e1 mode) ac electrical charact eristics - txa/txb (e1 or t1 mode) characteristic sym. min. typ. max. units test conditions 1 serial output delay t sod 20 ns 150 pf 2 txfp output delay t tfod 20 ns 150 pf rxmf/txfp txa/txb channel 23 bit 0 sbit channel 0 bit 7 channel 0 bit 6 e1.5o/exclk (liuen = 1) (tx8ken= 1) rxmf/txfp txa/txb channel 31 bit 0 channel 0 bit 7 channel 0 bit 6 e1.5o/exclk (liuen = 1) (tx8ken= 1) channel 0 bit 5 txa/txb t sod (output) t tfod t tfod v tt v tt v tt t sod txfp (output) e1.5o (output)
mt9076b data sheet 166 zarlink semiconductor inc. figure 36 - tx ima functional timing (t1 mode) figure 37 - rx ima functional timing (t1 mode) ac electrical character istics - ima timing (e1 or t1 mode) characteristic sym. min. typ. max. units test conditions 1c4b clock width high or low t 4w 80 122 150 ns e1 mode 2 frame pulse setup t fps 10 ns 3frame pulse hold t fps 10 ns 4 serial input setup t sis 4ns 5 serial input hold t sih 4ns 6 serial output delay t sod 45 ns 150 pf f0b c4b dsti channel 23 bit 0 sbit channel 0 bit 7 channel 0 bit 6 1.544 mhz rxfp dsto channel 23 bit 0 sbit channel 23 bit 1 exclk 1.544 mhz
mt9076b data sheet 167 zarlink semiconductor inc. figure 38 - tx ima functional timing (e1 mode) figure 39 - rx ima functional timing (e1 mode) figure 40 - tx ima timing diagram (t1 mode or e1 mode) f0b c4b dsti channel 31 bit 0 channel 0 bit 7 channel 0 bit 6 2.048 mhz channel 0 bit 5 rxfp dsto channel 0 bit 7 channel 31 bit 0 exclk 2.048 mhz channel 0 bit 6 f0b st-bus bit stream dsti bit cell bit cell t sih c4b (input) (input) t fps t fp h v tt v tt v tt t sis
mt9076b data sheet 168 zarlink semiconductor inc. figure 41 - rx ima timing diagram (t1 mode or e1 mode) figure 42 - d4 format figure 43 - pcm 30 format rxfp st-bus bit stream dsto bit cell bit cell t sod exclk (output) (output) v tt v tt v tt t sis frame 12 1 11 12 1 channel 12 2324 most significant bit (first) least significant bit (last) bit 12345678 frame frame frame frame channel channel channel bit bit bit bit bit bit bit 1.5 ms 5.2 s 125 s ???????? ???? sbit sbit frame 15 0 14 15 0 time slot 0 1 30 31 most significant bit (first) least significant bit (last) bit 1 23 45 6 78 frame frame frame frame time slot time slot time slot bit bit bit bit bit bit bit 2.0 ms (8/2.048) s 125 s ???????? ????
mt9076b data sheet 169 zarlink semiconductor inc. figure 44 - st-bus stream format - 2.048 mb/s figure 45 - st-bus stream format 8.192 mb/s channel 31 0 30 bit channel channel channel channel 31 0 bit bit bit bit bit bit bit ? ? ? least significant bit (last) most significant bit (first) 3.906 s 125 s 7654321 0 channel 127 0 126 bit channel channel channel channel 127 0 bit bit bit bit bit bit bit ? ? ? least significant bit (last) most significant bit (first) 0.977 s 125 s 7654321 0

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