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mos integrated circuit m m m m pd16732 384-output tft-lcd source driver (compatible with 64-gray scales) 1998 ? document no. s12933ej2v0ds00 (2nd edition) date published february 1999 ns cp(k) printed in japan data sheet the mark h shows major revised points. the m pd16732 is a source driver for tft-lcds capable of dealing with displays with 64-gray scales. data input is based on digital input configured as 6 bits by 6 dots (2 pixels), which can realize a full-color display of 260,000 colors by output of 64 values g -corrected by an internal d/a converter and 5-by-2 external power modules. because the output dynamic range is as large as v ss2 +0.1 v to v dd2 -0.1 v, level inversion operation of the lcds common electrode is rendered unnecessary. also, to be able to deal with dot-line inversion, n-line inversion and column line inversion when mounted on a single side, this source driver is equipped with a built-in 6-bit d/a converter circuit whose odd output pins and even output pins respectively output gray scale voltages of differing polarity. assuring a maximum clock frequency of 40 mhz when driving at 3.0 v, this driver is applicable to xga-standard tft-lcd panels and sxga tft-lcd panels by input display signal 2 systems (clock divide). features ? 384 outputs ? capable of outputting 64 values by means of 5-by-2 external power modules (10 units) and a d/a converter ? output dynamic range : v ss2 +0.1 v to v dd2 -0.1 v ? logic part power supply voltage (v dd1 ) : 3.3 0.3 v ? driver part power supply voltage (v dd2 ): 8.5 0.5 v ? cmos level input ? input of 6 bits (gradation data) by 6 dots ? high-speed data transfer: f max. = 40 mhz (internal data transfer speed when operating at 3.0 v) ? apply for dot-line inversion, n-line inversion and column line inversion ? single bank arrangement is possible (loaded with slim or bending tcp) (pol) ? display data inversion function (pol2) ordering information part number package m pd16732n- tcp (tab package) remark the tcps external shape is customized. to order your tcps external shape, please contact a nec salesperson. h h h h the information in this document is subject to change without notice. before using this document, please confirm that this is the latest version. not all devices/types available in every country. please check with local nec representative for availability and additional information.
data sheet s12933ej2v0ds00 2 m m m m pd16732 block diagram remark /xxx indicates active low signal. relationship between output circuit and d/a converter s 1 s 2 s 383 6-bit d/a converter s 384 v 4 5 5 pol multi- plexer v 9 v 0 v 5 sthl v dd1 v ss1 v dd2 v ss2 s 2 s 1 v 0 - v 9 pol d 00 - d 05 c 1 c 2 c 63 c 64 stb clk 64-bit bidirectional shift register data register latch level shifter d/a converter voltage follower output r,/l sthr d 10 - d 15 d 20 - d 25 s 3 s 384 pol2 d 30 - d 35 d 40 - d 45 d 50 - d 55
data sheet s12933ej2v0ds00 3 m m m m pd16732 pin configuration ( m m m m pd16732n- ) s 384 s 383 s 382 s 381 v dd1 r,/l d 55 d 54 s 4 s 3 s 2 s 1 d 53 d 52 d 51 d 50 v 9 v 8 v 7 v 6 v 5 v 4 v 3 v 2 v 1 v 0 sthr d 35 d 34 d 33 d 32 d 31 d 30 d 00 d 01 d 02 d 03 d 04 d 05 v ss1 v dd2 v ss2 stb sthl clk (cupper plated surface) pol2 d 10 d 11 d 12 d 13 d 14 d 15 d 20 d 21 d 22 d 23 d 24 d 25 pol d 45 d 44 d 43 d 42 d 41 d 40 remark this figure does not specify the tcp package.
data sheet s12933ej2v0ds00 4 m m m m pd16732 1. pin functions pin symbol pin name description s 1 to s 384 driver output the d/a converted 64-gray-scale analog voltage is output. d 00 to d 05 d 10 to d 15 d 20 to d 25 d 30 to d 35 d 40 to d 45 d 50 to d 55 display data input the display data is input with a width of 36 bits, viz., the gray scale data (6 bits) by 6 dots (2 pixels). d x0 : lsb, d x5 : msb r,/l shift direction control input these refer to the start pulse input/output pins when driver ics are connected in cascade. the shift directions of the shift registers are as follows. r,/l = h : sthr input, s 1 ? s 384 , sthl output r,/l = l : sthl input, s 384 ? s 1 , sthr output sthr right shift start pulse input/output r,/l = h : becomes the start pulse input pin. r,/l = l : becomes the start pulse output pin. sthl left shift start pulse input/output r,/l = h : becomes the start pulse output pin. r,/l = l : becomes the start pulse input pin. clk shift clock input refers to the shift registers shift clock input. the display data is incorporated into the data register at the rising edge. at the rising edge of the 64th clock after the start pulse input, the start pulse output reaches the high level, thus becoming the start pulse of the next-level driver. stb latch input the contents of the data register are transferred to the latch circuit at the rising edge. and, at the falling edge, the gray scale voltage is supplied to the driver. it is necessary to ensure input of one pulse per horizontal period. pol polarity input pol = l : the s 2nC1 output uses v 0 to v 4 as the reference supply. the s 2n output uses v 5 to v 9 as the reference supply. pol = h: the s 2nC1 output uses v 5 to v 9 as the reference supply. the s 2n output uses v 0 to v 4 as the reference supply. s 2n-1 indicates the odd output: and s 2n indicates the even output. input of the pol signal is allowed the setup time(t pol - stb ) with respect to stbs rising edge. pol2 data inversion pol2 = h : display data is inverted. pol2 = l : display data is not inverted. v 0 to v 9 g -corrected power supplies input the g -corrected power supplies from outside by using operational amplifier. make sure to maintain the following relationships. during the gray scale voltage output, be sure to keep the gray scale level power supply at a constant level. v dd2 > v 0 > v 1 > v 2 > v 3 > v 4 > v 5 > v 6 > v 7 > v 8 > v 9 > v ss2 v dd1 logic power supply 3.3 v 0.3 v v dd2 driver power supply 8.5 v 0.5 v v ss1 logic ground grounding v ss2 driver ground grounding cautions 1. the power start sequence must be v dd1 , logic input, and v dd2 & v 0 to v 9 in that order. reverse this sequence to shut down. (simultaneous power application to v dd2 and v 0 to v 9 is possible.) 2. to stabilize the supply voltage, please be sure to insert a 0.1 m m m m f bypass capacitor between v dd1 - v ss1 and v dd2 -v ss2 . furthermore, for increased precision of the d/a converter, insertion of a bypass capacitor of about 0.01 m m m m f is also advised between the g g g g -corrected power supply terminals (v 0 , v 1 , v 2 , , v 9 ) and v ss2 . h
data sheet s12933ej2v0ds00 5 m m m m pd16732 2. relationship between input data and output voltage value this product incorporates a 6-bit d/a converter whose odd output pins and even output pins output respectively gray scale voltages of differing polarity with respect to the lcds counter electrode (common electrode) voltage. the d/a converter consists of ladder resistors and switches. figure 2 - 1 shows the relationship between the driving voltages such as liquid-crystal driving voltages v dd2 and v ss2 , common electrode potential v com , and g -corrected voltages v 0 to v 9 and the input data. be sure to maintain the voltage relationships of v dd2 > v 0 > v 1 > v 2 > v 3 > v 4 > v 5 > v 6 > v 7 > v 8 > v 9 > v ss2 . figures 2 - 2 and 2 - 3 show the relationship between the input data and the output data. this driver ic is designed for only single-sided mounting. therefore, please do not use it for g -corrected power supply level inversion in double-sided mounting. figure 2 - - - - 1. relationship between input data and g g g g -corrected power supply v dd2 v ss2 v 1 v 2 v 3 v 4 v com v 5 v 6 v 7 v 8 00 08 10 18 20 28 30 input data (hex) 38 3f 0.1 v v 9 0.1 v v 0 16 16 16 16 16 16 15 15 split interval
data sheet s12933ej2v0ds00 6 m m m m pd16732 figure 2 - - - - 2. relationship between input data and output voltage(1/2) v dd2 > v 0 > v 1 > v 2 > v 3 > v 4 > v 5 , pol2 = l data d x5 d x4 d x3 d x2 d x1 d x0 output voltage rn ( w ) 00 h 000000v 0 'v 0 r 0 800 01 h 000001v 1 'v 1 + ( v 0 -v 1 ) 7250/8050 r 1 750 02 h 000010v 2 'v 1 + ( v 0 -v 1 ) 6500/8050 r 2 700 03 h 000011v 3 'v 1 + ( v 0 -v 1 ) 5800/8050 r 3 650 04 h 000100v 4 'v 1 + ( v 0 -v 1 ) 5150/8050 r 4 600 05 h 000101v 5 'v 1 + ( v 0 -v 1 ) 4550/8050 r 5 550 06 h 000110v 6 'v 1 + ( v 0 -v 1 ) 4000/8050 r 6 550 07 h 000111v 7 'v 1 + ( v 0 -v 1 ) 3450/8050 r 7 500 08 h 001000v 8 'v 1 + ( v 0 -v 1 ) 2950/8050 r 8 500 09 h 001001v 9 'v 1 + ( v 0 -v 1 ) 2450/8050 r 9 400 0a h 001010v 10 'v 1 + ( v 0 -v 1 ) 2050/8050 r 10 400 0b h 001011v 11 'v 1 + ( v 0 -v 1 ) 1650/8050 r 11 350 0c h 001100v 12 'v 1 + ( v 0 -v 1 ) 1300/8050 r 12 350 0d h 001101v 13 'v 1 + ( v 0 -v 1 ) 950/8050 r 13 350 0e h 001110v 14 'v 1 + ( v 0 -v 1 ) 600/8050 r 14 300 0f h 001111v 15 'v 1 + ( v 0 -v 1 ) 300/8050 r 15 300 10 h 010000v 16 'v 1 r 16 300 11 h 010001v 17 'v 2 + ( v 1 -v 2 ) 2450/2750 r 17 250 12 h 010010v 18 'v 2 + ( v 1 -v 2 ) 2200/2750 r 18 250 13 h 010011v 19 'v 2 + ( v 1 -v 2 ) 1950/2750 r 19 250 14 h 010100v 20 'v 2 + ( v 1 -v 2 ) 1700/2750 r 20 200 15 h 010101v 21 'v 2 + ( v 1 -v 2 ) 1500/2750 r 21 200 16 h 010110v 22 'v 2 + ( v 1 -v 2 ) 1300/2750 r 22 200 17 h 010111v 23 'v 2 + ( v 1 -v 2 ) 1100/2750 r 23 150 18 h 011000v 24 'v 2 + ( v 1 -v 2 ) 950/2750 r 24 150 19 h 011001v 25 'v 2 + ( v 1 -v 2 ) 800/2750 r 25 150 1a h 011010v 26 'v 2 + ( v 1 -v 2 ) 650/2750 r 26 150 1b h 011011v 27 'v 2 + ( v 1 -v 2 ) 500/2750 r 27 100 1c h 011100v 28 'v 2 + ( v 1 -v 2 ) 400/2750 r 28 100 1d h 011101v 29 'v 2 + ( v 1 -v 2 ) 300/2750 r 29 100 1e h 011110v 30 'v 2 + ( v 1 -v 2 ) 200/2750 r 30 100 1f h 011111v 31 'v 2 + ( v 1 -v 2 ) 100/2750 r 31 100 20 h 100000v 32 'v 2 r 32 100 21 h 100001v 33 'v 3 + ( v 2 -v 3 ) 1500/1600 r 33 100 22 h 100010v 34 'v 3 + ( v 2 -v 3 ) 1400/1600 r 34 100 23 h 100011v 35 'v 3 + ( v 2 -v 3 ) 1300/1600 r 35 100 24 h 100100v 36 'v 3 + ( v 2 -v 3 ) 1200/1600 r 36 100 25 h 100101v 37 'v 3 + ( v 2 -v 3 ) 1100/1600 r 37 100 26 h 100110v 38 'v 3 + ( v 2 -v 3 ) 1000/1600 r 38 100 27 h 100111v 39 'v 3 + ( v 2 -v 3 ) 900/1600 r 39 100 28 h 101000v 40 'v 3 + ( v 2 -v 3 ) 800/1600 r 40 100 29 h 101001v 41 'v 3 + ( v 2 -v 3 ) 700/1600 r 41 100 2a h 101010v 42 'v 3 + ( v 2 -v 3 ) 600/1600 r 42 100 2b h 101011v 43 'v 3 + ( v 2 -v 3 ) 500/1600 r 43 100 2c h 101100v 44 'v 3 + ( v 2 -v 3 ) 400/1600 r 44 100 2d h 101101v 45 'v 3 + ( v 2 -v 3 ) 300/1600 r 45 100 2e h 101110v 46 'v 3 + ( v 2 -v 3 ) 200/1600 r 46 100 2f h 101111v 47 'v 3 + ( v 2 -v 3 ) 100/1600 r 47 100 30 h 110000v 48 'v 3 r 48 100 31 h 110001v 49 'v 4 + ( v 3 -v 4 ) 3350/3450 r 49 100 32 h 110010v 50 'v 4 + ( v 3 -v 4 ) 3250/3450 r 50 100 33 h 110011v 51 'v 4 + ( v 3 -v 4 ) 3150/3450 r 51 100 34 h 110100v 52 'v 4 + ( v 3 -v 4 ) 3050/3450 r 52 100 35 h 110101v 53 'v 4 + ( v 3 -v 4 ) 2950/3450 r 53 150 36 h 110110v 54 'v 4 + ( v 3 -v 4 ) 2800/3450 r 54 150 37 h 110111v 55 'v 4 + ( v 3 -v 4 ) 2650/3450 r 55 150 38 h 111000v 56 'v 4 + ( v 3 -v 4 ) 2500/3450 r 56 200 39 h 111001v 57 'v 4 + ( v 3 -v 4 ) 2300/3450 r 57 200 3a h 111010v 58 'v 4 + ( v 3 -v 4 ) 2100/3450 r 58 250 3b h 111011v 59 'v 4 + ( v 3 -v 4 ) 1850/3450 r 59 250 3c h 111100v 60 'v 4 + ( v 3 -v 4 ) 1600/3450 r 60 300 3d h 111101v 61 'v 4 + ( v 3 -v 4 ) 1300/3450 r 61 500 3e h 111110v 62 'v 4 + ( v 3 -v 4 ) 800/3450 r 62 800 3f h 111111v 63 'v 4 r total 15850 caution between v 4 and v 5 terminal is not connected in the chip. v 0 ' v 17 ' v 1 ' v 47 ' v 2 ' v 48 ' v 3 ' v 49 ' v 15 ' v 16 ' v 63 ' v 61 ' v 62 ' r 0 r 17 r 1 r 47 r 46 r 2 r 48 r 3 r 49 r 14 r 15 r 16 r 60 r 61 r 62 v 4 v 3 v 1 v 0
data sheet s12933ej2v0ds00 7 m m m m pd16732 figure 2 - - - - 3. relationship between input data and output voltage(2/2) v 4 > v 5 > v 6 > v 7 > v 8 > v 9 > v ss2 , pol2 = l data d x5 d x4 d x3 d x2 d x1 d x0 output voltage rn ( w ) 3f h 111111v 63 '' v 5 r 62 800 3e h 111110v 62 '' v 6 + ( v 5 -v 6 ) 2650/3450 r 61 500 3d h 111101v 61 '' v 6 + ( v 5 -v 6 ) 2150/3450 r 60 300 3c h 111100v 60 '' v 6 + ( v 5 -v 6 ) 1850/3450 r 59 250 3b h 111011v 59 '' v 6 + ( v 5 -v 6 ) 1600/3450 r 58 250 3a h 111010v 58 '' v 6 + ( v 5 -v 6 ) 1350/3450 r 57 200 39 h 111001v 57 '' v 6 + ( v 5 -v 6 ) 1150/3450 r 56 200 38 h 111000v 56 '' v 6 +(v 5 -v 6 ) 950/3450 r 55 150 37 h 110111v 55 '' v 6 +(v 5 -v 6 ) 800/3450 r 54 150 36 h 110110v 54 '' v 6 +(v 5 -v 6 ) 650/3450 r 53 150 35 h 110101v 53 '' v 6 +(v 5 -v 6 ) 500/3450 r 52 100 34 h 110100v 52 '' v 6 +(v 5 -v 6 ) 400/3450 r 51 100 33 h 110011v 51 '' v 6 +(v 5 -v 6 ) 300/3450 r 50 100 32 h 110010v 50 '' v 6 +(v 5 -v 6 ) 200/3450 r 49 100 31 h 110001v 49 '' v 6 +(v 5 -v 6 ) 100/3450 r 48 100 30 h 110000v 48 '' v 6 r 47 100 2f h 101111v 47 '' v 7 + ( v 6 -v 7 ) 1500/1600 r 46 100 2e h 101110v 46 '' v 7 + ( v 6 -v 7 ) 1400/1600 r 45 100 2d h 101101v 45 '' v 7 + ( v 6 -v 7 ) 1300/1600 r 44 100 2c h 101100v 44 '' v 7 + ( v 6 -v 7 ) 1200/1600 r 43 100 2b h 101011v 43 '' v 7 + ( v 6 -v 7 ) 1100/1600 r 42 100 2a h 101010v 42 '' v 7 + ( v 6 -v 7 ) 1000/1600 r 41 100 29 h 101001v 41 '' v 7 +(v 6 -v 7 ) 900/1600 r 40 100 28 h 101000v 40 '' v 7 +(v 6 -v 7 ) 800/1600 r 39 100 27 h 100111v 39 '' v 7 +(v 6 -v 7 ) 700/1600 r 38 100 26 h 100110v 38 '' v 7 +(v 6 -v 7 ) 600/1600 r 37 100 25 h 100101v 37 '' v 7 +(v 6 -v 7 ) 500/1600 r 36 100 24 h 100100v 36 '' v 7 +(v 6 -v 7 ) 400/1600 r 35 100 23 h 100011v 35 '' v 7 +(v 6 -v 7 ) 300/1600 r 34 100 22 h 100010v 34 '' v 7 +(v 6 -v 7 ) 200/1600 r 33 100 21 h 100001v 33 '' v 7 +(v 6 -v 7 ) 100/1600 r 32 100 20 h 100000v 32 '' v 7 r 31 100 1f h 011111v 31 '' v 8 + ( v 7 -v 8 ) 2650/2750 r 30 100 1e h 011110v 30 '' v 8 + ( v 7 -v 8 ) 2550/2750 r 29 100 1d h 011101v 29 '' v 8 + ( v 7 -v 8 ) 2450/2750 r 28 100 1c h 011100v 28 '' v 8 + ( v 7 -v 8 ) 2350/2750 r 27 100 1b h 011011v 27 '' v 8 + ( v 7 -v 8 ) 2250/2750 r 26 150 1a h 011010v 26 '' v 8 + ( v 7 -v 8 ) 2100/2750 r 25 150 19 h 011001v 25 '' v 8 + ( v 7 -v 8 ) 1950/2750 r 24 150 18 h 011000v 24 '' v 8 + ( v 7 -v 8 ) 1800/2750 r 23 150 17 h 010111v 23 '' v 8 + ( v 7 -v 8 ) 1650/2750 r 22 200 16 h 010110v 22 '' v 8 + ( v 7 -v 8 ) 1450/2750 r 21 200 15 h 010101v 21 '' v 8 + ( v 7 -v 8 ) 1250/2750 r 20 200 14 h 010100v 20 '' v 8 + ( v 7 -v 8 ) 1050/2750 r 19 250 13 h 010011v 19 '' v 8 +(v 7 -v 8 ) 800/2750 r 18 250 12 h 010010v 18 '' v 8 +(v 7 -v 8 ) 550/2750 r 17 250 11 h 010001v 17 '' v 8 +(v 7 -v 8 ) 300/2750 r 16 300 10 h 010000v 16 '' v 8 r 15 300 0f h 001111v 15 '' v 9 + ( v 8 -v 8 ) 7750/8050 r 14 300 0e h 001110v 14 '' v 9 + ( v 8 -v 8 ) 7450/8050 r 13 350 0d h 001101v 13 '' v 9 + ( v 8 -v 8 ) 7100/8050 r 12 350 0c h 001100v 12 '' v 9 + ( v 8 -v 8 ) 6750/8050 r 11 350 0b h 001011v 11 '' v 9 + ( v 8 -v 8 ) 6400/8050 r 10 400 0a h 001010v 10 '' v 9 + ( v 8 -v 8 ) 6000/8050 r 9 400 09 h 001001v 9 '' v 9 + ( v 8 -v 8 ) 5600/8050 r 8 500 08 h 001000v 8 '' v 9 + ( v 8 -v 8 ) 5100/8050 r 7 500 07 h 000111v 7 '' v 9 + ( v 8 -v 8 ) 4600/8050 r 6 550 06 h 000110v 6 '' v 9 + ( v 8 -v 8 ) 4050/8050 r 5 550 05 h 000101v 5 '' v 9 + ( v 8 -v 8 ) 3500/8050 r 4 600 04 h 000100v 4 '' v 9 + ( v 8 -v 8 ) 2900/8050 r 3 650 03 h 000011v 3 '' v 9 + ( v 8 -v 8 ) 2250/8050 r 2 700 02 h 000010v 2 '' v 9 + ( v 8 -v 8 ) 1550/8050 r 1 750 01 h 000001v 1 '' v 9 +(v 8 -v 8 ) 800/8050 r 0 800 00 h 000000v 0 '' v 9 r total 15850 caution between v 4 and v 5 terminal is not connected in the chip. v 17 '' v 0 '' v 16 '' v 15 '' v 2 '' v 1 '' v 63 '' v 62 '' v 61 '' v 49 '' v 48 '' v 47 '' r 61 r 60 r 59 r 49 r 48 r 47 r 46 v 6 r 62 v 5 r 17 r 0 r 16 r 15 r 14 r 2 r 1 v 9 v 8 v 60 ''
data sheet s12933ej2v0ds00 8 m m m m pd16732 3. relationship between input data and output pin data format: 6 bits 2 rgbs (6 dots) input width : 36 bits (2-pixel data) r,/l = h (right shift) output s 1 s 2 s 3 s 4 xxx s 383 s 384 data d 00 to d 05 d 10 to d 15 d 20 to d 25 d 30 to d 35 xxx d 40 to d 45 d 50 to d 55 r,/l = l (left shift) output s 1 s 2 s 3 s 4 xxx s 383 s 384 data d 00 to d 05 d 10 to d 15 d 20 to d 25 d 30 to d 35 xxx d 40 to d 45 d 50 to d 55 pol s 2nC1 note s 2n note lv 0 to v 4 v 5 to v 9 hv 5 to v 9 v 0 to v 4 note s 2n-1 (odd output), s 2n (even output) 4. relationship between stb, pol, and output waveform the output voltage is written to the lcd panel synchronized with the stb falling edge. selected voltage of v 0 to v 4 hi-z stb pol s 2n s 2n-1 hi-z hi-z selected voltage of v 0 to v 4 selected voltage of v 0 to v 4 selected voltage of v 5 to v 9 selected voltage of v 5 to v 9 selected voltage of v 5 to v 9
data sheet s12933ej2v0ds00 9 m m m m pd16732 5. electrical specification absolute maximum ratings (t a = +25 c, v ss1 = v ss2 = 0 v) parameter symbol rating unit logic part supply voltage v dd1 C0.5 to +5.0 v driver part supply voltage v dd2 C0.5 to +10.0 v logic part input voltage v i1 C0.5 to v dd1 +0.5 v driver part input voltage v i2 C0.5 to v dd2 +0.5 v logic part output voltage v o1 C0.5 to v dd1 +0.5 v driver part output voltage v o2 C0.5 to v dd2 +0.5 v operating temperature range t a C10 to +75 c storage temperature range t stg C55 to +125 c caution if the absolute maximum rating of even one of the above parameters is exceeded even momentarily, the quality of the product may be degraded. absolute maximum ratings, therefore, specify the values exceeding which the product may be physically damaged. be sure to use the product within the range of the absolute maximum ratings. recommended operating range (t a = C10 to +75 c, v ss1 = v ss2 = 0 v) parameter symbol min. typ. max. unit logic part supply voltage v dd1 3.0 3.3 3.6 v driver part supply voltage v dd2 8.0 8.5 9.0 v high-level input voltage v ih 0.7 v dd1 v dd1 v low-level input voltage v il 0 0.3 v dd1 v g -corrected voltage v 0 to v 9 v ss2 v dd2 v driver part output voltage v o v ss2 + 0.1 v dd2 C 0.1 v maximum clock frequency f max. 40 mhz
data sheet s12933ej2v0ds00 10 m m m m pd16732 electrical specifications (t a = C10 to +75 c, v dd1 = 3.3 v 0.3 v, v dd2 = 8.5 v 0.5 v, v ss1 = v ss2 = 0 v) parameter symbol condition min. typ. max. unit input leak current i il 1.0 m a high-level output voltage v oh sthr (sthl), i oh = 0 ma v dd1 C 0.1 v low-level output voltage v ol sthr (sthl), i ol = 0 ma 0.1 v g -corrected supply current i g v 0 pin, v 4 pin 126 252 504 m a v 0 to v 4 = v 5 to v 9 = 4.0 v v 5 pin, v 9 pin C504 C252 C126 m a i voh v x = 7.0 v, v out = 6.5 v note C30 m a driver output current i vol v x = 1.0 v, v out = 1.5 v note 30 m a output voltage deviation d v o 7 20 mv output swing difference deviation d v pCp v dd1 = 3.3 v, v dd2 = 8.5 v, v out = 2.0 v, 4.25 v, 6.5 v 2 15 mv output voltage range v o input data 0.1 v dd2 C 0.1 v logic part dynamic current consumption i dd1 v dd1, with no load 2.0 10 ma driver part dynamic current consumption i dd2 v dd2, with no load 3.0 10 ma note v x refers to the output voltage of analog output pins s 1 to s 384 . v out refers to the voltage applied to analog output pins s 1 to s 384 . cautions 1. the stb cycle is defined to be 20 m m m m s at f clk = 40 mhz. 2. the typ. values refer to an all black or all white input pattern. the max. value refers to the measured values in the dot checkerboard input pattern. 3. refers to the current consumption per driver when cascades are connected under the assumption of xga single-sided mounting (8 units). switching characteristics (t a = C10 to +75 c, v dd1 = 3.3 v 0.3 v, v dd2 = 8.5 v 0.5 v, v ss1 = v ss2 = 0 v) parameter symbol condition min. typ. max. unit start pulse delay time t plh1 c l = 10 pf 10 20 ns t plh2 2.5 4 m s t plh3 57 m s t phl2 2.5 4 m s driver output delay time t phl3 c l = 75 pf, r l = 5 k w, v dd1 = 3.3 v, v dd2 = 9.0 v 57 m s c i1 sthr (sthl) excluded, t a = 25c 510pf input capacitance c i2 sthr (sthl),t a = 25c 5 10 pf
data sheet s12933ej2v0ds00 11 m m m m pd16732 measurement condition timing requirement (t a = C10 to +75 c, v dd1 = 3.3 v 0.3 v, v ss1 = v ss2 = 0 v) parameter symbol condition min. typ. max. unit clock pulse width pw clk 25 ns clock pulse high period pw clk(h) 4ns clock pulse low period pw clk(l) 4ns data setup time t setup1 4ns data hold time t hold1 0ns start pulse setup time t setup2 4ns start pulse hold time t hold2 0ns pol2 setup time t setup3 4ns pol2 hold time t hold3 0ns start pulse low period t spl 6ns 2clk stb pulse width pw stb 4 m s data invalid period t inv 1clk last data timing t ldt 2clk clk-stb time t clk-stb clk - ? stb - 6ns stb-clk time t stb-clk stb - ? clk - 6ns time between stb and start pulse t stb-sth stb - ? sthr(sthl) - 2clk pol-stb time t pol-stb pol - or ? stb - C5 ns stb-pol time t stb-pol stb ? pol or - 6ns output r l r l r l r l r l =1k c l c l c l c l c l c l =15pf r l h h
data sheet s12933ej2v0ds00 12 m m m m pd16732 6. switching characteristics waveform (r,/l = h) ( unless otherwise specified, the input level is defined to be v ih = 0.7 v dd1 , v il = 0.3 v dd1 , ) h pw clk (l) clk pol v out stb d n0- d n5 sthr sthl pw clk (h) t r t setup2 invalid d 1 -d 6 t hold2 12 12 3646566 513 514 t f v dd1 v ss1 v dd1 v ss1 v dd1 v ss1 v dd1 v ss1 v dd1 v ss1 v dd1 v ss1 pw clk t clk-stb t stb-clk t stb-sth t setup1 90% 10% t hold1 t plh1 t inv t pol-stb t stb-pol t plh3 t plh2 t phl2 t phl3 hi-z target voltage 0.1 v dd2 6-bit accuracy t ldt pw stb d 7 -d 12 d 1 -d 6 d 7 -d 12 d 373 - d 378 d 379 - d 384 d 385 - d 390 d 3067 - d 3072 invalid invalid v dd1 v ss1 t spl t setup3 t hold3 pol2 invalid (1st dr.) (1st dr.)
data sheet s12933ej2v0ds00 13 m m m m pd16732 7. recommended soldering conditions the following conditions must be met for soldering conditions of the m pd16732. for more details, refer to the semiconductor device mounting technology manual (c10535e). please consult with our sales offices in case other soldering process is used, or in case the soldering is done under different conditions. type of surface mount device m m m m pd16732n- : tcp (tab package) mounting condition mounting method condition soldering heating tool 300 to 350c: heating for 2 to 3 seconds: pressure 100g (per solder) thermocompression acf (adhesive conductive film) temporary bonding 70 to 100c: pressure 3 to 8 kg/cm 2 : time 3 to 5 secs. real bonding 165 to 180c: pressure 25 to 45 kg/cm 2 : time 30 to 40 secs. (when using the anisotropy conductive film sumizac1003 of sumitomo bakelite, ltd.) caution to find out the detailed conditions for packaging the acf part, please contact the acf manufacturing company. be sure to avoid using two or more packaging methods at a time.
data sheet s12933ej2v0ds00 14 m m m m pd16732 [memo]
data sheet s12933ej2v0ds00 15 m m m m pd16732 notes for cmos devices 1 precaution against esd for semiconductors note: strong electric field, when exposed to a mos device, can cause destruction of the gate oxide and ultimately degrade the device operation. steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. environmental control must be adequate. when it is dry, humidifier should be used. it is recommended to avoid using insulators that easily build static electricity. semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. all test and measurement tools including work bench and floor should be grounded. the operator should be grounded using wrist strap. semiconductor devices must not be touched with bare hands. similar precautions need to be taken for pw boards with semiconductor devices on it. 2 handling of unused input pins for cmos note: no connection for cmos device inputs can be cause of malfunction. if no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. cmos devices behave differently than bipolar or nmos devices. input levels of cmos devices must be fixed high or low by using a pull-up or pull-down circuitry. each unused pin should be connected to v dd or gnd with a resistor, if it is considered to have a possibility of being an output pin. all handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 status before initialization of mos devices note: power-on does not necessarily define initial status of mos device. production process of mos does not define the initial operation status of the device. immediately after the power source is turned on, the devices with reset function have not yet been initialized. hence, power-on does not guarantee out-pin levels, i/o settings or contents of registers. device is not initialized until the reset signal is received. reset operation must be executed immediately after power-on for devices having reset function.
m m m m pd16732 reference documents nec semiconductor device reliability / quality control system (c10983e) quality grades to necs semiconductor devices (c11531e) the information in this document is subject to change without notice. before using this document, please confirm that this is the latest version. no part of this document may be copied or reproduced in any form or by any means without the prior written consent of nec corporation. nec corporation assumes no responsibility for any errors which may appear in this document. nec corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. no license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of nec corporation or others. descriptions of circuits, software, and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. the incorporation of these circuits, software, and information in the design of the customer's equipment shall be done under the full responsibility of the customer. nec corporation assumes no responsibility for any losses incurred by the customer or third parties arising from the use of these circuits, software, and information. while nec corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. to minimize risks of damage or injury to persons or property arising from a defect in an nec semiconductor device, customers must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. nec devices are classified into the following three quality grades: "standard", "special", and "specific". the specific quality grade applies only to devices developed based on a customer designated "quality assurance program" for a specific application. the recommended applications of a device depend on its quality grade, as indicated below. customers must check the quality grade of each device before using it in a particular application. standard: computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots special: transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) specific: aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. the quality grade of nec devices is "standard" unless otherwise specified in nec's data sheets or data books. if customers intend to use nec devices for applications other than those specified for standard quality grade, they should contact an nec sales representative in advance. m7 98. 8

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