View INTERSILCORP-EL9200IL-T7_6851546.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

1 ? fn7438.0 caution: these devices are sensitive to electrosta tic discharge; follow proper ic handling procedures. 1-888-intersil or 321-724-7143 | intersil (and design) is a registered trademark of intersil americas inc. copyright ? intersil americas inc. 2005. all rights reserved. all other trademarks mentioned are the property of their respective owners. el9200, el9201, el9202 programmable v com the el9200, el9201, and el9202 represent programmable v com amplifiers for use in tft-lcd displays. featuring 1, 2, and 4 channels of v com amplification, respectively, each device features just a single programmable current source for adding offset to one v com output. this current source is programmable using a single wir e interface to one of 128 levels. the value is stored on an internal eeprom memory. the el9200 is available in the 12-pin dfn package and the el9201 and el9202 are available in 24-pin qfn packages. all are specified for operation over the -40c to +85c temperature range. typical block diagram features ? 128 step adjustable sink current ? eeprom memory ? 2-pin adjustment and disable ? single, dual or quad amplifiers - 44mhz bandwidth - 80v/s slew rate - 60ma continuous output - 180ma peak output ? up to 18v operation ? 2.6v to 3.6v logic control ? pb-free available (rohs compliant) applications ?tft-lcd v com supplies for -lcd-tvs - lcd monitors - + eeprom control up/down counter analog pot ctl ce v sd a vdd gnd set r set i out inp v out inn r f r g r 1 r 2 a vdd v s + gnd data sheet april 7, 2005
2 fn7438.0 april 7, 2005 pinouts el9200 (12-pin dfn) top view el9201 (24-pin qfn) top view el9202 (24-pin qfn) top view 12 11 10 9 8 7 1 2 3 4 5 6 thermal pad vina- gnd vina+ iout avdd gnd vs+ vouta set ce ctl vsd 19 18 17 16 15 14 13 24 23 22 21 20 8 9 10 11 12 1 2 3 4 5 6 7 nc nc vinb+ iout nc avdd gnd nc vouta vs+ voutb vinb- set ce nc gnd nc vina+ vina- nc nc nc vsd ctl thermal pad 19 18 17 16 15 14 13 24 23 22 21 20 8 9 10 11 12 1 2 3 4 5 6 7 vouta voutd vind- nc vind+ avdd ctl voutb voutc vinc- nc vinc+ gnd avdd vina- vina+ vs+ vinb+ vinb- ce nc set iout nc thermal pad ordering information part number package tape & reel pkg. dwg. # part number package tape & reel pkg. dwg. # el9200il 12-pin dfn - mdp0047 el9201ilz (see note) 24-pin qfn (pb-free) - mdp0046 el9200il-t7 12-pin dfn 7? mdp0047 el9201ilz-t7 (see note) 24-pin qfn (pb-free) 7? mdp0046 el9200il-t13 12-pin dfn 13? mdp0047 el9201ilz-t13 (see note) 24-pin qfn (pb-free) 13? mdp0046 el9200ilz (see note) 12-pin dfn (pb-free) - mdp0047 el9202il 24-pin qfn - mdp0046 el9200ilz-t7 (see note) 12-pin dfn (pb-free) 7? mdp0047 el9202il-t7 24-pin qfn 7? mdp0046 el9200ilz-t13 (see note) 12-pin dfn (pb-free) 13? mdp0047 el9202il-t13 24-pin qfn 13? mdp0046 el9201il 24-pin qfn - mdp0046 el9202ilz (see note) 24-pin qfn (pb-free) - mdp0046 el9201il-t7 24-pin qfn 7? mdp0046 el9202ilz-t7 (see note) 24-pin qfn (pb-free) 7? mdp0046 el9201il-t13 24-pin qfn 13? mdp0046 el9202ilz-t13 (see note) 24-pin qfn (pb-free) 13? mdp0046 note: intersil pb-free products em ploy special pb-free material sets; molding co mpounds/die attach materials and 100% matte tin plate termination finish, which are rohs compliant and compatible with both snpb and pb-free soldering operations. intersil pb-free products are msl classified at pb-free peak reflow temperatures that meet or ex ceed the pb-free requirements of ipc/jedec j std-020. el9200, el9201, el9202
3 fn7438.0 april 7, 2005 absolute maxi mum ratings (t a = 25c) v s + supply voltage between v s + and gnd . . . . . . . . . . . . . .18v supply voltage between v sd and gnd . . . . . . . . . . . . . . . . . . . .4v maximum continuous output current . . . . . . . . . . . . . . . . . . . 65ma input voltages to gnd set, ce . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to +4v ctl. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to +16v output voltages to gnd out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to +20v a vdd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to +20v esd rating - hbm for device . . . . . . . . . . . . . . . . . . . . . . . . . . . 2kv ambient operating temperature . . . . . . . . . . . . . . . .-40c to +85c maximum die temperature . . . . . . . . . . . . . . . . . . . . . . . . . . +150c storage temperature . . . . . . . . . . . . . . . . . . . . . . . .-65c to +150c maximum lead temperature (soldering 10s) . . . . . . . . . . . . +300c caution: stresses above those listed in ?absolute maximum ratings? may cause permanent damage to the device. this is a stress o nly rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. important note: all parameters having min/max specifications are guaranteed. typical values are for information purposes only. u nless otherwise noted, all tests are at the specified temperature and are pulsed tests, therefore: t j = t c = t a electrical specifications v sd = 3v, v s + = 15v, a vdd = 15v, r set = 24.9k ? , and t a = 25c unless otherwise specified parameter description condition min typ max unit v s+ supply voltage 4.5 16.5 v i s+ quiescent current el9200 3.8 4.8 ma el9201 7.6 9.6 ma el9202 10.5 16 ma v sd logic supply voltage for programming 3 3.6 v for operation 2.6 3.6 v i sd quiescent logic current ce = 3.6v 50 a ce = gnd 25 a program (charge pump current) (note 1) 23 ma read (note 1) 3 ma i add supply current note 2 25 a ctl ih ctl high voltage 2.6v < v sd < 3.6v 0.7*v sd 0.8*v sd v ctl il ctl low voltage 2.6v < v sd < 3.6v 0.2*v sd 0.3*v sd v ctl ihrpw ctl high rejected pulse width 20 s ctl ilrpw ctl low rejected pulse width 20 s ctl ihmpw ctl high minimum pulse width 200 s ctl ilmpw ctl low minimum pulse width 200 s ctl mtc ctl minimum time between counts 10 s ictl ctl input current ctl = gnd 10 a ctl = v sd 10 a ctl cap ctl input capacitance 10 pf ce il ce input low voltage 2.6v < v sd < 3.6v 0.4 v ce ih ce input high voltage 2.6v < v sd < 3.6v 1.6 v ce st ce minimum start up time (note 1) 1 m s ctl prom ctl eeprom program voltage 2.6v < v sd < 3.6v (note 2) 4.9 15.75 v ctl pt ctl eeprom programming signal time > 4.9v 200 s p t programming time 100 ms ee wc ee write cycles guaranteed by design 1000 cycles set dn set differential nonlineari ty monotonic over-temperature 1lsb el9200, el9201, el9202
4 fn7438.0 april 7, 2005 set zse set zero-scale error note 3 2lsb set fse set full-scale error note 3 8lsb i set set current through r set (note 1) 120 a set er set external resistance to gnd, a vdd = 20v (note 1) 10 200 k ? to gnd, a vdd = 4.5v (note 1) 2.25 45 k ? a vdd to set a vdd to set voltage attenuation 1:20 v/v out st out settling time to 0.5 lsb error band (note 1) 20 s v out out voltage range (note 1) v set + 0.5v 13 v out vd out voltage drift (note 1) 10 mv amplifier characteristics input characteristics v os input offset voltage v cm = 0v 3 15 mv tcv os average offset voltage drift (note 1) 7 v/c i b input bias current v cm = 0v 2 60 na r in input impedance 1g ? c in input capacitance 2pf cmrr common-mode rejection ratio for v in from -5.5v to +5.5v 50 70 db a vol open-loop gain -4.5v v out +4.5v 60 70 db output characteristics v ol output swing low r l = 1.5k ? to 0 0.09 0.15 v v oh output swing high 14.85 14.9 v i sc short-circuit current 150 180 ma i out output current 65 ma power supply performance psrr power supply rejection ratio v s+ is moved from 4.5v to 15.5v 55 80 db dynamic performance sr slew rate (note 4) -4.0v v out 4.0v, 20% to 80% 60 80 v/s t s settling to +0.1% (a v = +1) (a v = +1), v out = 2v step 80 ns bw -3db bandwidth 44 mhz gbwp gain-bandwidth product 32 mhz pm phase margin 50 cs channel separation f = 5mhz (el9201 & el9202 only) 110 db d g differential gain (note 5) r f = r g = 1k ? and v out = 1.4v 0.17 % d p differential phase (note 5) r f = r g = 1k ? and v out = 1.4v 0.24 notes: 1. simulated and determined via design and not directly tested 2. tested at a vdd = 20v 3. wafer sort only 4. ntsc signal generator used electrical specifications v sd = 3v, v s + = 15v, a vdd = 15v, r set = 24.9k ? , and t a = 25c unless otherwise specified parameter description condition min typ max unit el9200, el9201, el9202
5 fn7438.0 april 7, 2005 pin descriptions pin in/out description equivalent circuit vinx- input amplifier x inverting input, where: x = a for el9200 x = a, b for el9201 x = a, b, c, d for el9202 vinx+ input amplifier x non-inverting input, where: x = a for el9200 x = a, b for el9201 x = a, b, c, d for el9202 reference circuit 1 vs+ supply op amp supply; bypass to gnd with 0.1f capacitor voutx output amplifier x output, where: x = a for el9200 x = a, b for el9201 x = a, b, c, d for el9202 nc - no connect; not internally connected gnd supply ground connection iout output adjustable sink current output pin; the current sinks into the out pin is equal to the dac setting times the maximum adjustable sink current divided by 128; see set pin function description for the maxim ad justable sink current setting set output maximum sink current adjustment point; connect a resistor from set to gnd to set the maximum adjustable sink current of the out pin; the maximum adjustable sink current is equal to (a vdd /20) divided by r set ce input counter enable pin; connect ce to v dd to enable counting of the internal counter; connect ce to gnd to inhibit counting ctl input internal counter up/down control and internal eeprom programming control input; if ce is high, a mid-to-low transition increments the 7-bit counter, raising the dac setting, increasing the out sink current, and lowering the divider voltage at out; a mid-to-high transition decrements the 7-bit counter, lowering the dac setting, decreasing the out sink current, and increasing the divider voltage at out; applying 4.9v and above with appropriately arranged timing will overwrite eeprom with the contents in the 7-bit counter; see eeprom programming section for details avdd supply analog voltage supply; bypass to gnd with 0.1f capacitor vsd supply system power supply inpu t; bypass to gnd with 0.1f capacitor v s+ gnd circuit 1 v s+ gnd gnd circuit 2 el9200, el9201, el9202
6 fn7438.0 april 7, 2005 amplifier typical performance curves figure 1. input offset voltage distribution f igure 2. input bias current vs temperature figure 3. input offset voltage drift figure 4. output high voltage vs temperature figure 5. input offset voltage vs temperatur e figure 6. output low voltage vs temperature quantity (amplifiers) 500 400 300 200 100 0 -12 -10 -8 -6 -4 -2 0 2 4 6 8 10 12 input offset voltage (mv) v s =5v t a =25c typical production distribution v s =5v input bias current (a) 0.008 0.004 0 -0.004 -0.008 -0.012 -50 -10 30 70 110 150 temperature (c) v s =5v typical production distribution quantity (amplifiers) 25 20 15 10 5 0 1 3 5 7 9 11 13 15 17 19 21 input offset voltage drift, tcv os (v/c) v s =5v i out =5ma output high voltage (v) 4.96 4.94 4.92 4.9 4.88 4.86 -50 -10 30 70 110 150 temperature (c) input offset voltage (mv) 2 1.5 1 0.5 0 -0.5 -50 -10 30 70 110 150 temperature (c) v s =5v i out =5ma output low voltage (v) -4.85 -4.87 -4.89 -4.91 -4.93 -4.95 -50 -10 30 70 110 150 temperature (c) el9200, el9201, el9202
7 fn7438.0 april 7, 2005 figure 7. open-loop gain vs temperature figure 8. slew rate vs temperature figure 9. differential gain figure 10. differential phase figure 11. harmonic distortion vs v op-p figure 12. open loop gain and phase amplifier typical performance curves open-loop gain (db) 75 70 65 60 -50 -10 30 70 110 150 temperature (c) v s =5v r l =1k ? v s =v slew rate (v/s) 78 77 76 75 74 72 -50 -10 30 70 110 150 temperature (c) 73 v s =5v a v =2 r l =1k ? differential gain (%) 0 -0.02 -0.04 -0.12 -0.14 -0.18 0 100 200 ire -0.16 -0.06 -0.08 -0.1 differential phase () 0.3 0.25 0.2 0.05 0 0 100 200 ire 0.15 0.1 v s =5v a v =2 r l =1k ? freq=1mhz 2nd hd 3rd hd distortion (db) -30 -40 -50 -80 -90 0810 v op-p (v) -60 -70 246 gain phase 1k 10m 100m frequency (hz) 10k 100k 1m gain (db) 80 60 40 -20 20 0 250 190 130 -50 70 10 phase () el9200, el9201, el9202
8 fn7438.0 april 7, 2005 figure 13. frequency response for various r l figure 14. frequency response for various c l figure 15. closed loop output impedance fig ure 16. maximum output swing vs frequency figure 17. cmrr figure 18. psrr amplifier typical performance curves v s =5v a v =1 c load =0pf 1k ? 560 ? 150 ? 100k 100m frequency (hz) 1m 10m magnitude (normalized) (db) 5 3 1 -5 -1 -3 v s =5v a v =1 r l =1k ? 10pf 47pf 100pf 1000pf 100k 100m frequency (hz) 1m 10m magnitude (normalized) (db) 25 15 5 -25 -5 -15 10k 100m frequency (hz) 100k 10m output impedance ( ? ) 400 350 250 0 200 150 1m 100 50 300 v s =5v a v =1 r l =1k ? distortion <1% 10k 100m frequency (hz) 100k 10m maximum output swing (v p-p ) 12 10 6 0 4 2 1m 8 1k 100m frequency (hz) 100k 10m cmrr (db) -15 -25 -45 -65 -55 1m -35 10k psrr+ v s =5v t a =25c psrr- 100 10m frequency (hz) 10k 1m 100k 1k psrr (db) -80 -60 -20 0 -40 el9200, el9201, el9202
9 fn7438.0 april 7, 2005 figure 19. input voltage noise spectral density figure 20. channel separation figure 21. small-signal overshoot vs load capacitance figure 22. settling time vs step size figure 23. large signal trans ient response figure 24. smal l signal transient response amplifier typical performance curves 100 100m frequency (hz) 10k 1m 100k 1k voltage noise (nv/ hz) 1k 100 1 10 10m 1k 30m frequency (hz) 100k 10m 1m 10k xtalk (db) -60 -80 -140 -160 -120 -100 dual measured ch a to b quad measured ch a to d or b to c other combinations yield improved rejection v s =5v r l =1k ? a v =1 v in =110mv rms v s =5v a v =1 r l =1k ? v in =50mv t a =25c 10 1k load capacitance (pf) 100 overshoot (%) 100 60 0 20 80 40 v s =5v a v =1 r l =1k ? 0.1% 0.1% 55 105 settling time (ns) 75 95 65 step size (v) 5 3 -3 -5 -1 1 85 50ns/div 1v step v s =5v t a =25c a v =1 r l =1k ? 50ns/div 100mv step v s =5v t a =25c a v =1 r l =1k ? el9200, el9201, el9202
10 fn7438.0 april 7, 2005 application information this device provides the ability to reduce the flicker of an lcd panel by adjustment of the v com voltage during production test and alignment. a 128-step resolution is provided under digital control which adjusts the sink current of the output. the output is co nnected to an external voltage divider, so that the device will have the capability to reduce the voltage on the output by increasing the output sink current. the adjustment of the output and the programming of the non-volatile memory are provided on one pin while the counter enable (ce) is provided on a separate pin. the output is adjusted via the ctl pin either by counting up with a mid to low transition or by counting down with a mid to high transition. once the minimum or maximum value is reached on the 128 steps, the device will not overflow or underflow beyond that minimum or maximu m value. an increment of the counter will increase the output sink current which will lower the voltage on the external voltage divider. a decrement of the counter will decrease the output sink current, which will raise the voltage on the external voltage divider. once the desired output level is obtained, the part can store it's setting using the non-volatile memory in the device. see the non-volatile programming section for detailed information. note: once the desired output level is stored in the eeprom, the ce pin must go low to preserve the stored value. adjustable sink current output the device provides an output sink current which lowers the voltage on the external voltage divider. the equations that control the output are given below: note: where setting is an integer between 1 and 128. 7-bit up/down counter the counter sets the level to t he digital potentiometer and is connected to the non-volatile memory. when the part is programmed, the counter setting is loaded into the non- volatile memory. this value will be loaded from the non- volatile memory into the counter during power-on. the counter will not exceed its maximum level and will hold that value during subsequent increment requests on the ctl pin. the counter will not exceed its minimum level and will hold that value during subsequent decrement requests on the ctl pin. ctl pin ctl should have a noise filter to reduce bouncing or noise on the input that could cause unwanted counting when the ce pin is high. the board should have an additional esd protection circuit, with a series 1k ? resistor and a shunt 0.01f capacitor connected on the ctl pin. in order to increment the setting, pulse ctl low for more than 200s. the output sink current increases and lowers the v com lever by one least-significant bit (lsb). on the other hand, to decrement the setting, pulse ctl high for figure 25. package power dissipation vs ambient temperature figure 26. package power dissipation vs ambient temperature amplifier typical performance curves jedec jesd51-7 high effective thermal conductivity test board - qfn exposed diepad soldered to pcb per jesd51-5 3.378w j a = 3 7 c / w q f n 2 4 0 150 ambient temperature (c) 75 power dissipation (w) 4.5 3 0 1 4 2 2.5 0.5 3.5 1.5 25 100 50 125 85 jedec jesd51-3 low effective thermal conductivity test board j a = 1 4 0 c / w q f n 2 4 893mw 0 150 ambient temperature (c) 75 power dissipation (w) 1.2 0.6 0 1 0.2 0.4 0.8 25 100 50 125 85 i out setting 128 -------------------- - a vdd 20 r set () --------------------------- = v out r 2 r 1 r 2 + -------------------- - ?? ?? ?? v avdd 1 setting 128 -------------------- - r 1 20 r set () --------------------------- ? ?? ?? ?? = el9200, el9201, el9202
11 fn7438.0 april 7, 2005 more than 200s. the output si nk current will decrease and the v com level will increase by one lsb. to avoid unintentional adjustmen t, the el9200, el9201, and el9202 guarantees to reject ctl pulses shorter than 20s. since the internal comparators come up in an unknown state, the very first ctl pulse is ignored to avoid the possibility of a false pulse. see figure 27 for the timing information. figure 27. v com adjustment table 1. truth table input output ctl ce v dd set i cc memory mid to hi hi v dd decrement normal x mid to lo hi v dd increment normal x xlov dd no change lower x > 4.9v x v dd no change increased program x x 0 to v dd read increased read note: ce should be disabled (pulled low) befo re powering down the device to assure that the glitches and transients will not cau se unwanted eeprom overwriting. ctl high v dd /2 ctl low 78 79 7a 7b 7a undef ctl ihmpw ctl ilrpw ctl ilmpw ctl mtc ctl ihrpw ctl ce counter output v com el9200, el9201, el9202
12 fn7438.0 april 7, 2005 non-volatile memory (eeprom) programming when the ctl pin exceeds 4.9v, the non-volatile programming cycle will be acti vated. the ctl signal needs to remain above 4.9v for more than 200s. the level and timing needed to program the non-volatile memory is given below. it then takes a maximum of 100ms for the programming to be completed inside the device (see p t specification in electric al specification table). figure 28. eeprom programming amplifiers? operating voltage, input, and output the amplifiers are specified with a single nominal supply voltage from 5v to 15v or a split supply with its total range from 5v to 15v. correct operation is guaranteed for a supply range of 4.5v to 16.5v. most amplifier specifications are stable over both the full supply range and operating temperatures of -40c to +85 c. parameter variations with operating voltage and/or temperature are shown in the typical performance curves. the input common-mode volta ge range of the amplifiers extends 500mv beyond the supp ly rails. the output swings of the those typically extend to within 100mv of positive and negative supply rails with load currents of 5ma. decreasing load currents will extend the output voltage range even closer to the supply rails. figure 27 shows the input and output waveforms for the device in the unity-gain configuration. operation is from 5v supply with a 1k ? load connected to gnd. the input is a 10v p-p sinusoid. the output voltage is approximately 9.8v p-p . figure 29. operation with rail-to-rail input and output short-circuit current limit the amplifiers will limit the shor t circuit current to 180ma if the output is directly shorted to the positive or the negative supply. if an output is shorted indefinitely, the power dissipation could easily increase such that the device may be damaged. maximum reliability is maintained if the output continuous current never exceeds 65ma. this limit is set by the design of the internal metal interconnects. output phase reversal the amplifiers are immune to phase reversal as long as the input voltage is limited from v s - -0.5v to v s + +0.5v. figure 28 shows a photo of the output of the device with the input voltage driven beyond the supply rails. although the device's output will not change phase, the input's over-voltage should be avoided. if an input voltage exceeds supply voltage by more than 0.6v, electrostatic pr otection diodes placed in the input stage of the device begin to conduct and over-voltage damage could occur. figure 30. operation with beyond-the-rails input unused amplifiers it is recommended that any unused amplifiers in a dual and a quad package be configured as a unity gain follower. the inverting input should be dire ctly connected to the output and the non-inverting input tied to the ground plane. power supply bypassing and printed circuit board layout the amplifiers can provide gain at high frequency. as with any high-frequency device, good printed circuit board layout is necessary for optimum performance. ground plane construction is highly recommended, lead lengths should be as short as possible and the power supply pins must be well bypassed to reduce the risk of oscillation. for normal operation a 0.1f ceramic capacitor should be placed from v s to pin to gnd. a 4.7f tantalum capacitor should then be connected in parallel, placed in the region of the amplifier. ctl pt time 4.9v ctl voltage output input 5v 5v 10s a v =1 v s =5v t a =25c v in =10v p-p 1v 1v 10s v s =2.5v a v =1 t a =25c v in =6v p-p el9200, el9201, el9202
13 fn7438.0 april 7, 2005 replacing existing mechanical potentiometer circuits figures 29 and 30 show the common adjustment mechanical circuits and equivalent replacement with the el920x. figure 31. example of the replacement for th e mechanical potentiometer circuit using el9200 figure 32. example of the replacement for the mechanical potentiometer circuit using the el9200 - + v com r a r b r c a vdd v out in+ out el9200 set a vdd in- r f r g a vdd r 1 r 2 v com r set r 1 r a = r 2 r b r c + = r set r a r b r c + () 20r b ----------------------------------- - = - + v com r x r y r z a vdd v out in+ out el9200 set a vdd in- r f r g a vdd r 1 r 2 v com r set r 1 r x = r 2 r z = r set r x r x r y r z ++ () 20r y ------------------------------------------------- - = el9200, el9201, el9202
14 all intersil u.s. products are manufactured, asse mbled and tested utilizing iso9000 quality systems. intersil corporation?s quality certifications ca n be viewed at www.intersil.com/design/quality intersil products are sold by description only. intersil corpor ation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnishe d by intersil is believed to be accurate and reliable. however, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringements of paten ts or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiari es. for information regarding intersil corporation and its products, see www.intersil.com fn7438.0 april 7, 2005 qfn package outline drawing note: the package drawing shown here may not be the latest version. to check the latest revision, please refer to the intersil w ebsite at http://www.intersil.com/design/packages/index.asp el9200, el9201, el9202

▲Up To Search▲

Price & Availability of INTERSILCORP-EL9200IL-T7

	To Download INTERSILCORP-EL9200IL-T7 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .