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general description the 32k x 8 radiation hardened rom is a high perform- ance 32,768 word x 8-bit read only memory with industry- standard functionality. it is fabricated with honeywell?s radiation hardened technology, and is designed for use in systems operating in radiation environments. the rom operates over the full military temperature range and re- quires only a single 5 v 10% power supply. the rom is available with either ttl or cmos compatible i/o. power consumption is typically less than 15 mw/mhz in operation, and less than 5 mw when de-selected. the rom operation is fully asynchronous, with an associated typical access time of 14 ns. honeywell?s enhanced soi ricmos ? iv (radiation insen- sitive cmos) technology is radiation hardened through the use of advanced and proprietary design, layout, and pro- cess hardening techniques. the ricmos ? iv process is a 5-volt, simox cmos technology with a 150 ? gate oxide and a minimum drawn feature size of 0.75 m (0.6 m effective gate length?l eff ). additional features include tungsten via plugs, honeywell?s proprietary sharp pla- narization process, and a lightly doped drain (ldd) struc- ture for improved short channel reliability. radiation ? fabricated with ricmos ? iv silicon on insulator (soi) 0.75 m process (l eff = 0.6 m) ? total dose hardness through 1x10 6 rad(sio 2 ) ? dynamic and static transient upset hardness through 1x10 9 rad(si)/s ? dose rate survivability through 1x10 11 rad(si)/s ? neutron hardness through 1x10 14 cm -2 ? seu immune ? latchup free 32k x 8 rom?soi hx6656 other ? read cycle times < 17 ns (typical) 25 ns (-55 to 125 c) ? typical operating power <15 mw/mhz ? asynchronous operation ? cmos or ttl compatible i/o ? single 5 v 10% power supply ? packaging options - 28-lead flat pack (0.500 in. x 0.720 in.) - 28-lead dip, mil-std-1835, cdip2-t28 - 36-lead flat pack (0.630 in. x 0.650 in.) military & space products features
hx6656 2 functional diagram ncs ce* noe mode q l h l read data out h x xx deselected high z x l xx disabled high z signal definitions a: 0-14 address input pins which select a particular eight-bit word within the memory array. q: 0-7 data output pins. ncs negative chip select, when at a low level allows normal read operation. when at a high level ncs forces the rom to a precharge condition, holds the data output drivers in a high impedance state and disables all input buffers except ce. if this signal is not used it must be connected to vss. noe negative output enable, when at a high level holds the data output drivers in a high impedance state. when at a low level, the data output driver state is defined by ncs and ce. if this signal is not used it must be connected to vss. ce* chip enable, when at a high level allows normal operation. when at a low level ce forces the rom to a precharge condition, holds the data output drivers in a high impedance state and disables all the input buffers except the ncs input buffer. if this signal is not used it must be connected to vdd. *not available in 28-lead dip or 28-lead flat pack truth table notes: x: vi=vih or vil xx: vss vi vdd noe=h: high z output state maintained for ncs=x, ce=x ncs a:0-8,12-13 ce noe cs ? ce ? oe row decoder 32,768 x 8 m emory array a:9-11,14 # sig nal all controls must b e e nab le d fo r a sig nal to p ass. (#: numb er of b uffers, default = 1) 1 = e nab le d sig nal 4 q:0-7 (0 = high z) ? ? ? ? ? ? 11 column decoder data o utp ut 8
hx6656 3 radiation characteristics total ionizing radiation dose the rom will meet all stated functional and electrical specifications over the entire operating temperature range after the specified total ionizing radiation dose. all electrical and timing performance parameters will remain within specifications after rebound at vdd = 5.5 v and t =125 c extrapolated to ten years of operation. total dose hardness is assured by wafer level testing of process monitor transis- tors and rom product using 10 kev x-ray and co60 radiation sources. transistor gate threshold shift correla- tions have been made between 10 kev x-rays applied at a dose rate of 1x10 5 rad(sio 2 )/min at t = 25 c and gamma rays (cobalt 60 source) to ensure that wafer level x-ray testing is consistent with standard military radiation test environments. transient pulse ionizing radiation the rom is capable of reading and retaining stored data during and after exposure to a transient ionizing radiation pulse of 1 s duration up to 1x10 9 rad(si)/s, when applied under recommended operating conditions. to ensure va- lidity of all specified performance parameters before, dur- ing, and after radiation (timing degradation during tran- sient pulse radiation (timing degradation during transient pulse radiation is 10%), it is suggested that stiffening capacitance be placed on or near the package vdd and vss, with a maximum inductance between the package (chip) and stiffening capacitance of 0.7 nh per part. if there are no operate-through requirements, typical circuit board mounted de-coupling capacitors are recommended. the rom will meet any functional or electrical specifica- tion after exposure to a radiation pulse of 50 ns duration up to 1x10 11 rad(si)/s, when applied under recommended operating conditions. neutron radiation the rom will meet any functional or timing specification after a total neutron fluence of up to 1x10 14 cm -2 applied under recommended operating or storage conditions. this assumes an equivalent neutron energy of 1 mev. single event phenomena all storage elements within the rom are immune to single event upsets. no access time or other performance deg- radation will occur for let 190 mev/cm/mg 2 . latchup the rom will not latch up due to any of the above radiation exposure conditions when applied under recommended operating conditions. fabrication with the simox sub- strate material provides oxide isolation between adjacent pmos and nmos transistors and eliminates any potential scr latchup structures. sufficient transistor body tie con- nections to the p- and n-channel substrates are made to ensure no source/drain snapback occurs. total dose 1x10 6 rad(sio 2 ) transient dose rate upset (3) 1x10 9 rad(si)/s transient dose rate survivability (3) 1x10 11 rad(si)/s neutron fluence 1x10 14 n/cm 2 parameter limits (2) test conditions radiation hardness ratings (1) units t a =25 c (1) device will not latch up due to any of the specified radiation exposure conditions. (2) operating conditions (unless otherwise specified): vdd=4.5 v to 5.5 v, ta=-55 c to 125 c. (3) not guaranteed with 28?lead dip. 1 mev equivalent energy, unbiased, t a =25 c pulse width 50 ns, x-ray, vdd=6.0 v, t a =25 c pulse width 1 s
hx6656 4 vdd positive supply voltage (2) -0.5 7.0 v vpin voltage on any pin (2) -0.5 vdd+0.5 v tstore storage temperature (zero bias) -65 150 c tsolder soldering temperature ? time 270?5 c?s pd total package power dissipation (3) 2.5 w iout dc or average output current 25 ma vprot esd input protection voltage (4) 2000 v 28 fp/36 fp 2 28 dip 10 tj junction temperature 175 c parameter symbol absolute maximum ratings (1) parameter max symbol test conditions worst case units capacitance (1) (1) stresses in excess of those listed above may result in permanent damage. these are stress ratings only, and operation at the se levels is not implied. frequent or extended exposure to absolute maximum conditions may affect device reliability. (2) voltage referenced to vss. (3) rom power dissipation (iddsb + iddop) plus rom output driver power dissipation due to external loading must not exceed this specification. (4) class 2 electrostatic discharge (esd) input protection. tested per mil-std-883, method 3015 by desc certified lab. jc thermal resistance (jct-to-case) (1) this parameter is tested during initial design characterization only. recommended operating conditions symbol max typ description parameter min c/w units vdd supply voltage (referenced to vss) 4.5 5.0 5.5 v ta ambient temperature -55 25 125 c vpin voltage on any pin (referenced to vss) -0.3 vdd+0.3 v min typical (1) ci input capacitance 7 pf vi=vdd or vss, f=1 mhz co output capacitance 9 pf vio=vdd or vss, f=1 mhz units rating min max
hx6656 5 iddsb1 static supply current 1.5 ma iddsbmf standby supply current - deselected 1.5 ma iddopr dynamic supply current, selected 4.0 ma ii input leakage current -1 +1 a ioz output leakage current -1 +1 a vil low-level input voltage vih high-level input voltage dc electrical characteristics units test conditions min max worst case (2) symbol parameter typical (1) ncs=vdd, io=0, f=40 mhz vih=vdd io=0 vil=vss inputs stable (1) typical operating conditions: vdd= 5.0 v,ta=25 c, pre-radiation. (2) worst case operating conditions: vdd=4.5 v to 5.5 v, -55 c to +125 c, post total dose at 25 c. (3) all inputs switching. dc average current. f=1 mhz, io=0, ce=vih=vdd ncs=vil=vss vss vi vdd vss vio vdd output=high z 0.4 v vdd = 4.5v, iol = 10 ma 0.05 v vdd = 4.5v, iol = 200 a 4.2 v vdd = 4.5v, ioh = -5 ma v dd -0.05 v vdd = 4.5v, ioh = -200 a cmos 0.3xv dd v ttl 0.8 v vdd = 4.5v cmos 0.7xv dd v ttl 2.2 v vdd = 5.5v voh high-level output voltage vol low-level output voltage dut output valid low output vref1 c l > 50 pf* 249 ? tester equivalent load circuit 2.9 v valid high output vref2 - + - + *c l = 5 pf for twlqz, tshqz, telqz, and tghqz
hx6656 6 tavavr address read cycle time 25 ns tavqv address access time 25 ns taxqx address change to output invalid time 3 ns tslqv chip select access time 25 ns tslqx chip select output enable time 5 ns tshqz chip select output disable time 10 ns tehqv chip enable access time (4) 25 ns tehqx chip enable output enable time (4) 5 ns telqz chip enable output disable time (4) 10 ns tglqv output enable access time 9 ns tglqx output enable output enable time 0 ns tghqz output enable output disable time 9 ns read cycle ac timing characteristics (1) worst case (3) symbol parameter typical -55 to 125 c units (2) min max high impedance ncs noe data valid ce t avavr t avqv t axqx t slqv t slqx t shqz t ehqx t ehqv t glqx t glqv t ghqz t elqz address data out (1) test conditions: input switching levels vil/vih=0.5v/vdd-0.5v (cmos), vil/vih=0v/3v (ttl), input rise and fall times <1 ns/v , input and output timing reference levels shown in the tester ac timing characteristics table, capacitive output loading c l >50 pf, or equivalent capacitive output loading c l =5 pf for tshqz, telqz tghqz. for c l >50 pf, derate access times by 0.02 ns/pf (typical). (2) typical operating conditions: vdd=5.0 v, ta=25 c, pre-radiation. (3) worst case operating conditions: vdd=4.5 v to 5.5 v, -55 c to +125 c, post total dose at 25 c. (4) chip enable (ce) pin not available on 28-lead fp or dip.
hx6656 7 read cycle the rom is asynchronous in operation, allowing the read cycle to be controlled by address, chip select (ncs), or chip enable (ce) (refer to read cycle timing diagram). to perform a valid read operation, both chip select and output enable (noe) must be low and chip enable must be high. the output drivers can be controlled independently by the noe signal. consecutive read cycles can be executed with ncs held continuously low, and with ce held continuously high, and toggling the addresses. for an address activated read cycle, ncs and ce must be valid prior to or coincident with the activating address edge transition(s). any amount of toggling or skew between address edge transitions is permissible; however, data outputs will become valid tavqv time following the latest occurring address edge transition. the minimum address activated read cycle time is tavav. when the rom is operated at the minimum address activated read cycle time, the data outputs will remain valid on the i/o until taxqx time following the next sequential address transi- tion. to control a read cycle with ncs, all addresses and ce must be valid prior to or coincident with the enabling ncs edge transition. address or ce edge transitions can occur later than the specified setup times to ncs, however, the valid data access time will be delayed. any address edge transition, which occurs during the time when ncs is low, will initiate a new read access, and data outputs will not become valid until tavqv time following the address edge transition. data outputs will enter a high impedance state tshqz time following a disabling ncs edge transition. to control a read cycle with ce, all addresses and ncs must be valid prior to or coincident with the enabling ce edge transition. address or ncs edge transitions can occur later than the specified setup times to ce; however, the valid data access time will be delayed. any address edge transition which occurs during the time when ce is high will initiate a new read access, and data outputs will not become valid until tavqv time following the address edge transition. data outputs will enter a high impedance state telqz time following a disabling ce edge transition. dynamic electrical characteristics
hx6656 8 tester ac timing characteristics quality and radiation hardness assurance honeywell maintains a high level of product integrity through process control, utilizing statistical process control, a com- plete ?total quality assurance system,? a computer data base process performance tracking system, and a radia- tion-hardness assurance strategy. the radiation hardness assurance strategy starts with a technology that is resistant to the effects of radiation. radiation hardness is assured on every wafer by irradiating test structures as well as product die, and then monitoring key parameters which are sensitive to ionizing radiation. conventional mil-std-883c tm 5005 group e testing, which includes total dose exposure with cobalt 60, may also be performed as required. this total quality approach ensures our customers of a reliable product by engineering in reliability, starting with process development and con- tinuing through product qualification and screening. screening levels honeywell offers several levels of device screening to meet your system needs. ?engineering devices? are available with limited performance and screening for breadboarding and/or evaluation testing. hi-rel level b and s devices undergo additional screening per the requirements of mil- std-883. as a qml supplier, honeywell also offers qml class q and v devices per mil-prf-38535 and are avail- able per the applicable standard military drawing (smd). qml devices offer ease of procurement by eliminating the need to create detailed specifications and offer benefits of improved quality and cost savings through standardization. reliability honeywell understands the stringent reliability require - ments for space and defense systems and has extensive experience in reliability testing on programs of this nature. this experience is derived from comprehensive testing of vlsi processes. reliability attributes of the ricmos tm process were characterized by testing specially designed irradiated and non-irradiated test structures from which specific failure mechanisms were evaluated. these specific mechanisms included, but were not limited to, hot carriers, electromigration and time dependent dielectric breakdown. this data was then used to make changes to the design models and process to ensure more reliable products. in addition, the reliability of the ricmos tm process and product in a military environment was monitored by testing irradiated and non-irradiated circuits in accelerated dy- namic life test conditions. packages are qualified for prod- uct use after undergoing groups b & d testing as outlined in mil-std-883, tm 5005, class s. the product is qualified by following a screening and testing flow to meet the customer?s requirements. quality conformance testing is performed as an option on all production lots to ensure the ongoing reliability of the product. high z = 2.9v 3 v 0 v 1.5 v vdd-0.5 v 0.5 v vdd/2 1.5 v vdd-0.4v 0.4 v high z 3.4 v 2.4 v high z vdd/2 0.4 v high z 3.4 v 2.4 v high z ttl i/o configuration input levels* output sense levels cmos i/o configuration high z = 2.9v * input rise and fall times <1 ns/v vdd-0.4v
hx6656 9 packaging the 32k x 8 rom is offered in a custom 36-lead flat pack (fp), 28-lead fp, or standard 28-lead dip. each package is constructed of multilayer ceramic (al 2 o 3 ) and features internal power and ground planes. the 36-lead fp also features a non-conductive ceramic tie bar on the lead frame. the tie bar allows electrical testing of the device, while preserving the lead integrity during shipping and handling, up to the point of lead forming and insertion. ceramic chip capacitors can be mounted to the package to maximize supply noise decoupling and increase board packing density. these capacitors attach directly to the internal package power and ground planes. this design minimizes resistance and inductance of the bond wire and package. all nc (no connect) pins must be connected to either vdd, vss or an active driver to prevent charge build up in the radiation environment. 28-lead fp pinout 36-lead fp pinout 36-lead flat pack [1] parts delivered with leads unformed [2] at tie bar [3] lid tied to vss a b c d e e f g h i j l 0.095 0.014 0.008 0.002 0.005 to 0.0075 0.650 0.010 0.630 0.007 0.025 0.002 [2] 0.425 0.005 [2] 0.525 0.005 0.135 0.005 0.030 0.005 0.080 typ. 0.285 0.015 m n o p r s t u v w x y 0.008 0.003 0.050 0.010 0.090 ref 0.015 ref 0.075 ref 0.113 0.010 0.050 ref 0.030 ref 0.080 ref 0.005 ref 0.450 ref 0.400 ref all dimensions are in inches [1] kovar lid [3] ceramic body a j i c m 0.004 n x vdd optional capacitors 1 f vss v s w p u 1 y vdd vss o t r non- conductive tie-bar d b (width) e (pitch) e 1 h g l l t o p v i e w 22018131-001 vdd nwe a13 a8 a9 a11 noe a10 ncs dq7 dq6 dq5 dq4 dq3 a14 a12 a7 a6 a5 a4 a3 a2 a1 a0 dq0 dq1 dq2 vss 28 27 26 25 24 23 22 21 20 19 18 17 16 15 1 2 3 4 5 6 7 8 9 10 11 12 13 14 top view vss vdd nwe ce a13 a8 a9 a11 noe a10 ncs dq7 dq6 dq5 dq4 dq3 vdd vss vss vdd a14 a12 a7 a6 a5 a4 a3 a2 a1 a0 dq0 dq1 dq2 nc vdd vss 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 top view 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18
hx6656 10 e 1 e b d (width) (pitch) l top view u w x y capacitor pads f [1] bsc ? basic lead spacing between centers [2] where lead is brazed to package [3] parts delivered with leads unformed [4] lid connected to vss a b c d e e e2 e3 f g l q s u w x y 0.105 0.015 0.017 0.002 0.003 to 0.006 0.720 0.008 0.050 0.005 [1] 0.500 0.007 0.380 0.008 0.060 ref 0.650 0.005 [2] 0.035 0.004 0.295 min [3] 0.026 to 0.045 0.045 0.010 0.130 ref 0.050 ref 0.075 ref 0.010 ref all dimensions in inches 1 a lead alloy 42 [3] ceramic body c e2 g q kovar lid [4] e3 bottom view s index 28-lead flat pack (22017842-001) for 28-lead dip description, see mil-std-1835, type cdip2-t28, config. c, dimensions d-10 28-lead dip (22017785-001)
hx6656 11 vdd = 6.5v, r 10 k ? , vih = vdd, vil = vss ambient temperature 125 c, f0 100 khz sq wave frequency of f1 = f0/2, f2 = f0/4, f3 = f0/8, etc. vdd = 5.5v, r 10 k ? ambient temperature 125 c rom code the rom code can be provided to honeywell via ftp, e-mail or a variety of magnetic storage media, including 3.5 inch floppy disc, 4m digital tape and others. the rom code data file should contain the following format:

[/] [;] [comment] where items enclosed in ?[?and?]? are optional. the address and data must be hex numbers in the form, msb...lsb. the ?/? and the ?;? are optional and any characters after the ?#? are comments. for example the following input file, all of the lines are valid: 000 d4 001 / 32 002 1d 003 / 72; 4/5e; # all of these lines are in valid format r f0 f15 f12 f11 f10 f17 f9 f17 f1 f1 f1 f1 f1 vss vdd 32k x 8 rom a14 a12 a7 a6 a5 a4 a3 a2 a1 a0 dq0 dq1 dq2 vss vdd nc a13 a8 a9 a11 noe a10 ncs dq7 dq6 dq5 dq4 dq3 28 27 26 25 24 23 22 21 20 19 18 17 16 15 1 2 3 4 5 6 7 8 9 10 11 12 13 14 f16 f7 f6 f5 f4 f3 f2 f8 f13 f14 f1 f1 f1 r r r r r r r r r r r r r r r r r r r r r r r r r vss vdd 32k x 8 rom a14 a12 a7 a6 a5 a4 a3 a2 a1 a0 dq0 dq1 dq2 vss vdd nc a13 a8 a9 a11 noe a10 ncs dq7 dq6 dq5 dq4 dq3 28 27 26 25 24 23 22 21 20 19 18 17 16 15 1 2 3 4 5 6 7 8 9 10 11 12 13 14 vdd r r r r r r r r r r r r r r r r r r r r r r r r r r r *36-lead flat pack burn-in diagrams have similar connections and are available on request. dynamic burn-in diagram* static burn-in diagram*
honeywell reserves the right to make changes to any products or technology herein to improve reliability, function or design. h oneywell does not assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent rights nor the rights of others. helping you control your world 900154 2/96 source h=honeywell part number s 6656 x h n process x=soi c input buffer type c=cmos level t=ttl level h ordering information (1) package designation n=28-lead fp r=28-lead dip x=36-lead fp k=known good die - = bare die (no package) screen level v=qml class v q=qml class q s=level s b=level b e=engr device (2) total dose hardness r=1x10 5 rad(sio 2 ) f=3x10 5 rad(sio 2 ) h=1x10 6 rad(sio 2 ) n=no level guaranteed (1) orders may be faxed to 612-954-2051. please contact our customer logistics department at 612-954-2888 for further informatio n. (2) engineering device description: parameters are tested from -55 to 125 c, 24 hr burn-in, no radiation guaranteed. contact factory with other needs. to learn more about honeywell solid state electronics center, visit our web site at http://www.ssec.honeywell.com hx6656

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