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| the mark data sheet m14671ej9v0ds 2 pd442012a-x ordering information part number package access time operating operating remark ns (max.) supply voltage temperature v c pd442012agy-bb55x-mjh 48-pin plastic tsop (i) 55, 50 note 2.7 to 3.6 ? 25 to +85 bb version pd442012agy-bb70x-mjh (12 18) (normal bent) 70 pd442012agy-bb85x-mjh 85 pd442012agy-bc70x-mjh 70 2.2 to 3.6 bc version pd442012agy-bc85x-mjh 85 pd442012agy-bc10x-mjh 100 pd442012agy-dd85x-mjh 85 1.8 to 2.2 dd version pd442012agy-dd10x-mjh 100 pd442012agy-dd12x-mjh 120 pd442012agy-bb55x-mjh-a 55, 50 note 2.7 to 3.6 bb version pd442012agy-bb70x-mjh-a 70 pd442012agy-bb85x-mjh-a 85 pd442012agy-bc70x-mjh-a 70 2.2 to 3.6 bc version pd442012agy-bc85x-mjh-a 85 pd442012agy-bc10x-mjh-a 100 pd442012agy-dd85x-mjh-a 85 1.8 to 2.2 dd version pd442012agy-dd10x-mjh-a 100 pd442012agy-dd12x-mjh-a 120 note v cc 3.0 v remark products with -a at the end of t he part number are lead-free products. data sheet m14671ej9v0ds 3 pd442012a-x pin configuration (marking side) /xxx indicates active low signal. 48-pin plastic tsop (i) (12 18) (normal bent) [ pd442012agy-bbxxx-mjh ] [ pd442012agy-bcxxx-mjh ] [ pd442012agy-ddxxx-mjh ] [ pd442012agy-bbxxx-mjh-a ] [ pd442012agy-bcxxx-mjh-a ] [ pd442012agy-ddxxx-mjh-a ] a15 a14 a13 a12 a11 a10 a9 a8 nc nc /we ce2 ic /ub /lb nc nc a7 a6 a5 a4 a3 a2 a1 a16 nc gnd i/o16 i/o8 i/o15 i/o7 i/o14 i/o6 i/o13 i/o5 v cc i/o12 i/o4 i/o11 i/o3 i/o10 i/o2 i/o9 i/o1 /oe gnd /ce1 a0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 a0 - a16 : address inputs i/o1 - i/o16 : data inputs / outputs /ce1, ce2 : chip enable 1, 2 /we : write enable /oe : output enable /lb, /ub : byte data select v cc : power supply gnd : ground nc : no connection ic note : internal connection note leave this pin unconnected or connect to gnd. remark refer to package drawing for the 1-pin index mark. data sheet m14671ej9v0ds 4 pd442012a-x block diagram address buffer address buffer row decoder memory cell array 2,097,152 bits input data controller a0 a16 i/o9 - i/o16 /ce1 /we /oe ce2 /ub /lb output data controller i/o1 - i/o8 v cc gnd sense amplifier / switching circuit column decoder data sheet m14671ej9v0ds 5 pd442012a-x truth table /ce1 ce2 /oe /we /lb /ub mode i/o supply current i/o1 - i/o8 i/o9 - i/o16 h not selected high impedance high impedance i sb l not selected high impedance high impedance h h not selected high impedance high impedance l h h h l output disable hi gh impedance high impedance i cca l output disable hi gh impedance high impedance l h l l word read d out d out l h lower byte read d out high impedance h l upper byte read high impedance d out l l l word write d in d in l h lower byte write d in high impedance h l upper byte write high impedance d in remark : v ih or v il data sheet m14671ej9v0ds 6 pd442012a-x electrical specifications absolute maximum ratings parameter symbol product rating unit supply voltage v cc pd442012a-bbxxx, pd442012a-bcxxx ?0.5 note to +4.0 v pd442012a-ddxxx ?0.5 note to +2.7 input / output voltage v t pd442012a-bbxxx, pd442012a-bcxxx ?0.5 note to v cc +0.4 (4.0 v max.) v pd442012a-ddxxx ?0.5 note to v cc +0.4 (2.7 v max.) operating ambient temperature t a ?25 to +85 c storage temperature t stg ?55 to +125 c note ?3.0 v (min.) (pulse width : 30 ns) caution exposing the device to stress above those listed in absolute maximum rating could cause permanent damage. the device is not meant to be operated under conditions outside the limits described in the operational section of this speci fication. exposure to absolute maximum rating conditions for extended periods may affect device reliability. recommended operating conditions parameter symbol condition pd442012a-bbxxx pd442012a-bcxxx pd442012a-ddxxx unit min. max. min. max. min. max. supply voltage v cc 2.7 3.6 2.2 3.6 1.8 2.2 v high level input voltage v ih 2.7 v v cc 3.6 v 2.4 v cc +0.4 2.4 v cc +0.4 ? ? v 2.2 v v cc < 2.7 v ? ? 2.0 v cc +0.3 ? ? 1.8 v v cc < 2.2 v ? ? ? ? 1.6 v cc +0.2 low level input voltage v il ?0.3 note +0.5 ?0.3 note +0.4 ?0.2 note +0.2 v operating ambient t a ?25 +85 ?25 +85 ?25 +85 c temperature note ?1.0 v (min.) (pulse width : 20 ns) capacitance (t a = 25 c, f = 1 mhz) parameter symbol test condition min. typ. max. unit input capacitance c in v in = 0 v 8 pf input / output capacitance c i/o v i/o = 0 v 10 pf remarks 1. v in : input voltage v i/o : input / output voltage 2. these parameters ar e not 100% tested. data sheet m14671ej9v0ds 7 pd442012a-x dc characteristics (recommended operating c onditions unless otherwise noted) (1/2) parameter symbol test condition pd442012a-bbxxx unit min. typ. max. input leakage current i li v in = 0 v to v cc ?1.0 +1.0 a i/o leakage current i lo v i/o = 0 v to v cc , /ce1 = v ih or ?1.0 +1.0 a ce2 = v il or /we = v il or /oe = v ih operating supply current i cca1 /ce1 = v il , ce2 = v ih , cycle time = 50 ns ? 40 ma i i/o = 0 ma, cycle time = 55 ns ? 35 minimum cycle time cycle time 70 ns ? 30 i cca2 /ce1 = v il , ce2 = v ih , ? 4 i i/o = 0 ma, cycle time = i cca3 /ce1 0.2 v, ce2 v cc ? 0.2 v, ? 4 cycle time = 1 s, i i/o = 0 ma, v il 0.2 v, v ih v cc ? 0.2 v standby supply current i sb /ce1 = v ih or ce2 = v il or /lb = /ub = v ih ? 0.6 ma i sb1 /ce1 v cc ? 0.2 v, ce2 v cc ? 0.2 v 0.3 4 a i sb2 ce2 0.2 v 0.3 4 i sb3 /lb = /ub v cc ? 0.2 v, 0.3 4 /ce1 0.2 v, ce2 v cc ? 0.2 v high level output voltage v oh i oh = ?0.5 ma 2.4 v low level output voltage v ol i ol = 1.0 ma 0.4 v remarks 1. v in : input voltage v i/o : input / output voltage 2. these dc characteristics are in common regardless of produc t specification. data sheet m14671ej9v0ds 8 pd442012a-x dc characteristics (recommended operating c onditions unless otherwise noted) (2/2) parameter symbol test condition pd442012a-bcxxx pd442012a-ddxxx unit min. typ. max. min. typ. max. input leakage current i li v in = 0 v to v cc ?1.0 +1.0 ?1.0 +1.0 a i/o leakage current i lo v i/o = 0 v to v cc , /ce1 = v ih or ?1.0 +1.0 ?1.0 +1.0 a ce2 = v il or /we = v il or /oe = v ih operating supply current i cca1 /ce1 = v il , ce2 = v ih , ? 30 ? ? ma i i/o = 0 ma, v cc 2.7 v ? 25 ? ? minimum cycle time v cc 2.2 v ? ? ? 15 i cca2 /ce1 = v il , ce2 = v ih , ? 4 ? ? i i/o = 0 ma, v cc 2.7 v ? 2 ? ? cycle time = v cc 2.2 v ? ? ? 1 i cca3 /ce1 0.2 v, ce2 v cc ? 0.2 v, ? 4 ? ? cycle time = 1 s, i i/o = 0 ma, v il 0.2 v, v cc 2.7 v ? 3 ? ? v ih v cc ? 0.2 v v cc 2.2 v ? ? ? 3 standby supply current i sb /ce1 = v ih or ce2 = v il or ? 0.6 ? ? ma /lb = /ub = v ih v cc 2.7 v ? 0.6 ? ? v cc 2.2 v ? ? ? 0.6 i sb1 /ce1 v cc ? 0.2 v, 0.3 4 ? ? a ce2 v cc ? 0.2 v v cc 2.7 v 0.25 3.5 ? ? v cc 2.2 v ? ? 0.2 3 i sb2 ce2 0.2 v 0.3 4 ? ? v cc 2.7 v 0.25 3.5 ? ? v cc 2.2 v ? ? 0.2 3 i sb3 /lb = /ub v cc ? 0.2 v, 0.3 4 ? ? /ce1 0.2 v, v cc 2.7 v 0.25 3.5 ? ? ce2 v cc ? 0.2 v v cc 2.2 v ? ? 0.2 3 high level output voltage v oh i oh = ?0.5 ma 2.4 ? v v cc 2.7 v 1.8 ? v cc 2.2 v ? 1.5 low level output voltage v ol i ol = 1.0 ma 0.4 ? v v cc 2.7 v 0.4 ? v cc 2.2 v ? 0.4 remarks 1. v in : input voltage v i/o : input / output voltage 2. these dc characteristics are in common regardless of produc t specification. data sheet m14671ej9v0ds 9 pd442012a-x ac characteristics (recommended operati ng conditions unless otherwise noted) ac test conditions [ pd442012a-bb55x, pd442012a-bb70x, pd442012a-bb85x ] input waveform (rise and fall time 5 ns) 0.1 v cc 0.9 v cc test points v cc /2 v cc /2 output waveform test points v cc /2 v cc /2 output load 1ttl + 50 pf [ pd442012a-bc70x, pd442012a-bc85x, pd442012a-bc10x ] input waveform (rise and fall time 5 ns) 0.1 v cc 0.9 v cc test points v cc /2 v cc /2 output waveform test points v cc /2 v cc /2 output load 1ttl + 30 pf [ pd442012a-dd85x, pd442012a-dd10x, pd442012a-dd12x ] input waveform (rise and fall time 5 ns) 0.1 v cc 0.9 v cc test points v cc /2 v cc /2 output waveform test points v cc /2 v cc /2 output load 1ttl + 30 pf data sheet m14671ej9v0ds 10 pd442012a-x read cycle (1/3) (bb version) parameter symbol pd442012a-bb55x pd442012a pd442012a unit condition v cc 3.0 v -bb70x -bb85x min. max. min. max. min. max. min. max. read cycle time t rc 50 55 70 85 ns address access time t aa 50 55 70 85 ns note 1 /ce1 access time t co1 50 55 70 85 ns ce2 access time t co2 50 55 70 85 ns /oe to output valid t oe 30 30 35 40 ns /lb, /ub to output valid t ba 50 55 70 85 ns output hold from address change t oh 10 10 10 10 ns /ce1 to output in low impedance t lz1 10 10 10 10 ns note 2 ce2 to output in low impedance t lz2 10 10 10 10 ns /oe to output in low impedance t olz 5 5 5 5 ns /lb, /ub to output in low impedance t blz 10 10 10 10 ns /ce1 to output in high impedance t hz1 20 20 25 30 ns ce2 to output in high impedance t hz2 20 20 25 30 ns /oe to output in high impedance t ohz 20 20 25 30 ns /lb, /ub to output in high impedance t bhz 20 20 25 30 ns notes 1. the output load is 1ttl + 50 pf. 2. the output load is 1ttl + 5 pf. read cycle (2/3) (bc version) parameter symbol pd442012a pd442012a pd442012a unit condition -bc70x -bc85x -bc10x min. max. min. max. min. max. read cycle time t rc 70 85 100 ns address access time t aa 70 85 100 ns note 1 /ce1 access time t co1 70 85 100 ns ce2 access time t co2 70 85 100 ns /oe to output valid t oe 35 40 50 ns /lb, /ub to output valid t ba 70 85 100 ns output hold from address change t oh 10 10 10 ns /ce1 to output in low impedance t lz1 10 10 10 ns note 2 ce2 to output in low impedance t lz2 10 10 10 ns /oe to output in low impedance t olz 5 5 5 ns /lb, /ub to output in low impedance t blz 10 10 10 ns /ce1 to output in high impedance t hz1 25 30 35 ns ce2 to output in high impedance t hz2 25 30 35 ns /oe to output in high impedance t ohz 25 30 35 ns /lb, /ub to output in high impedance t bhz 25 30 35 ns notes 1. the output load is 1ttl + 30 pf. 2. the output load is 1ttl + 5 pf. data sheet m14671ej9v0ds 11 pd442012a-x read cycle (3/3) (dd version) parameter symbol pd442012a pd442012a pd442012a unit condition -dd85x -dd10x -dd12x min. max. min. max. min. max. read cycle time t rc 85 100 120 ns address access time t aa 85 100 120 ns note 1 /ce1 access time t co1 85 100 120 ns ce2 access time t co2 85 100 120 ns /oe to output valid t oe 40 50 60 ns /lb, /ub to output valid t ba 85 100 120 ns output hold from address change t oh 10 10 10 ns /ce1 to output in low impedance t lz1 10 10 10 ns note 2 ce2 to output in low impedance t lz2 10 10 10 ns /oe to output in low impedance t olz 5 5 5 ns /lb, /ub to output in low impedance t blz 10 10 10 ns /ce1 to output in high impedance t hz1 30 35 40 ns ce2 to output in high impedance t hz2 30 35 40 ns /oe to output in high impedance t ohz 30 35 40 ns /lb, /ub to output in high impedance t bhz 30 35 40 ns notes 1. the output load is 1ttl + 30 pf. 2. the output load is 1ttl + 5 pf. read cycle timing chart t hz2 t rc t oh t hz1 t blz t ba t lz2 t co2 t lz1 t co1 t bhz t aa high impedance data out /lb, /ub (input) ce2 (input) /ce1 (input) address (input) i/o (output) t olz t oe t ohz /oe (input) remark in read cycle, /we should be fixed to high level. data sheet m14671ej9v0ds 12 pd442012a-x write cycle (1/3) (bb version) parameter symbol pd442012a-bb55x pd442012a pd442012a unit condition v cc 3.0 v -bb70x -bb85x min. max. min. max. min. max. min. max. write cycle time t wc 50 55 70 85 ns /ce1 to end of write t cw1 45 50 55 70 ns ce2 to end of write t cw2 45 50 55 70 ns /lb, /ub to end of write t bw 45 50 55 70 ns address valid to end of write t aw 45 50 55 70 ns address setup time t as 0 0 0 0 ns write pulse width t wp 40 45 50 55 ns write recovery time t wr 0 0 0 0 ns data valid to end of write t dw 25 25 30 35 ns data hold time t dh 0 0 0 0 ns /we to output in high impedance t whz 20 20 25 30 ns note output active from end of write t ow 5 5 5 5 ns note the output load is 1ttl + 5 pf. write cycle (2/3) (bc version) parameter symbol pd442012a pd442012a pd442012a unit condition -bc70x -bc85x -bc10x min. max. min. max. min. max. write cycle time t wc 70 85 100 ns /ce1 to end of write t cw1 55 70 80 ns ce2 to end of write t cw2 55 70 80 ns /lb, /ub to end of write t bw 55 70 80 ns address valid to end of write t aw 55 70 80 ns address setup time t as 0 0 0 ns write pulse width t wp 50 55 60 ns write recovery time t wr 0 0 0 ns data valid to end of write t dw 30 35 40 ns data hold time t dh 0 0 0 ns /we to output in high impedance t whz 25 30 35 ns note output active from end of write t ow 5 5 5 ns note the output load is 1ttl + 5 pf. data sheet m14671ej9v0ds 13 pd442012a-x write cycle (3/3) (dd version) parameter symbol pd442012a pd442012a pd442012a unit condition -dd85x -dd10x -dd12x min. max. min. max. min. max. write cycle time t wc 85 100 120 ns /ce1 to end of write t cw1 70 80 100 ns ce2 to end of write t cw2 70 80 100 ns /lb, /ub to end of write t bw 70 80 100 ns address valid to end of write t aw 70 80 100 ns address setup time t as 0 0 0 ns write pulse width t wp 55 60 85 ns write recovery time t wr 0 0 0 ns data valid to end of write t dw 35 40 60 ns data hold time t dh 0 0 0 ns /we to output in high impedance t whz 30 35 40 ns note output active from end of write t ow 5 5 5 ns note the output load is 1ttl + 5 pf. data sheet m14671ej9v0ds 14 pd442012a-x write cycle timing chart 1 (/we controlled) t wc t cw1 t bw t whz t dw t dh t ow indefinite data out high impe- dance high impe- dance data in indefinite data out address (input) /ce1 (input) /lb, /ub (input) i/o (input / output) ce2 (input) t cw2 t aw t wp t as t wr /we (input) cautions 1. during address transition, at least one of pins /ce1, ce2, /we should be inactivated. 2. do not input data to the i/o pins while they are in the output state. remarks 1. write operation is done during the ov erlap time of a low level /ce1, a low level /we, a low level /lb (or low level /ub) and a high level ce2. 2. if /ce1 changes to low level at the same time or after the change of /we to low level, or if ce2 changes to high level at the same time or after the change of /we to low level, the i/o pins will remain high impedance state. 3. when /we is at low level, t he i/o pins are always high impedance. when /we is at high level, read operation is executed. ther efore /oe should be at high level to make the i/o pins high impedance. data sheet m14671ej9v0ds 15 pd442012a-x write cycle timing chart 2 (/ce1 controlled) t wc t as t cw1 t dw t dh data in high impedance address (input) /ce1 (input) /lb, /ub (input) i/o (input) high impedance ce2 (input) t cw2 t aw t wp t wr /we (input) t bw cautions 1. during address transition, at least one of pins /ce1, ce2, /we should be inactivated. 2. do not input data to the i/o pins while they are in the output state. remark write operation is done during t he overlap time of a low level /ce1, a low level /we, a low level /lb (or low level /ub) and a high level ce2. data sheet m14671ej9v0ds 16 pd442012a-x write cycle timing chart 3 (ce2 controlled) t wc t as t cw2 t bw t dw t dh data in high impedance address (input) ce2 (input) /lb, /ub (input) i/o (input) high impedance /ce1 (input) t cw1 t aw t wp t wr /we (input) cautions 1. during address transition, at least one of pins /ce1, ce2, /we should be inactivated. 2. do not input data to the i/o pins while they are in the output state. remark write operation is done during t he overlap time of a low level /ce1, a low level /we, a low level /lb (or low level /ub) and a high level ce2. data sheet m14671ej9v0ds 17 pd442012a-x write cycle timing chart 4 (/lb, /ub controlled) t wc t dw t dh data in high impedance address (input) /lb, /ub (input) i/o (input) high impedance ce2 (input) t cw2 t aw t wp t wr /we (input) t as t bw /ce1 (input) t cw1 cautions 1. during address transition, at least one of pins /ce1, ce2, /we should be inactivated. 2. do not input data to the i/o pins while they are in the output state. remark write operation is done during t he overlap time of a low level /ce1, a low level /we, a low level /lb (or low level /ub) and a high level ce2. data sheet m14671ej9v0ds 18 pd442012a-x low v cc data retention characteristics (t a = ?25 to +85 c) parameter symbol test condition pd442012a pd442012a pd442012a unit -bbxxx -bcxxx -ddxxx min. typ. max. min. typ. max. min. typ. max. data retention v ccdr1 /ce1 v cc ? 0.2 v, 1.0 3.6 1.0 3.6 1.0 2.2 v supply voltage ce2 v cc ? 0.2 v v ccdr2 ce2 0.2 v 1.0 3.6 1.0 3.6 1.0 2.2 v ccdr3 /lb = /ub v cc ? 0.2 v, 1.0 3.6 1.0 3.6 1.0 2.2 /ce1 0.2 v, ce2 v cc ? 0.2 v data retention i ccdr1 v cc = 1.2 v, /ce1 v cc ? 0.2 v, 0.15 2 0.15 2 0.15 2 a supply current ce2 v cc ? 0.2 v i ccdr2 v cc = 1.2 v, ce2 0.2 v 0.15 2 0.15 2 0.15 2 i ccdr3 v cc = 1.2 v, /lb = /ub v cc ? 0.2 v, 0.15 2 0.15 2 0.15 2 /ce1 0.2 v, ce2 v cc ? 0.2 v chip deselection t cdr 0 0 0 ns to data retention mode operation t r t rc note t rc note t rc note ns recovery time note t rc : read cycle time data sheet m14671ej9v0ds 19 pd442012a-x data retention timing chart (1) /ce1 controlled v ih (min.) v ccdr (min.) v il (max.) /ce1 /ce1 v cc ? 0.2 v gnd v cc (min.) note t cdr data retention mode t r v cc note bb version : 2.7 v, bc version : 2.2 v, dd version : 1.8 v remark on the data retention mode by controlling /ce1, the input level of ce2 must be v cc ? 0.2 v or 0.2 v. the other pins (address, i/o, /we, /oe, /lb, /ub) can be in high impedance state. (2) ce2 controlled v ih (min.) v ccdr (min.) v il (max.) ce2 ce2 0.2 v gnd v cc (min.) note t cdr data retention mode t r v cc note bb version : 2.7 v, bc version : 2.2 v, dd version : 1.8 v remark on the data retention mode by controlling ce2, the other pins (/ce1, address, i/o, /we, /oe, /lb, /ub) can be in high impedance state. data sheet m14671ej9v0ds 20 pd442012a-x (3) /lb, /ub controlled t cdr data retention mode v ih (min.) v ccdr (min.) v il (max.) t r /lb, /ub /lb, /ub v cc ? 0.2 v gnd v cc (min.) note v cc note bb version : 2.7 v, bc version : 2.2 v, dd version : 1.8 v remark on the data retention mode by c ontrolling /lb and /ub, the input le vel of /ce1 and ce2 must be v cc ? 0.2 v or 0.2 v. the other pins (address, i/o, /we, /oe) can be in high impedance state. data sheet m14671ej9v0ds 21 pd442012a-x package drawing notes 48-pin plastic tsop( i ) (12x18) item millimeters a b c e i 12.0 + ? s48gy-50-mjh1-1 s 0.60 data sheet m14671ej9v0ds 22 pd442012a-x recommended soldering conditions please consult with our sales offices for soldering conditions of the pd442012a-x. types of surface mount device pd442012agy-bbxxx-mjh : 48-pin plastic tsop (i) (12 18) (normal bent) pd442012agy-bcxxx-mjh : 48-pin plastic tsop (i) (12 18) (normal bent) pd442012agy-ddxxx-mjh : 48-pin plastic tsop (i) (12 18) (normal bent) pd442012agy-bbxxx-mjh-a : 48-pin plastic tsop (i) (12 18) (normal bent) pd442012agy-bcxxx-mjh-a : 48-pin plastic tsop (i) (12 18) (normal bent) pd442012agy-ddxxx-mjh-a : 48-pin plastic tsop (i) (12 18) (normal bent) quality grade ? a quality grade of the products is ?standard?. ? anti-radioactive design is not implemented in the products. ? semiconductor devices have the possibilit y of unexpected defects by affection of cosmic ray that reach to the ground and so forth. data sheet m14671ej9v0ds 23 pd442012a-x revision history edition/ page type of location description date this previous revision (previous edition this edition) edition edition 9th edition/ p.22 p.22 addition quality grade section of quality grade has been added. sep. 2006 data sheet m14671ej9v0ds 24 pd442012a-x [ memo ] data sheet m14671ej9v0ds 25 pd442012a-x [ memo ] data sheet m14671ej9v0ds 26 pd442012a-x [ memo ] data sheet m14671ej9v0ds 27 pd442012a-x 1 2 3 4 voltage application waveform at input pin waveform distortion due to input noise or a reflected wave may cause malfunction. if the input of the cmos device stays in the area between v il (max) and v ih (min) due to noise, etc., the device may malfunction. take care to prevent chattering noise from entering the device when the input level is fixed, and also in the transition period when the input level passes through the area between v il (max) and v ih (min). handling of unused input pins unconnected cmos device inputs can be cause of malfunction. if an input pin is unconnected, it is possible that an internal input level may be generated due to noise, etc., causing malfunction. cmos devices behave differently than bipolar or nmos devices. input levels of cmos devices must be fixed high or low by using pull-up or pull-down circuitry. each unused pin should be connected to v dd or gnd via a resistor if there is a possibility that it will be an output pin. all handling related to unused pins must be judged separately for each device and according to related specifications governing the device. precaution against esd a strong electric field, when exposed to a mos device, can cause destruction of the gate oxide and ultimately degrade the device operation. steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it when it has occurred. environmental control must be adequate. when it is dry, a humidifier should be used. it is recommended to avoid using insulators that easily build up static electricity. semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. all test and measurement tools including work benches and floors should be grounded. the operator should be grounded using a wrist strap. semiconductor devices must not be touched with bare hands. similar precautions need to be taken for pw boards with mounted semiconductor devices. status before initialization power-on does not necessarily define the initial status of a mos device. immediately after the power source is turned on, devices with reset functions have not yet been initialized. hence, power-on does not guarantee output pin levels, i/o settings or contents of registers. a device is not initialized until the reset signal is received. a reset operation must be executed immediately after power-on for devices with reset functions. power on/off sequence in the case of a device that uses different power supplies for the internal operation and external interface, as a rule, switch on the external power supply after switching on the internal power supply. when switching the power supply off, as a rule, switch off the external power supply and then the internal power supply. use of the reverse power on/off sequences may result in the application of an overvoltage to the internal elements of the device, causing malfunction and degradation of internal elements due to the passage of an abnormal current. the correct power on/off sequence must be judged separately for each device and according to related specifications governing the device. input of signal during power off state do not input signals or an i/o pull-up power supply while the device is not powered. the current injection that results from input of such a signal or i/o pull-up power supply may cause malfunction and the abnormal current that passes in the device at this time may cause degradation of internal elements. input of signals during the power off state must be judged separately for each device and according to related specifications governing the device. notes for cmos devices 5 6 pd442012a-x the information in this document is current as of september, 2006. the information is subject to change without notice. for actual design-in, refer to the latest publications of nec electronics data sheets or data books, etc., for the most up-to-date specifications of nec electronics products. not all products and/or types are available in every country. please check with an nec electronics sales representative for availability and additional information. no part of this document may be copied or reproduced in any form or by any means without the prior written consent of nec electronics. nec electronics assumes no responsibility for any errors that may appear in this document. nec electronics does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of nec electronics products listed in this document or any other liability arising from the use of such products. no license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of nec electronics or others. descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. the incorporation of these circuits, software and information in the design of a customer's equipment shall be done under the full responsibility of the customer. nec electronics assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. while nec electronics endeavors to enhance the quality, reliability and safety of nec electronics products, customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. to minimize risks of damage to property or injury (including death) to persons arising from defects in nec electronics products, customers must incorporate sufficient safety measures in their design, such as redundancy, fire-containment and anti-failure features. nec electronics products are classified into the following three quality grades: "standard", "special" and "specific". the "specific" quality grade applies only to nec electronics products developed based on a customer- designated "quality assurance program" for a specific application. the recommended applications of an nec electronics product depend on its quality grade, as indicated below. customers must check the quality grade of each nec electronics product before using it in a particular application. "standard": computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots. "special": transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support). "specific": aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems and medical equipment for life support, etc. the quality grade of nec electronics products is "standard" unless otherwise expressly specified in nec electronics data sheets or data books, etc. if customers wish to use nec electronics products in applications not intended by nec electronics, they must contact an nec electronics sales representative in advance to determine nec electronics' willingness to support a given application. (note) (1) "nec electronics" as used in this statement means nec electronics corporation and also includes its majority-owned subsidiaries. (2) "nec electronics products" means any product developed or manufactured by or for nec electronics (as defined above). ? ? ? ? ? ? m8e 02. 11-1 |
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