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ds04132033ae data sheet 1 copyright ? 1995 by fujitsu limited quick pro tm is a trademark of fujitsu limited linear ic cmos 8 bit 4-channel d/a converter mb86023 d0 d1 d2 d3 d4 d5 d6 d7 c0 c1 wr ce cmos 8-bit 4-channel d/a converter the fujitsu mb86023 is a 8-bit 4-channel digital to analog converter which is fabricated with fujitsu cmos technology. the data latch and output buffer circuitry are provided on each channel which can operate independently selected by 2bit data. ? resolution : 8-bits (4-channels) ? conversion rate : 500k sps ? digital input voltage : ttl level ? power supply voltage : 5v ? low power dissipation : 80mw typ. at 5v ? each channel operates independently ? on-chip data initialization & power down function ? reference voltage mode selection: on-chip or external generation ? easy to take interface with micro processor (parallel data input) plastic package dip-24p-m03 this device contains circuitry to protect the inputs against damage due to high static voltages or electric fields. however, it is advised that normal precautions be taken to avoid application of any voltage higher than maximum rated voltages to this high impedance circuit. plastic package fpt-24p-m02 pin assignment (top view) reset pd v dd nc vr ao0 ao1 ao2 ao3 v ss ag dg 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13
mb86023 2 absolute maximum ratings (see note) note: permanent device damage may occur if the above absolute maximum ratings are exceeded. functional operation should be restricted to the conditions as detailed in the operational sections of this data sheet. exposure to absolute maximum rating conditions for extended periods may affect device reliability. rating power supply voltage1 symbol pin name unit digital input voltage v v v dd v ss v di max 7 typ min power supply voltage2 analog input voltage v ai analog output voltage v ao pin current 10 power supply current i to i po storage temperature 125 tstg c (except power supply pin) v v v ma ma v dd +0.3 v dd +0.3 v dd +0.3 gnd+0.3 30 gnd0.3 10 40 7 30 v ss 0.3 v ss 0.3 gnd0.3 v dd v ss all digital input pins vr ao0,ao1,ao2,ao3 except v dd , v ss pin v dd , v ss parameter
mb86023 3 block diagram ao3 ao2 ao1 ao0 d0 to d7 ___ c0,c1 vr ___ ______ ___ 2 8 buffer amp. buffer amp. buffer amp. buffer amp. + + + + 8-bit pd reset ce wr dac 8-bit dac 8-bit dac 8-bit dac 8-bit data channel v ref circuit latch 8-bit data latch 8-bit data latch 8-bit data latch select & control logic dg ag v dd v ss
mb86023 4 pin description reference voltage (h level) input pin. v dd is given by internal reference voltage cir- cuitry to this pin when internal reference voltage mode. in this case, the capacitor be- tween this pin and ag pin is required to limit noise generation. in case of external refer- ence voltage mode, the reference voltage should be given from this pin. system pin number symbol descriptions 22 v dd power supply voltage 5v 15 v ss 13 dg 14 ag 9 10 1 2 c0 c1 d0 d1 3 4 5 6 d2 d3 d4 d5 7 8 d6 d7 power supply voltage 5v gnd for digital system gnd for analog system channel selection signal pin. channels are selected by following table. ttl interface. data input signal pin. the digital data is read by the channel which is selected by c0 and c1 pin when the rising edge of wr (l h), and analog output is shown correspond to that digital code. d0 is lsb and d7 is msb. code is set at 10000000 when reset. ttl interface. 23 ___ pd power down control signal pin. the circuit is set power down when this pin goes to alo. this pin is pulled up by high resistance. ttl interface. 24 ______ reset reset input signal pin. the data at all channels is initialized when this pin goes to alo. at this time, the d/a output is set at d(a)=128. this pin is pulled up by high resistance. ttl interface. 12 ___ ce chip enable signal pin. the data can be written when this pin goes to alo. this pin is pulled up by high resistance. ttl interface. 11 ___ wr data write pin. the data from d0 to d7 is written when the rising edge (l h) of this pin. ttl interface. c1 c0 channel ll 0 lh 1 hl 2 hh 3 power supply digital input 16 ao3 analog output pin of channel 3. this pin is set to highimpedance state at power down. 17 ao2 analog output pin of channel 2. this pin is set to highimpedance state at power down. 18 ao1 analog output pin of channel 1. this pin is set to highimpedance state at power down. 19 ao0 analog output pin of channel 0. this pin is set to highimpedance state at power down. 20 vr 21 n. c non connection pin 1 ___ 2 analog input analog output
mb86023 5 recommended operating conditions unit value v v dd parameter symbol pin name min typ max 4.75 5.0 5.25 power supply voltage1 v 5.25 5.0 4.75 power supply voltage2 v ss v 0 digital input voltage all digital input pins analog input voltage v 3.0 2.5 3.0 ma 1 1 analog output load analog output load pf 30 20 70 operating temperature vr ao0, ao1, ao2, ao3 current capacitance c v dd v dd v ss v di v 1 i al c al ta
mb86023 6 electrical characteristics (v dd =4.75v to 5.25v, v ss =5.25v to 4.75v, ta=20 c to 70 c) load unit value parameter symbol pin name min typ max conditions 816 m a v dd power supply power supply digital pull up current ___ digital input alo width data set up time 1 wr aho width ___ wr alo width data set up time 2 ___ ce set up time data hold time 1 data hold time 2 ___ ce hold time input v ss no pd=aho pd=alo pd=aho pd=alo v di =gnd v di =v dd v di =gnd ref. to timing chart 0.5 16 8 0.5 0 0.8 2.2 10 10 10 10 100 50 25 200 200 500 200 200 0 50 50 0 m a m a ma ma ma ma v v ns ns ns ns ns ns ns ns ns v dd all digital input pins d0 to d7, wr pd, ce, reset wr wr reset, pd d0 to d7, wr c0, c1, wr ce, wr d0 to d7, wr c0, c1, wr ce, wr ___ ______ ___ ___ ___ ___ ______ ___ ___ ___ ___ ___ ___ ___ ___ ___ current 1 currrent 2 ref. to timing chart ref. to timing chart ref. to timing chart ref. to timing chart ref. to timing chart ref. to timing chart ref. to timing chart ref. to timing chart alo voltage aho voltage alo current aho current i dd1 i dd2 i ss1 i ss2 v il v ih i il i ih i plu t whwr t wlwr t wlrp t sd1 t sd2 t sce t hd1 t hd2 t hce
mb86023 7 unit value parameter symbol min typ max conditions rising time 1 0 wr ___ ref. to timing chart 50 ns falling time 1 0 wr ___ 50 ns ref. to timing chart rising time 2 ref. to timing chart 0 50 ns falling time 2 0 50 ns ref. to timing chart resolution 8 bits analog output min. voltage analog output max. voltage code input no external vr input d(a)= 0 code input d(a)= 255 vr=open no external vr input vr=open (typ.) 0.1 v v (typ.) 0.1 (typ)+0.1 (typ)+0.1 analog 30 50 200 vr k w linearity error 1.5 1.5 no external vr input vr=open differential 1 1 lsb lsb setting time 2 full scale change (ref. to timing chart) m s linearity error analog input resistance analog output rising time falling time 1.5 m s input code d(a)=255 vr= 2 square wave input (ref. to timing chart) ____ 512 255 x v dd ____ 512 x v dd ao0, ao1, ao2, ao3 ao0, ao1, ao2, ao3 d0 to d7, c0, ___ ___ ______ c1, ce, reset, pd d0 to d7, c0, ___ ___ ______ c1, ce, reset, pd 255 pin name t r1 t f1 t r2 t f2 res v aol v aoh r in le d le t s t r t f (continued) (v dd =4.75v to 5.25v, v ss =5.25v to 4.75v, ta=20 c to 70 c)
mb86023 8 function description truth table ___ 0 ______ x ___ x ___ x pd reset ce wr 1 0 x x 1 1 1 x 1 1 0 c0, c1 d0 to d7 function power down initialization no analog output change channel selection no data input analog output change data input d0 to d7 c0, c1 ___ ce ___ wr data is read. analog output is changed. data is not read. analog output is not changed. fig. 1 data set timing diagram
mb86023 9 setting of analog output voltage d(a) 255 d7 1 d6 1 d5 1 d4 1 d3 1 d2 1 d1 1 d0 1 data analog output voltage 254 1 1 1 1 1 1 1 0 253 1 1 1 1 1 1 0 1 129 1 0 0 0 0 0 0 1 128 1 0 0 0 0 0 0 0 127 0 1 1 1 1 1 1 1 126 0 1 1 1 1 1 1 0 2 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1lsb ____ 512 3 ____ 512 1 ____ 512 1 ____ 512 251 ____ 512 253 ____ 512 255 ____ 512 251 ____ 512 3 ____ 512 x (2d (a) 255) ____ 256 1 v r open (no external input) vr=v 1 (external input) v dd ____ 512 253 ____ 512 255 ____ 256 255 x v 1 ____ 256 253 ____ 256 251 ____ 256 x (2d (a) 255) v 1 ____ 256 3 ____ 256 1 ____ 256 1 ____ 256 3 ____ 256 251 ____ 256 253 ____ 256 255 ____ 128 1 * code is set at o10000000o when reset mode. ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? x v dd x v dd x v dd x v dd x v dd x v dd x v dd x v dd x v dd x v dd x v dd x v 1 x v 1 x v 1 x v 1 x v 1 x v 1 x v 1 x v 1 x v 1 x v 1
mb86023 10 analog output voltage range v dd v ss ____ 512 255 x v dd v aoh lsb v aol d/a output range __ 2 1 x v dd ag __ 2 1 x v dd __ 2 1 ____ 512 1 x v dd ____ 512 255 x v dd fig. 2 on-chip reference voltage mode (vr=v 1 ) v dd v ss ____ 256 255 v 1 v aol lsb v aol d/a output range ag v 1 __ 2 1 ____ 256 1 x v 1 ____ 256 255 v 1 (vr1) v 1 fig. 3 external reference voltage mode
mb86023 11 typical application circuit for each mode (vr open) 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 ______ reset ___ pd d0 to d7 ___ ce ___ wr c1 c0 ao0 to 3 +5v (v dd ) 5v (v ss ) + 1 m f fig. 4 on-chip reference voltage mode (vr=v 1 ) 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 ______ reset ___ pd d0 to d7 ___ ce ___ wr c1 c0 ao0 to 3 +5v (v dd ) v 1 5v (v ss ) fig. 5 external reference voltage mode
mb86023 12 timing diagram 2.0v 2.0v 1.9v 2.0v t r t f vr ao0 to ao3 1.9v t r1 v ih v il v ih v il v ih v il v ih v il v ih v il t f1 t r2 t f2 t r2 t f2 t whwr t wlwr t sd1 t hd1 t sd2 t hd2 t f2 t r2 t sce t hce 1lsb 1lsb t s t wlrp ___ wr ___ ce ______ reset, pd ___ ao0 to ao3 d0 to d7 c0, c1 v aoh v aol
mb86023 13 package dimensions dimensions in inches (millimeters) 24-lead plastic dual in-line package (case no.: dip-24p-m03) ? 1991 fujitsu limited d24017s-3c 1.170 +.008 .012 (29.72 ) +0.20 0.30 .034 +.020 0 (0.86 ) +0.50 0 .260 .010 (6.60 0.25) index-1 .020(0.51)min .172(4.36)max .118(3.00)min .300(7.62) typ 15 max .050 +.020 0 (1.27 ) +0.50 0 index-2 .050(1.27) max .100(2.54) typ .010 .002 (0.25 0.05) .018 .003 (0.46 0.08)
mb86023 14 dimensions in inches (millimeters) 24-lead plastic flat package (case no.: fpt-24p-m02) ? 1991 fujitsu limited f24008s-4c .004(0.10) ? .005(0.13) m .402 .016 (10.20 0.40) .299 .012 (7.60 0.30) .050(1.27) typ aao .018 .004 (0.45 0.10) .110(2.80) max (mounting height) .002(0.05) min (stand off height) .362 .012 (9.20 0.30) .020 .008 (0.50 0.20) +.002 .001 +0.05 0.02 .006 (0.15 ) details of aao part .008(0.20) .024(0.60) .007(0.18) max .027(0.68) max .600 index .550(13.97) ref (15.24 ) +0.25 0.20 +.010 .008 all rights reserved. circuit diagrams utilizing fujitsu products are included as a means of illustrating typical semiconductor applications. complete information sufficient for construction purposes is not necessarily given. the information contained in this document has been carefully checked and is believed to be reliable. however, fujitsu assumes no responsibility for inaccuracies. the information contained in this document does not convey any license under the copyrights, patent rights or trademarks claimed and owned by fujitsu. fujitsu reserves the right to change products or specifications without notice. no part of this publication may be copied or reproduced in any form or by any means, or transferred to any third party without prior written consent of fujitsu.

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