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preliminary: the specification of this device are subject to change without notice. please contact your nearest hitachi? sales dept. regarding specification. hb52e648en-a6b/b6b, hb52e649en-a6b/b6b 512 mb unbuffered sdram dimm, 100 mhz memory bus (hb52e648en) 64-mword 64-bit, 2-bank module (16 pcs of 32 m 8 components) (hb52e649en) 64-mword 72-bit, 2-bank module (18 pcs of 32 m 8 components) pc100 sdram ade-203-1116a (z) preliminary rev. 0.1 nov. 29, 1999 description the hb52e648en, hb52e649en belong to 8-byte dimm (dual in-line memory module) family, and have been developed as an optimized main memory solution for 8-byte processor applications. they are synchronous dynamic ram module, mounted 256-mbit sdrams (hm5225805btt) sealed in tsop package, and 1 piece of serial eeprom (2-kbit eeprom) for presence detect (pd). the hb52e648en is organized 32m 64 2-bank mounted 16 pieces of 256-mbit sdram. the hb52e649en is organized 32m 72 2-bank mounted 18 pieces of 256-mbit sdram. an outline of the products is 168-pin socket type package (dual lead out). therefore, they make high density mounting possible without surface mount technology. they provide common data inputs and outputs. decoupling capacitors are mounted beside each tsop on the module board. features fully compatible with : jedec standard outline 8-byte dimm : intel pcb reference design (rev. 1.0) 168-pin socket type package (dual lead out) ? outline: 133.37 mm (length) 34.925 mm (height) 4.00 mm (thickness) ? lead pitch: 1.27 mm 3.3 v power supply clock frequency: 100 mhz (max) lvttl interface
hb52e648en/hb52e649en-a6b/b6b 2 data bus width : 64 non parity (hb52e648en) : 72 ecc (hb52e649en) single pulsed ras 4 banks can operates simultaneously and independently burst read/write operation and burst read/single write operation capability programmable burst length: 1/2/4/8 2 variations of burst sequence ? sequential ? interleave programmable ce latency : 2/3 (hb52e648en/52e649en-a6b) : 3 (hb52e648en/52e649en-b6b) byte control by dqmb refresh cycles: 8192 refresh cycles/64 ms 2 variations of refresh ? auto refresh ? self refresh ordering information type no. frequency ce latency package contact pad hb52e648en- a6b hb52e648en- b6b 100 mhz 100 mhz 2/ 3 3 168- pin dual le ad ou t soc ket ty pe gol d hb52e649en- a6b hb52e649en- b6b 100 mhz 100 mhz 2/ 3 3 pin arrangement 1 pin 10 pin 11 pin 40 pin 41 pin 84 pin 85 pin 94 pin 95 pin 124 pin 125 pin 168 pin
hb52e648en/hb52e649en-a6b/b6b 3 (hb52e648en) pin no. pin name pin no. pin name pin no. pin name pin no. pin name 1v ss 43 v ss 85 v ss 127 v ss 2 dq0 44 nc 86 dq32 128 cke0 3 dq1 45 s2 87 dq33 129 nc ( s3 ) * 2 4 dq2 46 dqmb2 88 dq34 130 dqmb6 5 dq3 47 dqmb3 89 dq35 131 dqmb7 6v c c 48 nc 90 v c c 132 nc 7 dq4 49 v c c 91 dq36 133 v c c 8 dq5 50 nc 92 dq37 134 nc 9 dq6 51 nc 93 dq38 135 nc 10 dq7 52 nc 94 dq39 136 nc 11 dq8 53 nc 95 dq40 137 nc 12 v ss 54 v ss 96 v ss 138 v ss 13 dq9 55 dq16 97 dq41 139 dq48 14 dq10 56 dq17 98 dq42 140 dq49 15 dq11 57 dq18 99 dq43 141 dq50 16 dq12 58 dq19 100 dq44 142 dq51 17 dq13 59 v c c 101 dq45 143 v c c 18 v c c 60 dq20 102 v c c 144 dq52 19 dq14 61 nc 103 dq46 145 nc 20 dq15 62 nc 104 dq47 146 nc 21 nc 63 nc ( cke1)* 1 105 nc 147 nc 22 nc 64 v ss 106 nc 148 v ss 23 v ss 65 dq21 107 v ss 149 dq53 24 nc 66 dq22 108 nc 150 dq54 25 nc 67 dq23 109 nc 151 dq55
hb52e648en/hb52e649en-a6b/b6b 4 pin no. pin name pin no. pin name pin no. pin name pin no. pin name 26 v c c 68 v ss 110 v c c 152 v ss 27 w 69 dq24 111 ce 153 dq56 28 dqmb0 70 dq25 112 dqmb4 154 dq57 29 dqmb1 71 dq26 113 dqmb5 155 dq58 30 s0 72 dq27 114 nc ( s1 ) * 3 156 dq59 31 nc 73 v c c 115 re 157 v c c 32 v ss 74 dq28 116 v ss 158 dq60 33 a0 75 dq29 117 a1 159 dq61 34 a2 76 dq30 118 a3 160 dq62 35 a4 77 dq31 119 a5 161 dq63 36 a6 78 v ss 120 a7 162 v ss 37 a8 79 ck2 121 a9 163 ck3 38 a10 (ap) 80 nc 122 ba0 164 nc 39 ba1 81 wp 123 a11 165 sa0 40 v c c 82 sda 124 v c c 166 sa1 41 v c c 83 scl 125 ck1 167 sa2 42 ck0 84 v c c 126 a12 168 v c c not es : 1. cke1: hb52e648en 2. s3 : hb52e648en 3. s1 : hb52e648en
hb52e648en/hb52e649en-a6b/b6b 5 (hb52e649en) pin no. pin name pin no. pin name pin no. pin name pin no. pin name 1v ss 43 v ss 85 v ss 127 v ss 2 dq0 44 nc 86 dq32 128 cke0 3 dq1 45 s2 87 dq33 129 nc ( s3 ) * 2 4 dq2 46 dqmb2 88 dq34 130 dqmb6 5 dq3 47 dqmb3 89 dq35 131 dqmb7 6v c c 48 nc 90 v c c 132 nc 7 dq4 49 v c c 91 dq36 133 v c c 8 dq5 50 nc 92 dq37 134 nc 9 dq6 51 nc 93 dq38 135 nc 10 dq7 52 cb2 94 dq39 136 cb6 11 dq8 53 cb3 95 dq40 137 cb7 12 v ss 54 v ss 96 v ss 138 v ss 13 dq9 55 dq16 97 dq41 139 dq48 14 dq10 56 dq17 98 dq42 140 dq49 15 dq11 57 dq18 99 dq43 141 dq50 16 dq12 58 dq19 100 dq44 142 dq51 17 dq13 59 v c c 101 dq45 143 v c c 18 v c c 60 dq20 102 v c c 144 dq52 19 dq14 61 nc 103 dq46 145 nc 20 dq15 62 nc 104 dq47 146 nc 21 cb0 63 nc ( cke1)* 1 105 cb4 147 nc 22 cb1 64 v ss 106 cb5 148 v ss 23 v ss 65 dq21 107 v ss 149 dq53 24 nc 66 dq22 108 nc 150 dq54 25 nc 67 dq23 109 nc 151 dq55 26 v c c 68 v ss 110 v c c 152 v ss 27 w 69 dq24 111 ce 153 dq56 28 dqmb0 70 dq25 112 dqmb4 154 dq57 29 dqmb1 71 dq26 113 dqmb5 155 dq58 30 s0 72 dq27 114 nc ( s1 ) * 3 156 dq59 31 nc 73 v c c 115 re 157 v c c 32 v ss 74 dq28 116 v ss 158 dq60 33 a0 75 dq29 117 a1 159 dq61
hb52e648en/hb52e649en-a6b/b6b 6 pin no. pin name pin no. pin name pin no. pin name pin no. pin name 34 a2 76 dq30 118 a3 160 dq62 35 a4 77 dq31 119 a5 161 dq63 36 a6 78 v ss 120 a7 162 v ss 37 a8 79 ck2 121 a9 163 ck3 38 a10 (ap) 80 nc 122 ba0 164 nc 39 ba1 81 wp 123 a11 165 sa0 40 v c c 82 sda 124 v c c 166 sa1 41 v c c 83 scl 125 ck1 167 sa2 42 ck0 84 v c c 126 a12 168 v c c not es : 1. cke1: hb52e649en 2. s3 : hb52e649en 3. s1 : hb52e649en pin description (hb52e648en) pin name function a0 toa12 addr ess input ? row address a0 to a12 ? column address a0 to a9 ba0/ ba1 bank sel ec t addres s dq0 to dq63 dat a input / out put s0 to s3 chi p sel ec t input re row enabl e (ras) input ce col umn enabl e (cas) input w wr i t e enabl e input dqmb0 t o dqmb7 by t e dat a mas k ck0 to ck3 cl oc k i nput cke0, cke1 cl oc k enabl e input wp wr i t e pr ot ec t for ser i al pd sda dat a input / out put for ser ial pd scl cl oc k i nput for s er i al pd sa0 to sa2 ser i al addr es s input v c c pr i mary po s i t i v e po we r suppl y v ss gr ound nc no connec t i on
hb52e648en/hb52e649en-a6b/b6b 7 pin description (hb52e649en) pin name function a0 toa12 addr ess input ? row address a0 to a12 ? column address a0 to a9 ba0/ ba1 bank sel ec t addres s dq0 to dq63 dat a input / out put cb0 to cb7 chec k bi t (dat a i nput / out pu t ) s0 to s3 chi p sel ec t input re row enabl e (ras) input ce col umn enabl e (cas) input w wr i t e enabl e input dqmb0 t o dqmb7 by t e dat a mas k ck0 to ck3 cl oc k i nput cke0, cke1 cl oc k enabl e input wp wr i t e pr ot ec t for ser i al pd sda dat a input / out put for ser ial pd scl cl oc k i nput for s er i al pd sa0 to sa2 ser i al addr es s input v c c pr i mary po s i t i v e po we r suppl y v ss gr ound nc no connec t i on
hb52e648en/hb52e649en-a6b/b6b 8 serial pd matrix * 1 byte no. function described bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 hex value comments 0 number of bytes used by module manufacturer 1000000080 128 1 total spd memory size 0000100008 256 byte 2 memory type 0000010004 sdram 3 number of row addresses bits 000011010d 13 4 number of column addresses bits 000010100a 10 5 number of banks 0000001002 2 6 module data width (hb52e648en) 0100000040 64 (hb52e649en) 0100100048 72 7 module data width (continued) 0000000000 0 (+) 8 module interface signal levels 0000000101 lvttl 9 sdram cycle time (highest ce latency) 10 ns 10100000a0 cl = 3 10 sdram access from clock (highest ce latency) 6 ns 0110000060 11 module configuration type (hb52e648en) 0000000000 non parity (hb52e649en) 0000001002 ecc 12 refresh rate/type 1000001082 normal (7.8125 m s) self refresh 13 sdram width 0000100008 32m 8 14 error checking sdram width (hb52e648en) 0000000000 (hb52e649en) 0000100008 8 15 sdram device attributes: minimum clock delay for back-to-back random column addresses 0000000101 1 clk 16 sdram device attributes: burst lengths supported 000011110f 1, 2, 4, 8
hb52e648en/hb52e649en-a6b/b6b 9 byte no. function described bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 hex value comments 17 sdram device attributes: number of banks on sdram device 0000010004 4 18 sdram device attributes: ce latency 0000011006 2, 3 19 sdram device attributes: s latency 0000000101 0 20 sdram device attributes: w latency 0000000101 0 21 sdram module attributes 0000000000 non buffer 22 sdram device attributes: general 000011100e v cc 10% 23 sdram cycle time (2nd highest ce latency) (-a6b) 10 ns 10100000a0 cl = 2 sdram cycle time (2nd highest ce latency) (-b6b) 15 ns 11110000f0 24 sdram access from clock (2nd highest ce latency) (-a6b) 6 ns 0110000060 cl = 2 sdram access from clock (2nd highest ce latency) (-b6b) 9 ns 1001000090 25 sdram cycle time (3rd highest ce latency) undefined 0000000000 26 sdram access from clock (3rd highest ce latency) undefined 0000000000 27 minimum row precharge time 0001010014 20 ns 28 row active to row active min 0001010014 20 ns 29 re to ce delay min 0001010014 20 ns 30 minimum re pulse width 0011001032 50 ns 31 density of each bank on module 0100000040 2 bank 256 m byte 32 address and command signal input setup time 0010000020 2.0 ns 33 address and command signal input hold time 0001000010 1.0 ns 34 data signal input setup time 0010000020 2.0 ns
hb52e648en/hb52e649en-a6b/b6b 10 byte no. function described bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 hex value comments 35 data signal input hold time 0001000010 1.0 ns 36 to 61 superset information 0000000000 future use 62 spd data revision code 0001001012 rev.1.2a 63 checksum for bytes 0 to 62 (hb52e648en-a6b) 10111010ba 186 (hb52e648en-b6b) 001110103a 58 (hb52e649en-a6b) 11001100cc 204 (HB52E649EN-B6B) 010011004c 76 64 manufacturer? jedec id code 0000011107 hitachi 65 to 71 manufacturer? jedec id code 0000000000 72 manufacturing location * 3 (ascii- 8bit code) 73 manufacturer? part number 0100100048 h 74 manufacturer? part number 0100001042 b 75 manufacturer? part number 0011010135 5 76 manufacturer? part number 0011001032 2 77 manufacturer? part number 0100010145 e 78 manufacturer? part number 0011011036 6 79 manufacturer? part number 0011010034 4 80 manufacturer? part number (hb52e648en) 0011100038 8 (hb52e649en) 0011100139 9 81 manuf ac t ur er ? s par t number0100010145 e 82 manuf ac t ur er ? s par t number010011104e n 83 manuf ac t ur er ? s par t number001011012d 84 manuf ac tur er ? pa rt number ( hb52e648en/ 649en- a6b) 0100000141 a ( hb52e648en/ 649en- b6b) 0100001042 b 85 manuf ac t ur er ? s par t number0011011036 6 86 manuf ac t ur er ? s par t number0100001042 b 87 manuf ac t ur er ? s par t number0010000020 ( spac e) 88 manuf ac t ur er ? s par t number0010000020 ( spac e)
hb52e648en/hb52e649en-a6b/b6b 11 byte no. function described bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 hex value comments 89 manuf ac t ur er ? s par t number0010000020 ( spac e) 90 manuf ac t ur er ? s par t number0010000020 ( spac e) 91 rev i s ion code 0011000030 i ni t i al 92 rev i s ion code 0010000020 ( spac e) 93 manuf ac t ur i ng dat e year code ( bcd) * 4 94 manuf ac t ur i ng dat e week code ( bcd) * 4 95 to 98 as s embl y ser i al number * 6 99 to 125 manuf ac t ur er spec i f i c da t a * 5 126 i nt el s pec i f i c ati on fr equenc y 0110010064 100 mhz 127 i nt el s pec i fi c ati on ce # l at en c y s upport (hb52e648en/ 649en- a6b) 11111111ff cl = 2, 3 (hb52e648en/ 649en- b6b) 11111101fd cl = 3 notes: 1. all serial pd data are not protected. 0: serial data, ?riven low? 1: serial data, ?riven high these spd are based on intel specification (rev.1.2a). 2. regarding byte32 to 35, based on jedec committee ballot jc42.5-97-119. 3. byte72 is manufacturing location code. (ex: in case of japan, byte72 is 4ah. 4ah shows ??on ascii code.) 4. regarding byte93 and 94, based on jedec committee ballot jc42.5-97-135. bcd is ?inary coded decimal? 5. all bits of 99 through 125 are not defined (??or ??. 6. bytes 95 through 98 are assembly serial number.
hb52e648en/hb52e649en-a6b/b6b 12 block diagram (hb52e648en) dqmb0 d1 i/o0 to i/o7 i/o0 to i/o7 dqm dqm dq0 to dq7 dq8 to dq15 dqmb1 * d0 to d15: hm5225805 u0: 2-kbit eeprom c0 to c15: 0.33 f, c16 to c31: 0.10 f r0: 10 k w , r1: 47 k w n0 to n15: network registor 10 w r100 to r103: 10 w cke (d8 to d15) serial pd sda wp r1 a0 a1 a2 sa0 sa1 sa2 v ss cke1 cke (d0 to d7) cke0 scl u0 sda scl notes : 1. the sda pull-up resistor is required due to the open-drain/open-collector output. 2. the scl pull-up resistor is recommended because of the normal scl line inacitve r0 8 n0, n1 n2, n3 n4, n5 n6, n7 n8, n9 n10, n11 n12, n13 n14, n15 8 dqmb4 dq32 to dq39 dq40 to dq47 dqmb5 8 8 v cc (d0 to d15, u0) v ss (d0 to d15, u0) v ss v cc v cc c16 to c31 c0 to c15 re , ce , w cs cs d5 d4 d0 i/o0 to i/o7 i/o0 to i/o7 dqm dqm cs cs s1 s2 "high" state. dqmb2 d3 i/o0 to i/o7 i/o0 to i/o7 dqm dqm dq16 to dq23 dq24 to dq31 dqmb3 8 8 dqmb6 dq48 to dq55 dq56 to dq63 dqmb7 8 8 cs cs d7 d6 d2 i/o0 to i/o7 i/o0 to i/o7 dqm dqm cs cs s0 a0 to a12, ba0, ba1 d13 d12 i/o0 to i/o7 i/o0 to i/o7 dqm dqm cs cs s3 d15 d14 i/o0 to i/o7 i/o0 to i/o7 dqm dqm cs cs d9 i/o0 to i/o7 i/o0 to i/o7 dqm dqm cs cs d8 d11 i/o0 to i/o7 i/o0 to i/o7 dqm dqm cs cs d10 r100 r101 ck0 clk; 4 sdrams + 3.3 pf cap clk; 4 sdrams + 3.3 pf cap ck1 r102 r103 ck2 clk; 4 sdrams + 3.3 pf cap clk; 4 sdrams + 3.3 pf cap ck3
hb52e648en/hb52e649en-a6b/b6b 13 block diagram (hb52e649en) dqmb0 d1 i/o0 to i/o7 i/o0 to i/o7 dqm dqm dq0 to dq7 dq8 to dq15 dqmb1 * d0 to d17: hm5225805 u0: 2-kbit eeprom c0 to c17: 0.33 f, c18 to c35: 0.10 f r0: 10 k w , r1: 47 k w n0 to n17: network registor 10 w r100 to r103: 10 w cke (d9 to d17) serial pd sda a0 a1 a2 sa0 sa1 sa2 v cc cke1 cke (d0 to d8) cke0 scl u0 sda scl notes : 1. the sda pull-up resistor is required due to the open-drain/open-collector output. 2. the scl pull-up resistor is recommended 3. sdram d11 dqmb input is wired to dqmb5 because of the normal scl line inacitve r0 8 n0, n1 n4, n5 n6, n7 n8, n9 n10, n11 n12, n13 n14, n15 n16, n17 8 dqmb4 dq32 to dq39 dq40 to dq47 dqmb5 8 8 v cc (d0 to d17, u0) v ss (d0 to d17, u0) v ss v cc c18 to c35 c0 to c17 v ss r1 re , ce , w cs cs d6 d5 d0 i/o0 to i/o7 i/o0 to i/o7 dqm dqm cs cs s1 s2 "high" state. dqmb2 d4 i/o0 to i/o7 i/o0 to i/o7 dqm dqm dq16 to dq23 dq24 to dq31 dqmb3 8 8 dqmb6 dq48 to dq55 dq56 to dq63 dqmb7 8 8 cs cs d8 d7 d3 i/o0 to i/o7 i/o0 to i/o7 dqm dqm cs cs s0 a0 to a12, ba0, ba1 d15 d14 i/o0 to i/o7 i/o0 to i/o7 dqm dqm cs cs s3 d17 d16 i/o0 to i/o7 i/o0 to i/o7 dqm dqm cs cs d10 i/o0 to i/o7 i/o0 to i/o7 dqm dqm cs cs d2 i/o0 to i/o7 dqm cb0 to cb7 8 cs d11 i/o0 to i/o7 dqm cs d9 d13 i/o0 to i/o7 i/o0 to i/o7 dqm dqm cs cs d12 r100 r101 ck0 clk (5 sdrams) clk (5 sdrams) ck1 r102 r103 ck2 clk (4 sdrams + 3.3 pf cap) clk (4 sdrams + 3.3 pf cap) ck3 wp n2, n3
hb52e648en/hb52e649en-a6b/b6b 14 absolute maximum ratings parameter symbol value unit note vol t age on any pi n rel at i ve to v ss v t ?. 5 to v c c + 0. 5 ( 4. 6 (max ) ) v1 suppl y vol t age rel at i v e to v ss v c c ?. 5 to +4. 6v1 shor t c i r c ui t out put cur r ent i out 50 ma power di s s i pat i on (hb52e648en) p t 8. 0w power di s s i pat i on (hb52e649en) p t 9. 0w oper ati ng temperat ur e topr 0 to + 65 c st or age temper atur ets t g ?5 to +125 c not e: 1. res pect to v ss dc operating conditions (ta = 0 to +65 c) parameter symbol min max unit notes suppl y vol t age v c c 3. 03. 6 v 1, 2 v ss 00v3 i nput hi gh vol t ag e v ih 2. 0v c c + 0. 3 v 1, 4 i nput l ow vol t age v il ?. 30. 8 v 1, 5 not es : 1. al l vol t age ref er r ed to v ss 2. the suppl y vol t age wi t h all v c c pi ns mus t be on th e sa me l ev el . 3. the suppl y vol t age wi t h al l v ss pi ns mus t be on th e sa me l ev el . 4. v ih (max ) = v c c + 2. 0 v for pu ls e wi t h 3 ns at v c c . 5. v il (mi n) = v ss ?2. 0 v for pu ls e wi dt h 3 ns at v ss .
hb52e648en/hb52e649en-a6b/b6b 15 v il /v ih clamp (component characteristic) this sdram component has v il and v ih clamp for ck, cke, s , dqmb and dq pins. minimum v il clamp current v il (v) i (m a) ? ?2 ?. 8 ?5 ?. 6 ?9 ?. 4 ?3 ?. 28 ? ? ?. 92 ?. 8 ?. 6 ?. 60 ?. 40 ?. 20 00 v il (v) i (ma) ?.5 ? ?.5 ? ?5 ?0 ?5 ?0 ?0 0 ?5 ? 0
hb52e648en/hb52e649en-a6b/b6b 16 minimum v ih clamp current v ih (v) i (m a) v c c + 2 1 0 v c c + 1. 88 v c c + 1. 65. 5 v c c + 1. 43. 5 v c c + 1. 21. 5 v c c + 1 0 . 3 v c c + 0. 80 v c c + 0. 60 v c c + 0. 40 v c c + 0. 20 v c c + 0 0 v ih (v) v cc + 0 v cc + 1 v cc + 2 v cc + 0.5 v cc + 1.5 i (ma) 8 4 6 0 2 10
hb52e648en/hb52e649en-a6b/b6b 17 i ol /i oh characteristics (component characteristic) output low current (i ol ) i o l i o l vout (v) mi n (ma) max (ma) 00 0 0. 427 71 0. 65 41 108 0. 85 51 134 1 58 151 1. 4 70 188 1. 5 72 194 1. 65 75 203 1. 8 77 209 1. 95 77 212 3 80 220 3. 45 81 223 i ol (ma) vout (v) 250 200 150 100 50 0 0 0.5 1 1.5 2 2.5 3 3.5 min max
hb52e648en/hb52e649en-a6b/b6b 18 output high current (i oh ) (ta = 0 to 65?c, v cc = 3.0 v to 3.45 v, v ss = 0 v) i o h i o h vout (v) mi n (ma) max (ma) 3. 45 3 3. 3 ?8 3 0 ?5 2. 6 ?1 ?30 2. 4 ?4 ?54 2 ?9 ?97 1. 8 ?7 ?27 1. 65 ?3 ?48 1. 5 ?8 ?70 1. 4 ?1 ?85 1 ?9 ?45 0 ?3 ?03 i oh (ma) vout (v) 0 ?00 ?00 ?00 ?00 ?00 ?00 0.5 1 1.5 2 2.5 3 min max 3.5 0
hb52e648en/hb52e649en-a6b/b6b 19 dc characteristics (ta = 0 to 65 c, v cc = 3.3 v 0.3 v, v ss = 0 v) (hb52e648en) hb52e648en -a6b/b6b parameter symbol min max unit test conditions notes oper ati ng cur r ent ( ce la t enc y = 2) i c c 1 1000 ma bur s t l engt h = 1 t r c = mi n 1, 2, 3 ( ce la t enc y = 3) i c c 1 1000 ma st andby cur r ent i n power do w n i c c 2 p 48 ma cke = v il , t c k = 12 ns 6 st andby cur r ent i n power do w n ( i nput si gnal stabl e) i c c 2 ps 32 ma cke = v il , t c k = 7 st andby cur r ent i n non power down i c c 2 n 320 ma cke, s = v ih , t c k = 12 ns 4 ac t i v e st andby cur r ent in power down i c c 3 p 64 ma cke = v il , t c k = 12 ns 1, 2, 6 ac t i v e st andby cur r ent in non power down i c c 3 n 480 ma cke, s = v ih , t c k = 12 ns 1, 2, 4 bur s t oper at i ng c ur r ent ( ce la t enc y = 2) i c c 4 1040 ma t c k = mi n, bl = 4 1 , 2, 5 ( ce la t enc y = 3) i c c 4 1040 ma ref r esh cur r ent i c c 5 2000 ma t r c = mi n3 sel f re f r es h curr ent i c c 6 ?8mav ih 3 v c c ?0. 2 v v il 0. 2 v 8 i nput l eak age cur r ent i l i ?0 10 m a0 vin v c c out put leak age cur r ent i l o ?0 10 m a0 vout v c c dq = di s abl e out put hi gh vol tage v o h 2. 4 vi o h = 4 ma out put low vol t ag e v o l ?. 4vi o l = 4 m a notes: 1. i cc depends on output load condition when the device is selected. i cc (max) is specified at the output open condition. 2. one bank operation. 3. input signals are changed once per one clock. 4. input signals are changed once per two clocks. 5. input signals are changed once per four clocks. 6. after power down mode, ck operating current. 7. after power down mode, no ck operating current. 8. after self refresh mode set, self refresh current.
hb52e648en/hb52e649en-a6b/b6b 20 dc characteristics (ta = 0 to 65 c, v cc = 3.3 v 0.3 v, v ss = 0 v) (hb52e649en) hb52e649en -a6b/b6b parameter symbol min max unit test conditions notes oper ati ng cur r ent ( ce la t enc y = 2) i c c 1 1125 ma bur s t l engt h = 1 t r c = mi n 1, 2, 3 ( ce la t enc y = 3) i c c 1 1125 ma st andby cur r ent i n power do w n i c c 2 p 54 ma cke = v il , t c k = 12 ns 6 st andby cur r ent i n power do w n ( i nput si gnal stabl e) i c c 2 ps 36 ma cke = v il , t c k = 7 st andby cur r ent i n non power down i c c 2 n 360 ma cke, s = v ih , t c k = 12 ns 4 ac t i v e st andby cur r ent in power down i c c 3 p 72 ma cke = v il , t c k = 12 ns 1, 2, 6 ac t i v e st andby cur r ent in non power down i c c 3 n 540 ma cke, s = v ih , t c k = 12 ns 1, 2, 4 bur s t oper at i ng c ur r ent ( ce la t enc y = 2) i c c 4 1170 ma t c k = mi n, bl = 4 1 , 2, 5 ( ce la t enc y = 3) i c c 4 1170 ma ref r esh cur r ent i c c 5 2250 ma t r c = mi n3 sel f re f r es h curr ent i c c 6 ?4mav ih 3 v c c ?0. 2 v v il 0. 2 v 8 i nput l eak age cur r ent i l i ?0 10 m a0 vin v c c out put leak age cur r ent i l o ?0 10 m a0 vout v c c dq = di s abl e out put hi gh vol tage v o h 2. 4 vi o h = 4 ma out put low vol t ag e v o l ?. 4vi o l = 4 m a notes: 1. i cc depends on output load condition when the device is selected. i cc (max) is specified at the output open condition. 2. one bank operation. 3. input signals are changed once per one clock. 4. input signals are changed once per two clocks. 5. input signals are changed once per four clocks. 6. after power down mode, ck operating current. 7. after power down mode, no ck operating current. 8. after self refresh mode set, self refresh current.
hb52e648en/hb52e649en-a6b/b6b 21 capacitance (ta = 25 c, v cc = 3.3 v 0.3 v) (hb52e648en) parameter symbol max unit notes i nput c apac i t ance (addr es s) c i1 105 pf 1, 2, 4 i nput c apac i t ance ( re , ce , w ) c i2 90 pf 1, 2, 4 i nput c apac i t ance (cke) c i3 68 pf 1, 2, 4 i nput c apac i t ance ( s ) c i4 38 pf 1, 2, 4 i nput c apac i t ance (ck) c i5 50 pf 1, 2, 4 i nput c apac i t ance (dqmb) c i6 23 pf 1, 2, 4 i nput /out put capac i t anc e (dq) c i/o 1 22 pf 1, 2, 3, 4 not es : 1. capac it anc e measur ed wi t h boont on met er or ef fec t i v e capac i t anc e m eas ur i ng m et hod. 2. meas urement condi t i on: f = 1 mhz , 1. 4 v bi as , 200 mv swi ng. 3. dqmb = v ih to dis abl e dat a- out . 4. thi s par amet er is sampl ed and not 100% tes t ed. capacitance (ta = 25 c, v cc = 3.3 v 0.3 v) (hb52e649en) parameter symbol max unit notes i nput c apac i t ance (addr es s) c i1 112 pf 1, 2, 4 i nput c apac i t ance ( re , ce , w ) c i2 97 pf 1, 2, 4 i nput c apac i t ance (cke) c i3 70 pf 1, 2, 4 i nput c apac i t ance ( s ) c i4 40 pf 1, 2, 4 i nput c apac i t ance (ck) c i5 50 pf 1, 2, 4 i nput c apac i t ance (dqmb) c i6 27 pf 1, 2, 4 i nput /out put capac i t anc e (dq) c i/o 1 22 pf 1, 2, 3, 4 not es : 1. capac it anc e measur ed wi t h boont on met er or ef fec t i v e capac i t anc e m eas ur i ng m et hod. 2. meas urement condi t i on: f = 1 mhz , 1. 4 v bi as , 200 mv swi ng. 3. dqmb = v ih to dis abl e dat a- out . 4. thi s par amet er is sampl ed and not 100% tes t ed.
hb52e648en/hb52e649en-a6b/b6b 22 ac characteristics (ta = 0 to 65 c, v cc = 3.3 v 0.3 v, v ss = 0 v) hb52e648en/649en -a6b/b6b parameter hitachi symbol pc100 symbol min max unit notes sy s t em cl oc k cy cl e ti me ( ce la t enc y = 2) t c k tc l k 10 ns 1 ( ce la t enc y = 3) t c k tc l k 10 ns ck hi gh pu l s e widt ht c kh tc h3 ns 1 ck low pul s e wi dt ht c kl tc l 3 ns 1 ac c es s ti me fr om ck ( ce la t enc y = 2) t ac tac 6 ns 1, 2 ( ce la t enc y = 3) t ac tac 6 ns dat a- ou t hol d time t o h toh 3 ns 1, 2 ck to dat a- out low impedanc et l z 2 ns 1, 2, 3 ck to dat a- out hi gh impedanc et h z 6 ns 1, 4 dat a- in se t up time t d s ts i 2 ns 1 dat a in hol d ti me t d h thi 1 ns 1 addr ess set up time t as ts i 2 ns 1 addr ess hol d ti me t ah thi 1 ns 1 cke set up ti me t c es ts i 2 ns 1, 5 cke set up ti me for power do w n e x i t t c esp tpde 2 ns 1 cke hol d ti me t c eh thi 1 ns 1 command set up time t c s ts i 2 ns 1 command hol d ti me t c h thi 1 ns 1 ref / act i v e to ref / ac t i v e command per i od t r c tr c 70 ns 1 ac t i v e to pr ec har ge command per i od t r as tr as 50 120000 ns 1 ac t i v e command to col umn command ( s ame bank ) t r c d tr c d 20 ns 1 pr ec har ge to ac ti v e command per i od t r p tr p 20 ns 1 wr i t e r ec ov er y or da t a- i n t o pr ec harge l ead ti me t d pl tdpl 20 ns 1 ac t i v e (a) to act i v e (b) command per i od t r r d tr r d 20 ns 1 tr ans it i on ti me ( r i s e and f al l ) t t 15ns ref r esh per i od t r ef ?4ms
hb52e648en/hb52e649en-a6b/b6b 23 notes: 1. ac measurement assumes t t = 1 ns. reference level for timing of input signals is 1.5 v. 2. access time is measured at 1.5 v. load condition is c l = 50 pf. 3. t lz (min) defines the time at which the outputs achieves the low impedance state. 4. t hz (max) defines the time at which the outputs achieves the high impedance state. 5. t ces defines cke setup time to ck rising edge except power down exit command. test conditions input and output timing reference levels: 1.5 v input waveform and output load: see following figures t t 2.4 v 0.4 v 0.8 v 2.0 v input t t dq cl
hb52e648en/hb52e649en-a6b/b6b 24 relationship between frequency and minimum latency hb52e648en/649en parameter -a6b/b6b frequency (mhz) 100 t ck (ns) hitachi symbol pc100 symbol 10 notes ac t i v e command to col umn command (s ame bank ) i r c d 21 ac t i v e command to ac t i v e command (s ame bank ) i r c 7= [i r as + i r p ] 1 ac t i v e command to pr ec har ge command ( s ame bank ) i r as 51 pr ec har ge command to ac t i ve command ( s ame bank ) i r p 21 wr i t e r ec ov er y or dat a- i n to pr ec har ge command ( s ame bank ) i d pl tdpl 2 1 ac t i v e command to ac t i v e command ( di f f er ent bank ) i r r d 21 sel f re f r es h ex it ti me i sr ex ts r x 1 2 las t da t a in to ac t i v e command ( aut o pr ec har ge, same bank) i apw tdal 4 = [i d pl + i r p ] sel f re f r es h ex it to command input i sec 7= [i r c ] 3 pr ec har ge command to hi gh i mpedanc e ( ce la t enc y = 2) i h zp tr oh 2 ( ce la t enc y = 3) i h zp tr oh 3 las t da t a out to ac t i v e command (auto pr ec har ge) ( s ame bank ) i apr 1 las t da t a out to pr ec har ge (ear l y prec har ge) ( ce la t enc y = 2) i ep ? ( ce la t enc y = 3) i ep ? col umn command to col umn command i c c d tc c d1 wr i t e c ommand to dat a in lat enc y i w c d tdwd 0 dqmb to dat a in i d id tdqm 0 dqmb to dat a out i d o d tdqz 2 cke to ck di s able i c l e tc k e1 regi s ter set to ac t i v e command i r sa tmr d1 s to command di s abl ei c d d 0 power down ex i t t o command input i pec 1
hb52e648en/hb52e649en-a6b/b6b 25 not es : 1. i r c d to i r r d ar e rec ommended val ue. 2. be vali d [dsel] or [nop] at ne x t command of sel f re f r es h ex i t . 3. ex c ept [dsel] and [nop]
hb52e648en/hb52e649en-a6b/b6b 26 pin functions ck0 to ck3 (input pin): ck is the master clock input to this pin. the other input signals are referred at ck rising edge. s0 to s3 (input pin): when s is low, the command input cycle becomes valid. when s is high, all inputs are ignored. however, internal operations (bank active, burst operations, etc.) are held. re , ce and w (input pins): although these pin names are the same as those of conventional drams, they function in a different way. these pins define operation commands (read, write, etc.) depending on the combination of their voltage levels. for details, refer to the command operation section. a0 to a12 (input pins): row address (ax0 to ax12) is determined by a0 to a12 level at the bank active command cycle ck rising edge. column address (ay0 to ay9) is determined by a0 to a9 level at the read or write command cycle ck rising edge. and this column address becomes burst access start address. a10 defines the precharge mode. when a10 = high at the precharge command cycle, all banks are precharged. but when a10 = low at the precharge command cycle, only the bank that is selected by ba0/ba1 (bs) is precharged. ba0/ba1 (input pin): ba0/ba1 are bank select signal (bs). the memory array is divided into bank 0, bank 1, bank 2 and bank 3. if ba1 is low and ba0 is low, bank 0 is selected. if ba1 is high and ba0 is low, bank 1 is selected. if ba1 is low and ba0 is high, bank 2 is selected. if ba1 is high and ba0 is high, bank 3 is selected. cke0, cke1 (input pin): this pin determines whether or not the next ck is valid. if cke is high, the next ck rising edge is valid. if cke is low, the next ck rising edge is invalid. this pin is used for power-down and clock suspend modes. dqmb0 to dqmb7 (input pins): read operation: if dqmb is high, the output buffer becomes high-z. if the dqmb is low, the output buffer becomes low-z. write operation: if dqmb is high, the previous data is held (the new data is not written). if dqmb is low, the data is written. dq0 to dq63 (input/output pins): data is input to and output from these pins. cb0 to cb7 (input/output pins): data is input to and output from these pins. v cc (power supply pins): 3.3 v is applied. v ss (power supply pins): ground is connected. detailed operation part refer to the hm5225165b/hm5225805b/hm5225405b-75/a6/b6 datasheet.
hb52e648en/hb52e649en-a6b/b6b 27 physical outline 6.35 0.250 6.35 0.250 1.00 0.039 detail b detail c detail a 0.20 0.15 2.50 0.20 0.010 0.0004 0.098 0.008 3.125 0.125 3.125 0.125 0.123 0.005 0.123 0.005 1.27 0.050 3.00 typ 133.37 0.15 0.118 typ 5.251 0.006 3.00 0.10 0.118 0.004 11.43 36.83 54.61 0.450 2.150 (63.67) (2.51) 1.450 a b c 1 84 front side back side 85 4.00 0.10 0.157 0.004 17.80 0.70 34.925 1.375 168 2 ? f 3.00 0.10 2 ? f 0.118 0.003 1.00 0.05 0.039 0.002 2.00 0.10 0.079 0.004 4.175 0.164 2.00 0.10 0.079 0.004 (datum -a-) (datum -a-) unit: mm inch (datum -a-) r full r full note: tolerance on all dimensions 0.15/0.006 unless otherwise specified. 127.35 0.15 5.014 0.006 component area (front) component area (back) 1.27 0.10 4.00 min 0.157 min 0.050 0.004 4.00 max 0.157 max
hb52e648en/hb52e649en-a6b/b6b 28 cautions 1. hitachi neither warrants nor grants licenses of any rights of hitachi? or any third party? patent, copyright, trademark, or other intellectual property rights for information contained in this document. hitachi bears no responsibility for problems that may arise with third party? rights, including intellectual property rights, in connection with use of the information contained in this document. 2. products and product specifications may be subject to change without notice. confirm that you have received the latest product standards or specifications before final design, purchase or use. 3. hitachi makes every attempt to ensure that its products are of high quality and reliability. however, contact hitachi? sales office before using the product in an application that demands especially high quality and reliability or where its failure or malfunction may directly threaten human life or cause risk of bodily injury, such as aerospace, aeronautics, nuclear power, combustion control, transportation, traffic, safety equipment or medical equipment for life support. 4. design your application so that the product is used within the ranges guaranteed by hitachi particularly for maximum rating, operating supply voltage range, heat radiation characteristics, installation conditions and other characteristics. hitachi bears no responsibility for failure or damage when used beyond the guaranteed ranges. even within the guaranteed ranges, consider normally foreseeable failure rates or failure modes in semiconductor devices and employ systemic measures such as fail- safes, so that the equipment incorporating hitachi product does not cause bodily injury, fire or other consequential damage due to operation of the hitachi product. 5. this product is not designed to be radiation resistant. 6. no one is permitted to reproduce or duplicate, in any form, the whole or part of this document without written approval from hitachi. 7. contact hitachi? sales office for any questions regarding this document or hitachi semiconductor products. hitachi, ltd. semiconductor & integrated circuits. nippon bldg., 2-6-2, ohte-machi, chiyoda-ku, tokyo 100-0004, japan tel: tokyo (03) 3270-2111 fax: (03) 3270-5109 copyright ?hitachi, ltd., 1998. all rights reserved. printed in japan. hitachi asia pte. ltd. 16 collyer quay #20-00 hitachi tower singapore 049318 tel: 535-2100 fax: 535-1533 url northamerica : http:semiconductor.hitachi.com/ europe : http://www.hitachi-eu.com/hel/ecg asia (singapore) : http://www.has.hitachi.com.sg/grp3/sicd/index.htm asia (taiwan) : http://www.hitachi.com.tw/e/product/sicd_frame.htm asia (hongkong) : http://www.hitachi.com.hk/eng/bo/grp3/index.htm japan : http://www.hitachi.co.jp/sicd/indx.htm hitachi asia ltd. taipei branch office 3f, hung kuo building. no.167, tun-hwa north road, taipei (105) tel: <886> (2) 2718-3666 fax: <886> (2) 2718-8180 hitachi asia (hong kong) ltd. group iii (electronic components) 7/f., north tower, world finance centre, harbour city, canton road, tsim sha tsui, kowloon, hong kong tel: <852> (2) 735 9218 fax: <852> (2) 730 0281 telex: 40815 hitec hx hitachi europe ltd. electronic components group. whitebrook park lower cookham road maidenhead berkshire sl6 8ya, united kingdom tel: <44> (1628) 585000 fax: <44> (1628) 778322 hitachi europe gmbh electronic components group dornacher stra? 3 d-85622 feldkirchen, munich germany tel: <49> (89) 9 9180-0 fax: <49> (89) 9 29 30 00 hitachi semiconductor (america) inc. 179 east tasman drive, san jose,ca 95134 tel: <1> (408) 433-1990 fax: <1>(408) 433-0223 for further information write to:
hb52e648en/hb52e649en-a6b/b6b 29 revision record rev. date contents of modification drawn by approved by 0.0 oct. 20, 1999 initial issue (referred to hm5225165b/hm5225805b/hm5225405b- 75/a60/b60 rev 0.0) t. kudoh k. tsuneda 0.1 nov. 29, 1999 (referred to hm5225165b/hm5225805b/hm5225405b- 75/a60/b60 rev 0.0) deletion of hb52e328em-a6b/b6b and hb52e329em- a6b/b6b.

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