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84330av-01 www.icst.com/products/hiperclocks.html rev. a february 14, 2003 1

ics84330-01 700mh z , l ow j itter , c rystal - to -3.3v d ifferential lvpecl f requency s ynthesizer preliminary g eneral d escription the ics84330-01 is a general purpose, single out- put high frequency synthesizer and a member of the hiperclocks? family of high performance clock solutions from ics. the vco operates at a fre- quency range of 200mhz to 700mhz. the vco and output frequency can be programmed using the serial or parallel interfaces to the configuration logic. the output can be configured to divide the vco frequency by 1, 2, 4, and 8. out- put frequency steps from 250khz to 2mhz can be achieved using a 16mhz crystal depending on the output divider setting. f eatures ? fully integrated pll, no external loop filter requirements ? 1 differential 3.3v lvpecl output ? crystal oscillator interface: 10mhz to 25mhz ? output frequency range: 25mhz to 700mhz ? vco range: 200mhz to 700mhz ? parallel or serial interface for programming m and n dividers during power-up ? rms period jitter: tbd ? cycle-to-cycle jitter: 15ps (typical) ? 3.3v supply voltage ? 0c to 70c ambient operating temperature ? pin compatible with the sy89430v hiperclocks? ,&6 p in a ssignment b lock d iagram s_clock s_data s_load v cca nc nc xtal1 ics84330-01 28-lead plcc v package 11.6mm x 11.4mm x 4.1mm top view 25 24 23 22 21 20 19 5 6 7 8 9 10 11 26 27 28 1 2 3 4 18 17 16 15 14 13 12 m3 m2 m1 m0 np_load v cc xtal2 v ee test v cc v ee nfout fout v cco n1 n0 m8 m7 m6 m5 m4 ics84330-01 28-lead soic 7.5mm x 18.05mm x 2.25mm body package m package to p vi e w m0 m1 m2 m3 m4 m5 m6 m7 m8 n0 n1 v ee test v cc 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 np_load v cc xtal2 xtal1 nc nc v cca s_load s_data s_clock v cco fout nfout v ee fout nfout osc xtal1 xtal2 s_load s_data s_clock np_load m0:m8 n0:n1 vco pll test configuration interface logic m 16 phase detector n 1 0 2 the preliminary information presented herein represents a product in prototyping or pre-production. the noted characteristics a re based on initial product characterization. integrated circuit systems, incorporated (ics) reserves the right to change any circuitry or specific ations without notice.
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ics84330-01 700mh z , l ow j itter , c rystal - to -3.3v d ifferential lvpecl f requency s ynthesizer preliminary f unctional d escription note: the functional description that follows describes operation using a 16mhz crystal. valid pll loop divider values for different crystal or input frequencies are defined in the input frequency characteristics, table 6, note 1. the ics84330-01 features a fully integrated pll and therefore requires no external components for setting the loop band- width. a quartz crystal is used as the input to the on-chip oscillator. the output of the oscillator is divided by 16 prior to the phase detector. with a 16mhz crystal this provides a 1mhz reference frequency. the vco of the pll operates over a range of 200mhz to 700mhz. the output of the m divider is also applied to the phase detector. the phase detector and the m divider force the vco output frequency to be 2m times the reference frequency divided by 16 by adjusting the vco control voltage. note that for some values of m (either too high or too low), the pll will not achieve lock. the output of the vco is scaled by a divider prior to being sent to each of the lvpecl output buffers. the divider provides a 50% o utput duty cycle. the programmable features of the ics84330-01 support two input modes to program the m divider and n output divider. the two input operational modes are parallel and serial. figure 1 shows the timing diagram for each mode. in parallel mode the np_load input is low. the data on inputs m0 through m8 and n0 through n1 is passed directly to the m divider and n output divider. on t he low-to-high transition of the np_load input, the data is latched and the m divider remains loaded until the next low transition on np_load or until a serial event occurs. the test output is mode 000 (shift register out) when operating in the parallel inpu t mode. the relationship between the vco frequency, the crystal frequency and the m divider is defined as follows: the m value and the required values of m0 through m8 are shown in table 3b, programmable vco frequency function table. valid m values for which the pll will achieve lock are defined as 100 m 350. the frequency out is defined as follows: serial operation occurs when np_load is high and s_load is low. the shift register is loaded by sampling the s_data bits with the rising edge of s_clock. the contents of the shift register are loaded into the m divider when s_load transitions from low-to-high. the m divide and n output divide values are latched on the high-to-low transition of s_load. if s_load is held high, data at the s_data input is passed directly to the m divider on each rising edge of s_clock. the serial mode can be used to program the m and n bits and test bits t2:t0. the internal registers t2:t0 determine the state of the test output as follows : time s erial l oading p arallel l oading m, n t s t h t s t h t s f igure 1. p arallel & s erial l oad o perations 16 2m fvco = fxtal x n fout = fvco = 16 2m fxtal x n t2 t1 t0 test output 0 0 0 shift register out 0 0 1 high 0 1 0 pll reference xtal 16 0 1 1 (vco m) /2 (non 50% duty m divider) 1 0 0 fout lvcmos output frequency < 200mhz 1 0 1 low 1 1 0 (s_clock m) /2 (non 50% duty cycle m divider) 1 1 1 fout 4 fout fout fout fout fout fout fout s_clock n divider fout t2 t1 t0 n1 n0 m8 m7 m6 m5 m4 m3 m2 m1 m0 s_clock s_data s_load np_load m0:m8, n0:n1 np_load
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ics84330-01 700mh z , l ow j itter , c rystal - to -3.3v d ifferential lvpecl f requency s ynthesizer preliminary t able 2. p in c haracteristics t able 1. p in d escriptions e m a ne p y tn o i t p i r c s e d v c c r e w o p. s n i p y l p p u s e r o c v a c c r e w o p. l l p e h t r o f n i p y l p p u s g o l a n a v e e r e w o p. s n i p y l p p u s e v i t a g e n v o c c r e w o p. n i p y l p p u s t u p t u o c nd e s u n u. t c e n n o c t o n o d 2 l a t x , 1 l a t xt u p n i . t u p t u o e h t s i 2 l a t x . t u p n i e h t s i 1 l a t x . e c a f r e t n i r o t a l l i c s o l a t s y r c d a o l _ p nt u p n ip u l l u p o t n i d e d a o l s i 0 m : 8 m t a t n e s e r p a t a d n e h w s e n i m r e t e d . t u p n i d a o l l e l l a r a p . e u l a v e d i v i d t u p t u o n e h t s t e s 0 n : 1 n t a t n e s e r p a t a d n e h w d n a , r e d i v i d m . s l e v e l e c a f r e t n i l t t v l / s o m c v l k c o l c _ st u p n in w o d l l u p e h t n o r e t s i g e r t f i h s e h t o t n i t u p n i a t a d _ s t a t n e s e r p a t a d l a i r e s e h t s k c o l c . s l e v e l e c a f r e t n i l t t v l / s o m c v l . k c o l c _ s f o e g d e g n i s i r a t a d _ st u p n in w o d l l u p . k c o l c _ s f o e g d e g n i s i r e h t n o d e l p m a s a t a d . t u p n i l a i r e s r e t s i g e r t f i h s . s l e v e l e c a f r e t n i l t t v l / s o m c v l d a o l _ st u p n in w o d l l u p . r e d i v i d m e h t o t n i r e t s i g e r t f i h s m o r f a t a d f o n o i t i s n a r t s l o r t n o c . s l e v e l e c a f r e t n i l t t v l / s o m c v l 2 m , 1 m , 0 m 5 m , 4 m , 3 m 8 m , 7 m , 6 m t u p n ip u l l u p . t u p n i d a o l _ p n f o n o i t i s n a r t h g i h - o t - w o l n o d e h c t a l a t a d . s t u p n i r e d i v i d m . s l e v e l e c a f r e t n i l t t v l / s o m c v l 1 n , 0 nt u p n ip u l l u p . e l b a t n o i t c n u f c 3 e l b a t n i d e n i f e d s a e u l a v r e d i v i d t u p t u o n s e n i m r e t e d . s l e v e l e c a f r e t n i l t t v l / s o m c v l t s e tt u p t u o . n o i t a r e p o f o e d o m l a i r e s e h t n i d e s u s i h c i h w t u p t u o t s e t . s l e v e l e c a f r e t n i l t t v l / s o m c v l t u o f , t u o f nt u p t u o . s l e v e l e c a f r e t n i l c e p v l v 3 . 3 . r e z i s e h t n y s e h t r o f t u p t u o l a i t n e r e f f i d : e t o n p u l l u p d n a n w o d l l u p . s e u l a v l a c i p y t r o f , s c i t s i r e t c a r a h c n i p , 2 e l b a t e e s . s r o t s i s e r t u p n i l a n r e t n i o t r e f e r l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u c n i e c n a t i c a p a c t u p n i 4f p r p u l l u p r o t s i s e r p u l l u p t u p n i 1 5k ? r n w o d l l u p r o t s i s e r n w o d l l u p t u p n i 1 5k ?
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ics84330-01 700mh z , l ow j itter , c rystal - to -3.3v d ifferential lvpecl f requency s ynthesizer preliminary t able 3a. p arallel and s erial m ode f unction t able t able 3b. p rogrammable vco f requency f unction t able y c n e u q e r f o c v ) z h m ( e d i v i d m 6 5 28 2 14 62 36 18421 8 m7 m6 m5 m4 m3 m2 m1 m0 m 0 0 20 0 1001100100 2 0 21 0 1 001100101 4 0 22 0 1 0 0 1 10 0 1 10 6 0 23 0 1 00 1100 111 6 9 68 4 3 10 10 11100 8 9 69 4 3 10 10 1110 1 0 0 70 5 3 10 10 11110 . z h m 6 1 f o y c n e u q e r f l a t s y r c a o t d n o p s e r r o c s e i c n e u q e r f g n i t l u s e r e h t d n a s e u l a v e d i v i d m e s e h t : 1 e t o n t able 3c. p rogrammable o utput d ivider f unction t able s t u p n i e u l a v r e d i v i d n ) z h m ( y c n e u q e r f t u p t u o 1 n0 nm u m i n i mm u m i x a m 00 2 0 0 10 5 3 01 4 0 55 7 1 10 8 5 25 . 7 8 11 1 0 0 20 0 7 s t u p n i s n o i t i d n o c d a o l _ p nmnd a o l _ sk c o l c _ sa t a d _ s xxxx x x . h g i h t e s l l a e r a s t i b n d n a m . t e s e r la t a da t a dx x x d n a r e d i v i d m o t y l t c e r i d d e s s a p s t u p n i n d n a m n o a t a d . 0 0 0 e d o m t s e t . r e d i v i d t u p t u o n a t a da t a dx x x d e d a o l s n i a m e r d n a s r e t s i g e r t u p n i o t n i d e h c t a l s i a t a d . s r u c c o t n e v e l a i r e s a l i t n u r o n o i t i s n a r t w o l t x e n l i t n u hxxl a t a d n o a t a d h t i w d e d a o l s i r e t s i g e r t f i h s . e d o m t u p n i l a i r e s . k c o l c _ s f o e g d e g n i s i r h c a e n o a t a d _ s hxx la t a d r e d i v i d m e h t o t d e s s a p e r a r e t s i g e r t f i h s e h t f o s t n e t n o c . r e d i v i d t u p t u o n d n a hxx la t a d. d e h c t a l e r a s e u l a v e d i v i d t u p t u o n d n a e d i v i d m hxxl x x . s r e t s i g e r t f i h s t c e f f a t o n o d t u p n i l a i r e s r o l e l l a r a p hxxh a t a d. d e k c o l c s i t i s a r e d i v i d m o t y l t c e r i d d e s s a p a t a d _ s w o l = l : e t o n h g i h = h e r a c t ' n o d = x n o i t i s n a r t e g d e g n i s i r = n o i t i s n a r t e g d e g n i l l a f =
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ics84330-01 700mh z , l ow j itter , c rystal - to -3.3v d ifferential lvpecl f requency s ynthesizer preliminary t able 4c. lvpecl dc c haracteristics , v cc = v cca = v cco = 3.3v5%, t a = 0 c to 70 c lobmy sr etemara ps noitidnoctse tm umini ml acipy tm umixa ms tinu v ho 1eton;egatlovhgihtuptu ov cc 4.1 -v cc 0.1 -v v lo 1eton;egatlovwoltuptu ov cc 0.2 -v cc 7.1 -v v gniws gniwsegatlovtuptuokaep-ot-kae p6 . 05 9. 0v 05htiwdetanimretstuptuo:1eton ? vot occ .v2- t able 4a. p ower s upp l y d c c haracteristic s , v cc = v cca = v cco = 3.3v5%, t a = 0 c to 70 c t able 4b. lvcmos / lvttl dc c haracteristics , v cc = v cca = v cco = 3.3v5%, t a = 0 c to 70 c lobmy sr etemara ps noitidnoctse tm umini ml acipy tm umixa ms tinu v cc egatlovylppuseroc 531. 33 . 35 64. 3v v acc egatlovylppusgolana 531. 33 . 35 64. 3v i ee tnerrucylppusrewop 51 1a m i acc tnerrucylppusgolana 5 1a m lobmy sr etemara ps noitidnoctse tm umini ml acipy tm umixa ms tinu v hi egatlovhgihtupni 2v cc 3.0 +v v li egatlovwoltupni 3.0 -8 . 0v i hi tnerruchgihtupni ,1n,0n,8m:0m les_latx,daol_pn v cc v= ni v564.3 =5a ,atad_s,daol_s kcolc_s v cc v= ni v564.3 =0 5 1a i li tnerrucwoltupni ,1n,0n,8m:0m les_latx,daol_pn v cc v,v564.3= ni v0 =0 51 -a ,atad_s,daol_s kcolc_s v cc v,v564.3= ni v0 =5 -a v ho 1eton;egatlovhgihtuptuo 6. 2v v lo 1eton;egatlovwoltuptuo 5. 0v 05htiwdetanimretstuptuo:1eton ? vot occ .2/ a bsolute m aximum r atings supply voltage, v cc 4.6v inputs, v i -0.5v to v cc + 0.5 v outputs, v o -0.5v to v cco + 0.5v package thermal impedance, ja 37.8 c/w (0 lfpm) storage temperature, t stg -65 c to 150 c note: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these ratings are stress specifications only. functional operation of product at these conditions or any conditions be- yond those listed in the dc characteristics or ac character- istics is not implied. exposure to absolute maximum rating conditions for extended periods may affect product reliability.
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ics84330-01 700mh z , l ow j itter , c rystal - to -3.3v d ifferential lvpecl f requency s ynthesizer preliminary t able 6. i nput f requency c haracteristics , v cc = v cca = v cco = 3.3v5%, t a = 0 c to 70 c l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u f n i y c n e u q e r f t u p n i 1 e t o n ; l a t x0 15 2z h m k c o l c _ s 0 5z h m y c n e u q e r f o c v m u m i x a m r o m u m i n i m e h t e v e i h c a o t t e s e b t s u m e u l a v m e h t e g n a r y c n e u q e r f l a t s y r c e h t r o f : 1 e t o n 0 6 1 e r a m f o s e u l a v d i l a v , z h m 0 1 f o y c n e u q e r f m u m i n i m e h t g n i s u . z h m 0 0 7 r o z h m 0 0 2 f o e g n a r m . 1 1 5 4 6 e r a m f o s e u l a v d i l a v , z h m 5 2 f o y c n e u q e r f m u m i x a m e h t g n i s u m . 4 2 2 t able 5. c rystal c haracteristics r e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u n o i t a l l i c s o f o e d o m l a t n e m a d n u f y c n e u q e r f 0 15 2z h m ) r s e ( e c n a t s i s e r s e i r e s t n e l a v i u q e 0 7 ? e c n a t i c a p a c t n u h s 7f p t able 7. ac c haracteristics , v cc = v cca = v cco = 3.3v5%, t a = 0 c to 70 c l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u f t u o y c n e u q e r f t u p t u o 0 0 7z h m t ) r e p ( t i j2 , 1 e t o n ; s m r , r e t t i j d o i r e p d b ts p t ) c c ( t i j2 , 1 e t o n ; r e t t i j e l c y c - o t - e l c y c 5 1s p t r t , f e m i t l l a f / e s i r t u p t u o% 0 8 o t % 0 20 0 5s p t s e m i t p u t e s k c o l c _ s o t a t a d _ s0 2s n d a o l _ s o t k c o l c _ s0 2s n d a o l _ p n o t n , m0 2s n t h e m i t d l o h k c o l c _ s o t a t a d _ s0 2s n d a o l _ p n o t n , m0 2s n t l e m i t k c o l l l p 0 1s m c d oe l c y c y t u d t u p t u o 0 5% . n o i t c e s n o i t a m r o f n i t n e m e r u s a e m r e t e m a r a p e e s . l a t x z h m 6 1 a g n i s u d e z i r e t c a r a h c 5 6 d r a d n a t s c e d e j h t i w e c n a d r o c c a n i d e n i f e d s i r e t e m a r a p s i h t : 1 e t o n . n o i t c e s s n o i t a c i l p p a e e s : 2 e t o n
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ics84330-01 700mh z , l ow j itter , c rystal - to -3.3v d ifferential lvpecl f requency s ynthesizer preliminary p arameter m easurement i nformation p eriod j itter c ycle - to -c ycle j itter 3.3v o utput l oad ac t est c ircuit scope qx nqx lvpecl v cc , v cca , v cco = 2v odc & t p eriod o utput r ise /f all t ime v oh v ref v ol mean period (first edge after trigger) reference point (trigger edge) 1 contains 68.26% of all measurements 2 contains 95.4% of all measurements 3 contains 99.73% of all measurements 4 contains 99.99366% of all measurements 6 contains (100-1.973x10 -7 )% of all measurements histogram v ee = -1.3v 0.165v clock outputs 20% 80% 80% 20% t r t f v sw i n g pulse width t period t pw t period odc = fout nfout ? ? ? ? t jit(cc) = t cycle n ? t cycle n+1 1000 cycles t cycle n t cycle n+1 nfout fout
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ics84330-01 700mh z , l ow j itter , c rystal - to -3.3v d ifferential lvpecl f requency s ynthesizer preliminary the clock layout topology shown below is a typical termina- tion for lvpecl outputs. the two different layouts mentioned are recommended only as guidelines. fout and nfout are low impedance follower outputs that generate ecl/lvpecl compatible outputs. therefore, terminat- ing resistors (dc current path to ground) or current sources must be used for functionality. these outputs are designed to f igure 3b. lvpecl o utput t ermination 3.3v f out f in 5 2 z o z o 5 2 z o 3 2 z o 3 2 z o = 50 ? z o = 50 ? f igure 3a. lvpecl o utput t ermination rtt = 1 (v oh + v ol / v cc ? 2) ? 2 z o 50 ? 50 ? rtt v cc - 2v f in f out ? drive 50 ? transmission lines. matched impedance techniques should be used to maximize operating frequency and minimize signal distortion. figures 3a and 3b show two different layouts which are recommended only as guidelines. other suitable clock layouts may exist and it would be recommended that the board designers simulate to guarantee compatibility across all printed circuit and clock component process variations. t ermination for lvpecl o utputs a pplication i nformation as in any high speed analog circuitry, the power supply pins are vulnerable to random noise. the ics84330-01 provides separate power supplies to isolate any high switching noise from the outputs to the internal pll. v cc , v cca and v cco should be individually connected to the power supply plane through vias, and bypass capacitors should be used for each pin. to achieve optimum jitter performance, power supply isolation is required. figure 2 illustrates how a 10 ? resistor along with a 10 f and a .01 f bypass capacitor should be connected to each v cca pin. f igure 2. p ower s upply f iltering 10 ? v cca 10 f .01 f 3.3v .01 f v cc p ower s upply f iltering t echniques z o = 50 ? z o = 50 ?
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ics84330-01 700mh z , l ow j itter , c rystal - to -3.3v d ifferential lvpecl f requency s ynthesizer preliminary ja by velocity (linear feet per minute) 0 200 500 multi-layer pcb, jedec standard test boards 37.8 c/w 31.1 c/w 28.3 c/w note: most modern pcb designs use multi-layered boards. the data in the second row pertains to most designs. t able 8a. t hermal r esistance ja for 28- pin plcc, f orced c onvection ja by velocity (linear feet per minute) 0 200 500 single-layer pcb, jedec standard test boards 76.2 c/w 60.8 c/w 53.2 c/w multi-layer pcb, jedec standard test boards 46.2 c/w 39.7 c/w 36.8 c/w note: most modern pcb designs use multi-layered boards. the data in the second row pertains to most designs. t able 8b. t hermal r esistance ja for 28- pin soic, f orced c onvection p ower c onsiderations this section provides information on power dissipation and junction temperature for the ics84330-01. equations and example calculations are also provided. 1. power dissipation. the total power dissipation for the ics84330-01 is the sum of the core power plus the power dissipated in the load(s). the following is the power dissipation for v cc = 3.3v + 5% = 3.465v, which gives worst case results. note: please refer to section 3 for details on calculating power dissipated in the load. ? power (core) max = v cc_max * i ee_max = 3.465v * 115ma = 398.5mw ? power (outputs) max = 30.2mw/loaded output pair if all outputs are loaded, the total power is 1 * 30.2mw = 30.2mw total power _max (3.465v, with all outputs switching) = 398.5mw + 30.2mw = 428.7mw 2. junction temperature. junction temperature, tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. the maximum recommended junction temperature for hiperclocks tm devices is 125 c. the equation for tj is as follows: tj = ja * pd_total + t a tj = junction temperature ja = junction-to-ambient thermal resistance pd_total = total device power dissipation (example calculation is in section 1 above) t a = ambient temperature in order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance ja must be used. assuming a moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 31.1 c/w per table 8a below. therefore, tj for an ambient temperature of 70 c with all outputs switching is: 70 c + 0.429w * 31.1 c/w = 83.3 c. this is well below the limit of 125 c. this calculation is only an example. tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow , and the type of board (single layer or multi-layer).
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ics84330-01 700mh z , l ow j itter , c rystal - to -3.3v d ifferential lvpecl f requency s ynthesizer preliminary 3. calculations and equations. the purpose of this section is to derive the power dissipated into the load. lvpecl output driver circuit and termination are shown in the figure 4. t o calculate worst case power dissipation into the load, use the following equations which assume a 50 ? load, and a termination voltage of v cco - 2v. for logic high, v out = v oh_max = v cco_max ? 1.0v (v cco_max - v oh_max ) = 1.0v for logic low, v out = v ol_max = v cco_max ? 1.7v (v cco_max - v ol_max ) = 1.7v pd_h is power dissipation when the output drives high. pd_l is the power dissipation when the output drives low. pd_h = [(v oh_max ? (v cco_max - 2v))/r l ] * (v cco_max - v oh_max ) = [(2v - (v cco _max - v oh_max )) /r l ] * (v cco_max - v oh_max ) = [(2v - 1v)/50 ? ] * 1v = 20.0mw pd_l = [(v ol_max ? (v cco_max - 2v))/r l ] * (v cco_max - v ol_max ) = [(2v - (v cco _max - v ol_max )) /r l ] * (v cco_max - v ol_max ) = [(2v - 1.7v)/50 ? ] * 1.7v = 10.2mw total power dissipation per output pair = pd_h + pd_l = 30.2mw f igure 4. lvpecl d river c ircuit and t ermination q1 v out v cco rl 50 v cco - 2v
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ics84330-01 700mh z , l ow j itter , c rystal - to -3.3v d ifferential lvpecl f requency s ynthesizer preliminary 0 200 500 multi-layer pcb, jedec standard test boards 37.8 c/w 31.1 c/w 28.3 c/w note: most modern pcb designs use multi-layered boards. the data in the second row pertains to most designs. r eliability i nformation t ransistor c ount the transistor count for ics84330-01 is: 4442 t able 9a. ja vs . a ir f low plcc t able ja by velocity (linear feet per minute) ja by velocity (linear feet per minute) 0 200 500 single-layer pcb, jedec standard test boards 76.2 c/w 60.8 c/w 53.2 c/w multi-layer pcb, jedec standard test boards 46.2 c/w 39.7 c/w 36.8 c/w note: most modern pcb designs use multi-layered boards. the data in the second row pertains to most designs. t able 9b. ja vs . a ir f low soic t able
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ics84330-01 700mh z , l ow j itter , c rystal - to -3.3v d ifferential lvpecl f requency s ynthesizer preliminary p ackage o utline - v s uffix n o i t a i r a v c e d e j s r e t e m i l l i m n i s n o i s n e m i d l l a l o b m y sm u m i n i mm u m i x a m n 8 2 a 9 1 . 47 5 . 4 1 a 9 2 . 25 0 . 3 2 a 7 5 . 11 1 . 2 b 3 3 . 03 5 . 0 c 9 1 . 02 3 . 0 d 2 3 . 2 17 5 . 2 1 1 d 3 4 . 1 18 5 . 1 1 2 d 5 8 . 46 5 . 5 e 2 3 . 2 17 5 . 2 1 1 e 3 4 . 1 18 5 . 1 1 2 e 5 8 . 46 5 . 5 t able 10a. p ackage d imensions reference document: jedec publication 95, ms-018
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ics84330-01 700mh z , l ow j itter , c rystal - to -3.3v d ifferential lvpecl f requency s ynthesizer preliminary p ackage o utline - m s uffix t able 10b. p ackage d imensions reference document: jedec publication 95, ms-013, mo-119 l o b m y s s r e t e m i l l i m m u m i n i mm u m i x a m n8 2 a- -5 6 . 2 1 a0 1 . 0- - 2 a5 0 . 25 5 . 2 b3 3 . 01 5 . 0 c8 1 . 02 3 . 0 d0 7 . 7 10 4 . 8 1 e0 4 . 70 6 . 7 ec i s a b 7 2 . 1 h0 0 . 0 15 6 . 0 1 h5 2 . 05 7 . 0 l0 4 . 07 2 . 1 0 8
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ics84330-01 700mh z , l ow j itter , c rystal - to -3.3v d ifferential lvpecl f requency s ynthesizer preliminary t able 11. o rdering i nformation r e b m u n r e d r o / t r a pg n i k r a me g a k c a pt n u o ce r u t a r e p m e t 1 0 - v a 0 3 3 4 8 s c i1 0 - v a 0 3 3 4 8 s c ic c l p d a e l 8 2e b u t r e p 8 3c 0 7 o t c 0 1 0 - t v a 0 3 3 4 8 s c i1 0 - v a 0 3 3 4 8 s c il e e r d n a e p a t n o c c l p d a e l 8 20 0 5c 0 7 o t c 0 1 0 - m a 0 3 3 4 8 s c i1 0 - m a 0 3 3 4 8 s c ic i o s d a e l 8 2e b u t r e p 6 2c 0 7 o t c 0 t 1 0 - m a 0 3 3 4 8 s c i1 0 - m a 0 3 3 4 8 s c il e e r d n a e p a t n o c i o s d a e l 8 20 0 0 1c 0 7 o t c 0 while the information presented herein has been checked for both accuracy and reliability, integrated circuit systems, incorpor ated (ics) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. no other circuits, patent s, or licenses are implied. this product is intended for use in normal commercial applications. any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by ics. ics reserves the right to change any circuitry or specifications without notice. ics does not authorize or warrant any ics product for use in life support devices or critical medical instruments.

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