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description the hcpl-7560 optically isolated modulator and hcpl- 0872 digital interface ic or digital flter together form an isolated programmable two-chip analog-to-digital converter. the isolated modulator allows direct mea - surement of motor phase currents in power inverters. in operation, the hcpl-7560 isolated modulator (op - tocoupler with 3750 v rms dielectric withstand voltage rating) converts a low-bandwidth analog input into a high-speed one-bit data stream by means of a sigma- delta ( - ? ) over-sampling modulator. this modulation provides for high noise margins and excellent immunity against isolation-mode transients. the modulator data and on-chip sampling clock are encoded and transmit - ted across the isolation boundary where they are recov - ered and decoded into separate high-speed clock and data channels. features ? 8-bit linearity ? 200 ns conversion time (pre-trigger mode 2 with hcpl-0872) ? 8-bit efective resolution with 5 s signal delay (14-bit with 102 s) (with hcpl-0872) ? fast 3 s over-range detection (with hcpl-0872) ? 200 mv input range with single 5 v supply ? 5% internal reference voltage matching ? ofset calibration (with hcpl-0872) ? -40c to +85c operating temperature range ? 15 kv/ s isolation transient immunity ? safety approval: ul 1577, csa and iec/en/din en 60747-5-2 applications ? motor phase and rail current sensing ? data acquisition systems ? industrial process control ? inverter current sensing ? general purpose current sensing and monitoring hcpl-7560 optically isolated sigma-delta ( - ? ) modulator data sheet caution: it is advised that normal static precautions be taken in handling and assembly of this component to prevent damage and/or degradation, which may be induced by esd. lead (pb) free rohs 6 fully compliant rohs 6 fully compliant options available; -xxxe denotes a lead-free product note: a 0.1 ff bypass capacitor must be connected between pins vdd1 and gnd1 and between pins vdd2 and gnd2. si gm a- de lt a mo d. / en co de de co de 1 2 3 4 8 7 6 5 in pu t cu rr en t hc pl - 087 2 or di gi ta l fi lt er mc u or ds p hcpl -7 56 0 - - -
2 pin description 1 2 3 4 8 7 6 5 v dd1 v in + v in - gnd1 v dd 2 mclk mdat gnd2 shield isolation boundary decode sigma- delta mod./ encode hcpl-7560 symbol description v dd1 supply voltage input (4.5 v to 5.5 v) v in+ positive input ( 200mv recommended) v in- negative input (normally connected to gnd1) gnd1 input ground v dd2 supply voltage input (4.5 v to 5.5 v) mclk clock output (10 mhz typical) mdat serial data output gnd2 output ground ordering information hcpl-7560 is ul recognized with 3750 vrms for 1 minute per ul1577. part number option package surface mount gull wing tape & reel iec/en/din en 60747-5-2 quantity rohs compliant non-rohs compliant hcpl-7560 -000e no option 300 mil dip-8 50 per tube -300e -300 x x 50 per tube -500e -500 x x x 1000 per reel -060e -060 x 50 per tube -360e -360 x x x 50 per tube -560e -560 x x x x 1000 per reel to order, choose a part number from the part number column and combine with the desired option from the option column to form an order entry. example 1: HCPL-7560-560E to order product of gull wing surface mount package in tape and reel packaging with iec/en/ din en 60747-5-2 safety approval in rohs compliant. example 2: hcpl-7560 to order product of 300 mil dip-8 package in tube packaging and non-rohs compliant. option datasheets are available. contact your avago sales representative or authorized distributor for information.
3 package outline drawings 8-pin dip package 8-pin gull wing surface mount option 300 0.635 0.25 (0.025 0.010 ) 12 ? nom. 9.65 0.25 (0.380 0.010 ) 0.51 0.130 (0.020 0.005 ) 7.62 0.25 (0.300 0.010) 5 6 7 8 4 3 2 1 9.80 0.25 (0.386 0.010) 6.350 0.25 (0.250 0.010 ) 1.02 (0.040) 1.27 (0.050 ) 10.9 (0.430) 2.0 (0.080) land pattern recommendation 1.080 0.320 (0.043 0.013) 3.56 0.1 3 (0.140 0.005 ) 1.78 0 (0.070 ) max. 1.19 (0.047) max. 2.540 (0.100) bsc 0.255 (0.075 ) 0.010 (0.003 ) note: floating lead protrusion is 0.15 mm (6 mils) max. dimensions in millimeters (inches) . tolerances (unless otherwise specified) : xx.xx = 0.01 xx.xxx = 0.005 lead coplanarity maximum: 0.102 (0.004) molded 9.80 0.25 (0.386 0.010) 1.78 (0.070) max . 1.19 (0.047) max. a 7560 z yyw w date code 1.080 0.320 (0.043 0.013) 2.54 0.25 (0.100 0.010) 0.51 (0.020) min. 0.65 (0.025) max . 4.70 (0.185) max. 2.92 (0.115) min. 5 6 7 8 4 3 2 1 5? typ. 0.20 (0.008) 0.33 (0.013) 7.62 0.25 (0.300 0.010) 6.35 0.25 (0.250 0.010) dimensions in millimeters and (inches). note: floating lead protusion is 0.5 mm (20 mils) max . note: initial or continued variation in the color of the hcpl-7560?s white mold compound is normal and does not affect device performance or reliability. 3.56 0.13 (0.140 0.005) option code * marking code letter for option numbers "v" = option 060 option numbers 300 and 500 not marked.
4 solder refow temperature profle recommended pb-free ir profle 0 time (seconds) temperature (?c) 200 100 50 150 100 200 250 300 0 30 sec. 50 sec. 30 sec. 160?c 140?c 150?c peak temp. 245?c peak temp. 240?c peak temp. 230?c soldering time 200?c preheating time 150?c, 90 + 30 sec. 2.5?c 0.5?c/sec. 3?c + 1?c/-0.5?c tight typical loose room temperature preheating rate 3?c + 1?c/-0.5?c/sec. reflow heating rate 2.5?c 0.5?c/sec. 217 ? c ramp-down 6 ? c/sec. max. ramp-up 3 ? c/sec. max. 150 - 200 ? c 260 +0/-5 ? c t 25 ? c to peak 60 to 150 sec. 20-40 sec. time within 5 ? c of actual peak temperature t p t s preheat 60 to 180 sec. t l t l t smax t smin 25 t p time (seconds) temperature ( ? c) notes: the time from 25 c to peak temperature = 8 minutes max. t smax = 200 ? c, t smin = 150 ? c note: use of non-chlorine-activated fuxes is highly recommended. note: use of non-chlorine-activated fuxes is highly recommended.
5 regulatory information the hcpl-7560 has been approved by the following organizations: iec/en/din en 60747-5-2 approved under: iec 60747-5-2:1997 + a1:2002 en 60747-5-2:2001 + a1:2002 din en 60747-5-2 (vde 0884 teil 2):2003-01. ul approval under ul 1577, component recognition program up to v iso = 3750 v rms . file e55361. csa approval under csa component acceptance notice #5, file ca 88324. iec/en/din en 60747-5-2 insulation characteristics [1] notes: 1. insulation characteristics are guaranteed only within the safety maximum ratings, which must be ensured by protective circuits within the application. surface mount classifcations is class a in accordance with cecc00802. 2. refer to the optocoupler section of the isolation and control components designers catalog, under product safety regulations section, (iec/ en/din en 60747-5-2) for a detailed description of method a and method b partial discharge test profles. 3. refer to the following fgure for dependence of p s and i s on ambient temperature. description symbol hcpl-7560 unit installation classifcation per din vde 0110/1.89, table 1 for rated mains voltage 300 vrms for rated mains voltage 450 vrms for rated mains voltage 600 vrms i - iv i - iii i - ii climatic classifcation 40/85/21 pollution degree (din vde 0110/1.89) 2 maximum working insulation voltage v iorm 891 v peak input to output test voltage, method b [2] v iorm x 1.875=v pr , 100% production test with t m =1 sec, partial discharge < 5 pc v pr 1670 v peak input to output test voltage, method a [2] v iorm x 1.5=v pr , type and sample test, t m =60 sec, partial discharge < 5 pc v pr 1336 v peak highest allowable overvoltage (transient overvoltage t ini = 10 sec) v iotm 6000 v peak safety-limiting values - maximum values allowed in the event of a failure, also see figure 13. case temperature input current [3] output power [3] t s i s, input p s, output 175 400 600 c ma mw insulation resistance at t s , v io = 500 v r s >10 9 w
6 insulation and safety related specifcations parameter symbol hcpl-7560 units conditions minimum external air gap (clearance) l(101) 7.4 mm measured from input terminals to output terminals, shortest distance through air. minimum external tracking (creepage) l(102) 8.0 mm measured from input terminals to output terminals, shortest distance path along body. minimum internal plastic gap (internal clearance) 0.5 mm through insulation distance conductor to conductor, usually the straight line distance thickness between the emitter and detector. tracking resistance (comparative tracking index) cti >175 v din iec 112/vde 0303 part 1 isolation group iiia material group (din vde 0110, 1/89, table 1) option 300 - surface mount classifcation is class a in accordance with cecc 00802. absolute maximum ratings parameter symbol min. max. units note storage temperature t s -55 125 c ambient operating temperature t a -40 85 c supply voltages v dd1 , v dd2 0 5.5 v steady-state input voltage v in+ ,v in- -2.0 v dd1 + 0.5 v 1 two second transient input voltage -6.0 output voltages mclk, mdat -0.5 v dd2 + 0.5 v lead solder temperature 260c for 10 sec., 1.6 mm below seating plane 2 solder refow temperature profle see maximum solder refow thermal profle section recommended operating conditions parameter symbol min. max. units note ambient operating temperature t a -40 +85 c supply voltages v dd1 , v dd2 4.5 5.5 v input voltage v in+ , v in- -200 +200 mv 1 output power - p s , input current - i s 0 0 t a - case temperature - o c 200 50 400 125 25 75 100 150 600 800 200 100 300 500 700 175 p s (mw) i s (ma)
7 electrical specifcations (dc) unless otherwise noted, all specifcations are at v in+ = 0 v and v in- = 0 v, all typical specifcations are at t a = 25c and v dd1 = v dd2 = 5 v, and all minimum and maximum specifcations apply over the following ranges: t a = -40c to +85c, v dd1 = 4.5 to 5.5 v and v dd2 = 4.5 to 5.5 v. electrical specifcations (tested with hcpl-0872 or sinc 3 filter) unless otherwise noted, all specifcations are at v in+ = -200 mv to +200 mv and v in- = 0 v; all typical specifcations are at t a = 25c and v dd1 = v dd2 = 5 v, and all minimum and maximum specifcations apply over the following ranges: t a = -40c to +85c, v dd1 = 4.5 to 5.5 v and v dd2 = 4.5 to 5.5 v. parameter symbol min. typ. max. units conditions fig. note average input bias current i in -0.8 a 1 3 average input resistance r in 450 k w 3 input dc common-mode rejection ratio cmrr in 60 db 4 output logic high voltage v oh 3.9 4.9 v i out = -100 a output logic low voltage v ol 0.1 0.6 v i out = 1.6 ma output short circuit current |i osc | 30 ma v out = v dd2 or gnd2 5 input supply current i dd1 10 20 ma v in+ = -350 mv to +350 mv 2 output supply current i dd2 10 20 ma 3 output clock frequency f clk 7.5 10 15 mhz 4 data hold time t hddat 15 ns 6 parameter symbol min. typ. max. units conditions fig. note static characteristics resolution 15 bits 7 integral nonlinearity inl 64 256 lsb 5 8 0.2 0.8 % 6 8 diferential nonlinearity dnl 1 lsb 9 uncalibrated input ofset v os -6 0 6 mv v in+ = 0 v 7 ofset drift vs. temperature dv os /dt a 2 35 v/c v in+ = 0 v 7 10 ofset drift vs. vdd1 dv os /dv dd1 0.12 mv/v v in+ = 0 v 7 internal reference voltage v ref 320 mv 8 absolute reference voltage tolerance -5 5 % 8 vref drift vs. temperature dv ref /dt a 150 ppm/c. 8 vref drift vs. vdd1 dv ref /dv dd1 0.2 % 8 full scale input range -v ref +v ref mv 11 recommended input voltage range -200 +200 mv
8 dynamic characteristics (digital interface ic hcpl-0872 is set to conversion mode 5.) * the input-output momentary withstand voltage is a dielectric voltage rating that should not be interpreted as an input-output continuous voltage rating. for the continuous voltage rating refer to the iec/en/din en 60747-5-2 insulation characteristics table (if applicable), your equipment level safety specifcation, or avago technologies application note 1074, optocoupler input-output endurance voltage. package characteristics parameter symbol min. typ. max. units conditions note input-output momentary withstand voltage* v iso 3750 vrms rh 50%, t = 1 min; t a = 25c 19, 20 input-output resistance r i-o 10 9 w v i-o = 500 vdc 20 input-output capacitance c i-o 1.4 pf f = 1 mhz 20 parameter symbol min. typ. max. units conditions fig. note signal-to-noise ratio snr 53 db v in+ = 35 hz, 400 mv pk-pk (141 mvrms) sine wave. 9,10 total harmonic distortion thd -51 db signal-to-(noise + distortion) snd 50 db efective number of bits enob 8 bits 11 12 conversion time t c2 0.2 0.8 s pre-trigger mode 2 1,12 13 t c1 5 8 s pre-trigger mode 1 1,12 13 t c0 10 16 s pre-trigger mode 0 1,12 signal delay t dsig 5 s 13 14 over-range detect time t ovr1 2.0 3.0 4.2 s v in+ = 0 to 400mv step waveform 14 15 threshold detect time (default confguration) t thr1 10 s 16 signal bandwidth bw 90 khz 15 17 isolation transient immunity cmr 15 20 kv/s v iso = 1 kv 18
9 notes: 1. if v in- (pin 3) is brought above v dd1 - 2 v with respect to gnd1 an internal optical-coupling test mode may be activated. this test mode is not intended for customer use. 2. avago technologies recommends the use of non-chlorinated sol - der fuxes. 3. because of the switched-capacitor nature of the isolated modula - tor, time averaged values are shown. 4. cmrr in is defned as the ratio of the gain for diferential inputs ap - plied between v in+ and v in- to the gain for common-mode inputs applied to both v in+ and v in- with respect to input ground gnd1. 5. short-circuit current is the amount of output current generated when either output is shorted to v dd2 or gnd2. use under these conditions is not recommended. 6. data hold time is amount of time that the data output mdat will stay stable following the rising edge of output clock mclk. 7. resolution is defned as the total number of output bits. the use - able accuracy of any a/d converter is a function of its linearity and signal-to-noise ratio, rather than how many total bits it has. 8. integral nonlinearity is defined as one-half the peak-to-peak deviation of the best-ft line through the transfer curve for v in+ = -200 mv to +200 mv, expressed either as the number of lsbs or as a percent of measured input range (400 mv). 9. diferential nonlinearity is defned as the deviation of the actual diference from the ideal diference between midpoints of succes - sive output codes, expressed in lsbs. 10. data sheet value is the average magnitude of the diference in of - set voltage from t a =25c to t a = 85c, expressed in microvolts per c. three standard deviation from typical value is less than 6 v/c. 11. beyond the full-scale input range the output is either all zeroes or all ones. 12. the efective number of bits (or efective resolution) is defned by the equation enob = (snr-1.76)/6.02 and represents the resolu - tion of an ideal, quantization-noise limited a/d converter with the same snr. 13. conversion time is defned as the time from when the convert start signal cs is brought low to when sdat goes high, indicating that output data is ready to be clocked out. this can be as small as a few cycles of the isolated modulator clock and is determined by the frequency of the isolated modulator clock and the selected conversion and pre-trigger modes. for determining the true signal delay characteristics of the a/d converter for closed-loop phase margin calculations, the signal delay specifcation should be used. 14. signal delay is defned as the efective delay of the input signal through the isolated a/d converter. it can be measured by ap - plying a -200 mv to 200 mv step at the input of modulator and adjusting the relative delay of the convert start signal cs so that the output of the converter is at mid scale. the signal delay is the elapsed time from when the step signal is applied at the input to when output data is ready at the end of the conversion cycle. the signal delay is the most important specifcation for determin - ing the true signal delay characteristics of the a/d converter and should be used for determining phase margins in closed-loop applications. the signal delay is determined by the frequency of the modulator clock and which conversion mode is selected, and is independent of the selected pre-trigger mode and, therefore, conversion time. 15. the minimum and maximum overrange detection time is deter - mined by the frequency of the channel 1 isolated modulator clock. 16. the minimum and maximum threshold detection time is deter - mined by the user-defned confguration of the adjustable thresh - old detection circuit and the frequency of the channel 1 isolated modulator clock. see the applications information section for fur - ther detail. the specifed times apply for the default confguration. 17. the signal bandwidth is the frequency at which the magnitude of the output signal has decreased 3 db below its low-frequency value. the signal bandwidth is determined by the frequency of the modulator clock and the selected conversion mode. 18. the isolation transient immunity (also known as common-mode rejection) specifes the minimum rate-of-rise of an isolation-mode signal applied across the isolation boundary beyond which the modulator clock or data signals are corrupted. 19. in accordance with ul1577, for devices with minimum v iso speci - fed at 3750 v rms , each isolated modulator (optocoupler) is proof- tested by applying an insulation test voltage greater than 4500 v rms for one second (leakage current detection limit i i-o < 5 a). this test is performed before the method b, 100% production test for partial discharge shown in iec/en/din en 60747-5-2 insulation characteristics table. 20. this is a two-terminal measurement: pins 1-4 are shorted together and pins 5-8 are shorted together.
10 figure 1. i in vs. v in . figure 2. i dd1 vs. v in . figure 3. i dd2 vs. v in . figure 4. clock frequency vs. temperature. figure 5. inl (bits) vs. temperature figure 6. inl (%) vs. temperature figure 7. ofset change vs. temperature figure 8. v ref change vs. temperature figure 9. snr vs. temperature i dd1 - ma v in - mv 9.0 8.5 -200 10.5 200 8.0 9.5 -40 o c 10.0 -400 400 0 25 o c 85 o c i dd2 - ma v in - mv 8.6 8.2 -200 9.4 200 8.0 8.8 -40 o c 9.2 -400 400 0 25 o c 85 o c 8.4 9.0 clock frequency - mhz temperature - o c 9.2 -15 10.0 60 8.6 9.4 9.8 -40 85 10 35 8.8 9.0 9.6 v dd1 = 4.5 v v dd1 = 5.0 v v dd1 = 5.5 v inl-ls b temperature - o c 4 -15 7 60 2 5 v dd1 = 4.5 v 6 -40 85 10 35 v dd1 = 5.0 v v dd1 = 5.5 v 3 inl-% temperature - ?c 0.012 -15 0.02 60 0.006 0.014 v dd1 = 4.5 v 0.016 -40 85 10 35 v dd1 = 5.0 v v dd1 = 5.5 v 0.008 0.018 0.01 offset change - v temperature - ?c -50 -15 150 60 -150 0 v dd1 = 4.5 v 100 -40 85 10 35 v dd1 = 5.0 v v dd1 = 5.5 v -100 50 v ref change - % temperature - ?c 0 -1 5 0. 8 60 -0.4 0. 2 v dd1 = 4.5 v 0. 6 -4 0 8 5 10 35 v dd1 = 5.0 v v dd1 = 5.5 v -0.2 0. 4 i in - ma v in - v -4 -5 -4 1 0 -9 -2 0 -6 6 -2 2 -1 -3 -8 -6 -7 4 snr temperature - ?c 64 62 -15 68 60 61 65 v dd1 = 4.5 v 67 -40 85 10 35 v dd1 = 5.0 v v dd1 = 5.5 v 63 66
11 figure 10. snr vs. conversion mode. figure 11. efective resolution vs. conversion mode. figure 12. conversion time vs. conversion mode. figure 13. signal delay vs. conversion mode. figure 14. over-range and threshold detect times. figure 15. signal bandwidth vs. conversion mode. snr conversion mode # 60 2 80 3 45 70 75 55 50 65 1 4 5 conversion time - s conversion mode # 100 80 2 200 3 0 140 pre-trigger mode 2 180 1 160 120 60 40 20 pre-trigger mode 0 pre-trigger mode 1 4 5 signal delay - s conversion mode # 40 2 100 3 0 80 1 90 30 20 60 70 50 10 4 5 effective resolution (# bits) conversion mode # 11 2 14 3 8 12 1 13 10 9 4 5 2 s/div. v in + (200 mv/div.) ovr1 (200 mv/div.) thr1 (2 v/div.) signal bandwidth - khz conversion mode # 40 2 100 3 0 80 1 90 30 20 60 70 50 10 4 5
12 applications information digital current sensing as shown in figure 16, using the isolated 2-chip a/d converter to sense current can be as simple as connect - ing a current-sensing resistor, or shunt, to the input and reading output data through the 3-wire serial output interface. by choosing the appropriate shunt resistance, any range of current can be monitored, from less than 1 a to more than 100 a. figure 16. typical application circuit. r shunt 0.02 input current v dd1 isolated + 5 v v in + v in - gnd1 v dd2 mclk mdat gnd2 c1 0.1 f + cdat sclk cclk v dd clat chan mclk1 sdat mdat1 cs mclk2 thr1 mdat2 ovr1 gnd reset non-isolated + 5 v c3 10 f + hcpl-7560 3-wire serial interface c2 0.1 f hcpl-0872 even better performance can be achieved by fully utiliz - ing the more advanced features of the isolated a/d con - verter, such as the pre-trigger circuit, which can reduce conversion time to less than 1 s, the fast over-range detector for quickly detecting short circuits, diferent conversion modes giving various resolution/speed trade-ofs, ofset calibration mode to eliminate initial ofset from measurements, and an adjustable threshold detector for detecting non-short circuit overload condi - tions.
13 product description the hcpl-7560 isolated modulator (optocoupler) uses sigma-delta modulation to convert an analog input signal into a high-speed (10 mhz) single-bit digital data stream; the time average of the modulators single-bit data is directly proportional to the input signal. the isolated modulators other main function is to provide galvanic isolation between the analog input and the digital output. an internal voltage reference determines the full-scale analog input range of the modulator (ap - proximately 320 mv); an input range of 200 mv is recommended to achieve optimal performance. hcpl-7560 can be used together with hcpl-0872, digital interface ic or a digital flter. the primary func - tions of the hcpl-0872 digital interface ic are to derive a multi-bit output signal by averaging the single-bit modulator data, as well as to provide a direct micro- controller interface. the effective resolution of the multi-bit output signal is a function of the length of time (measured in modulator clock cycles) over which the average is taken; averaging over longer periods of time results in higher resolution. the digital interface ic can be confgured for fve conversion modes, which have diferent combinations of speed and resolution to achieve the desired level of performance. other functions of the hcpl-0872 digital interface ic include a phase locked loop based pre-trigger circuit that can either give more precise control of the efective sampling time or reduce conversion time to less than 1 s, a fast over-range detection circuit that rapidly indi - cates when the magnitude of the input signal is beyond full-scale, an adjustable threshold detection circuit that indicates when the magnitude of the input signal is above a user adjustable threshold level, an ofset calibration circuit, and a second multiplexed input that allows a second isolated modulator to be used with a single digital interface ic. the digital output format of the isolated a/d converter is 15 bits of unsigned binary data. the input full-scale range and code assignment is shown in table 1 below. although the output contains 15 bits of data, the efec - tive resolution is lower and is determined by selected conversion mode as shown in table 2 below. table 1. input full-scale range and code assignment. notes: bold italic type indicates default values. table 2. isolated a/d converter typical performance characteristics. conversion mode signal-to-noise ratio (db) efective resolution (bits) conversion time (s) signal delay(s) signal bandwidth (khz) pre-trigger mode 0 1 2 1 83 13.5 205 102 0.2 102 3.4 2 79 12.8 103 51 51 6.9 3 73 11.9 39 19 19 22 4 66 10.7 20 10 10 45 5 53 8.5 10 5 5 90 analog input voltage input digital output full scale range 640 mv 32768 lsbs minimum step size 20 v 1 lsb +full scale +320 mv 111111111111111 zero 0 mv 100000000000000 -full scale -320 mv 000000000000000
14 power supplies and bypassing the recommended application circuit is shown in figure 17. a foating power supply (which in many ap - plications could be the same supply that is used to drive the high-side power transistor) is regulated to 5 v using a simple zener diode (d1); the value of resistor r1 should be chosen to supply sufcient current from the existing foating supply. the voltage from the cur - rent sensing resistor or shunt (rsense) is applied to the input of the hcpl-7560 (u2) through an rc anti-aliasing flter (r2 and c2). and fnally, the output clock and data of the isolated modulator are connected to the digital interface ic. although the application circuit is relatively simple, a few recommendations should be followed to ensure optimal performance. the power supply for the isolated modulator is most often obtained from the same supply used to power the power transistor gate drive circuit. if a dedicated supply is required, in many cases it is possible to add an ad - ditional winding on an existing transformer. otherwise, some sort of simple isolated supply can be used, such as a line powered transformer or a high-frequency dc- dc converter. an inexpensive 78l05 three-terminal regulator can also be used to reduce the foating supply voltage to 5 v. to help attenuate high-frequency power supply noise or ripple, a resistor or inductor can be used in series with the input of the regulator to form a low-pass flter with the regulators input bypass capacitor. as shown in figure 17, 0.1 f bypass capacitors (c1 and c3) should be located as close as possible to the input and output power-supply pins of the isolated modula - tor (u2). the bypass capacitors are required because of the high-speed digital nature of the signals inside the isolated modulator. a 0.01 f bypass capacitor (c2) is also recommended at the input due to the switched- capacitor nature of the input circuit. the input bypass capacitor also forms part of the anti-aliasing flter, which is recommended to prevent high-frequency noise from aliasing down to lower frequencies and interfering with the input signal. figure 17. recommended application circuit. + - motor hv- hv+ r sense floating positive supply gate drive circuit v dd1 v in + v in - gnd1 v dd2 mclk mdat gnd2 cdat sclk cclk v dd clat chan mclk1 sdat mdat1 cs mclk2 thr1 mdat2 ovr1 gnd reset + 5 v hcpl-7560 to control circuit c3 0.1 f c1 0.1 f c2 0.01 f r2 39 ? r1 d1 5.1 v hcpl-0872
15 pc board layout the design of the printed circuit board (pcb) should follow good layout practices, such as keeping bypass capacitors close to the supply pins, keeping output signals away from input signals, the use of ground and power planes, etc. in addition, the layout of the pcb can also afect the isolation transient immunity (cmr) of the isolated modulator, due primarily to stray capacitive coupling between the input and the output circuits. to obtain optimal cmr performance, the layout of the pc board should minimize any stray coupling by maintain - ing the maximum possible distance between the input and output sides of the circuit and ensuring that any ground or power plane on the pc board does not pass directly below or extend much wider than the body of the isolated modulator. shunt resistors the current-sensing shunt resistor should have low resistance (to minimize power dissipation), low induc - tance (to minimize di/dt induced voltage spikes which could adversely afect operation), and reasonable toler - ance (to maintain overall circuit accuracy). choosing a particular value for the shunt is usually a compromise between minimizing power dissipation and maximiz - ing accuracy. smaller shunt resistances decrease power dissipation, while larger shunt resistances can improve circuit accuracy by utilizing the full input range of the isolated modulator. the frst step in selecting a shunt is determining how much current the shunt will be sens - ing. the graph in figure 18 shows the rms current in each phase of a three-phase induction motor as a func - tion of average motor output power (in horsepower, hp) and motor drive supply voltage. the maximum value of the shunt is determined by the current being measured and the maximum recommended input voltage of the isolated modulator. the maximum shunt resistance can be calculated by taking the maximum recommended input voltage and dividing by the peak current that the shunt should see during normal operation. for example, if a motor will have a maximum rms current of 10 a and can experience up to 50% overloads during normal op - eration, then the peak current is 21.1 a (= 10 x 1.414 x 1.5). assuming a maximum input voltage of 200 mv, the maximum value of shunt resistance in this case would be about 10 m w . the maximum average power dissipation in the shunt can also be easily calculated by multiplying the shunt resistance times the square of the maximum rms cur - rent, which is about 1 w in the previous example. figure 18. motor output horsepower vs. motor phase current and supply voltage. 15 5 40 15 20 25 30 25 motor phase current - a (rms) 10 30 motor output power - horsepower 5 3 5 0 0 440 380 220 120 10 20 35 if the power dissipation in the shunt is too high, the resistance of the shunt can be decreased below the maximum value to decrease power dissipation. the minimum value of the shunt is limited by precision and accuracy requirements of the design. as the shunt value is reduced, the output voltage across the shunt is also reduced, which means that the ofset and noise, which are fxed, become a larger percentage of the signal amplitude. the selected value of the shunt will fall somewhere between the minimum and maximum values, depending on the particular requirements of a specifc design. when sensing currents large enough to cause signif - cant heating of the shunt, the temperature coefcient (tempco) of the shunt can introduce nonlinearity due to the signal dependent temperature rise of the shunt. the efect increases as the shunt-to-ambient thermal resis - tance increases. this efect can be minimized either by reducing the thermal resistance of the shunt or by us - ing a shunt with a lower tempco. lowering the thermal resistance can be accomplished by repositioning the shunt on the pc board, by using larger pc board traces to carry away more heat, or by using a heat sink. for a two-terminal shunt, as the value of shunt resis - tance decreases, the resistance of the leads becomes a signifcant percentage of the total shunt resistance. this has two primary efects on shunt accuracy. first, the ef - fective resistance of the shunt can become dependent on factors such as how long the leads are, how they are bent, how far they are inserted into the board, and how far solder wicks up the lead during assembly (these is - sues will be discussed in more detail shortly). second, the leads are typically made from a material such as copper, which has a much higher tempco than the ma - terial from which the resistive element itself is made, resulting in a higher tempco for the shunt overall. both of these efects are eliminated when a four-terminal shunt is used. a four-terminal shunt has two additional terminals that are kelvin-connected directly across the
16 shunt connections the recommended method for connecting the isolated modulator to the shunt resistor is shown in figure 17. v in+ (pin 2 of the hpcl-7560) is connected to the posi - tive terminal of the shunt resistor, while v in- (pin 3) is shorted to gnd1 with the power-supply return path functioning as the sense line to the negative terminal of the current shunt. this allows a single pair of wires or pc board traces to connect the isolated modulator circuit to the shunt resistor. by referencing the input circuit to the negative side of the sense resistor, any load cur - rent induced noise transients on the shunt are seen as a common-mode signal and will not interfere with the current-sense signal. this is important because the large load currents fowing through the motor drive, along with the parasitic inductances inherent in the wiring of the circuit, can generate both noise spikes and ofsets that are relatively large compared to the small voltages that are being measured across the current shunt. if the same power supply is used both for the gate drive circuit and for the current sensing circuit, it is very im - portant that the connection from gnd1 of the isolated modulator to the sense resistor be the only return path for supply current to the gate drive power supply in order to eliminate potential ground loop problems. the only direct connection between the isolated modulator circuit and the gate drive circuit should be the positive power supply line. resistive element itself; these two terminals are used to monitor the voltage across the resistive element while the other two terminals are used to carry the load cur - rent. because of the kelvin connection, any voltage drops across the leads carrying the load current should have no impact on the measured voltage. several four-terminal shunts from isotek (isabellen - htte) suitable for sensing currents in motor drives up to 71 arms (71 hp or 53 kw) are shown in table 3; the maximum current and motor power range for each of the pbv series shunts are indicated. for shunt resis - tances from 50 m w down to 10 m w , the maximum cur - rent is limited by the input voltage range of the isolated modulator. for the 5 m w and 2 m w shunts, a heat sink may be required due to the increased power dissipation at higher currents. when laying out a pc board for the shunts, a couple of points should be kept in mind. the kelvin connections to the shunt should be brought together under the body of the shunt and then run very close to each other to the input of the isolated modulator; this minimizes the loop area of the connection and reduces the pos - sibility of stray magnetic felds from interfering with the measured signal. if the shunt is not located on the same pc board as the isolated modulator circuit, a tightly twisted pair of wires can accomplish the same thing. also, multiple layers of the pc board can be used to increase current carrying capacity. numerous plated- through vias should surround each non-kelvin terminal of the shunt to help distribute the current between the layers of the pc board. the pc board should use 2 or 4 oz. copper for the layers, resulting in a current carrying capacity in excess of 20 a. making the current carrying traces on the pc board fairly large can also improve the shunts power dissipation capability by acting as a heat sink. liberal use of vias where the load current enters and exits the pc board is also recommended.
17 table 3. isotek (isabellenhtte) four-terminal shunt summary. in some applications, however, supply currents fowing through the power-supply return path may cause ofset or noise problems. in this case, better performance may be obtained by connecting v in+ and v in- directly across the shunt resistor with two conductors, and connecting gnd1 to the shunt resistor with a third conductor for the power-supply return path, as shown in figure 19. when connected this way, both input pins should be bypassed. to minimize electromagnetic interference of the sense signal, all of the conductors (whether two or three are used) connecting the isolated modulator to the sense resistor should be either twisted pair wire or closely spaced traces on a pc board. figure 19. schematic for three conductor shunt connection. shunt resistor part num shunt resistance tol. maximum rms current motor power range 120 v ac -440 v ac m w % a hp kw pbv-r050-0.5 50 0.5 3 0.8 - 3 0.6 - 2 pbv-r020-0.5 20 0.5 7 2 - 7 0.6 - 2 pbv-r010-0.5 10 0.5 14 4 - 14 3 - 10 pbv-r005-0.5 5 0.5 25 [28] 7 - 25 [8 - 28] 5 - 19 [6 - 21] pbv-r002-0.5 2 0.5 39 [71] 11 - 39 [19 - 71] 8 - 29 [14 - 53] the 39 w resistor in series with the input lead (r2) forms a lowpass anti-aliasing filter with the 0.01 f input bypass capacitor (c2) with a 400 khz bandwidth. the resistor performs another important function as well; it dampens any ringing which might be present in the circuit formed by the shunt, the input bypass capacitor, and the inductance of wires or traces connecting the two. undamped ringing of the input circuit near the input sampling frequency can alias into the baseband producing what might appear to be noise at the output of the device. + - motor hv- hv+ r sense floating positive supply gate drive circuit v dd1 v in + v in - gnd1 v dd2 mclk mdat gnd2 hcpl-7560 c1 0.1 f c2a 0.01 f r2a 39 ? r1 d1 5.1 v c2b 0.01 f r2b 39 ? note: values in brackets are with a heatsink for the shunt.
voltage sensing the hcpl-7560 isolated modulator can also be used to isolate signals with amplitudes larger than its recom - mended input range with the use of a resistive voltage divider at its input. the only restrictions are that the impedance of the divider be relatively small (less than 1 k w ) so that the input resistance (280 k w ) and input bias current (1 a) do not afect the accuracy of the mea - surement. an input bypass capacitor is still required, although the 39 w series damping resistor is not (the resistance of the voltage divider provides the same function). the low-pass flter formed by the divider re - sistance and the input bypass capacitor may limit the achievable bandwidth. to obtain higher bandwidth, the input bypass capacitor (c2) can be reduced, but it should not be reduced much below 1000 pf to maintain adequate input bypassing of the isolated modulator. for product information and a complete list of distributors, please go to our web site: www.avagotech.com avago, avago technologies, and the a logo are trademarks of avago technologies, limited in the united states and other countries. data subject to change. copyright ? 2006 avago technologies limited. all rights reserved. obsoletes 5989-2164en av02-0408en - june 18, 2007

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