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1 el5411t 60mhz rail-to-rail input-ou tput operational amplifier el5411t the el5411t is a high voltage rail-to-rail input-output amplifier with low power consumption. the el5411t contains four amplifiers. each amplifier exhibits beyond the rail input capability, rail-to-rail output capability and is unity gain stable. the maximum operating voltage range is from 4.5v to 19v. it can be configured for single or dual supply operation, and typically consumes only 3ma per amplifier. the el5411t has an output short circuit capability of 300ma and a continuous output current capability of 70ma. the el5411t features a high slew rate of 100v/s, and fast settling time. also, the device provides common mode input capability beyond the supply rails, rail-to-rail output capability, and a band width of 60mhz (-3db). this enables the amplifiers to offer maximum dynamic range at any supply voltage. these features make the el5411t an ideal amplifier solution for use in tft-lcd panels as a v com driver or static gamma buffer, and in high speed filtering and signal conditioning applications. other applications include battery power and portable devices, especially where low power consumption is important. the el5411t is available in a 14 ld htssop and a space saving thermally enhanced 16 ld 4mmx4mm tqfn package. the device operates over an ambient temperature range of -40c to +85c. features ? 60mhz (-3db) bandwidth ? 4.5v to 19v maximum supply voltage range ?100v/s slew rate ? 3ma supply current (per amplifier) ? 70ma continuous output current ? 300ma output short circuit current ? unity-gain stable ? beyond the rails input capability ? rail-to-rail output swing ? built-in thermal protection ? -40c to +85c ambient temperature range ? pb-free (rohs compliant) applications ?tft-lcd panels ?v com amplifiers ? static gamma buffers ? drivers for a/d converters ? data acquisition ? video processing ? audio processing ? active filters ?test equipment ? battery-powered applications ? portable equipment pin configurations el5411t (16 ld 4x4 tqfn) top view el5411t (14 ld htssop) top view thermal pad connects to vs- 1 2 3 4 12 11 10 9 5 6 7 8 16 15 14 13 vina- vina+ vs+ vinb+ vinb- voutb voutc vinc- nc vouta voutd nc vind- vind+ vs- vinc+ thermal pad - + - + - + - + vs- vs+ vinb+ vinb- voutb vina+ vina- vouta vinc+ vinc- voutc vind+ vind- voutd 1 2 3 4 14 13 12 11 5 6 7 10 9 8 thermal pad connects to vs- caution: these devices are sensitive to electrostatic discharge; follow proper ic handling procedures. 1-888-intersil or 1-888-468-3774 | intersil (and design) is a registered trademark of intersil americas inc. copyright intersil americas inc. 2009, 2010. all rights reserved all other trademarks mentioned are the property of their respective owners. august 3, 2010 fn6837.2
2 fn6837.2 el5411t pin descriptions el5411t (14 ld htssop) el5411t (16 ld tqfn) pin name function equivalent circuit 1 15 vouta amplifier a output (reference circuit 1) 2 1 vina- amplifier a inverting input (reference circuit 2) 3 2 vina+ amplifier a non-invert ing input (reference circuit 2) 4 3 vs+ positive power supply 5 4 vinb+ amplifier b non-inverting input (reference circuit 2) 6 5 vinb- amplifier b inverting input (reference circuit 2) 7 6 voutb amplifier b output (reference circuit 1) 8 7 voutc amplifier c output (reference circuit 1) 9 8 vinc- amplifier c inverting input (reference circuit 2) 10 9 vinc+ amplifier c non-invert ing input (reference circuit 2) 11 10 vs- negative power supply (connects to gnd for single supply operation) 12 11 vind+ amplifier d non-invert ing input (reference circuit 2) 13 12 vind- amplifier d invertin g input (reference circuit 2) 14 14 voutd amplifier d output (reference circuit 1) 13, 16 nc not connected pad pad thermal pad functi ons as a heat sink. connects to most negative potential, vs- v s+ gnd v s- circuit 1 v s+ v s- circuit 2 v out v in ordering information part number (notes 1, 2, 3) part marking package (pb-free) pkg. dwg. # el5411tirez 5411tire z 14 ld htssop m14.173a el5411tilz 5411til z 16 ld tqfn l16.4x4f notes: 1. add ?t7? or ?t13? suffix for ta pe and reel. please refer to tb347 for details on reel specifications. 2. these intersil pb-free plastic packaged products employ special pb-free material sets, molding compounds/die attach materials, and 100% matte tin pl ate plus anneal (e3 termination finish, which is rohs compliant and compatible with both snpb and pb-free soldering operations). inte rsil pb-free products are msl classified at pb-free peak reflow temperatures that meet or exceed the pb-free requirements of ipc/jedec j std-020. 3. for moisture sensitivity level (msl), please see device information page for el5411t . for more information on msl please see techbrief tb363 .
3 fn6837.2 important note: all parameters having min/max specifications are guaranteed. typ values are for information purposes only. unles s otherwise noted, all tests are at the specified temperature and are pulsed tests, therefore: t j = t c = t a absolute maximum ratings (t a = +25c) thermal information supply voltage between v s + and v s - . . . . . . . . . . . .+19.8v input voltage range (v inx+ , v inx- ) . v s - - 0.5v, v s + + 0.5v input differential voltage (v inx+ - v inx- ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (v s + + 0.5v)-(v s - - 0.5v) maximum continuous output curre nt . . . . . . . . . . .70ma esd rating human body model . . . . . . . . . . . . . . . . . . . . . . . 3000v thermal resistance (typical) ja (c/w) jc (c/w) 14 ld htssop (notes 4, 5) . . . 38 8 16 ld tqfn (notes 4, 5) . . . . . 40 8.5 storage temperature . . . . . . . . . . . . . . . . -65c to +150c ambient operating temperature . . . . . . . . . -40c to +85c maximum junction temperature . . . . . . . . . . . . . . . +150c power dissipation . . . . . . . . . . . . . . . see figures 32 and 33 pb-free reflow profile . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/pb-freereflow.asp caution: do not operate at or near the maximum ratings listed for extended periods of time. exposure to such conditions may adv ersely impact product reliability and result in failures not covered by warranty. notes: 4. ja is measured in free air with the component mounted on a high ef fective thermal conductivity test board with ?direct attach? fe atures. see tech brief tb379. 5. for jc , the ?case temp? location is the center of the exposed metal pad on the package underside. electrical specifications v s + = +5v, v s - = -5v, r l = 1k to 0v, t a = +25c, unless otherwise specified. parameter description conditions min typ max unit input characteristics v os input offset voltage v cm = 0v 3.5 17 mv tcv os average offset voltage drift (note 6) 14 ld htssop package 26 v/c 16 ld tqfn package 4 v/c i b input bias current v cm = 0v 2 60 na r in input impedance 1g c in input capacitance 2pf cmir common-mode input range -5.5 +5.5 v cmrr common-mode rejection ratio for v in from -5.5v to 5.5v 50 73 db a vol open-loop gain -4.5v v outx 4.5v 62 78 db output characteristics v ol output swing low i l = -5ma -4.94 -4.85 v v oh output swing high i l = +5ma 4.85 4.94 v i sc short-circuit current v cm = 0v, source: v outx short to v s -, sink: v outx short to v s + 300 ma i out output current 70 ma power supply performance (v s +) - (v s -) supply voltage range 4.5 19 v i s supply current v cm = 0v, no load 11 15 ma psrr power supply rejection ratio supply is moved from 2.25v to 9.5v 60 75 db dynamic performance sr slew rate (note 7) -4.0v v outx 4.0v, 20% to 80% 100 v/s t s settling to +0.1% (note 8) a v = +1, v outx = 2v step, r l = 1k || 1k (probe), c l = 1.5pf 85 ns bw -3db bandwidth r f = 1k , c l = 1.5pf 60 mhz gbwp gain-bandwidth product a v = -10, r f = 1k , r g = 100 r l = 1k || 1k (probe), c l = 1.5pf 32 mhz el5411t
4 fn6837.2 el5411t pm phase margin a v = -10, r f = 1k , r g = 100 r l = 1k || 1k (probe), c l = 1.5pf 50 cs channel separation f = 5mhz 90 db electrical specifications v s + = +5v, v s - = -5v, r l = 1k to 0v, t a = +25c, unless otherwise specified. parameter description conditions min typ max unit electrical specifications v s + = +5v, v s - = 0v, r l = 1k to 2.5v, t a = +25c, unless otherwise specified. parameter description condition min typ max unit input characteristics v os input offset voltage v cm = 2.5v 3.5 17 mv tcv os average offset voltage drift (note 6) 14 ld htssop package 23 v/c 16 ld tqfn package 3 v/c i b input bias current v cm = 2.5v 2 60 na r in input impedance 1g c in input capacitance 2pf cmir common-mode input range -0.5 +5.5 v cmrr common-mode rejection ratio for v in from -0.5v to 5.5v 45 68 db a vol open-loop gain 0.5v v outx 4.5v 62 82 db output characteristics v ol output swing low i l = -4.2ma 60 150 mv v oh output swing high i l = +4.2ma 4.85 4.94 v i sc short-circuit current v cm = 2.5v, source: v outx short to v s -, sink: v outx short to v s + 110 ma i out output current 70 ma power supply performance (v s +) - (v s -) supply voltage range 4.5 19 v i s supply current v cm = 2.5v, no load 12 15 ma psrr power supply rejection ratio supply is moved from 4.5v to 19v 60 75 db dynamic performance sr slew rate (note 7) 1v v outx 4v, 20% to 80% 75 v/s t s settling to +0.1% (note 8) a v = +1, v outx = 2v step, r l = 1k || 1k (probe), c l = 1.5pf 90 ns bw -3db bandwidth r f = 1k , c l = 1.5pf 60 mhz gbwp gain-bandwidth product a v = -10, r f = 1k , r g = 100 r l = 1k || 1k (probe), c l = 1.5pf 32 mhz pm phase margin a v = -10, r f = 1k , r g = 100 r l = 1k || 1k (probe), c l = 1.5pf 50 cs channel separation f = 5mhz 90 db
5 fn6837.2 el5411t electrical specifications v s + = +18v, v s - = 0v, r l = 1k to 9v, t a = +25c, unless otherwise specified. parameter description condition min typ max unit input characteristics v os input offset voltage v cm = 9v 3.5 17 mv tcv os average offset voltage drift (note 6) 14 ld htssop package 21 v/c 16 ld tqfn package 5 v/c i b input bias current v cm = 9v 2 60 na r in input impedance 1g c in input capacitance 2pf cmir common-mode input range -0.5 +18.5 v cmrr common-mode rejection ratio for v in from -0.5v to 18.5v 53 75 db a vol open-loop gain 0.5v v outx 17.5v 62 104 db output characteristics v ol output swing low i l = -6ma 80 150 mv v oh output swing high i l = +6ma 17.85 17.92 v i sc short-circuit current v cm = 9v, source: v outx short to v s -, sink: v outx short to v s + 300 ma i out output current 70 ma power supply performance (v s +) - (v s -) supply voltage range 4.5 19 v i s supply current v cm = 9v, no load 12.3 15 ma psrr power supply rejection ratio supply is moved from 4.5v to 19v 60 75 db dynamic performance sr slew rate (note 7) 1v v outx 17v, 20% to 80% 100 v/s t s settling to +0.1% (note 8) a v = +1, v outx = 2v step, r l = 1k || 1k (probe), c l = 1.5pf 100 ns bw -3db bandwidth r f = 1k , c l = 1.5pf 60 mhz gbwp gain-bandwidth product a v = -10, r f = 1k , r g = 100 r l = 1k || 1k (probe), c l = 1.5pf 32 mhz pm phase margin a v = -10, r f = 1k , r g = 100 r l = 1k || 1k (probe), c l = 1.5pf 50 cs channel separation f = 5mhz 90 db notes: 6. measured over -40c to +85c ambient operating temperature range. see the typical tcv os production distri bution shown in the ?typical performan ce curves? on page 6. 7. typical slew rate is an average of the slew rates measured on the rising (20% to 80%) and the falling (80% to 20%) edges of the output signal. 8. settling time measured as the time from when the output leve l crosses the final value on rising/falling edge to when the outp ut level settles within a 0.1% error band. the range of the error band is determined by: final value(v)[full scale(v)*0.1%].
6 fn6837.2 typical performance curves figure 1. input offset voltage distribution fi gure 2. input offset voltage drift (htssop) figure 3. input offset voltage drift (tqfn) fi gure 4. input offset voltage vs temperature figure 5. input bias current vs temperature f igure 6. output high voltage vs temperature 0 100 200 300 400 500 600 700 800 900 -15-13-11 -9 -7 -5 -3 -1 1 3 5 7 9 11 13 15 input offset voltage (mv) typical production distribution v s = 5v t a = +25c quantity (amplifiers) 0 2 4 6 8 10 12 14 16 3 9 15 21 27 33 39 45 51 57 input offset voltage drift (v/c) quantity (amplifiers) v s = 5v -40c to +85c typical production distribution 0 5 10 15 20 25 0 101112131415 input offset voltage drift (v/c) quantity (amplifiers) v s = 5v -40c to +85c typical production distribution 9 8 7 6 5 4 3 2 1 -3.5 -3.0 -2.5 -2.0 -1.5 -1.0 -0.5 0.0 -50 0 50 100 150 temperature (c) input offset voltage (mv) v s = 5v 6.0 6.5 7.0 7.5 8.0 -50 0 50 100 temperature (c) input bias current (na) v s = 5v 150 4.88 4.90 4.92 4.94 4.96 -50 0 50 100 150 temperature (c) output high voltage (v) v s = 5v i out = +5ma el5411t
7 fn6837.2 figure 7. output low voltage vs temperature figure 8. open-loop gain vs temperature figure 9. slew rate vs temperature figure 10. supply current per amplifier vs temperature figure 11. supply current per amplifier vs supply voltage figure 12. slew rate vs supply voltage typical performance curves (continued) -4.96 -4.95 -4.94 -4.93 -4.92 -4.91 -4.90 -50 0 50 100 150 temperature (c) output low voltage (v) v s = 5v i out = -5ma 20 40 60 80 100 120 -50 0 50 100 150 temperature (c) open loop gain (db) v s = 5v r l = 1k 60 70 80 90 100 110 120 130 -50 0 50 100 150 temperature (c) slew rate (v/s) v s = 5v r l = 1k 2.65 2.70 2.75 2.80 2.85 -50 0 50 100 150 temperature (c) supply current (ma) v s = 5v no load inputs at gnd 2.0 2.5 3.0 3.5 4.0 2.5 3.5 4.5 5.5 6.5 7.5 8.5 9.5 supply voltage (v) supply current (ma) t a = +25c no load inputs at gnd 40 60 80 100 120 140 210 supply voltage (v) slew rate (v/s) t a = +25c a v = 1 r l = 1k c l = 8pf 8 6 4 el5411t
8 fn6837.2 figure 13. open loop gain vs supply voltage figure 14. open loop gain and phase vs frequency figure 15. open loop gain and phase vs frequency figure 16. frequency re sponse for various r l figure 17. frequency response for various c l figure 18. closed loop output impedance vs frequency typical performance curves (continued) 40 60 80 100 120 140 210 supply voltage (v) open loop gain (db) t a = +25c r l = 1k 8 6 4 -20 0 20 40 60 80 100 10 100 1k 10k 100k 1m 10m 100m frequency (hz) open loop gain (db) -40 0 40 80 120 160 200 phase () gain phase v s = 5v r f = 5k , r g = 100 r l = 1k c l = 8pf -20 0 20 40 60 80 100 10 100 1k 10k 100k 1m 10m 100m frequency (hz) open loop gain (db) -40 0 40 80 120 160 200 phase () gain phase v s = 5v r f = 1k r g = 100 r l = 1k || 1k (probe) c l = 1.5pf -10 -8 -6 -4 -2 0 2 4 6 8 10 100k 1m 10m 100m frequency (hz) gain (db) v s = 5v a v = 1 c l = 1.5pf r l || 1k (probe) 1k 560 150 -20 -15 -10 -5 0 5 10 15 20 100k 1m 10m 100m frequency (hz) gain (db) v s = 5v a v = 1 r l = 1k 1000pf 100pf 47pf 10pf 0 50 100 150 200 250 300 350 400 450 10k 100k 1m 10m 100m frequency (hz) output impedance ( ) v s = 5v a v = 1 r l = open v outx = +15dbm el5411t
9 fn6837.2 figure 19. maximum output swing vs frequency figure 20. harmonic distortion vs v op-p figure 21. cmrr vs frequency figure 22. psrr vs frequency figure 23. input voltage noise spectral density vs frequency figure 24. channel sepa ration vs frequency typical performance curves (continued) 0 2 4 6 8 10 12 10k 100k 1m 10m 100m frequency (hz) maximum output swing (v p-p ) v s = 5v a v = 1 r l = 1k distortion <1% -90 -80 -70 -60 -50 -40 -30 010 output voltage (v op-p ) distortion (dbc) 2nd hd 3rd hd v s = 5v a v = 2 r l = 1k f in = 1mhz 8 6 4 2 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 1k 10k 100k 1m 10m 100m frequency (hz) cmrr (db) v s = 5v t a = +25c v inx = -10dbm -90 -80 -70 -60 -50 -40 -30 -20 -10 0 1k 10k 100k 1m 10m 100m frequency (hz) psrr (db) psrr- psrr+ v s = 5v t a = +25c 1 10 100 1000 100 1k 10k 100k 1m 10m 100m frequency (hz) voltage noise (nv/ hz) t a = +25c -140 -120 -100 -80 -60 -40 -20 10k 100k 1m 10m 100m frequency (hz) xtalk(db) measured ch a to d, or b to c other combinations yield improved rejection v s = 5v a v = 1 v inx = 0dbm el5411t
10 fn6837.2 figure 25. small-signal overshoot vs load capacitance figure 26. step size vs settling time figure 27. large signal transient response figure 28. small signal transient response figure 29. basic test circuit typical performance curves (continued) 0 20 40 60 80 100 10 100 1k load capacitance (pf) overshoot (%) v s = 5v t a = +25c a v = 1 r l = 1k v inx = 50mv -5 -4 -3 -2 -1 0 1 2 3 4 5 70 80 90 settling time (ns) step size (v) v s = 5v t a = +25c a v = 1 r l = 1k || 1k (probe) c l =1.5pf 6v step 50ns/div 1v/div v s = 5v t a = +25c a v = 1 r l = 1k || 1k (probe) c l = 1.5pf 50ns/div 100mv step 50mv/div v s = 5v t a = +25c a v = 1 r l = 1k || 1k (probe) c l = 1.5pf c la r la 49.9 voutd c ld r ld c lc r lc 4.7f 0.1f + voutb c lb r lb 49.9 49.9 vs- 4.7f 0.1f + vinc+ 49.9 0 0 0 0 vina+ vouta thermal pad connected to vs- voutc vs+ el5411t (14 ld htssop shown) vinb+ vind+ vouta vina- vina+ vs+ vinb+ vinb- voutb voutd vind- vind+ vs- vinc+ vinc- voutc 1 2 3 4 5 6 7 14 13 12 11 10 9 8 el5411t
11 fn6837.2 applications information product description the el5411t is a high voltage rail-to-rail input-output amplifier with low power consumption. the el5411t contains four amplifiers. each amplifier exhibits beyond the rail input capability, rail-to-rail output capability and is unity gain stable. the el5411t features a high slew rate of 100v/s, and fast settling time. also, the device provides common mode input capability beyond the supply rails, rail-to-rail output capability, and a band width of 60mhz (-3db). this enables the amplifiers to offer maximum dynamic range at any supply voltage. operating voltage, input and output capability the el5411t can operate on a single supply or dual supply configuration. the el5411t operating voltage ranges from a minimum of 4.5v to a maximum of 19v. this range allows for a standard 5v (or 2.5v) supply voltage to dip to -10%, or a standard 18v (or 9v) to rise by +5.5% without affecting performance or reliability. the input common-mode voltage range of the el5411t extends 500mv beyond the supply rails. also, the el5411t is immune to phase reversal. however, if the common mode input voltage exceeds the supply voltage by more than 0.5v, electrostatic protection diodes in the input stage of the device begin to conduct. even though phase reversal will not occur, to maintain optimal reliability it is suggested to avoid input overvoltage conditions. figure 30 shows the input voltage driven 500mv beyond the supply rails and the device output swinging between the supply rails. the el5411t output typically swings to within 50mv of positive and negative supply rails with load currents of 5ma. decreasing load currents will extend the output voltage range even closer to the supply rails. figure 31 shows the input and output waveforms for the device in a unity-gain configuration. operation is from 5v supply with a 1k load connected to gnd. the input is a 10v p-p sinusoid and the output voltage is approximately 9.9v p-p . refer to the ?electrical specifications? table beginning on page 3 for specific device parameters. parameter variations with operating voltage, loading and/or temperature are shown in the ?typical performance curves? on page 6. output current the el5411t is capable of output short circuit currents of 300ma (source and sink), and the device has built-in protection circuitry which limits the short circuit current to 300ma (typical). to maintain maximum reliability, the continuous output current should never exceed 70ma. this 70ma limit is determined by the characteristics of the internal metal interconnects. also, see ?power dissipation? on page 12 for detailed information on ensuring proper device operation and reliability for temperature and load conditions. unused amplifiers it is recommended that any unused amplifiers be configured as a unity gain follower. the inverting input should be directly connected to the output and the non-inverting input tied to the ground. figure 30. operation with beyond-the-rails input 10s/div 1v/div input output v s = 2.5v, t a = +25c, a v = 1, v inx = 6v p-p, r l = 1k to gnd figure 31. operation with rail-to-rail input and output 5v/div 10 s/ div input output v s = 5v, t a = +25c, a v = 1, v inx = 10v p-p, r l = 1k to gnd el5411t
12 fn6837.2 driving capacitive loads as load capacitance increase s, the -3db bandwidth will decrease and peaking can occur. depending on the application, it may be necessary to reduce peaking and to improve device stability. to improve device stability a snubber circuit or a series resistor may be added to the output of the el5411t. a snubber is a shunt load consisting of a resistor in series with a capacitor. an optimized snubber can improve the phase margin and the stability of the el5411t. the advantage of a snubber circuit is that it does not draw any dc load current or reduce the gain. another method to reduce peaking is to add a series output resistor (typically between 1 to 10 ). depending on the capacitive loading, a small value resistor may be the most appropriate choice to minimize any reduction in gain. power dissipation with the high-output drive capability of the el5411t amplifiers, it is possible to exceed the +150c absolute maximum junction temperature under certain load current conditions. it is important to calculate the maximum power dissipation of the el5411t in the application. proper load conditions will ensure that the el5411t junction temperature stays within a safe operating region. the maximum power dissipation allowed in a package is determined according to equation 1: where: ?t jmax = maximum junction temperature ?t amax = maximum ambient temperature ? ja = thermal resistance of the package ?p dmax = maximum power dissipation allowed the total power dissipation produced by an ic is the total quiescent supply current times the total power supply voltage, plus the power dissipation in the ic due to the loads, or: when sourcing, and: when sinking, where: ?i = 1 to 4 (1, 2, 3, 4 corresponds to channel a, b, c, d respectively) ?v s = total supply voltage ( v s + - v s - ) ?v s + = positive supply voltage ?v s - = negative supply voltage ?i smax = maximum supply current per amplifier (i smax = el5411t quiescent current 4) ?v out = output voltage ?i load = load current device overheating can be avoided by calculating the minimum resistive load condition, r load , resulting in the highest power dissi pation. to find r load set the two p dmax equations equal to each other and solve for v out /i load . reference the package power dissipation curves, figures 32 and 33, for further information. p dmax t jmax t amax ? ja -------------------------------------------- - = (eq. 1) p dmax iv [ s i smax v ( s +v out i ) i load i ? + ] = (eq. 2) p dmax iv [ s i smax v ( out iv s - ) i load i ? + ] = (eq. 3) 0.0 0.2 0.4 0.6 0.8 1.0 1.2 0 255075100125150 ambient temperature (c) power dissipation (w) figure 32. package power dissipation vs ambient temperature jedec jesd51-3 low effective thermal conductivity test board 85 ja = +130c/w tqfn16 ja = +140c/w htssop14 893mw 962mw 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 0 25 50 75 100 125 150 ambient temperature (c) power dissipation (w) figure 33. package power dissipation vs ambient temperature jedec jesd51-7 high effective thermal conductivity (4-layer) test board - exposed die pad soldered to pcb per jesd51-5 85 ja = +40c/w tqfn16 ja = +38c/w htssop14 3.29w 3.13w el5411t
13 fn6837.2 thermal shutdown the el5411t has a built-in thermal protection which ensures safe operation and prevents internal damage to the device due to overheating. when the die temperature reaches +165c (typical) the device automatically shuts off the outputs by putting them in a high impedance state. when the die cools by +15c (typical) the device automatically turns on the outputs by putting them in a low impedance (normal) operating state. power supply bypassing and printed circuit board layout the el5411t can provide gain at high frequency, so good printed circuit board layout is necessary for optimum performance. ground plane construction is highly recommended, trace lengths should be as short as possible and the power supply pins must be well bypassed to reduce any risk of oscillation. for normal single supply operation (the v s - pin is connected to ground) a 4.7f capacitor should be placed from v s + to ground, then a parallel 0.1f capacitor should be connected as close to the amplifier as possible. one 4.7f capacitor may be used for multiple devices. for dual supply operation the same capacitor combination should be placed at each supply pin to ground. it is highly recommended that el5411t exposed thermal pad packages should always have the pad connected to the lowest potential, v s -, to optimize thermal and operating performance. pcb vias should be placed below the device?s exposed thermal pad to transfer heat to the v s - plane and away from the device. el5411t
14 intersil products are manufactured, assembled and tested utilizing iso9000 qu ality systems as noted in the quality certifications found at www.intersil.com/design/quality intersil products are sold by description only. intersil corporation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, th e reader is cautioned to verify that data sheets are current before placing orders. information furnished by intersil is believed to be accura te and reliable. however, no re sponsibility is assumed by inte rsil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which ma y result from its use. no licen se is granted by implication o r otherwise under any patent or patent rights of intersil or its subsidiaries. for information regarding intersil corporation and its products, see www.intersil.com fn6837.2 for additional products, see www.intersil.com/product_tree products intersil corporation is a leader in the design and manuf acture of high-performance analog semiconductors. the company's products address some of the industry's fastest growing markets, such as, flat panel displays, cell phones, handheld products, and notebooks. intersil's product families address power management and analog signal processing functions. go to www.intersil.com/products for a complete list of intersil product families. *for a complete listing of applications, related documentat ion and related parts, please see the respective device information page on intersil.com: el5411t to report errors or suggestions for this datasheet, please go to www.intersil.com/askourstaff fits are available from our website at http://rel.intersil.com/reports/search.php revision history the revision history provided is for informational purposes only an d is believed to be accurate, but not warranted. please go t o web to make sure you have the latest rev. date revision change 8/3/10 fn6837.2 converted to new intersil data sheet template. changed theta jc for 16 ld tqfn in ?therm al information? on page 3 from ?9? to ?8.5? corrected theta ja note 4 from " ja is measured in free air with the component mounted on a high effective therma l conductivity test board." to " ja is measured in free air with the component mounted on a high effective thermal conductivity test board with ?dir ect attach? features." numbered notes in ?ordering informatio n? on page 2 and added msl note 3. moved ?ordering information? from page 1 to page 2 and ?pin configurations? from page 2 to page 1. moved ?pin de scriptions? from page 11 to page 2. added ?products? on page 14. updated ?package outline drawing? on page 15 (m14.173a). added land pad for exposed die attach pad. 10/8/09 fn6837.1 updated ordering information by removing ?contact factory for availability?. add "vs frequency" to the plot titles in fig 14,15,18,21,22,23,24: fig 21: changed y-axis label to read "cmrr (db)" fig 22: changed y-axis la bel to read "psrr (db)" fig 26: changed label to read "step size vs settling time" changed 1st sentence in pa ges 1 and 12 from ?the el5411t is a low power, high voltage rail-to-rail input-output amplifier? to ?the el5411t is a high voltage rail- to-rail input-output amplifier with low power consumption?. updated package outline drawing m14. 173a to add land pattern and move dimensions from table onto drawing 8/21/09 fn6837.0 initial release. el5411t
15 fn6837.2 el5411t package outline drawing l16.4x4f 16 lead thin quad flat no-lead plastic package rev 0, 04/09 located within the zone indicated. the pin #1 indentifier may be unless otherwise specified, tolerance : decimal 0.05 tiebar shown (if present) is a non-functional feature. the configuration of the pin #1 id entifier is optional, but must be between 0.15mm and 0.30mm from the terminal tip. dimension applies to the metallized terminal and is measured dimensions in ( ) for reference only. dimensioning and tolerancing conform to amse y14.5m-1994. 6. either a mold or mark feature. 3. 5. 4. 2. dimensions are in millimeters. 1. notes: bottom view detail "x" side view typical recommended land pattern top view 2 . 70 0 . 05 see detail "x" 0.30 0 . 05 pin #1 index area 5 8 ( 3 . 8 typ ) ( 2 . 70 typ ) ( 12x 0 . 65 ) ( 16x 0 .30 ) ( 16 x 0 . 6 ) 0 . 75 0 . 05 16x 0 . 4 0 . 05 0 . 2 ref 0 . 00 min. 0 . 05 max. c 5 4 0.10 c m index area (4x) 0.15 pin 1 6 4.00 12 4.00 9 a b 4 0.65 12x 13 4x 1.95 16 1 6 0.08 c c 0.10 c ab
16 fn6837.2 el5411t package outline drawing m14.173a 14 lead heat-sink thin shrink small outline package (htssop) rev 2, 10/09 c bottom view detail "x" typical recommended land pattern top view side view end view b a 17 8 14 plane seating 0.10 c 0.10 c b a h pin #1 i.d. mark 5.00 0.10 4.40 0.10 0.25 +0.05/-0.06 6.40 0.20 c b a 0.05 3.20 0.10 3.00 0.10 0- 8 gauge plane see 0.90 +0.15/-0.10 0.60 0.15 0.09-0.20 5 2 3 1 3 1.00 ref 0.65 1.20 max 0.25 0.05 min 0.15 max exposed thermal pad detail "x" (1.45) (5.65) (0.65 typ) (0.35 typ) (3.20) (3.00) 1. dimension does not include mold flash, protrusions or gate burrs. mold flash, protrusions or gate burrs shall not exceed 0.15 per side. 2. dimension does not include interlead flash or protrusion. interlead flash or protrusion shall not exceed 0.25 per side. 3. dimensions are measured at datum plane h. 4. dimensioning and tolerancing per asme y14.5m-1994. 5. dimension does not include dambar protrusion. allowable protrusion shall be 0.80mm total in excess of dimension at maximum material condition. minimum space between protrusion and adjacent lead is 0.07mm. 6. dimension in ( ) are for reference only. 7. conforms to jedec mo-153, variation ab-1. notes:

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