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acpl-p314 and acpl-w314 0.6 amp output current igbt gate driver optocoupler data sheet description the acpl-p314/w314 consists of a gaasp led optically coupled to an integrated circuit with a power output stage. these optocouplers are ideally suited for driving power igbts and mosfets used in motor control inverter applications. the high operating voltage range of the output stage provides the drive voltages required by gate controlled devices. the voltage and current supplied by this optocoupler makes it ideally suited for directly driving small or medium power igbts. applications isolated igbt/power mosfet gate drive ac and brushless dc motor drives industrial inverters inverter for home appliances induction cooker switching power supplies (sps) functional diagram features high speed response. ultra high cmr. bootstrappable supply current. available in stretched so-6 package package clearance/creepage at 8mm (acpl-w314) safety approval: ul1577 recognized with 3750 vrms for 1 minute for acpl-p314 and 5000 vrms for 1 minute for acpl- w314. csa approved. iec/en/din en 60747-5-5 approved v iorm = 891vpeak for acpl-p314 v iorm = 1140vpeak for acpl-w314 speci?cations 0.6 a maximum peak output current. 0.4 a minimum peak output current. 0.7 s maximum propagation delay over temperature range. i cc(max) = 3 ma maximum supply current. 10 kv/s minimum common mode rejection (cmr) at v cm = 1000 v. wide v cc operating range: 10 v to 30 v over tempera- ture range. wide operating tempera ture range: C40c to 100c. note: a 0.1 f bypass capacitor must be connected between pins v cc and vee. 6 1 5 2 4 3 anode n.c. cathode v cc v o v ee shield truth table led vo off low on high caution: it is advised that normal static precautions be taken in handling and assembly of this component to prevent damage and/or degradation which may be induced by esd. lead (pb) free rohs 6 fully compliant r o hs 6 f u lly comp l iant option s avai l a bl e ; -xxxe d enote s a l ea d-f ree pro d uct
2 ordering information acpl-p314 is ul recognized with 3750 vrms for 1 minute per ul1577. acpl-w314 is ul recognized with 5000 vrms for 1 minute per ul1577. part number option package surface mount tape & reel ul 5000 vrms / 1 minute rating iec/en/din en 60747-5-5 quantity rohs compliant acpl-p314 -000e stretched so-6 x 100 per tube -500e x x 1000 per reel -060e x x 100 per tube -560e x x x 1000 per reel acpl-w314 -000e stretched so-6 x x 100 per tube -500e x x x 1000 per reel -060e x x x 100 per tube -560e x x x x 1000 per reel to order, choose a part number from the part number column and combine with the desired option from the option column to form an order entry. example 1: acpl-p314-560e to order product of stretched so-6 surface mount package in tape and reel packaging with iec/en/din en 60747-5-5 safety approval in rohs compliant. example 2: acpl-p314-000e to order product of stretched so-6 surface mount package in tube packaging and rohs compli- ant. option datasheets are available. contact your avago sales representative or authorized distributor for information. remarks: the notation #xxx is used for existing products, while (new) products launched since 15th july 2001 and rohs compliant option will use -xxxe.
3 package outline drawings acpl-p314 stretched so-6 package dimensions in millimeters [inches] coplanarity = 0.1mm [0.004 inches] 0.380.127 [.015.005] 1.27[.050] bsg 4.580 +0.254 0 .180 +.010 - .000 0.45 .018 7.62 6.81 .300 .268 [.063.005] 1.5900.127 a [.382.010] 9.70.250 3.1800.127 7.00 45.00 7.00 7.00 7.00 [.040.010] 1.0.250 0.200.10 [.008.004] 0.20[.008] 2.16[.085] 10.7[.421] [.125.005] land pattern recommendation acpl-w314 stretched so-6 package
4 table 1. iec/en/din en 60747-5-5 insulation related characteristics * (acpl-p314/w314 option 060) description symbol acpl-w14 acpl-p314 units installation classi?cation per din vde 0110/1.89, table 1 for rated mains voltage 150 vrms for rated mains voltage 300 vrms for rated mains voltage 450 vrms for rated mains voltage 600 vrms for rated mains voltage 1000 vrms i-iv i-iv i-iv i-iv i-iii i-iv i-iv i-iii i-iii climatic classi?cation 55/100/21 55/100/21 pollution degree (din vde 0110/1.89) 2 2 maximum working insulation voltage v iorm 1140 891 v peak input to output test voltage, method b* v iorm x 1.875 = v pr , 100% production test with t m = 1 sec partial discharge < 5 pc, v pr 2137 1670 v peak input to output test voltage, method a* v iorm x 1.5 = v pr , type and sample test, t m = 60 sec, partial discharge < 5 pc v pr 1710 1336 v peak highest allowable overvoltage* (transient overvoltage, t ini = 10 sec) v iotm 8000 6000 v peak safety limiting values (maximum values allowed in the event of a failure) case temperature input current** output power ** t s i s,input p s,output 175 230 600 175 230 600 c ma mw insulation resistance at t s , v io = 500 v r s 10 9 10 9 * refer to the optocoupler section of the isolation and control components designers catalog, under product safety regulations section, (iec/en/din en 60747-5-5) for a detailed description of method a and method b partial discharge test pro?les. ** refer to the following ?gure for dependence of p s and i s on ambient temperature. recommended pb-free ir pro?le recommended re?ow condition as per jedec standard, j-std-020 (latest revision). non-halide flux should be used. regulatory information the acpl-p314/w314 is approved by the following organizations: iec/en/din en 60747-5-5 (option 060 only) approval under: iec 60747-5-5:2007 ul approval under ul 1577 component recognition program up to v iso = 3750 v rms for the acpl-p314 and v iso = 5000 v rms for the acpl-w314, file e55361. csa approval under csa component acceptance notice #5, file ca 88324.
5 table 2. insulation and safety related speci?cations parameter symbol acpl- unit conditions p314 w314 minimum external air gap (external clearance) l(101) 7.0 8.0 mm measured from input terminals to output termi- nals, shortest distance through air. minimum external tracking (external creepage) l(102) 8.0 8.0 mm measured from input terminals to output termi- nals, shortest distance path along body. minimum internal plastic gap (internal clearance) 0.08 0.08 mm through insulation distance conductor to con- ductor, usually the straight line distance thick- ness between the emitter and detector. minimum internal tracking (internal creepage) na na mm measured from input terminals to output termi- nals, along internal cavity. tracking resistance (comparative tracking index) cti >175 >175 v din iec 112/vde 0303 part 1 isolation group iiia iiia material group (din vde 0110, 1/89, table 1) table 3. absolute maximum ratings parameter symbol min. max. units note storage temperature t s -55 125 c operating temperature t a -40 100 c average input current i f(avg) 25 ma 1 peak transient input current (<1 s pulse width, 300pps) i f(tran) 1.0 a reverse input voltage v r 5v high peak output current i oh(peak) 0.6 a 2 low peak output current i ol(peak) 0.6 a 2 supply voltage v cc - v ee -0.5 35 v output voltage v o(peak) -0.5 v cc v output power dissipation p o 250 mw 3 input power dissipation p i 45 mw 4 lead solder temperature 260c for 10 sec., 1.6 mm below seating plane solder re?ow temperature pro?le see package outline drawings section table 4. recommended operating conditions parameter symbol min. max. units note power supply v cc - v ee 10 30 v input current (on) i f(on) 812ma input voltage (off) v f(off) - 3.6 0.8 v operating temperature t a - 40 100 c notes: 1. derate linearly above 70c free air temperature at a rate of 0.3 ma/c. 2. maximum pulse width = 10 s, maximum duty cycle = 0.2%. this value is intended to allow for component tolerances for designs with i o peak minimum = 0.4 a. see application section for additional details on limiting i ol peak. 3. derate linearly above 85c, free air temperature at the rate of 4.0 mw/c. 4. input power dissipation does not require derating.
6 table 5. electrical speci?cations (dc) over recommended operating conditions unless otherwise speci?ed. parameter symbol min. typ. max. units test conditions fig. note high level output current i oh 0.2 a v o = v cc - 4 2 1 0.4 0.5 a v o = v cc - 10 3 2 low level output current i ol 0.2 0.4 a v o = v ee + 2.5 5 1 0.4 0.5 a v o = v ee + 10 6 2 high level output voltage v oh v cc -4 v cc -1.8 v i o = -100 ma 1 3, 4 low level output voltage v ol 0.41v i o = 100 ma 4 high level supply current i cch 0.73mai o = 0 ma 7, 8 5 low level supply current i ccl 1.23mai o = 0 ma 7, 8 5 threshold input current low to high i flh 7mai o = 0 ma, v o > 5 v 9, 15 threshold input voltage high to low v fhl 0.8 v i o = 0 ma, v o > 5 v input forward voltage v f 1.2 1.5 1.8 v i f = 10 ma 16 temperature coe?cient of input forward voltage v f / t a -1.6 mv/c i f = 10 ma input reverse breakdown voltage bv r 5vi r = 10 a input capacitance c in 60 pf f = 1 mhz, v f = 0 v table 6. switching speci?cations (ac) over recommended operating conditions unless otherwise speci?ed. parameter symbol min. typ. max. units test conditions fig. note propagation delay time to high output level t plh 0.1 0.2 0.7 s r g = 47 , c g = 3 nf, f = 10 khz, duty cycle = 50%, i f = 8 ma, v cc = 30 v 10, 11, 12, 13, 14, 17 6 propagation delay time to low output level t phl 0.1 0.3 0.7 s 6 propagation delay di?erence between any two parts or channels pdd -0.5 0.5 s 7 rise time t r 50 ns fall time t f 50 ns output high level common mode transient immunity |cm h | 10 kv/s t a = 25c, v cm = 1000 v 18 8 output low level common mode transient immunity |cm l | 10 kv/s 18 9 notes: 1. maximum pulse width = 50 s, maximum duty cycle = 0.5%. 2. maximum pulse width = 10 s, maximum duty cycle = 0.2%. this value is intended to allow for component tolerances for designs with i o peak minimum = 0.4 a. see application section for additional details on limiting i ol peak. 3. in this test, v oh is measured with a dc load current. when driving capacitive load v oh will approach v cc as i oh approaches zero amps. 4. maximum pulse width = 1 ms, maximum duty cycle = 20%. 5. the power supply current increases when operating frequency and q g of the driven igbt increases. 6. this load condition approximates the gate load of a 1200 v/25 a igbt. 7. pdd is the di?erence between t phl and t plh between any two parts or channels under the same test conditions. 8. common mode transient immunity in the high state is the maximum tolerable |dv cm /dt| of the common mode pulse v cm to assure that the output will remain in the high state (i.e. v o > 6.0 v). 9. common mode transient immunity in a low state is the maximum tolerable |dv cm /dt| of the common mode pulse, v cm , to assure that the output will remain in a low state (i.e. v o < 1.0 v).
7 table 7. package characteristics parameter symbol min. typ. max. units test conditions fig. note input-output momentary withstand voltage acpl-p314 v iso 3750 v rms t a = 25c, rh < 50% for 1 min. 1, 3 acpl-w314 5000 2, 3 input-output resistance r i-o 10 12 v i-o = 500 v 3 input-output capacitance c i-o 0.6 pf freq=1 mhz notes: 1. in accordance with ul 1577, each optocoupler is proof tested by applying an insulation test voltage > 4500 v rms for 1 second (leakage detection current limit i i-o < 5 a). this test is performed before 100% production test for partial discharge (method b) shown in the iec/en/din en 60747-5-5 insulation characteristics table, if applicable. 2. in accordance with ul 1577, each optocoupler is proof tested by applying an insulation test voltage > 6000 vrms for 1 second (leakage detection current limit ii-o < 5 a). this test is performed before 100% production test for partial discharge (method b) shown in the iec /en/din en 60747- 5-5 insulation characteristics table, if applicable. 3. device considered a two-terminal device: pins on input side shorted together and pins on output side shorted together.
8 figure 1. v oh vs. temperature. figure 2. i oh vs. temperature. figure 3. v oh vs. i oh . figure 4. v ol vs. temperature. figure 5. i ol vs. temperature. figure 6. v ol vs. i ol .
9 figure 7. i cc vs. temperature. figure 8. i cc vs. v cc . figure 9. i flh vs. temperature. figure 10. propagation delay vs. v cc . figure 11. propagation delay vs. i f . figure 12. propagation delay vs. temperature.
10 + - 500 i f = 7 to 16 ma + - v cc = 15 to 30 v 47 3 nf v o 6 1 5 2 4 3 0.1 f 10 khz 50% duty cycle + - + - cc + - + - figure 13. propagation delay vs. rg. figure 14. propagation delay vs. cg. figure 15. transfer characteristics. figure 16. input current vs. forward voltage. figure 17. propagation delay test circuit and waveforms. figure 18. cmr test circuit and waveforms. a + - i f + - v cc = 30v v o 6 1 5 2 4 3 0.1 f v cm = 1000v 5 v + - b + - + - + - + - + - + -
11 applications information eliminating negative igbt gate drive to keep the igbt ?rmly o?, the acpl-p314/w314 has a very low maximum v ol speci?cation of 1.0 v. minimizing r g and the lead inductance from the acpl-p314/w314 to the igbt gate and emitter (possibly by mounting the acpl-p314/w314 on a small pc board directly above the igbt) can eliminate the need for negative igbt gate drive in many applications as shown in figure 19. care should be taken with such a pc board design to avoid routing the igbt collector or emitter traces close to the acpl- p314/w314 input as this can result in unwanted coupling of transient signals into the input of acpl-p314/w314 and degrade performance. (if the igbt drain must be routed near the acpl-p314/w314 input, then the led should be reverse biased when in the o? state, to prevent the transient signals coupled from the igbt drain from turning on the acpl-p314/w314. selecting the gate resistor (rg) step 1: calculate r g minimum from the i ol peak speci?- cation. the igbt and r g in figure 19 can be analyzed as a simple rc circuit with a voltage supplied by the acpl- p314/w314. r g 270 v cc = 24v + - 6 1 5 2 4 3 0.1 f +5 v control input 74 xxx open collector + hvd c -hvd c 3-pha se ac q 1 q 2 acpl-p314 /w 314 + - 1 figure 19. recommended led drive and application circuit for acpl-p314/w314 figure 20. energy dissipated in the acpl-p314/w314 and for each igbt switching cycle. step 2: check the acpl-p314/w314 power dissipation and increase r g if necessary. the acpl-p314/w314 total power dissipation (p t ) is equal to the sum of the emitter power (p e ) and the output power (p o ). the v ol value of 5 v in the previous equation is the v ol at the peak current of 0.6a. (see figure 6). where k icc q g f is the increase in i cc due to switching and k icc is a constant of 0.001 ma/(nc*khz). for the circuit in figure 19 with i f (worst case) = 10 ma, r g = 32 , max duty cycle = 80%, q g = 100 nc, f = 20 khz and t amax = 85c: the value of 3 ma for i cc in the previous equation is the max. i cc over entire operating temperature range. since p o for this case is less than p o(max) , r g = 32 is alright for the power dissipation. 32 0.6 32 ? 5 i v v r olpea k ol c g = = ? ( r ) ? f )( r ) f q ; e v f q k q ; e v i p p du t ycyc l e v p p p g g sw cc g i cc ccb i as g g sw cc cc o(sw it c hi ng) o(b i as) o f f e o e t ? + ? ? ? + = ( i + ? = + = p ? ? = i + = p @ 85 c) 0.4 j ? 20 k hz = 1 28 mw 250 mw ( p p p o(ma x ) o e = ( 3 ma + ( 0.00 1 ma/nc ? k hz ) ? 20 k hz ? 1 00 nc) ? 24v + = 1 0 ma ? 1 .8v ? 0.8 = 1 4 mw
12 led drive circuit considerations for ultra high cmr per- formance without a detector shield, the dominant cause of opto- coupler cmr failure is capacitive coupling from the input side of the optocoupler, through the package, to the detector ic as shown in figure 21. the acpl-p314/w314 improves cmr performance by using a detector ic with an optically transparent faraday shield, which diverts the capacitively coupled current away from the sensitive ic circuitry. however, this shield does not eliminate the ca- pacitive coupling between the led and optocoupler pins 5-8 as shown in figure 22. this capacitive coupling causes perturbations in the led current during common mode transients and becomes the major source of cmr failures for a shielded optocoupler. the main design objective of a high cmr led drive circuit becomes keeping the led in the proper state (on or o? ) during common mode tran- sients. for example, the recommended application circuit (figure 19), can achieve 10 kv/ s cmr while minimizing component complexity. techniques to keep the led in the proper state are discussed in the next two sections. cmr with the led o? (cmrl) a high cmr led drive circuit must keep the led o? (v f v f(off) ) during common mode transients. for example, during a -dv cm /dt transient in figure 23, the current ?owing through c ledp also ?ows through the r sat and v sat of the logic gate. as long as the low state voltage developed across the logic gate is less than v f(off) the led will remain o? and no common mode failure will occur. figure 21. optocoupler input to output capacitance model for unshielded optocouplers. figure 22. optocoupler input to output capacitance model for shielded optocouplers. c ledp c ledn 6 1 5 2 4 3 c ledp c ledn 6 1 5 2 4 3 c ledp c ledn 6 1 5 2 4 3 shield c led01 c led02 c ledp c ledn 6 1 5 2 4 3 shield c led01 c led02 c ledp c ledn 6 1 5 2 4 3 shield i ledp r g v cc = 18v + - 0.1 f + - the arro w s indicate the direction of current flo w during - dv cm /dt +5 v v sat + - v cm i + - + - v sat + - v sat + - ? ? c ledp c ledn 6 1 5 2 4 3 shield i ledp r g v cc = 18v + - 0.1 f + - ? the arro w s indicate the direction ? of current flo w during - dv cm /dt +5 v v sat + - v cm i ledp + - + - figure 23. equivalent circuit for figure 17 during common mode transient. cmr with the led on (cmr h ) a high cmr led drive circuit must keep the led on during common mode transients. this is achieved by overdriving the led current beyond the input threshold so that it is not pulled below the threshold during a transient. a minimum led current of 8 ma provides adequate margin over the maximum i flh of 5 ma to achieve 10 kv/s cmr. the open collector drive circuit, shown in figure 24, can not keep the led o? during a +dv cm /dt transient, since all the current ?owing through cledn must be supplied by the led, and it is not recommended for applications requiring ultra high cmr1 performance. the alternative drive circuit which like the recommended application circuit (figure 19), does achieve ultra high cmr perfor- mance by shunting the led in the o? state. figure 24. not recommended open collector drive circuit. c ledp c ledn 6 1 5 2 4 3 shield i ledn +5 v q 1 c ledp c ledn 6 1 5 2 4 3 shield i ledn +5 v q 1 q 1
13 figure 25. recommended led drive circuit for ultra-high cmr dead time and propagation delay speci?cations. c ledp c ledn 6 1 5 2 4 3 shield +5 v c ledp c ledn 6 1 5 2 4 3 +5 v dead time and propagation delay speci?cations the acpl-p314/w314 includes a propagation delay dif- ference (pdd) speci?cation intended to help designers minimize dead time in their power inverter designs. dead time is the time high and low side power transistors are o?. any overlap in ql and q2 conduction will result in large currents ?owing through the power devices from the high voltage to the low-voltage motor rails. to minimize dead time in a given design, the turn on of led2 should be delayed (relative to the turn o? of led1) so that under worst-case conditions, transistor q1 has just turned o? when transistor q2 turns on, as shown in figure 26. the amount of delay necessary to achieve this condition is equal to the maximum value of the propa- gation delay di?erence speci?cation, pdd max, which is speci?ed to be 500 ns over the operating temperature range of -40 to 100c. figure 26. minimum led skew for zero dead time. figure 27. waveforms for dead time. delaying the led signal by the maximum propagation delay di?erence ensures that the minimum dead time is zero, but it does not tell a designer what the maximum dead time will be. the maximum dead time is equivalent to the di?erence between the maximum and minimum propagation delay di?erence speci?cation as shown in figure 27. the maximum dead time for the acpl-p314/ w314 is 1 s (= 0.5 s - (-0.5 s)) over the operating tem- perature range of C40c to 100c. note that the propagation delays used to calculate pdd and dead time are taken at equal temperatures and test conditions since the optocouplers under consideration are typically mounted in close proximity to each other and are switching identical igbts.
for pro d uct in f ormation an d a complete li s t o f d i s tri b utor s , plea s e go to our we b s ite: www.avagotech.com avago, avago technologie s , an d the a logo are tra d emark s o f avago technologie s , in the unite d s tate s an d other countrie s . data s u b ject to change. cop y right ? 2005 - 2010 avago technologie s . all right s re s erve d . o bs olete s av01 - 0634en av02 - 0158en - march 3, 2010 description this thermal model assumes that an 6-pin single-channel plastic package optocoupler is soldered into a 7.62 cm x 7.62 cm printed circuit board (pcb). the temperature at the led and detector junctions of the optocoupler can be calculated using the equations below. t 1 = (r 11 * p 1 + r 12 * p 2 ) + t a -- (1) t 2 = (r 21 * p 1 + r 22 * p 2 ) + t a -- (2) j edec speci?cations r 11 r 12 , r 21 r 22 low k board 357 150, 166 228 high k board 249 76, 79 159 notes: 1. maximum junction temperature for above parts: 125 c. thermal model for acpl-p314/w314 streched-so6 pack- age optocoupler de?nitions r 11 : junction to ambient thermal resistance of led due to heating of led r 12 : junction to ambient thermal resistance of led due to heating of detector (output ic) r 21 : junction to ambient thermal resistance of detec- tor (output ic) due to heating of led. r 22 : junction to ambient thermal resistance of detec- tor (output ic) due to heating of detector (output ic). p 1 : power dissipation of led (w). p 2 : power dissipation of detector / output ic (w). t 1 : junction temperature of led (?c). t 2 : junction temperature of detector (?c). t a : ambient temperature. ?t 1 : temperature di?erence between led junction and ambient (?c). ?t 2 : temperature deference between detector junction and ambient. ambient temperature: junction to ambient thermal resistances were measured approximately 1.25cm above optocoupler at ~23?c in still air

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