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ds123 (v2.1) november 18, 2003 www.xilinx.com 1 preliminary product specification 1-800-255-7778 ? 2002 xilinx, inc. all rights reserved. all xilinx trademarks, registered trademarks, patents, and disclaimers are as listed a t http://www.xilinx.com/legal.htm . all other trademarks and registered trademarks are the property of their respective owners. all specifications are subject to c hange without notice. features ? in-system programmable proms for configuration of xilinx fpgas low-power advanced cmos flash process endurance of 20,000 program/erase cycles operation over full industrial temperature range (?40c to +85c) available in small footprint packages: vo20, vo48, and fs48 ieee standard 1149. 1/1532 boundar y-scan (jtag) support for programming, prototyping, and testing jtag command initiation of standard fpga configuration cascadable for storing longer or multiple bitstreams dedicated boundary-scan (jtag) i/o power supply (v ccj ) i/o pins compatible with voltage levels ranging from 1.5v to 3.3v design support using the xilinx alliance ise and foundation ise series software packages xcf01s/xcf02s/xcf04s - 3.3v supply voltage - serial fpga configuration interface xcf08p/xcf16p/XCF32P - 1.8v supply voltage - serial or parallel fpga configuration interface - design revision technology enables storing and accessing multiple design revisions for configuration - built-in data decompressor compatible with xilinx advanced compression technology description xilinx introduces the platform flash series of in-system pro- grammable configuration proms. available in 1 to 32 megabit (mbit) densities, these proms provide an easy-to-use, cost-effective, and reprogrammable method for storing large xilinx fpga configuration bitstreams. the platform flash prom series includes both the 3.3v xcfxxs prom and the 1.8v xcfxxp prom. the xcfxxs version includes 4-mbit, 2-mbit, and 1-mbit proms that support master serial and slave serial fpga configuration modes ( figure 1 ). the xcfxxp version includes 32-mbit, 16-mbit, and 8-mbit proms that support master serial, slave serial, master selectmap, and slave selectmap fpga configuration modes ( figure 2 ). a summary of the platform flash prom family members and supported fea- tures is shown in ta bl e 1 . 0 platform flash in-system programmable configuration proms ds123 (v2.1) november 18, 2003 00 preliminary product specification r ta bl e 1 : platform flash prom features density v ccint v cco / v ccj range packages jtag isp programming serial configuration parallel configuration design revisioning compression xcf01s 1 mbit 3.3v 1.8v - 3.3v vo20 ? xcf02s 2 mbit 3.3v 1.8v - 3.3v vo20 ? xcf04s 4 mbit 3.3v 1.8v - 3.3v vo20 ? xcf08p 8 mbit 1.8v 1.5v - 3.3v vo48 fs48 ???? xcf16p 16 mbit 1.8v 1.5v - 3.3v vo48 fs48 ???? XCF32P 32 mbit 1.8v 1.5v - 3.3v vo48 fs48 ???? this datasheet has been downloaded from http://www.digchip.com at this page free datasheet http:///
platform flash in-system programmable configuration proms 2 www.xilinx.com ds123 (v2.1) november 18, 2003 1-800-255-7778 preliminary product specification r when the fpga is in master serial mode, it generates a configuration clock that drives the prom. a short access time after ce and oe are enabled, data is available on the prom data (d0) pin that is connected to the fpga din pin. new data is available a short access time after each ris- ing clock edge. the fpga generates the appropriate num- ber of clock pulses to complete the configuration. when the fpga is in slave serial mode, the prom and the fpga are both clocked by an external clock source, or optionally, for the xcfxxp prom only, the prom can be used to drive the fpgas configuration clock. the xcfxxp version of the platform flash prom also sup- ports master selectmap and slave selectmap (or slave parallel) fpga configuration modes. when the fpga is in master selectmap mode, the fpga generates a configura- tion clock that drives the prom. when the fpga is in slave selectmap mode, either an external oscillator generates the configuration clock that drives the prom and the fpga, or optionally, the xcfxxp prom can be used to drive the fpgas configuration clock. after ce and oe are enabled, data is available on the proms data (d0-d7) pins. new data is available a short access time after each rising clock edge. the data is clocked into the fpga on the following rising edge of the cc lk. a free-running oscillator can be used in the slave parallel /slave selecmap mode. the xcfxxp version of the platform flash prom provides additional advanced features. a built-in data decompressor supports utilizing compressed pr om files, and design revi- sioning allows multiple design revisions to be stored on a single prom or stored across several proms. for design revisioning, external pins or internal control bits are used to select the active design revision. multiple platform flash prom devices can be cascaded to support the larger configuration files required when target- ing larger fpga devices or targeting multiple fpgas daisy chained together. when utilizi ng the advanced features for the xcfxxp platform flash prom, such as design revi- sioning, programming files which span cascaded prom devices can only be created for cascaded chains containing only xcfxxp proms. if the advanced xcfxxp features are not enabled, then the cascaded chain can include both xcfxxp and xcfxxs proms. figure 1: xcfxxs platform flash block diagram control and jtag interface memory serial interface data (d0) serial mode data address clk ce tck tms tdi tdo oe/reset ceo data ds123_01_30603 cf fi figure 2: xcfxxp platform flash block diagram clkout ceo data (d0) (serial/parallel mode) d[1:7] (parallel mode) tck tms tdi tdo clk ce en_ext_sel oe/reset busy data data address rev_sel [1:0] cf control and jtag interface memory osc serial or parallel interface decompressor ds123_19_102003
platform flash in-system programmable configuration proms ds123 (v2.1) november 18, 2003 www.xilinx.com 3 preliminary product specification 1-800-255-7778 r the platform flash proms are compatible with all of the existing fpga device families. a reference list of xilinx fpgas and the respective compatible platform flash proms is given in ta b l e 2 . a list of platform flash proms and their capacities is given in ta b l e 3 . ta bl e 2 : xilinx fpgas and compatible platform flash proms fpga configuration bitstream platform flash prom (1) virtex-ii pro xc2vp2 1,305,440 xcf02s xc2vp4 3,006,560 xcf04s xc2vp7 4,485,472 xcf08p xc2vp20 8,214,624 xcf08p xc2vp30 11,589,984 xcf16p xc2vp40 15,868,256 xcf16p xc2vp50 19,021,408 XCF32P xc2vp70 26,099,040 XCF32P xc2vp100 34,292,832 XCF32P (2) xc2vp125 43,602,784 XCF32P (2) virtex-ii xc2v40 360,096 xcf01s xc2v80 635,296 xcf01s xc2v250 1,697,184 xcf02s xc2v500 2,761,888 xcf04s xc2v1000 4,082,592 xcf04s xc2v1500 5,659,296 xcf08p xc2v2000 7,492,000 xcf08p xc2v3000 10,494,368 xcf16p xc2v4000 15,659,936 xcf16p xc2v6000 21,849,504 XCF32P xc2v8000 29,063,072 XCF32P virtex-e xcv50e 630,048 xcf01s xcv100e 863,840 xcf01s xcv200e 1,442,016 xcf02s xcv300e 1,875,648 xcf02s xcv400e 2,693,440 xcf04s xcv405e 3,430,400 xcf04s xcv600e 3,961,632 xcf04s xcv812e 6,519,648 xcf08p xcv1000e 6,587,520 xcf08p xcv1600e 8,308,992 xcf08p xcv2000e 10,159,648 xcf16p xcv2600e 12,922,336 xcf16p xcv3200e 16,283,712 xcf16p virtex xcv50 559,200 xcf01s xcv100 781,216 xcf01s xcv150 1,040,096 xcf01s xcv200 1,335,840 xcf02s xcv300 1,751,808 xcf02s xcv400 2,546,048 xcf04s xcv600 3,607,968 xcf04s xcv800 4,715,616 xcf08p xcv1000 6,127,744 xcf08p spartan-3 xc3s50 439,264 xcf01s xc3s200 1,047,616 xcf01s xc3s400 1,699,136 xcf02s xc3s1000 3,223,488 xcf04s xc3s1500 5,214,784 xcf08p xc3s2000 7,673,024 xcf08p xc3s4000 11,316,864 xcf16p xc3s5000 13,271,936 xcf16p spartan-iie xc2s50e 630,048 xcf01s xc2s100e 863,840 xcf01s xc2s150e 1,134,496 xcf02s xc2s200e 1,442,016 xcf02s xc2s300e 1,875,648 xcf02s xc2s400e 2,693,440 xcf04s xc2s600e 3,961,632 xcf04s spartan-ii xc2s15 197,696 xcf01s xc2s30 336,768 xcf01s xc2s50 559,200 xcf01s xc2s100 781,216 xcf01s xc2s150 1,040,096 xcf01s xc2s200 1,335,840 xcf02s notes: 1. if design revisioning or other advanc ed feature support is required, the xcfxxp can be used as an alternative to the xcf01s, xcf02s, or xcf04s. 2. assumes compression used. ta b l e 3 : platform flash prom capacity platform flash prom configuration bits platform flash prom configuration bits xcf01s 1,048,576 xcf08p 8,388,608 xcf02s 2,097,152 xcf16p 16,777,216 xcf04s 4,194,304 XCF32P 33,554,432 ta b l e 2 : xilinx fpgas and compatible platform flash proms (continued) fpga configuration bitstream platform flash prom (1)
platform flash in-system programmable configuration proms 4 www.xilinx.com ds123 (v2.1) november 18, 2003 1-800-255-7778 preliminary product specification r programming in-system programming in-system programmable proms can be programmed indi- vidually, or two or more can be daisy-chained together and programmed in-system via the standard 4-pin jtag proto- col as shown in figure 3 . in-system programming offers quick and efficient design iterations and eliminates unnec- essary package handling or socketing of devices. the pro- gramming data sequence is delivered to the device using either xilinx impact software and a xilinx download cable, a third-party jtag development system, a jtag-compatible board tester, or a simple microprocessor interface that emu- lates the jtag instruction se quence. the impact software also outputs serial vector format (svf) files for use with any tools that accept svf format, including automatic test equipment. during in-system programming, the ceo output is driven high. all other outputs are held in a high-imped- ance state or held at clamp levels during in-system pro- gramming. in-system programming is fully supported across the recommended operating voltage and tempera- ture ranges. oe/reset the 1/2/4 mbit xcfxxs platform flash proms in-system programming algorithm requires issuance of a reset that causes oe/reset to pulse low. external programming xilinx reprogrammable proms can also be programmed by the xilinx multipro desktop to ol or a third-party device programmer. this provides t he added flexibility of using pre-programmed devices with an in-system programmable option for future enhancements and design changes. reliability and endurance xilinx in-system programmable products pr ovide a guaran- teed endurance level of 20,000 in-system program/erase cycles and a minimum data retention of 20 years. each device meets all functional, performance, and data retention specifications within this endurance limit. design security the xilinx in-system programmable platform flash prom devices incorporate advanced data security features to fully protect the fpga programming data against unauthorized reading via jtag. the xcfxxp proms can also be pro- grammed to prevent inadvertent writing via jtag. ta b l e 4 and ta b l e 5 show the security settings available for the xcfxxs prom and xcfxxp prom, respectively. read protection the read protect security bit can be set by the user to pre- vent the internal programming pattern from being read or copied via jtag. read protection does not prevent write operations. for the xcfxxs prom, the read protect secu- rity bit is set for the entire device, and resetting the read pro- tect security bit requires erasing the entire device. for the xcfxxp prom the read protect security bit can be set for individual design revisions, and resetting the read protect bit requires erasing the particular design revision. write protection the xcfxxp prom device also allows the user to write protect (or lock) a particular design revision to prevent inad- vertent erase or program operations. once set, the write protect security bit for an individual design revision must be reset (using the unlock command followed by isc_erase command) before an erase or program opera- tion can be performed. figure 3: jtag in-system programming operation (a) solder device to pcb (b) program using download cable ds026_02_082703 gnd v cc (a) (b) ta b l e 4 : xcfxxs device data security options read protect read/verify inhibited program inhibited erase inhibited reset (default) set
platform flash in-system programmable configuration proms ds123 (v2.1) november 18, 2003 www.xilinx.com 5 preliminary product specification 1-800-255-7778 r ieee 1149.1 boundary-scan (jtag) the platform flash prom family is ieee standard 1532 in-system programming compat ible, and is fully compliant with the ieee std. 1149.1 boun dary-scan, also known as jtag, which is a subset of ieee std. 1532 boundary-scan. a test access port (tap) and registers are provided to sup- port all required boundary scan instructions, as well as many of the optional instruct ions specified by ieee std. 1149.1. in addition, the jtag interface is used to implement in-system programming (isp) to facilitate configuration, era- sure, and verification operations on the platform flash prom device. ta b l e 6 lists the required and optional boundary-scan instructions supported in the platform flash proms. refer to the ieee std. 1149.1 specification for a complete description of boundary-scan architecture and the required and optional instructions. instruction register the instruction register (ir) for the platform flash prom is connected between tdi and tdo during an instruction scan sequence. in preparation for an instruction scan sequence, the instruction register is parallel loaded with a fixed instruction capture pattern. this pattern is shifted out onto tdo (lsb first), while an instruction is shifted into the instruction register from tdi. xcfxxs instruction register (8 bits wide) the instruction register (ir) for the xcfxxs prom is eight bits wide and is connected between tdi and tdo during an instruction scan sequence. the detailed composition of the instruction capt ure pattern is illustrated in figure 4 . the instruction capture pattern shifted out of the xcfxxs device includes ir[7:0]. ir[7:5] are reserved bits and are set to a logic "0". the isc status field, ir[4], contains logic "1" if the device is currently in in-system configuration (isc) mode; otherwise, it contains logic "0". the security field, ir[3], contains logic "1" if the device has been programmed with the security option turned on; otherwise, it contains logic "0". ir[2] is unused, and is set to '0'. the remaining bits ir[1:0] are set to '01' as defined by i eee std. 1149.1. xcfxxp instruction register (16 bits wide) the instruction register (ir) for the xcfxxp prom is six- teen bits wide and is connected between tdi and tdo dur- ing an instruction scan sequence. the detailed composition of the instruction capture pattern is illustrated in figure 5 . the instruction capture pattern shifted out of the xcfxxp device includes ir[15:0]. ir[15:9] are reserved bits and are set to a logic "0". the isc error field, ir[8:7], contains a "10" when an isc operation is a success, otherwise a "01" when an in-system configuration (isc) operation fails the erase/program (er/prog) error field, ir[6:5], contains a "10" when an erase or program operation is a success, oth- erwise a "01" when an erase or program operation fails. the erase/program (er/prog) status field, ir[4], contains a logic "1" when the device is busy performing an erase or programming operation, otherwise, it contains a logic "0". the isc status field, ir[3], contains logic "1" if the device is currently in in-system configuration (isc) mode; otherwise, it contains logic "0". the done field, ir[2], contains logic "1" if the sampled design revision has been successfully programmed; otherwise, a logic "0" indicates incomplete programming. the remaining bits ir[1:0] are set to '01' as defined by ieee std. 1149.1. ta bl e 5 : xcfxxp design revision data security options read protect write protect read/verify inhibited program inhibited erase inhibited reset (default) reset (default) reset (default) set ? set reset (default) set set ?? ta bl e 6 : platform flash prom boundary scan instructions boundary-scan command xcfxxs ir[7:0] (hex) xcfxxp ir[15:0] (hex) instruction description required instructions bypass ff ffff enables bypass sample/preload 01 0001 enables boundary-scan sample/preload operation extest 00 0000 enables boundary-scan extest operation
platform flash in-system programmable configuration proms 6 www.xilinx.com ds123 (v2.1) november 18, 2003 1-800-255-7778 preliminary product specification r boundary scan register the boundary-scan register is used to control and observe the state of the device pins during the extest, sam- ple/preload, and clamp inst ructions. each output pin on the platform flash prom has two register stages which contribute to the boundary-scan register, while each input pin has only one register stage. the bidirectional pins have a total of three register stages which contribute to the boundary-scan register. for each output pin, the register stage nearest to tdi controls and observes the output state, and the second stage closest to tdo controls and observes the high-z enable state of the output pin. for each input pin, a single register stage controls and observes the input state of the pin. the bidirectional pin combines the three bits, the input stage bit is first, followed by the output stage bit and finally the output enable stage bit. the output enable stage bit is closest to tdo. see the xcfxxs/xcfxxp pin names and descriptions ta b l e s i n t h e pinouts and pin descriptions section for the boundary-scan bit order for all connected device pins, or see the appropriate bsdl file for the complete bound- ary-scan bit order description under the "attribute boundary_register" section in the bsdl file. the bit assigned to boundary-scan cell "0" is the lsb in the bound- ary-scan register, and is the register bit closest to tdo. optional instructions clamp fa 00fa enables boundary-scan clamp operation highz fc 00fc places all outputs in high-impedance state simultaneously idcode fe 00fe enables shifting out 32-bit idcode usercode fd 00fd enables shifting out 32-bit usercode platform flash prom specific instructions config ee 00ee initiates fpga configuration by pulsing cf pin low once. (for the xcfxxp this command also resets the selected design revision based on either the external rev_sel[1:0] pins or on the internal design revision selection bits.) (1) notes: 1. for more information see initiating fpga configuration. tdi ir[7:5] ir[4] ir[3] ir[2] ir[1:0] tdo reserved isc status security 0 0 1 figure 4: xcfxxs instruction capture values loaded into ir as part of an instruction scan sequence tdi ir[15:9] ir[8:7] ir[6:5] ir[4] ir[3] ir[2] ir[1:0] tdo reserved isc error er/prog error er/prog status isc status done 0 1 figure 5: xcfxxp instruction capture values loaded into ir as part of an instruction scan sequence ta bl e 6 : platform flash prom boundary scan instructions (continued) boundary-scan command xcfxxs ir[7:0] (hex) xcfxxp ir[15:0] (hex) instruction description
platform flash in-system programmable configuration proms ds123 (v2.1) november 18, 2003 www.xilinx.com 7 preliminary product specification 1-800-255-7778 r identification registers idcode register the idcode is a fixed, vendor-assigned value that is used to electrically identify the manufacturer and type of the device being addressed. the idcode register is 32 bits wide. the idcode register can be shifted out for examina- tion by using the idcode inst ruction. the idcode is avail- able to any other system component via jtag. ta b l e 7 lists the idcode register values for the platform flash proms. the idcode register has th e following binary format: vvvv:ffff:ffff:aaaa:aaaa:cccc:cccc:ccc1 where v = the die version number f = the prom family code a = the specific platform flash prom product id c = the xilinx manufacture's id the lsb of the idcode register is always read as logic "1" as defined by ieee std. 1149.1. usercode register the usercode instruction gives access to a 32-bit user programmable scratch pad typically used to supply informa- tion about the device's programmed contents. by using the usercode instruction, a user-programmable identifica- tion code can be shifted out for examination. this code is loaded into the usercode register during programming of the platform flash prom. if the device is blank or was not loaded during programming, the usercode register con- tains ffffffffh . customer code register for the xcfxxp platform flash prom, in addition to the usercode, a unique 32-byte customer code can be assigned to each design revision enabled for the prom. the customer code is set during programming, and is typ- ically used to supply information about the design revision contents. a private jtag instruction is required to read the customer code. if the prom is blank, or the customer code for the selected design revision was not loaded during programming, or if the particular design revision is erased, the customer code will contain all ones. platform flash prom tap characteristics the platform flash prom family performs both in-system programming and ieee 1149.1 boundary-scan (jtag) test- ing via a single 4-wire test access port (tap). this simpli- fies system designs and allows standard automatic test equipment to perform both functions. the ac characteris- tics of the platform flash prom tap are described as fol- lows. tap timing figure 6 shows the timing relationships of the tap signals. these tap timing characteristics are identical for both boundary-scan and isp operations. ta bl e 7 : idcodes assigned to platform flash proms device idcode (1) (hex) xcf01s 05044093 xcf02s 05045093 xcf04s 05046093 xcf08p 05057093 xcf16p 05058093 XCF32P 05059093 notes: 1. the first four bits indicate the die version number, and may vary. figure 6: test access port timing tck t ckmin t mss tms tdi tdo t msh t dih t dov t dis ds026_04_020300
platform flash in-system programmable configuration proms 8 www.xilinx.com ds123 (v2.1) november 18, 2003 1-800-255-7778 preliminary product specification r tap ac parameters ta bl e 8 shows the timing parameters for the tap waveforms shown in figure 6 . additional features for the xcfxxp internal oscillator the 8/16/32 mbit xcfxxp platform flash proms include an optional internal oscillator which can be used to drive the clkout and data pins on fpga configuration interface. the internal oscillator can be enabled during device pro- gramming, and can be set to either the default frequency or to a slower frequency ( ac characteristics over operat- ing conditions when cascading ). clkout the 8/16/32 mbit xcfxxp platform flash proms include the programmable option to enable the clkout signal which allows the prom to provide a source synchronous clock aligned to the data on the configuration interface. the clkout signal is derived from one of two clock sources: the clk input pin or the intern al oscillator. the input clock source is selected during the prom programming sequence. output data is available on the rising edge of clkout. the clkout signal is enabled during programming, and is active when ce is low and oe/reset is high. when dis- abled, the clkout pin is put into a high-impedance state and should be pulled high externally to provide a known state. when cascading platform flash proms with clkout enabled, after completing it's data transfer, the first prom disables clkout and releases the ceo pin enabling the next prom in the prom chain. the next prom will begin driving the clkout signal once that prom is enabled and data is available for transfer. during high-speed parallel configuration without compres- sion, the fpga drives the busy signal on the configuration interface. when busy is asserted high, the proms inter- nal address counter stops incrementing, and the current data value is held on the data outputs. while busy is high, the prom will continue drivin g the clkout signal to the fpga, clocking the fpgas configuration logic. when the fpga deasserts busy, indicating that it is ready to receive additional configuration data , the prom will begin driving new data onto the configuration interface. decompression the 8/16/32 mbit xcfxxp platform flash proms include a built-in data decompressor co mpatible with xilinx advanced compression technology. co mpressed platform flash prom files are created from the target fpga bitstream(s) using the impact software. only slave serial and slave selectmap (parallel) configuration modes are supported for fpga configuration when using a xcfxxp prom pro- grammed with a compressed bitstream. compression rates will vary depending on several fa ctors, including the target device family and the target design contents. the decompression option is enabled during the prom programming sequence. the prom decompresses the stored data before driving both clock and data onto the fpga's configuration interface. if decompression is enabled, then the platform flash clock output pin (clk- out) must be used as the clock signal for the configuration interface, driving the target fpga's configuration clock input pin (cclk). either the prom's clk input pin or the internal oscillator must be selected as the source for clkout. any target fpga connected to the prom must operate as slave in the configuration chain, with the configuration mode set to slave serial mode or slave selectmap (parallel) mode. when decompression is enabled, the clkout signal becomes a controlled clock output with a reduced maximum frequency and remains low when decompressed data is not ready. the busy input is automatically disabled when decompres- sion is enabled. design revisioning design revisioning allows the user to create up to four unique design revisions on a single prom or stored across ta bl e 8 : test access port timing parameters symbol parameter min max units t ckmin1 tck minimum clock period when v ccj = 2.5v or 3.3v 100 - ns t ckmin2 tck minimum clock period, bypass mode, when v ccj = 2.5v or 3.3v 50 - ns t mss tms setup time when v ccj = 2.5v or 3.3v 10 - ns t msh tms hold time when v ccj = 2.5v or 3.3v 25 - ns t dis tdi setup time when v ccj = 2.5v or 3.3v 10 - ns t dih tdi hold time when v ccj = 2.5v or 3.3v 25 - ns t dov tdo valid delay when v ccj = 2.5v or 3.3v - 30 ns
platform flash in-system programmable configuration proms ds123 (v2.1) november 18, 2003 www.xilinx.com 9 preliminary product specification 1-800-255-7778 r multiple cascaded proms. de sign revisioning is sup- ported for the 8/16/32 mbit xcfxxp platform flash proms in both serial and parallel modes. design revisioning can be used with compressed prom files, and also when the clkout feature is enabled. the prom programming files along with the revision information files (.cfi) are created using the impact software. the .cfi file is required to enable design revision programming in impact. a single design revision requires at least 8 mbits of memory, but a larger design revision can span several devices. a sin- gle 32 mbit prom can store from one to four separate design revisions: one 32 mbit design revision, two 16 mbit design revisions, three 8 mbit design revisions, or four 8 mbit design revisions. a single 16 mbit prom can store up to two separate design revisions: one 16 mbit design revision, two 8 mbit design revisions. a single 8 mbit prom can store only one 8 mbit design revision. larger design revisions can be split over several cascaded proms. during the prom file crea tion, each design revision is assigned a revision number: revision 0 = '00' revision 1 = '01' revision 2 = '10' revision 3 = '11' after programming the platform flash prom, a particular design revision can be selected using the external rev_sel[1:0] pins or using the internal programmable design revision control bits. the en_ext_sel pin deter- mines if the external pins or internal bits are used to select the design revision. when en_ext_sel is low, design revision selection is controlled by the external revision select pins, rev_sel[1 :0]. when en_ext_sel is high, design revision selection is controlled by the internal pro- grammable revision select control bits. during power up, the design revision selection inputs (pins or control bits) are sampled internally. after power up, the design revision selection inputs are sampled again after the rising edge of the cf pulse. the data from the selected design revision is then presented on the fpga configuration interface. figure 7: design revision storage examples rev 0 (8 mbits) rev 1 (8 mbits) rev 2 (8 mbits) rev 3 (8 mbits) rev 0 (8 mbits) rev 1 (8 mbits) rev 2 (16 mbits) rev 0 (16 mbits) rev 1 (16 mbits) rev 0 (8 mbits) rev 1 (24 mbits) rev 0 (32 mbits) 4 design revisions 3 design revisions 2 design revisions 1 design revision (a) design revision storage examples for a single XCF32P prom rev 0 (16 mbits) rev 1 (16 mbits) rev 2 (16 mbits) rev 3 (16 mbits) rev 0 (16 mbits) rev 1 (16 mbits) rev 2 (32 mbits) rev 0 (32 mbits) rev 1 (32 mbits) rev 0 (16 mbits) rev 1 (16 mbits) rev 0 (32 mbits) 4 design revisions 3 design revisions 2 design revisions 1 design revision (b) design revision storage examples spanning two XCF32P proms prom 0 prom 0 prom 0 prom 0 prom 0 prom 0 prom 0 prom 0 prom 0 prom 0 rev 0 (32 mbits) rev 1 (32 mbits) prom 1 prom 1 prom 1 prom 1 prom 1 ds123_20_102103
platform flash in-system programmable configuration proms 10 www.xilinx.com ds123 (v2.1) november 18, 2003 1-800-255-7778 preliminary product specification r prom to fpga configuration mode and connections summary the fpga's i/o, logical functions, and internal interconnec- tions are established by the configuration data contained in the fpgas bitstream. the bitstream is loaded into the fpga either automatically upon power up, or on command, depending on the state of th e fpga's mode pins. xilinx platform flash proms are designed to download directly to the fpga configuration interface. fpga configuration modes which are supported by the xcfxxs platform flash proms include: master serial and slave serial. fpga con- figuration modes which are supported by the xcfxxp plat- form flash proms include: master serial, slave serial, master selectmap, and slave selectmap. below is a short summary of the supported fpga configuration modes. see the respective fpga data sheet for device configuration details, including which configuration modes are supported by the targeted fpga device. fpga master serial mode in master serial mode, the fpga automatically loads the configuration bitstream in bit-serial form from external mem- ory synchronized by the configuration clock (cclk) gener- ated by the fpga. upon power-up or reconfiguration, the fpga's mode select pins are used to select the master serial configuration mode. master serial mode provides a simple configuration interface. only a serial data line, a clock line, and two control lines (init and done) are required to configure an fpga. data from the prom is read out sequentially on a single data line (din), accessed via the prom's internal address counter which is incre- mented on every valid rising edge of cclk. the serial bit- stream data must be setup at the fpgas din input pin a short time before each rising edge of the fpga's internally generated cclk signal. typically, a wide range of frequencies can be selected for the fpga?s internally genera ted cclk which always starts at a slow default frequency. the fpgas bitstream contains configuration bits which can switch cclk to a higher fre- quency for the remainder of the master serial configuration sequence. the desired cclk frequency is selected during bitstream generation. connecting the fpga device to the configuration prom for master serial configuration mode ( figure 8 ): the data output of the prom(s) drive the din input of the lead fpga device. the master fpga cclk output drives the clk input(s) of the prom(s) the ceo output of a prom drives the ce input of the next prom in a daisy chain (if any). the oe/reset pins of all proms are connected to the init_b pins of all fpga devices. this connection assures that the prom addre ss counter is reset before the start of any (re)configuration. the prom ce input can be driven from the done pin. the ce input of the first (or only) prom can be driven by the done output of all target fpga devices, provided that done is not permanently grounded. ce can also be permanently tied low, but this keeps the data output active and causes an unnecessary i cc active supply current ( dc characteristics over operating conditions ). the prom cf pin is typically connected to the fpga's prog_b (or program ) input. fpga slave serial mode in slave serial mode, the fpga loads the configuration bit- stream in bit-serial form from external memory synchro- nized by an externally supplied clock. upon power-up or reconfiguration, the fpga's mode select pins are used to select the slave serial configuration mode. slave serial mode provides a simple configuration interface. only a serial data line, a clock line, and two control lines (init and done) are required to configure an fpga. data from the prom is read out sequentially on a single data line (din), accessed via the prom's internal address counter which is incremented on every valid rising edge of cclk. the serial bitstream data must be setup at the fpgas din input pin a short time before each rising edge of the externally provided cclk. connecting the fpga device to the configuration prom for slave serial configuration mode ( figure 9 ): the data output of the prom(s) drive the din input of the lead fpga device. the prom clkout (for xcfxxp only) or an external clock source drives the fpga's cclk input. the ceo output of a prom drives the ce input of the next prom in a daisy chain (if any). the oe/reset pins of all proms are connected to the init_b (or init) pins of all fpga devices. this connection assures that the prom address counter is reset before the start of any (re)configuration. the prom ce input can be driven from the done pin. the ce input of the first (or only) prom can be driven by the done output of all target fpga devices, provided that done is not permanently grounded. ce can also be permanently tied low, but this keeps the data output active and causes an unnecessary i cc active supply current ( dc characteristics over operating conditions ). the prom cf pin is typically connected to the fpga's prog_b (or program ) input. serial daisy chain multiple fpgas can be daisy-chained for serial configura- tion from a single source. after a particular fpga has been configured, the data for the next device is routed internally
platform flash in-system programmable configuration proms ds123 (v2.1) november 18, 2003 www.xilinx.com 11 preliminary product specification 1-800-255-7778 r to the fpgas dout pin. typically the data on the dout pin changes on the fallin g edge of cclk, although for some devices the dout pin changes on the rising edge of cclk. consult the respective device data sheets for detailed infor- mation on a particular fpga device. for clocking the daisy-chained configuration, either the first fpga in the chain can be set to master serial, generating the cclk, with the remaining devices set to slave serial ( figure 10 ), or all the fpga devices can be set to slave serial and an externally generated clock can be used to drive the fpga's configuration interface. fpga master selectmap (parallel) mode (1) in master selectmap mode, byte-wide data is written into the fpga, typically with a busy flag controlling the flow of data, synchronized by the configuration clock (cclk) gen- erated by the fpga. upon power-up or reconfiguration, the fpga's mode select pins are used to select the master selectmap configuration mode. the configuration interface typically requires a parallel data bus, a clock line, and two control lines (init and done). in addition, the fpgas chip select, write, and busy pins must be correctly controlled to enable selectmap configuration. the configuration data is read from the prom byte by byte on pins [d0..d7], accessed via the prom's internal address counter which is incremented on every valid rising edge of cclk. the bit- stream data must be setup at the fpgas [d0..d7] input pins a short time before each rising edge of the fpga's inter- nally generated cclk signal. if busy is asserted (high) by the fpga, the configuration data must be held until busy goes low. an external data source or external pull-down resistors must be used to enable the fpga's active low chip select (cs or cs_b) and write (write or rdwr_b) signals to enable the fpga's selectmap configuration pro- cess. the master selectmap configuration interface is clocked by the fpga?s internal oscillator. typically, a wide range of fre- quencies can be selected for the internally generated cclk which always starts at a slow default frequency. the fpgas bitstream contains configuration bits which can switch cclk to a higher frequency for the remainder of the master selectmap configuration sequence. the desired cclk fre- quency is selected during bitstream generation. connecting the fpga device to the configuration prom for master selectmap (paral lel) configuration mode ( figure 11 ): the data outputs of the prom(s) drive the [d0..d7] input of the lead fpga device. the master fpga cclk output drives the clk input(s) of the prom(s) the ceo output of a prom drives the ce input of the next prom in a daisy chain (if any). the oe/reset pins of all proms are connected to the init_b pins of all fpga devices. this connection assures that the prom address counter is reset before the start of any (re)configuration. the prom ce input can be driven from the done pin. the ce input of the first (or only) prom can be driven by the done output of all target fpga devices, provided that done is not permanently grounded. ce can also be permanently tied low, but this keeps the data output active and causes an unnecessary i cc active supply current ( dc characteristics over operating conditions ). for high-frequency parallel configuration, the busy pins of all proms are connected to the fpga's busy output. this connection assures that the prom is only enabled when the fpga is ready for the next configuration data byte. the prom cf pin is typically connected to the fpga's prog_b (or program ) input. fpga slave selectma p (parallel) mode (2) in slave selectmap mode, byte-wide data is written into the fpga, typically with a busy flag controlling the flow of data, synchronized by an externally supplied configuration clock (cclk). upon power-up or reconfiguration, the fpga's mode select pins are used to select the slave selectmap configuration mode. the configuration interface typically requires a parallel data bus, a clock line, and two control lines (init and done). in addition, the fpgas chip select, write, and busy pins must be correctly controlled to enable selectmap configuration. the configuration data is read from the prom byte by byte on pins [d0..d7], accessed via the prom's internal address counter which is incremented on every valid rising edge of cclk. the bit- stream data must be setup at the fpgas [d0..d7] input pins a short time before each rising edge of the provided cclk. if busy is asserted (high) by the fpga, the configuration data must be held until busy goes low. an external data source or external pull-down resistors must be used to enable the fpga's active low chip select (cs or cs_b) and write (write or rdwr_b) signals to enable the fpga's selectmap configuration process. after configuration, the pins of the selectmap port can be used as additional user i/o. alternatively, the port can be retained using the persist option. connecting the fpga device to the configuration prom for slave selectmap (parallel) configuration mode ( figure 12 ): 1. the master selectmap (parallel) fpga configuration mode is sup- ported only by the xcfxxp platform flash prom. this mode is not supported by the xcfxxs platform flash prom. 2. the slave selectmap (parallel) fpga configuration mode is sup- ported only by the xcfxxp platform flash proms.this mode is not supported by the xcfxxs platform flash prom.
platform flash in-system programmable configuration proms 12 www.xilinx.com ds123 (v2.1) november 18, 2003 1-800-255-7778 preliminary product specification r the data outputs of the prom(s) drives the [d0..d7] inputs of the lead fpga device. the prom clkout (for xcfxxp only) or an external clock source drives the fpga's cclk input the ceo output of a prom drives the ce input of the next prom in a daisy chain (if any). the oe/reset pins of all proms are connected to the init_b pins of all fpga devices. this connection assures that the prom addre ss counter is reset before the start of any (re)configuration. the prom ce input can be driven from the done pin. the ce input of the first (or only) prom can be driven by the done output of all target fpga devices, provided that done is not permanently grounded. ce can also be permanently tied low, but this keeps the data output active and causes an unnecessary i cc active supply current ( dc characteristics over operating conditions ). for high-frequency parallel configuration, the busy pins of all proms are connected to the fpga's busy output. this connection assures that the prom is only enabled when the fpga is ready for the next configuration data byte. the prom cf pin is typically connected to the fpga's prog_b (or program ) input. fpga selectmap (paral lel) device chaining (1) multiple virtex-ii fpgas can be configured using the selectmap mode, and be made to start-up simultaneously. to configure multiple devices in this way, wire the individual cclk, done, init, data ([d0..d7]), write (write or rdwr_b), and busy pins of all the devices in parallel. if all devices are to be configured with the same bitstream, read- back is not being used, and the cclk frequency selected does not require the use of the busy signal, the cs_b pins can be connected to a common line so all of the devices are configured simultaneously ( figure 13 ). with additional control logic, the individual devices can be loaded separately by asserting the cs_b pin of each device in turn and then enabling the appropriate configuration data. the prom can also store the individual bitstreams for each fpga for selectmap configuration in separate design revi- sions. when design revisionin g is utilized, additional control logic can be used to select the appropriate bitstream by asserting the en_ext_sel pin, and using the rev_sel[1:0] pins to select the required bitstream, while asserting the cs_b pin for the fpga the bitstream is target- ing ( figure 14 ). for clocking the parallel configuration chain, either the first fpga in the chain can be set to master selectmap, gener- ating the cclk, with the remaining devices set to slave selectmap, or all the fpga devices can be set to slave selectmap and an externally generated clock can be used to drive the configuration interface. again, the respective device data sheets should be consulted for detailed infor- mation on a particular fpga device, including which config- uration modes are supported by the targeted fpga device. cascading configuration proms when configuring multiple fpgas in a serial daisy chain, configuring multiple fpgas in a selectmap parallel chain, or configuring a single fpga requiring a larger configura- tion bitstream, cascaded proms provide additional mem- ory ( figure 10 , figure 13 , figure 14 , and figure 15 ). multiple platform flash proms can be concatenated by using the ceo output to drive the ce input of the down- stream device. the clock signal and the data outputs of all platform flash proms in the chain are interconnected. after the last data from the first prom is read, the first prom asserts its ceo output low and drives its outputs to a high-impedance state. the second prom recognizes the low level on its ce input and immediately enables its out- puts. after configuration is complete, address counters of all cas- caded proms are reset if the prom oe/reset pin goes low or ce goes high. when utilizing the advanced features for the xcfxxp plat- form flash prom, including the clock output (clkout) option, decompression option, or design revisioning, pro- gramming files which span cascaded prom devices can only be created for cascaded chains containing only xcfxxp proms. if the advanced features are not used, then cascaded prom chains can contain both xcfxxp and xcfxxs proms. initiating fpga configuration the options for initiating fpga configuration via the plat- form flash prom include: 1. automatic configuration on power up 2. applying an external prog_b (or program ) pulse 3. applying the jtag config instruction following the fpga?s power-on sequence or the assertion of the prog_b (or program ) pin the fpgas configura- tion memory is cleared, the configuration mode is selected, and the fpga is ready to accept a new configuration bit- stream. the fpga?s prog_b pin can be controlled by an external source, or alternatively, the platform flash proms incorporate a cf pin that can be tied to the fpgas prog_b pin. executing the config instruction through jtag pulses the cf output low once for 300-500 ns, reset- ting the fpga and initiating configuration. the impact soft- 1. the selectmap (parallel) fpga configuration modes are sup- ported only by the xcfxxp platform flash prom.these modes are not supported by the xcfxxs platform flash prom.
platform flash in-system programmable configuration proms ds123 (v2.1) november 18, 2003 www.xilinx.com 13 preliminary product specification 1-800-255-7778 r ware can issue the jtag co nfig command to initiate fpga configuration by setting the "load fpga" option. when using the xcfxxp platform flash prom with design revisioning enabled, the cf pin should always be connected to the prog_b (or program ) pin on the fpga to ensure that the current design revision selection is sampled when the fpga is reset. the xcfxxp prom samples the current design revision selection from the external rev_sel pins or the internal programmable revision select bits on the ris- ing edge of cf . when the jtag config command is exe- cuted, the xcfxxp will sample the new design revision before initiating the fpga configuration sequence. configuration prom to fpga devi ce interface connection diagrams figure 8: configuring in master serial mode xilinx fpga master serial din cclk done init_b prog_b tdi tms tck gnd mode pins (1) dout tdo v ccj v cco v ccint dout cclk done init_b prog_b din cclk done init_b prog_b 4.7 k ? 4.7 k ? (1) v cco (2) ...optional daisy-chained slave fpgas with different configurations ...optional slave fpgas with identical configurations tdi tms tck tdo notes: 1 for mode pin connections and done pin pullup value, refer to the appropriate fpga data sheet. 2 for compatible voltages, refer to the appropriate data sheet. platform flash prom v ccint v cco (2) v ccj (2) tdi tms tck gnd d0 clk ce ceo oe/reset cf tdo ds123_11_110303
platform flash in-system programmable configuration proms 14 www.xilinx.com ds123 (v2.1) november 18, 2003 1-800-255-7778 preliminary product specification r figure 9: configuring in slave serial mode xilinx fpga slave serial din cclk done init_b prog_b tdi tms tck gnd mode pins (1) dout tdo v ccj v cco v ccint dout cclk done init_b prog_b din cclk done init_b prog_b 4.7 k ? 4.7 k ? (1) v cco (2) ...optional daisy-chained slave fpgas with different configurations ...optional slave fpgas with identical configurations tdi tms tck tdo notes: 1 for mode pin connections and done pin pullup value, refer to the appropriate fpga data sheet. 2 for compatible voltages, refer to the appropriate data sheet. 3 in slave serial mode, the configuration interface can be clocked by an external oscillator, or optionally?for the xcfxxp platform flash prom only?the clkout signal can be used to drive the fpga's configuration clock (cclk). if the xcfxxp prom's clkout signal is used, then it must be tied to a 4.7k ? resistor pulled up to v cco . platform flash prom v ccint v cco (2) v ccj (2) tdi tms tck gnd d0 clk (3) ce ceo oe/reset cf tdo ds123_12_110303 external (3) oscillator
platform flash in-system programmable configuration proms ds123 (v2.1) november 18, 2003 www.xilinx.com 15 preliminary product specification 1-800-255-7778 r figure 10: configuring multiple devices master/slave serial mode platform flash prom first prom (prom 0) v ccint v cco (2) v ccj (2) tdi tms tck d0 clk ce ceo oe/reset cf tdo xilinx fpga master serial din cclk done init_b prog_b tdi tms tck mode pins (1) dout tdo v ccj v cco v ccint 4.7 k ? 4.7 k ? (1) v cco (2) tdi tms tck tdo notes: 1 for mode pin connections and done pin pullup value, refer to the appropriate fpga data sheet. 2 for compatible voltages, refer to the appropriate data sheet. xilinx fpga slave serial din cclk done init_b prog_b tdi tms tck platform flash prom cascaded prom (prom 1) v ccint v cco (2) v ccj (2) tdi tms tck d0 clk ce ceo oe/reset cf tdo v ccj v cco v ccint mode pins (1) tdo ds123_13_110303 gnd gnd gnd gnd
platform flash in-system programmable configuration proms 16 www.xilinx.com ds123 (v2.1) november 18, 2003 1-800-255-7778 preliminary product specification r figure 11: configuring in master selectmap mode xcfxxp platform flash prom v ccint v cco (2) v ccj (2) tdi tms tck gnd d[0:7] clk ce ceo oe/reset cf busy (4) tdo xilinx fpga master selectmap d[0:7] cclk done init_b prog_b busy (4) tdi tms tck gnd mode pins (1) rdwr_b cs_b tdo v ccj v cco v ccint d[0:7] cclk done init_b prog_b busy (4) 4.7 k ? 4.7 k ? (1) v cco (2) ...optional slave fpgas with identical configurations tdi tms tck tdo notes: 1 for mode pin connections and done pin pullup value, refer to the appropriate fpga data sheet. 2 for compatible voltages, refer to the appropriate data sheet. 3 cs_b (or cs) and rdwr_b (or write) must be either driven low or pulled down exernally. one option is shown. 4 the busy pin is only available with the xcfxxp platform flash prom, and the connection is only required for high-frequency selectmap mode configuration. for busy pin requirements, refer to the appropriate fpga data sheet. 1k ? 1k ? i/o (3) i/o (3) ds123_14_110303
platform flash in-system programmable configuration proms ds123 (v2.1) november 18, 2003 www.xilinx.com 17 preliminary product specification 1-800-255-7778 r figure 12: configuring in slave selectmap mode xcfxxp platform flash prom v ccint v cco (2) v ccj (2) tdi tms tck gnd d[0:7] clk (5) ce ceo oe/reset cf busy (4) tdo xilinx fpga slave selectmap d[0:7] cclk done init_b prog_b busy (4) tdi tms tck gnd mode pins (1) rdwr_b cs_b tdo v ccj v cco v ccint d[0:7] cclk done init_b prog_b busy (4) 4.7 k ? 4.7 k ? (1) v cco (2) ...optional slave fpgas with identical configurations tdi tms tck tdo notes: 1 for mode pin connections and done pin pullup value, refer to the appropriate fpga data sheet. 2 for compatible voltages, refer to the appropriate data sheet. 3 cs_b (or cs) and rdwr_b (or write) must be either driven low or pulled down exernally. one option is shown. 4 the busy pin is only available with the xcfxxp platform flash prom, and the connection is only required for high-frequency selectmap mode configuration. for busy pin requirements, refer to the appropriate fpga data sheet. 5 if the xcfxxp platform flash prom is not used with clkout enabled to drive cclk, then an external clock is required for slave selectmap (or slave parallel) modes. if clkout is used, then it must be tied to a 4.7k ? resistor pulled up to v cco . 1k ? 1k ? i/o (3) i/o (3) ds123_15_110303 external (5) oscillator
platform flash in-system programmable configuration proms 18 www.xilinx.com ds123 (v2.1) november 18, 2003 1-800-255-7778 preliminary product specification r figure 13: configuring multiple devices with identical patterns in master/slave selectmap mode xcfxxp platform flash prom first prom (prom 0) v ccint v cco (2) v ccj (2) tdi tms tck gnd d[0:7] clk ce ceo oe/reset cf busy (4) tdo xilinx fpga master selectmap d[0:7] cclk done init_b prog_b busy (4) tdi tms tck gnd mode pins (1) tdo v ccj v cco v ccint 4.7 k ? 4.7 k ? (1) v cco (2) tdi t ms tck t do notes: 1 for mode pin connections and done pin pullup value, refer to the appropriate fpga data sheet. 2 for compatible voltages, refer to the appropriate data sheet. 3 cs_b (or cs) and rdwr_b (or write) must be either driven low or pulled down exernally. one option is shown. 4 the busy pin is only available with the xcfxxp platform flash prom, and the connection is only required for high-frequency selectmap mode configuration. for busy pin requirements, refer to the appropriate fpga data sheet. xilinx fpga slave selectmap d[0:7] cclk done init_b prog_b busy (4) tdi tms tck gnd xcfxxp platform flash prom cascaded prom (prom 1) v ccint v cco (2) v ccj (2) tdi tms tck gnd d[0:7] clk ce ceo oe/reset cf busy (4) tdo v ccj v cco v ccint mode pins (1) tdo ds123_16_110303 1k ? 1k ? i/o (3) i/o (3) 1k ? 1k ? i/o (3) i/o (3) rdwr_b cs_b rdwr_b cs_b
platform flash in-system programmable configuration proms ds123 (v2.1) november 18, 2003 www.xilinx.com 19 preliminary product specification 1-800-255-7778 r figure 14: configuring multiple devices with desi gn revisioning in slave serial mode xcfxxp platform flash prom first prom (prom 0) v ccint v cco (2) v ccj (2) tdi tms tck en_ex_sel rev_sel[1:0] d0 clk (3) ce ceo oe/reset cf tdo xilinx fpga slave serial din cclk done init_b prog_b tdi tms tck v ccj v cco v ccint 4.7 k ? 4.7 k ? (1) v cco (2) tdi tms tck tdo notes: 1 for mode pin connections and done pin pullup value, refer to the appropriate fpga data sheet. 2 for compatible voltages, refer to the appropriate data sheet. 3 in slave serial mode, the configuration interface can be clocked by an external oscillator, or optionally the clkout signal can be used to drive the fpga's configuration clock (cclk). if the xcfxxp prom's clkout signal is used, then it must be tied to a 4.7k ? resistor pulled up to v cco . xcfxxp platform flash prom cascaded prom (prom 1) v ccint v cco (2) v ccj (2) tdi tms tck en_ex_sel rev_sel[1:0] d0 clk (3) ce ceo oe/reset cf tdo v ccj v cco v ccint ds123_17_110503 design revision control logic en_ext_sel rev_sel[1:0] done cf / prog_b xilinx fpga slave serial din cclk done init_b prog_b tdi tms tck mode pins (1) tdo gnd gnd gnd dout mode pins (1) gnd external (3) oscillator
platform flash in-system programmable configuration proms 20 www.xilinx.com ds123 (v2.1) november 18, 2003 1-800-255-7778 preliminary product specification r figure 15: configuring multiple devices with de sign revisioning in slave selectmap mode xcfxxp platform flash prom first prom (prom 0) vccint v cco (2) v ccj (2) tdi tms tck en_ex_sel rev_sel[1:0] gnd d[0:7] clk (5) ce ceo oe/reset cf busy (4) tdo xilinx fpga slave selectmap d[0:7] cclk done init_b prog_b busy (4) tdi tms tck mode pins (1) rdwr_b cs_b tdo v ccj v cco v ccint 4.7 k ? 4.7 k ? (1) v cco (2) tdi tms tck tdo notes: 1 for mode pin connections and done pin pullup value, refer to the appropriate fpga data sheet. 2 for compatible voltages, refer to the appropriate data sheet. 3 rdwr_b (or write) must be either driven low or pulled down exernally. one option is shown. 4 the busy pin is only available with the xcfxxp platform flash prom, and the connection is only required for high frequency selectmap mode configuration. for busy pin requirements, refer to the appropriate fpga data sheet. 5 in slave selectmap mode, the configuration interface can be clocked by an external oscillator, or optionally the clkout signal can be used to drive the fpga's configuration clock (cclk). if the xcfxxp prom's clkout signal is used, then it must be tied to a 4.7k ? resistor pulled up to v cco . xilinx fpga slave selectmap d[0:7] cclk done init_b prog_b busy (4) tdi tms tck mode pins (1) rdwr_b cs_b tdo xcfxxp platform flash prom cascaded prom (prom 1) v ccint v cco (2) v ccj (2) tdi tms tck en_ex_sel rev_sel[1:0] gnd d[0:7] clk (5) ce ceo oe/reset cf busy (4) tdo v ccj v cco v ccint 1k ? i/o (3) 1k ? i/o (3) en_ext_sel rev_sel[1:0] cf done prog_b cs_b[1:0] design revision control logic gnd gnd ds123_18_110303 external (5) oscillator
platform flash in-system programmable configuration proms ds123 (v2.1) november 18, 2003 www.xilinx.com 21 preliminary product specification 1-800-255-7778 r reset and power-on reset activation at power up, the device requires the v ccint power supply to monotonically rise to the nominal operating voltage within the specified v ccint rise time. if the power supply cannot meet this requirement, then the device might not perform power-on reset properly. during the power-up sequence, oe/reset is held low by the prom. once the required supplies have reached their respective por (power on reset) thresholds, the oe/reset release is delayed (t oer minimum) to allow more margin for the power supplies to stabilize before initiating configuration. the oe/reset pin is connected to an external pull-up resistor and also to the target fpga's init pin. fo r systems utilizing slow-rising power supplies, an additional power monitoring circuit can be used to delay the target configuration until the system power reaches minimum operating voltages by holding the oe/reset pin low. when oe/reset is released, the fpgas init pin is pulled high allowing the fpga's configu- ration sequence to begin. if the power drops below the power-down threshold (v ccpd ), the prom resets and oe/reset is again held low until the after the por thresh- old is reached. oe/reset polarity is not programmable. these power-up requirements are shown graphically in figure 16 . for a fully powered platform flash prom, a reset occurs whenever oe/reset is asserted (low) or ce is deas- serted (high). the address counter is reset, ceo is driven high, and the remaining outputs are placed in a high-imped- ance state. notes: 1. the xcfxxs prom only requires v ccint to rise above its por threshold before releasing oe/reset . 2. the xcfxxp prom requires both v ccint to rise above its por threshold and for v cco to reach the recommended operating voltage level before releasing oe/reset . i/o input voltage tolerance and power sequencing the i/os on each re-programmable platform flash prom are fully 3.3v-tolerant. this a llows 3v cmos signals to con- nect directly to the inputs without damage. the v ccint power can be applied before or after 3v cmos signals are applied to the i/os. the core power supply (v ccint ), jtag pin power supply (v ccj ), and output power supply (v cco ) can be applied in any order. the prom should not be par- tially powered, with one supply left unpowered while another supply is fully powere d. failure to power the prom correctly may result in damage to the device. additionally, for the xcfxxs prom only, when v cco is sup- plied at 2.5v or 3.3v and v ccint is supplied at 3.3v, the i/os are 5v-tolerant. this allows 5v cmos signals to connect directly to the inputs on a powered xcfxxs prom without damage. standby mode the prom enters a low-power standby mode whenever ce is deasserted (high). in standby mode, the address counter is reset, ceo is driven high, and t he remaining outputs are placed in a high-impedance state regardless of the state of the oe/reset input. for the device to remain in the low-power standby mode, the jtag pins tms, tdi, and tdo must not be pulled low, and tck must be stopped (high or low). figure 16: platform flash prom power-up requirements t oer v ccint v ccpor v ccpd 200 s ramp 50 ms ramp t oer t rst time (ms) a slow-ramping v ccint supply may still be below the minimum operating voltage when oe/reset is released. in this case, the configuration sequence must be delayed until both v ccint and v cco have reached their recommended operating conditions. recommended operating range delay or restart configuration ds123_21_103103
platform flash in-system programmable configuration proms 22 www.xilinx.com ds123 (v2.1) november 18, 2003 1-800-255-7778 preliminary product specification r dc electrical characteristics absolute maximum ratings , page 23 supply voltage requirements for power-on reset and power-down , page 23 recommended operating conditions , page 24 quality and reliability characteristics , page 24 dc characteristics over operating conditions , page 25 ac electrical characteristics ac characteristics over operating conditions , page 26 ac characteristics over operat ing conditions when cascading , page 29 ta bl e 9 : truth table for xcfxxs prom control inputs control inputs internal address outputs oe/reset ce data ceo icc high low if address < tc (2) : increment active high active if address = tc (2) : don't change high-z low reduced low low held reset high-z high active x (1) high held reset high-z high standby notes: 1. x = don?t care. 2. tc = terminal count = highest address value. tc + 1 = address 0. ta bl e 1 0 : truth table for xcfxxp prom control inputs control inputs internal address outputs oe/reset ce busy data ceo clkout icc high low low if address < tc (2) and address < ea (3) : increment active high active active if address < tc (2) and address = ea (3) : don't change high-z high high-z reduced else if address = tc (2) : don't change high-z low high-z reduced high low high unchanged active and unchanged high active active low low x held reset (4) high-z high high-z active x (1) high x held reset (4) high-z high high-z standby notes: 1. x = don?t care. 2. tc = terminal count = highest address value. 3. for the xcfxxp with design revisioning enabled, ea = end address (last address in t he selected design revision). 4. for the xcfxxp with design revisioning enabled, held reset = address reset to the beginning address of the selected bank. if design revisioning is not enabled, then held reset = address reset to address 0.
platform flash in-system programmable configuration proms ds123 (v2.1) november 18, 2003 www.xilinx.com 23 preliminary product specification 1-800-255-7778 r absolute maximum ratings supply voltage requirements fo r power-on reset and power-down symbol description xcf01s, xcf02s, xcf04s xcf08p, xcf16p, XCF32P units v ccint internal supply voltage relative to gnd ?0.5 to +4.0 ?0.5 to +2.7 v v cco i/o supply voltage relative to gnd ?0.5 to +4.0 ?0.5 to +4.0 v v ccj jtag i/o supply voltage relative to gnd ?0.5 to +4.0 ?0.5 to +4.0 v v in input voltage with respect to gnd v cco < 2.5v ?0.5 to +3.6 ?0.5 to v cco +0.5 v v cco 2.5v ?0.5 to +5.5 ?0.5 to v cco +0.5 v v ts voltage applied to high-z output v cco < 2.5v ?0.5 to +3.6 ?0.5 to v cco +0.5 v v cco 2.5v ?0.5 to +5.5 ?0.5 to v cco +0.5 v t stg storage temperature (ambient) ?65 to +150 ?65 to +150 c t sol (3) maximum soldering temperature (10s @ 1/16 in.) +220 +220 c t j junction temperature +125 +125 c notes: 1. maximum dc undershoot below gnd must be limited to either 0.5v or 10 ma, whichever is easier to achieve. during transitions, t he device pins can undershoot to ?2.0v or overshoot to +7.0v, provided this over- or under shoot lasts less then 10 ns and with the forcing current being limited to 200 ma. 2. stresses beyond those listed under absolute maximum ratings mi ght cause permanent damage to the device. these are stress rati ngs only, and functional operation of the device at thes e or any other conditions beyond those li sted under operating conditions is not impli ed. exposure to absolute maximum ratings conditions for extended peri ods of time adversely affects device reliability. 3. for soldering guidelines, see the information on "packaging and thermal characteristics" at www.xilinx.com . symbol description xcf01s, xcf02s, xcf04s xcf08p, xcf16p, XCF32P units min max min max v ccpor por threshold for the v ccint supply 1 - tbd - v t oer oe/reset release delay following por (4) 010tbdms t vcc v ccint rise time from 0v to nominal voltage 0.2 50 0.2 50 ms t rst time required to trigger a device reset when the v ccint supply drops below the maximum v ccpd threshold 10 - 10 - ms v ccpd power-down threshold for v ccint supply - 1 - tbd v notes: 1. v ccint , v cco , and v ccj supplies may be applied in any order. 2. at power up, the device requires the v ccint power supply to monotonically rise to the nominal operating voltage within the specified t vcc rise time. if the power supply cannot meet this requirement, then t he device might not perform power-on-reset properly. see figure 16, page 21 . 3. if the v ccint and v cco supplies do not reach their respective recommended operati ng conditions before the oe/reset pin is released, then the configuration data from the prom will not be available at t he recommended threshold levels. the configuration sequence must be delayed until both v ccint and v cco have reached their recommended operating conditions.
platform flash in-system programmable configuration proms 24 www.xilinx.com ds123 (v2.1) november 18, 2003 1-800-255-7778 preliminary product specification r recommended operating conditions quality and reliability characteristics symbol description xcf01s, xcf02s, xcf04s xcf08p, xcf16p, XCF32P units min max min max v ccint internal voltage supply 3.0 3.6 1.65 2.0 v v cco /v ccj supply voltage for output drivers 3.3v operation 3.0 3.6 3.0 3.6 v 2.5v operation 2.3 2.7 2.3 2.7 v 1.8v operation 1.7 2.0 1.7 2.0 v 1.5v operation - - tbd tbd v v il low-level input voltage 2.5v or 3.3v operation 0 0.8 0 0.8 v 1.8v operation 0 20% v cco 020% v cco v v ih high-level input voltage 2.5v or 3.3v operation 2.0 5.5 2.0 3.6 v 1.8v operation 70% v cco 3.6 70% v cco 3.6 v v o output voltage 0 v cco 0v cco v t a operating ambient temperature ?40 85 ?40 85 c symbol description min max units t dr data retention 20 - years n pe program/erase cycles (endurance) 20,000 - cycles v esd electrostatic discharge (esd) 2,000 - volts
platform flash in-system programmable configuration proms ds123 (v2.1) november 18, 2003 www.xilinx.com 25 preliminary product specification 1-800-255-7778 r dc characteristics over operating conditions symbol description xcf01s, xcf02s, xcf04s xcf08p, xcf16p, XCF32P units test conditions min max test conditions min max v oh high-level output voltage for 3.3v outputs i oh = ?4 ma 2.4 - i oh = tbd tbd - v high-level output voltage for 2.5v outputs i oh = ?500 a v cco ? 0.4 - i oh = tbd tbd - v high-level output voltage for 1.8v outputs i oh = ?50 a v cco ? 0.4 - i oh = tbd tbd - v high-level output voltage for 1.5v outputs - - - i oh = tbd tbd - v v ol low-level output voltage for 3.3v outputs i ol = 8 ma -0.4 i ol = tbd -tbd v low-level output voltage for 2.5v outputs i ol = 500 a -0.4 i ol = tbd -tbd v low-level output voltage for 1.8v outputs i ol = 50 a - 0.4 i ol = tbd - tbd v low-level output voltage for 1.5v outputs ---i ol = tbd - tbd v i ccint internal voltage supply current, active mode 33 mhz - 10 tbd - 10 ma i cco output driver supply current, active mode tbd - tbd tbd - tbd ma i ccj jtag supply current, active mode tbd - tbd tbd - tbd ma i ccints internal voltage supply current, standby mode --1--tbdma i ccos output driver supply current, standby mode tbd - tbd tbd - tbd ma i ccjs jtag supply current, standby mode tbd - tbd tbd - tbd ma i ilj jtag pins tms, tdi, and tdo pull-up current v ccj = max v in = gnd -100 v ccj = max v in = gnd -tbda i il input leakage current v ccint = max v in = gnd or v ccint ?10 10 v ccint = max v in = gnd or v ccint tbd tbd a i ih input and output high-z leakage current v ccint = max v in = gnd or v ccint ?10 10 v ccint = max v in = gnd or v ccint tbd tbd a c in input capacitance v in = gnd f = 1.0 mhz -8 v in = gnd f = 1.0 mhz -tbdpf c out output capacitance v in = gnd f = 1.0 mhz -14 v in = gnd f = 1.0 mhz -tbdpf
platform flash in-system programmable configuration proms 26 www.xilinx.com ds123 (v2.1) november 18, 2003 1-800-255-7778 preliminary product specification r ac characteristics over operating conditions symbol description xcf01s, xcf02s, xcf04s xcf08p, xcf16p, XCF32P units min max min max t oe oe/reset to data delay (6) when v cco = 3.3v or 2.5v -10tbdtbdns oe/reset to data delay (6) when v cco = 1.8v -30tbdtbdns t ce ce to data delay (5) when v cco = 3.3v or 2.5v -15tbdtbdns ce to data delay (5) when v cco = 1.8v -30tbdtbdns t cac clk to data delay when v cco = 3.3v or 2.5v -15tbdtbdns clk to data delay when v cco = 3.3v or 2.5v -30tbdtbdns t oh data hold from ce , oe/reset , or clk when v cco = 3.3v or 2.5v 0-tbdtbdns data hold from ce , oe/reset , or clk when v cco = 1.8v 0-tbdtbdns t df ce or oe/reset to data float delay (2) when v cco = 3.3v or 2.5v -25tbdtbdns ce or oe/reset to data float delay (2) when v cco = 1.8v -30tbdtbdns t cyc clock period (7) when v cco = 3.3v or 2.5v 30 - tbd tbd ns clock period when v cco = 1.8v 67 - tbd tbd ns t lc clk low time (3) when v cco = 3.3v or 2.5v 10 - tbd tbd ns clk low time (3) when v cco = 1.8v 15 - tbd tbd ns ce oe/reset clk clkout (optional) busy (optional) data t ce t lc t hc t sce t oe t cac t hce t hoe t cyc t oh t df t oh t hb t sb t oec t cec t clko t coh t cdd cf en_ext_sel rev_sel[1:0] t sxt t hxt t srv t hrv ds123_22_110403
platform flash in-system programmable configuration proms ds123 (v2.1) november 18, 2003 www.xilinx.com 27 preliminary product specification 1-800-255-7778 r t hc clk high time (3) when v cco = 3.3v or 2.5v 10 - tbd tbd ns clk high time (3) when v cco = 1.8v 15 - tbd tbd ns t sce ce setup time to clk (guarantees proper counting) (3) when v cco = 3.3v or 2.5v 20 - tbd tbd ns ce setup time to clk (guarantees proper counting) (3) when v cco = 1.8v 30 tbd tbd ns t hce ce hold time (guarantees counters are reset) (5) when v cco = 3.3v or 2.5v 250 - tbd tbd ns ce hold time (guarantees counters are reset) (5) when v cco = 1.8v 250 - tbd tbd ns t hoe oe/reset hold time (guarantees counters are reset) (6) when v cco = 3.3v or 2.5v 250 - tbd tbd ns oe/reset hold time (guarantees counters are reset) (6) when v cco = 1.8v 250 - tbd tbd ns t sb busy setup time to clk when v cco = 3.3v or 2.5v --tbdtbdns busy setup time to clk when v cco = 1.8v --tbdtbdns t hb busy hold time to clk when v cco = 3.3v or 2.5v --tbdtbdns busy hold time to clk when v cco = 1.8v --tbdtbdns t clko clk input to clkout output delay when v cco = 3.3v or 2.5v --tbdtbdns clk input to clkout output delay when v cco = 1.8v --tbdtbdns t cec ce to clkout delay when v cco = 3.3v or 2.5v --tbdtbdns ce to clkout delay when v cco = 1.8v --tbdtbdns t oec oe/reset to clkout delay when v cco = 3.3v or 2.5v --tbdtbdns oe/reset to clkout delay when v cco = 1.8v --tbdtbdns t cdd clkout to data delay when v cco = 3.3v or 2.5v --tbdtbdns clkout to data delay when v cco = 1.8v --tbdtbdns t coh data hold from clkout when v cco = 3.3v or 2.5v --tbdtbdns data hold from clkout when v cco = 1.8v --tbdtbdns t sxt en_ext_sel setup time to cf (rising edge) when v cco = 3.3v or 2.5v --tbdtbdns en_ext_sel setup time to cf (rising edge) when v cco = 1.8v --tbdtbdns t hxt en_ext_sel hold time from cf (rising edge) when v cco = 3.3v or 2.5v --tbdtbdns en_ext_sel hold time from cf (rising edge) when v cco = 1.8v --tbdtbdns t srv rev_sel setup time to cf (rising edge) when v cco = 3.3v or 2.5v --tbdtbdns rev_sel setup time to cf (rising edge) when v cco = 1.8v --tbdtbdns symbol description xcf01s, xcf02s, xcf04s xcf08p, xcf16p, XCF32P units min max min max
platform flash in-system programmable configuration proms 28 www.xilinx.com ds123 (v2.1) november 18, 2003 1-800-255-7778 preliminary product specification r t hrv rev_sel hold time from cf (rising edge) when v cco = 3.3v or 2.5v --tbdtbdns rev_sel hold time from cf (rising edge) when v cco = 1.8v --tbdtbdns t ff clkout default (fast) frequency --tbdtbdns clkout default (fast) frequency with compression --tbdtbdns t sf clkout alternate (slower) frequency --tbdtbdns clkout alternate (slower) frequency with compression --tbdtbdns notes: 1. ac test load = 50 pf. 2. float delays are measured with 5 pf ac loads. transition is measured at 200 mv from steady state active levels. 3. guaranteed by design, not tested. 4. all ac parameters are measured with v il = 0.0v and v ih = 3.0v. 5. if t hce high < 2 s, t ce = 2 s. 6. if t hoe low < 2 s, t oe = 2 s. 7. minimum possible t cyc . actual t cyc = t cac + fpga data setup time. if fpga data setup time = 15 ns, actual t cyc =15ns +15ns = 30ns. symbol description xcf01s, xcf02s, xcf04s xcf08p, xcf16p, XCF32P units min max min max
platform flash in-system programmable configuration proms ds123 (v2.1) november 18, 2003 www.xilinx.com 29 preliminary product specification 1-800-255-7778 r ac characteristics over oper ating conditions when cascading symbol description xcf01s, xcf02s, xcf04s xcf08p, xcf16p, XCF32P units min max min max t cdf clk to output float delay (2,3) when v cco = 2.5v or 3.3v -25tbdtbdns clk to output float delay (2,3) when v cco = 1.8v -35tbdtbdns t ock clk to ceo delay (3,5) when v cco = 2.5v or 3.3v -20tbdtbdns clk to ceo delay (3,5) when v cco = 1.8v -35tbdtbdns t oce ce to ceo delay (3) when v cco = 2.5v or 3.3v -20tbdtbdns ce to ceo delay (3) when v cco = 1.8v -35tbdtbdns t ooe oe/reset to ceo delay (3) when v cco = 2.5v or 3.3v -20tbdtbdns oe/reset to ceo delay (3) when v cco = 1.8v -35tbdtbdns t coce clkout to ceo delay when v cco = 2.5v or 3.3v --tbdtbdns clkout to ceo delay when v cco = 1.8v --tbdtbdns t codf clkout to output float delay when v cco = 2.5v or 3.3v --tbdtbdns clkout to output float delay when v cco = 1.8v --tbdtbdns notes: 1. ac test load = 50 pf. 2. float delays are measured with 5 pf ac loads. transition is measured at 200 mv from steady state active levels. 3. guaranteed by design, not tested. 4. all ac parameters are measured with v il = 0.0v and v ih = 3.0v. 5. for cascaded proms minimum, t cyc = t ock + fpga data setup time. oe/reset ce clk clkout (optional) data ceo t oce t ooe first bit last bit t cdf t codf t ock t coce ds123_23_102203
platform flash in-system programmable configuration proms 30 www.xilinx.com ds123 (v2.1) november 18, 2003 1-800-255-7778 preliminary product specification r pinouts and pin descriptions the xcfxxs platform flash prom is available in the vo20 pa ckage. the xcfxxp platform flash prom is available in the vo48 and fs48 packages. this section includes: ta bl e 1 1 , xcfxxs pin names and descriptions , page 30 figure 17 , vo20 pinout diagram (top view) with pin names , page 31 ta bl e 1 2 , xcfxxp pin names and descriptions , page 32 figure 18 , vo48 pinout diagram (top view) with pin names , page 34 figure 19 , fs48 pinout diagram (top view) , page 34 ta bl e 1 3 , fs48 pin number/name reference , page 35 notes: 1. vo20 denotes a 20-pin (tssop) plastic thin shrink small outline package 2. vo48 denotes a 48-pin (tsop) plastic thin small outline package. 3. fs48 denotes a 48-pin (tfbga) plastic thin fine pitch ball grid array (0.8 mm pitch). xcfxxs pinouts and pin descriptions ta bl e 1 1 provides a list of the pin names and descri ptions for the xcfxxs 20-pin vo20 package. ta bl e 1 1 : xcfxxs pin names and descriptions pin name boundary scan order boundary scan function pin description 20-pin tssop (vo20) d0 4data out d0 is the data output pin to provide data for configuring an fpga in serial mode. the d0 output is set to a high-impedance state during ispen (when not clamped). 1 3 output enable clk 0data in configuration clock input. each rising edge on the clk input increments the internal address counter if the clk input is selected, ce is low, and oe/reset is high. 3 oe/reset 20 data in output enable/reset (open-drain i/o). when low, this input holds the address counter reset and the data output is in a high-impedance state. this is a bidirectional open-drain pin that is held low while the prom is reset. polarity is not programmable. 8 19 data out 18 output enable ce 15 data in chip enable input. when ce is high, the device is put into low-power standby mode, the address counter is reset, and the data pins are put in a high-impedance state. 10 cf 22 data out configuration pulse (open-drain output). allows jtag config instruction to initiate fpga configuration without powering down fpga. this is an open-drain output that is pulsed low by the jtag config command. 7 21 output enable ceo 12 data out chip enable output. chip enable output (ceo ) is connected to the ce input of the next prom in the chain. this output is low when ce is low and oe/reset input is high, and the internal address counter has been incremented beyond its terminal count (tc) value. ceo returns to high when oe/reset goes low or ce goes high. 13 11 output enable tms mode select jtag mode select input. the state of tms on the rising edge of tck determines the state transitions at the test access port (tap) controller. tms has an internal 50k ? resistive pull-up to v ccj to provide a logic "1" to the device if the pin is not driven. 5
platform flash in-system programmable configuration proms ds123 (v2.1) november 18, 2003 www.xilinx.com 31 preliminary product specification 1-800-255-7778 r xcfxxs pinout diagram tck clock jtag clock input. this pin is the jtag test clock. it sequences the tap controller and all the jtag test and programming electronics. 6 tdi data in jtag serial data input. this pin is the serial input to all jtag instruction and data registers. tdi has an internal 50k ? resistive pull-up to v ccj to provide a logic "1" to the device if the pin is not driven. 4 tdo data out jtag serial data output. this pin is the serial output for all jtag instruction and data registers. tdo has an internal 50k ? resistive pull-up to v ccj to provide a logic "1" to the system if the pin is not driven. 17 vccint +3.3v supply. positive 3.3v supply voltage for internal logic. 18 vcco +3.3v, 2.5v, or 1.8v i/o supply. positive 3.3v, 2.5v, or 1.8v supply voltage connected to the output voltage drivers and input buffers. 19 vccj +3.3v, 2.5v, or 1.8v jtag i/o supply. positive 3.3v, 2.5v, or 1.8v supply voltage connected to the tdo output voltage driver and tck, tms, and tdi input buffers. 20 gnd ground 11 dnc do not connect. (these pins must be left unconnected.) 2 , 9, 12, 14, 15, 16 figure 17: vo20 pinout diagram (top view) with pin names ta bl e 1 1 : xcfxxs pin names and descriptions (continued) pin name boundary scan order boundary scan function pin description 20-pin tssop (vo20) vo20 top view ds123_02_102303 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 d0 (dnc) clk tdi tms tck cf oe/reset (dnc) ce vccj vcco vccint tdo (dnc) (dnc) ceo (dnc) gnd (dnc)
platform flash in-system programmable configuration proms 32 www.xilinx.com ds123 (v2.1) november 18, 2003 1-800-255-7778 preliminary product specification r xcfxxp pinouts and pin descriptions ta bl e 1 2 provides a list of the pin names and descriptions for the xcfxxp 48-pin vo48 and 48-pin fs48 packages. ta bl e 1 2 : xcfxxp pin names and descriptions pin name boundary scan order boundary scan function pin description 48-pin tsop (vo48) 48-pin tfbga (fs48) d0 28 data out d0 is the data output pin to provide data for configuring an fpga in serial mode. d0-d7 are the data output pins to provide parallel data for configuring a xilinx fpga in selectmap (parallel) mode. the d0 output is set to a high-impedance state during ispen (when not clamped). the d1-d7 outputs are set to a high-impedance state during ispen (when not clamped) and when serial mode is selected for configuration. the d1-d7 pins can be left unconnected when the prom is used in serial mode. 28 h6 27 output enable d1 26 data out 29 h5 25 output enable d2 24 data out 32 e5 23 output enable d3 22 data out 33 d5 21 output enable d4 20 data out 43 c5 19 output enable d5 18 data out 44 b5 17 output enable d6 16 data out 47 a5 15 output enable d7 14 data out 48 a6 13 output enable clk 01 data in configuration clock input. an internal programmable control bit selects between the internal oscillator and the clk input pin as the clock source to control the configuration sequence. each rising edge on the clk input increments the internal address counter if the clk input is selected, ce is low, and oe/reset is high. 12 b3 oe/reset 04 data in output enable/reset (open-drain i/o). when low, this input holds the address counter reset and the data and clkout outputs are placed in a high-impedance state. this is a bidirectional open-drain pin that is held low while the prom is reset. polarity is not programmable. 11 a3 03 data out 02 output enable ce 00 data in chip enable input. when ce is high, the device is put into low-power standby mode, the address counter is reset, and the data and clkout outputs are placed in a high-impedance state. 13 b4 cf 11 data in configuration pulse (open-drain i/o). as an output, this pin allows jtag config instruction to initiate fpga configuration without powering down the fpga. this is an open-drain signal that is pulsed low by the jtag config command. as an input, when low, this signal enables the device to sample the current design revision selection. 6d1 10 data out 09 output enable
platform flash in-system programmable configuration proms ds123 (v2.1) november 18, 2003 www.xilinx.com 33 preliminary product specification 1-800-255-7778 r ceo 06 data out chip enable output. chip enable output (ceo ) is connected to the ce input of the next prom in the chain. this output is low when ce is low and oe/reset input is high, and the internal address counter has been incremented beyond its terminal count (tc) value. ceo returns to high when oe/reset goes low or ce goes high. 10 d2 05 output enable en_ext_sel 31 data in enable external selection input. when this pin is low, design revision selection is controlled by the revision select pins. when this pin is high, design revision selection is controlled by the internal programmable revision select control bits. en_ext_sel has an internal 50k ? resistive pull-up to v cco to provide a logic "1" to the device if the pin is not driven. 25 h4 rev_sel0 30 data in revision select[1:0] input s. when the en_ext_sel is low, the revision select pins are used to select the design revision to be enabled, overriding the internal programmable revision select control bits. the revision select[1:0] inputs have an internal 50k ? resistive pull-up to vcco to provide a logic "1" to the device if the pins are not driven. 26 g3 rev_sel1 29 data in 27 g4 busy 12 data in busy input. the busy input is enabled when parallel mode is selected for configuration. when busy is high, the internal address counter stops incrementing and the current data remains on the data pins. on the first rising edge of clk after busy transitions from high to low, the data for the next address is driven on the data pins. when serial mode or decompression is enabled during device programming, the busy input is disabled. busy has an internal 50k ? resistive pull-down to gnd to provide a logic "0" to the device if the pin is not driven. 5c1 clkout 08 data out configuration clock output. an internal programmable control bit enables the clkout signal which is sourced from either the internal oscillator or the clk input pin. each rising edge on the selected clock source increments the internal address counter if data is available, ce is low, and oe/reset is high. output data is available on the rising edge of clkout. clkout remains low when data is not ready. when clkout is not enabled , the clkout pin is put into a high-impedance state. 9c2 07 output enable tms mode select jtag mode select input. the state of tms on the rising edge of tck determines the state transitions at the test access port (tap) controller. tms has an internal 50k ? resistive pull-up to v ccj to provide a logic "1" to the device if the pin is not driven. 21 e2 tck clock jtag clock input. this pin is the jtag test clock. it sequences the tap controller and all the jtag test and programming electronics. 20 h3 tdi data in jtag serial data input. this pin is the serial input to all jtag instruction and data registers. tdi has an internal 50k ? resistive pull-up to v ccj to provide a logic "1" to the device if the pin is not driven. 19 g1 ta bl e 1 2 : xcfxxp pin names and descriptions pin name boundary scan order boundary scan function pin description 48-pin tsop (vo48) 48-pin tfbga (fs48)
platform flash in-system programmable configuration proms 34 www.xilinx.com ds123 (v2.1) november 18, 2003 1-800-255-7778 preliminary product specification r xcfxxp pinout diagrams tdo data out jtag serial data output. this pin is the serial output for all jtag instruction and data registers. tdo has an internal 50k ? resistive pull-up to v ccj to provide a logic "1" to the system if the pin is not driven. 22 e6 vccint +1.8v supply. positive 1.8v supply voltage for internal logic. 4, 15, 34 b1, e1, g6 vcco +3.3v, 2.5v, or 1.8v i/o supply . positive 3.3v, 2.5v, or 1.8v supply voltage connected to the output voltage drivers and input buffers. 8, 30, 38, 45 b2, c6, d6, g5 vccj +3.3v, 2.5v, or 1.8v jtag i/o supply. positive 3.3v, 2.5v, or 1.8v supply voltage connected to the tdo output voltage driver and tck, tms, and tdi input buffers. 24 h2 gnd ground 2, 7, 17, 23, 31, 36, 46 a1, a2, b6, f1, f5, f6, h1 dnc do not connect. (these pins must be left unconnected.) 1, 3, 14, 16, 18, 35, 37, 39, 40, 41, 42 a4, c3, c4, d3, d4, e3, e4, f2, f3, f4, g2 ta bl e 1 2 : xcfxxp pin names and descriptions pin name boundary scan order boundary scan function pin description 48-pin tsop (vo48) 48-pin tfbga (fs48) figure 18: vo48 pinout diagram (top view) with pin names ds123_24_111703 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 dnc gnd dnc vccint busy cf gnd vcco clkout ceo oe/reset clk ce dnc vccint dnc gnd dnc tdi tck tms tdo gnd vccj 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 d7 d6 gnd vcco d5 d4 dnc dnc dnc dnc vcco dnc gnd dnc vccint d3 d2 gnd vcco d1 d0 rev_sel1 rev_sel0 en_ext_sel vo48 top view figure 19: fs48 pinout diagram (top view) 123456 ds121_01_102303 a b c d e f g h fs48 top view
platform flash in-system programmable configuration proms ds123 (v2.1) november 18, 2003 www.xilinx.com 35 preliminary product specification 1-800-255-7778 r ta bl e 1 3 : fs48 pin number/name reference pin number pin name pin number pin name a1 gnd e1 vccint a2 gnd e2 tms a3 oe/reset e3 dnc a4 dnc e4 dnc a5 d6 e5 d2 a6 d7 e6 tdo b1 vccint f1 gnd b2 vcco f2 dnc b3 clk f3 dnc b4 ce f4 dnc b5 d5 f5 gnd b6 gnd f6 gnd c1 busy g1 tdi c2 clkout g2 dnc c3 dnc g3 rev_sel0 c4 dnc g4 rev_sel1 c5 d4 g5 vcco c6 vcco g6 vccint d1 cf h1 gnd d2 ceo h2 vccj d3 dnc h3 tck d4 dnc h4 en_ext_sel d5 d3 h5 d1 d6 vcco h6 d0
platform flash in-system programmable configuration proms 36 www.xilinx.com ds123 (v2.1) november 18, 2003 1-800-255-7778 preliminary product specification r ordering information valid ordering combinations marking information xcf01svo20 c xcf08pvo48 c xcf08pfs48 c xcf02svo20 c xcf16pvo48 c xcf16pfs48 c xcf04svo20 c XCF32Pvo48 c XCF32Pfs48 c xcf04s vo20 c operating range/processing c = (t a = ?40 c to +85 c) package type vo20 = 20-pin tssop package device number xcf01s xcf02s xcf04s XCF32P fs48 c operating range/processing c = (t a = ?40 c to +85 c) package type vo48 = 48-pin tsop package fs48 = 48-pin tfbga package device number xcf08p xcf16p XCF32P xcf04s -v operating range/processing c = (t a = ?40 c to +85 c) package type v = 20-pin tssop package (vo20) vo48 = 48-pin tsop package (vo48) f48 = 48-pin tfbga package (fs48) device number xcf01s xcf02s xcf04s xcf08p xcf16p XCF32P
platform flash in-system programmable configuration proms ds123 (v2.1) november 18, 2003 www.xilinx.com 37 preliminary product specification 1-800-255-7778 r revision history the following table shows the revision history for this document. date version revision 04/29/03 1.0 xilinx initial release. 06/03/03 1.1 made edits to all pages. 11/05/03 2.0 major revision. 11/18/03 2.1 pinout corrections as follows: ta bl e 1 2 : - for vo48 package, removed 38 from vccint and added it to vcco. - for fs48 package, removed pin d6 from vccint and added it to vcco. ta bl e 1 3 (fs48 package): - for pin d6, changed name from vccint to vcco. - for pin a4, changed name from gnd to dnc. figure 18 (vo48 package): for pin 38, changed name from vccint to vcco.

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