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revision 1/may 09, 2002
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the sk10/100el90w is a triple ecl to pecl/lvpecl and lvecl to pecl/lvpecl translator. it is fully compatible with mc100el90 and mc100lvel90. the sk10/ 100el90w provides a v bb output for single-ended use or dc bias for ac coupling to the device. v bb is an output pin and should be used as a bias for the el90w as its current source/sink capability is limited. whenever used, the v bb output pin should be bypassed to v cc via a 0.01 f capacitor. to accomplish levels of translation, the el90w requires three power rails, v cc , v ee and gnd. please refer to the function table below for more details. v cc supply should be connected to the positive supply, and v ee should be connected to the negative supply. the gnd pins are connected to the system ground plane. both v cc and v ee pins should be bypassed to ground via a 0.01 f capacitor. under open input conditions, the d* input will be biased at v ee /2, and the d input will be pulled to v ee . this condition will force the q output to low, ensuring stability. ? extended supply voltage range (v ee = ?5.5v to ?3.0v and v cc = 3.0v to 5.5v) high bandwidth output transition 500 ps propagation delay v bb output internal input pulldown resistors new differential input common mode range fully compatible with mc100el90 and mc100lvel90 esd protection of >4000v industrial temperature range: ?40 o c to +85 o c available in 20-lead soic package function table n i pn o i t c n u f * n d , n ds t u p n i l c e v l / l c e l a i t n e r e f f i d * n q , n qs t u p t u o l c e p v l / l c e p l a i t n e r e f f i d v b b t u p t u o e g a t l o v e c n e r e f e r l c e v l / l c e n o i t c n u fe e vc c v l c e p - o t - l c e v lv 3 . 3 -v 0 . 5 + l c e p v l - o t - l c e v lv 3 . 3 -v 3 . 3 + l c e p - o t - l c ev 0 . 5 -v 0 . 5 + l c p e v l - o t - l c ev 0 . 5 -v 3 . 3 + v cc d0 d1 d1* v bb d2 d2* v ee d0* v bb v cc q0 q1 q1* gnd q2 q2* v cc q0* gnd 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 ecl pecl ecl pecl ecl pecl

revision 1/may 09, 2002

20 pin soic package e a a1 ? t 18x seating plane c l h x 45 ? b d h e 10x 20x 20 11 0.010 (0.25) m t a s b s 0.010 (0.25) m bm notes: 1. dimensions and tolerances per asme y14.5m, 1994. 2. controlling dimension: millimeters. 3. dimensions d and e do not include mold protrusion. 4. maximum mold protrusion 0.15 per side. 5. dimension b does not include dambar protrusion. allowable dambar protrusion shall be 0.13 total in excess of b dimension at maximum material condition. s r e t e m i l l i m m i dn i mx a m a5 3 . 25 6 . 2 1 a0 1 . 05 2 . 0 b5 3 . 09 4 . 0 c3 2 . 02 3 . 0 d5 6 . 2 15 9 . 2 1 e0 4 . 70 6 . 7 ec s b 7 2 . 1 h5 0 . 0 15 5 . 0 1 h5 2 . 05 7 . 0 l0 5 . 00 9 . 0 0 o 7 o

revision 1/may 09, 2002 0 4 - = a t o c0 = a t o c5 2 + = a t o c5 8 + = a t o c l o b m y sc i t s i r e t c a r a h cn i mx a mn i mx a mn i mx a mn i mx a mt i n u v h i e g a t l o v h g i h t u p n i l e 0 1 l e 0 0 1 0 3 2 1 - 5 6 1 1 - 0 9 8 - 0 8 8 - 0 7 1 1 - 5 6 1 1 - 0 4 8 - 0 8 8 - 0 3 1 1 - 5 6 1 1 - 0 1 8 - 0 8 8 - 0 6 0 1 - 5 6 1 1 - 0 2 7 - 0 8 8 - v m v m v l i e g a t l o v w o l t u p n i l e 0 1 l e 0 0 1 0 5 9 1 - 0 1 8 1 - 0 0 5 1 - 5 7 4 1 - 0 5 9 1 - 0 1 8 1 - 0 8 4 1 - 5 7 4 1 - 0 5 9 1 - 0 1 8 1 - 0 8 4 1 - 5 7 4 1 - 0 5 9 1 - 0 1 8 1 - 5 4 4 1 - 5 7 4 1 - v m v m v b b e g a t l o v e c n e r e f e r t u p n i l e 0 1 l e 0 0 1 0 3 4 1 - 0 8 3 1 - 0 0 3 1 - 0 6 2 1 - 0 8 3 1 - 0 8 3 1 - 0 7 2 1 - 0 6 2 1 - 0 5 3 1 - 0 8 3 1 - 0 5 2 1 - 0 6 2 1 - 0 1 3 1 - 0 8 3 1 - 0 9 1 1 - 0 6 2 1 - v m v m i n i ) f f i d ( t n e r r u c t u p n i0 5 1 -0 5 10 5 1 -0 5 10 5 1 -0 5 10 5 1 -0 5 1a i e e t n e r r u c y l p p u s r e w o p 2 6 262626a m 0 4 - = a t o c0 = a t o c5 2 + = a t o c5 8 + = a t o c l o b m y sc i t s i r e t c a r a h cn i mx a mn i mx a mn i mx a mn i mx a mt i n un o i t i d n o c v h o e g a t l o v h g i h t u p t u o l e 0 1 2 9 . 3 2 2 . 2 1 1 . 4 1 4 . 2 8 9 . 3 8 2 . 2 6 1 . 4 6 4 . 2 2 0 . 4 2 3 . 2 9 1 . 4 9 4 . 2 9 0 . 4 9 3 . 2 8 2 . 4 8 5 . 2 v v v c c v 5 = v c c v 3 . 3 = v h o e g a t l o v h g i h t u p t u o l e 0 0 1 5 1 9 . 3 5 1 2 . 2 2 1 . 4 2 4 . 2 5 7 9 . 3 5 7 2 . 2 2 1 . 4 2 4 . 2 5 7 9 . 3 5 7 2 . 2 2 1 . 4 2 4 . 2 5 7 9 . 3 5 7 2 . 2 2 1 . 4 2 4 . 2 v v v c c v 5 = v c c v 3 . 3 = v l o e g a t l o v w o l t u p t u o l e 0 1 5 0 . 3 5 3 . 1 5 3 . 3 5 6 . 1 5 0 . 3 5 3 . 1 7 3 . 3 7 6 . 1 5 0 . 3 5 3 . 1 7 3 . 3 7 6 . 1 5 0 . 3 5 3 . 1 5 0 4 . 3 5 0 7 . 1 v v v c c v 5 = v c c v 3 . 3 = v l o e g a t l o v w o l t u p t u o l e 0 0 1 7 1 . 3 7 4 . 1 5 4 4 . 3 5 4 7 . 1 9 1 . 3 9 4 . 1 8 3 . 3 8 6 . 1 9 1 . 3 9 4 . 1 8 3 . 3 8 6 . 1 9 1 . 3 9 4 . 1 8 3 . 3 8 6 . 1 v v v c c v 5 = v c c v 3 . 3 = i d n g t n e r r u c y l p p u s r e w o p l e 0 1 l e 0 0 1 7 1 7 1 2 3 5 3 7 1 7 1 2 3 5 3 7 1 7 1 2 3 5 3 7 1 7 1 2 3 5 3 a m a m sk10/100el90w pecl/lvpecl output dc electrical characteristics (notes 1, 2) (v ee = 5.5v to 3.0v; v cc = +3.0v to +5.5v; v out loaded 50 ? to v cc 2.0v) sk10/100el90w ecl/lvecl input dc electrical characteristics (notes 1, 2, 6) (v ee = 5.5v to 3.0v; v cc = +3.0v to +5.5v ; v out loaded 50 ? to v cc 2.0v)

revision 1/may 09, 2002
0 4 - = a t o c0 = a t o c5 2 + = a t o c5 8 + = a t o c l o b m y sc i t s i r e t c a r a h cn i mx a mn i mx a mn i mx a mn i mx a mt i n u t w e k s w e k s t u p t u o o t t u p t u o0 0 10 0 10 0 10 0 1s p t l h p t h l p y a l e d n o i t a g a p o r p ) f f i d ( 3 0 2 40 3 55 3 40 5 50 4 40 6 50 6 45 8 5s p t h l p t h p y a l e d n o i t a g a p o r p ) e s ( 3 5 3 45 4 50 5 45 6 50 6 40 8 50 7 45 0 6s p t r t , f s e m i t l l a f / e s i r t u p t u o ) % 0 8 o t % 0 2 ( 5 7 20 7 45 7 20 7 45 7 20 7 45 7 20 7 4s p v r m c e g n a r e d o m n o m m o c 5 + e e v 2 . 1 d n g + e e v 2 . 1 d n g + e e v 2 . 1 d n g + e e v 2 . 1 d n gv v p p g n i w s t u p n i m u m i n i m 4 0 5 10 0 0 10 5 10 0 0 10 5 10 0 0 10 5 10 0 0 1v m sk10/100el90w ac electrical characteristics notes: 1. 10el circuits are designed to meet the dc specifications shown in the table after thermal equilibrium has been established. the circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained. outputs are terminated through a 50 ? resistor to vcc 2.0v. 2. 100k circuits are designed to meet the dc specification shown in the table where transverse airflow greater than 500 lfpm is maintained. 3. duty cycle skew is the difference between t plh and t phl propagation delay through a device. 4. minimum input swing for which parameters guaranteed. 5. cmr range is referenced to the most positive side of the differential input signal. normal operation is obtained if the high level falls within the specified range and the peak-to-peak voltage lies between vpp (min) and 1v. the lower end of the cmr range varies 1:1 with vee and is equal to vee + 1.2v. 6. for standard ecl dc specifications, refer to the ecl logic family standard dc specifications data sheet. 7. for part ordering description, see hpp part ordering information data sheet. (v ee = 5.5v to 3.0v; v cc = +3.0v to +5.5v ; v out loaded 50 ? to v cc 2.0v)
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revision 1/may 09, 2002 "#

e d o c g n i r e d r od i e g a k c a p d w 0 9 l e 0 1 k sc i o s - 0 2 t d w 0 9 l e 0 1 k sc i o s - 0 2 d w 0 9 l e 0 0 1 k sc i o s - 0 2 t d w 0 9 l e 0 0 1 k sc i o s - 0 2 u w 0 9 l e 0 1 k se i d u w 0 9 l e 0 0 1 k se i d division headquarters 10021 willow creek road san diego, ca 92131 phone: (858) 695-1808 fax: (858) 695-2633 marketing group 1111 comstock street santa clara, ca 95054 phone: (408) 566-8776 fax: (408) 566-8759 semtech corporation high-performance products division

an1002 - interfacing between ecl / lvecl / pecl / lvpecl - to - ttl / lvttl / cmos / lvcmos an1003 - termination techniques for ecl / lvecl / pecl / lvpecl devices an1004 - interfacing between lvds and ecl / lvecl / pecl / lvpecl an1005 - using ecl / lvecl devices as pecl / lvpecl an1006 - designing with 10k and 100k ecl / pecl devices

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