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ltc4101 1 4101fa typical application description smart battery charger controller the ltc ? 4101 smart battery charger is a single chip charging solution that dramatically simpli? es construction of an sbs compliant system. the ltc4101 implements a level 2 charger function whereby the charger can be programmed by the battery or by the host. a safetysignal on the battery being charged is monitored for temperature, connectivity and battery type information. the smbus interface remains alive when the ac power adapter is removed and responds to all smbus activity directed to it, including safetysignal status (via the chargerstatus command). the charger also provides an interrupt to the host whenever a status change is detected (e.g., battery removal, ac adapter connection). charging current and voltage are restricted to chemistry- speci? c limits for improved system safety and reliability. limits are programmable by two external resistors. ad- ditionally, the maximum average current from the ac adapter is programmable to avoid overloading the adapter when simultaneously supplying load current and charging current. when supplying system load current, charg- ing current is automatically reduced to prevent adapter overload. figure 1. 1a smart battery charger features applications n single chip smart battery charger controller n 100% compliant (rev. 1.1) smbus support allows for operation with or without host n up to 4a charging current capability n high ef? ciency synchronous buck charger n v bat optimized 3v to 5.5v n smbus accelerator improves smbus timing n hardware interrupt and smbalert response eliminate interrupt polling n 0.5v dropout voltage; maximum duty cycle > 98% n ac adapter current limit maximizes charge rate n 0.8% voltage accuracy; 4% current accuracy n 10-bit dac for charge current programming n 11-bit dac for charger voltage programming n user-selectable overvoltage and overcurrent limits n high noise immunity safetysignal sensor n available in a 24-pin ssop package n portable instruments and computers n data storage systems and battery backup servers 17 11 6 10 7 9 8 15 16 13 14 20 5 4 24 23 1 3 2 21 22 18 19 12 3v to 5.5v 0.12f 0.1f 0.068f 0.1f 0.03f 0.0015f 6.04k 10k 54.9k 100 0.05 5f 5f 0.1f 24h 0.1 1% smbclk 5k smbdat smbclk smbdat dcin 9v to 12v, 2a 4101 f01a chgen smbalert# acp smart battery system load 1.13k 1.21k 6.04k safetysignal v dd dcdiv chgen acp smbalert scl sda thb tha i lim v lim i dc dcin infet clp cln tgate bgate pgnd csp bat v set i th gnd ltc4101 v bat < 5.5v > 5.5v ltc4101 ltc4100 part l , lt, ltc, ltm, linear technology and the linear logo are registered trademarks of linear technology corporation. all other trademarks are the property of their respective owners. protected by u.s. patents including 6650174, 5723970.
ltc4101 2 4101fa package/order information absolute maximum ratings voltage from v dd to gnd ................................. 7v/C0.3v voltage from chgen, dcdiv, sda, scl and smbalert to gnd ............................ 7v/C0.3v voltage from dcin, clp , cln to gnd............. 32v/C0.3v voltage from clp to cln .......................................0.3v pgnd wrt. gnd ..................................................... 0.3v csp , bat to gnd ............................................... 28v/C5v operating ambient temperature range (note 4) .................................................................C40c to 85c junction temperature range ................ C40c to 125c storage temperature range ...................C65c to 150c lead temperature (soldering, 10 sec) .................. 300c (note 1) 1 2 3 4 5 6 7 8 9 10 11 12 top view g package 24-lead plastic ssop 24 23 22 21 20 19 18 17 16 15 14 13 clp cln bat csp i dc i th v set v dd tha thb v lim i lim tgate pgnd bgate infet dcin chgen smbalert sda scl acp dcdiv gnd t jmax = 125c, ja = 90c/w electrical characteristics symbol parameter conditions min typ max units dcin operating range l 628v i dcin dcin operating current charging, sum of currents on dcin, clp and cln 35ma v tol charge voltage accuracy (note 2) l C1.1 C1.3 1.1 1.3 % % i tol charge current accuracy (note 3) v csp C v bat target = 102.3mv i dac = 0xffff l C2 C3 6 7 % % v dd v dd operating voltage 0v v dcin 28v l 3 5.5 v shutdown battery leakage current dcin = 0v, v clp = v cln = v csp = v bat l 15 35 a uvlo undervoltage lockout threshold dcin rising, v bat = 0v l 4.2 4.7 5.5 v v dd power-fail part held in reset until this v dd present l 3v dcin current in shutdown v chgen = 0v 2 3 ma the l denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. v dcin = 20v, v dd = 3.3v, v bat = 4v unless otherwise noted. (note 4) order information lead free finish tape and reel part marking package description temperature range ltc4101eg#pbf ltc4101eg#trpbf ltc4101eg 24-lead plastic ssop C40c to 85c lead based finish tape and reel part marking package description temperature range ltc4101eg ltc4101eg#tr ltc4101eg 24-lead plastic ssop C40c to 85c consult ltc marketing for parts speci? ed with wider operating temperature ranges. for more information on lead free part marking, go to: http://www.linear.com/leadfree/ for more information on tape and reel speci? cations, go to: http://www.linear.com/tapeandreel/
ltc4101 3 4101fa electrical characteristics the l denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. v dcin = 20v, v dd = 3.3v, v bat = 4v unless otherwise noted. (note 4) symbol parameter conditions min typ max units current sense ampli? er, ca1 input bias current into bat pin 11.66 a cmsl ca1/i 1 input common mode low l 0v cmsh ca1/i 1 input common mode high v dcin 28v l v cln C0.2 v current comparators i rev i trev reverse current threshold (v csp -v bat ) C30 mv current sense ampli? er, ca2 transconductance 1 mmho source current measured at i th , v ith = 1.4v C40 a sink current measured at i th , v ith = 1.4v 40 a current limit ampli? er transconductance 1.5 mmho v clp current limit threshold l 93 100 107 mv i cln cln input bias current 50 na voltage error ampli? er, ea transconductance 1 mmho sink current measured at i th, v ith = 1.4v 36 a ovsd overvoltage shutdown threshold as a percent of programmed charger voltage l 102 107 110 % input p-channel fet driver (infet) dcin detection threshold (v dcin -v clp ) dcin voltage ramping up from v clp -0.05v l 0 0.17 0.25 v forward regulation voltage (v dcin -v clp ) l 25 50 mv reverse voltage turn-off voltage (v dcin -v clp ) l C60 C25 mv infet on clamping voltage (v dcin -v infet )i infet = 1a l 5 5.8 6.5 v infet off clamping voltage (v dcin -v infet )i infet = C25a 0.25 v oscillator f osc regulator switching frequency 255 300 345 khz f min regulator switching frequency in drop out duty cycle 98% 20 25 khz dc max regulator maximum duty cycle v csp = v bat 98 99 % gate drivers (tgate, bgate) v tgate high (v clp -v tgate )i tgate = C1ma 50 mv v bgate high c load = 3000pf 4.5 5.6 10 v v tgate low (v clp -v tgate )c load = 3000pf 4.5 5.6 10 v v bgate low i bgate = 1ma 50 mv tgtr tgtf tgate transition time tgate rise time tgate fall time c load = 3000pf, 10% to 90% c load = 3000pf, 10% to 90% 50 50 110 100 ns ns bgtr bgtf bgate transition time bgate rise time bgate fall time c load = 3000pf, 10% to 90% c load = 3000pf, 10% to 90% 40 40 90 80 ns ns v tgate at shutdown (v cln -v tgate )i tgate = C1a 100 mv
ltc4101 4 4101fa electrical characteristics the l denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. v dcin = 20v, v dd = 3.3v, v bat = 4v unless otherwise noted. (note 4) symbol parameter conditions min typ max units v bgate at shutdown i tgate = 1a 100 mv ac present comparator v acp dcdiv threshold v dcdiv rising from 1v to 1.4v l 1.14 1.20 1.26 v dcdiv hysteresis 25 mv dcdiv input bias current v dcdiv = 1.2v C1 1 a acp v oh i acp = C2ma 2 v acp v ol i acp = 1ma 0.5 v dcdiv to acp delay v dcdiv = 1.3v 10 s safetysignal decoder safetysignal trip (res_cold/res_or) r tha = 1130 1%, c th = 1nf (note 6) r thb = 54.9 1% l 95 100 105 k safetysignal trip (res_ideal/res_cold) r tha = 1130 1%, c th = 1nf (note 6) r thb = 54.9 1% l 28.5 30 31.5 k safetysignal trip (res_hot/res_ideal) r tha = 1130 1%, c th = 1nf (note 6) r thb = 54.9 1% l 2.85 3 3.15 k safetysignal trip (res_ur/res_hot) r tha = 1130 1%, c th = 1nf (note 6) r thb = 54.9 1% l 425 500 575 time between safetysignal measurements dcdiv = 1.3v dcdiv = 1v 32 250 ms ms dacs charging current resolution guaranteed monotonic above i max /16 10 bits charging current granularity r ilim = 0 r ilim = 10k 1% r ilim = 33k 1% r ilim = open (or short to v dd ) 1 2 4 4 ma ma ma ma wake-up charging current (i wake-up ) all values of r ilim all values of r vlim 80 (note 5) ma charging current limit csp C bat r ilim = 0 (0-1a) charging current = 0x03ff (0x0400 note 7) 97.3 107.3 mv r ilim = 10k 1% (0-2a) charging current = 0x07fe (0x0800 note 7) 97.3 107.3 mv r ilim = 33k 1% (0-3a) charging current = 0x0bfc (0x0c00 note 7) 72.3 82.3 mv r ilim = 0pen (or short to v dd ) (0-4a) charging current = 0x0ffc (0x1000 note 7) l 97.3 107.3 mv charging voltage resolution guaranteed monotonic (2.9v v bat 5.6v) 11 bits charging voltage granularity 16 mv charging voltage limit r vlim = 0 charging voltage = 0x1090 (note 7) 4.206 4.240 4.274 v r vlim = 10k 1% charging voltage = 0x10d0 (note 7) 4.270 4.304 4.338 v r vlim = 33k 1% charging voltage = 0x1150 (note 7) 4.397 4.432 4.467 v r vlim = 100k 1% charging voltage = 0x11a0 (note 7) 4.476 4.512 4.548 v r vlim = 0pen (or short to v dd ) charging voltage = 0x1580 (note 7) 5.460 5.504 5.548 v
ltc4101 5 4101fa electrical characteristics the l denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. v dcin = 20v, v dd = 3.3v, v bat = 4v unless otherwise noted. (note 4) symbol parameter conditions min typ max units logic levels v il scl/sda input low voltage v dd = 3v and v dd = 5.5v l 0.8 v v ih scl/sda input high voltage v dd = 3v and v dd = 5.5v l 2.1 v v ol sda output low voltage i pull-up = 350a l 0.4 v i il scl/sda input current v sda , v scl = v il C1 1 a i ih scl/sda input current v sda , v scl = v ih C1 1 a v ol smbalert output low voltage i pull-up = 500a l 0.4 v smbalert output pull-up current v smbalert = v ol C17.5 C10 C3.5 a i leak sda/scl/ smbalert power down leakage v sda , v scl , v smbalert = 5.5v, v dd = ov l C2 2 a v ol chgen output low voltage i ol = 100a l 0.5 v chgen output pull-up current v chgen = v ol C17.5 C10 C3.5 a v il chgen input low voltage l 0.9 v v ih chgen input high voltage v dd = 3v v dd = 5.5v l 2.5 3.9 v v power-on reset duration v dd ramp from 0v to >3v in <5s 100 s smbus timing (refer to system management bus speci? cation, revision 1.1, section 2.1 for timing diagrams) t high scl serial clock high period i pull-up = 350a, c load = 250pf, r pu = 9.31k, v dd = 3v and v dd = 5.5v l 4s t low scl serial clock low period i pull-up = 350a, c load = 250pf, r pu = 9.31k, v dd = 3v and v dd = 5.5v l 4.7 15000 s t r sda/scl rise time c load = 250pf, r pu = 9.31k, v dd = 3v and v dd = 5.5v l 1000 ns t f sda/scl fall time c load = 250pf, r pu = 9.31k, v dd = 3v and v dd = 5.5v l 300 ns t su:sta start condition setup time v dd = 3v and v dd = 5.5v l 4.7 s t hd:sta start condition hold time v dd = 3v and v dd = 5.5v l 4s t hd:dat sda to scl falling-edge hold time, slave clocking in data v dd = 3v and v dd = 5.5v l 300 ns t timeout time between receiving valid chargingcurrent() and chargingvoltage() commands v dd = 3v and v dd = 5.5v l 140 175 210 sec note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: see test circuit. note 3: does not include tolerance of current sense resistor. note 4: the ltc4101e is guaranteed to meet performance speci? cations from 0c to 85c. speci? cations over the C40c to 85c operating temperature range are assured by design, characterization and correlation with statistical process controls. note 5: current accuracy dependent upon circuit compensation and sense resistor. note 6: c th is de? ned as the sum of capacitance on tha, thb and safetysignal. note 7: the corresponding overrange bit will be set when a hex value greater than or equal to this value is used.
ltc4101 6 4101fa typical performance characteristics disconnect/reconnect battery (load dump) battery leakage current vs battery voltage ef? ciency at v prog = 4.208v smbus accelerator operation low current operation infet response time to reverse current output voltage vs output current pwm frequency vs duty cycle t a = 25c, unless otherwise noted. test performed on demoboard v in = 15v dc charger = on i charge = <10ma v s of pfet (5v/div) i d (reverse) of pfet (5a/div) v gs of pfet (2v/div) 4101 g01 v charge = 4.2v infet = 1/2 si4925dy v gs = 0 v s = 0v i d = 0a 1.25s/div output current (a) 0 0.5 1.0 2.0 3.0 4.0 1.5 2.5 3.5 4.5 output voltage error (%) 4101 g02 0 C0.5 C1.0 C1.5 C2.0 C2.5 C3.0 C3.5 C4.0 C4.5 C5.0 v dcin = 20v v prog = 4.176v i prog = 4v duty cycle (v out /v in ) 0 0.1 0.2 0.4 0.6 0.9 0.8 0.3 0.5 0.7 1.0 pwm frequency (khz) 4101 g03 programmed current = 10% dcin = 9v dcin = 12v dcin = 24v 350 300 250 200 150 100 50 0 4101 g04 load current = 1a, 2a, 3a dcin = 12v v float = 4.2v v float 1v/(div) load state disconnect reconnect 1a step 3a step 3a step 1a step battery voltage (v) 0 5 10 15 20 25 30 battery leakage current (a) 4101 g05 40 35 30 25 20 15 10 5 0 vdcin = 0v i out (a) 0.5 0.0 1.5 1.0 2.0 2.5 3.5 3.0 power efficiency (%) 4101 g06 v in = 20v v in = 8v 100 96 92 88 84 80 76 72 1s/div 4101 g07 5v 0v r pullup = 15k ltc4101 v dd = 5v c bus = 200pf i prog (a) 0 i charge (a) 0.6 0.4 0.5 0.3 0.2 0.1 0 0.05 4101 g08 0.10 0.40 0.15 0.20 0.25 0.30 0.35 v dd = 5v v bat = 4v v dcin = 20v v prog = 4.208v programmed current no low current mode low current mode
ltc4101 7 4101fa typical performance characteristics charging current error transfer function of charger t a = 25c, unless otherwise noted. pin functions tgate (pin 1): drives the top external p-mosfet of the battery charger buck converter. pgnd (pin 2): high current ground return for bgate driver. bgate (pin 3): drives the bottom external n-mosfet of the battery charger buck converter. infet (pin 4): drives the gate of the external input p-mosfet. dcin (pin 5): external dc power source input. bypass to ground with a 0.1f capacitor. chgen (pin 6): digital bidirectional pin to enable charger function. this pin is connected as a wired and bus. the following events will cause the power_fail bit in the chargerstatus register to become set: 1. an external device pulling the chgen signal to within 0.9v to gnd; 2. the ac adapter voltage is not above the battery voltage. smbalert (pin 7): active low interrupt output to host (referred to as the smbalert signal in the smbus revi- sion 1.1 speci? cation). signals host that there has been a change of status in the charger registers and that the host should read the ltc4101 status registers to determine if any action on its part is required. this signal can be connected to the optional smbalert line of the smbus. open drain with weak current source pull-up to v dd (with schottky to allow it to be pulled to 5v externally). sda (pin 8): smbus data signal from main (host-con- trolled) smbus. external pull-up resistor is required. scl (pin 9): smbus clock signal from main (host-con- trolled) smbus. external pull-up resistor is required. acp (pin 10): this output indicates the value of the dcdiv comparator. it can be used to indicate whether ac is present or not. dcdiv (pin 11): supply divider input. this is a high im- pedance comparator input with a 1.2v threshold (rising edge) and hysteresis. gnd (pin 12): ground for digital and analog circuitry. charging current (a) 0 output current error (ma) 200 100 0 C100 C200 1 4101 g09 2 4 3 v dcin = 20v v dd = 5v v dcin = 9v charging voltage (v) 0 output voltage error (v) 0 50 C50 C100 C150 4101 g10 45 3 12 6 v dd = 5v i bat = 0.120a v dcin = 9v v dcin = 20v v dcin = 28v
ltc4101 8 4101fa pin functions i lim (pin 13): an external resistor is connected between this pin and gnd. the value of the external resistor programs the range and resolution of the programmed charger current. this is a digital, not an analog, function. v lim (pin 14): an external resistor is connected between this pin and gnd. the value of the external resistor programs the range and resolution of the charging voltage. this is a digital, not an analog, function. thb (pin 15): safetysignal force/sense pin to smart battery. see description of operation for more detail. the maximum allowed combined capacitance on tha, thb and safetysignal is 1nf (see figure 4). a series resistor 54.9k needs to be connected between this pin and the batterys safetysignal for this circuit to work correctly. tha (pin 16): safetysignal force/sense pin to smart battery. see description of operation for more detail. the maximum allowed combined capacitance on tha, thb and safetysignal is 1nf (see figure 4). a series resistor 1130 needs to be connected between this pin and the batterys safetysignal for this circuit to work correctly. v dd (pin 17): power supply input for the ltc4101 digital circuitry. bypass this pin with 0.1f. typically between 3.3v and 5v dc . v set (pin 18): tap point of the programmable resistor divider, which provides battery voltage feedback to the charger. i th (pin 19): control signal of the inner loop of the current mode pwm. higher i th corresponds to higher charging current in normal operation. a 0.0015f capacitor to gnd ? lters out pwm ripple. typical full-scale output current is 40a. nominal voltage range for this pin is 0v to 3v. i dc (pin 20): bypass to gnd with a 0.068f capacitor. csp (pin 21): current ampli? er ca1 input. this pin and the bat pin measure the voltage across the sense resistor, r sense , to provide the instantaneous current signals required for both peak and average current mode operation. bat (pin 22): battery sense input and the negative refer- ence for the current sense resistor. a bypass capacitor of at least 10f is required. cln (pin 23): negative input to the input current limiting circuit block. if no current limit function is desired, connect this pin to clp. the threshold is set at 100mv below the voltage at the clp pin. when used to limit supply current, a ? lter is needed to ? lter out the switching noise. clp (pin 24): positive input to the input current limiting circuit block. this pin also serves as a power supply for the ic.
ltc4101 9 4101fa block diagram figure 2. c7 0.0015f r5, 6.04k + C + C + + 1.28v 1.19v watchdog detect t on oscillator dcin pwm logic s r q ca1 buffered i th gm = 1m + C + C 5 + C 17mv 100mv gm = 1m gm = 1.5m 1.19v 1.2v clp smbus interface and control thermister interface limit decoder i cmp i rev 0v v set bat csp i dc i lim v lim i th acp dcdiv to smbus power supply pgnd cln clp dcin infet chgen smbalert sda scl tha thb gnd clp tgate bgate system load ea cl1 5.8v 11-bit v dac 10-bit i dac 3k 11.67a 3k 9k C C 12 18 1 3 2 23 24 5 4 6 8 9 16 15 13 14 11 10 19 20 21 22 r4 100 c4 0.03f c5, 0.1f v bat v bat csp csp q2 q3 q1 r cl 20f d1 l1 v in v in 7 10a v dd r sense 20f c8 0.068f r vlim r ilim 17 v dd r1 c9 c1, 0.1f 1.13k to host and battery 54.9k 10k ca2 r10 r11 c6, 0.12f
ltc4101 10 4101fa overview (refer to block diagram) the ltc4101 is composed of a battery charger section, a charger controller, a 10-bit dac to control charger current, an 11-bit dac to control charger voltage, a safetysignal decoder, limit decoder and an smbus controller block. if no battery is present, the safetysignal decoder indicates a res_or condition and charging is disabled by the charger controller (chgen = low). charging will also be disabled if dcdiv is low, or the safetysignal is decoded as res_hot. if a battery is inserted and ac power is connected, the battery will be charged with an 80ma wake-up current. the wake-up current is discontinued after t timeout if the safetysignal is decoded as res_ur or res_c0ld, and the battery or host doesnt transmit charging commands. the smbus interface and control block receives charg- ingcurrent() and chargingvoltage() commands via the smbus. if chargingcurrent() and chargingvoltage() command pairs are received within a t timeout interval, the values are stored in the current and voltage dacs and the charger controller asserts the chgen line if the decoded safetysignal value will allow charging to commence. charg- ingcurrent() and chargingvoltage() values are compared against limits programmed by the limit decoder block; if the commands exceed the programmed limits these limits are substituted and overrange ? ags are set. the charger controller will assert smbalert whenever a status change is detected, namely: ac_present, bat- tery_present, alarm_inhibited, or v dd power-fail. the host may query the charger, via the smbus, to obtain chargerstatus() information. smbalert will be deasserted upon a successful read of chargerstatus() or a successful alert response address (ara) request. battery charger controller the ltc4101 charger controller uses a constant off-time, current mode step-down architecture. during normal operation, the top mosfet is turned on each cycle when the oscillator sets the sr latch and turned off when the main current comparator i cmp resets the sr latch. while the top mosfet is off, the bottom mosfet is turned on until either the inductor current trips the current comparator i rev , or the beginning of the next cycle. the oscillator uses the equation, t off = (v dcin ?v bat ) (v dcin ?f osc ) test circuit + C + C + C ea v dac 0.7v lt1055 csp bat bat v set i th ltc4101 1.19v 4101 tc01 21 22 18 19 v tol = v bat ?v vdac v vdac ? 100 for v vdac = 4.176v(0 x1050) dcin = 21v cln = clp = 20v v dd = 3.3v operation
ltc4101 11 4101fa operation to set the bottom mosfet on time. the result is quasi- constant frequency operation: the converter frequency remains nearly constant over a wide range of output voltages. this activity is diagrammed in figure 3. the peak inductor current, at which i cmp resets the sr latch, is controlled by the voltage on i th . i th is in turn controlled by several loops, depending upon the situation at hand. the average current control loop converts the voltage between csp and bat to a representative current. error amp ca2 compares this current against the desired current programmed by the i dac at the i dc pin and adjusts i th for the desired voltage across r sense . the voltage at bat is divided down by an internal resis- tor divider set by the v dac and is used by error amp ea to decrease i th if the divider voltage is above the 1.19v reference. the ampli? er cl1 monitors and limits the input current, normally from the ac adapter, to a preset level (100mv/r cl ). at input current limit, cl1 will decrease the i th voltage to reduce charging current. an overvoltage comparator, ov, guards against transient overshoots (>7%). in this case, the top mosfet is turned off until the overvoltage condition is cleared. this feature is useful for batteries that load dump themselves by opening their protection switch to perform functions such as calibration or pulse mode charging. pwm watchdog timer there is a watchdog timer that observes the activity on the tgate pin. if tgate stops switching for more than 40s, the watchdog activates and turns off the top mosfet for about 400ns. the watchdog engages to prevent very low frequency operation in dropout C a potential source of audible noise when using ceramic input and output capacitors. charger start-up when the charger is enabled, it will not begin switching until the i th voltage exceeds a threshold that assures initial current will be positive. this threshold is 5% to 15% of the maximum programmed current. after the charger begins switching, the various loops will control the current at a level that is higher or lower than the initial current. the duration of this transient condition depends upon the loop compensation, but is typically less than 1ms. smbus interface all communications over the smbus are interpreted by the smbus interface block. the smbus interface is a smbus slave device at address 0x12. all internal ltc4101 reg- isters may be updated and accessed through the smbus interface, and charger controller as required. the smbus protocol is a derivative of the i 2 c bus (reference i 2 c- bus and how to use it, v1.0 by philips, and system management bus speci? cation, version 1.1, from the sbs implementers forum, for a complete description of the bus protocol requirements.) all data is clocked into the shift register on the rising edge of scl. all data is clocked out of the shift register on the falling edge of scl. detection of an smbus stop condi- tion, or power-on reset via the v dd power-fail, will reset the smbus interface to an initial state at any time. the ltc4101 command set is interpreted by the smbus interface and passed onto the charger controller block as control signals or updates to internal registers. description of supported battery charger functions the functions are described as follows (see table 1 also): functionname() 'hnn (command code) description: a brief description of the function. purpose: the purpose of the function, and an example where appropriate. ? smbus protocol: refer to section 5 of the smart battery charger speci? cation for more details. figure 3. t off off off on on tgate bgate inductor current trip point set by i th voltage 4101 f01 *http://www.sbs-forum.org
ltc4101 12 4101fa operation input, output or input/output: a description of the data supplied to or returned by the function. chargerspecinfo() ('h11) description: the smbus host uses this command to read the ltc4101s extended status bits. purpose: allows the system host to determine the speci? cation revision the charger supports as well as other extended status information. ? smbus protocol: read word. output: the charger_spec indicates that the ltc4101 supports version 1.1 of the smart battery charger speci? cation. the selector_support indicates that the ltc4101 does not support the optional smart battery selector commands. chargermode() ('h12) description: the smbus host uses this command to set the various charger modes. the default values are set to allow a smart battery and the ltc4101 to work in concert without requiring an smbus host. purpose: allows the smbus host to con? gure the charger and change the default modes. this is a write only function, but the value of the mode bit, inhibit_charge may be determined using the chargerstatus() function. ? smbus protocol: write word. input: the inhibit_charge bit allows charging to be inhibited without changing the chargingcurrent() and chargingvoltage() values. the charging may be resumed by clearing this bit. this bit is automatically cleared when power is reapplied or when a battery is reinserted. the enable_polling bit is not supported by the ltc4101. values written to this bit are ignored. the por_reset bit sets the ltc4101 to its power-on default condition. the reset_to_zero bit sets the chargingcurrent()and chargingvoltage() values to zero. this function always clears the chargingvoltage() and chargingcurrent() values to zero even if the inhibit_charge bit is set. chargerstatus() ('h13) description: the smbus host uses this command to read the ltc4101s status bits. purpose: allows the smbus host to determine the status and level of the ltc4101. ? smbus protocol: read word. output: the charge_inhibited bit re? ects the status of the ltc4101 set by the inhibit_charge bit in the chargermode() function. the polling_enabled, voltage_notreg, and cur- rent_notreg are not supported by the ltc4101. the ltc4101 always reports itself as a level 2 smart battery charger. current_or bit is set only when chargingcurrent() is set to a value outside the current regulation range of the ltc4101. this bit may be used in conjunction with the inhibit_charge bit of the chargermode() and charg- ingcurrent() to determine the current capability of the ltc4101. when chargingcurrent() is set to i lim + 1, the current_or bit will be set. voltage_or bit is set only when chargingvoltage() is set to a value outside the voltage regulation range of the ltc4101. this bit may be used in conjunction with the inhibit_charge bit of the chargermode() and charg- ingvoltage() to determine the voltage capability of the ltc4101. when chargingvoltage() is set to the v lim , the voltage_or bit will be set. the res_or bit is set only when the safetysignal resis- tance value is greater than 95k. this indicates that the safetysignal is to be considered as an open circuit. the res_cold bit is set only when the safetysignal re- sistance value is greater than 28.5k. the safetysignal indicates a cold battery. the res_cold bit will be set whenever the res_or bit is set. the res_hot bit is set only when the safetysignal resis- tance is less than 3150, which indicates a hot battery. the res_hot bit will be set whenever the res_ur bit is set.
ltc4101 13 4101fa operation table 1: summary of supported charger functions chargerspecinfo() 7'b0001_001 8'h11 info 0x12 return read values chargermode() 7'b0001_001 8'h12 control permitted write values chargerstatus() 7'b0001_001 8'h13 status return read values chargingcurrent() 7'b0001_001 8'h14 value charging_current[15:0] permitted write values chargingvoltage() 7'b0001_001 8'h15 value charging_voltage[15:0] permitted write values alarmwarning() 7'b0001_001 8'h16 control permitted write values ltco() 7'b0001_001 8'h3c register permitted write values return read values alert response 7'b0001_100 n/a status ltc4101's address address 0x18 read byte access smbus address command code data type d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 do 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1/0 1/0 ign 1/0 1/0 1/0 1/0 1/0 1/0 1/0 1/0 1/0 1/0 1/0 0 1 0 0 0 1/0 1/0 1/0 1/0 1/0 0 1 0 1/0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 0 0 1 x function selector_support charger_spec reset_to_zero por_reset enable_polling inhibit_charge ac_present battery_present power_fail alarm_inhibited res_ur res_hot res_cold res_or voltage_or current_or current_notreg voltage_notreg polling_enabled charge_inhibited reserved reserved ignored ignored over_charged_alarm terminate_charge_alarm reserved_alarm over_temp_alarm terminate_discharge_alarm reserved remaining_capacity_alarm remaining_time_alarm initialized discharging fully_charged fully discharged error no_lowi unde?ned reserved ltc4101's version identi?cation ignored ignored unsigned integer representing current in ma level:3/level:2 not supported unsigned integer representing voltage in mv 1/0 return values
ltc4101 14 4101fa operation the res_ur bit is set only when the safetysignal resis- tance value is less than 575. alarm_inhibited bit is set if a valid alarmwarning() message has been received and charging is inhibited as a result. this bit is cleared if both chargingvoltage() and chargingcurrent() are rewritten to the ltc4101, power is removed (dcdiv < v acp ), or if a battery is removed. the setting of the alarm_inhibited will activate the ltc4101 smbalert pull-down. power_fail bit is set if the ltc4101 does not have suf- ? cient dcin voltage to charge the battery or if an external device is pulling the chgen input signal low. charging is disabled whenever this bit is set. the setting of this bit does not clear the values in the chargingvoltage() and chargingcurrent() function values, nor does it necessarily affect the charging modes of the ltc4101. battery_present is set if a battery is present other- wise it is cleared. the ltc4101 uses the safetysignal in order to determine battery presence. if the ltc4101 detects a res_or condition, the battery_present bit is cleared immediately. the ltc4101 will not set the battery_present bit until it successfully samples the safetysignal twice and does not detect a res_or condi- tion on either sampling. if ac is not present (e.g. dcdiv < v acp ), this bit may not be set for up to one-half second after the battery is connected to the safetysignal. the chargingcurrent() and chargingvoltage() function val- ues are immediately cleared whenever this bit is cleared. charging will never be allowed if this bit is cleared. a change in battery_present will activate the ltc4101 smbalert pull-down. ac_present is set if the voltage on dcdiv is greater than v acp . this does not necessarily indicate that the voltage on dcin is suf? cient to charge the battery. a change in ac_present will activate the ltc4101 smbalert pull- down. chargingcurrent() ('h14) description: the battery, system host or other master de- vice sends the desired charging current (ma) to the ltc4101. purpose: the ltc4101 uses r ilim , the granularity of the i dac , and the value of the chargingcurrent() function to determine its charging current supplied to the battery. the charging current will never exceed the maximum current permitted by r ilim . the chargingcurrent() value will be truncated to the granularity of the i dac . the charging cur- rent will also be reduced if the battery voltage exceeds the programmed charging voltage. ? smbus protocol: write word. input: the charging_current is an unsigned 16 bit integer specifying the requested charging current in ma. the following table de? nes the maximum permissible value of charging_current that will not set the cur- rent_or in the chargerstatus() function for a given value of the r ilim : r ilim chargingcurrent() current short to gnd 0x0000 through 0x03ff 0ma through 1023ma 10k 1% 0x0000 through 0x07ff 0ma through 2047ma 33k 1% 0x0000 through 0x0bff 0ma through 3071ma open (or short to v dd ) 0x0000 through 0x0fff 0ma through 4095ma chargingvoltage() ('h15) description: the battery, smbus host or other master device sends the desired charging voltage (mv) to the ltc4101. purpose: the ltc4101 uses r vlim , the granularity of the v dac , and the value of the chargingvoltage() function to determine its charging voltage supplied to the battery. the charging voltage will never be forced beyond the voltage permitted by r vlim . the chargingvoltage() value will be truncated to the granularity of the v dac . the charging voltage will also be reduced if the battery current exceeds the programmed charging current. ? smbus protocol: write word. input: the charging_voltage is an unsigned 16-bit integer specifying the requested charging voltage in mv. the ltc4101 considers any value from 0x0001 through 0x044f the same as writing 0x0000. the following
ltc4101 15 4101fa operation table de? nes the maximum permissible value of charg- ing_voltage that will not set the voltage_or in the chargerstatus() function for a given value of r vlim : r ilim maximum chargingvoltage() short to gnd 0x1090 (4240mv) 10k 1% 0x10d0 (4304mv) 33k 1% 0x1150 (4432mv) 100k 1% 0x11a0 (4512mv) open (or short to v dd ) 0x1580 (5504mv) alarmwarning() ('h16) description: the smart battery, acting as a bus master device, sends the alarmwarning() message to the ltc4101 to notify it that one or more alarm conditions exist. alarm indications are encoded as bit ? elds in the batterys status register, which is then sent to the ltc4101 by this func- tion. purpose: the ltc4101 will use the information sent by this function to properly charge the battery. the ltc4101 will only respond to certain alarm bits. writing to this function does not necessarily cause an alarm condition that inhibits battery charging. ? smbus protocol: write word. input: only the over_charged_alarm, terminate _charge_alarm, reserved (0x2000), and over _temp_alarm bits are supported by the ltc4101. writing a one to any of these speci? ed bits will inhibit the charging by the ltc4101 and will set the alarm_ inhibited bit in the chargerstatus() function. the terminate_discharge_alarm, remaining_ capacity_alarm, remaining_time_alarm, and the error bits are ignored by the ltc4101. ltc0() ('h3c) description: the smbus host uses this command to determine the version number of the ltc4101 and set extended operation modes not de? ned by the smart bat- tery charger speci? cation. purpose: this function allows the smbus host to deter- mine if the battery charger is an ltc4101. identifying the manufacturer and version of the smart battery charger permits software to perform tasks speci? c to a given charger. the ltc4101 also provides a means of disabling the lowi current mode of the i dac . ? smbus protocol: write word. input: the no_lowi is the only bit recognized by this function. the default value of no_lowi is zero. the ltc4101 lowi current mode provides a more accurate average charge current when the charge current is less than 1/16 of the full-scale i dac value. when the no_lowi is set, a less accurate i dac algorithm is used to generate the charging current, but because the charger is not pulsed on and off, it may be preferred. ? smbus protocol: read word. output: the no_lowi indicates the i dac mode of opera- tion. if clear, then the lowi current mode will be used when the charging current is less than 1/16 of the full- scale i dac value. the ltc version identi? cation will always be 0x4040 for the ltc4101. alert response address (ara) description: the smbus system host uses the alert response address to quickly identify the generator of an smbalert# event. purpose: the ltc4101 will respond to an ara address 0x18 if the smbalert signal is actively pulling down the smbalert# bus. the ltc4101 will follow the prioritiza- tion reporting as de? ned in the system management bus speci? cation, version 1.1, from the sbs implementers forum. ? smbus protocol: a 7-bit addressable device re- sponds to an ara. output: the device address will be sent to the smbus system host. the ltc4101 device address is 0x12. the following events will cause the ltc4101 to pull-down the smbalert# bus through the smbalert pin: ? change of ac_present in the chargerstatus() func- tion. ? change of battery_present in the chargerstatus() function. ? setting alarm_inhibited in the chargerstatus() function. ? internal power-on reset condition.
ltc4101 16 4101fa operation smbus accelerator pull-ups both scl and sda have smbus accelerator circuits which reduce the rise time on systems with signi? cant capacitance on the two smbus signals. the dynamic pull-up circuitry detects a rising edge on sda or scl and applies 1ma to 10ma pull-up to v dd when v in > 0.8v until v in < v dd C 0.8v (external pull-up resistors are still required to supply dc current). this action allows the bus to meet smbus rise time requirements with as much as 250pf on each smbus signal. the improved rise time will bene? t all of the devices which use the smbus, especially those devices that use the i 2 c logic levels. note that the dynamic pull-up circuits only pull to v dd , so some smbus devices that are not compliant to the smbus speci? cations may still have rise time compliance problems if the smbus pull-up resistors are terminated with voltages higher than v dd . the control block the ltc4101 charger operations are handled by the con- trol block. this block is capable of charging the selected battery autonomously or under smbus host control. the control block can request communications with the system management host (smbus host) by asserting smbalert = 0; this will cause the smbus host, if present, to poll the ltc4101. the control block receives smbus slave commands from the smbus interface block. the control block allows the ltc4101 to meet the fol- lowing smart battery-controlled (level 2) charger requirements: 1. implements the smart batterys critical warning mes- sages over the smbus. 2. operates as an smbus slave device that responds to chargingvoltage() and chargingcurrent() commands and adjusts the charger output parameters accordingly. 3. the host may control charging by disabling the smart batterys ability to transmit chargingcurrent() and chargingvoltage() request functions and broadcast- ing the charging commands to the ltc4101 over the smbus. 4. the ltc4101 will still respond to smart battery critical warning messages without host intervention. wake-up charging mode the following conditions must be met in order to allow wake-up charging of the battery: 1. the safetysignal must be res_cold, res_ideal, or res_ur. 2. ac must be present. this is quali? ed by dcdiv > v acp . wake-up charging initiates when a newly inserted battery does not send chargingcurrent() and chargingvoltage() functions to the ltc4101. the following conditions will terminate the wake-up charging mode. 1. a t timeout period is reached when the safetysignal is res_cold or res_ur. 2. the safetysignal is registering res_or. 3. the successful writing of the chargingcurrent() and chargingvoltage() function. the ltc4101 will proceed to the controlled charging mode after these two func- tions are written. 4. the safetysignal is registering res_hot. 5. the ac power is no longer present. (dcdiv < v acp ) 6. the alarm_inhibited becomes set in the charger- status() function. 7. the inhibit_charge is set in the chargermode() function. 8. the chgen pin is pulled low by an external device. the ltc4101 will resume wake-up charging, if the chgen pin is released by the external device. toggling the chgen pin will not reset the t timeout timer. 9. there is insuf? cient dcin voltage to charge the battery. the ltc4101 will resume wake-up charging when there is suf? cient dcin voltage to charge the battery. this condition will not reset the t timeout timer.
ltc4101 17 4101fa operation controlled charging algorithm overview the following conditions must be met in order to allow controlled charging to start on the ltc4101: 1. the chargingvoltage() and chargingcurrent() function must be written to non-zero values. 2. the safetysignal must be res_cold, res_ideal, or res_ur. 3. ac must be present. this is quali? ed by dcdiv > v acp . the following conditions will stop the controlled charging algorithm and will cause the battery charger controller to stop charging: 1. the chargingcurrent() and chargingvoltage() func- tions have not been written for t timeout . 2. the safetysignal is registering res_or. 3. the safetysignal is registering res_hot. 4. the ac power is no longer present. (dcdiv < v acp ) 5. alarm_inhibited is set in the chargerstatus() function. 6. inhibit_charge is set in the chargermode() function. clearing inhibit_charge will cause the ltc4101 to resume charging using the previous chargingvoltage() and chargingcurrent() function values. 7. reset_to_zero is set in the chargermode() function. 8. chgen pin is pulled low by an external device. the ltc4101 will resume charging using the previous chargingvoltage() and chargingcurrent() function values, if the chgen pin is released by the external device. 9. insuf? cient dcin voltage to charge the battery. the ltc4101 will resume charging using the previous chargingvoltage() and chargingcurrent() function values, when there is suf? cient dcin voltage to charge the battery. 10. writing a zero value to chargingvoltage() function. 11. writing a zero value to chargingcurrent() function. the safetysignal decoder block this block measures the resistance of the safetysignal and features high noise immunity at critical trip points. the low power standby mode supports only battery presence smb charger reporting requirements when ac is not present. the safetysignal decoder is shown in figure 4. the value of r tha is 1.13k and r thb is 54.9k. safetysignal sensing is accomplished by a state machine that recon? gures the switches of figure 4 using tha_selb and thb_selb, a selectable reference generator, and two comparators. this circuit has two modes of operation based upon whether ac is present. figure 4. safetysignal decoder block r tha 1.13k r safetysignal r thb 54.9k v dd v dd 4101 f04 tha_selb thb_selb + C + C res_or res_cold res_h0t res_ur latch safetysignal control mux ref hi_ref lo_ref th_hi th_lo tha thb c ss 16 15
ltc4101 18 4101fa operation when ac is present, the ltc4101 samples the value of the safetysignal and updates the chargerstatus register approximately every 32ms. the state machine successively samples the safetysignal value starting with the res_or res_cold threshold, then res_c0ld res_ideal threshold, res_ideal res_hot threshold, and ? nally the res_hot res_ur threshold. once the safetysig- nal range is determined, the lower value thresholds are not sampled. the safetysignal decoder block uses the previously determined safetysignal value to provide the appropriate adjustment in threshold to add hysteresis. the r thb resistor value is used to measure the res_or res_cold and res_cold res_ideal thresholds by connecting the thb pin to v dd and measuring the voltage resultant on the tha pin. the r tha resistor value is used to measure the res_ideal res_hot and res_hot res_ur thresholds by connecting the tha pin to v dd and measuring the voltage resultant on the thb pin. the safetysignal decoder block uses a voltage divider network between v dd and gnd to determine safetysig- nal range thresholds. since the tha and thb inputs are sequentially connected to v dd , this provides v dd noise immunity during safetysignal measurement. when ac power is not available the safetysignal block supports the following low power operating features: 1. the safetysignal is sampled every 250ms or less, instead of 32ms. 2. a full safetysignal status is sampled every 30s or less, instead of every 32ms. the safetysignal impedance is interpreted according to table 4. table 4. safetysignal state ranges safetysignal resistance charge status bits description 0 to 500 res_ur, res_hot battery_present underrange 500 to 3k res_hot battery_present hot 3k to 30k battery_present ideal 30k to 100k res_cold battery_present cold above 100k res_or res_cold overrange note: the underrange detection scheme is a very important feature of the ltc4101. the r tha /r safetysignal divider trip point of 0.333 ? v dd (1v) is well above the 0.047 ? v dd (140mv) threshold of a system using a 10k pull-up. a system using a 10k pull-up would not be able to resolve the important underrange to hot transition point with a modest 100mv of ground offset between battery and safetysignal detection circuitry. such offsets are anticipated when charging at normal current levels. the required values for r tha and r thb are shown in table 5. table 5. safetysignal external resistor values external resistor value ( ) r tha 1130 1% r thb 54.9k 1% c ss represents the capacitance between the safetysignal and gnd. c ss may be added to provide additional noise immunity from transients in the application. c ss cannot exceed 1nf if the ltc4101 is to properly sense the value of r safetysignal .
ltc4101 19 4101fa operation the i lim decoder block the value of an external resistor connected from this pin to gnd determines one of four current limits that are used for maximum charging current value. these limits provide a measure of safety with a hardware restriction on charging current which cannot be overridden by software. table 6. i lim trip points and ranges external resistor (r ilim )i lim voltage controlled charging current range granularity short to gnd v ilim < 0.09v dd 0 < i < 1023ma 1ma 10k 1% 0.17v vdd < v ilim < 0.34v vdd 0 < i < 2046ma 2ma 33k 1% 0.42v vdd < v ilim < 0.59v 0 < i < 3068ma 4ma open (>250k, or short to v dd ) 0.66v vdd < v ilim 0 < i < 4092ma 4ma the v lim decoder block the value of an external resistor connected from this pin to gnd determines one of ? ve voltage limits that are ap- plied to the charger output value. these limits provide a measure of safety with a hardware restriction on charging voltage which cannot be overridden by software. table 7. v lim trip points and ranges (see figure 5) external resistor (r ilim )i lim voltage controlled charging current range granularity short to gnd v vlim < 0.09v vccp 2900mv < v out < 4240mv 16mv 10k 1% 0.17v vdd < v vlim < 0.34v vdd 2900mv < v out < 4304mv 16mv 33k 1% 0.42v vccp < v vlim < 0.59v vdd 2900mv < v out < 4432mv 16mv 100k 1% 0.66v vdd < v vlim < 0.84v vdd 2900mv < v out < 4512mv 16mv open or tied to v dd 0.91v vdd < v vlim 2900mv < v out < 5504mv 16mv figure 5. simpli? ed v lim circuit concept (i lim is similar) v lim 12.5k 25k 33k 25k 25k 12.5k r vlim v dd v lim [3:0] 4101 f05 ac_present 4 + C + C + C + C encoder 14
ltc4101 20 4101fa operation the voltage dac block note that the charger output voltage is offset by v ref . therefore, the value of v ref is subtracted from the smbus chargingvoltage() value in order for the output voltage to be programmed properly (without offset). if the charging- voltage() value is below the nominal reference voltage of the charger, nominally 1.104v, the charger output voltage is programmed to zero. in addition, if the chargingvolt- age() value is above the limit set by the v lim pin, then the charger output voltage is set to the value determined by the v lim resistor and the voltage_or bit is set. these limits are demonstrated in figure 6. the current dac block the current dac is a delta-sigma modulator which controls the effective value of an external resistor, r set , used to set the current limit of the charger. figure 7 is a simpli? ed diagram of the dac operation. the delta-sigma modulator and switch convert the chargingcurrent() value, received via the smbus, to a variable resistance equal to: 1.25r set /[chargingcurrent()/i lim[x] ] = r idc therefore, programmed current is equal to: i charge = (102.3mv/r sense ) (chargingcurrent()/i lim[x] ), for chargingcurrent() < i lim[x] . figure 6. transfer function of charger programmed value (v) 0 charger v bat (v) 6 5 4 3 2 1 0 4101 f06 45 3 12 6 r vlim = 33k note: the ltc4101 can be programmed with chargingvoltage() function values between 1.104v and 2.9v, however, the battery charger controller output voltage may be zero with programmed values below 2.9v. when a value less than 1/16th of the maximum current allowed by i lim is applied to the current dac input, the current dac enters a different mode of operation called lowi. the current dac output is pulse width modulated with a high frequency clock having a duty cycle value of 1/8. therefore, the maximum output current provided by the charger is i max /8. the delta-sigma output gates this low duty cycle signal on and off. the delta-sigma shift registers are then clocked at a slower rate, about 45ms/bit, so that the charger has time to settle to the i max /8 value. the resulting average charging current is equal to that requested by the chargingcurrent() value. note: the lowi mode can be disabled by setting the no_lowi bit in the ltc0() function. when wake-up is asserted to the current dac block, the delta-sigma is then ? xed at a value equal to 80ma, inde- pendent of the i lim setting. input fet the input fet circuit performs two functions. it enables the charger if the input voltage is higher than the clp pin, and provides an indication of this condition at both the chgen pin and the pwr_fail bit in the chargerstatus() register. it also controls the gate of the input fet to keep a low forward voltage drop when charging and prevents reverse current ? ow through the input fet. if the input voltage is less than v clp , it must go at least 130mv higher than v clp to activate the charger. the chgen pin is forced low unless this condition is met. the gate of the input fet is driven to a voltage suf? cient to keep a low forward voltage drop from drain to source. if the voltage between dcin and clp drops to less than 25mv, the input fet is turned off slowly. if the voltage between figure 7. current dac operation i prog (from ca1 amp) 4101 f07 + C r set v ref i dc charging_current value i th - modulator 19 20
ltc4101 21 4101fa operation dcin and clp is ever less than C25mv, then the input fet is turned off quickly to prevent signi? cant reverse current from ? owing in the input fet. in this condition the chgen pin is driven low and the charger is disabled. the ac present block (ac_present) the dcdiv pin is used to determine ac presence. if the dcdiv voltage is above the dcdiv comparator threshold (v acp ), then the acp output pin will be switched to v dd and the ac_present bit in the chargerstatus() func- tion will be set. if the dcdiv voltage is below the dcdiv comparator threshold minus the dcdiv comparator hysteresis, then the acp output pin is switched to gnd and the ac_present bit in the chargerstatus() function is cleared. the acp output pin is designed to drive 2ma continuously. adapter limiting an important feature of the ltc4101 is the ability to auto- matically adjust charging current to a level which avoids overloading the wall adapter. this allows the product to operate at the same time that batteries are being charged without complex load management algorithms. addition- ally, batteries will automatically be charged at the maximum possible rate of which the adapter is capable. this feature is created by sensing total adapter output cur- rent and adjusting charging current downward if a preset adapter current limit is exceeded. true analog control is used, with closed loop feedback ensuring that adapter load current remains within limits. ampli? er cl1 in figure 9 senses the voltage across r cl , connected between the clp and cln pins. when this voltage exceeds 100mv, the ampli? er will override programmed charging current to limit adapter current to 100mv/r cl . a lowpass ? lter formed by 4.99k and 0.1f is required to eliminate switching noise. if the current limit is not used, clp should be connected to clp, but leave cln connected to power. setting input current limit to set the input current limit, you need to know the mini- mum wall adapter current rating. subtract 7% for the input current limit tolerance and use that current to determine the resistor value. r cl = 100mv/i lim i lim = adapter min current C (adapter min current ? 7%) as is often the case, the wall adapter will usually have at least a +10% current limit margin and many times one can simply set the adapter current limit value to the actual adapter rating (see figure 9). figure 8. charging current waveform in low current mode figure 9. adapter current limiting i limit /8 average charger current 4101 f08 ~40ms 0 100mv C + r1 4.99k clp cln infet 4101 f09 ltc4101 c9 0.1f + r cl * v in cl1 *r cl = 100mv adapter current limit to load 24 23 4
ltc4101 22 4101fa applications information charge termination issues batteries with constant current charging and voltage-based charger termination might experience problems with re- ductions of charger current caused by adapter limiting. it is recommended that input limiting feature be defeated in such cases. consult the battery manufacturer for informa- tion on how your battery terminates charging. setting output current limit (refer to figure 1) the ltc4101 current dac and the pwm analog circuitry must coordinate the setting of the charger current. failure to do so will result in incorrect charge currents. table 9. recommended resistor values i max (a) r sense ( ) 1% r sense (w) r ilim ( ) 1% 1.023 0.100 0.25 0 2.046 0.05 0.25 10k 3.068 0.025 0.5 33k 4.092 0.025 0.5 open warning do not change the value of r ilim during opera- tion. the value must remain ? xed and track the r sense value at all times. changing the current setting can result in currents that greatly exceed the requested value and potentially damage the battery or overload the wall adapter if no input current limiting is provided. inductor selection higher operating frequencies allow the use of smaller inductor and capacitor values. a higher frequency gener- ally results in lower ef? ciency because of mosfet gate charge losses. in addition, the effect of inductor value on ripple current and low current operation must also be considered. the inductor ripple current i l decreases with higher frequency and increases with higher v in . i l = 1 f () l () v out 1 ? v out v in ? ? ? ? ? ? i l allows the use of low inductances, but results in higher output voltage ripple and greater core losses. a reasonable starting point for setting ripple current is i l = 0.4(i max ). remember the maximum i l occurs at the maximum input voltage. the inductor value also has an effect on low current operation. the transition to low current operation begins when the inductor current reaches zero while the bottom mosfet is on. lower inductor values (higher i l ) will cause this to occur at higher load currents, which can cause a dip in ef? ciency in the upper range of low current operation. table 8. recommended resistor values adapter rating (a) C7% adapter rating (a) r cl value* ( )1% r cl limit (a) r cl power dissipation (w) r cl power rating(w) 1.5 1.40 0.068 1.47 0.15 0.25 1.8 1.67 0.062 1.61 0.16 0.25 2.0 1.86 0.051 1.96 0.20 0.25 2.3 2.14 0.047 2.13 0.21 0.25 2.5 2.33 0.043 2.33 0.23 0.50 2.7 2.51 0.039 2.56 0.26 0.50 3.0 2.79 0.036 2.79 0.28 0.50 3.3 3.07 0.033 3.07 0.31 0.50 3.6 3.35 0.030 3.35 0.33 0.50 4.0 3.72 0.027 3.72 0.37 0.50 * rounded to nearest 5% standard step value. many non standard values are popular.
ltc4101 23 4101fa applications information table 10. recommended inductor values inductance i max (a) 2 v in range (v) 1 3* and 4 7.5 16h 20% 8h 20% 4h 20% 9.0 20h 20% 10h 20% 5h 20% 12.0 24h 20% 12h 20% 6h 20% 15.0 26h 20% 13h 20% 6.5h 20% 28.0 30h 20% 15h 20% 7.5h 20% r sense 0.1 0.05 0.025 * 3 amp uses the same r sense that 4 amps uses. thus the inductance can be the same. choose and inductor whos inductance value is equal to or greater than the value shown. values assume: 1. C32% rss result from C20% inductance tolerance and a C25% inductance loss at i max . 2. inductor ripple current ratio of 0.51 of i out across r sense . 3. v out is at 4.2v charger switching power mosfet and diode selection two external power mosfets must be selected for use with the charger: a p-channel mosfet for the top (main) switch and an n-channel mosfet for the bottom (syn- chronous) switch. the peak-to-peak gate drive levels are set internally. this voltage is typically 6v. consequently, logic-level threshold mosfets must be used. pay close attention to the bv dss speci? cation for the mosfets as well; many of the logic level mosfets are limited to 30v or less. selection criteria for the power mosfets include the on resistance r ds(on) , total gate capacitance q g , reverse transfer capacitance c rss , input voltage and maximum output current. the charger is operating in continuous mode so the duty cycles for the top and bottom mosfets are given by: main switch duty cycle = v out /v in synchronous switch duty cycle = (v in C v out )/v in . the mosfet power dissipations at maximum output current are given by: pmain = v out /v in (i max ) 2 (1 + ? t)r ds(on) + k(v in ) 2 (i max )(c rss )(f osc ) psync = (v in C v out )/v in (i max ) 2 (1 + ? t)r ds(on) where t is the temperature dependency of r ds(on) and k is a constant inversely related to the gate drive current. both mosfets have i 2 r losses while the pmain equation includes an additional term for transition losses, which are highest at high input voltages. for v in < 20v the high current ef? ciency generally improves with larger mosfets, while for v in > 20v the transition losses rapidly increase to the point that the use of a higher r ds(on) device with lower c rss actually provides higher ef? ciency. the synchronous mosfet losses are greatest at high input voltage or during a short circuit when the duty cycle in this switch in nearly 100%. the term (1 + ? t) is generally given for a mosfet in the form of a normalized r ds(on) vs temperature curve, but = 0.005/c can be used as an approximation for low voltage mosfets. c rss = q gd / v ds is usually speci? ed in the mosfet characteristics. the constant k = 2 can be used to estimate the contributions of the two terms in the main switch dissipation equation. if the charger is to operate in low dropout mode or with a high duty cycle less than 50%, then the bottomside n-channel ef? ciency generally improves with a larger mosfet. using asymmetrical mosfets may achieve cost savings or ef? ciency gains. both of the ltc4101 mosfet drivers are optimized to take advantage of mosfets q g values of less than 22nc and a td-off delay speci? cation of around 60ns or less. larger fets may work, but you must qualify them and monitor ltc4101 temperature rise. using excessively large mosfets relative to the i max charge current they are working with will actually reduce ef? ciency at lighter current levels with very limited gain at high currents. a good place to start looking for a suit- able mosfet in a data sheet is to look for a part with an i d rating a little over 2 times the i max charge current rating. for the ltc4101, the p-channel fet can typically be scaled down a bit to take advantage of the lower duty cycle limits. however make sure you never exceed the p d rating of the device.
ltc4101 24 4101fa applications information the schottky diode d1, shown in the typical application on the back page, conducts during the dead-time between the conduction of the two power mosfets. this prevents the body diode of the bottom mosfet from turning on and storing charge during the dead-time, which could cost as much as 1% in ef? ciency. a 1a schottky is generally a good size for 4a regulators due to the relatively small average current. larger diodes can result in additional transition losses due to their larger junction capacitance. the diode may be omitted if the ef? ciency loss can be tolerated. calculating ic power dissipation the power dissipation of the ltc4101 is dependent upon the gate charge of the top and bottom mosfets (q2 & q3 respectively) the gate charge (qg) is determined from the manufacturers data sheet and is dependent upon both the gate voltage swing and the drain voltage swing of the mosfet. use 6v for the gate voltage swing and v dcin for the drain voltage swing. p d = v dcin ? (f osc (qg q2 + qg q3 ) + i dcin ) + v dd ? i dd example: v dcin = 12v, f osc = 345khz, qg q2 = 25nc, qg q3 = 15nc, i dcin = 5ma, v dd = 5.5v, i dd = 1ma. p d = 231mw calculating v dd current the ltc4101 v dd current, or i dd , consist of three parts: a. i run = current due to active clocking and bias inside the ic. b. i thrm = current due to thermistor circuit activity. c. i accel = current due to smbus acceleration activity. i dd = i run + i thrm + i accel a) i run current is basically independent of scl clock rate. once the ltc4101 determines that there is activity on the smbus, it turns on its internal hf oscillator. this hf oscillator remains on until a stop event occurs or sda and scl are at logic level 1 for the smbus timeout period. then it shuts off the hf oscillator. thus, the length of the transmission and the rate of transmission bursts are more important in determining how much current the ltc4101 burns, rather than the scl rate. in the equation below, i q is the static current the ic consumes as a function of the v dd voltage when not active. since it is hard to quantify the actual messages going down the smbus, one must estimate the smbus activity level in term of bus utilization per second. i run = message duty cycle ? 950a + (1 C message duty cycle) ? i q where i q(typ) = v dd /47.2k b) i thrm current is due to safetysignal (thermistor pin) sampling that will vary with the presence of dc power being on or off. dcdiv is detected every 32ms. rthx is the value of the safety signal resistance, which will vary with temperature or battery con? guration. b1) i thrm(on) when dc is on: i thrm(on)_overrange = 1/16 ? v dd /(54.9k + rthx) where rthx > 100k i thrm(on)_cold = 1/8 ? v dd /(54.9k + rthx) where rthx > 30k i thrm(on)_normal = 1/8 ? v dd /(54.9k + rthx) + 1/16 ? v dd /(1.13k + rthx) i thrm(on)_hot* = 1/8 ? v dd /(54.9k + rthx) + 1/8 ? v dd /(1.13k + rthx) rthx < 3k * includes underrange b2) i thrm(off) when dc is off, the thermistor monitoring rate is reduced to every 250ms or less. i thrm(off)_overrange = 1/50 ? v dd /(54.9k + rthx) where rthx > 100k i thrm(off)_cold = 1/50 ? v dd /(54.9k + rthx) + 1/1000 ? v dd /(54.9k + rthx) rthx > 30k i thrm(off)_normal = 1/50 ? v dd /(54.9k + rthx) + 1/500 ? v dd /(54.9k + rthx) + 1/1000 ? v dd /(1.13k + rthx) i thrm(off)_hot* = 1/50 ? v dd /(54.9k + rthx) + 1/500 ? v dd /(54.9k + rthx) + 1/500 ? v dd /(1.13k + rthx) where rthx < 3k * includes underrange
ltc4101 25 4101fa applications information c) i accel is the current used by the smbus accelerators. this directly depends on the smbus frequency, duty cycle of messages sent on the smbus and how long it takes to drive the smbus to v dd . i accel = i pull-up ? 2 ? smbus frequency ? message duty cycle ? v dd /2.25v ? rise time complete examples 1) battery thermistor = 400, v dd = 5.0v battery mode (dc is off), smbus activity is 10khz and a 2% smbus duty cycle, which represents a suspended or sleep condition of a notebook. i total = i run + i thrm(off) + i accel = 121.9a + 5.26a + 2.44a = 130a battery mode and a 10% smbus duty cycle, which represents an active notebook at idle. i total = i run + i thrm(off) + i accel = 189.5a + 5.26a + 12.2a = 207a dcin = on and a 20% smbus duty cycle which represents an active notebook charging. i total = i run + i thrm(on) + i accel = 274a + 215.6a + 24.4a = 514a 2) battery thermistor = 10k, v dd = 5.0v battery mode (dc is off), smbus activity is 10khz and a 2% smbus duty cycle: i total = i run + i thrm(off) + i accel = 121.9a + 2.14a + 2.44a = 126a battery mode and a 10% smbus duty cycle: i total = i run + i thrm(off) + i accel = 189.5a + 2.14a + 12.2a = 204a dcin = on and a 20% smbus duty cycle: i total = i run + i thrm(on) + i accel = 274a + 37.7a + 24.4a = 336a soft-start and undervoltage lockout the ltc4101 is soft-started by the 0.12f capacitor on the i th pin. on start-up, i th pin voltage will rise quickly to 0.5v, then ramp up at a rate set by the internal 30a pull-up current and the external capacitor. battery charging current starts ramping up when i th voltage reaches 0.8v and full current is achieved with i th at 2v. with a 0.12f capacitor, time to reach full charge current is about 2ms and it is assumed that input voltage to the charger will reach full value in less than 2ms. the capacitor can be increased up to 1f if longer input start-up times are needed. in any switching regulator, conventional timer-based soft-starting can be defeated if the input voltage rises much slower than the time out period. this happens because the switching regulators in the battery charger and the computer power supply are typically supplying a ? xed amount of power to the load. if input voltage comes up slowly compared to the soft-start time, the regulators will try to deliver full power to the load when the input voltage is still well below its ? nal value. if the adapter is current limited, it cannot deliver full power at reduced output voltages and the possibility exists for a quasi latch state where the adapter output stays in a current limited state at reduced output voltage. for instance, if maximum charger plus computer load power is 30w, a 15v adapter might be current limited at 2.5a. if adapter voltage is less than (30w/2.5a = 12v) when full power is drawn, the adapter voltage will be pulled down by the constant 30w load until it reaches a lower stable state where the switching regulators can no longer supply full load. this situation can be prevented by utilizing the dcdiv resistor divider, set higher than the minimum adapter voltage where full power can be achieved. input and output capacitors we recommend the use of high capacity low esr/esl x5r type ceramic capacitors. alternative capacitors include oscon or poscap type capacitors. aluminum electrolytic capacitors are not recommended for poor esr and esl reasons. solid tantalum low esr capacitors are acceptable, but caution must be used when tantalum capacitors are used for input or output bypass. high input surge currents can be created when the power adapter is hot-plugged into the charger or when a battery is connected to the charger. use only surge robust low esr tantalums. re- gardless of which type of capacitor you use, after voltage selection, the most important thing to meet is the ripple current requirements followed by the capacitance value. by the time you solve the ripple current requirements, the minimum capacitance value is often met by default.
ltc4101 26 4101fa applications information the following equation shows the minimum c out (20% tolerance) capacitance values for stability when used with the compensation shown in the typical application on the back page. c out(min) = 120/l1 the use of aluminum electrolytic for c1, located at the ac adapter input terminal, is helpful in reducing ringing during the hot-plug event. refer to application note 88 for more information. in the 4a lithium battery charger (typical application on back page), the input capacitor (c2) is assumed to absorb all input switching ripple current in the converter, so it must have adequate ripple current rating. worst-case rms ripple current will be equal to one half of output charging current. c2 is recommended to be equal to or greater than c4 (output capacitor) in capacitance value. the output capacitor (c4) is also assumed to absorb output switching current ripple. the general formula for capacitor current is: i rms = 0.29(v bat )1? v bat v dcin ? ? ? ? ? ? (l1)(f) for example, v dcin = 12v, v bat = 4.2v, l1 = 10h, and f = 300khz, i rms = 0.26a. emi considerations usually make it desirable to minimize ripple current in the battery leads, and beads or induc- tors may be added to increase battery impedance at the 300khz switching frequency. switching ripple current splits between the battery and the output capacitor depending on the esr of the output capacitor and the battery imped- ance. if the esr of c3 is 0.2 and the battery impedance is raised to 4 with a bead or inductor, only 5% of the current ripple will ? ow in the battery. protecting smbus inputs the smbus inputs, scl and sda, are exposed to uncon- trolled transient signals whenever a battery is connected to the system. if the battery contains a static charge, the smbus inputs are subjected to transients which can cause damage after repeated exposure. also, if the batterys posi- tive terminal makes contact to the connector before the negative terminal, the smbus inputs can be forced below ground with the full battery potential, causing a potential for latch-up in any of the devices connected to the smbus inputs. therefore it is good design practice to protect the smbus inputs as shown in figure 10. figure 10. recommended smbus transient protection connector to battery to system 4101 f13 v dd safetysignal (thermistor) value the safetysignal (typical application on back page), is a multifunction signal that communicates three pieces of information in order of importance: 1) presence of the smart battery 2) the maximum time duration of the wake-up charge allowed. 3) an optional and redundant temperature measurement system. the value of the resistance to ground communicates all this information. the resistance ranges and what it does is covered by the sbs smart battery charger standard in section 6. basically if you have a battery chemistry, such as li-ion, that cannot safely withstand an in? nite dura- tion wake-up charge, the safetysignal resistance value needs to be less than 425. the popular value to use is a ? xed 300 resistor. otherwise the resistance value is 10k which is normally expected to be done using a 10k ntc resistor. pcb layout considerations for maximum ef? ciency, the switch node rise and fall times should be minimized. to prevent magnetic and electrical ? eld radiation and high frequency resonant problems, proper layout of the components connected to the ic is
ltc4101 27 4101fa figure 11. high speed switching path 4101 f15 v bat l1 v in high frequency circulating path bat switch node c2 c4 d1 essential. (see figure 11.) here is a pcb layout priority list for proper layout. layout the pcb using this speci? c order. 1. input capacitors need to be placed as close as possible to switching fets supply and ground connections. shortest copper trace connections possible. these parts must be on the same layer of copper. vias must not be used to make this connection. 2. the control ic needs to be close to the switching fets gate terminals. keep the gate drive signals short for a clean fet drive. this includes ic supply pins that connect to the switching fet source pins. the ic can be placed on the opposite side of the pcb relative to above. 3. place inductor input as close as possible to switching fets output connection. minimize the surface area of this trace. make the trace width the minimum amount needed to support currentno copper ? lls or pours. avoid running the connection using multiple layers in parallel. minimize capacitance from this node to any other trace or plane. 4. place the output current sense resistor right next to the inductor output but oriented such that the ics current sense feedback traces going to resistor are not applications information long. the feedback traces need to be routed together as a single pair on the same layer at any given time with smallest trace spacing possible. locate any ? lter component on these traces next to the ic and not at the sense resistor location. 5. place output capacitors next to the sense resistor output and ground. 6. output capacitor ground connections need to feed into same copper that connects to the input capacitor ground before tying back into system ground. interfacing with a selector the ltc4101 is designed to be used with a true analog multiplexer for the safetysignal sensing path. some selector ics from various manufacturers may not imple- ment this. consult ltc applications department for more information. electronic loads the ltc4101 is designed to work with a real battery. electronic loads will create instability within the ltc4101 preventing accurate programming currents and volt- ages. consult ltc applications department for more information. figure 12. kelvin sensing of charging current vias to csp and bat 4101 f14 direction of charging current r sense
ltc4101 28 4101fa package description g package 24-lead plastic ssop (5.3mm) (reference ltc dwg # 05-08-1640) g24 ssop 0204 0.09 ? 0.25 (.0035 ? .010) 0 ? 8 0.55 ? 0.95 (.022 ? .037) 5.00 ? 5.60** (.197 ? .221) 7.40 ? 8.20 (.291 ? .323) 1234 5 6 7 8 9 10 11 12 7.90 ? 8.50* (.311 ? .335) 21 22 18 17 16 15 14 13 19 20 23 24 2.0 (.079) max 0.05 (.002) min 0.65 (.0256) bsc 0.22 ? 0.38 (.009 ? .015) typ millimeters (inches) dimensions do not include mold flash. mold flash shall not exceed .152mm (.006") per side dimensions do not include interlead flash. interlead flash shall not exceed .254mm (.010") per side * ** note: 1. controlling dimension: millimeters 2. dimensions are in 3. drawing not to scale 0.42 0.03 0.65 bsc 5.3 ? 5.7 7.8 ? 8.2 recommended solder pad layout 1.25 0.12
ltc4101 29 4101fa information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representa- tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. revision history rev date description page number a 11/09 text added to pin functions text changes to operation section changes to table 1 added calculating v dd current section updated input and output capacitors section added safetysignal (thermistor) value section changes to typical application 8 11, 12, 15 13 24 26 27 31
ltc4101 30 4101fa linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax: (408) 434-0507 www.linear.com ? linear technology corporation 2006 lt 1109 rev a ? printed in usa related parts typical application part number description comments ltc1760 smart battery system manager autonomous power management and battery charging for two smart batteries, smbus rev 1.1 compliant ltc4006 small, high ef? ciency, fixed voltage, lithium-ion battery charger constant current/constant voltage switching regulator with termination timer, ac adapter current limit and safetysignal sensor in a small 16-pin package ltc4007 high ef? ciency, programmable voltage battery charger with termination complete charger for 3- or 4-cell li-ion batteries, ac adapter current limit, safetysignal sensor and indicator outputs ltc4008 high ef? ciency, programmable voltage/current battery charger constant current/constant voltage switching regulator; resistor voltage/ current programming, ac adapter current limit and safetysignal sensor ltc4010 high ef? ciency standalone nickel battery charger complete nimh/nicd charger in a 16-pin tssop package, constant-current switching regulator ltc4011 high ef? ciency standalone nickel battery charger complete nimh/nicd charger in a 20-pin tssop package, powerpath? control. constant-current switching regulator ltc4060 standalone linear nimh/nicd fast charger complete nimh/nicd charger in a small leaded or leadless 16-pin package, no sense resistor or blocking diode required ltc4100 smart battery charger controller for smart batteries with voltages above 5.5v ltc4412 low loss powerpath controller very low loss replacement for power supply oring diodes using minimal external components powerpath is a trademark of linear technology corporation. ltc4101 li-ion battery charger i lim = 4a/v lim = 4.240v, adapter rating = 2.7a 5 11 20 12 17 14 13 10 6 7 8 9 1 3 21 18 16 15 c4 0.03f 25v c5 0.1f 10v 0.1f 10v c9 0.1f 10v r4 100 300 r thb 54.9k 1% r tha 1.13k 1% r sns 0.025 0.5w, 1% r cl 0.033 0.5w 1% c4,c5 10f s 2 10v x5r c2, c3 10f s 2 16v x5r system load sda scl q3 q1 q2 100k q4 1/2 si790iedn r11 1.21k 1% r5 6.04k 1% c6, 0.12f 10v, x7r c8, 0.068f 10v, x7r c7, 0.0015f 10v, x7r r10 6.04k 1% c1 0.1f dcin dcin 9v to 12v dcin from wall adapter r1 4.9k l1 6h 4a 424 23 d1 d1: mbrm140t3 d2-d5: small signal schottky q1: 1/2 si790iedn q2: fds6685 q3: si7804dn 4101 ta02 sda scl 10k 10k 3v to 5.5v safetysignal 1 cell li-ion battery d2 d3 d4 d5 22 19 dcin dcdiv i dc gnd v dd v lim i lim acp chgen smbalert sda scl infet tgate bgate csp v set tha thb cln clp ltc4101 bat i th pgnd

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