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1 ? fn6826.1 isl59920, ISL59921, isl59922, isl59923 triple analog vi deo delay lines the isl59920, ISL59921, isl59922, and isl59923 are triple analog delay lines that provide skew compensation between three high-speed signals. these parts are ideal for compensating for the skew introduced by a typical cat-5, cat-6 or cat-7 cable (with differing electrical lengths on each twisted pair) when transmitting analog video. using a simple serial interface, the isl59920, ISL59921, isl59922, and isl59923?s delays are programmable in steps of 2, 1.5, 1, or 2ns (respectively) for up to a total delay of 62, 46.5, 31, or 30ns (respectively) on each channel. the gain of the video amplifiers can be set to x1 (0db) or x2 (6db) for back-termination. the delay lines require a 5v supply. features ? 30, 31, 46.5, or 62ns total delay ? 1.0, 1.5, or 2.0ns delay step increments ? very low offset voltage ? drop-in compatible with the el9115 ? low power consumption ? 20 ld qfn package ? pb-free (rohs compliant) applications ? skew control for rgb video signals ? generating programmable high-speed analog delays pinout isl59920, ISL59921, isl59922, isl59923 (20 ld 5x5 qfn) top view ordering information part number (note) part marking max delay (ns) delay step size (ns) typical power dissipation (mw) package (pb-free) pkg. dwg. # isl59920irz* 59920 irz 62 2.0 645 20 ld 5mmx5mm qfn l20.5x5c ISL59921irz* 59921 irz 46.5 1.5 645 20 ld 5mmx5mm qfn l20.5x5c isl59922irz* 59922 irz 31 1.0 645 20 ld 5mmx5mm qfn l20.5x5c isl59923irz* 59923 irz 30 2.0 540 20 ld 5mmx5mm qfn l20.5x5c *add ?-t7? suffix for tape and reel. please refer to tb347 for details on reel specifications. note: these intersil pb-free plastic packa ged products employ special pb-free material sets, molding compounds/die attach materi als, and 100% matte tin plate plus anneal (e3 termination fi nish, which is rohs compliant and compatible with both snpb and pb-free soldering operations). intersil pb-free products are msl classified at pb-free peak reflow temperatures that meet or exceed the pb-free requirements o f ipc/jedec j std-020. 1 2 3 4 15 14 13 12 6 7 8 9 20 19 18 17 v sp r in gnd g in b in cenable senable sdata x2 testr testg testb r out gndo g out v smo thermal pad 5 v sm 10 sclock 11 b out 16 v spo data sheet may 28, 2009 caution: these devices are sensitive to electrosta tic discharge; follow proper ic handling procedures. 1-888-intersil or 1-888-468-3774 | intersil (and design) is a registered trademark of intersil americas inc. copyright intersil americas inc. 2009. all rights reserved all other trademarks mentioned are the property of their respective owners.
2 fn6826.1 may 28, 2009 absolute maxi mum ratings (t a = +25c) thermal information supply voltage (v s + to v s -) . . . . . . . . . . . . . . . . . . . . . . . . . . . .12v maximum output current. . . . . . . . . . . . . . . . . . . . . . . . . . . . 60ma storage temperature range . . . . . . . . . . . . . . . . . .-65c to +150c esd classification human body model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3000v machine model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .300v charged device model . . . . . . . . . . . . . . . . . . . . . . . . . . . .1200v thermal resistance (typical, note 1) ja (c/w) 20 lead qfn . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 pb-free reflow profile. . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/pb-freereflow.asp recommended operating conditions operating junction temperature . . . . . . . . . . . . . . . . . . . . . . +135c ambient operating temperature . . . . . . . . . . . . . . . .-40c to +85c caution: do not operate at or near the maximum ratings listed fo r extended periods of time. exposure to such conditions may adv ersely impact product reliability and result in failures not covered by warranty. note: 1. ja is measured with the component mounted on a high effective therma l conductivity test board in free air. see tech brief tb379 f or details. important note: all parameters having min/max specifications are guaranteed. typical values are for information purposes only. u nless otherwise noted, all tests are at the specified temperature and are pulsed tests, therefore: t j = t c = t a electrical specifications v sp = v spo = +5v, v sm = v smp = -5v, gain = 2, t a = +25c, exposed die plate = -5v, x2 = 5v, r load = 150 on all video outputs, unless otherwise specified. parameter description condition min typ max unit d t nominal delay increment (note 2) isl59920 1.8 2 2.2 ns ISL59921 1.4 1.5 1.7 ns isl59922 0.9 1 1.2 ns isl59923 1.8 2 2.3 ns t max maximum delay isl59920 55 62 68 ns ISL59921 42.5 46.5 53.5 ns isl59922 26.5 31 38.5 ns isl59923 26.5 30 34.5 ns d eldt delay difference between channels for same delay settings on all channels 1ns t pd propagation delay isl59920, isl59923, measured input to output, delay setting = 0ns 10 ns ISL59921, measured input to output, delay setting = 0ns 8ns isl59922, measured input to output, delay setting = 0ns 7ns bw -3db 3db bandwidth, 0ns delay time isl59920, isl59923 153 mhz ISL59921 200 mhz isl59922 230 mhz bw 0.1db 0.1db bandwidth, 0ns delay time isl59920, isl59923 50 mhz ISL59921 60 mhz isl59922 50 mhz sr slew rate isl59920, 20-80, delay = 0ns 550 v/s ISL59921, 20-80, delay = 0ns 640 v/s isl59922, 20-80, delay = 0ns 700 v/s isl59923; 20-80, delay = 0ns 550 v/s isl59920, ISL59921, isl59922, isl59923
3 fn6826.1 may 28, 2009 t r - t f transient response time isl59920, 20% to 80%, for any delay, 1v step delay = 0ns 1.7 ns ISL59921, 20% to 80%, for any delay, 1v step delay = 0ns 1.6 ns isl59922, 20% to 80%, for any delay, 1v step delay = 0ns 1.43 ns isl59923, 20% to 80%, for any delay, 1v step delay = 0ns 1.7 ns v over voltage overshoot for any delay, response to 1v step input 4 % glitch switching glitch output settling time from last sclk edge 100 ns thd total harmonic distortion 1v p-p 10mhz sinewave, offset by +0.2v at mid delay setting -43 -38 db x crosstalk stimulate g, measure r/b at 1mhz, isl59920, ISL59921, isl59923 -80 -63 db isl59922 -78 -59 db v n output noise bandwidth = 150mhz 2 mv rm s g_0 gain zero delay 1.74 1.8 1.92 v/v g_m gain mid delay 1.67 1.8 1.97 v/v g_f gain full delay 1.6 1.8 2 v/v dg_m0 difference in gain, 0 to mid -8 0.6 7.5 % dg_f0 difference in gain, 0 to full -12 -1.8 10 % dg_fm difference in gain, mid to full -10 -1.7 7.5 % v in input voltage range isl59920, gain remains > 90% of nominal, gain = 2 -0.7 1.1 v ISL59921, gain remains > 90% of nominal, gain = 2 -0.7 1.04 v isl59922, gain remains > 90% of nominal, gain = 2 -0.7 1.04 v isl59923, gain remains > 90% of nominal, gain = 2 -0.7 1.15 v i b r in , g in , b in input bias current isl59920, ISL59921 3 6 8 a isl59922, isl59923 1.5 8 a v os output offset voltage post offset calibration (note 4), delay = 0ns and delay = full -25 -4 +20 mv z out output impedance isl59920, ISL59921, enabled, chip enable = 5v 4.5 5.4 6.3 isl59922, isl59923, enabled, chip enable = 5v 3.5 6.3 disabled, chip enable = 0v 8 m +psrr rejection of positive supply -42 -29 db -psrr rejection of negative supply -58 -46 db i out output drive current 10 load, 0.5v drive 43 53 70 ma v ih logic high switch high threshold 1.6 v v il logic low switch low threshold 0.8 v electrical specifications v sp = v spo = +5v, v sm = v smp = -5v, gain = 2, t a = +25c, exposed die plate = -5v, x2 = 5v, r load = 150 on all video outputs, unless otherwise specified. (continued) parameter description condition min typ max unit isl59920, ISL59921, isl59922, isl59923
4 fn6826.1 may 28, 2009 power supply characteristics v+ v sp , v spo positive supply range +4.5 +5.5 v v- v sm , v smo negative supply range -4.5 -5.5 v i sp positive supply current (note 3) isl59920 98 115 127 ma ISL59921, isl59922 98 125 146 ma isl59923 74 90 106 ma i spo positive output supply current (note 3) isl59920 11.3 13 15.3 ma ISL59921, isl59922 11.3 13 16.3 ma isl59923 9.9 13 16 ma i sm negative supply current (note 3) -35.45 -31 -26 ma i smo negative output supply current (note 3) isl59920, ISL59921, isl59922 -15.5 -13 -11 ma isl59923 -17.5 -13 -9.5 ma i sp supply current (note 3) increase in i sp per unit step in delay per channel 0.9 ma i standby positive supply standby current (note 3) chip enable = 0v 2.6 ma serial interface characteristics t max max sclock frequency maximum programming clock speed 10 mhz t sen _setup senable to sclock falling edge setup time. see figure 34. senable falling edge should occur at least t sen _setup ns after previous (ignored) clock and t sen _setup before next (desired) clock. clock edges occurring within t_en_ck of the senable falling edge will have indeterminate effect. 10 ns t sen _cycle minimum separation between senable rising edge and next senable falling edge. se e figure 34. if senable is taken low less than 3s after it was taken high, there is a small possibility that an offset correction will not be initiated. 3s notes: 2. the limits for the ?nominal delay increment? are derived by ta king the limits for the ?maximum delay? and dividing by the num ber of steps for the device. for the isl59920, ISL59921, and isl59922 the number of st eps is 31; for the isl59923 the number of steps is 15. 3. all supply currents measured with delay r = 0ns, g = mid delay, b = full delay. 4. offset measurements are referred to 75 load as shown in figure 1. electrical specifications v sp = v spo = +5v, v sm = v smp = -5v, gain = 2, t a = +25c, exposed die plate = -5v, x2 = 5v, r load = 150 on all video outputs, unless otherwise specified. (continued) parameter description condition min typ max unit figure 1. v os measurement conditions x2 - 75 v os v in v out 75 isl59920, ISL59921, isl59922, isl59923
5 fn6826.1 may 28, 2009 pin descriptions pin number pin name pin description 1v sp +5v for delay circuitry and input amp 2r in red channel video input 3 gnd 0v for delay circuitry supply 4g in green channel video input 5v sm -5v for input amp 6b in blue channel video input 7 cenable chip enable input, active high: l ogical high enables chip, low disables chip 8 senable serial enable input, active low: l ogical low enables serial communication 9 sdata serial data input, logic threshold 1.2v: data to be programmed into chip 10 sclock serial clock input: clock to enter data; logical; data written on negative edge 11 b out blue channel video output 12 v smo -5v for video output buffers 13 g out green channel video output 14 gndo 0v reference for input and output buffers 15 r out red channel video output 16 v spo +5v for video output buffers 17 testb blue channel phase detector output 18 testg green channel phase detector output 19 testr red channel phase detector output 20 x2 gain select input: logical high = 2x (+6db), logical low = 1x (0db) thermal pad must be tied to -5v. for best thermal con ductivity also tie to a larger -5v copper plane (inner or bottom). use many vias to minimize t hermal resistance between thermal pad and copper plane. do not connect to gnd - connection to gnd is equivalent to shorting the -5v and gnd planes together. isl59920, ISL59921, isl59922, isl59923
6 fn6826.1 may 28, 2009 typical performance curves figure 2. isl59920 frequency response (gain = 1) figure 3. isl59920 frequency response (gain = 2) figure 4. ISL59921 frequency response (gain = 1) figure 5. ISL59921 frequency response (gain = 2) figure 6. isl59922 frequency response (gain = 1) figure 7. isl59922 frequency response (gain = 2) -10 -9 -8 -7 -6 -5 -4 -3 -2 -1 0 1 2 100k 1m 10m 100m 1g frequency (hz) normalized gain (db) v in = 700mv p-p gain = 1 10ns 50ns 20ns 40ns 62ns 30ns 0ns -10 -9 -8 -7 -6 -5 -4 -3 -2 -1 0 1 2 100k 1m 10m 100m 1g frequency (hz) normalized gain (db) v in = 700mv p-p gain = 2 10ns 50ns 20ns 40ns 62ns 30ns 0ns -10 -8 -6 -4 -2 0 2 100k 1m 10m 100m 1g frequency (hz) normalized magnitude (db) v in = 700mv p-p gain = 1 46.5ns 30ns 0ns 10.5ns 21ns -10 -8 -6 -4 -2 0 2 100k 1m 10m 100m 1g frequency (hz) normalized magnitude (db) 30ns 46.5ns 0ns 21ns 10.5ns v in = 700mv p-p gain = 2 -10 -8 -6 -4 -2 0 2 4 100k 1m 10m 100m 1g frequency (hz) normalized magnitude (db) 31ns 20ns 10ns 0ns v in = 700mv p-p gain = 1 -10 -8 -6 -4 -2 0 2 4 100k 1m 10m 100m 1g frequency (hz) normalized magnitude (db) 31ns 20ns 10ns 0ns v in = 700mv p-p gain = 2 isl59920, ISL59921, isl59922, isl59923
7 fn6826.1 may 28, 2009 figure 8. isl59923 frequency response (gain = 1) figure 9. isl59923 frequency response (gain = 2) figure 10. offset correction dac adjust figure 11. isl59920 noise spectrum (10k to 500mhz) figure 12. ISL59921 noise spectrum (10k to 500mhz) figure 13. isl59922 noise spectrum (10k to 500mhz) typical performance curves (continued) -10 -8 -6 -4 -2 0 2 100k 1m 10m 100m 1g frequency (hz) normalized magnitude (db) v in = 700mv p-p gain = 1 30ns 20ns 10ns 0ns -10 -8 -6 -4 -2 0 2 100k 1m 10m 100m 1g frequency (hz) normalized magnitude (db) v in = 700mv p-p gain = 2 30ns 20ns 10ns 0ns senable output timebase: 500ns/div senable: 1v/div output: 100mv/div gain: 1 0 50 100 150 200 250 0m 100m 200m 300m 400m 500m 600m frequency (hz) spectrum (nv/ isl59920, ISL59921, isl59922, isl59923
8 fn6826.1 may 28, 2009 figure 14. isl59923 noise spectrum (10k to 500mhz) fi gure 15. isl59920 rise/fall time vs delay time (gain = 2) figure 16. ISL59921 rise/fall time vs delay time (gain = 2) figure 17. isl59922 rise/fall time vs delay time (gain = 2) figure 18. isl59923 rise/fall time vs delay time (gain = 2) figure 19. harmonic distortion vs frequency typical performance curves (continued) 0 50 100 150 200 250 0m 100m 200m 300m 400m 500m 600m frequency (hz) s pe c trum ( nv / 0 0.5 1.0 1.5 2.0 2.5 3.0 12 16 20 24 28 32 36 40 44 48 52 56 60 delay (ns) rise/fall time 04 8 0 0.5 1.0 1.5 2.0 2.5 3.0 12 16 20 24 28 32 36 40 44 48 delay (ns) rise/fall time 04 8 fall rise 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 0 2 4 6 8 101214161820222426 283032 delay (ns) rise/fall time fall rise 0.5 1.0 1.5 2.0 2.5 0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 delay (ns) rise/fall time 0 fall rise -80 -70 -60 -50 -40 -30 -20 -10 0 2m 6m 10m 14m 18m 22m 26m 30m 34m 38m frequency (hz) harmonic distortion (dbc) 3 rd hd v+ = +5.0v, v- = -5.0v v out = 1.0v p-p , sine wave r l = 150 gain = 2 2 nd hd 2 nd hd isl59920, ISL59921, isl59922, isl59923
9 fn6826.1 may 28, 2009 figure 20. isl59920 positive supply current (v sp ) vs delay time figure 21. ISL59921 positive supply current (v sp ) vs delay time figure 22. isl59922 positive supply current (v sp ) vs delay time figure 23. isl59923 positive supply current (v sp ) vs delay time figure 24. isl59920 i supply + vs v supply + figure 25. isl59920 i supply - vs v supply - typical performance curves (continued) 60 80 100 120 140 160 180 positive supply current (ma) 3 channels 2 channels 1 channel gain = 2 0 4 8 121620242832 36404448525660 delay (ns) 60 80 100 120 140 160 180 200 220 0 12151821242730333639424548 delay (ns) positive supply current (ma) gain = 2 no input, no load 369 3 channels 2 channels 1 channel 60 80 100 120 140 160 180 200 220 10 12 14 16 18 20 22 24 26 28 30 32 delay (ns) positive supply current (ma) 8 6 4 2 0 gain = 2 no input, no load 2 channels 1 channel 3 channels 60 70 80 90 100 110 120 130 140 150 0 101214161820222426283032 delay (ns) positive supply current (ma) 2468 gain = 2 no input, no load 2 channels 1 channel 3 channels 60 80 100 120 140 160 180 200 4.0 4.2 4.4 4.6 4.8 5.0 5.2 5.4 5.6 5.8 6.0 supply voltage (v) supply current (ma) delay = 62ns delay = 0ns gain = 1 or 2 -46.5 -46.0 -45.5 -44.0 -44.5 -44.0 -43.5 -43.0 -42.5 -4.0 -4.2 -4.4 -4.6 -4.8 -5.0 -5.2 -5.4 -5.6 -5.8 -6.0 supply voltage (v) negative supply current (ma) delay = 62ns delay = 0ns gain = 1 or 2 isl59920, ISL59921, isl59922, isl59923
10 fn6826.1 may 28, 2009 figure 26. ISL59921 i supply + vs v supply + figure 27. ISL59921 i supply - vs v supply - figure 28. isl59922 i supply + vs v supply + figure 29. isl59922 i supply - vs v supply - figure 30. isl59923 i supply + vs v supply + figure 31. isl59923 i supply - vs v supply - typical performance curves (continued) 60 80 100 120 140 160 180 200 220 240 4.0 4.2 4.4 4.6 4.8 5.0 5.2 5.4 5.6 5.8 6.0 supply voltage (v) supply current (ma) delay = 46.5ns delay = 0ns gain = 1 or 2 delay applied to all channels no input, no load -51.0 -50.5 -50.0 -49.5 -49.0 -48.5 -48.0 -47.5 -47.0 -46.5 -46.0 4.0 4.2 4.4 4.6 4.8 5.0 5.2 5.4 5.6 5.8 6.0 supply voltage (v) negative supply current (ma) delay = 46.5ns delay = 0ns gain = 2 60 80 100 120 140 160 180 200 220 4.04.24.44.64.85.05.25.45.65.86.0 supply voltage (v) supply current (ma) delay = 31ns delay = 0ns gain = 1 or 2 delay applied to all channels no input, no load -50.5 -50.0 -49.5 -49.0 -48.5 -48.0 -47.5 -47.0 -46.5 -46.0 -45.5 -45.0 4.0 4.2 4.4 4.6 4.8 5.0 5.2 5.4 5.6 5.8 6.0 supply voltage (v) negative supply current (ma) delay = 31ns delay = 0ns gain = 2 60 70 80 90 100 110 120 130 140 150 4.0 4.2 4.4 4.6 4.8 5.0 5.2 5.4 5.6 5.8 6.0 supply voltage (v) supply current (ma) delay = 30ns delay = 0ns gain = 1 or 2 delay applied to all channels no input, no load 60 70 80 90 100 110 120 130 140 150 4.0 4.2 4.4 4.6 4.8 5.0 5.2 5.4 5.6 5.8 6.0 supply voltage (v) supply current (ma) delay = 30ns delay = 0ns gain = 1 or 2 delay applied to all channels no input, no load -49.5 -49.0 -48.5 -48.0 -47.5 -47.0 -46.5 -46.0 4.0 4.2 4.4 4.6 4.8 5.0 5.2 5.4 5.6 5.8 6.0 supply voltage (v) negative supply current (ma) delay = 30ns gain = 2 delay = 0ns isl59920, ISL59921, isl59922, isl59923
11 fn6826.1 may 28, 2009 applications information the isl59920, ISL59921, isl59922, and isl59923 are triple analog delay lines that provide skew compensation between three high-speed signals. these devices compensate for time skew introduced by a typical cat-5, cat-6 or cat-7 cable with differin g electrical lengths (due to different twist ratios) on each pair. via their spi interface, these devices can be programmed to independently compensate for the three different cable delays while maintaining 80mhz bandwidth at their maximum setting. there are four different variat ions of the isl5992x (isl5992x will be used when talking about characteristics that are common to all four devices). figure 32. package power dissipation vs ambient temperature typical performance curves (continued) jedec jesd51-7 high effective thermal conductivity test board - qfn exposed diepad soldered to pcb per jesd51-5 3.54w j a = 3 1 c / w q f n 2 0 4.5 4.0 3.5 3.0 2.0 1.0 0 0 255075100 150 ambient temperature (c) power dissipation (w) 125 85 2.5 1.5 0.5 figure 33. isl59920, ISL59921, isl59922, isl59923 block diagram + + + + + + delay line delay line delay line 18 testg testb testr 17 senable sclock sdata x2 19 3 10 8 9 r in g in b in control logic b out g out r out gnd gnd v smo v sm 51214 20 11 13 15 2 4 6 cenable 7 c [bottom plate] v spo 16 v sp 1 table 1. part number max delay (ns) nominal delay increment (ns) isl59920 62 2.0 ISL59921 46.5 1.5 isl59922 31 1.0 isl59923 30 2.0 isl59920, ISL59921, isl59922, isl59923
12 fn6826.1 may 28, 2009 figure 33 shows the isl5992x block diagram. the 3 analog inputs are ground referenced single-ended signals. after the signal is received, the delay is introduced by switching filter blocks into the signal path. each filter block is an all-pass filter introducing either 1, 1.5 or 2ns of delay. in addition to adding delay, each filter block also introduces some low pass filtering. as a result, the bandwidth of the signal path decreases from the 0ns delay setting to the maximum delay setting, as shown in figures 2 through 9 of the ?typical performance curves?. in operation, it is best to allocate the most delayed signal 0ns delay then increase the delay on the other channels to bring them into line. this will result in delay compensation with the lowest power and distortion. serial bus operation the isl5992x is programmed via 8-bit words sent through its serial interface. the first bit (msb) of sdata is latched on the first falling clock edge after senable goes low, as shown in figure 34. this bit should be a 0 under all conditions. the next two bits determine the color register to be written to: 01 = r, 02 = g, and 03 = b (00 is reserved for the test register). the final five bits set the delay for the specified color. after 8 bits are latched, any additional clocks are treated as a new word (data is shifted directly to the final registers as it is clocked in). th is allows the user to write (for example) the 24 bits of data necessary for r, g, and b as a single 24-bit word. it is the user's responsibility to send complete multiples of 8 cl ock cycles. the serial state machine is reset on the falling edge of senable , so any data corruption that may have occurred due to too many or too few clocks can be correcte d with a new word with the correct number of clocks. the in itial value of all registers on power-up is 0. senable sclock sdata a1 a0 d4 d3 d2 d1 d0* 0 a b v w x y z figure 34. serial timing *d0 is 0 when addressing the test register t sen _setup t sen _cycle table 2. serial bus data vwxyz isl59920 delay ISL59921 delay isl59922 delay isl59923 delay 00000 0 0 0 0 00001 2 1.5 1 2 00010 4 3 2 4 00011 6 4.5 3 6 00100 8 6 4 8 00101 10 7.5 5 10 00110 12 9 6 12 00111 14 10.5 7 14 01000 16 12 8 16 01001 18 13.5 9 18 01010 20 15 10 20 01011 22 16.5 11 22 01100 24 18 12 24 01101 26 19.5 13 26 01110 28 21 14 28 01111 30 22.5 15 30 10000 32 24 16 n/a 10001 34 25.5 17 n/a 10010 36 27 18 n/a 10011 38 28.5 19 n/a 10100 40 30 20 n/a 10101 42 31.5 21 n/a 10110 44 33 22 n/a 10111 46 34.5 23 n/a 11000 48 36 24 n/a 11001 50 37.5 25 n/a 11010 52 39 26 n/a 11011 54 40.5 27 n/a 11100 56 42 28 n/a 11101 58 43.5 29 n/a 11110 60 45 30 n/a 11111 62 46.5 31 n/a note: delay register word = 0abvwxyz; red register - ab = 01; green register - ab = 10; blue register - ab = 11; vwxyz selects delay; ab = 00 writes to the test register to change the dac slice level. table 2. serial bus data (continued) vwxyz isl59920 delay ISL59921 delay isl59922 delay isl59923 delay isl59920, ISL59921, isl59922, isl59923
13 fn6826.1 may 28, 2009 offset compensation to counter the effects of offse t, the isl5992x incorporates an offset compensation circuit that reduces the offset to less than 25mv. an offset correction cycl e is triggered by the rising edge of the senable pin after writing a delay word to any of the 3 channels. the offset calibration starts about 500ns after the senable rising edge to allow the isl5992x time to settle (electrically and thermally) to the new delay setting. it lasts about 2.5s, for a total offset correction time of 3.0s. during calibration, the isl5992x?s inputs are internally shorted together (however the characteristics of the isl5992x?s differential input pins stay the same), and the offset of the output stage is adjusted until it has been minimized. in addition to automatically triggering after a delay change (or any register write), an addi tional offset calibration may be initiated at any time, such as: ? when the die temperature changes. applying power to the isl5992x will cause the die temp erature to quickly increase then slowly settle over 20 to 30 seconds. because the isl5992x powers-down unused delay stages (to minimize power consumption), the die temp will also change and settle after a delay change. initiating an offset 20 seconds (or longer, depending on the thermal characteristics of the system) after power-on or a delay change will minimize the offset in normal operation thereafter. ? when the ambient temperature changes. if you are monitoring the temperature, init iate a calibration every time the temperature shifts by 5 to 10 degrees. if you are not monitoring temperature, initiate a calibration periodically, as expected by the environment the device is in. ? after a cenable (chip enable) cycle. the cenable pin may be taken low to put the isl5992x in a low power standby mode to conserve power when not needed. when the cenable pin goes high to exit this low power mode, the isl5992x will recall the delay settings but it will not recall the correct offset calibr ation settings, so to maintain low offset, a write to the delay register is required after a cenable cycle. offset errors may be as large as 200mv coming out of standby mode - recalibration is a necessity . for best performance, initiate an additional calibration again once the die temperature has settled (20 to 30 seconds after coming out of standby). ? after a gain change (x2 pin changes state). the systematic offset is different for a gain of x1 vs. a gain of x2, so an offset calibration is recommended after a gain change. however in a typical application the gain is permanently fixed at x1 or x2, so this is not usually a concern. test pins three test pins are provided (test r, test g, test b). during normal operation, the test pins output pulses of current for a duration of the overlap between the inputs, as shown in figure 35: test r pulse = red out (a) with respect to green out (b) test g pulse = green out with respect to blue out test b pulse = blue out with respect to red out averaging the current gives a direct measure of the delay between the two edges. when a precedes b, the current pulse is +50a, and the output voltage goes up. when b precedes a, the pulse is -50a. for the logic to work correctly, a and b must have a period of overlap while they are high (a delay longer than the pulse width cannot be measured). signals a and b are derived from the video input by comparing the video signal with a slicing level, which is set by an internal dac. this enables the delay to be measured either from the rising edges of sync-like signals encoded on top of the video or from a dedicated set-up signal. the outputs can be used to set the correct delays for the signals received. the dac level is set through the serial input by bits 1 through 4 directed to the test register (00). internal dac voltage the slice level of the internal dac may be programmed by writing a byte to the test re gister (00). table 3 shows the values that should be written to change the dac slice level. please keep in mind when writing to the test register that the lsb should always be zero. referred to the input, the dac slice range for the isl5992x is cut in half for gain of 2 mode because the slicing occurs after the x1/x2 stage output amplifier. (in the el9115, the slicing occurred before the amp lifier so the range of the dac voltage was the same for either gain of 1 or gain of 2). figure 35. delay detector a b output 4 slicing level comparators a b internal dac 000wxyz0 test r a b test g a b test b red out green out blue out isl59920, ISL59921, isl59922, isl59923
14 fn6826.1 may 28, 2009 power dissipation as the delay setting increases, additional filter blocks turn on and insert into the signal path. when the delay per channel increments, v sp current increases by 0.9ma while v sm does not change significantly. under the extreme settings, the positive supply current reaches 141ma and the negative supply current can be 41ma. o perating at 5v power supply, the worst-case isl5992x power dissipation is: the minimum ja required for long term reliable operation of the isl5992x is calculated using equation 2: where: t j is the maximum junction temperature (+135c) t a is the maximum ambient temperature (+85c) for a 20 ld package on a well laid-out pcb with good connectivity between the qfn?s pad and the pcb copper area, 31c/w ja thermal resistance can be achieved. this yields a much higher power dissipation of 3.54w using equation 2 (see figure 32). to disperse the heat, the bottom heat spreader must be soldered to the pcb. heat flows through the heat spreader to the circuit board copper then spreads and convects to air. thus, the pcb copper plane becomes the heatsink (see tb389). this has proven to be a very effective technique. a separate application note, which details the 20 ld qfn pcb design considerations, is available. table 3. dac voltage range - input referred wxyz dac range [mv] (gain 1) dac range [mv] (gain 2) 1000 -400 -200 1001 -350 -175 1010 -300 -150 1011 -250 -125 1100 -200 -100 1101 -150 -75 1110 -100 -50 1111 -50 -25 0000 0 0 0001 50 25 0010 100 50 0011 150 75 0100 200 100 0101 250 125 0110 300 150 0111 350 175 note: test register word = 000wxyz0. wxyz fed to dac. z is lsb pd 5 141ma 5 41ma ? 910mw = + ? = (eq. 1) ja t j ( t a ) pd 55 = ? cw ? ? = (eq. 2) isl59920, ISL59921, isl59922, isl59923
15 all intersil u.s. products are manufactured, asse mbled and tested utilizing iso9000 quality systems. intersil corporation?s quality certifications ca n be viewed at www.intersil.com/design/quality intersil products are sold by description only. intersil corpor ation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnishe d by intersil is believed to be accurate and reliable. however, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringements of paten ts or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiari es. for information regarding intersil corporation and its products, see www.intersil.com fn6826.1 may 28, 2009 isl59920, ISL59921, isl59922, isl59923 quad flat no-lead plastic package (qfn) a b e 1 2 3 n (n-1) (n-2) pin #1 i.d. mark (n/2) 0.075 (2x) c 0.075 (2x) c top view side view c seating plane 0.08 c n leads and exposed pad see detail ?x? e 0.10 c l b n (n-1) (n-2) 1 2 3 pin #1 i.d. 0.01 b a m c 3 ne 5 7 (n/2) (d2) (e2) c (c) a1 a 2 bottom view detail ?x? (l) n leads n leads d l20.5x5c 20 lead quad flat no-lead plastic package (compliant to jedec mo-220) symbol millimeters notes min nominal max a 0.80 0.90 1.00 - a1 0.00 0.02 0.05 - b 0.28 0.30 0.32 - c0.20 ref- d 5.00 basic - d2 3.70 ref 8 e 5.00 basic - e2 3.70 ref 8 e 0.65 basic - l 0.35 0.40 0.45 - n204 nd 5 ref 6 ne 5 ref 5 rev. 0 6/06 notes: 1. dimensioning and tolerancing per asme y14.5m-1994. 2. tiebar view shown is a non-functional feature. 3. bottom-side pin #1 i.d. is a diepad chamfer as shown. 4. n is the total number of terminals on the device. 5. ne is the number of terminals on the ?e? side of the package (or y-direction). 6. nd is the number of terminals on the ?d? side of the package (or x-direction). nd = (n/2)-ne. 7. inward end of terminal may be s quare or circular in shape with radius (b/2) as shown. 8. if two values are listed, multiple exposed pad options are available. refer to dev ice-specific datasheet. 9. one of 10 packages in mdp0046

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