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w83195br - 25 200mhz 3 - dimm clock for solano chipset publication release date: may 2000 - 1 - revision 0.52 1.0 general descrip tion the w83195br - 25 is a clock synthesizer for intel 815 solano chipset. w83195br - 25 provides all clocks required for high - speed risc or cisc microprocessor and also provides 64 different frequencies of cpu, sdram, pci, 3v66, ioapic c locks frequency setting. all clocks are externally selectable with smooth transitions. the w83195br - 25 provides i 2 c serial bus interface to program the registers to enable or disable each clock outputs and provides 0.25% and 0.5% center type spread spectrum to reduce emi. the w83195br - 25 provides stepless frequency programming by controlling the vco freq. and the clock output divisor ratio. also skew of cpu,sdram and 3v66 clock outputs are programmable. a watch dog timer is quipped and when time out, t he reset# pin will output 4ms pulse signal. the w83195br - 25 accepts a 14.318 mhz reference crystal as its input and runs on a 3.3v supply. high drive pci and sdram clock outputs typically provide greater than 1 v /ns slew rate into 30 pf loads. cpu clock outputs typically provide better than 1 v /ns slew rate into 20 pf loads as maintaining 50 5% duty cycle. the fixed frequency outputs as ref, 24mhz, and 48 mhz provide better than 0.5v /ns slew rate. 2.0 product feature s 2 cpu clocks (2.5v) 3 3v - 6 6 clocks (3.3v) 12 sdram clocks for 3 dimms(3.3v) 8 pci synchronous clocks. optional single or mixed supply: (vddr = vddp=vdds = vdd48 = vdd3 = 3.3v, vdda=vddc=2.5v) skew form cpu to pci clock - 1 to 4 ns, center 2.6 ns smooth frequency switch with selections from 66.8 to 200mhz i 2 c 2 - wire serial interface and i 2 c read back 0.25% center and 0.5% center type spread spectrum programmable registers to enable/stop each output and select modes (mode as tri - state or normal ) 48 mhz for usb 24 mhz for super i/o packaged in 56 - pin ssop
w83195br - 25 preliminary publication release date: m ay 2000 - 2 - revision 0.52 3.0 pin configurati on 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 vddr vss xin xout vdd3 pciclk0/ fs0& vss pciclk6^ pciclk2/sel24_48* pciclk3^/mode1* pciclk4^ sdram_f vss 3v66-0 vddp pd#/reset$ *sdata *sdclk vdda ref0/ fs4&^ ioapic vss cpuclk0 vddc cpuclk1 vss sdram 0 sdram 1 sdram 2 vdds sdram 3 vss sdram 4 sdram 5 sdram 6 sdram 7 vss vdds 48mhz/ *fs3 ^ 24_48mhz/ fs2& pciclk5^ vdd48 vss 3v66-1 vddp pciclk1/ *fs1 pciclk7 vss vss vdds vdds sdram 8 sdram 9 sdram 11 sdram 10 49 50 51 52 53 54 55 56 3v66-2 note: * internal pull - up &: internal pull - down ^ 1.5~2 strength $: open drain 4.0 pin description in - input out - output i/o - bi - directional pin
w83195br - 25 preliminary publication release date: m ay 2000 - 3 - revision 0.52 # - active low * - internal 250k w pull - up 4.1 crystal i/o symbol pin i/o function xin 2 in crystal input with internal loading capacitors(36pf) and feedback resistors. xout 3 out crystal output at 14.318mhz nominally with internal lo ading capacitors(36pf). 4.2 cpu, sdram, pci, ioapic clock outputs symbol pin i/o function cpuclk [0:1] 52,51 out low skew (< 250ps) clock outputs for host frequencies such as cpu and chipset. pd#/reset$ 22 in mode1*=1, power down mode when driven low. mode1*=0, reset# open drain (4ms low active pulse when watch dog time out) ioapic 54 out clock outputs synchronous with pci clock and powered by vdda. sdram_f, sdram[0:11] 38, 48,47,46, 44,43,42,40, 39,31, 30,27, 26 out sdram clock outputs. pciclk0/ f s0& 11 i/o 3.3v 33mhz pci clock during normal operation. latched input for fs0 at initial power up for h/w selecting the output frequency of cpu, sdram and pci clocks(default=0). pciclk1/ *fs1 12 i/o low skew (< 250ps) pci clock outputs. latched input for fs1 at initial power up for h/w selecting the output frequency of cpu, sdram and pci clocks(default=1). pciclk2/ *sel24_48 13 i/o low skew (< 250ps) pci clock outputs. latched input for sel24_48 at initial power up for the out put frequency of 24mhz(high) and 48mhz(low) clocks. pciclk3/ mode1* 15 i/o low skew (< 250ps) pci clock outputs. latched input for mode* pin at initial power up for the output pd# /reset# output selection. pciclk [ 4:7 ] 16,17,19,20 out low skew (< 250ps) pci clock outputs. 3v66 [0:2] 6,7,8 out 3.3v output clocks for the chipset.
w83195br - 25 preliminary publication release date: m ay 2000 - 4 - revision 0.52 4.3 i 2 c control interface symbol pin i/o function *sdata 24 i/o serial data of i 2 c 2 - wire control interface with internal pull - up resistor. *sdclk 23 in ser ial clock of i 2 c 2 - wire control interface with internal pull - up resistor. 4.4 fixed frequency outputs symbol pin i/o function ref0 / fs4& 56 i/o 14.318mhz reference clock. this ref output is the stronger buffer for isa bus loads. latched input for fs4 at initial power up for h/w selecting the output frequency of cpu, sdram and pci clocks (default=0). 24_48mhz/fs2& 35 i/o 24mhz or 48mhz output clock. default is 24mhz. latched input for fs2 at initial power up for h/w selecting the output frequency of cpu , sdram and pci clocks(default=0). 48mhz/ fs3* 34 i/o 48mhz / latched input for fs3 at initial power up for h/w selecting the output frequency of cpu, sdram and pci clocks (default=1). 4.5 power pins symbol pin function vddc,vdda 53,55 power supply for cpu & ioapic, 2.5v or 3.3v. vdd48 33 power supply for 48mhz output,3.3v. vdd3 9 power supply for 3v_66 output, 3.3v. vddp 10,18 power supply for pciclk, 3.3v. vddr 1 power supply for ref0, 3.3v. vdds 45,37,32,25 power supply for sdram_f,sdram[0:11] , nominal 3.3v. vss 4,5,14,21,28,29,36, 41, 49.50 circuit ground.
w83195br - 25 preliminary publication release date: m ay 2000 - 5 - revision 0.52 5.0 frequency selection by hardware fs4 fs3 fs2 fs1 fs0 cpu(mhz) sdram(mhz) 3v66(mhz) pci(mhz) ioapic (mhz) 0 0 0 0 0 55.00 82.50 55.00 27.50 13.75 0 0 0 0 1 60.00 90.00 60.00 30.00 15.00 0 0 0 1 0 66.80 100.20 66.80 33.40 16.70 0 0 0 1 1 68.33 102.50 68.33 34.17 17.08 0 0 1 0 0 70.00 105.00 70.00 35.00 17.50 0 0 1 0 1 72.00 108.00 72.00 36.00 18.00 0 0 1 1 0 75.00 112.50 75.00 37.50 18.75 0 0 1 1 1 77.00 115.50 77.00 38.50 19.25 0 1 0 0 0 83.30 83.30 55.53 27.77 13.88 0 1 0 0 1 90.00 90.00 60.00 30.00 15.00 0 1 0 1 0 100.30 100.30 66.87 33.43 16.72 0 1 0 1 1 103.00 103.00 68.67 34.33 17.17 0 1 1 0 0 112.50 112.50 75.00 37.50 18.75 0 1 1 0 1 115.00 115.00 76.67 38.33 19.17 0 1 1 1 0 120.00 120.00 80.00 40.00 20.00 0 1 1 1 1 125.00 125.00 83.33 41.67 20.83 1 0 0 0 0 128.00 128.00 64.00 32.00 16.00 1 0 0 0 1 130.00 130.00 65.00 32.50 16.25 1 0 0 1 0 133.70 133.70 66.85 33.43 16.71 1 0 0 1 1 137.00 137.00 68.50 34.25 17.13 1 0 1 0 0 140.00 140.00 70.00 35.00 17.50 1 0 1 0 1 145.00 145.00 72.50 36.25 18.13 1 0 1 1 0 150.00 150.00 75.00 37.50 18.75 1 0 1 1 1 153.33 153.33 76.67 38.33 19.17 1 1 0 0 0 125.00 93.75 62.50 31.25 15.63 1 1 0 0 1 130.00 97.50 65.00 32.50 16.25 1 1 0 1 0 133.70 100.28 66.85 33.43 16.71 1 1 0 1 1 137.00 102.75 68.50 34.25 17.13 1 1 1 0 0 140.00 105.00 70.00 35.00 17.50 1 1 1 0 1 145.00 108.75 72.50 36.25 18.13 1 1 1 1 0 150.00 112.50 75.00 37.50 18.75 1 1 1 1 1 153.33 115.00 76.67 38.33 19.17
w83195br - 25 preliminary publication release date: m ay 2000 - 6 - revision 0.52 6. serial control registers the pin column lists the affected pin number and the @powerup column gives the state at true power up. registers are set to the values shown only on true power up. "command code" byte and "byte count" byte must be sent following the acknowledge of the address byte. although the data (bits) in these two bytes are considered "don't care", they must be sent and will be acknowledge. after that, the below described sequence (register 0, register 1, register 2, ....) will be valid and acknowledged. frequency table setting by i2c (sel5 ~ sel0) ssel5 ssel4 ssel3 ssel2 ssel1 ssel0 cpu (mhz) sdram (mhz) 3v66 (mhz) pci(mhz) ioapic (mhz) 0 0 0 0 0 0 55.00 82.50 55.00 27.50 13.75 0 0 0 0 0 1 60.00 90.00 60.00 30.00 15.00 0 0 0 0 1 0 66.80 100.20 66.80 33.40 16.70 0 0 0 0 1 1 68.33 102.50 68.33 34.17 17.08 0 0 0 1 0 0 70.00 105.00 70.00 35.00 17.50 0 0 0 1 0 1 72.00 108.00 72.00 36.00 18.00 0 0 0 1 1 0 75.00 112.50 75.00 37.50 18.75 0 0 0 1 1 1 77.00 115.50 77.00 38.50 19.25 0 0 1 0 0 0 83.30 83.30 55.53 27.77 13.88 0 0 1 0 0 1 90.00 90.00 60.00 30.00 15.00 0 0 1 0 1 0 100.30 100.30 66.87 33.43 16.72 0 0 1 0 1 1 103.00 103.00 68.67 34.33 17.17 0 0 1 1 0 0 112.50 112.50 75.00 37.50 18.75 0 0 1 1 0 1 115.00 115.00 76.67 38.33 19.17 0 0 1 1 1 0 120.00 120.00 80.00 40.00 20.00 0 0 1 1 1 1 125.00 125.00 83.33 41.67 20.83 0 1 0 0 0 0 128.00 128.00 64.00 32.00 16.00 0 1 0 0 0 1 130.00 130.00 65.00 32.50 16.25 0 1 0 0 1 0 133.70 133.70 66.85 33.43 16.71 0 1 0 0 1 1 137.00 137.00 68.50 34.25 17.13 0 1 0 1 0 0 140.00 140.00 70.00 35.00 17.50 0 1 0 1 0 1 145.00 145.00 72.50 36.25 18.13 0 1 0 1 1 0 150.00 150.00 75.00 37.50 18.75 0 1 0 1 1 1 153.33 153.33 76.67 38.33 19.17 0 1 1 0 0 0 125.00 93. 75 62.50 31.25 15.63 0 1 1 0 0 1 130.00 97.50 65.00 32.50 16.25 0 1 1 0 1 0 133.70 100.28 66.85 33.43 16.71 0 1 1 0 1 1 137.00 102.75 68.50 34.25 17.13 0 1 1 1 0 0 140.00 105.00 70.00 35.00 17.50 0 1 1 1 0 1 145.00 108.75 72.50 36.25 18.13
w83195br - 25 preliminary publication release date: m ay 2000 - 7 - revision 0.52 0 1 1 1 1 0 150.00 112.50 75.00 37.50 18.75 0 1 1 1 1 1 153.33 115.00 76.67 38.33 19.17 ssel5 ssel4 ssel3 ssel2 ssel1 ssel0 cpu (mhz) sdram (mhz) 3v66 (mhz) pci(mhz) ioapic (mhz) 1 0 0 0 0 0 66.8 133.00 66.80 33.40 16.70 1 0 0 0 0 1 135.00 135.00 67.50 33.75 16.88 1 0 0 0 1 0 142.00 142.00 71.00 35.50 17.75 1 0 0 0 1 1 143.00 143.00 71.50 35.75 17.88 1 0 0 1 0 0 144.00 144.00 72.00 36.00 18.00 1 0 0 1 0 1 146.00 146.00 73.00 36.50 18.25 1 0 0 1 1 0 147.00 147.00 73.50 36.75 18.38 1 0 0 1 1 1 148.00 148.00 74.00 37.00 18.50 1 0 1 0 0 0 100.20 133.00 66.80 33.40 16.70 1 0 1 0 0 1 156.00 156.00 78.00 39.00 19.50 1 0 1 0 1 0 158.00 158.00 79.00 39.50 19.75 1 0 1 0 1 1 160.00 160.00 80.00 40.00 20.00 1 0 1 1 0 0 135.00 101.25 67.50 33.75 16.88 1 0 1 1 0 1 139.00 104.25 69.50 34.75 17.38 1 0 1 1 1 0 141.00 105.75 70.50 35.25 17.63 1 0 1 1 1 1 142.00 106.50 71.00 35.50 17.75 1 1 0 0 0 0 143.00 107.25 71.50 35.75 17.88 1 1 0 0 0 1 144.00 108.00 72.00 36.00 18.00 1 1 0 0 1 0 146.00 109.50 73.00 36.50 18.25 1 1 0 0 1 1 147.00 110.25 73.50 36.75 18.38 1 1 0 1 0 0 148.00 111.00 74.00 37.00 18.50 1 1 0 1 0 1 149 .00 111.75 74.50 37.25 18.63 1 1 0 1 1 0 153.00 114.75 76.50 38.25 19.13 1 1 0 1 1 1 157.00 117.75 78.50 39.25 19.63 1 1 1 0 0 0 159.00 119.25 79.50 39.75 19.88 1 1 1 0 0 1 162.00 121.50 81.00 40.50 20.25 1 1 1 0 1 0 164.00 123.00 82.00 41.00 20.50 1 1 1 0 1 1 170.00 127.50 85.00 42.50 21.25 1 1 1 1 0 0 175.00 116.67 58.30 29.15 14.58 1 1 1 1 0 1 180.00 120.00 60.00 30.00 15.00 1 1 1 1 1 0 190.00 190.00 63.33 31.67 15.83 1 1 1 1 1 1 200.40 13 3.60 66.80 33.40 16.70
w83195br - 25 preliminary publication release date: m ay 2000 - 8 - revision 0.52 6.1 register 0: cpu frequency select register bit @powerup pin description 7 0 - ssel3 (frequency table selection by software via i 2 c ) 6 0 - ssel2 ( frequency table selection by software via i 2 c) 5 0 - ssel1 ( frequency table selection by software via i 2 c) 4 0 - ssel0 ( frequency table selection by software via i 2 c) 3 0 - 0 = selection by hardware 1 = selection by software i 2 c - bit (2, 7:4) 2 0 - ssel4 (frequency table selection by software via i 2 c ) 1 0 - ssel5 (freq uency table selection by software via i 2 c ) 0 0 - 0 = running 1 = tristate all outputs 6.2 register 1 : cpu clock register (1 = active, 0 = inactive) bit @powerup pin escription 7 x - fs0# 6 x - fs1# 5 x - fs2# 4 x - fs3# 3 x - fs4# 2 0 - 1 = 0.25% center type spread spectrum modulation 0 = 0.5% center type spread spectrum modulation 1 0 - 0 = normal 1 = spread spectrum enabled 0 1 - 1 = center type spread spectrum modulation 0 = down type spread spectrum modulation 6.3 register 2: sdram clock register (1 = active, 0 = inactive) bit @powerup pin description 7 1 39 sdram7 (active / inactive) 6 1 40 sdram6 (active / inactive) 5 1 42 sdram5 (active / inactive) 4 1 43 sdram4 (active / inactive) 3 1 44 sdram3 (active / inactive) 2 1 46 sdram2 (active / inactive) 1 1 47 sdram1 (active / inactive) 0 1 48 sdram0 (active / inactive)
w83195br - 25 preliminary publication release date: m ay 2000 - 9 - revision 0.52 6.4 register 3: pci clock register (1 = active, 0 = inactive) bit @powerup pin description 7 1 20 pciclk7 (active / inactive) 6 1 19 pciclk6 (active / inactive) 5 1 17 pciclk5 (active / inactive) 4 1 16 pciclk4 (active / inactive) 3 1 15 pciclk3 (active / inactive) 2 1 13 pciclk2 (active / inactive) 1 1 12 pciclk1 (active / inactive) 0 1 11 pciclk0 (active / inactive) 6.5 register 4: additional register (1 = active, 0 = inactive) bit @powerup pin description 7 1 8 3v66_2(active / inactive) 6 1 7 3v66_1(active / inactive) 5 1 6 3v66_0(active / inactive) 4 1 26 sdram11 (active / inactive) 3 1 27 sdram10 (active / inactive) 2 1 30 sdram9 (active / inactive ) 1 1 31 sdram8(active / inactive) 0 1 38 sdram_f (active / inactive) 6.6 register 5: sdram clock register (1 = active, 0 = inactive) bit @powerup pin description 7 1 - cskew2 (cpu to sdram skew program bit) 6 0 - cskew1 (cpu to sdram skew program bit) 5 0 - cskew0 (cpu to sdram skew program bit) 4 1 - caskew2 (cpu to 3v66 skew program bit) 3 0 - caskew1 (cpu to 3v66 skew program bit) 2 0 - caskew0 (cpu to 3v66 skew program bit) 1 1 51 cpuclk1(active / inactive) 0 1 52 cpuclk0(active / inactive)
w83195br - 25 preliminary publication release date: m ay 2000 - 10 - revision 0.52 6.7 register 6~10: step - less m/n mode control register 6.12 register 11 : winbond chip id register (read only) bit @powerup pin description 7 0 - winbond chip id 6 1 - winbond chip id 5 0 - winbond chip id 4 1 - winbond chip id 3 0 - winbond chip id 2 0 - winbond chip id 1 0 - winbond chip id 0 0 - winbond chip id 6.14 register 12 : winbond chip id register (read only) bit @powerup pin description 7 0 - winbond chip id 6 0 - winbond chip id 5 0 - winbond chip id 4 1 - winbond chip id 3 0 - winbond version id 2 0 - winbond version id 1 1 - winbond version id 0 0 - winbond version id register10 bit3 - 6 ratio bit6 bit 5 bit 4 bit 3 ds3 ds2 ds1 ds0 cpu sdram 3v66 0 0 0 0 4 4 6 0 0 0 1 3 3 6 0 0 1 0 2 3 6
w83195br - 25 preliminary publication release date: m ay 2000 - 11 - revision 0.52 0 0 1 1 2 2 6 0 1 0 0 6 4 6 0 1 0 1 3 4 6 0 1 1 0 6 3 6 0 1 1 1 4 3 6 1 0 x x 2 2 4 1 1 x x 2 4 6 7.0 specifications 7.1 absolute maximum ratings stresses greater than those listed in this table may cause permanent damage to the device. precautions should be taken to avoid application of any voltage higher than the maximum rated voltages to this circuit. maximum conditions for extended periods may affect reliability. unused inputs must always be tied to an appropriate logic voltage level (ground or vdd). symbol parameter rating vdd , v in voltage on any pin with respect to gnd - 0.5 v to + 7.0 v t stg storage temperature - 65 c to + 150 c t b ambient temperature - 55 c to + 125 c t a operating temperature 0 c to + 70 c 7.2 electronical characteristics - -- input/output vddq1=vddq2 = vddq3 = vddq4 =3.3v, vddl1 =vddl2= 2.5v , t a = 0 c to +70 c parameter symbol min typ max units test conditions
w83195br - 25 preliminary publication release date: m ay 2000 - 12 - revision 0.52 input low voltage v il vss - 0.3 0.8 v dc input high voltage v ih 2.0 vdd+0.3 v dc input low current i il - 5 m a no pull - up resistors input low current i il - 200 m a pull - up resistros input high current i ih - 5 5 m a input capacitance c in 5 pf logic inputs c out 6 pf output capacitance c inx 27 45 pf xin and xout operating supply current i dd3 100 ma cpu = 66.6 mhz pci = 33.3 mhz with load power down supply current i dd2 600 m a settling time ts 3 ms from first crossing to 1% target freq. delay t pzh ,t pzh 1 10 ns output enable delay t plz ,t pzh 1 10 ns output enable delay 7.3 electronical characteristics of cpu clock vdd=2.5v +/ - 5%; c l =10 - 20pf parameter symbol min typ max units test conditions ouput impedance r dsp 13.5 40 ohm ouput impedance r dsn 13.5 40 ohm output low voltage v ol 0.4 v i ol =1ma output high voltage v oh 2.0 v i oh = - 1ma output low current i ol 27 30 ma output high current i oh - 27 - 27 ma pull - up current min i oh(min) - 27 ma vout = 1.0 v pull - up current max i oh(max) - 27 ma vout = 2.0v rise/fall time min between 0.4 v and 2.0 v t rf(min) 0.4 ns 10pf load rise/fall time max between 0.4 v and 2.0 v t rf(max) 1.6 ns 20pf load duty cycle dt 45 55 % v t =1.25v skew t sk 175 ps v t =1.25v jitter tsc - c 250 ps v t =1.25v
w83195br - 25 preliminary publication release date: m ay 2000 - 13 - revision 0.52 7.4 electronical characteristics of 3v66 clock vdd=3.3v +/ - 5%; c l =10 - 30pf parameter symbol m in typ max units test conditions ouput impedance r dsp 15 55 ohm ouput impedance r dsn 15 55 ohm output low voltage v ol 0.55 v i ol =1ma output high voltage v oh 2.4 v i oh = - 1ma output low current i ol 30 38 ma output high current i oh - 33 - 33 ma rise/fall time min between 0.4 v and 2.0 v t rf(min) 0.4 ns 10pf load rise/fall time max between 0.4 v and 2.0 v t rf(max) 1.6 ns 20pf load duty cycle dt 45 55 % v t =1.5v skew t sk 175 ps v t =1.5v jitter tsc - c 500 ps v t =1.5v 7.5 electronical ch aracteristics of sdram clock vdd=3.3v +/ - 5%; c l =20 - 30pf parameter symbol min typ max units test conditions ouput impedance r dsp 13.5 40 ohm ouput impedance r dsn 13.5 40 ohm output low voltage v ol 0.45 v i ol =1ma output high voltage v oh 2.4 v i oh = - 1ma output low current i ol 54 54 ma output high current i oh - 54 - 45 ma rise/fall time min between 0.4 v and 2.0 v t rf(min) 0.4 ns 10pf load rise/fall time max between 0.4 v and 2.0 v t rf(max) 1.6 ns 20pf load duty cycle dt 45 55 % v t =1.5v skew t sk 250 ps v t =1.5v jitter tsc - c 250 ps v t =1.5v
w83195br - 25 preliminary publication release date: m ay 2000 - 14 - revision 0.52 7.6 electronical characteristics of pci clock vdd=3.3v +/ - 5%; c l =10 - 30pf parameter symbol min typ max units test conditions ouput impedance r dsp 15 55 ohm ouput impedance r dsn 15 55 ohm output low voltage v ol 0.55 v i ol =1ma output high voltage v oh 2.4 v i oh = - 1ma output low current i ol 30 38 ma output high current i oh - 33 - 33 ma rise/fall time min between 0.4 v and 2.0 v t rf(min) 0.5 ns 10pf load rise/fall time max between 0.4 v and 2.0 v t rf(max) 2.0 ns 20pf load duty cycle dt 45 55 % v t =1.5v skew t sk 500 ps v t =1.5v jitter tsc - c 500 ps v t =1.5v 7.7 electronical characteristics of 48mhz, ref clock vdd=3.3v +/ - 5%; c l =10 - 20pf parameter symbol min typ max units test conditions ouput impedance r dsp 20 55 ohm ouput impedance r dsn 20 55 ohm output low voltage v ol 0.4 v i ol =1ma output high voltage v oh 2.4 v i oh = - 1ma output low current i ol 29 27 ma output high current i oh - 29 - 23 ma risetime t r 1.8 4 ns 1 0pf load fall time t f 1.7 4 ns 20pf load duty cycle dt 45 55 % v t =1.5v skew t sk 500 ps v t =1.5v jitter tsc - c 1000 ps v t =1.5v
w83195br - 25 preliminary publication release date: m ay 2000 - 15 - revision 0.52 8.0 ordering inform ation part number package type production flow w83195br - 25 56 pin ssop commercial, 0 c to +70 c 9.0 how to read the top marking 1st line: winbond logo and the type number: w83195br - 25 2nd line: tracking code 2 8051234 2 : wafers manufactured in winbond fab 2 8051234 : wafer production se ries lot number 3rd line: tracking code 814 g a b 814 : packages made in ' 98 , week 14 g : assembly house id; o means ose, g means gr a : internal use code w83195br - 25 28051234 814gab
w83195br - 25 preliminary publication release date: m ay 2000 - 16 - revision 0.52 b : ic revision all the trade marks of products and companies mentioned in this data sheet belong to their respective owners.
w83195br - 25 preliminary publication release date: m ay 2000 - 17 - revision 0.52 10.0 package drawin g and dimensions e e b y seating plane c l c l1 0 0.008 0.400 0.292 7.52 0 7.42 8 7.59 10.31 b e d c 18.2 9 10.16 a1 a2 a 10.41 18.54 18.42 2.79 2.34 8 0.299 0.296 0.092 0.110 0.410 0.720 0.730 0.725 0.406 min. dimension in inch symbol dimension in mm min. nom max. max. nom 0.20 e l l1 y q 0.008 0.0135 0.005 0.010 0.024 0.032 0.055 0.003 0.20 0.34 0.13 0.25 0.51 0.76 0.64 0.020 0.030 0.025 0.61 0.81 1.40 0.08 h e q q 2.57 0.101 .045 .055 .035 .045 he 0.40/0.50 dia top view end view see detail "a" parting line side view d a1 a2 a detail"a" 0.095 0.012 0.016 0.088 0.090 0.010 0.040 2.41 0.30 0.41 2.24 2.29 0.25 1.02 headquarters no. 4, creation rd. iii science-based industrial park hsinchu, taiwan tel: 886-35-770066 fax: 886-35-789467 www: http://www.winbond.com.tw/ taipei office 11f, no. 115, sec. 3, min-sheng east rd. taipei, taiwan tel: 886-2-7190505 fax: 886-2-7197502 tlx: 16485 wintpe winbond electronics (h.k.) ltd. rm. 803, world trade square, tower ii 123 hoi bun rd., kwun tong kowloon, hong kong tel: 852-27516023-7 fax: 852-27552064 winbond electronics (north america) corp. 2730 orchard parkway san jose, ca 95134 u.s.a. tel: 1-408-9436666 fax: 1-408-9436668 please note that all data and specifications are subject to change without notice. all the trade marks of products and c ompanies mentioned in this data sheet belong to their respective owners . these products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. winbond customers using or selling these products for use in such applications do so at their
w83195br - 25 preliminary publication release date: m ay 2000 - 18 - revision 0.52 own risk and agree to fully indemnify winbond for any damages resulting from such improper use or s \ \ \ \ \ \ \ \

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