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pd780024a, 780034a, 780024ay, 780034ay subseries 8-bit single-chip microcontrollers pd780021a pd780031a pd780021ay pd780031ay pd780022a pd780032a pd780022ay pd780032ay pd780023a pd780033a pd780023ay pd780033ay pd780024a pd780034a pd780024ay pd780034ay pd780021a(a) pd780031a(a) pd780021ay(a) pd780031ay(a) pd780022a(a) pd780032a(a) pd780022ay(a) pd780032ay(a) pd780023a(a) pd780033a(a) pd780023ay(a) pd780033ay(a) pd780024a(a) pd780034a(a) pd780024ay(a) pd780034ay(a) pd78f0034a pd78f0034ay pd78f0034b pd78f0034by pd78f0034b(a) pd78f0034by(a) document no. u14046ej3v0ud00 (3rd edition) date published october 2003 n cp(k) 1999, 2003 user? manual printed in japan ?
2 user? manual u14046ej3v0ud [memo]
3 user? manual u14046ej3v0ud eeprom, fip, and iebus are trademarks of nec electronics corporation. windows and windows nt are either registered trademarks or trademarks of microsoft corporation in the united states and/or other countries. pc/at is a trademark of international business machines corporation. hp9000 series 700 and hp-ux are trademarks of hewlett-packard company. sparcstation is a trademark of sparc international, inc. solaris and sunos are trademarks of sun microsystems, inc. tron is an abbreviation of the realtime operating system nucleus. itron is an abbreviation of industrial tron. notes for cmos devices 1 precaution against esd for semiconductors note: strong electric field, when exposed to a mos device, can cause destruction of the gate oxide and ultimately degrade the device operation. steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. environmental control must be adequate. when it is dry, humidifier should be used. it is recommended to avoid using insulators that easily build static electricity. semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. all test and measurement tools including work bench and floor should be grounded. the operator should be grounded using wrist strap. semiconductor devices must not be touched with bare hands. similar precautions need to be taken for pw boards with semiconductor devices on it. 2 handling of unused input pins for cmos note: no connection for cmos device inputs can be cause of malfunction. if no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. cmos devices behave differently than bipolar or nmos devices. input levels of cmos devices must be fixed high or low by using a pull-up or pull-down circuitry. each unused pin should be connected to v dd or gnd with a resistor, if it is considered to have a possibility of being an output pin. all handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 status before initialization of mos devices note: power-on does not necessarily define initial status of mos device. production process of mos does not define the initial operation status of the device. immediately after the power source is turned on, the devices with reset function have not yet been initialized. hence, power-on does not guarantee out-pin levels, i/o settings or contents of registers. device is not initialized until the reset signal is received. reset operation must be executed immediately after power-on for devices having reset function.
4 user s manual u14046ej3v0ud these commodities, technology or software, must be exported in accordance with the export administration regulations of the exporting country. diversion contrary to the law of that country is prohibited.
5 user s manual u14046ej3v0ud purchase of nec electronics i 2 c components conveys a license under the philips i 2 c patent rights to use these components in an i 2 c system, provided that the system conforms to the i 2 c standard specification as defined by philips. the information in this document is current as of march, 2003. the information is subject to change without notice. for actual design-in, refer to the latest publications of nec electronics data sheets or data books, etc., for the most up-to-date specifications of nec electronics products. not all products and/or types are available in every country. please check with an nec electronics sales representative for availability and additional information. no part of this document may be copied or reproduced in any form or by any means without the prior written consent of nec electronics. nec electronics assumes no responsibility for any errors that may appear in this document. nec electronics does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of nec electronics products listed in this document or any other liability arising from the use of such products. no license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of nec electronics or others. descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. the incorporation of these circuits, software and information in the design of a customer s equipment shall be done under the full responsibility of the customer. nec electronics assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. while nec electronics endeavors to enhance the quality, reliability and safety of nec electronics products, customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. to minimize risks of damage to property or injury (including death) to persons arising from defects in nec electronics products, customers must incorporate sufficient safety measures in their design, such as redundancy, fire-containment and anti-failure features. nec electronics products are classified into the following three quality grades: "standard", "special" and "specific". the "specific" quality grade applies only to nec electronics products developed based on a customer- designated "quality assurance program" for a specific application. the recommended applications of an nec electronics product depend on its quality grade, as indicated below. customers must check the quality grade of each nec electronics product before using it in a particular application. the quality grade of nec electronics products is "standard" unless otherwise expressly specified in nec electronics data sheets or data books, etc. if customers wish to use nec electronics products in applications not intended by nec electronics, they must contact an nec electronics sales representative in advance to determine nec electronics willingness to support a given application. (note) ? ? ? ? ? ? m8e 02. 11-1 (1) (2) "nec electronics" as used in this statement means nec electronics corporation and also includes its majority-owned subsidiaries. "nec electronics products" means any product developed or manufactured by or for nec electronics (as defined above). computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots. transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support). aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems and medical equipment for life support, etc. "standard": "special": "specific":
6 user s manual u14046ej3v0ud regional information ? device availability ? ordering information ? product release schedule ? availability of related technical literature ? development environment specifications (for example, specifications for third-party tools and components, host computers, power plugs, ac supply voltages, and so forth) ? network requirements in addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary from country to country. [global support] http://www.necel.com/en/support/support.html nec electronics america, inc. (u.s.) santa clara, california tel: 408-588-6000 800-366-9782 nec electronics hong kong ltd. hong kong tel: 2886-9318 nec electronics hong kong ltd. seoul branch seoul, korea tel: 02-558-3737 nec electronics shanghai, ltd. shanghai, p.r. china tel: 021-6841-1138 nec electronics taiwan ltd. taipei, taiwan tel: 02-2719-2377 nec electronics singapore pte. ltd. novena square, singapore tel: 6253-8311 j03.4 n ec electronics (europe) gmbh duesseldorf, germany tel: 0211-65 03 01 sucursal en espa ? a madrid, spain tel: 091-504 27 87 v ? lizy-villacoublay, france tel: 01-30-67 58 00 succursale fran ? aise filiale italiana milano, italy tel: 02-66 75 41 branch the netherlands eindhoven, the netherlands tel: 040-244 58 45 tyskland filial taeby, sweden tel: 08-63 80 820 united kingdom branch milton keynes, uk tel: 01908-691-133 some information contained in this document may vary from country to country. before using any nec electronics product in your application, piease contact the nec electronics office in your country to obtain a list of authorized representatives and distributors. they will verify:
7 user s manual u14046ej3v0ud major revisions in this edition (1/3) page description throughout addition of the following products pd780021ay(a), 780022ay(a), 780023ay(a), 780024ay(a), pd780031ay(a), 780032ay(a), 780033ay(a), 780034ay(a), pd78f0034b, 78f0034b(a), 78f0034by, 78f0034by(a) addition of the following packages ? 64-pin plastic lqfp (gc-8bs type) ? 73-pin plastic fbga (f1-cn3 type) addition of expanded-specification products to pd780024a, 780034a subseries p.34 addition of 1.1 expanded-specification products and conventional products p.54 addition of 1.10 correspondence between mask rom versions and flash memory versions p.54 modification of 1.11 differences between standard grade products and special grade products p.55 addition of 1.12 correspondence between products and packages p.74 addition of 2.9 correspondence between mask rom versions and flash memory versions p.75 modification of 2.10 differences between standard grade products and special grade products p.75 addition of 2.11 correspondence between products and packages p.84 addition of description of pin processing in 3.2.18 v pp (flash memory versions only) p.85 modification of table 3-1 pin i/o circuit types p.96 addition of description of pin processing in 4.2.18 v pp (flash memory versions only) p.97 modification of table 4-1 pin i/o circuit types p.108 addition of description of program area in 5.1.2 internal data memory space pp.116, 117 modification of figure 5-14 data to be saved to stack memory and figure 5-15 data to be restored from stack memory p.130 modification of [description example] in 5.4.4 short direct addressing pp.133 to 135 addition of [illustration] in 5.4.7 based addressing , 5.4.8 based indexed addressing , and 5.4.9 stack addressing pp.140 to 160 modification of port block diagram ( figures 6-2 block diagram of p00 to p03 to 6-23 block diagram of p74 and p75 ) p.163 addition of table 6-6 port mode registers and output latch settings when alternate function is used pp.171, 174 addition of description of internal feedback resistor and oscillation stabilization time select register (osts) in 7.3 clock generator control registers p.185 modification of figure 8-1 block diagram of 16-bit timer/event counter 0 pp.186, 187 modification of tables 8-2 ti00/to0/p70 pin valid edge and cr00, cr01 capture trigger and 8-3 ti01/ p71 pin valid edge and cr00 capture trigger in 2nd edition to table 8-2 cr00 capture trigger and valid edges of ti00 and ti01 pins and table 8-3 cr01 capture trigger and valid edge of ti00 pin (crc02 = 1) p.194 modification of description procedure of each function in 8.4 operation of 16-bit timer/event counter 0 p.208 addition of figure 8-26 ppg output configuration diagram and figure 8-27 ppg output operation timing p.209 addition of 8.5 program list pp.216, 218 modification of 8.6 (3) capture register data retention timing and addition of (11) stop mode or main system clock stop mode setting
8 user? manual u14046ej3v0ud major revisions in this edition (2/3) page description p.220 modification of figures 9-1 block diagram of 8-bit timer/event counter 50 and 9-2 block diagram of 8- bit timer/event counter 51 pp.224, 225 deletion of caution in figures 9-5 format of 8-bit timer mode control register 50 (tmc50) and 9-6 format of 8-bit timer mode control register 51 (tmc51) p.231 addition of [setting] in 9.4.2 external event counter operation p.232 addition of description of frequency to [setting] in 9.4.3 square-wave output (8-bit resolution) operation p.233 addition of description of cycle and duty ratio to [setting] in 9.4.4 8-bit pwm output operation p.238 addition of 9.5 program list p.200 in 2nd deletion of 9.5 (2) operation after compare register change during timer count operation in 2nd edition edition p.208 in 2nd deletion of oscillation stabilization time select register (osts) from 11.3 registers to control watchdog edition timer in 2nd edition p.252 modification of figure 12-1 block diagram of clock output/buzzer output controller pp.259, 260 modification of description in 13.2 (3) sample & hold circuit , (4) voltage comparator , and addition of (10) adtrg pin p.266 addition of table 13-2 sampling time and a/d conversion start delay time of a/d converter pp.277, 278 deletion of 13.6 (4) noise countermeasures (contents of deletion are added to figure 13-18 example of connecting capacitor to av ref pin and figure 13-20 example of connection if signal source impedance is high ), and addition of (14) input impedance of ani0 to ani7 pins p.278 modification of table 13-3 resistances and capacitances of equivalent circuit (reference values) p.281 addition of figure 14-2 format of a/d conversion result register 0 (adcr0) pp.281, 282 modification of description in 14.2 (3) sample & hold circuit , (4) voltage comparator , and addition of (10) adtrg pin p.288 addition of table 14-2 sampling time and a/d conversion start delay time of a/d converter pp.298, 299 deletion of 14.6 (4) noise countermeasures (contents of deletion are added to figure 14-19 example of connecting capacitor to av ref pin and figure 14-21 example of connection if signal source impedance is high ), and addition of (14) input impedance of ani0 to ani7 pins p.299 modification of table 14-3 resistances and capacitances of equivalent circuit (reference values) p.302 modification of figure 16-1 block diagram of serial interface uart0 p.304 move of description of asynchronous serial interface status register 0 (asis0) in 16.3 registers to control serial interface uart0 to 16.2 configuration of serial interface uart0 p.315 addition of caution in figure 16-7 error tolerance (when k = 0 ), including sampling errors p.319 modification of caution in figure 16-10 timing of asynchronous serial interface receive completion interrupt request pp.321, 326 addition of (1) registers to be used and (3) relationship between main system clock and baud rate in 16.4.3 infrared data transfer mode p.328 addition of table 16-6 register settings p.329 modification of figure 17-1 block diagram of serial interface sio3n pp.332, 333 addition of note 3 and caution in figures 17-2 format of serial operation mode register 30 (csim30) and 17-3 format of serial operation mode register 31 (csim31) p.339 addition of table 17-2 register settings p.341 modification of figure 18-1 block diagram of serial interface iic0
9 user s manual u14046ej3v0ud major revisions in this edition (3/3) page description p.343 unification of 18.2 (1) iic shift register 0 (iic0) and (4) iic shift register 0 (iic0) in 2nd edition, and (2) slave address register 0 (sva0) and (3) slave address register 0 (sva0) in 2nd edition p.360 addition of description to transfer lines in figure 18-16 wait signal p.362 addition of description to notes 1 and 2 in table 18-2 intiic0 timing and wait control p.369 modification of figure 18-21 master operation flowchart p.374 modification of 18.5.15 (2) slave operation p.396 modification of (1) start condition ~ address and (2) data in figure 18-23 example of master to slave communication (when 9-clock wait is selected for both master and slave) p.399 modification of figure 18-24 example of slave to master communication (when 9-clock wait is selected for both master and slave) p.405 modification of (e) software interrupt in figure 19-1 basic configuration of interrupt function p.407 addition of caution 5 in figure 19-2 format of interrupt request flag registers (if0l, if0h, if1l) p.410 addition of caution in figure 19-5 format of external interrupt rising edge enable register (egp), external interrupt falling edge enable register (egn) p.412 addition of description and remark in 19.4.1 non-maskable interrupt request acknowledgment operation p.415 addition of description in 19.4.2 maskable interrupt request acknowledgment operation p.418 addition of an item in table 19-4 interrupt requests enabled for nesting during interrupt servicing p.422 addition of description of using expanded-specification products in chapter 20 external device expansion function p.435 addition of clock output and buzzer output in table 21-1 halt mode operating statuses p.438 modification of clock output in table 21-3 stop mode operating statuses p.445 revision of chapter 23 pd78f0034a, 78f0034b, 78f0034ay, 78f0034by p.487 addition of chapter 25 electrical specifications (expanded-specification products: f x = 1.0 to 12 mhz) p.518 addition of chapter 26 electrical specifications (conventional products: f x = 1.0 to 8.38 mhz) p.550 addition of chapter 27 package drawings p.556 addition of chapter 28 recommended soldering conditions p.561 revision of appendix a differences between pd78018f, 780024a, 780034a, and 780078 subseries p.564 revision of appendix b development tools p.581 addition of appendix c notes on target system design the mark shows major revised points.
10 user s manual u14046ej3v0ud introduction readers this manual has been prepared for user engineers who understand the functions of the pd780024a, 780034a, 780024ay, and 780034ay subseries and wish to design and develop application systems and programs for these devices. ? pd780024a subseries pd780021a, 780022a, 780023a, 780024a pd780021a(a), 780022a(a), 780023a(a), 780024a(a) ? pd780034a subseries pd780031a, 780032a, 780033a, 780034a, 78f0034a, 78f0034b pd780031a(a), 780032a(a), 780033a(a), 780034a(a), 78f0034b(a) ? pd780024ay subseries pd780021ay, 780022ay, 780023ay, 780024ay pd780021ay(a), 780022ay(a), 780023ay(a), 780024ay(a) ? pd780034ay subseries pd780031ay, 780032ay, 780033ay, 780034ay, 78f0034ay, 78f0034by pd780031ay(a), 780032ay(a), 780033ay(a), 780034ay(a), 78f0034by(a) purpose this manual is intended to provide users an understanding of the functions described in the organization below. organization the pd780024a, 780034a, 780024ay, and 780034ay subseries manual is separated into two parts: this manual and the instructions edition (common to the 78k/0 series). pd780024a, 780034a, 780024ay, 780034ay 78k/0 series subseries user s manual user s manual (this manual) instructions pin functions cpu functions internal block functions instruction set interrupt explanation of each instruction other on-chip peripheral functions electrical specifications
11 user s manual u14046ej3v0ud how to read this manual it is assumed that the reader of this manual has general knowledge in the fields of electrical engineering, logic circuits, and microcontrollers. for readers who use this as an (a) product: standard products differ from (a) products in their quality grade only. re-read the product name as indicated below if your product is an (a) product. pd780021a pd780021a(a) pd780021ay pd780021ay(a) pd780022a pd780022a(a) pd780022ay pd780022ay(a) pd780023a pd780023a(a) pd780023ay pd780023ay(a) pd780024a pd780024a(a) pd780024ay pd780024ay(a) pd780031a pd780031a(a) pd780031ay pd780031ay(a) pd780032a pd780032a(a) pd780032ay pd780032ay(a) pd780033a pd780033a(a) pd780033ay pd780033ay(a) pd780034a pd780034a(a) pd780034ay pd780034ay(a) pd78f0034b pd78f0034b(a) pd78f0034by pd78f0034by(a) to gain a general understanding of functions: read this manual in the order of the contents. how to interpret the register format: for the bit number enclosed in brackets, the bit name is defined as a reserved word in ra78k0, and in cc78k0, already defined in the header file named sfrbit.h. to check the details of a register when you know the register name: see appendix d register index. to know the details of the 78k/0 series instruction functions: refer to the 78k/0 series instructions user s manual (u12326e). to know the electrical specifications of the pd780024a, 780034a, 780024ay, 780034ay subseries: see chapter 25 electrical specifications (expanded-specification products: f x = 1.0 to 12 mhz) and chapter 26 electrical specifications (conventional products: f x = 1.0 to 8.38 mhz). caution examples in this manual employ the standard quality grade for general electronics. when using examples in this manual for the special quality grade, review the quality grade of each part and/or circuit actually used. differences between pd780024a, 780034a, 780024ay, and 780034ay subseries the configuration of the serial interface and the resolution of the a/d converter differ on pd780024a, 780034a, 780024ay, and 780034ay subseries products. subseries pd780024a pd780034a pd780024ay pd780034ay item configuration of 3-wire serial i/o mode 2ch (sio30, sio31) 1ch (sio30 only) serial interface uart mode 1ch 1ch i 2 c mode none 1ch a/d converter 8-bit resolution 10-bit resolution 8-bit resolution 10-bit resolution
12 user s manual u14046ej3v0ud chapter organization this manual divides the descriptions for the subseries into different chapters as shown below. read only the chapters related to the device you use. chapter pd780024a pd780034a pd780024ay pd780034ay subseries subseries subseries subseries chapter 1 outline ( pd780024a, 780034a subseries) ??? chapter 2 outline ( pd780024ay, 780034ay subseries) ??? chapter 3 pin function ( pd780024a, 780034a subseries) ??? chapter 4 pin function ( pd780024ay, 780034ay subseries) ??? chapter 5 cpu architecture ??? chapter 6 port functions ??? chapter 7 clock generator ??? chapter 8 16-bit timer/event counter 0 ??? chapter 9 8-bit timer/event counters 50, 51 ??? chapter 10 watch timer ??? chapter 11 watchdog timer ??? chapter 12 clock output/buzzer output controller ??? chapter 13 8-bit a/d converter ?? ( pd780024a, 780024ay subseries) chapter 14 10-bit a/d converter ?? ( pd780034a, 780034ay subseries) chapter 15 serial interface outline ??? chapter 16 serial interface uart0 ??? chapter 17 serial interface sio3 ??? chapter 18 serial interface iic0 ??? ( pd780024ay, 780034ay subseries only) chapter 19 interrupt functions ??? chapter 20 external device expansion function ??? chapter 21 standby function ??? chapter 22 reset function ??? chapter 23 pd78f0034a, 78f0034b, 78f0034ay, 78f0034by ??? chapter 24 instruction set ??? chapter 25 electrical specifications (expanded-specification ??? products: f x = 1.0 to 12 mhz) chapter 26 electrical specifications (conventional products: ??? f x = 1.0 to 8.38 mhz) chapter 27 package drawings ??? chapter 28 recommended soldering conditions ??? conventions data significance: higher digits on the left and lower digits on the right active low representation: (overscore over pin or signal name) note : footnote for item marked with note in the text caution : information requiring particular attention remark : supplementary information numerical representation: binary or b decimal hexadecimal h
13 user s manual u14046ej3v0ud related documents the related documents indicated in this publication may include preliminary versions. however, preliminary versions are not marked as such. documents related to devices document name document no. pd780024a, 780034a, 780024ay, 780034ay subseries user s manual this manual 78k/0 series instructions user s manual u12326e 78k/0 series basic (i) application note u12704e documents related to development tools (software) (user s manuals) document name document no. ra78k0 assembler package operation u14445e language u14446e structured assembly language u11789e cc78k0 c compiler operation u14297e language u14298e sm78k series system simulator ver.2.30 or operation (windows tm based) u15373e later external part user open interface specifications u15802e id78k series integrated debugger ver.2.30 or later operation (windows based) u15185e rx78k0 real-time os fundamentals u11537e installation u11536e project manager ver.3.12 or later (windows based) u14610e documents related to development tools (hardware) (user s manuals) document name document no. ie-78k0-ns in-circuit emulator u13731e ie-78k0-ns-a in-circuit emulator u14889e ie-78k0-ns-pa performance board to be prepared ie-780034-ns-em1 emulation board u14642e ie-78001-r-a in-circuit emulator u14142e ie-78k0-r-ex1 in-circuit emulator to be prepared documents related to flash memory programming document name document no. pg-fp3 flash memory programmer user s manual u13502e pg-fp4 flash memory programmer user s manual u15260e caution the related documents listed above are subject to change without notice. be sure to use the latest version of each document for designing.
14 user s manual u14046ej3v0ud other documents document name document no. semiconductor selection guide ? products and packages ? x13769x semiconductor device mount manual note quality grades on nec semiconductor devices c11531e nec semiconductor device reliability/quality control system c10983e guide to prevent damage for semiconductor devices by electrostatic discharge (esd) c11892e note see the semiconductor device mount manual website (http://www.necel.com/pkg/en/mount/index.html). caution the related documents listed above are subject to change without notice. be sure to use the latest version of each document for designing.
15 user? manual u14046ej3v0ud contents chapter 1 outline ( pd780024a, 780034a subseries) .................................................... 34 1.1 expanded-specification products and conventional products ....................................... 34 1.2 features .................................................................................................................... ............. 35 1.3 applications ................................................................................................................ .......... 36 1.4 ordering information ........................................................................................................ .... 37 1.5 quality grade ............................................................................................................... ......... 41 1.6 pin configuration (top view) ............................................................................................... 4 5 1.7 78k/0 series lineup ......................................................................................................... ..... 49 1.8 block diagram ............................................................................................................... ........ 51 1.9 outline of function ......................................................................................................... ...... 52 1.10 correspondence between mask rom versions and flash memory versions ............... 54 1.11 differences between standard grade products and special grade products ............... 54 1.12 correspondence between products and packages .......................................................... 55 1.13 mask options ............................................................................................................... ......... 55 chapter 2 outline ( pd780024ay, 780034ay subseries) .................................................. 56 2.1 features .................................................................................................................... ............. 56 2.2 applications ................................................................................................................ .......... 57 2.3 ordering information ........................................................................................................ .... 58 2.4 quality grade ............................................................................................................... ......... 62 2.5 pin configuration (top view) ............................................................................................... 6 6 2.6 78k/0 series lineup ......................................................................................................... ..... 70 2.7 block diagram ............................................................................................................... ........ 72 2.8 outline of function ......................................................................................................... ...... 73 2.9 correspondence between mask rom versions and flash memory versions ............... 74 2.10 differences between standard grade products and special grade products ............... 75 2.11 correspondence between products and packages .......................................................... 75 2.12 mask options ............................................................................................................... ......... 76 chapter 3 pin function ( pd780024a, 780034a subseries) .......................................... 77 3.1 pin function list ........................................................................................................... ........ 77 3.2 description of pin functions ............................................................................................... 8 0 3.2.1 p00 to p03 (port 0) ....................................................................................................... ............. 80 3.2.2 p10 to p17 (port 1) ....................................................................................................... ............. 80 3.2.3 p20 to p25 (port 2) ....................................................................................................... ............. 81 3.2.4 p30 to p36 (port 3) ....................................................................................................... ............. 81 3.2.5 p40 to p47 (port 4) ....................................................................................................... ............. 82 3.2.6 p50 to p57 (port 5) ....................................................................................................... ............. 82 3.2.7 p64 to p67 (port 6) ....................................................................................................... ............. 82 3.2.8 p70 to p75 (port 7) ....................................................................................................... ............. 83 3.2.9 av ref ............................................................................................................................... ........... 83 3.2.10 av dd ............................................................................................................................... ............ 83 3.2.11 av ss ............................................................................................................................... ............ 83 3.2.12 reset .................................................................................................................... ................... 84 3.2.13 nc ....................................................................................................................... ....................... 84
16 user? manual u14046ej3v0ud 3.2.14 x1 and x2 ................................................................................................................ .................. 84 3.2.15 xt1 and xt2 .............................................................................................................. ................ 84 3.2.16 v dd0 and v dd1 ............................................................................................................................. 84 3.2.17 v ss0 and v ss1 ............................................................................................................................. 84 3.2.18 v pp (flash memory versions only) ............................................................................................... 84 3.2.19 ic (mask rom version only) ............................................................................................... ....... 84 3.3 pin i/o circuits and recommended connection of unused pins .................................... 85 chapter 4 pin function ( pd780024ay, 780034ay subseries) ....................................... 89 4.1 pin function list ........................................................................................................... ........ 89 4.2 description of pin functions ............................................................................................... 9 2 4.2.1 p00 to p03 (port 0) ....................................................................................................... ............. 92 4.2.2 p10 to p17 (port 1) ....................................................................................................... ............. 92 4.2.3 p20 to p25 (port 2) ....................................................................................................... ............. 93 4.2.4 p30 to p36 (port 3) ....................................................................................................... ............. 93 4.2.5 p40 to p47 (port 4) ....................................................................................................... ............. 94 4.2.6 p50 to p57 (port 5) ....................................................................................................... ............. 94 4.2.7 p64 to p67 (port 6) ....................................................................................................... ............. 94 4.2.8 p70 to p75 (port 7) ....................................................................................................... ............. 95 4.2.9 av ref ............................................................................................................................... ........... 95 4.2.10 av dd ............................................................................................................................... ............ 95 4.2.11 av ss ............................................................................................................................... ............ 95 4.2.12 reset .................................................................................................................... ................... 96 4.2.13 nc ....................................................................................................................... ....................... 96 4.2.14 x1 and x2 ................................................................................................................ .................. 96 4.2.15 xt1 and xt2 .............................................................................................................. ................ 96 4.2.16 v dd0 and v dd1 ............................................................................................................................. 96 4.2.17 v ss0 and v ss1 ............................................................................................................................. 96 4.2.18 v pp (flash memory versions only) ............................................................................................... 96 4.2.19 ic (mask rom version only) ............................................................................................... ....... 96 4.3 pin i/o circuits and recommended connection of unused pins .................................... 97 chapter 5 cpu architecture ................................................................................................. 101 5.1 memory spaces ............................................................................................................... ...... 101 5.1.1 internal program memory space ............................................................................................. ... 106 5.1.2 internal data memory space ................................................................................................ ...... 108 5.1.3 special function register (sfr) area ...................................................................................... .... 108 5.1.4 external memory space ..................................................................................................... ........ 108 5.1.5 data memory addressing .................................................................................................... ....... 109 5.2 processor registers ......................................................................................................... .... 114 5.2.1 control registers ......................................................................................................... ................ 114 5.2.2 general-purpose registers ................................................................................................. ........ 118 5.2.3 special function register (sfr) ........................................................................................... ....... 119 5.3 instruction address addressing ......................................................................................... 123 5.3.1 relative addressing ....................................................................................................... ............ 123 5.3.2 immediate addressing ...................................................................................................... .......... 124 5.3.3 table indirect addressing ................................................................................................. .......... 125 5.3.4 register addressing ....................................................................................................... ............ 126
17 user? manual u14046ej3v0ud 5.4 operand address addressing ............................................................................................. 127 5.4.1 implied addressing ........................................................................................................ ............. 127 5.4.2 register addressing ....................................................................................................... ............ 128 5.4.3 direct addressing ......................................................................................................... .............. 129 5.4.4 short direct addressing ................................................................................................... ........... 130 5.4.5 special function register (sfr) addressing ............................................................................... 1 31 5.4.6 register indirect addressing .............................................................................................. ........ 132 5.4.7 based addressing .......................................................................................................... ............ 133 5.4.8 based indexed addressing .................................................................................................. ....... 134 5.4.9 stack addressing .......................................................................................................... ............. 135 chapter 6 port functions ................................................................................................... ... 136 6.1 port functions .............................................................................................................. ......... 136 6.2 port configuration .......................................................................................................... ...... 139 6.2.1 port 0 .................................................................................................................... ...................... 139 6.2.2 port 1 .................................................................................................................... ...................... 141 6.2.3 port 2 .................................................................................................................... ...................... 142 6.2.4 port 3 ( pd780024a, 780034a subseries) ............................................................................... 145 6.2.5 port 3 ( pd780024ay, 780034ay subseries) ........................................................................... 150 6.2.6 port 4 .................................................................................................................... ...................... 154 6.2.7 port 5 .................................................................................................................... ...................... 155 6.2.8 port 6 .................................................................................................................... ...................... 156 6.2.9 port 7 .................................................................................................................... ...................... 158 6.3 port function control registers ......................................................................................... 161 6.4 port function operations .................................................................................................... . 167 6.4.1 writing to i/o port ....................................................................................................... ................ 167 6.4.2 reading from i/o port ..................................................................................................... ........... 167 6.4.3 operations on i/o port .................................................................................................... ........... 167 6.5 selection of mask option .................................................................................................... . 168 chapter 7 clock generator ................................................................................................. 1 69 7.1 clock generator functions .................................................................................................. 1 69 7.2 clock generator configuration ........................................................................................... 169 7.3 clock generator control registers ..................................................................................... 171 7.4 system clock oscillator ..................................................................................................... .. 175 7.4.1 main system clock oscillator .............................................................................................. ........ 175 7.4.2 subsystem clock oscillator ................................................................................................ ......... 176 7.4.3 when subsystem clock is not used .......................................................................................... .. 179 7.5 clock generator operations ................................................................................................ 18 0 7.5.1 main system clock operations .............................................................................................. ...... 181 7.5.2 subsystem clock operations ................................................................................................ ...... 182 7.6 changing system clock and cpu clock settings ............................................................. 182 7.6.1 time required for switchover between system clock and cpu clock ......................................... 182 7.6.2 system clock and cpu clock switching procedure .................................................................... 183 chapter 8 16-bit timer/event counter 0 .......................................................................... 184 8.1 functions of 16-bit timer/event counter 0 ........................................................................ 184 8.2 configuration of 16-bit timer/event counter 0 .................................................................. 185
18 user? manual u14046ej3v0ud 8.3 registers to control 16-bit timer/event counter 0 ........................................................... 188 8.4 operation of 16-bit timer/event counter 0 ........................................................................ 194 8.4.1 interval timer operation .................................................................................................. ............ 194 8.4.2 external event counter operation .......................................................................................... ..... 197 8.4.3 pulse width measurement operations ........................................................................................ 199 8.4.4 square-wave output operation .............................................................................................. ..... 206 8.4.5 ppg output operation ...................................................................................................... .......... 207 8.5 program list ................................................................................................................ .......... 209 8.5.1 interval timer ............................................................................................................ .................. 210 8.5.2 pulse width measurement by free-running counter and one capture register ........................... 211 8.5.3 two pulse widths measurement by free-running counter .......................................................... 212 8.5.4 pulse width measurement by restart ........................................................................................ .. 214 8.5.5 ppg output ................................................................................................................ ................ 215 8.6 cautions related to 16-bit timer/event counter 0 ............................................................ 216 chapter 9 8-bit timer/event counters 50, 51 ................................................................ 219 9.1 functions of 8-bit timer/event counters 50, 51 ................................................................ 219 9.2 configuration of 8-bit timer/event counters 50, 51 .......................................................... 221 9.3 registers to control 8-bit timer/event counters 50, 51 ................................................... 222 9.4 operation of 8-bit timer/event counters 50, 51 ................................................................ 227 9.4.1 8-bit interval timer operation ............................................................................................ .......... 227 9.4.2 external event counter operation .......................................................................................... ..... 231 9.4.3 square-wave output (8-bit resolution) operation ........................................................................ 232 9.4.4 8-bit pwm output operation ................................................................................................ ....... 233 9.4.5 interval timer (16-bit) operations ........................................................................................ ........ 237 9.5 program list ................................................................................................................ .......... 238 9.5.1 interval timer (8-bit) .................................................................................................... ................ 238 9.5.2 external event counter .................................................................................................... ........... 239 9.5.3 interval timer (16-bit) ................................................................................................... ............... 240 9.6 cautions related to 8-bit timer/event counters 50, 51 .................................................... 241 chapter 10 watch timer ..................................................................................................... ..... 242 10.1 watch timer functions ...................................................................................................... .. 242 10.2 watch timer configuration .................................................................................................. 243 10.3 register to control watch timer ......................................................................................... 244 10.4 watch timer operations ..................................................................................................... . 245 10.4.1 watch timer operation .................................................................................................... ............ 245 10.4.2 interval timer operation .............................................................................................. ................ 245 chapter 11 watchdog timer .................................................................................................. 247 11.1 watchdog timer functions .................................................................................................. 2 47 11.2 watchdog timer configuration ........................................................................................... 248 11.3 registers to control watchdog timer ................................................................................ 248 11.4 watchdog timer operations ................................................................................................ 25 0 11.4.1 watchdog timer operation .............................................................................................. ............ 250 11.4.2 interval timer operation .............................................................................................. ................. 251
19 user? manual u14046ej3v0ud chapter 12 clock output/buzzer output controller ............................................ 252 12.1 clock output/buzzer output controller functions ........................................................... 252 12.2 configuration of clock output/buzzer output controller ................................................ 253 12.3 register to control clock output/buzzer output controller ............................................ 253 12.4 operation of clock output/buzzer output controller ....................................................... 256 12.4.1 operation as clock output ............................................................................................. ............. 256 12.4.2 operation as buzzer output ............................................................................................ ............ 256 chapter 13 8-bit a/d converter ( pd780024a, 780024ay subseries) ....................... 257 13.1 a/d converter functions ................................................................................................. .... 257 13.2 a/d converter configuration ............................................................................................. .. 259 13.3 registers to control a/d converter .................................................................................... 26 1 13.4 a/d converter operations ................................................................................................ .... 264 13.4.1 basic operations of a/d converter ..................................................................................... ......... 264 13.4.2 input voltage and conversion results .................................................................................. ........ 267 13.4.3 a/d converter operation mode .......................................................................................... ......... 268 13.5 how to read a/d converter characteristics table ........................................................... 271 13.6 a/d converter cautions .................................................................................................. ..... 274 chapter 14 10-bit a/d converter ( pd780034a, 780034ay subseries) ...................... 279 14.1 a/d converter functions ................................................................................................. .... 279 14.2 a/d converter configuration ............................................................................................. .. 281 14.3 registers to control a/d converter .................................................................................... 28 3 14.4 a/d converter operation ................................................................................................. ..... 286 14.4.1 basic operations of a/d converter ..................................................................................... ......... 286 14.4.2 input voltage and conversion results .................................................................................. ........ 289 14.4.3 a/d converter operation mode .......................................................................................... ......... 290 14.5 how to read a/d converter characteristics table ........................................................... 292 14.6 a/d converter cautions .................................................................................................. ..... 295 chapter 15 serial interface outline ............................................................................... 300 chapter 16 serial interface uart0 ................................................................................... 301 16.1 functions of serial interface uart0 ................................................................................... 301 16.2 configuration of serial interface uart0 ............................................................................ 303 16.3 registers to control serial interface uart0 ...................................................................... 305 16.4 operation of serial interface uart0 ................................................................................... 310 16.4.1 operation stop mode ................................................................................................... ............... 310 16.4.2 asynchronous serial interface (uart) mode ............................................................................. 310 16.4.3 infrared data transfer mode ........................................................................................... ............. 321 chapter 17 serial interfaces sio30 and sio31 ............................................................ 329 17.1 functions of serial interfaces sio30 and sio31 ................................................................ 329 17.2 configuration of serial interfaces sio30 and sio31 ......................................................... 330 17.3 registers to control serial interfaces sio30 and sio31 ................................................... 331 17.4 operations of serial interfaces sio30 and sio31 .............................................................. 335 17.4.1 operation stop mode ................................................................................................... ............... 335 17.4.2 3-wire serial i/o mode ................................................................................................ ................ 336
20 user? manual u14046ej3v0ud chapter 18 serial interface iic0 ( pd780024ay, 780034ay subseries only) ..... 340 18.1 functions of serial interface iic0 ........................................................................................ 3 40 18.2 configuration of serial interface iic0 .................................................................................. 343 18.3 registers to control serial interface iic0 ........................................................................... 345 18.4 i 2 c bus mode functions ....................................................................................................... 355 18.4.1 pin configuration ..................................................................................................... ................... 355 18.5 i 2 c bus definitions and control methods ........................................................................... 356 18.5.1 start conditions ......................................................................................................... ................. 356 18.5.2 addresses ................................................................................................................ .................. 357 18.5.3 transfer direction specification ......................................................................................... ......... 357 18.5.4 acknowledge (ack) signal ................................................................................................. ....... 358 18.5.5 stop condition ........................................................................................................... ................. 359 18.5.6 wait signal (wait) ....................................................................................................... .............. 360 18.5.7 interrupt request (intiic0) generation timing and wait control .................................................. 362 18.5.8 address match detection method ........................................................................................... ... 363 18.5.9 error detection .......................................................................................................... ................. 363 18.5.10 extension code .......................................................................................................... ................ 363 18.5.11 arbitration ............................................................................................................. ...................... 364 18.5.12 wake-up function ........................................................................................................ ............... 365 18.5.13 communication reservation ............................................................................................... ........ 366 18.5.14 other cautions .......................................................................................................... .................. 368 18.5.15 communication operations ................................................................................................ ........ 369 18.5.16 timing of i 2 c interrupt request (intiic0) occurrence ................................................................. 377 18.6 timing charts .............................................................................................................. .......... 395 chapter 19 interrupt functions ......................................................................................... 402 19.1 interrupt function types ................................................................................................... ... 402 19.2 interrupt sources and configuration .................................................................................. 402 19.3 interrupt function control registers .................................................................................. 406 19.4 interrupt servicing operations ............................................................................................ 4 12 19.4.1 non-maskable interrupt request acknowledgment operation ..................................................... 412 19.4.2 maskable interrupt request acknowledgment operation ............................................................ 415 19.4.3 software interrupt request acknowledgment operation .............................................................. 417 19.4.4 nesting interrupt servicing .............................................................................................. ........... 418 19.4.5 interrupt request hold ................................................................................................... .............. 421 chapter 20 external device expansion function ...................................................... 422 20.1 external device expansion function .................................................................................. 422 20.2 external device expansion function control registers ................................................... 425 20.3 external device expansion function timing ..................................................................... 427 20.4 example of connection with memory ................................................................................. 432 chapter 21 standby function ............................................................................................... 4 33 21.1 standby function and configuration .................................................................................. 433 21.1.1 standby function ......................................................................................................... ............... 433 21.1.2 standby function control register ........................................................................................ ....... 434 21.2 standby function operations .............................................................................................. 43 5 21.2.1 halt mode ................................................................................................................ ................ 435 21.2.2 stop mode ................................................................................................................ ............... 438
21 user? manual u14046ej3v0ud chapter 22 reset function .................................................................................................. .. 441 chapter 23 pd78f0034a, 78f0034b, 78f0034ay, 78f0034by .............................................. 445 23.1 differences between pd78f0034a, 78f0034ay and pd78f0034b, 78f0034by ......... 446 23.2 differences between pd78f0034b, 78f0034by and pd78f0034b(a), 78f0034by(a) ......................................................................................... 447 23.3 differences between pd78f0034a, 78f0034b, 78f0034ay, 78f0034by and mask rom versions ...................................................................................................... 448 23.4 memory size switching register ......................................................................................... 450 23.5 flash memory characteristics ............................................................................................. 45 1 23.5.1 programming environment .................................................................................................. ....... 451 23.5.2 communication mode ....................................................................................................... ......... 452 23.5.3 on-board pin processing .................................................................................................. .......... 457 23.5.4 connection on adapter for flash memory writing ....................................................................... 460 chapter 24 instruction set ................................................................................................. .. 472 24.1 conventions ................................................................................................................ .......... 473 24.1.1 operand identifiers and specification methods .......................................................................... 47 3 24.1.2 description of ?peration?column ........................................................................................ ...... 474 24.1.3 description of ?lag operation?column ................................................................................... .... 474 24.2 operation list ............................................................................................................. ........... 475 24.3 instructions listed by addressing type ............................................................................ 483 chapter 25 electrical specifications (expanded-specification products: fx = 1.0 to 12 mhz) ..................... 487 chapter 26 electrical specifications (conventional products: fx = 1.0 to 8.38 mhz) ...................................... 518 chapter 27 package drawings ............................................................................................. 550 chapter 28 recommended soldering conditions ........................................................ 556 appendix a differences between pd78018f, 780024a, 780034a, and 780078 subseries ......................................................................................... 561 appendix b development tools ........................................................................................... 564 b.1 software package ............................................................................................................ ..... 567 b.2 language processing software .......................................................................................... 567 b.3 control software ............................................................................................................ ....... 568 b.4 flash memory writing tools ................................................................................................ 56 9 b.5 debugging tools (hardware) ............................................................................................... 569 b.5.1 when using the in-circuit emulator ie-78k0-ns, ie-78k0-ns-a ................................................ 569 b.5.2 when using the in-circuit emulator ie-78001-r-a ...................................................................... 571 b.6 debugging tools (software) ................................................................................................ 57 2 b.7 embedded software ........................................................................................................... .. 573 b.8 system upgrade from former in-circuit emulator for 78k/0 series to ie-78001-r-a .... 574 b.9 package drawings of conversion socket and conversion adapter ............................... 575
22 user? manual u14046ej3v0ud appendix c notes on target system design ................................................................ 581 appendix d register index .................................................................................................. .... 591 d.1 register name index ......................................................................................................... ... 591 d.2 register symbol index ....................................................................................................... .. 594 appendix e revision history ................................................................................................ .. 597
23 user? manual u14046ej3v0ud list of figures (1/8) figure no. title page 3-1 pin i/o circuit list ........................................................................................................ ........................ 87 4-1 pin i/o circuit list ........................................................................................................ ........................ 99 5-1 memory map ( pd780021a, 780031a, 780021ay, 780031ay) .......................................................... 101 5-2 memory map ( pd780022a, 780032a, 780022ay, 780032ay) .......................................................... 102 5-3 memory map ( pd780023a, 780033a, 780023ay, 780033ay) .......................................................... 103 5-4 memory map ( pd780024a, 780034a, 780024ay, 780034ay) .......................................................... 104 5-5 memory map ( pd78f0034a, 78f0034b, 78f0034ay, 78f0034by) ................................................. 105 5-6 correspondence between data memory and addressing ( pd780021a, 780031a, 780021ay, 780031ay) ................................................................................ 109 5-7 correspondence between data memory and addressing ( pd780022a, 780032a, 780022ay, 780032ay) ................................................................................ 110 5-8 correspondence between data memory and addressing ( pd780023a, 780033a, 780023ay, 780033ay) ................................................................................ 111 5-9 correspondence between data memory and addressing ( pd780024a, 780034a, 780024ay, 780034ay) ................................................................................ 112 5-10 correspondence between data memory and addressing ( pd78f0034a, 78f0034b, 78f0034ay, 78f0034by) ....................................................................... 113 5-11 program counter format ..................................................................................................... ................ 114 5-12 program status word format ................................................................................................. ............. 114 5-13 stack pointer format ....................................................................................................... .................... 116 5-14 data to be saved to stack memory ........................................................................................... .......... 116 5-15 data to be restored from stack memory ...................................................................................... ...... 117 5-16 general-purpose register configuration ..................................................................................... ........ 118 6-1 port types .................................................................................................................. .......................... 136 6-2 block diagram of p00 to p03 ................................................................................................. .............. 140 6-3 block diagram of p10 to p17 ................................................................................................. .............. 141 6-4 block diagram of p20, p23, and p25 .......................................................................................... ........ 142 6-5 block diagram of p21 and p24 ................................................................................................ ............ 143 6-6 block diagram of p22 ........................................................................................................ .................. 144 6-7 block diagram of p30 and p31 ( pd780024a, 780034a subseries) .................................................. 145 6-8 block diagram of p32 and p33 ( pd780024a, 780034a subseries) .................................................. 146 6-9 block diagram of p34 ( pd780024a, 780034a subseries) ................................................................ 147 6-10 block diagram of p35 ( pd780024a, 780034a subseries) ................................................................ 148 6-11 block diagram of p36 ( pd780024a, 780034a subseries) ................................................................ 149 6-12 block diagram of p30 and p31 ( pd780024ay, 780034ay subseries) .............................................. 151 6-13 block diagram of p32 and p33 ( pd780024ay, 780034ay subseries) .............................................. 151 6-14 block diagram of p34 and p36 ( pd780024ay, 780034ay subseries) .............................................. 152
24 user? manual u14046ej3v0ud list of figures (2/8) figure no. title page 6-15 block diagram of p35 ( pd780024ay, 780034ay subseries) ............................................................ 153 6-16 block diagram of p40 to p47 ................................................................................................ ............... 154 6-17 block diagram of falling edge detector ..................................................................................... ......... 155 6-18 block diagram of p50 to p57 ................................................................................................ ............... 155 6-19 block diagram of p64, p65, and p67 ......................................................................................... ......... 156 6-20 block diagram of p66 ....................................................................................................... ................... 157 6-21 block diagram of p70, p72, and p73 ......................................................................................... ......... 158 6-22 block diagram of p71 ....................................................................................................... ................... 159 6-23 block diagram of p74 and p75 ............................................................................................... ............. 160 6-24 format of port mode register (pm0, pm2 to pm7) ............................................................................. 162 6-25 format of pull-up resistor option register (pu0, pu2 to pu7) ......................................................... 166 7-1 block diagram of clock generator ............................................................................................ .......... 170 7-2 format of processor clock control register (pcc) ............................................................................ 172 7-3 format of oscillation stabilization time select register (osts) ........................................................ 174 7-4 external circuit of main system clock oscillator ............................................................................ ..... 175 7-5 external circuit of subsystem clock oscillator .............................................................................. ...... 176 7-6 examples of incorrect oscillator connection ................................................................................. ...... 177 7-7 subsystem clock feedback resistor ........................................................................................... ....... 179 7-8 main system clock stop function ............................................................................................. .......... 181 7-9 system clock and cpu clock switching ........................................................................................ ..... 183 8-1 block diagram of 16-bit timer/event counter 0 ............................................................................... ... 185 8-2 format of 16-bit timer mode control register 0 (tmc0) .................................................................... 189 8-3 format of capture/compare control register 0 (crc0) ..................................................................... 190 8-4 format of 16-bit timer output control register 0 (toc0) .................................................................. 191 8-5 format of prescaler mode register 0 (prm0) .................................................................................. .. 192 8-6 format of port mode register 7 (pm7) ........................................................................................ ........ 193 8-7 control register settings for interval timer operation ...................................................................... .. 194 8-8 interval timer configuration diagram ........................................................................................ .......... 195 8-9 timing of interval timer operation .......................................................................................... ............. 195 8-10 timing after change of compare register during timer count operation ......................................... 196 8-11 control register settings in external event counter mode ................................................................. 19 7 8-12 external event counter configuration diagram ............................................................................... .... 198 8-13 external event counter operation timing (with rising edge specified) ............................................. 198 8-14 control register settings for pulse width measurement with free-running counter and one capture register ....................................................................................................... ............ 199 8-15 configuration diagram for pulse width measurement with free-running counter ............................ 200 8-16 timing of pulse width measurement operation with free-running counter and one capture register (with both edges specified) ...................................................................... 200 8-17 control register settings for measurement of two pulse widths with free-running counter ........... 201
25 user? manual u14046ej3v0ud list of figures (3/8) figure no. title page 8-18 timing of pulse width measurement operation with free-running counter (with both edges specified) .................................................................................................... ............. 202 8-19 control register settings for pulse width measurement with free-running counter and two capture registers ...................................................................................................... ........... 203 8-20 timing of pulse width measurement operation with free-running counter and two capture registers (with rising edge specified) ................................................................... 204 8-21 control register settings for pulse width measurement by means of restart ................................... 205 8-22 timing of pulse width measurement operation by means of restart (with rising edge specified) ... 205 8-23 control register settings in square-wave output mode .................................................................... 206 8-24 square-wave output operation timing ........................................................................................ ....... 206 8-25 control register settings for ppg output operation ......................................................................... . 207 8-26 ppg output configuration diagram ........................................................................................... ......... 208 8-27 ppg output operation timing ................................................................................................ ............. 208 8-28 start timing of 16-bit timer counter 0 (tm0) ............................................................................... ....... 216 8-29 capture register data retention timing ..................................................................................... ........ 216 8-30 operation timing of ovf0 flag .............................................................................................. ............. 217 8-31 cr01 capture operation with rising edge specified ......................................................................... 2 18 9-1 block diagram of 8-bit timer/event counter 50 ............................................................................... ... 220 9-2 block diagram of 8-bit timer/event counter 51 ............................................................................... ... 220 9-3 format of timer clock select register 50 (tcl50) ............................................................................ . 222 9-4 format of timer clock select register 51 (tcl51) ............................................................................ . 223 9-5 format of 8-bit timer mode control register 50 (tmc50) .................................................................. 224 9-6 format of 8-bit timer mode control register 51 (tmc51) .................................................................. 225 9-7 format of port mode register 7 (pm7) ........................................................................................ ........ 226 9-8 interval timer operation timing ............................................................................................. .............. 228 9-9 external event counter operation timing (with rising edge specified) ............................................. 231 9-10 square-wave output operation timing ........................................................................................ ....... 233 9-11 pwm output operation timing ................................................................................................ ............ 235 9-12 timing of operation by change of cr5n ...................................................................................... ....... 236 9-13 16-bit resolution cascade connection mode .................................................................................. ... 237 9-14 start timing of 8-bit timer counter 5n (tm5n) .............................................................................. ...... 241 10-1 watch timer block diagram .................................................................................................. .............. 242 10-2 format of watch timer operation mode register (wtm) ................................................................... 244 10-3 operation timing of watch timer/interval timer ............................................................................. ..... 246 11-1 watchdog timer block diagram ............................................................................................... ........... 247 11-2 format of watchdog timer clock select register (wdcs) ................................................................. 248 11-3 format of watchdog timer mode register (wdtm) ........................................................................... 249
26 user? manual u14046ej3v0ud list of figures (4/8) figure no. title page 12-1 block diagram of clock output/buzzer output controller ................................................................... 25 2 12-2 format of clock output select register (cks) ............................................................................... .... 254 12-3 format of port mode register 7 (pm7) ....................................................................................... ......... 255 12-4 remote control output application example .................................................................................. .... 256 13-1 8-bit a/d converter block diagram .......................................................................................... ........... 258 13-2 format of a/d converter mode register 0 (adm0) ............................................................................. 262 13-3 format of analog input channel specification register 0 (ads0) ...................................................... 263 13-4 basic operation of 8-bit a/d converter ..................................................................................... .......... 265 13-5 relationship between analog input voltage and a/d conversion result ............................................ 267 13-6 a/d conversion by hardware start (when falling edge is specified) ................................................ 269 13-7 a/d conversion by software start ........................................................................................... ............ 270 13-8 overall error.............................................................................................................. ........................... 271 13-9 quantization error ......................................................................................................... ....................... 271 13-10 zero scale error .......................................................................................................... ......................... 272 13-11 full scale error .......................................................................................................... .......................... 272 13-12 integral linearity error .................................................................................................. ....................... 272 13-13 differential linearity error .............................................................................................. ...................... 272 13-14 circuit configuration of series resistor string ........................................................................... ......... 274 13-15 a/d conversion end interrupt request generation timing ................................................................. 275 13-16 timing of reading conversion result (when conversion result is undefined) ................................. 276 13-17 av dd pin connection ................................................................................................................ ........... 276 13-18 example of connecting capacitor to av ref pin ................................................................................... 277 13-19 internal equivalent circuit of pins ani0 to ani7 .......................................................................... ........ 277 13-20 example of connection if signal source impedance is high .............................................................. 278 14-1 10-bit a/d converter block diagram ......................................................................................... .......... 280 14-2 format of a/d conversion result register 0 (adcr0) ....................................................................... 28 1 14-3 format of a/d converter mode register 0 (adm0) ............................................................................. 284 14-4 format of analog input channel specification register 0 (ads0) ...................................................... 285 14-5 basic operation of 10-bit a/d converter .................................................................................... ......... 287 14-6 relationship between analog input voltage and a/d conversion result ............................................ 289 14-7 a/d conversion by hardware start (when falling edge is specified) ................................................ 290 14-8 a/d conversion by software start ........................................................................................... ............ 291 14-9 overall error.............................................................................................................. ........................... 292 14-10 quantization error ........................................................................................................ ........................ 292 14-11 zero scale error .......................................................................................................... ......................... 293 14-12 full scale error .......................................................................................................... .......................... 293 14-13 integral linearity error .................................................................................................. ....................... 293 14-14 differential linearity error .............................................................................................. ...................... 293
27 user? manual u14046ej3v0ud list of figures (5/8) figure no. title page 14-15 circuit configuration of series resistor string ........................................................................... ......... 295 14-16 a/d conversion end interrupt request generation timing ................................................................. 296 14-17 timing of reading conversion result (when conversion result is undefined) ................................. 297 14-18 av dd pin connection ................................................................................................................ ........... 297 14-19 example of connecting capacitor to av ref pin ................................................................................... 298 14-20 internal equivalent circuit of pins ani0 to ani7 .......................................................................... ........ 298 14-21 example of connection if signal source impedance is high .............................................................. 299 16-1 block diagram of serial interface uart0 .................................................................................... ........ 302 16-2 block diagram of baud rate generator ....................................................................................... ....... 302 16-3 format of asynchronous serial interface status register 0 (asis0) .................................................. 304 16-4 format of asynchronous serial interface mode register 0 (asim0) ................................................... 306 16-5 format of baud rate generator control register 0 (brgc0) ............................................................ 308 16-6 format of port mode register 2 (pm2) ....................................................................................... ......... 309 16-7 error tolerance (when k = 0), including sampling errors ................................................................... 3 15 16-8 example of transmit/receive data format in asynchronous serial interface .................................... 316 16-9 timing of asynchronous serial interface transmit completion interrupt request ............................... 318 16-10 timing of asynchronous serial interface receive completion interrupt request ............................... 319 16-11 receive error timing ...................................................................................................... ..................... 320 16-12 data format comparison between infrared data transfer mode and uart mode ............................ 326 17-1 block diagram of serial interface sio3n .................................................................................... ......... 329 17-2 format of serial operation mode register 30 (csim30) ..................................................................... 33 2 17-3 format of serial operation mode register 31 (csim31) ..................................................................... 33 3 17-4 format of port mode register 2 (pm2) ....................................................................................... ......... 334 17-5 format of port mode register 3 (pm3) ....................................................................................... ......... 334 17-6 timing of 3-wire serial i/o mode ........................................................................................... .............. 338 18-1 block diagram of serial interface iic0 ..................................................................................... ............ 341 18-2 serial bus configuration example using i 2 c bus ............................................................................... 342 18-3 format of iic shift register 0 (iic0) ...................................................................................... .............. 343 18-4 format of slave address register 0 (sva0) .................................................................................. ...... 343 18-5 format of iic control register 0 (iicc0) ................................................................................... .......... 346 18-6 format of iic status register 0 (iics0) .................................................................................... ........... 350 18-7 format of iic transfer clock select register 0 (iiccl0) .................................................................... . 353 18-8 format of port mode register 3 (pm3) ....................................................................................... ......... 354 18-9 pin configuration diagram .................................................................................................. ................. 355 18-10 i 2 c bus serial data transfer timing .............................................................................................. ...... 356 18-11 start conditions .......................................................................................................... ......................... 356 18-12 address ................................................................................................................... ............................. 357 18-13 transfer direction specification .......................................................................................... ................. 357
28 user? manual u14046ej3v0ud list of figures (6/8) figure no. title page 18-14 ack signal................................................................................................................ ........................... 358 18-15 stop condition ............................................................................................................ ......................... 359 18-16 wait signal ............................................................................................................... ............................ 360 18-17 arbitration timing example ................................................................................................ .................. 364 18-18 communication reservation timing .......................................................................................... .......... 367 18-19 timing for accepting communication reservations ........................................................................... . 367 18-20 communication reservation protocol ........................................................................................ ......... 368 18-21 master operation flowchart ................................................................................................ ................ 369 18-22 slave operation flowchart ................................................................................................. ................. 375 18-23 example of master to slave communication (when 9-clock wait is selected for both master and slave) .............................................................. 396 18-24 example of slave to master communication (when 9-clock wait is selected for both master and slave) .............................................................. 399 19-1 basic configuration of interrupt function .................................................................................. .......... 404 19-2 format of interrupt request flag registers (if0l, if0h, if1l) ........................................................... 407 19-3 format of interrupt mask flag registers (mk0l, mk0h, mk1l) ......................................................... 408 19-4 format of priority specification flag registers (pr0l, pr0h, pr1l) ................................................. 409 19-5 format of external interrupt rising edge enable register (egp), external interrupt falling edge enable register (egn) ...................................................................... 410 19-6 program status word format ................................................................................................. ............. 411 19-7 non-maskable interrupt request generation to acknowledge flowchart ........................................... 413 19-8 non-maskable interrupt request acknowledge timing ....................................................................... 413 19-9 non-maskable interrupt request acknowledge operation .................................................................. 414 19-10 interrupt request acknowledge processing algorithm ........................................................................ 416 19-11 interrupt request acknowledge timing (minimum time) .................................................................... 417 19-12 interrupt request acknowledge timing (maximum time) ................................................................... 417 19-13 nesting examples .......................................................................................................... ...................... 419 19-14 interrupt request hold .................................................................................................... ..................... 421 20-1 memory map when using external device expansion function ........................................................ 423 20-2 format of memory expansion mode register (mem) .......................................................................... 425 20-3 format of memory expansion wait setting register (mm) .................................................................. 426 20-4 instruction fetch from external memory ..................................................................................... ......... 428 20-5 external memory read timing ................................................................................................ ............ 429 20-6 external memory write timing ............................................................................................... .............. 430 20-7 external memory read modify write timing ................................................................................... ..... 431 20-8 connection example of pd780024a and memory ............................................................................ 432 21-1 format of oscillation stabilization time select register (osts) ........................................................ 434 21-2 halt mode release by interrupt request generation ....................................................................... 436
29 user? manual u14046ej3v0ud list of figures (7/8) figure no. title page 21-3 halt mode release by reset input ........................................................................................... ...... 437 21-4 stop mode release by interrupt request generation ....................................................................... 439 21-5 stop mode release by reset input ........................................................................................... ..... 440 22-1 reset function block diagram ............................................................................................... ............. 441 22-2 timing of reset by reset input ............................................................................................. ............ 442 22-3 timing of reset due to watchdog timer overflow ............................................................................. . 442 22-4 timing of reset in stop mode by reset input ................................................................................ . 442 23-1 format of memory size switching register (ims) ............................................................................. .. 450 23-2 environment for writing program to flash memory ............................................................................ . 451 23-3 communication mode selection format ........................................................................................ ...... 453 23-4 example of connection with dedicated flash programmer ................................................................ 454 23-5 v pp pin connection example ........................................................................................................ ....... 457 23-6 signal conflict (input pin of serial interface) ............................................................................ ........... 458 23-7 abnormal operation of other device ......................................................................................... .......... 458 23-8 signal conflict (reset pin) ................................................................................................ ................ 459 23-9 example of wiring adapter for flash memory writing in 3-wire serial i/o (sio30) mode .................. 460 23-10 example of wiring adapter for flash memory writing in 3-wire serial i/o (sio31) mode ( pd78f0034a, 78f0034b only) ..................................................................................................... .... 462 23-11 example of wiring adapter for flash memory writing in 3-wire serial i/o (sio30 + hs) mode ( pd78f0034b, 78f0034by only) .................................................................................................... .. 464 23-12 example of wiring adapter for flash memory writing in i 2 c bus (iic0) mode ( pd78f0034ay, 78f0034by only) ................................................................................................... .. 466 23-13 example of wiring adapter for flash memory writing in uart (uart0) mode .................................. 468 23-14 example of wiring adapter for flash memory writing in pseudo 3-wire serial i/o mode ................... 470 b-1 development tool configuration .............................................................................................. ............ 565 b-2 ev-9200gc-64 package drawing (for reference only) ...................................................................... 575 b-3 ev-9200gc-64 recommended board mounting pattern (for reference only) .................................. 576 b-4 tgc-064sap package drawing (for reference only) ........................................................................ 577 b-5 tgk-064sbw package drawing (for reference only) ....................................................................... 578 b-6 tgb-064sdp package drawing (for reference only) ........................................................................ 579 c-1 distance between in-circuit emulator and conversion adapter (when using 64cw) ....................... 582 c-2 connection conditions of target system (when using np-64cw) ..................................................... 582 c-3 connection conditions of target system (when using np-h64cw) .................................................. 583 c-4 distance between in-circuit emulator and conversion adapter (when using 64gc) ........................ 584 c-5 connection conditions of target system (when using np-64gc-tq) ............................................... 584 c-6 connection conditions of target system (when using np-h64gc-tq) ............................................ 585
30 user? manual u14046ej3v0ud list of figures (8/8) figure no. title page c-7 distance between in-circuit emulator and conversion adapter (when using 64gk) ........................ 586 c-8 connection conditions of target system (when using np-64gk) ..................................................... 586 c-9 connection conditions of target system (when using np-h64gk-tq) ............................................. 587 c-10 distance between in-circuit emulator and conversion adapter (when using 64gb) ........................ 588 c-11 connection conditions of target system (when using np-64gb-tq) ............................................... 588 c-12 connection conditions of target system (when using np-h64gb-tq) ............................................. 589 c-13 distance between in-circuit emulator and conversion socket (when using np-73f1-cn3) ............ 590 c-14 connection conditions of target system (when using np-73f1-cn3) .............................................. 590
31 user? manual u14046ej3v0ud list of tables (1/3) table no. title page 1-1 correspondence between mask rom versions and flash memory versions .................................... 54 1-2 differences between standard grade products and special grade products .................................... 54 1-3 correspondence between products and packages ............................................................................ 55 1-4 mask options of mask rom versions ........................................................................................... ...... 55 2-1 correspondence between mask rom versions and flash memory versions .................................... 74 2-2 differences between standard grade products and special grade products .................................... 75 2-3 correspondence between products and packages ............................................................................ 75 2-4 mask options of mask rom versions ........................................................................................... ...... 76 3-1 pin i/o circuit types ....................................................................................................... ..................... 85 4-1 pin i/o circuit types ....................................................................................................... ..................... 97 5-1 internal rom capacity ....................................................................................................... ................. 106 5-2 vector table ................................................................................................................ ......................... 107 5-3 internal high-speed ram capacity ............................................................................................ ......... 108 5-4 internal high-speed ram area ................................................................................................ ........... 115 5-5 special function register list .............................................................................................. ............... 120 6-1 port functions ( pd780024a, 780034a subseries) ............................................................................ 137 6-2 port functions ( pd780024ay, 780034ay subseries) ........................................................................ 138 6-3 port configuration .......................................................................................................... ...................... 139 6-4 pull-up resistor of port 3 ( pd780024a, 780034a subseries) .......................................................... 145 6-5 pull-up resistor of port 3 ( pd780024ay, 780034ay subseries) ...................................................... 150 6-6 port mode registers and output latch settings when alternate function is used ............................ 163 6-7 comparison between mask rom version and flash memory version ............................................... 168 7-1 clock generator configuration ............................................................................................... ............. 169 7-2 relationship between cpu clock and minimum instruction execution time ...................................... 173 7-3 maximum time required for cpu clock switchover .......................................................................... 182 8-1 configuration of 16-bit timer/event counter 0 ............................................................................... ..... 185 8-2 cr00 capture trigger and valid edges of ti00 and ti01 pins ........................................................... 186 8-3 cr01 capture trigger and valid edge of ti00 pin (crc02 = 1) ......................................................... 187 9-1 configuration of 8-bit timer/event counters 50, 51 .......................................................................... .. 221 10-1 watch timer configuration .................................................................................................. ................ 243 10-2 interval timer interval time ............................................................................................... .................. 245
32 user? manual u14046ej3v0ud list of tables (2/3) table no. title page 11-1 watchdog timer configuration ............................................................................................... ............. 248 11-2 watchdog timer loop detection time ......................................................................................... ........ 250 11-3 interval timer interval time ............................................................................................... .................. 251 12-1 configuration of clock output/buzzer output controller ..................................................................... 253 13-1 a/d converter configuration ................................................................................................ ................ 259 13-2 sampling time and a/d conversion start delay time of a/d converter ............................................. 266 13-3 resistances and capacitances of equivalent circuit (reference values) ........................................... 278 14-1 a/d converter configuration ................................................................................................ ................ 281 14-2 sampling time and a/d conversion start delay time of a/d converter ............................................. 288 14-3 resistances and capacitances of equivalent circuit (reference values) ........................................... 299 15-1 differences between pd780024a, 780034a subseries and pd780024ay, 780034ay subseries ................................................................................................. . 300 16-1 configuration of serial interface uart0 .................................................................................... .......... 303 16-2 relationship between main system clock and baud rate error ........................................................ 314 16-3 causes of receive errors ................................................................................................... ................. 320 16-4 relationship between main system clock and baud rate ................................................................. 326 16-5 bit rate and pulse width values ............................................................................................ ............. 326 16-6 register settings .......................................................................................................... ....................... 328 17-1 configuration of serial interface sio3n .................................................................................... ........... 330 17-2 register settings .......................................................................................................... ....................... 339 18-1 configuration of serial interface iic0 ..................................................................................... .............. 343 18-2 intiic0 timing and wait control ............................................................................................ ............. 362 18-3 extension code bit definitions ............................................................................................. ............... 363 18-4 status during arbitration and interrupt request generation timing .................................................... 365 18-5 wait periods ............................................................................................................... .......................... 366 19-1 interrupt source list ...................................................................................................... ...................... 403 19-2 flags corresponding to interrupt request sources ........................................................................... . 406 19-3 times from generation of maskable interrupt until servicing ............................................................. 415 19-4 interrupt requests enabled for nesting during interrupt servicing ..................................................... 418 20-1 pin functions in external memory expansion mode ........................................................................... 4 22 20-2 state of port 4 to 6 pins in external memory expansion mode ........................................................... 422
33 user? manual u14046ej3v0ud list of tables (3/3) table no. title page 21-1 halt mode operating statuses .............................................................................................. ........... 435 21-2 operation after halt mode release ......................................................................................... ......... 437 21-3 stop mode operating statuses .............................................................................................. .......... 438 21-4 operation after stop mode release ......................................................................................... ........ 440 22-1 hardware statuses after reset .............................................................................................. ............. 443 23-1 correspondence between pd78f0034a, 78f0034b, 78f0034ay, 78f0034by, and mask rom versions .......................................................................................................... ........... 445 23-2 differences between pd78f0034a and pd78f0034b .................................................................... 446 23-3 differences between pd78f0034ay and pd78f0034by ............................................................... 447 23-4 differences between pd78f0034b, 78f0034by and pd78f0034b(a), 78f0034by(a) ................ 447 23-5 differences between pd78f0034a, 78f0034b and mask rom versions ........................................ 448 23-6 differences between pd78f0034ay, 78f0034by and mask rom versions .................................... 449 23-7 memory size switching register settings .................................................................................... ....... 450 23-8 communication mode list .................................................................................................... ............... 452 23-9 pin connection list ........................................................................................................ ...................... 456 24-1 operand identifiers and specification methods .............................................................................. ..... 473 28-1 surface mounting type soldering conditions ................................................................................. ..... 556 28-2 insertion type soldering conditions ........................................................................................ ............ 560 a-1 major differences between pd78018f, 780024a, 780034a, and 780078 subseries (hardware) .... 561 a-2 major differences between pd78018f, 780024a, 780034a, and 780078 subseries (software) ..... 562 b-1 system upgrade method from former in-circuit emulator for 78k/0 series to ie-78001-r-a ............ 574 c-1 distance between ie system and conversion adapter ....................................................................... 581
34 user? manual u14046ej3v0ud chapter 1 outline ( pd780024a, 780034a subseries) 1.1 expanded-specification products and conventional products the expanded-specification products and conventional products refer to the following products. expanded-specification products: pd780021a, 780022a, 780023a, 780024a, 780031a, 780032a, 780033a, 780034a for which orders were received after december 1, 2001 (products with a rank note other than k, e, p, x) pd78f0034b conventional products: products other than the above expanded-specification products (products with rank note k, e, p, x) pd78f0034a note the rank is indicated by the 5th digit from the left in the lot number marked on the package. lot number year code rank week code expanded-specification products and conventional products differ in the operating frequency ratings. power supply voltage (v dd ) guaranteed operating speed (operating frequency) conventional products expanded-specification products 4.5 to 5.5 v 8.38 mhz (0.238 s) 12 mhz (0.166 s) 4.0 to 5.5 v 8.38 mhz (0.238 s) 8.38 mhz (0.238 s) 3.0 to 5.5 v 5 mhz (0.4 s) 8.38 mhz (0.238 s) 2.7 to 5.5 v 5 mhz (0.4 s) 5 mhz (0.4 s) 1.8 to 5.5 v 1.25 mhz (1.6 s) 1.25 mhz (1.6 s) remark the parenthesized values indicate the minimum instruction execution time. caution only the conventional products are available in the pd780024ay and 780034ay subseries ( pd780021ay, 780022ay, 780023ay, 780024ay, 780031ay, 780032ay, 780033ay, 780034ay, 78f0034ay, 78f0034by).
35 chapter 1 outline ( pd780024a, 780034a subseries) user s manual u14046ej3v0ud 1.2 features internal memory type program memory data memory part number (rom/flash memory) (high-speed ram) pd780021a, 780031a 8 kb 512 bytes pd780022a, 780032a 16 kb pd780023a, 780033a 24 kb 1024 bytes pd780024a, 780034a 32 kb pd78f0034a, 78f0034b 32 kb note 1024 bytes note note the capacities of internal flash memory and internal high-speed ram can be changed by means of the memory size switching register (ims). external memory expansion space: 64 kb minimum instruction execution time changeable from high speed (expanded-specification product (0.166 s: @12 mhz operation with main system clock), conventional product (0.238 s: @ 8.38 mhz operation with main system clock)) to ultra-low speed (122 s: @ 32.768 khz operation with subsystem clock) instruction set suited to system control bit manipulation possible in all address spaces multiply and divide instructions fifty-one i/o ports: (four n-ch open-drain ports) 8-bit resolution a/d converter: 8 channels ( pd780024a subseries only) 10-bit resolution a/d converter: 8 channels ( pd780034a subseries only) serial interface: 3 channels 3-wire serial i/o mode: 2 channels uart mode: 1 channel timer: five channels 16-bit timer/event counter: 1 channel 8-bit timer/event counter: 2 channels watch timer: 1 channel watchdog timer: 1 channel vectored interrupt sources: 20 two types of on-chip clock oscillators (main system clock and subsystem clock) power supply voltage: v dd = 1.8 to 5.5 v
36 chapter 1 outline ( pd780024a, 780034a subseries) user s manual u14046ej3v0ud 1.3 applications pd780021a, 780022a, 780023a, 780024a pd780031a, 780032a, 780033a, 780034a, 78f0034a, 78f0034b home electric appliances, pagers, av equipment, car audios, car electric equipment, office automation equipment, etc. pd780021a(a), 780022a(a), 780023a(a), 780024a(a) pd780031a(a), 780032a(a), 780033a(a), 780034a(a), 78f0034b(a) control of transportation equipment, gas detection breakers, safety devices, etc.
37 chapter 1 outline ( pd780024a, 780034a subseries) user s manual u14046ej3v0ud 1.4 ordering information (1) pd780024a subseries (1/2) part number package internal rom pd780021acw- 64-pin plastic sdip (19.05 mm (750)) mask rom pd780021agc- -ab8 64-pin plastic qfp (14 14) mask rom pd780021agc- -8bs 64-pin plastic lqfp (14 14) mask rom pd780021agk- -9et 64-pin plastic tqfp (12 12) mask rom pd780021agb- -8eu 64-pin plastic lqfp (10 10) mask rom pd780021af1- -cn3 73-pin plastic fbga (9 9) mask rom pd780022acw- 64-pin plastic sdip (19.05 mm (750)) mask rom pd780022agc- -ab8 64-pin plastic qfp (14 14) mask rom pd780022agc- -8bs 64-pin plastic lqfp (14 14) mask rom pd780022agk- -9et 64-pin plastic tqfp (12 12) mask rom pd780022agb- -8eu 64-pin plastic lqfp (10 10) mask rom pd780022af1- -cn3 73-pin plastic fbga (9 9) mask rom pd780023acw- 64-pin plastic sdip (19.05 mm (750)) mask rom pd780023agc- -ab8 64-pin plastic qfp (14 14) mask rom pd780023agc- -8bs 64-pin plastic lqfp (14 14) mask rom pd780023agk- -9et 64-pin plastic tqfp (12 12) mask rom pd780023agb- -8eu 64-pin plastic lqfp (10 10) mask rom pd780023af1- -cn3 73-pin plastic fbga (9 9) mask rom pd780024acw- 64-pin plastic sdip (19.05 mm (750)) mask rom pd780024agc- -ab8 64-pin plastic qfp (14 14) mask rom pd780024agc- -8bs 64-pin plastic lqfp (14 14) mask rom pd780024agk- -9et 64-pin plastic tqfp (12 12) mask rom pd780024agb- -8eu 64-pin plastic lqfp (10 10) mask rom pd780024af1- -cn3 73-pin plastic fbga (9 9) mask rom remark indicates rom code suffix.
38 chapter 1 outline ( pd780024a, 780034a subseries) user s manual u14046ej3v0ud (1) pd780024a subseries (2/2) part number package internal rom pd780021acw(a)- 64-pin plastic sdip (19.05 mm (750)) mask rom pd780021agc(a)- -ab8 64-pin plastic qfp (14 14) mask rom pd780021agc(a)- -8bs 64-pin plastic lqfp (14 14) mask rom pd780021agk(a)- -9et 64-pin plastic tqfp (12 12) mask rom pd780021agb(a)- -8eu note 64-pin plastic lqfp (10 10) mask rom pd780022acw(a)- 64-pin plastic sdip (19.05 mm (750)) mask rom pd780022agc(a)- -ab8 64-pin plastic qfp (14 14) mask rom pd780022agc(a)- -8bs 64-pin plastic lqfp (14 14) mask rom pd780022agk(a)- -9et 64-pin plastic tqfp (12 12) mask rom pd780022agb(a)- -8eu note 64-pin plastic lqfp (10 10) mask rom pd780023acw(a)- 64-pin plastic sdip (19.05 mm (750)) mask rom pd780023agc(a)- -ab8 64-pin plastic qfp (14 14) mask rom pd780023agc(a)- -8bs 64-pin plastic lqfp (14 14) mask rom pd780023agk(a)- -9et 64-pin plastic tqfp (12 12) mask rom pd780023agb(a)- -8eu note 64-pin plastic lqfp (10 10) mask rom pd780024acw(a)- 64-pin plastic sdip (19.05 mm (750)) mask rom pd780024agc(a)- -ab8 64-pin plastic qfp (14 14) mask rom pd780024agc(a)- -8bs 64-pin plastic lqfp (14 14) mask rom pd780024agk(a)- -9et 64-pin plastic tqfp (12 12) mask rom pd780024agb(a)- -8eu note 64-pin plastic lqfp (10 10) mask rom note under development remark indicates rom code suffix.
39 chapter 1 outline ( pd780024a, 780034a subseries) user s manual u14046ej3v0ud (2) pd780034a subseries (1/2) part number package internal rom pd780031acw- 64-pin plastic sdip (19.05 mm (750)) mask rom pd780031agc- -ab8 64-pin plastic qfp (14 14) mask rom pd780031agc- -8bs 64-pin plastic lqfp (14 14) mask rom pd780031agk- -9et 64-pin plastic tqfp (12 12) mask rom pd780031agb- -8eu 64-pin plastic lqfp (10 10) mask rom pd780031af1- -cn3 73-pin plastic fbga (9 9) mask rom pd780032acw- 64-pin plastic sdip (19.05 mm (750)) mask rom pd780032agc- -ab8 64-pin plastic qfp (14 14) mask rom pd780032agc- -8bs 64-pin plastic lqfp (14 14) mask rom pd780032agk- -9et 64-pin plastic tqfp (12 12) mask rom pd780032agb- -8eu 64-pin plastic lqfp (10 10) mask rom pd780032af1- -cn3 73-pin plastic fbga (9 9) mask rom pd780033acw- 64-pin plastic sdip (19.05 mm (750)) mask rom pd780033agc- -ab8 64-pin plastic qfp (14 14) mask rom pd780033agc- -8bs 64-pin plastic lqfp (14 14) mask rom pd780033agk- -9et 64-pin plastic tqfp (12 12) mask rom pd780033agb- -8eu 64-pin plastic lqfp (10 10) mask rom pd780033af1- -cn3 73-pin plastic fbga (9 9) mask rom pd780034acw- 64-pin plastic sdip (19.05 mm (750)) mask rom pd780034agc- -ab8 64-pin plastic qfp (14 14) mask rom pd780034agc- -8bs 64-pin plastic lqfp (14 14) mask rom pd780034agk- -9et 64-pin plastic tqfp (12 12) mask rom pd780034agb- -8eu 64-pin plastic lqfp (10 10) mask rom pd780034af1- -cn3 73-pin plastic fbga (9 9) mask rom pd78f0034acw 64-pin plastic sdip (19.05 mm (750)) flash memory pd78f0034agc-ab8 note 64-pin plastic qfp (14 14) flash memory pd78f0034agc-8bs 64-pin plastic lqfp (14 14) flash memory pd78f0034agk-9et 64-pin plastic tqfp (12 12) flash memory pd78f0034agb-8eu 64-pin plastic lqfp (10 10) flash memory pd78f0034bgc-8bs 64-pin plastic lqfp (14 14) flash memory pd78f0034bgk-9et 64-pin plastic tqfp (12 12) flash memory pd78f0034bgb-8eu 64-pin plastic lqfp (10 10) flash memory pd78f0034bf1-cn3 73-pin plastic fbga (9 9) flash memory note maintenance product remark indicates rom code suffix.
40 chapter 1 outline ( pd780024a, 780034a subseries) user s manual u14046ej3v0ud (2) pd780034a subseries (2/2) part number package internal rom pd780031acw(a)- 64-pin plastic sdip (19.05 mm (750)) mask rom pd780031agc(a)- -ab8 64-pin plastic qfp (14 14) mask rom pd780031agc(a)- -8bs 64-pin plastic lqfp (14 14) mask rom pd780031agk(a)- -9et 64-pin plastic tqfp (12 12) mask rom pd780031agb(a)- -8eu note 64-pin plastic lqfp (10 10) mask rom pd780032acw(a)- 64-pin plastic sdip (19.05 mm (750)) mask rom pd780032agc(a)- -ab8 64-pin plastic qfp (14 14) mask rom pd780032agc(a)- -8bs 64-pin plastic lqfp (14 14) mask rom pd780032agk(a)- -9et 64-pin plastic tqfp (12 12) mask rom pd780032agb(a)- -8eu note 64-pin plastic lqfp (10 10) mask rom pd780033acw(a)- 64-pin plastic sdip (19.05 mm (750)) mask rom pd780033agc(a)- -ab8 64-pin plastic qfp (14 14) mask rom pd780033agc(a)- -8bs 64-pin plastic lqfp (14 14) mask rom pd780033agk(a)- -9et 64-pin plastic tqfp (12 12) mask rom pd780033agb(a)- -8eu note 64-pin plastic lqfp (10 10) mask rom pd780034acw(a)- 64-pin plastic sdip (19.05 mm (750)) mask rom pd780034agc(a)- -ab8 64-pin plastic qfp (14 14) mask rom pd780034agc(a)- -8bs 64-pin plastic lqfp (14 14) mask rom pd780034agk(a)- -9et 64-pin plastic tqfp (12 12) mask rom pd780034agb(a)- -8eu note 64-pin plastic lqfp (10 10) mask rom pd78f0034bgc(a)-8bs 64-pin plastic lqfp (14 14) flash memory pd78f0034bgk(a)-9et 64-pin plastic tqfp (12 12) flash memory pd78f0034bgb(a)-8eu 64-pin plastic lqfp (10 10) flash memory note under development remark indicates rom code suffix.
41 chapter 1 outline ( pd780024a, 780034a subseries) user s manual u14046ej3v0ud 1.5 quality grade (1) pd780024a subseries (1/2) part number package quality grades pd780021acw- 64-pin plastic sdip (19.05 mm (750)) standard pd780021agc- -ab8 64-pin plastic qfp (14 14) standard pd780021agc- -8bs 64-pin plastic lqfp (14 14) standard pd780021agk- -9et 64-pin plastic tqfp (12 12) standard pd780021agb- -8eu 64-pin plastic lqfp (10 10) standard pd780021af1- -cn3 73-pin plastic fbga (9 9) standard pd780022acw- 64-pin plastic sdip (19.05 mm (750)) standard pd780022agc- -ab8 64-pin plastic qfp (14 14) standard pd780022agc- -8bs 64-pin plastic lqfp (14 14) standard pd780022agk- -9et 64-pin plastic tqfp (12 12) standard pd780022agb- -8eu 64-pin plastic lqfp (10 10) standard pd780022af1- -cn3 73-pin plastic fbga (9 9) standard pd780023acw- 64-pin plastic sdip (19.05 mm (750)) standard pd780023agc- -ab8 64-pin plastic qfp (14 14) standard pd780023agc- -8bs 64-pin plastic lqfp (14 14) standard pd780023agk- -9et 64-pin plastic tqfp (12 12) standard pd780023agb- -8eu 64-pin plastic lqfp (10 10) standard pd780023af1- -cn3 73-pin plastic fbga (9 9) standard pd780024acw- 64-pin plastic sdip (19.05 mm (750)) standard pd780024agc- -ab8 64-pin plastic qfp (14 14) standard pd780024agc- -8bs 64-pin plastic lqfp (14 14) standard pd780024agk- -9et 64-pin plastic tqfp (12 12) standard pd780024agb- -8eu 64-pin plastic lqfp (10 10) standard pd780024af1- -cn3 73-pin plastic fbga (9 9) standard remark indicates rom code suffix. please refer to "quality grades on nec semiconductor devices" (document no. c11531e) published by nec electronics corporation to know the specification of the quality grade on the device and its recommended applications.
42 chapter 1 outline ( pd780024a, 780034a subseries) user s manual u14046ej3v0ud (1) pd780024a subseries (2/2) part number package quality grades pd780021acw(a)- 64-pin plastic sdip (19.05 mm (750)) special pd780021agc(a)- -ab8 64-pin plastic qfp (14 14) special pd780021agc(a)- -8bs 64-pin plastic lqfp (14 14) special pd780021agk(a)- -9et 64-pin plastic tqfp (12 12) special pd780021agb(a)- -8eu note 64-pin plastic lqfp (10 10) special pd780022acw(a)- 64-pin plastic sdip (19.05 mm (750)) special pd780022agc(a)- -ab8 64-pin plastic qfp (14 14) special pd780022agc(a)- -8bs 64-pin plastic lqfp (14 14) special pd780022agk(a)- -9et 64-pin plastic tqfp (12 12) special pd780022agb(a)- -8eu note 64-pin plastic lqfp (10 10) special pd780023acw(a)- 64-pin plastic sdip (19.05 mm (750)) special pd780023agc(a)- -ab8 64-pin plastic qfp (14 14) special pd780023agc(a)- -8bs 64-pin plastic lqfp (14 14) special pd780023agk(a)- -9et 64-pin plastic tqfp (12 12) special pd780023agb(a)- -8eu note 64-pin plastic lqfp (10 10) special pd780024acw(a)- 64-pin plastic sdip (19.05 mm (750)) special pd780024agc(a)- -ab8 64-pin plastic qfp (14 14) special pd780024agc(a)- -8bs 64-pin plastic lqfp (14 14) special pd780024agk(a)- -9et 64-pin plastic tqfp (12 12) special pd780024agb(a)- -8eu note 64-pin plastic lqfp (10 10) special note under development remark indicates rom code suffix. please refer to "quality grades on nec semiconductor devices" (document no. c11531e) published by nec electronics corporation to know the specification of the quality grade on the device and its recommended applications.
43 chapter 1 outline ( pd780024a, 780034a subseries) user s manual u14046ej3v0ud (2) pd780034a subseries (1/2) part number package quality grades pd780031acw- 64-pin plastic sdip (19.05 mm (750)) standard pd780031agc- -ab8 64-pin plastic qfp (14 14) standard pd780031agc- -8bs 64-pin plastic lqfp (14 14) standard pd780031agk- -9et 64-pin plastic tqfp (12 12) standard pd780031agb- -8eu 64-pin plastic lqfp (10 10) standard pd780031af1- -cn3 73-pin plastic fbga (9 9) standard pd780032acw- 64-pin plastic sdip (19.05 mm (750)) standard pd780032agc- -ab8 64-pin plastic qfp (14 14) standard pd780032agc- -8bs 64-pin plastic lqfp (14 14) standard pd780032agk- -9et 64-pin plastic tqfp (12 12) standard pd780032agb- -8eu 64-pin plastic lqfp (10 10) standard pd780032af1- -cn3 73-pin plastic fbga (9 9) standard pd780033acw- 64-pin plastic sdip (19.05 mm (750)) standard pd780033agc- -ab8 64-pin plastic qfp (14 14) standard pd780033agc- -8bs 64-pin plastic lqfp (14 14) standard pd780033agk- -9et 64-pin plastic tqfp (12 12) standard pd780033agb- -8eu 64-pin plastic lqfp (10 10) standard pd780033af1- -cn3 73-pin plastic fbga (9 9) standard pd780034acw- 64-pin plastic sdip (19.05 mm (750)) standard pd780034agc- -ab8 64-pin plastic qfp (14 14) standard pd780034agc- -8bs 64-pin plastic lqfp (14 14) standard pd780034agk- -9et 64-pin plastic tqfp (12 12) standard pd780034agb- -8eu 64-pin plastic lqfp (10 10) standard pd780034af1- -cn3 73-pin plastic fbga (9 9) standard pd78f0034acw 64-pin plastic sdip (19.05 mm (750)) standard pd78f0034agc-ab8 note 64-pin plastic qfp (14 14) standard pd78f0034agc-8bs 64-pin plastic lqfp (14 14) standard pd78f0034agk-9et 64-pin plastic tqfp (12 12) standard pd78f0034agb-8eu 64-pin plastic lqfp (10 10) standard pd78f0034bgc-8bs 64-pin plastic lqfp (14 14) standard pd78f0034bgk-9et 64-pin plastic tqfp (12 12) standard pd78f0034bgb-8eu 64-pin plastic lqfp (10 10) standard pd78f0034bf1-cn3 73-pin plastic fbga (9 9) standard note maintenance product remark indicates rom code suffix. please refer to "quality grades on nec semiconductor devices" (document no. c11531e) published by nec electronics corporation to know the specification of the quality grade on the device and its recommended applications.
44 chapter 1 outline ( pd780024a, 780034a subseries) user s manual u14046ej3v0ud (2) pd780034a subseries (2/2) part number package quality grades pd780031acw(a)- 64-pin plastic sdip (19.05 mm (750)) special pd780031agc(a)- -ab8 64-pin plastic qfp (14 14) special pd780031agc(a)- -8bs 64-pin plastic lqfp (14 14) special pd780031agk(a)- -9et 64-pin plastic tqfp (12 12) special pd780031agb(a)- -8eu note 64-pin plastic lqfp (10 10) special pd780032acw(a)- 64-pin plastic sdip (19.05 mm (750)) special pd780032agc(a)- -ab8 64-pin plastic qfp (14 14) special pd780032agc(a)- -8bs 64-pin plastic lqfp (14 14) special pd780032agk(a)- -9et 64-pin plastic tqfp (12 12) special pd780032agb(a)- -8eu note 64-pin plastic lqfp (10 10) special pd780033acw(a)- 64-pin plastic sdip (19.05 mm (750)) special pd780033agc(a)- -ab8 64-pin plastic qfp (14 14) special pd780033agc(a)- -8bs 64-pin plastic lqfp (14 14) special pd780033agk(a)- -9et 64-pin plastic tqfp (12 12) special pd780033agb(a)- -8eu note 64-pin plastic lqfp (10 10) special pd780034acw(a)- 64-pin plastic sdip (19.05 mm (750)) special pd780034agc(a)- -ab8 64-pin plastic qfp (14 14) special pd780034agc(a)- -8bs 64-pin plastic lqfp (14 14) special pd780034agk(a)- -9et 64-pin plastic tqfp (12 12) special pd780034agb(a)- -8eu note 64-pin plastic lqfp (10 10) special pd78f0034bgc(a)-8bs 64-pin plastic lqfp (14 14) special pd78f0034bgk(a)-9et 64-pin plastic tqfp (12 12) special pd78f0034bgb(a)-8eu 64-pin plastic lqfp (10 10) special note under development remark indicates rom code suffix. please refer to "quality grades on nec semiconductor devices" (document no. c11531e) published by nec electronics corporation to know the specification of the quality grade on the device and its recommended applications.
45 chapter 1 outline ( pd780024a, 780034a subseries) user s manual u14046ej3v0ud 1.6 pin configuration (top view) 64-pin plastic sdip (19.05 mm (750)) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 p40/ad0 p41/ad1 p42/ad2 p43/ad3 p44/ad4 p45/ad5 p46/ad6 p47/ad7 p50/a8 p51/a9 p52/a10 p53/a11 p54/a12 p55/a13 p56/a14 p57/a15 v ss0 v dd0 p30 p31 p32 p33 p34/si31 p35/so31 p36/sck31 p20/si30 p21/so30 p22/sck30 p23/rxd0 p24/txd0 p25/asck0 v dd1 p67/astb p66/wait p65/wr p64/rd p75/buz p74/pcl p73/ti51/to51 p72/ti50/to50 p71/ti01 p70/ti00/to0 p03/intp3/adtrg p02/intp2 p01/intp1 p00/intp0 v ss1 x1 x2 ic (v pp ) xt1 xt2 reset av dd av ref p10/ani0 p11/ani1 p12/ani2 p13/ani3 p14/ani4 p15/ani5 p16/ani6 p17/ani7 av ss 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 cautions 1. connect the ic (internally connected) pin directly to v ss0 or v ss1 . 2. connect the av ss pin to v ss0 . remarks 1. when the pd780024a, 780034a subseries products are used in applications where the noise generated inside the microcontroller needs to be reduced, the implementation of noise reduction measures, such as supplying voltage to v dd0 and v dd1 individually and connecting v ss0 and v ss1 to different ground lines, is recommended. 2. pin connection in parentheses is intended for the pd78f0034a.
46 chapter 1 outline ( pd780024a, 780034a subseries) user s manual u14046ej3v0ud 64-pin plastic qfp (14 14) 64-pin plastic lqfp (14 14) 64-pin plastic tqfp (12 12) 64-pin plastic lqfp (10 10) cautions 1. connect the ic (internally connected) pin directly to v ss0 or v ss1 . 2. connect the av ss pin to v ss0 . remarks 1. when the pd780024a, 780034a subseries products are used in applications where the noise generated inside the microcontroller needs to be reduced, the implementation of noise reduction measures, such as supplying voltage to v dd0 and v dd1 individually and connecting v ss0 and v ss1 to different ground lines, is recommended. 2. pin connection in parentheses is intended for the pd78f0034a, 78f0034b. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 p50/a8 p51/a9 p52/a10 p53/a11 p54/a12 p55/a13 p56/a14 p57/a15 v ss0 v dd0 p30 p31 p32 p33 p34/si31 p35/so31 p71/ti01 p70/ti00/to0 p03/intp3/adtrg p02/intp2 p01/intp1 p00/intp0 v ss1 x1 x2 ic (v pp ) xt1 xt2 reset av dd av ref p10/ani0 p47/ad7 p46/ad6 p45/ad5 p44/ad4 p43/ad3 p42/ad2 p41/ad1 p40/ad0 p67/astb p66/wait p65/wr p64/rd p75/buz p74/pcl p73/ti51/to51 p72/ti50/to50 p36/sck31 p20/si30 p21/so30 p22/sck30 p23/rxd0 p24/txd0 p25/asck0 v dd1 av ss p17/ani7 p16/ani6 p15/ani5 p14/ani4 p13/ani3 p12/ani2 p11/ani1
47 chapter 1 outline ( pd780024a, 780034a subseries) user s manual u14046ej3v0ud pin no . pin name pin no . pin name pin no . pin name pin no . pin name pin no . pin name a1 nc c1 p52/a10 e1 p57/a15 g1 p33 j1 nc a2 p46/ad6 c2 p53/a11 e2 v dd0 g2 p32 j2 p36/sck31 a3 p44/ad4 c3 p45/ad5 e3 p54/a12 g3 p20/si30 j3 nc a4 p41/ad1 c4 p42/ad2 e4 ? g4 p21/so30 j4 p25/asck0 a5 p67/astb c5 p64/rd e5 ? g5 p24/txd0 j5 nc a6 p65/wr c6 p73/ti51/to51 e6 ? g6 v dd1 j6 p17/ani7 a7 p74/pcl c7 p03/intp3/adtrg e7 p00/intp0 g7 p16/ani6 j7 p12/ani2 a8 nc c8 p01/intp1 e8 xt1 g8 av dd j8 p13/ani3 a9 nc c9 v ss1 e9 x2 g9 nc j9 nc b1 p51/a9 d1 p55/a13 f1 p30 h1 p34/si31 b2 p47/ad7 d2 p56/a14 f2 p31 h2 p35/so31 b3 p43/ad3 d3 p50/a8 f3 v ss0 h3 p23/rxd0 b4 p40/ad0 d4 nc f4 ? h4 p22/sck30 b5 p66/wait d5 ? f5 ? h5 av ss b6 p75/buz d6 ? f6 ? h6 p15/ani5 b7 p72/ti50/to51 d7 p02/intp2 f7 p14/ani4 h7 p11/ani1 b8 p71/ti01 d8 ic (v pp ) f8 reset h8 p10/ani0 b9 p70/ti00/to0 d9 x1 f9 xt2 h9 av ref cautions 1. connect the ic (internally connected) pin directly to v ss0 or v ss1 . 2. connect the av ss pin to v ss0 . remarks 1. when the pd780024a, 780034a subseries products are used in applications where the noise generated inside the microcontroller needs to be reduced, the implementation of noise reduction measures, such as supplying voltage to v dd0 and v dd1 individually and connecting v ss0 and v ss1 to different ground lines, is recommended. 2. pin connection in parentheses is intended for the pd78f0034b. 73-pin plastic fbga (9 9) top view bottom view jhgfedcba abcdefghj 9 8 7 6 5 4 3 2 1 index mark
48 chapter 1 outline ( pd780024a, 780034a subseries) user s manual u14046ej3v0ud a8 to a15: address bus p64 to p67: port 6 ad0 to ad7: address/data bus p70 to p75: port 7 adtrg: ad trigger input pcl: programmable clock ani0 to ani7: analog input rd: read strobe asck0: asynchronous serial clock reset: reset astb: address strobe rxd0: receive data av dd : analog power supply sck30, sck31: serial clock av ref : analog reference voltage si30, si31: serial input av ss : analog ground so30, so31: serial output buz: buzzer clock ti00, ti01, ti50, ti51: timer input ic: internally connected to0, to50, to51: timer output intp0 to intp3: external interrupt input txd0: transmit data nc: non-connection v dd0 , v dd1 : power supply p00 to p03: port 0 v pp : programming power supply p10 to p17: port 1 v ss0 , v ss1 : ground p20 to p25: port 2 wait: wait p30 to p36: port 3 wr: write strobe p40 to p47: port 4 x1, x2: crystal (main system clock) p50 to p57: port 5 xt1, xt2: crystal (subsystem clock)
49 chapter 1 outline ( pd780024a, 780034a subseries) user? manual u14046ej3v0ud 1.7 78k/0 series lineup the products in the 78k/0 series are listed below. the names enclosed in boxes are subseries name. remark vfd (vacuum fluorescent display) is referred to as fip tm (fluorescent indicator panel) in some documents, but the functions of the two are the same. pd78083 pd78018f pd78018fy pd78014h emi-noise reduced version of the pd78018f basic subseries for control on-chip uart, capable of operating at low voltage (1.8 v) 42/44-pin 64-pin 64-pin 52-pin 52-pin version of the pd780024a pd780024as 52-pin 52-pin version of the pd780034a pd780034as pd78054 with iebus tm controller pd78054 with enhanced serial i/o pd78078y with enhanced serial i/o and limited functions pd78054 with timer and enhanced external interface 64-pin 64-pin 80-pin 80-pin 80-pin emi-noise reduced version of the pd78054 pd78018f with uart and d/a converter, and enhanced i/o pd780034a pd780988 pd780034ay 64-pin pd780024a with expanded ram pd780024a with enhanced a/d converter on-chip inverter controller and uart. emi-noise reduced. pd78064 pd78064b pd780308 100-pin 100-pin 100-pin pd780308y pd78064y 80-pin 78k/0 series lcd drive pd78064 with enhanced sio, and expanded rom and ram emi-noise reduced version of the pd78064 basic subseries for driving lcds, on-chip uart bus interface supported pd78018f with enhanced serial i/o 80-pin 100-pin 100-pin products in mass production products under development y subseries products are compatible with i 2 c bus. romless version of the pd78078 100-pin 100-pin emi-noise reduced version of the pd78078 inverter control pd780208 100-pin vfd drive pd78044f with enhanced i/o and vfd c/d. display output total: 53 pd78098b 100-pin pd780024a pd780024ay 80-pin 80-pin pd780852 pd780828b for automobile meter driver. on-chip can controller 100-pin pd780958 for industrial meter control on-chip automobile meter controller/driver meter control 80-pin on-chip iebus controller 80-pin on-chip controller compliant with j1850 (class 2) pd780833y pd780948 on-chip can controller 64-pin pd780078 pd780078y pd780034a with timer and enhanced serial i/o pd78054 pd78054y pd78058f pd78058fy pd780058 pd780058y pd78070a pd78070ay pd78078 pd78078y pd780018ay control pd78075b pd780065 pd78044h pd780232 80-pin 80-pin for panel control. on-chip vfd c/d. display output total: 53 pd78044f with n-ch open-drain i/o. display output total: 34 pd78044f 80-pin basic subseries for driving vfd. display output total: 34 120-pin pd780308 with enhanced display function and timer. segment signal output: 40 pins max. pd780318 pd780328 120-pin 120-pin pd780308 with enhanced display function and timer. segment signal output: 32 pins max. pd780308 with enhanced display function and timer. segment signal output: 24 pins max. pd780338 pd780308 with enhanced display function and timer. segment signal output: 40 pins max. on-chip can controller specialized for can controller function 80-pin pd780703ay pd780702y 64-pin pd780816 pd780344 with enhanced a/d converter 100-pin 100-pin pd780344 pd780344y pd780354 pd780354y
50 chapter 1 outline ( pd780024a, 780034a subseries) user s manual u14046ej3v0ud the major functional differences between the subseries are shown below. subseries without the suffix y function rom timer 8-bit 10-bit 8-bit serial interface i/o external subseries name capacity 8-bit 16-bit watch wdt a/d a/d d/a expansion control pd78075b 32 kb to 40 kb 4 ch 1 ch 1 ch 1 ch 8 ch 2 ch 3 ch (uart: 1 ch) 88 1.8 v yes pd78078 48 kb to 60 kb pd78070a 61 2.7 v pd780058 24 kb to 60 kb 2 ch 3 ch (time-division uart: 1 ch) 68 1.8 v pd78058f 48 kb to 60 kb 3 ch (uart: 1 ch) 69 2.7 v pd78054 16 kb to 60 kb 2.0 v pd780065 40 kb to 48 kb 4 ch (uart: 1 ch) 60 2.7 v pd780078 48 kb to 60 kb 2 ch 8 ch 3 ch (uart: 2 ch) 52 1.8 v pd780034a 8 kb to 32 kb 1 ch 3 ch (uart: 1 ch) 51 pd780024a 8 ch pd780034as 4 ch 39 pd780024as 4 ch pd78014h 8 ch 2 ch 53 yes pd78018f 8 kb to 60 kb pd78083 8 kb to 16 kb 1 ch (uart: 1 ch) 33 inverter pd780988 16 kb to 60 kb 3 ch note 1 ch 8 ch 3 ch (uart: 2 ch) 47 4.0 v yes control vfd pd780208 32 kb to 60 kb 2 ch 1 ch 1 ch 1 ch 8 ch 2 ch 74 2.7 v drive pd780232 16 kb to 24 kb 3 ch 4 ch 40 4.5 v pd78044h 32 kb to 48 kb 2 ch 1 ch 1 ch 8 ch 1 ch 68 2.7 v pd78044f 16 kb to 40 kb 2 ch lcd pd780354 24 kb to 32 kb 4 ch 1 ch 1 ch 1 ch 8 ch 3 ch (uart: 1 ch) 66 1.8 v drive pd780344 8 ch pd780338 48 kb to 60 kb 3 ch 2 ch 10 ch 1 ch 2 ch (uart: 1 ch) 54 pd780328 62 pd780318 70 pd780308 48 kb to 60 kb 2 ch 1 ch 8 ch 3 ch (time-division uart: 1 ch) 57 2.0 v pd78064b 32 kb 2 ch (uart: 1 ch) pd78064 16 kb to 32 kb bus pd780948 60 kb 2 ch 2 ch 1 ch 1 ch 8 ch 3 ch (uart: 1 ch) 79 4.0 v yes interface pd78098b 40 kb to 60 kb 1 ch 2 ch 69 2.7 v supported pd780816 32 kb to 60 kb 2 ch 12 ch 2 ch (uart: 1 ch) 46 4.0 v meter control pd780958 48 kb to 60 kb 4 ch 2 ch 1 ch 2 ch (uart: 1 ch) 69 2.2 v dashboard pd780852 32 kb to 40 kb 3 ch 1 ch 1 ch 1 ch 5 ch 3 ch (uart: 1 ch) 56 4.0 v control pd780828b 32 kb to 60 kb 59 note 16-bit timer: 2 channels 10-bit timer: 1 channel v dd min. value
51 chapter 1 outline ( pd780024a, 780034a subseries) user s manual u14046ej3v0ud 1.8 block diagram 16-bit timer/ event counter 0 8-bit timer/ event counter 50 8-bit timer/ event counter 51 watchdog timer watch timer serial interface sio30 serial interface sio31 uart0 a/d converter interrupt control clock/buzzer output control ti00/to0/p70 ti01/p71 ti50/to50/p72 ti51/to51/p73 si30/p20 so30/p21 sck30/p22 si31/p34 so31/p35 sck31/p36 rxd0/p23 txd0/p24 asck0/p25 av dd av ss av ref buz/p75 pcl/p74 ani0/p10 to ani7/p17 intp0/p00 to intp3/p03 v dd0 v dd1 v ss0 v ss1 ic (v pp ) 78k/0 cpu core rom (flash memory) ram port 0 p00 to p03 port 1 p10 to p17 port 2 p20 to p25 port 3 p30 to p36 port 4 p40 to p47 port 5 p50 to p57 port 6 p64 to p67 port 7 p70 to p75 external access system control ad0/p40 to ad7/p47 a8/p50 to a15/p57 rd/p64 wr/p65 wait/p66 astb/p67 reset x1 x2 xt1 xt2 8 4 4 8 6 7 8 8 4 6 8 8 remarks 1. the internal rom and ram capacities depend on the product. 2. pin connection in parentheses is intended for the pd78f0034a, 78f0034b.
52 chapter 1 outline ( pd780024a, 780034a subseries) user s manual u14046ej3v0ud 1.9 outline of function part number pd780021a pd780022a pd780023a pd780024a pd78f0034a item pd780031a pd780032a pd780033a pd780034a pd78f0034b internal memory rom 8 kb 16 kb 24 kb 32 kb 32 kb note (mask rom) (mask rom) (mask rom) (mask rom) (flash memory) high-speed ram 512 bytes 1024 bytes 1024 bytes note memory space 64 kb general-purpose register 8 bits 32 registers (8 bits 8 registers 4 banks) minimum instruction minimum instruction execution time changeable function execution time when main system ? 0.166 s/0.333 s/0.666 s/1.33 s/2.66 s (@ 12 mhz operation, clock selected expanded-specification product only) ? 0.238 s/0.477 s/0.954 s/1.90 s/3.81 s (@ 8.38 mhz operation) when subsystem 122 s (@ 32.768 khz operation) clock selected instruction set 16-bit operation multiply/divide (8 bits 8 bits, 16 bits 8 bits) bit manipulate (set, reset, test, and boolean operation) bcd adjust, etc. i/o port total: 51 cmos input: 8 cmos i/o: 39 n-ch open-drain i/o (5 v breakdown): 4 a/d converter 8-bit resolution 8 channels ( pd780021a, 780022a, 780023a, 780024a) 10-bit resolution 8 channels ( pd780031a, 780032a, 780033a, 780034a, 78f0034a, 78f0034b) low-voltage operation: av dd = 1.8 to 5.5 v serial interface 3-wire serial i/o mode: 2 channels uart mode: 1 channel timer 16-bit timer/event counter: 1 channel 8-bit timer/event counter: 2 channels watch timer: 1 channel watchdog timer: 1 channel timer output three outputs (8-bit pwm output enable: 2) clock output 93.7 khz, 187 khz, 375 khz, 750 khz, 1.5 mhz, 3 mhz, 6 mhz, 12 mhz (12 mhz with main system clock, expanded-specification product only) 65.5 khz, 131 khz, 262 khz, 524 khz, 1.05 mhz, 2.10 mhz, 4.19 mhz, 8.38 mhz (8.38 mhz with main system clock) 32.768 khz (32.768 khz with subsystem clock) buzzer output 1.46 khz, 2.92 khz, 5.85 khz, 11.7 khz (12 mhz with main system clock, expanded-specification product only) 1.02 khz, 2.05 khz, 4.10 khz, 8.19 khz (8.38 mhz with main system clock) vectored interrupt maskable internal: 13, external: 5 source non-maskable internal: 1 software 1 note the capacities of internal flash memory and internal high-speed ram can be changed by means of the memory size switching register (ims).
53 chapter 1 outline ( pd780024a, 780034a subseries) user s manual u14046ej3v0ud part number pd780021a pd780022a pd780023a pd780024a pd78f0034a item pd780031a pd780032a pd780033a pd780034a pd78f0034b power supply voltage v dd = 1.8 to 5.5 v operating ambient temperature t a = 40 to +85 c package 64-pin plastic sdip (19.05 mm (750)) 64-pin plastic qfp (14 14) 64-pin plastic lqfp (14 14) 64-pin plastic tqfp (12 12) 64-pin plastic lqfp (10 10) 73-pin plastic fbga (9 9) (standard grade product only) the outline of the timer/event counter is as follows (for details, see chapter 8 16-bit timer/event counter 0 , chapter 9 8-bit timer/event counters 50, 51 , chapter 10 watch timer , and chapter 11 watchdog timer ). 16-bit timer/ 8-bit timer/ watch timer watchdog timer event counter 0 event counters 50, 51 operation interval timer 1 channel 2 channels 1 channel note 1 1 channel note 2 mode external event counter ? function timer output ? ppg output pwm output pulse width measurement square-wave output ? interrupt request ? ? notes 1. the watch timer can perform both watch timer and interval timer functions at the same time. 2. the watchdog timer can perform either the watchdog timer function or the interval timer function.
54 chapter 1 outline ( pd780024a, 780034a subseries) user? manual u14046ej3v0ud 1.10 correspondence between mask rom versions and flash memory versions table 1-1. correspondence between mask rom versions and flash memory versions mask rom version pd780021a/2a/3a/4a pd780021a(a)/2a(a)/3a(a)/4a(a) pd780031a/2a/3a/4a pd780031a(a)/2a(a)/3a(a)/4a(a) conventional expanded- conventional expanded- flash memory version products specification products products specification products pd78f0034a ? ? ? pd78f0034b ? ? ? pd78f0034b(a) ?? note note the pd78f0034b(a) and the conventional products of the pd780021a(a), 780022a(a), 780023a(a), 780024a(a), 780031a(a), 780032a(a), 780033a(a), and 780034a(a) differ in the operating frequency. when replacing a flash memory version with a mask rom version, note the supply voltage and operating frequency. remarks 1. : supported, ? : not supported 2. the pd780034a and pd78f0034b, 78f0034b(a) differ in operating frequency ratings and the communication mode of flash memory programming. see 23.1 differences between pd78f0034a, 78f0034ay and pd78f0034b, 78f0034by . 3. expanded-specification products and conventional products of the pd780024a and 780034a subseries differ in operating frequency ratings. for details, see chapter 25 electrical specifications (expanded-specification products: f x = 1.0 to 12 mhz) and chapter 26 electrical specifications (conventional products: f x = 1.0 to 8.38 mhz) . 4. a special grade product of the pd78f0034a is not available. only a standard grade product is available. 1.11 differences between standard grade products and special grade products the differences between standard grade products ( pd780021a, 780022a, 780023a, 780024a, 780031a, 780032a, 780033a, 780034a, 78f0034a, 78f0034b) and special grade products ( pd780021a(a), 780022a(a), 780023a(a), 780024a(a), 780031a(a), 780032a(a), 780033a(a), 780034a(a), 78f0034b(a)) are shown in table 1-2. table 1-2. differences between standard grade products and special grade products pd780021a, 780022a, 780023a, pd780021a(a), 780022a(a), 780024a, 780031a, 780032a, 780033a, 780023a(a), 780024a(a), 780031a(a), 780034a, 78f0034a, 78f0034b 780032a(a), 780033a(a), 780034a(a), 78f0034b(a) quality grade standard special package see 1.12 correspondence between products and packages other (functions, electrical same specifications, etc.)
55 chapter 1 outline ( pd780024a, 780034a subseries) user s manual u14046ej3v0ud 1.12 correspondence between products and packages the following table shows the correspondence between the products and packages. table 1-3. correspondence between products and packages mask rom version flash memory version pd780021a/2a/3a/4a pd78f0034a pd78f0034b pd780031a/2a/3a/4a standard special standard standard special 64-pin sdip (cw type) ??? ? 64-pin qfp (gc-ab8 type) ?? note 1 ?? 64-pin lqfp (gc-8bs type) ??? 64-pin tqfp (gk-9et type) ??? 64-pin lqfp (gb-8eu type) ? note 2 ? 73-pin fbga (f1-cn3 type) ?? ? notes 1. maintenance product 2. under development remarks 1. : package available, ? : package not available 2. a special grade product of the pd78f0034a is not available. only a standard grade product is available. 1.13 mask options the mask rom versions ( pd780021a, 780022a, 780023a, 780024a, 780031a, 780032a, 780033a, and 780034a) provide pull-up resistor mask options which allow users to specify whether to connect a pull-up resistor to a specific port pin when the user places an order for device production. using the mask option when pull-up resistors are required reduces the number of components to add to the device, resulting in board space saving. the mask options provided in the pd780024a and 780034a subseries are shown in table 1-4. table 1-4. mask options of mask rom versions pin names mask option p30 to p33 pull-up resistor connection can be specified in 1-bit units.
56 user? manual u14046ej3v0ud chapter 2 outline ( pd780024ay, 780034ay subseries) 2.1 features internal memory type program memory data memory part number (rom/flash memory) (high-speed ram) pd780021ay, 780031ay 8 kb 512 bytes pd780022ay, 780032ay 16 kb pd780023ay, 780033ay 24 kb 1024 bytes pd780024ay, 780034ay 32 kb pd78f0034ay, 78f0034by 32 kb note 1024 bytes note note the capacities of internal flash memory and internal high-speed ram can be changed by means of the memory size switching register (ims). external memory expansion space: 64 kb minimum instruction execution time changeable from high speed (0.238 s: @ 8.38 mhz operation with main system clock) to ultra-low speed (122 s: @ 32.768 khz operation with subsystem clock) instruction set suited to system control bit manipulation possible in all address spaces multiply and divide instructions fifty-one i/o ports: (four n-ch open-drain ports) 8-bit resolution a/d converter: 8 channels ( pd780024ay subseries only) 10-bit resolution a/d converter: 8 channels ( pd780034ay subseries only) serial interface: 3 channels 3-wire serial mode: 1 channel uart mode: 1 channel ? 2 c mode: 1 channel timer: five channels 16-bit timer/event counter: 1 channel 8-bit timer/event counter: 2 channels watch timer: 1 channel watchdog timer: 1 channel vectored interrupt sources: 20 two types of on-chip clock oscillators (main system clock and subsystem clock) power supply voltage: v dd = 1.8 to 5.5 v caution only the conventional products are available in the pd780024ay and 780034ay subseries (for details of conventional products, see 1.1 expanded-specification products and conventional products).
57 chapter 2 outline ( pd780024ay, 780034ay subseries) user? manual u14046ej3v0ud 2.2 applications pd780021ay, 780022ay, 780023ay, 780024ay pd780031ay, 780032ay, 780033ay, 780034ay, 78f0034ay, 78f0034by home electric appliances, pagers, av equipment, car audios, car electric equipment, office automation equipment, etc. pd780021ay(a), 780022ay(a), 780023ay(a), 780024ay(a) pd780031ay(a), 780032ay(a), 780033ay(a), 780034ay(a), 78f0034by(a) control of transportation equipment, gas detection breakers, safety devices, etc.
58 chapter 2 outline ( pd780024ay, 780034ay subseries) user? manual u14046ej3v0ud 2.3 ordering information (1) pd780024ay subseries (1/2) part number package internal rom pd780021aycw- 64-pin plastic sdip (19.05 mm (750)) mask rom pd780021aygc- -ab8 64-pin plastic qfp (14 14) mask rom pd780021aygc- -8bs 64-pin plastic lqfp (14 14) mask rom pd780021aygk- -9et 64-pin plastic tqfp (12 12) mask rom pd780021aygb- -8eu 64-pin plastic lqfp (10 10) mask rom pd780021ayf1- -cn3 73-pin plastic fbga (9 9) mask rom pd780022aycw- 64-pin plastic sdip (19.05 mm (750)) mask rom pd780022aygc- -ab8 64-pin plastic qfp (14 14) mask rom pd780022aygc- -8bs 64-pin plastic lqfp (14 14) mask rom pd780022aygk- -9et 64-pin plastic tqfp (12 12) mask rom pd780022aygb- -8eu 64-pin plastic lqfp (10 10) mask rom pd780022ayf1- -cn3 73-pin plastic fbga (9 9) mask rom pd780023aycw- 64-pin plastic sdip (19.05 mm (750)) mask rom pd780023aygc- -ab8 64-pin plastic qfp (14 14) mask rom pd780023aygc- -8bs 64-pin plastic lqfp (14 14) mask rom pd780023aygk- -9et 64-pin plastic tqfp (12 12) mask rom pd780023aygb- -8eu 64-pin plastic lqfp (10 10) mask rom pd780023ayf1- -cn3 73-pin plastic fbga (9 9) mask rom pd780024aycw- 64-pin plastic sdip (19.05 mm (750)) mask rom pd780024aygc- -ab8 64-pin plastic qfp (14 14) mask rom pd780024aygc- -8bs 64-pin plastic lqfp (14 14) mask rom pd780024aygk- -9et 64-pin plastic tqfp (12 12) mask rom pd780024aygb- -8eu 64-pin plastic lqfp (10 10) mask rom pd780024ayf1- -cn3 73-pin plastic fbga (9 9) mask rom remark indicates rom code suffix.
59 chapter 2 outline ( pd780024ay, 780034ay subseries) user? manual u14046ej3v0ud (1) pd780024ay subseries (2/2) part number package internal rom pd780021aycw(a)- note 64-pin plastic sdip (19.05 mm (750)) mask rom pd780021aygc(a)- -ab8 note 64-pin plastic qfp (14 14) mask rom pd780021aygc(a)- -8bs note 64-pin plastic lqfp (14 14) mask rom pd780021aygk(a)- -9et note 64-pin plastic tqfp (12 12) mask rom pd780021aygb(a)- -8eu note 64-pin plastic lqfp (10 10) mask rom pd780022aycw(a)- note 64-pin plastic sdip (19.05 mm (750)) mask rom pd780022aygc(a)- -ab8 64-pin plastic qfp (14 14) mask rom pd780022aygc(a)- -8bs note 64-pin plastic lqfp (14 14) mask rom pd780022aygk(a)- -9et note 64-pin plastic tqfp (12 12) mask rom pd780022aygb(a)- -8eu note 64-pin plastic lqfp (10 10) mask rom pd780023aycw(a)- note 64-pin plastic sdip (19.05 mm (750)) mask rom pd780023aygc(a)- -ab8 note 64-pin plastic qfp (14 14) mask rom pd780023aygc(a)- -8bs note 64-pin plastic lqfp (14 14) mask rom pd780023aygk(a)- -9et note 64-pin plastic tqfp (12 12) mask rom pd780023aygb(a)- -8eu note 64-pin plastic lqfp (10 10) mask rom pd780024aycw(a)- note 64-pin plastic sdip (19.05 mm (750)) mask rom pd780024aygc(a)- -ab8 note 64-pin plastic qfp (14 14) mask rom pd780024aygc(a)- -8bs note 64-pin plastic lqfp (14 14) mask rom pd780024aygk(a)- -9et note 64-pin plastic tqfp (12 12) mask rom pd780024aygb(a)- -8eu note 64-pin plastic lqfp (10 10) mask rom note under development remark indicates rom code suffix.
60 chapter 2 outline ( pd780024ay, 780034ay subseries) user? manual u14046ej3v0ud (2) pd780034ay subseries (1/2) part number package internal rom pd780031aycw- 64-pin plastic sdip (19.05 mm (750)) mask rom pd780031aygc- -ab8 64-pin plastic qfp (14 14) mask rom pd780031aygc- -8bs 64-pin plastic lqfp (14 14) mask rom pd780031aygk- -9et 64-pin plastic tqfp (12 12) mask rom pd780031aygb- -8eu 64-pin plastic lqfp (10 10) mask rom pd780031ayf1- -cn3 73-pin plastic fbga (9 9) mask rom pd780032aycw- 64-pin plastic sdip (19.05 mm (750)) mask rom pd780032aygc- -ab8 64-pin plastic qfp (14 14) mask rom pd780032aygc- -8bs 64-pin plastic lqfp (14 14) mask rom pd780032aygk- -9et 64-pin plastic tqfp (12 12) mask rom pd780032aygb- -8eu 64-pin plastic lqfp (10 10) mask rom pd780032ayf1- -cn3 73-pin plastic fbga (9 9) mask rom pd780033aycw- 64-pin plastic sdip (19.05 mm (750)) mask rom pd780033aygc- -ab8 64-pin plastic qfp (14 14) mask rom pd780033aygc- -8bs 64-pin plastic lqfp (14 14) mask rom pd780033aygk- -9et 64-pin plastic tqfp (12 12) mask rom pd780033aygb- -8eu 64-pin plastic lqfp (10 10) mask rom pd780033ayf1- -cn3 73-pin plastic fbga (9 9) mask rom pd780034aycw- 64-pin plastic sdip (19.05 mm (750)) mask rom pd780034aygc- -ab8 64-pin plastic qfp (14 14) mask rom pd780034aygc- -8bs 64-pin plastic lqfp (14 14) mask rom pd780034aygk- -9et 64-pin plastic tqfp (12 12) mask rom pd780034aygb- -8eu 64-pin plastic lqfp (10 10) mask rom pd780034ayf1- -cn3 73-pin plastic fbga (9 9) mask rom pd78f0034aycw 64-pin plastic sdip (19.05 mm (750)) flash memory pd78f0034aygc-ab8 64-pin plastic qfp (14 14) flash memory pd78f0034aygc-8bs 64-pin plastic lqfp (14 14) flash memory pd78f0034aygk-9et 64-pin plastic tqfp (12 12) flash memory pd78f0034aygb-8eu 64-pin plastic lqfp (10 10) flash memory pd78f0034bygc-8bs 64-pin plastic lqfp (14 14) flash memory pd78f0034bygk-9et 64-pin plastic tqfp (12 12) flash memory pd78f0034bygb-8eu 64-pin plastic lqfp (10 10) flash memory pd78f0034byf1-cn3 73-pin plastic fbga (9 9) flash memory remark indicates rom code suffix.
61 chapter 2 outline ( pd780024ay, 780034ay subseries) user? manual u14046ej3v0ud (2) pd780034ay subseries (2/2) part number package internal rom pd780031aycw(a)- note 64-pin plastic sdip (19.05 mm (750)) mask rom pd780031aygc(a)- -ab8 note 64-pin plastic qfp (14 14) mask rom pd780031aygc(a)- -8bs note 64-pin plastic lqfp (14 14) mask rom pd780031aygk(a)- -9et note 64-pin plastic tqfp (12 12) mask rom pd780031aygb(a)- -8eu note 64-pin plastic lqfp (10 10) mask rom pd780032aycw(a)- note 64-pin plastic sdip (19.05 mm (750)) mask rom pd780032aygc(a)- -ab8 note 64-pin plastic qfp (14 14) mask rom pd780032aygc(a)- -8bs note 64-pin plastic lqfp (14 14) mask rom pd780032aygk(a)- -9et note 64-pin plastic tqfp (12 12) mask rom pd780032aygb(a)- -8eu note 64-pin plastic lqfp (10 10) mask rom pd780033aycw(a)- note 64-pin plastic sdip (19.05 mm (750)) mask rom pd780033aygc(a)- -ab8 note 64-pin plastic qfp (14 14) mask rom pd780033aygc(a)- -8bs note 64-pin plastic lqfp (14 14) mask rom pd780033aygk(a)- -9et note 64-pin plastic tqfp (12 12) mask rom pd780033aygb(a)- -8eu note 64-pin plastic lqfp (10 10) mask rom pd780034aycw(a)- note 64-pin plastic sdip (19.05 mm (750)) mask rom pd780034aygc(a)- -ab8 note 64-pin plastic qfp (14 14) mask rom pd780034aygc(a)- -8bs note 64-pin plastic lqfp (14 14) mask rom pd780034aygk(a)- -9et note 64-pin plastic tqfp (12 12) mask rom pd780034aygb(a)- -8eu note 64-pin plastic lqfp (10 10) mask rom pd78f0034bygc(a)-8bs 64-pin plastic lqfp (14 14) mask rom pd78f0034bygk(a)-9et 64-pin plastic tqfp (12 12) mask rom pd78f0034bygb(a)-8eu 64-pin plastic lqfp (10 10) mask rom note under development remark indicates rom code suffix.
62 chapter 2 outline ( pd780024ay, 780034ay subseries) user? manual u14046ej3v0ud 2.4 quality grade (1) pd780024ay subseries (1/2) part number package quality grades pd780021aycw- 64-pin plastic sdip (19.05 mm (750)) standard pd780021aygc- -ab8 64-pin plastic qfp (14 14) standard pd780021aygc- -8bs 64-pin plastic lqfp (14 14) standard pd780021aygk- -9et 64-pin plastic tqfp (12 12) standard pd780021aygb- -8eu 64-pin plastic lqfp (10 10) standard pd780021ayf1- -cn3 73-pin plastic fbga (9 9) standard pd780022aycw- 64-pin plastic sdip (19.05 mm (750)) standard pd780022aygc- -ab8 64-pin plastic qfp (14 14) standard pd780022aygc- -8bs 64-pin plastic lqfp (14 14) standard pd780022aygk- -9et 64-pin plastic tqfp (12 12) standard pd780022aygb- -8eu 64-pin plastic lqfp (10 10) standard pd780022ayf1- -cn3 73-pin plastic fbga (9 9) standard pd780023aycw- 64-pin plastic sdip (19.05 mm (750)) standard pd780023aygc- -ab8 64-pin plastic qfp (14 14) standard pd780023aygc- -8bs 64-pin plastic lqfp (14 14) standard pd780023aygk- -9et 64-pin plastic tqfp (12 12) standard pd780023aygb- -8eu 64-pin plastic lqfp (10 10) standard pd780023ayf1- -cn3 73-pin plastic fbga (9 9) standard pd780024aycw- 64-pin plastic sdip (19.05 mm (750)) standard pd780024aygc- -ab8 64-pin plastic qfp (14 14) standard pd780024aygc- -8bs 64-pin plastic lqfp (14 14) standard pd780024aygk- -9et 64-pin plastic tqfp (12 12) standard pd780024aygb- -8eu 64-pin plastic lqfp (10 10) standard pd780024ayf1- -cn3 73-pin plastic fbga (9 9) standard remark indicates rom code suffix. please refer to "quality grades on nec semiconductor devices" (document no. c11531e) published by nec electronics corporation to know the specification of the quality grade on the device and its recommended applications.
63 chapter 2 outline ( pd780024ay, 780034ay subseries) user s manual u14046ej3v0ud (1) pd780024ay subseries (2/2) part number package quality grades pd780021aycw(a)- note 64-pin plastic sdip (19.05 mm (750)) special pd780021aygc(a)- -ab8 note 64-pin plastic qfp (14 14) special pd780021aygc(a)- -8bs note 64-pin plastic lqfp (14 14) special pd780021aygk(a)- -9et note 64-pin plastic tqfp (12 12) special pd780021aygb(a)- -8eu note 64-pin plastic lqfp (10 10) special pd780022aycw(a)- note 64-pin plastic sdip (19.05 mm (750)) special pd780022aygc(a)- -ab8 64-pin plastic qfp (14 14) special pd780022aygc(a)- -8bs note 64-pin plastic lqfp (14 14) special pd780022aygk(a)- -9et note 64-pin plastic tqfp (12 12) special pd780022aygb(a)- -8eu note 64-pin plastic lqfp (10 10) special pd780023aycw(a)- note 64-pin plastic sdip (19.05 mm (750)) special pd780023aygc(a)- -ab8 note 64-pin plastic qfp (14 14) special pd780023aygc(a)- -8bs note 64-pin plastic lqfp (14 14) special pd780023aygk(a)- -9et note 64-pin plastic tqfp (12 12) special pd780023aygb(a)- -8eu note 64-pin plastic lqfp (10 10) special pd780024aycw(a)- note 64-pin plastic sdip (19.05 mm (750)) special pd780024aygc(a)- -ab8 note 64-pin plastic qfp (14 14) special pd780024aygc(a)- -8bs note 64-pin plastic lqfp (14 14) special pd780024aygk(a)- -9et note 64-pin plastic tqfp (12 12) special pd780024aygb(a)- -8eu note 64-pin plastic lqfp (10 10) special note under development remark indicates rom code suffix. please refer to "quality grades on nec semiconductor devices" (document no. c11531e) published by nec electronics corporation to know the specification of the quality grade on the device and its recommended applications.
64 chapter 2 outline ( pd780024ay, 780034ay subseries) user s manual u14046ej3v0ud (2) pd780034ay subseries (1/2) part number package quality grades pd780031aycw- 64-pin plastic sdip (19.05 mm (750)) standard pd780031aygc- -ab8 64-pin plastic qfp (14 14) standard pd780031aygc- -8bs 64-pin plastic lqfp (14 14) standard pd780031aygk- -9et 64-pin plastic tqfp (12 12) standard pd780031aygb- -8eu 64-pin plastic lqfp (10 10) standard pd780031ayf1- -cn3 73-pin plastic fbga (9 9) standard pd780032aycw- 64-pin plastic sdip (19.05 mm (750)) standard pd780032aygc- -ab8 64-pin plastic qfp (14 14) standard pd780032aygc- -8bs 64-pin plastic lqfp (14 14) standard pd780032aygk- -9et 64-pin plastic tqfp (12 12) standard pd780032aygb- -8eu 64-pin plastic lqfp (10 10) standard pd780032ayf1- -cn3 73-pin plastic fbga (9 9) standard pd780033aycw- 64-pin plastic sdip (19.05 mm (750)) standard pd780033aygc- -ab8 64-pin plastic qfp (14 14) standard pd780033aygc- -8bs 64-pin plastic lqfp (14 14) standard pd780033aygk- -9et 64-pin plastic tqfp (12 12) standard pd780033aygb- -8eu 64-pin plastic lqfp (10 10) standard pd780033ayf1- -cn3 73-pin plastic fbga (9 9) standard pd780034aycw- 64-pin plastic sdip (19.05 mm (750)) standard pd780034aygc- -ab8 64-pin plastic qfp (14 14) standard pd780034aygc- -8bs 64-pin plastic lqfp (14 14) standard pd780034aygk- -9et 64-pin plastic tqfp (12 12) standard pd780034aygb- -8eu 64-pin plastic lqfp (10 10) standard pd780034ayf1- -cn3 73-pin plastic fbga (9 9) standard pd78f0034aycw 64-pin plastic sdip (19.05 mm (750)) standard pd78f0034aygc-ab8 64-pin plastic qfp (14 14) standard pd78f0034aygc-8bs 64-pin plastic lqfp (14 14) standard pd78f0034aygk-9et 64-pin plastic tqfp (12 12) standard pd78f0034aygb-8eu 64-pin plastic lqfp (10 10) standard pd78f0034bygc-8bs 64-pin plastic lqfp (14 14) standard pd78f0034bygk-9et 64-pin plastic tqfp (12 12) standard pd78f0034bygb-8eu 64-pin plastic lqfp (10 10) standard pd78f0034byf1-cn3 73-pin plastic fbga (9 9) standard remark indicates rom code suffix. please refer to "quality grades on nec semiconductor devices" (document no. c11531e) published by nec electronics corporation to know the specification of the quality grade on the device and its recommended applications.
65 chapter 2 outline ( pd780024ay, 780034ay subseries) user s manual u14046ej3v0ud (2) pd780034ay subseries (2/2) part number package quality grades pd780031aycw(a)- note 64-pin plastic sdip (19.05 mm (750)) special pd780031aygc(a)- -ab8 note 64-pin plastic qfp (14 14) special pd780031aygc(a)- -8bs note 64-pin plastic lqfp (14 14) special pd780031aygk(a)- -9et note 64-pin plastic tqfp (12 12) special pd780031aygb(a)- -8eu note 64-pin plastic lqfp (10 10) special pd780032aycw(a)- note 64-pin plastic sdip (19.05 mm (750)) special pd780032aygc(a)- -ab8 note 64-pin plastic qfp (14 14) special pd780032aygc(a)- -8bs note 64-pin plastic lqfp (14 14) special pd780032aygk(a)- -9et note 64-pin plastic tqfp (12 12) special pd780032aygb(a)- -8eu note 64-pin plastic lqfp (10 10) special pd780033aycw(a)- note 64-pin plastic sdip (19.05 mm (750)) special pd780033aygc(a)- -ab8 note 64-pin plastic qfp (14 14) special pd780033aygc(a)- -8bs note 64-pin plastic lqfp (14 14) special pd780033aygk(a)- -9et note 64-pin plastic tqfp (12 12) special pd780033aygb(a)- -8eu note 64-pin plastic lqfp (10 10) special pd780034aycw(a)- note 64-pin plastic sdip (19.05 mm (750)) special pd780034aygc(a)- -ab8 note 64-pin plastic qfp (14 14) special pd780034aygc(a)- -8bs note 64-pin plastic lqfp (14 14) special pd780034aygk(a)- -9et note 64-pin plastic tqfp (12 12) special pd780034aygb(a)- -8eu note 64-pin plastic lqfp (10 10) special pd78f0034bygc(a)-8bs 64-pin plastic lqfp (14 14) special pd78f0034bygk(a)-9et 64-pin plastic tqfp (12 12) special pd78f0034bygb(a)-8eu 64-pin plastic lqfp (10 10) special note under development remark indicates rom code suffix. please refer to "quality grades on nec semiconductor devices" (document no. c11531e) published by nec electronics corporation to know the specification of the quality grade on the device and its recommended applications.
66 chapter 2 outline ( pd780024ay, 780034ay subseries) user s manual u14046ej3v0ud 2.5 pin configuration (top view) 64-pin plastic sdip (19.05 mm (750)) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 p67/astb p66/wait p65/wr p64/rd p75/buz p74/pcl p73/ti51/to51 p72/ti50/to50 p71/ti01 p70/ti00/to0 p03/intp3/adtrg p02/intp2 p01/intp1 p00/intp0 v ss1 x1 x2 ic (v pp ) xt1 xt2 reset av dd av ref p10/ani0 p11/ani1 p12/ani2 p13/ani3 p14/ani4 p15/ani5 p16/ani6 p17/ani7 av ss 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 p40/ad0 p41/ad1 p42/ad2 p43/ad3 p44/ad4 p45/ad5 p46/ad6 p47/ad7 p50/a8 p51/a9 p52/a10 p53/a11 p54/a12 p55/a13 p56/a14 p57/a15 v ss0 v dd0 p30 p31 p32/sda0 p33/scl0 p34 p35 p36 p20/si30 p21/so30 p22/sck30 p23/rxd0 p24/txd0 p25/asck0 v dd1 cautions 1. connect the ic (internally connected) pin directly to v ss0 or v ss1 . 2. connect the av ss pin to v ss0 . remarks 1. when the pd780024ay, 780034ay subseries products are used in applications where the noise generated inside the microcontroller needs to be reduced, the implementation of noise reduction measures, such as supplying voltage to v dd0 and v dd1 individually and connecting v ss0 and v ss1 to different ground lines, is recommended. 2. pin connection in parentheses is intended for the pd78f0034ay.
67 chapter 2 outline ( pd780024ay, 780034ay subseries) user s manual u14046ej3v0ud 64-pin plastic qfp (14 14) 64-pin plastic lqfp (14 14) 64-pin plastic tqfp (12 12) 64-pin plastic lqfp (10 10) cautions 1. connect the ic (internally connected) pin directly to v ss0 or v ss1 . 2. connect the av ss pin to v ss0 . remarks 1. when the pd780024ay, 780034ay subseries products are used in applications where the noise generated inside the microcontroller needs to be reduced, the implementation of noise reduction measures, such as supplying voltage to v dd0 and v dd1 individually and connecting v ss0 and v ss1 to different ground lines, is recommended. 2. pin connection in parentheses is intended for the pd78f0034ay, 78f0034by. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 p50/a8 p51/a9 p52/a10 p53/a11 p54/a12 p55/a13 p56/a14 p57/a15 v ss0 v dd0 p30 p31 p32/sda0 p33/scl0 p34 p35 p36 p20/si30 p21/so30 p22/sck30 p23/rxd0 p24/txd0 p25/asck0 v dd1 av ss p17/ani7 p16/ani6 p15/ani5 p14/ani4 p13/ani3 p12/ani2 p11/ani1 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 p71/ti01 p70/ti00/to0 p03/intp3/adtrg p02/intp2 p01/intp1 p00/intp0 v ss1 x1 x2 ic (v pp ) xt1 xt2 reset av dd av ref p10/ani0 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 p47/ad7 p46/ad6 p45/ad5 p44/ad4 p43/ad3 p42/ad2 p41/ad1 p40/ad0 p67/astb p66/wait p65/wr p64/rd p75/buz p74/pcl p73/ti51/to51 p72/ti50/to50
68 chapter 2 outline ( pd780024ay, 780034ay subseries) user s manual u14046ej3v0ud pin no . pin name pin no . pin name pin no . pin name pin no . pin name pin no . pin name a1 nc c1 p52/a10 e1 p57/a15 g1 p33/scl0 j1 nc a2 p46/ad6 c2 p53/a11 e2 v dd0 g2 p32/sda0 j2 p36 a3 p44/ad4 c3 p45/ad5 e3 p54/a12 g3 p20/si30 j3 nc a4 p41/ad1 c4 p42/ad2 e4 ? g4 p21/so30 j4 p25/asck0 a5 p67/astb c5 p64/rd e5 ? g5 p24/txd0 j5 nc a6 p65/wr c6 p73/ti51/to51 e6 ? g6 v dd1 j6 p17/ani7 a7 p74/pcl c7 p03/intp3/adtrg e7 p00/intp0 g7 p16/ani6 j7 p12/ani2 a8 nc c8 p01/intp1 e8 xt1 g8 av dd j8 p13/ani3 a9 nc c9 v ss1 e9 x2 g9 nc j9 nc b1 p51/a9 d1 p55/a13 f1 p30 h1 p34 b2 p47/ad7 d2 p56/a14 f2 p31 h2 p35 b3 p43/ad3 d3 p50/a8 f3 v ss0 h3 p23/rxd0 b4 p40/ad0 d4 nc f4 ? h4 p22/sck30 b5 p66/wait d5 ? f5 ? h5 av ss b6 p75/buz d6 ? f6 ? h6 p15/ani5 b7 p72/ti50/to51 d7 p02/intp2 f7 p14/ani4 h7 p11/ani1 b8 p71/ti01 d8 ic (v pp ) f8 reset h8 p10/ani0 b9 p70/ti00/to0 d9 x1 f9 xt2 h9 av ref cautions 1. connect the ic (internally connected) pin directly to v ss0 or v ss1 . 2. connect the av ss pin to v ss0 . remarks 1. when the pd780024ay, 780034ay subseries products are used in applications where the noise generated inside the microcontroller needs to be reduced, the implementation of noise reduction measures, such as supplying voltage to v dd0 and v dd1 individually and connecting v ss0 and v ss1 to different ground lines, is recommended. 2. pin connection in parentheses is intended for the pd78f0034by. ? 73-pin plastic fbga (9 9) top view bottom view jhgfedcba abcdefghj 9 8 7 6 5 4 3 2 1 index mark
69 chapter 2 outline ( pd780024ay, 780034ay subseries) user s manual u14046ej3v0ud a8 to a15: address bus p70 to p75: port 7 ad0 to ad7: address/data bus pcl: programmable clock adtrg: ad trigger input rd: read strobe ani0 to ani7: analog input reset: reset asck0: asynchronous serial clock rxd0: receive data astb: address strobe sck30: serial clock av dd : analog power supply scl0: serial clock av ref : analog reference voltage sda0: serial data av ss : analog ground si30: serial input buz: buzzer clock so30: serial output ic: internally connected ti00, ti01, ti50, ti51: timer input intp0 to intp3: external interrupt input to0, to50, to51: timer output nc: non-connection txd0: transmit data p00 to p03: port 0 v dd0 , v dd1 : power supply p10 to p17: port 1 v pp : programming power supply p20 to p25: port 2 v ss0 , v ss1 : ground p30 to p36: port 3 wait: wait p40 to p47: port 4 wr: write strobe p50 to p57: port 5 x1, x2: crystal (main system clock) p64 to p67: port 6 xt1, xt2: crystal (subsystem clock)
70 chapter 2 outline ( pd780024ay, 780034ay subseries) user? manual u14046ej3v0ud 2.6 78k/0 series lineup the products in the 78k/0 series are listed below. the names enclosed in boxes are subseries name. remark vfd (vacuum fluorescent display) is referred to as fip (fluorescent indicator panel) in some documents, but the functions of the two are the same. pd78083 pd78018f pd78018fy pd78014h emi-noise reduced version of the pd78018f basic subseries for control on-chip uart, capable of operating at low voltage (1.8 v) 42/44-pin 64-pin 64-pin 52-pin 52-pin version of the pd780024a pd780024as 52-pin 52-pin version of the pd780034a pd780034as pd78054 with iebus controller pd78054 with enhanced serial i/o pd78078y with enhanced serial i/o and limited functions pd78054 with timer and enhanced external interface 64-pin 64-pin 80-pin 80-pin 80-pin emi-noise reduced version of the pd78054 pd78018f with uart and d/a converter, and enhanced i/o pd780034a pd780988 pd780034ay 64-pin pd780024a with expanded ram pd780024a with enhanced a/d converter on-chip inverter controller and uart. emi-noise reduced. pd78064 pd78064b pd780308 100-pin 100-pin 100-pin pd780308y pd78064y 80-pin 78k/0 series lcd drive pd78064 with enhanced sio, and expanded rom and ram emi-noise reduced version of the pd78064 basic subseries for driving lcds, on-chip uart bus interface supported pd78018f with enhanced serial i/o 80-pin 100-pin 100-pin products in mass production products under development y subseries products are compatible with i 2 c bus. romless version of the pd78078 100-pin 100-pin emi-noise reduced version of the pd78078 inverter control pd780208 100-pin vfd drive pd78044f with enhanced i/o and vfd c/d. display output total: 53 pd78098b 100-pin pd780024a pd780024ay 80-pin 80-pin pd780852 pd780828b for automobile meter driver. on-chip can controller 100-pin pd780958 for industrial meter control on-chip automobile meter controller/driver meter control 80-pin on-chip iebus controller 80-pin on-chip controller compliant with j1850 (class 2) pd780833y pd780948 on-chip can controller 64-pin pd780078 pd780078y pd780034a with timer and enhanced serial i/o pd78054 pd78054y pd78058f pd78058fy pd780058 pd780058y pd78070a pd78070ay pd78078 pd78078y pd780018ay control pd78075b pd780065 pd78044h pd780232 80-pin 80-pin for panel control. on-chip vfd c/d. display output total: 53 pd78044f with n-ch open-drain i/o. display output total: 34 pd78044f 80-pin basic subseries for driving vfd. display output total: 34 120-pin pd780308 with enhanced display function and timer. segment signal output: 40 pins max. pd780318 pd780328 120-pin 120-pin pd780308 with enhanced display function and timer. segment signal output: 32 pins max. pd780308 with enhanced display function and timer. segment signal output: 24 pins max. pd780338 pd780308 with enhanced display function and timer. segment signal output: 40 pins max. on-chip can controller specialized for can controller function 80-pin pd780703ay pd780702y 64-pin pd780816 pd780344 with enhanced a/d converter 100-pin 100-pin pd780344 pd780344y pd780354 pd780354y
71 chapter 2 outline ( pd780024ay, 780034ay subseries) user s manual u14046ej3v0ud the major functional differences between the subseries are shown below. subseries with the suffix y function rom timer 8-bit 10-bit 8-bit serial interface i/o v dd external subseries name capacity 8-bit 16-bit watch wdt a/d a/d d/a min. value expansion control pd78078y 48 kb to 60 kb 4 ch 1 ch 1 ch 1 ch 8 ch ? 2 ch 3 ch (uart: 1 ch, 88 1.8 v yes pd78070ay ? i 2 c: 1 ch) 61 2.7 v pd780018ay 48 kb to 60 kb ? 3 ch (i 2 c: 1 ch) 88 pd780058y 24 kb to 60 kb 2 ch 2 ch 3 ch (time-division 68 1.8 v uart: 1 ch, i 2 c: 1 ch) pd78058fy 48 kb to 60 kb 3 ch (uart: 1 ch, 69 2.7 v pd78054y 16 kb to 60 kb i 2 c: 1 ch) 2.0 v pd780078y 48 kb to 60 kb 2 ch ? 8 ch ? 4 ch (uart: 2 ch, 52 1.8 v i 2 c: 1 ch) pd780034ay 8 kb to 32 kb 1 ch 3 ch (uart: 1 ch, 51 pd780024ay 8 ch ? i 2 c: 1 ch) pd78018fy 8 kb to 60 kb 2 ch (i 2 c: 1 ch) 53 lcd pd780354y 24 kb to 32 kb 4 ch 1 ch 1 ch 1 ch ? 8 ch ? 4 ch (uart: 1 ch, 66 1.8 v ? drive pd780344y 8 ch ? i 2 c: 1 ch) pd780308y 48 kb to 60 kb 2 ch 3 ch (time-division 57 2.0 v uart: 1 ch, i 2 c: 1 ch) pd78064y 16 kb to 32 kb 2 ch (uart: 1 ch, i 2 c: 1 ch) bus pd780702y 60 kb 3 ch 2 ch 1 ch 1 ch 16 ch ?? 4 ch (uart: 1 ch, 67 3.5 v ? interface pd780703ay 59.5 kb i 2 c: 1 ch) supported pd780833y 60 kb 65 4.5 v remark the functions of the subseries without the suffix y and the subseries with the suffix y are the same, except for the serial interface (if a subseries without the suffix y is available).
72 chapter 2 outline ( pd780024ay, 780034ay subseries) user s manual u14046ej3v0ud 2.7 block diagram ti00/to0/p70 16-bit timer/ event counter 0 serial interface sio30 interrupt control clock/buzzer output control uart0 78k/0 cpu core port 0 port 1 port 2 port 3 port 4 port 5 port 6 port 7 p70 to p75 p64 to p67 p50 to p57 p40 to p47 p30 to p36 p20 to p25 p10 to p17 p00 to p03 external access system control reset x1 x2 xt1 xt2 rd/p64 wr/p65 wait/p66 astb/p67 ad0/p40 to ad7/p47 a8/p50 to a15/p57 rom (flash memory) ram a/d converter i 2 c bus v dd0 v dd1 v ss0 v ss1 ic (v pp ) watchdog timer watch timer 8-bit timer/ event counter 50 8-bit timer/ event counter 51 ti50/to50/p72 ti51/to51/p73 si30/p20 so30/p21 sck30/p22 rxd0/p23 txd0/p24 asck0/p25 av dd av ss av ref sda0/p32 scl0/p33 buz/p75 pcl/p74 ani0/p10 to ani7/p17 intp0/p00 to intp3/p03 ti01/p71 8 4 4 8 6 7 8 8 4 6 8 8 remarks 1. the internal rom and ram capacities depend on the product. 2. pin connection in parentheses is intended for the pd78f0034ay, 78f0034by.
73 chapter 2 outline ( pd780024ay, 780034ay subseries) user s manual u14046ej3v0ud 2.8 outline of function part number pd780021ay pd780022ay pd780023ay pd780024ay pd78f0034ay item pd780031ay pd780032ay pd780033ay pd780034ay pd78f0034by internal memory rom 8 kb 16 kb 24 kb 32 kb 32 kb note (mask rom) (mask rom) (mask rom) (mask rom) (flash memory) high-speed ram 512 bytes 1024 bytes 1024 bytes note memory space 64 kb general-purpose register 8 bits 32 registers (8 bits 8 registers 4 banks) minimum instruction minimum instruction execution time changeable function execution time when main system 0.238 s/0.477 s/0.954 s/1.90 s/3.81 s (@ 8.38 mhz operation) clock selected when subsystem 122 s (@ 32.768 khz operation) clock selected instruction set 16-bit operation multiply/divide (8 bits 8 bits, 16 bits 8 bits) bit manipulate (set, reset, test, and boolean operation) bcd adjust, etc. i/o port total: 51 cmos input: 8 cmos i/o: 39 n-ch open-drain i/o (5 v breakdown): 4 a/d converter 8-bit resolution 8 channels ( pd780021ay, 780022ay, 780023ay, 780024ay) 10-bit resolution 8 channels ( pd780031ay, 780032ay, 780033ay, 780034ay, 78f0034ay, 78f0034by) low-voltage operation: av dd = 1.8 to 5.5 v serial interface 3-wire serial i/o mode: 1 channel uart mode: 1 channel i 2 c bus mode: 1 channel timer 16-bit timer/event counter: 1 channel 8-bit timer/event counter: 2 channels watch timer: 1 channel watchdog timer: 1 channel timer output three outputs (8-bit pwm output enable: 2) clock output 65.5 khz, 131 khz, 262 khz, 524 khz, 1.05 mhz, 2.10 mhz, 4.19 mhz, 8.38 mhz (8.38 mhz with main system clock) 32.768 khz (32.768 khz with subsystem clock) buzzer output 1.02 khz, 2.05 khz, 4.10 khz, 8.19 khz (8.38 mhz with main system clock) vectored interrupt maskable internal: 13, external: 5 source non-maskable internal: 1 software 1 power supply voltage v dd = 1.8 to 5.5 v operating ambient temperature t a = 40 to +85 c package 64-pin plastic sdip (19.05 mm (750)) 64-pin plastic qfp (14 14) 64-pin plastic lqfp (14 14) 64-pin plastic tqfp (12 12) 64-pin plastic lqfp (10 10) 73-pin plastic fbga (9 9) (standard grade product only) note the capacities of internal flash memory and internal high-speed ram can be changed by means of the memory size switching register (ims).
74 chapter 2 outline ( pd780024ay, 780034ay subseries) user s manual u14046ej3v0ud the outline of the timer/event counter is as follows (for details, see chapter 8 16-bit timer/event counter 0 , chapter 9 8-bit timer/event counters 50, 51 , chapter 10 watch timer , and chapter 11 watchdog timer ). 16-bit timer/ 8-bit timer/ watch timer watchdog timer event counter 0 event counters 50, 51 operation interval timer 1 channel 2 channels 1 channel note 1 1 channel note 2 mode external event counter ? function timer output ? ppg output pwm output pulse width measurement square-wave output ? interrupt request ? ? notes 1. the watch timer can perform both watch timer and interval timer functions at the same time. 2. the watchdog timer can perform either the watchdog timer function or the interval timer function. 2.9 correspondence between mask rom versions and flash memory versions table 2-1. correspondence between mask rom versions and flash memory versions mask rom version pd780021ay/2ay/3ay/4ay pd780021ay(a)/2ay(a)/3ay(a)/4ay(a) pd780031ay/2ay/3ay/4ay pd780031ay(a)/2ay(a)/3ay(a)/4ay(a) flash memory version pd78f0034ay ? pd78f0034by ? pd78f0034by(a) ? remarks 1. : supported, ? : not supported 2. the pd780034ay and pd78f0034by, 78f0034by(a) differ in the communication mode of flash memory programming. see 23.1 differences between pd78f0034a, 78f0034ay and pd78f0034b, 78f0034by . 3. expanded-specification products of the pd780024ay and 780034ay subseries are not available. only conventional products are available. 4. a special grade product of the pd78f0034ay is not available. only a standard grade product is available.
75 chapter 2 outline ( pd780024ay, 780034ay subseries) user s manual u14046ej3v0ud 2.10 differences between standard grade products and special grade products the differences between standard grade products ( pd780021ay, 780022ay, 780023ay, 780024ay, 780031ay, 780032ay, 780033ay, 780034ay, 78f0034ay, 78f0034by) and special grade products ( pd780021ay(a), 780022ay(a), 780023ay(a), 780024ay(a), 780031ay(a), 780032ay(a), 780033ay(a), 780034ay(a), 78f0034by(a)) are shown in table 2-2. table 2-2. differences between standard grade products and special grade products pd780021ay, 780022ay, 780023ay, pd780021ay(a), 780022ay(a), 780024ay, 780031ay, 780032ay, 780023ay(a), 780024ay(a), 780031ay(a), 780033ay, 780034ay, 78f0034ay, 780032ay(a), 780033ay(a), 780034ay(a), 78f0034by 78f0034by(a) quality grade standard special package see 2.11 correspondence between products and packages other (functions, electrical same specifications, etc.) 2.11 correspondence between products and packages the following table shows the correspondence between the products and packages. table 2-3. correspondence between products and packages mask rom version flash memory version pd780021ay/2ay/3ay/4ay pd78f0034ay pd78f0034by pd780031ay/2ay/3ay/4ay standard special standard standard special 64-pin sdip (cw type) ? note 1 ? ? 64-pin qfp (gc-ab8 type) ? note 2 ? ? 64-pin lqfp (gc-8bs type) ? note 1 ? 64-pin tqfp (gk-9et type) ? note 1 ? 64-pin lqfp (gb-8eu type) ? note 1 ? 73-pin fbga (f1-cn3 type) ?? ? notes 1. under development 2. only the pd780022aygc(a)-ab8 is under mass production. the other models are still under development. remarks 1. : package available, ? : package not available 2. a special grade product of the pd78f0034ay is not available. only a standard grade product is available.
76 chapter 2 outline ( pd780024ay, 780034ay subseries) user s manual u14046ej3v0ud 2.12 mask options the mask rom versions ( pd780021ay, 780022ay, 780023ay, 780024ay, 780031ay, 780032ay, 780033ay, 780034ay) provide pull-up resistor mask options which allow users to specify whether to connect a pull-up resistor to a specific port pin when the user places an order for device production. using the mask option when pull-up resistors are required reduces the number of components to add to the device, resulting in board space saving. the mask options provided in the pd780024ay and 780034ay subseries are shown in table 2-4. table 2-4. mask options of mask rom versions pin names mask option p30, p31 pull-up resistor connection can be specified in 1-bit units.
77 user? manual u14046ej3v0ud pin name i/o function after reset alternate function p00 i/o input intp0 p01 intp1 p02 intp2 p03 intp3/adtrg p10 to p17 input port 1 input ani0 to ani7 8-bit input-only port. p20 i/o input si30 p21 so30 p22 sck30 p23 rxd0 p24 txd0 p25 asck0 p30 i/o input ? p31 p32 p33 p34 si31 p35 so31 p36 sck31 p40 to p47 i/o port 4 input ad0 to ad7 8-bit i/o port input/output mode can be specified in 1-bit units. an on-chip pull-up resistor can be used by software settings. interrupt request flag (krif) is set to 1 by falling edge detection. p50 to p57 i/o port 5 input a8 to a15 8-bit i/o port leds can be driven directly. input/output mode can be specified in 1-bit units. an on-chip pull-up resistor can be used by software settings. p64 i/o input rd p65 wr p66 wait p67 astb chapter 3 pin function ( pd780024a, 780034a subseries) 3.1 pin function list (1) port pins (1/2) port 0 4-bit i/o port input/output mode can be specified in 1-bit units. an on-chip pull-up resistor can be used by software settings. port 2 6-bit i/o port input/output mode can be specified in 1-bit units. an on-chip pull-up resistor can be used by software settings. port 3 7-bit i/o port input/output mode can be specified in 1-bit units. n-ch open-drain i/o port on-chip pull-up resistor can be specified by mask option (mask rom version only). leds can be driven directly. an on-chip pull-up resistor can be used by software settings. port 6 4-bit i/o port input/output mode can be specified in 1-bit units. an on-chip pull-up resistor can be used by software settings.
78 chapter 3 pin function ( pd780024a, 780034a subseries) user? manual u14046ej3v0ud pin name i/o function after reset alternate function intp0 input input p00 intp1 p01 intp2 p02 intp3 p03/adtrg si30 input serial interface serial data input input p20 si31 p34 so30 output serial interface serial data output input p21 so31 p35 sck30 i/o serial interface serial clock input/output input p22 sck31 p36 rxd0 input asynchronous serial interface serial data input input p23 txd0 output asynchronous serial interface serial data output input p24 asck0 input asynchronous serial interface serial clock input input p25 ti00 input external count clock input to 16-bit timer/event counter 0 input p70/to0 capture trigger input to 16-bit timer/event counter 0 capture register (cr00, cr01) ti01 capture trigger input to 16-bit timer/event counter 0 p71 capture register (cr00) ti50 external count clock input to 8-bit timer/event counter 50 p72/to50 ti51 external count clock input to 8-bit timer/event counter 51 p73/to51 to0 output 16-bit timer/event counter 0 output input p70/ti00 to50 8-bit timer/event counter 50 output input p72/ti50 (also used for 8-bit pwm output) to51 8-bit timer/event counter 51 output p73/ti51 (also used for 8-bit pwm output) pcl output clock output (for main system clock and subsystem clock input p74 trimming) buz output buzzer output input p75 ad0 to ad7 i/o lower address/data bus when expanding external memory input p40 to p47 pin name i/o function after reset alternate function p70 i/o input ti00/to0 p71 ti01 p72 ti50/to50 p73 ti51/to51 p74 pcl p75 buz (2) non-port pins (1/2) (1) port pins (2/2) external interrupt request input with specifiable valid edges (rising edge, falling edge, both rising and falling edges) port 7 6-bit i/o port input/output mode can be specified in 1-bit units. an on-chip pull-up resistor can be used by software settings.
79 chapter 3 pin function ( pd780024a, 780034a subseries) user? manual u14046ej3v0ud pin name i/o function after reset alternate function a8 to a15 output higher address bus when expanding external memory input p50 to p57 rd output strobe signal output for read operation from external memory input p64 wr strobe signal output for write operation from external memory p65 wait input wait insertion when accessing external memory input p66 astb output strobe output externally latching address information input p67 output to ports 4, 5 to access external memory ani0 to ani7 input a/d converter analog input input p10 to p17 adtrg input a/d converter trigger signal input input p03/intp3 av ref input a/d converter reference voltage input ?? av dd ? a/d converter analog power supply. connect to v dd0 or v dd1 . ?? av ss ? a/d converter ground potential. connect to v ss0 or v ss1 . ?? reset input system reset input input ? x1 input crystal/ceramic connection for main system clock oscillation ?? x2 ? ?? xt1 input crystal connection for subsystem clock oscillation ?? xt2 ? ?? v dd0 ? positive power supply for ports ?? v dd1 ? positive power supply other than ports ?? v ss0 ? ground potential for ports ?? v ss1 ? ground potential other than ports ?? ic ? internally connected. connect directly to v ss0 or v ss1 . ?? nc note ? not internally connected. leave open. ?? v pp ? high-voltage application for program write/verify. ?? note the nc pin is available only for a 73-pin plastic fbga. (2) non-port pins (2/2)
80 chapter 3 pin function ( pd780024a, 780034a subseries) user? manual u14046ej3v0ud 3.2 description of pin functions 3.2.1 p00 to p03 (port 0) these are 4-bit i/o ports. besides serving as i/o ports, they function as an external interrupt input, and a/d converter external trigger input. the following operating modes can be specified in 1-bit units. (1) port mode these ports function as 4-bit i/o ports. p00 to p03 can be specified as input or output ports in 1-bit units with port mode register 0 (pm0). on-chip pull- up resistors can be used by setting pull-up resistor option register 0 (pu0). (2) control mode these ports function as an external interrupt request input, and a/d converter external trigger input. (a) intp0 to intp3 intp0 to intp3 are external interrupt request input pins which can specify valid edges (rising edge, falling edge, and both rising and falling edges). (b) adtrg a/d converter external trigger input pin. caution when p03 is used as an a/d converter external trigger input, specify the valid edge by bits 1, 2 (ega00, ega01) of a/d converter mode register (adm0) and set interrupt mask flag (pmk3) to 1. 3.2.2 p10 to p17 (port 1) these are 8-bit input-only ports. besides serving as input ports, they function as an a/d converter analog input. the following operating modes can be specified in 1-bit units. (1) port mode these ports function as 8-bit input-only ports. (2) control mode these ports function as a/d converter analog input pins (ani0 to ani7).
81 chapter 3 pin function ( pd780024a, 780034a subseries) user? manual u14046ej3v0ud 3.2.3 p20 to p25 (port 2) these are 6-bit i/o ports. besides serving as i/o ports, they function as data i/o and clock i/o of serial interface sio30 or uart0. the following operating modes can be specified in 1-bit units. (1) port mode these ports function as 6-bit i/o ports. they can be specified as input or output ports in 1-bit units with port mode register 2 (pm2). on-chip pull-up resistors can be used by setting pull-up resistor option register 2 (pu2). (2) control mode these ports function as data i/o and clock i/o of serial interface sio30 or uart0. (a) si30 and so30 serial data i/o pins of serial interface sio30. (b) sck30 serial clock i/o pin of serial interface sio30. (c) r x d0 and t x d0 serial data i/o pins of serial interface uart0. (d) asck0 serial clock input pin of serial interface uart0. 3.2.4 p30 to p36 (port 3) these are 7-bit i/o ports. besides serving as i/o ports, they function as data i/o and clock i/o of serial interface sio31. p30 to p33 can drive leds directly. the following operating modes can be specified in 1-bit units. (1) port mode these ports function as 7-bit i/o ports. they can be specified as input or output ports in 1-bit units with port mode register 3 (pm3). p30 to p33 are n-ch open-drain i/o port. on-chip pull-up resistor can be used by mask option (mask rom version only). on-chip pull-up resistors of p34 to p36 can be used by setting pull-up resistor option register 3 (pu3). (2) control mode these ports function as data i/o and clock i/o of serial interface sio31. (a) si31 and so31 serial data i/o pins of serial interface sio31. (b) sck31 serial clock i/o pin of serial interface sio31.
82 chapter 3 pin function ( pd780024a, 780034a subseries) user? manual u14046ej3v0ud 3.2.5 p40 to p47 (port 4) these are 8-bit i/o ports. besides serving as i/o ports, they function as an address/data bus. the interrupt request flag (krif) can be set to 1 by detecting a falling edge. the following operating mode can be specified in 1-bit units. caution when using the falling edge detection interrupt (intkr), be sure to set the memory expansion mode register (mem) to 01h. (1) port mode these ports function as 8-bit i/o ports. they can be specified as input or output ports in 1-bit units with port mode register 4 (pm4). on-chip pull-up resistors can be used by setting pull-up resistor option register 4 (pu4). (2) control mode these ports function as lower address/data bus pins (ad0 to ad7) in external memory expansion mode. 3.2.6 p50 to p57 (port 5) these are 8-bit i/o ports. besides serving as i/o ports, they function as an address bus. port 5 can drive leds directly. the following operating modes can be specified in 1-bit units. (1) port mode these ports function as 8-bit i/o ports. they can be specified as input or output ports in 1-bit units with port mode register 5 (pm5). on-chip pull-up resistors can be used by setting pull-up resistor option register 5 (pu5). (2) control mode these ports function as higher address bus pins (a8 to a15) in external memory expansion mode. 3.2.7 p64 to p67 (port 6) these are 4-bit i/o ports. besides serving as i/o ports, they are used for control in external memory expansion mode. the following operating modes can be specified in 1-bit units. (1) port mode these ports function as 4-bit i/o ports. they can be specified as input or output ports in 1-bit units with port mode register 6 (pm6). on-chip pull-up resistors can be used by setting pull-up resistor option register 6 (pu6). (2) control mode these ports function as control signal output pins (rd, wr, wait, astb) in external memory expansion mode. caution when external wait is not used in external memory expansion mode, p66 can be used as an i/o port.
83 chapter 3 pin function ( pd780024a, 780034a subseries) user? manual u14046ej3v0ud 3.2.8 p70 to p75 (port 7) these are 6-bit i/o ports. besides serving as i/o ports, they function as a timer i/o, clock output, and buzzer output. the following operating modes can be specified in 1-bit units. (1) port mode port 7 functions as a 6-bit i/o port. they can be specified as an input port or output port in 1-bit units with port mode register 7 (pm7). on-chip pull-up resistors can be used by setting pull-up resistor option register 7 (pu7). p70 and p71 are also 16-bit timer/event counter 0 capture trigger signal input pins with a valid edge input. (2) control mode port 7 functions as timer i/o, clock output, and buzzer output. (a) ti00 external count clock input pin to 16-bit timer/event counter 0 and capture trigger signal input pin to 16-bit timer/event counter capture register (cr01). (b) ti01 capture trigger signal input pin to 16-bit timer/event counter 0 capture register (cr00). (c) ti50 and ti51 external count clock input pins to 8-bit timer/event counters 50 and 51. (d) to0, to50, and to51 timer output pins. (e) pcl clock output pin. (f) buz buzzer output pin. 3.2.9 av ref this is an a/d converter reference voltage input pin. when no a/d converter is used, connect this pin directly to v ss0 or v ss1 . 3.2.10 av dd this is an analog power supply pin of a/d converter. always use the same potential as that of the v dd0 pin or v dd1 pin even when no a/d converter is used. 3.2.11 av ss this is a ground potential pin of a/d converter. always use the same potential as that of the v ss0 pin or v ss1 pin even when no a/d converter is used.
84 chapter 3 pin function ( pd780024a, 780034a subseries) user? manual u14046ej3v0ud 3.2.12 reset this is a low-level active system reset input pin. 3.2.13 nc nc (non-connection) pin is not internally connected. leave this pin open. 3.2.14 x1 and x2 crystal/ceramic resonator connection pins for main system clock oscillation. for external clock supply, input clock signal to x1 and its inverted signal to x2. 3.2.15 xt1 and xt2 crystal resonator connection pins for subsystem clock oscillation. for external clock supply, input the clock signal to xt1 and its inverted signal to xt2. 3.2.16 v dd0 and v dd1 v dd0 is a positive power supply port pin. v dd1 is a positive power supply pin other than port pin. 3.2.17 v ss0 and v ss1 v ss0 is a ground potential port pin. v ss1 is a ground potential pin other than port pin. 3.2.18 v pp (flash memory versions only) high-voltage apply pin for flash memory programming mode setting and program write/verify. handle in either of the following ways. independently connect a 10 k ? pull-down resistor. set the jumper on the board so that this pin is connected directly to the dedicated flash programmer in programming mode and directly to v ss0 or v ss1 in normal operation mode. when there is a potential difference between the v pp pin and v ss0 pin or v ss1 pin because the wiring between the two pins is too long or external noise is input to the v pp pin, the user program may not operate normally. 3.2.19 ic (mask rom version only) the ic (internally connected) pin is provided to set the test mode to check the pd780024a, 780034a subseries at delivery. connect it directly to the v ss0 or v ss1 pin with the shortest possible wire in the normal operating mode. when a potential difference is produced between the ic pin and v ss0 pin or v ss1 pin, because the wiring between those two pins is too long or an external noise is input to the ic pin, the user? program may not operate normally. ? connect ic pins to v ss0 pins or v ss1 pins directly. as short as possible ic v ss0 or v ss1
85 chapter 3 pin function ( pd780024a, 780034a subseries) user s manual u14046ej3v0ud 3.3 pin i/o circuits and recommended connection of unused pins table 3-1 shows the types of pin i/o circuit and the recommended connections of unused pins. see figure 3-1 for the configuration of the i/o circuit of each type. table 3-1. pin i/o circuit types (1/2) pin name i/o circuit type i/o recommended connection of unused pins p00/intp0 to p02/intp2 8-c i/o input: independently connect to v ss0 or v ss1 via a p03/intp3/adtrg resistor. output: leave open. p10/ani0 to p17/ani7 25 input connect directly to v dd0 , v dd1 , v ss0 , or v ss1 . p20/si30 8-c i/o input: independently connect to v dd0 , v dd1 , v ss0 , p21/so30 5-h or v ss1 via a resistor. p22/sck30 8-c output: leave open. p23/rxd0 p24/txd0 5-h p25/asck0 8-c p30, p31 13-q input: connect directly to v ss0 or v ss1 . (for mask rom version) output: set the output latch of the port to 0, and p30, p31 13-p leave these pins open at low level. (for flash memory version) p32, p33 13-s (for mask rom version) p32, p33 13-r (for flash memory version) p34/si31 8-c input: independently connect to v dd0 , v dd1 , v ss0 , p35/so31 5-h or v ss1 via a resistor. p36/sck31 8-c output: leave open. p40/ad0 to p47/ad7 5-h input: independently connect to v dd0 or v dd1 via a resistor. output: leave open.
86 chapter 3 pin function ( pd780024a, 780034a subseries) user s manual u14046ej3v0ud table 3-1. pin i/o circuit types (2/2) pin name i/o circuit type i/o recommended connection of unused pins p50/a8 to p57/a15 5-h i/o input: independently connect to v dd0 , v dd1 , v ss0 , p64/rd or v ss1 via a resistor. p65/wr output: leave open. p66/wait p67/astb p70/ti00/to0 8-c p71/ti01 p72/ti50/to50 p73/ti51/to51 p74/pcl 5-h p75/buz reset 2 input ? nc note ?? leave open. xt1 16 input connect directly to v dd0 or v dd1 . xt2 ? leave open. av dd ? connect directly to v dd0 or v dd1 . av ref connect directly to v ss0 or v ss1 . av ss ic (for mask rom version) v pp independently connect a 10 k ? pull-down resistor (for flash memory version) to this pin, or connect directly to v ss0 or v ss1 . note the nc pin is available only for a 73-pin plastic fbga.
87 chapter 3 pin function ( pd780024a, 780034a subseries) user s manual u14046ej3v0ud figure 3-1. pin i/o circuit list (1/2) type 2 schmitt-triggered input with hysteresis characteristics in type 8-c data output disable p-ch in/out v dd0 n-ch p-ch v dd0 pullup enable type 5-h data output disable p-ch in/out v dd0 n-ch input enable p-ch v dd0 pullup enable type 13-q data output disable in/out n-ch v dd0 mask option ? ? ? ? ? ? data output disable in/out n-ch data output disable in/out n-ch type 13-p input enable v ss0 input enable v ss0 type 13-r v ss0 v ss0 v ss0
88 chapter 3 pin function ( pd780024a, 780034a subseries) user s manual u14046ej3v0ud figure 3-1. pin i/o circuit list (2/2) p-ch feedback cut-off xt1 xt2 type 13-s type 16 data output disable in/out n-ch input enable comparator + p-ch n-ch v ref (threshold voltage) v ss0 type 25 v ss0 in v dd0 mask option ? ? ? ? ? ?
89 user? manual u14046ej3v0ud chapter 4 pin function ( pd780024ay, 780034ay subseries) 4.1 pin function list (1) port pins (1/2) pin name i/o function after reset alternate function p00 i/o input intp0 p01 intp1 p02 intp2 p03 intp3/adtrg p10 to p17 input port 1 input ani0 to ani7 8-bit input-only port. p20 i/o input si30 p21 so30 p22 sck30 p23 rxd0 p24 txd0 p25 asck0 p30 i/o input ? p31 p32 sda0 p33 scl0 p34 ? p35 p36 p40 to p47 i/o port 4 input ad0 to ad7 8-bit i/o port input/output mode can be specified in 1-bit units. an on-chip pull-up resistor can be used by software settings. interrupt request flag (krif) is set to 1 by falling edge detection. p50 to p57 i/o port 5 input a8 to a15 8-bit i/o port leds can be driven directly. input/output mode can be specified in 1-bit units. an on-chip pull-up resistor can be used by software settings. p64 i/o input rd p65 wr p66 wait p67 astb port 0 4-bit i/o port input/output mode can be specified in 1-bit units. an on-chip pull-up resistor can be used by software settings. port 2 6-bit i/o port input/output mode can be specified in 1-bit units. an on-chip pull-up resistor can be used by software settings. port 3 7-bit i/o port input/output mode can be specified in 1-bit units. n-ch open-drain i/o port on-chip pull-up resistor can be specified by mask option (p30 and p31 are mask rom version only). leds can be driven directly. an on-chip pull-up resistor can be used by software settings. port 6 4-bit i/o port input/output mode can be specified in 1-bit units. an on-chip pull-up resistor can be used by software settings.
90 chapter 4 pin function ( pd780024ay, 780034ay subseries) user? manual u14046ej3v0ud (1) port pins (2/2) (2) non-port pins (1/2) pin name i/o function after reset alternate function p70 i/o input ti00/to0 p71 ti01 p72 ti50/to50 p73 ti51/to51 p74 pcl p75 buz port 7 6-bit i/o port input/output mode can be specified in 1-bit units. an on-chip pull-up resistor can be used by software settings. pin name i/o function after reset alternate function intp0 input input p00 intp1 p01 intp2 p02 intp3 p03/adtrg si30 input serial interface serial data input input p20 so30 output serial interface serial data output input p21 sda0 i/o serial interface serial data input/output input p32 sck30 i/o serial interface serial clock input/output input p22 scl0 p33 rxd0 input asynchronous serial interface serial data input input p23 txd0 output asynchronous serial interface serial data output input p24 asck0 input asynchronous serial interface serial clock input input p25 ti00 input external count clock input to 16-bit timer/event counter 0 input p70/to0 capture trigger input to 16-bit timer/event counter 0 capture register (cr00, cr01) ti01 capture trigger input to 16-bit timer/event counter 0 p71 capture register (cr00) ti50 external count clock input to 8-bit timer/event counter 50 p72/to50 ti51 external count clock input to 8-bit timer/event counter 51 p73/to51 to0 output 16-bit timer/event counter 0 output input p70/ti00 to50 8-bit timer/event counter 50 output input p72/ti50 (also used for 8-bit pwm output) to51 8-bit timer/event counter 51 output p73/ti51 (also used for 8-bit pwm output) pcl output clock output (for main system clock and subsystem clock input p74 trimming) buz output buzzer output input p75 ad0 to ad7 i/o lower address/data bus when expanding external memory input p40 to p47 a8 to a15 output higher address bus when expanding external memory input p50 to p57 rd output strobe signal output for read operation from external memory input p64 wr strobe signal output for write operation from external memory p65 external interrupt request input with specifiable valid edges (rising edge, falling edge, both rising and falling edges)
91 chapter 4 pin function ( pd780024ay, 780034ay subseries) user? manual u14046ej3v0ud pin name i/o function after reset alternate function wait input wait insertion when accessing external memory input p66 astb output strobe output externally latching address information input p67 output to ports 4, 5 to access external memory ani0 to ani7 input a/d converter analog input input p10 to p17 adtrg input a/d converter trigger signal input input p03/intp3 av ref input a/d converter reference voltage input ?? av dd ? a/d converter analog power supply. connect to v dd0 or v dd1 . ?? av ss ? a/d converter ground potential. connect to v ss0 or v ss1 . ?? reset input system reset input input ? x1 input crystal connection for main system clock oscillation ?? x2 ? ?? xt1 input crystal connection for subsystem clock oscillation ?? xt2 ? ?? v dd0 ? positive power supply for ports ?? v dd1 ? positive power supply other than ports ?? v ss0 ? ground potential for ports ?? v ss1 ? ground potential other than ports ?? ic ? internally connected. connect directly to v ss0 or v ss1 . ?? nc note ? not internally connected. leave open. ?? v pp ? high-voltage application for program write/verify. ?? note the nc pin is available only for a 73-pin plastic fbga. (2) non-port pins (2/2)
92 chapter 4 pin function ( pd780024ay, 780034ay subseries) user? manual u14046ej3v0ud 4.2 description of pin functions 4.2.1 p00 to p03 (port 0) these are 4-bit i/o ports. besides serving as i/o ports, they function as an external interrupt input, and a/d converter external trigger input. the following operating modes can be specified in 1-bit units. (1) port mode these ports function as 4-bit i/o ports. p00 to p03 can be specified as input or output ports in 1-bit units with port mode register 0 (pm0). on-chip pull- up resistors can be used by setting pull-up resistor option register 0 (pu0). (2) control mode these ports function as an external interrupt request input, and a/d converter external trigger input. (a) intp0 to intp3 intp0 to intp3 are external interrupt request input pins which can specify valid edges (rising edge, falling edge, and both rising and falling edges). (b) adtrg a/d converter external trigger input pin. caution when p03 is used as an a/d converter external trigger input, specify the valid edge by bits 1, 2 (ega00, ega01) of a/d converter mode register (adm0) and set interrupt mask flag (pmk3) to 1. 4.2.2 p10 to p17 (port 1) these are 8-bit input-only ports. besides serving as input ports, they function as an a/d converter analog input. the following operating modes can be specified in 1-bit units. (1) port mode these ports function as 8-bit input-only ports. (2) control mode these ports function as a/d converter analog input pins (ani0 to ani7).
93 chapter 4 pin function ( pd780024ay, 780034ay subseries) user? manual u14046ej3v0ud 4.2.3 p20 to p25 (port 2) these are 6-bit i/o ports. besides serving as i/o ports, they function as serial interface data i/o and clock i/o. the following operating modes can be specified in 1-bit units. (1) port mode these ports function as 6-bit i/o ports. they can be specified as input or output ports in 1-bit units with port mode register 2 (pm2). on-chip pull-up resistors can be used by setting pull-up resistor option register 2 (pu2). (2) control mode these ports function as data i/o and clock i/o of serial interface sio30 or uart0. (a) si30 and so30 serial data i/o pins of serial interface sio30. (b) sck30 serial clock i/o pin of serial interface sio30. (c) r x d0 and t x d0 serial data i/o pins of serial interface uart0. (d) asck0 serial clock input pin of serial interface uart0. 4.2.4 p30 to p36 (port 3) these are 7-bit i/o ports. besides serving as i/o ports, they function as data i/o and clock i/o of serial interface iic0. p30 to p33 can drive leds directly. the following operating modes can be specified in 1-bit units. (1) port mode these ports function as 7-bit i/o ports. they can be specified as input or output ports in 1-bit units with port mode register 3 (pm3). p30 to p33 are n-ch open-drain i/o port. mask rom version can contain pull-up resistors in p30 and p31 with the mask option. on-chip pull-up resistors of p34 to p36 can be used by setting pull-up resistor option register 3 (pu3). (2) control mode these ports function as data i/o and clock i/o of serial interface iic0. (a) sda0 serial data i/o pin of serial interface iic0. (b) scl0 serial clock i/o pin of serial interface iic0.
94 chapter 4 pin function ( pd780024ay, 780034ay subseries) user? manual u14046ej3v0ud 4.2.5 p40 to p47 (port 4) these are 8-bit i/o ports. besides serving as i/o ports, they function as an address/data bus. the interrupt request flag (krif) can be set to 1 by detecting a falling edge. the following operating mode can be specified in 1-bit units. caution when using the falling edge detection interrupt (intkr), be sure to set the memory expansion mode register (mem) to 01h. (1) port mode these ports function as 8-bit i/o ports. they can be specified as input or output ports in 1-bit units with port mode register 4 (pm4). on-chip pull-up resistors can be used by setting pull-up resistor option register 4 (pu4). (2) control mode these ports function as lower address/data bus pins (ad0 to ad7) in external memory expansion mode. 4.2.6 p50 to p57 (port 5) these are 8-bit i/o ports. besides serving as i/o ports, they function as an address bus. port 5 can drive leds directly. the following operating modes can be specified in 1-bit units. (1) port mode these ports function as 8-bit i/o ports. they can be specified as input or output ports in 1-bit units with port mode register 5 (pm5). on-chip pull-up resistors can be used by setting pull-up resistor option register 5 (pu5). (2) control mode these ports function as higher address bus pins (a8 to a15) in external memory expansion mode. 4.2.7 p64 to p67 (port 6) these are 4-bit i/o ports. besides serving as i/o ports, they are used for control in external memory expansion mode. the following operating modes can be specified in 1-bit units. (1) port mode these ports function as 4-bit i/o ports. they can be specified as input or output ports in 1-bit units with port mode register 6 (pm6). on-chip pull-up resistors can be used by setting pull-up resistor option register 6 (pu6). (2) control mode these ports function as control signal output pins (rd, wr, wait, astb) in external memory expansion mode. caution when external wait is not used in external memory expansion mode, p66 can be used as an i/o port.
95 chapter 4 pin function ( pd780024ay, 780034ay subseries) user? manual u14046ej3v0ud 4.2.8 p70 to p75 (port 7) these are 6-bit i/o ports. besides serving as i/o ports, they function as a timer i/o, clock output, and buzzer output. the following operating modes can be specified in 1-bit units. (1) port mode port 7 functions as a 6-bit i/o port. they can be specified as an input port or output port in 1-bit units with port mode register 7 (pm7). on-chip pull-up resistors can be used by setting pull-up resistor option register 7 (pu7). p70 and p71 are also 16-bit timer/event counter 0 capture trigger signal input pins with a valid edge input. (2) control mode port 7 functions as timer i/o, clock output, and buzzer output. (a) ti00 external count clock input pin to 16-bit timer/event counter 0 and capture trigger signal input pin to 16-bit timer/event counter capture register (cr01). (b) ti01 capture trigger signal input pin to 16-bit timer/event counter 0 capture register (cr00). (c) ti50 and ti51 external count clock input pins to 8-bit timer/event counters 50 and 51. (d) to0, to50, and to51 timer output pins. (e) pcl clock output pin. (f) buz buzzer output pin. 4.2.9 av ref this is an a/d converter reference voltage input pin. when no a/d converter is used, connect this pin directly to v ss0 or v ss1 . 4.2.10 av dd this is an analog power supply pin of a/d converter. always use the same potential as that of the v dd0 pin or v dd1 pin even when no a/d converter is used. 4.2.11 av ss this is a ground potential pin of a/d converter. always use the same potential as that of the v ss0 pin or v ss1 pin even when no a/d converter is used.
96 chapter 4 pin function ( pd780024ay, 780034ay subseries) user? manual u14046ej3v0ud 4.2.12 reset this is a low-level active system reset input pin. 4.2.13 nc nc (non-connection) pin is not internally connected. leave this pin open. 4.2.14 x1 and x2 crystal/ceramic resonator connection pins for main system clock oscillation. for external clock supply, input the clock signal to x1 and its inverted signal to x2. 4.2.15 xt1 and xt2 crystal resonator connection pins for subsystem clock oscillation. for external clock supply, input the clock signal to xt1 and its inverted signal to xt2. 4.2.16 v dd0 and v dd1 v dd0 is a positive power supply pin. v dd1 is a positive power supply pin other than port pin. 4.2.17 v ss0 and v ss1 v ss0 is a ground potential port pin. v ss1 is a ground potential pin other than port pin. 4.2.18 v pp (flash memory versions only) high-voltage apply pin for flash memory programming mode setting and program write/verify. handle in either of the following ways. independently connect a 10 k ? pull-down resistor. set the jumper on the board so that this pin is connected directly to the dedicated flash programmer in programming mode and directly to v ss0 or v ss1 in normal operation mode. when there is a potential difference between the v pp pin and v ss0 pin or v ss1 pin because the wiring between the two pins is too long or external noise is input to the v pp pin, the user program may not operate normally. 4.2.19 ic (mask rom version only) the ic (internally connected) pin is provided to set the test mode to check the pd780024ay, 780034ay subseries at delivery. connect it directly to the v ss0 or v ss1 pin with the shortest possible wire in the normal operating mode. when a potential difference is produced between the ic pin and v ss0 pin or v ss1 pin, because the wiring between those two pins is too long or an external noise is input to the ic pin, the user? program may not operate normally. ? connect ic pins to v ss0 pins or v ss1 pins directly. as short as possible ic v ss0 or v ss1
97 chapter 4 pin function ( pd780024ay, 780034ay subseries) user s manual u14046ej3v0ud 4.3 pin i/o circuits and recommended connection of unused pins table 4-1 shows the types of pin i/o circuit and the recommended connections of unused pins. see figure 4-1 for the configuration of the i/o circuit of each type. table 4-1. pin i/o circuit types (1/2) pin name i/o circuit type i/o recommended connection of unused pins p00/intp0 to p02/intp2 8-c i/o input: independently connect to v ss0 or v ss1 via a p03/intp3/adtrg resistor. output: leave open. p10/ani0 to p17/ani7 25 input connect directly to v dd0 , v dd1 , v ss0 , or v ss1 . p20/si30 8-c i/o input: independently connect to v dd0 , v dd1 , v ss0 , p21/so30 5-h or v ss1 via a resistor. p22/sck30 8-c output: leave open. p23/rxd0 p24/txd0 5-h p25/asck0 8-c p30, p31 13-q input: connect directly to v ss0 or v ss1 . (for mask rom version) output: set the output latch of the port to 0, and p30, p31 13-p leave these pins open at low level. (for flash memory version) p32/sda0 13-r p33/scl0 p34 8-c input: independently connect to v dd0 , v dd1 , v ss0 , p35 5-h or v ss1 via a resistor. p36 8-c output: leave open. p40/ad0 to p47/ad7 5-h input: independently connect to v dd0 or v dd1 via a resistor. output: leave open.
98 chapter 4 pin function ( pd780024ay, 780034ay subseries) user s manual u14046ej3v0ud table 4-1. pin i/o circuit types (2/2) pin name i/o circuit type i/o recommended connection of unused pins p50/a8 to p57/a15 5-h i/o input: independently connect to v dd0 , v dd1 , v ss0 , p64/rd or v ss1 via a resistor. p65/wr output: leave open. p66/wait p67/astb p70/ti00/to0 8-c p71/ti01 p72/ti50/to50 p73/ti51/to51 p74/pcl 5-h p75/buz reset 2 input ? nc note ?? leave open. xt1 16 input connect directly to v dd0 or v dd1 . xt2 ? leave open. av dd ? connect directly to v dd0 or v dd1 . av ref connect directly to v ss0 or v ss1 . av ss ic (for mask rom version) v pp independently connect a 10 k ? pull-down resistor (for flash memory version) to this pin, or connect directly to v ss0 or v ss1 . note the nc pin is available only for a 73-pin plastic fbga.
99 chapter 4 pin function ( pd780024ay, 780034ay subseries) user s manual u14046ej3v0ud figure 4-1. pin i/o circuit list (1/2) type 2 schmitt-triggered input with hysteresis characteristics in type 8-c data output disable p-ch in/out v dd0 n-ch p-ch v dd0 pullup enable type 5-h data output disable p-ch in/out v dd0 n-ch input enable p-ch v dd0 pullup enable type 13-q data output disable in/out n-ch v dd0 mask option ? ? ? ? ? ? data output disable in/out n-ch data output disable in/out n-ch type 13-p input enable v ss0 input enable v ss0 type 13-r v ss0 v ss0 v ss0
100 chapter 4 pin function ( pd780024ay, 780034ay subseries) user s manual u14046ej3v0ud figure 4-1. pin i/o circuit list (2/2) p-ch feedback cut-off xt1 xt2 type 16 input enable comparator + p-ch n-ch v ref (threshold voltage) type 25 v ss0 in
101 user? manual u14046ej3v0ud chapter 5 cpu architecture 5.1 memory spaces pd780024a, 780034a, 780024ay, 780034ay subseries can access 64 kb memory space respectively. figures 5-1 to 5-5 show memory maps. caution in case of the internal memory capacity, the initial value of memory size switching register (ims) of all products ( pd780024a, 780034a, 780024ay, and 780034ay subseries) is fixed (ims = cfh). therefore, set the value corresponding to each product indicated below. pd780021a, 780031a, 780021ay, 780031ay: 42h pd780022a, 780032a, 780022ay, 780032ay: 44h pd780023a, 780033a, 780023ay, 780033ay: c6h pd780024a, 780034a, 780024ay, 780034ay: c8h pd78f0034a, 78f0034b, 78f0034ay, 78f0034by: value for mask rom version figure 5-1. memory map ( pd780021a, 780031a, 780021ay, 780031ay) 0000h data memory space general-purpose registers 32 8 bits internal rom 8192 8 bits 1fffh 1000h 0fffh 0800h 07ffh 0080h 007fh 0040h 003fh 0000h callf entry area callt table area vector table area program area program area external memory 55296 8 bits program memory space 2000h 1fffh f800h f7ffh fee0h fedfh ff00h feffh ffffh internal high-speed ram 512 8 bits special function registers (sfrs) 256 8 bits reserved fd00h fcffh
102 chapter 5 cpu architecture user s manual u14046ej3v0ud figure 5-2. memory map ( pd780022a, 780032a, 780022ay, 780032ay) 0000h data memory space general-purpose registers 32 8 bits internal rom 16384 8 bits 3fffh 1000h 0fffh 0800h 07ffh 0080h 007fh 0040h 003fh 0000h callf entry area callt table area vector table area program area program area external memory 47104 8 bits program memory space 4000h 3fffh f800h f7ffh fee0h fedfh ff00h feffh ffffh internal high-speed ram 512 8 bits special function registers (sfrs) 256 8 bits reserved fd00h fcffh
103 chapter 5 cpu architecture user s manual u14046ej3v0ud figure 5-3. memory map ( pd780023a, 780033a, 780023ay, 780033ay) 0000h data memory space general-purpose registers 32 8 bits internal rom 24576 8 bits 5fffh 1000h 0fffh 0800h 07ffh 0080h 007fh 0040h 003fh 0000h callf entry area callt table area vector table area program area program area external memory 38912 8 bits program memory space 6000h 5fffh f800h f7ffh fee0h fedfh ff00h feffh ffffh internal high-speed ram 1024 8 bits special function registers (sfrs) 256 8 bits reserved fb00h faffh
104 chapter 5 cpu architecture user s manual u14046ej3v0ud figure 5-4. memory map ( pd780024a, 780034a, 780024ay, 780034ay) 0000h data memory space internal rom 32768 8 bits 7fffh 1000h 0fffh 0800h 07ffh 0080h 007fh 0040h 003fh 0000h callf entry area callt table area vector table area program area program area external memory 30720 8 bits program memory space 8000h 7fffh f800h f7ffh fee0h fedfh ff00h feffh ffffh internal high-speed ram 1024 8 bits special function registers (sfrs) 256 8 bits reserved fb00h faffh general-purpose registers 32 8 bits
105 chapter 5 cpu architecture user s manual u14046ej3v0ud figure 5-5. memory map ( pd78f0034a, 78f0034b, 78f0034ay, 78f0034by) 0000h data memory space general-purpose registers 32 8 bits flash memory 32768 8 bits 7fffh 1000h 0fffh 0800h 07ffh 0080h 007fh 0040h 003fh 0000h callf entry area callt table area vector table area program area program area external memory 30720 8 bits program memory space 8000h 7fffh f800h f7ffh fee0h fedfh ff00h feffh ffffh internal high-speed ram 1024 8 bits special function registers (sfrs) 256 8 bits reserved fb00h faffh
106 chapter 5 cpu architecture user s manual u14046ej3v0ud 5.1.1 internal program memory space the internal program memory space contains the program and table data. normally, it is addressed with the program counter (pc). the pd780024a, 780034a, 780024ay, and 780034ay subseries products incorporate an on-chip rom (mask rom or flash memory), as listed below. table 5-1. internal rom capacity part number type capacity pd780021a, 780031a, 780021ay, 780031ay mask rom 8192 8 bits (0000h to 1fffh) pd780022a, 780032a, 780022ay, 780032ay 16384 8 bits (0000h to 3fffh) pd780023a, 780033a, 780023ay, 780033ay 24576 8 bits (0000h to 5fffh) pd780024a, 780034a, 780024ay, 780034ay 32768 8 bits (0000h to 7fffh) pd78f0034a, 78f0034b, 78f0034ay, 78f0034by flash memory 32768 8 bits (0000h to 7fffh) the internal program memory space is divided into the following three areas.
107 chapter 5 cpu architecture user s manual u14046ej3v0ud (1) vector table area the 64-byte area 0000h to 003fh is reserved as a vector table area. the reset input and program start addresses for branch upon generation of each interrupt request are stored in the vector table area. of the 16- bit address, lower 8 bits are stored at even addresses and higher 8 bits are stored at odd addresses. table 5-2. vector table vector table address interrupt source 0000h reset input 0004h intwdt 0006h intp0 0008h intp1 000ah intp2 000ch intp3 000eh intser0 0010h intsr0 0012h intst0 0014h intcsi30 0016h intcsi31 note 1 0018h intiic0 note 2 001ah intwti 001ch inttm00 001eh inttm01 0020h inttm50 0022h inttm51 0024h intad0 0026h intwt 0028h intkr 003eh brk notes 1. pd780024a, 780034a subseries only 2. pd780024ay, 780034ay subseries only (2) callt instruction table area the 64-byte area 0040h to 007fh can store the subroutine entry address of a 1-byte call instruction (callt). (3) callf instruction entry area the area 0800h to 0fffh can perform a direct subroutine call with a 2-byte call instruction (callf).
108 chapter 5 cpu architecture user s manual u14046ej3v0ud 5.1.2 internal data memory space the pd780024a, 780034a, 780024ay, and 780034ay subseries products incorporate an internal high-speed ram, as listed below. table 5-3. internal high-speed ram capacity part number internal high-speed ram pd780021a, 780031a, 780021ay, 780031ay 512 8 bits (fd00h to feffh) pd780022a, 780032a, 780022ay, 780032ay pd780023a, 780033a, 780023ay, 780033ay 1024 8 bits (fb00h to feffh) pd780024a, 780034a, 780024ay, 780034ay pd78f0034a, 78f0034b, 78f0034ay, 78f0034by the 32-byte area fee0h to feffh is allocated four general-purpose register banks composed of eight 8-bit registers. this area cannot be used as a program area in which instructions are written and executed. the internal high-speed ram can also be used as a stack memory. 5.1.3 special function register (sfr) area an on-chip peripheral hardware special function register (sfr) is allocated in the area ff00h to ffffh (see 5.2.3 special function register (sfr) table 5-5 special function register list ). caution do not access addresses where the sfr is not assigned. 5.1.4 external memory space the external memory space is accessible with memory expansion mode register (mem). external memory space can store program, table data, etc., and allocate peripheral devices.
109 chapter 5 cpu architecture user s manual u14046ej3v0ud 5.1.5 data memory addressing addressing refers to the method of specifying the address of the instruction to be executed next or the address of the register or memory relevant to the execution of instructions. several addressing modes are provided for addressing the memory relevant to the execution of instructions for the pd780024a, 780034a, 780024ay, and 780034ay subseries, based on operability and other considerations. for areas containing data memory in particular, special addressing methods designed for the functions of special function registers (sfr) and general-purpose registers are available for use. correspondence between data memory and addressing is illustrated in figures 5-6 to 5-10. for the details of each addressing mode, see 5.4 operand address addressing . figure 5-6. correspondence between data memory and addressing ( pd780021a, 780031a, 780021ay, 780031ay) 0000h general-purpose registers 32 8 bits internal rom 8192 8 bits external memory 55296 8 bits 2000h 1fffh f800h f7ffh fee0h fedfh ff00h feffh ffffh internal high-speed ram 512 8 bits reserved fd00h fcffh ff20h ff1fh fe20h fe1fh special function registers (sfrs) 256 8 bits sfr addressing register addressing short direct addressing direct addressing register indirect addressing based addressing based indexed addressing
110 chapter 5 cpu architecture user s manual u14046ej3v0ud figure 5-7. correspondence between data memory and addressing ( pd780022a, 780032a, 780022ay, 780032ay) 0000h general-purpose registers 32 8 bits internal rom 16384 8 bits external memory 47104 8 bits 4000h 3fffh f800h f7ffh fee0h fedfh ff00h feffh ffffh internal high-speed ram 512 8 bits reserved fd00h fcffh ff20h ff1fh fe20h fe1fh special function registers (sfrs) 256 8 bits sfr addressing register addressing short direct addressing direct addressing register indirect addressing based addressing based indexed addressing
111 chapter 5 cpu architecture user s manual u14046ej3v0ud figure 5-8. correspondence between data memory and addressing ( pd780023a, 780033a, 780023ay, 780033ay) 0000h general-purpose registers 32 8 bits internal rom 24576 8 bits external memory 38912 8 bits 6000h 5fffh f800h f7ffh fee0h fedfh ff00h feffh ffffh internal high-speed ram 1024 8 bits reserved fb00h faffh ff20h ff1fh fe20h fe1fh special function registers (sfrs) 256 8 bits sfr addressing register addressing short direct addressing direct addressing register indirect addressing based addressing based indexed addressing
112 chapter 5 cpu architecture user s manual u14046ej3v0ud figure 5-9. correspondence between data memory and addressing ( pd780024a, 780034a, 780024ay, 780034ay) 0000h general-purpose registers 32 8 bits internal rom 32768 8 bits external memory 30720 8 bits 8000h 7fffh f800h f7ffh fee0h fedfh ff00h feffh ffffh internal high-speed ram 1024 8 bits reserved fb00h faffh ff20h ff1fh fe20h fe1fh special function registers (sfrs) 256 8 bits sfr addressing register addressing short direct addressing direct addressing register indirect addressing based addressing based indexed addressing
113 chapter 5 cpu architecture user s manual u14046ej3v0ud figure 5-10. correspondence between data memory and addressing ( pd78f0034a, 78f0034b, 78f0034ay, 78f0034by) 0000h general-purpose registers 32 8 bits flash memory 32768 8 bits external memory 30720 8 bits 8000h 7fffh f800h f7ffh fee0h fedfh ff00h feffh ffffh internal high-speed ram 1024 8 bits reserved fb00h faffh ff20h ff1fh fe20h fe1fh special function registers (sfrs) 256 8 bits sfr addressing register addressing short direct addressing direct addressing register indirect addressing based addressing based indexed addressing
114 chapter 5 cpu architecture user s manual u14046ej3v0ud 5.2 processor registers the pd780024a, 780034a, 780024ay, 780034ay subseries products incorporate the following processor registers. 5.2.1 control registers the control registers control the program sequence, statuses and stack memory. the control registers consist of a program counter (pc), a program status word (psw) and a stack pointer (sp). (1) program counter (pc) the program counter is a 16-bit register which holds the address information of the next program to be executed. in normal operation, the pc is automatically incremented according to the number of bytes of the instruction to be fetched. when a branch instruction is executed, immediate data and register contents are set. reset input sets the reset vector table values at addresses 0000h and 0001h to the program counter. figure 5-11. program counter format 15 0 pc pc15 pc14 pc13 pc12 pc11 pc10 pc9 pc8 pc7 pc6 pc5 pc4 pc3 pc2 pc1 pc0 (2) program status word (psw) the program status word is an 8-bit register consisting of various flags to be set/reset by instruction execution. program status word contents are automatically stacked upon interrupt request generation or push psw instruction execution and are automatically reset upon execution of the retb, reti and pop psw instructions. reset input sets the psw to 02h. figure 5-12. program status word format 70 psw ie z rbs1 ac rbs0 0 isp cy
115 chapter 5 cpu architecture user s manual u14046ej3v0ud (a) interrupt enable flag (ie) this flag controls the interrupt request acknowledge operations of the cpu. when 0, the ie is set to the disable interrupt (di) state, and only non-maskable interrupt request becomes acknowledgeable. other interrupt requests are all disabled. when 1, the ie is set to the enable interrupt (ei) state and interrupt request acknowledge enable is controlled with an in-service priority flag (isp), an interrupt mask flag for various interrupt sources and a priority specification flag. the ie is reset (0) upon di instruction execution or interrupt acknowledgment and is set (1) upon ei instruction execution. (b) zero flag (z) when the operation result is zero, this flag is set (1). it is reset (0) in all other cases. (c) register bank select flags (rbs0 and rbs1) these are 2-bit flags to select one of the four register banks. in these flags, the 2-bit information which indicates the register bank selected by sel rbn instruction execution is stored. (d) auxiliary carry flag (ac) if the operation result has a carry from bit 3 or a borrow at bit 3, this flag is set (1). it is reset (0) in all other cases. (e) in-service priority flag (isp) this flag manages the priority of acknowledgeable maskable vectored interrupts. when this flag is 0, low- level vectored interrupt requests specified with a priority specification flag register (pr0l, pr0h, pr1l) (see 19.3 (3) priority specification flag registers (pr0l, pr0h, pr1l) ) are disabled for acknowledgment. when it is 1, all interrupts are acknowledgeable. actual request acknowledgment is controlled with the interrupt enable flag (ie). (f) carry flag (cy) this flag stores overflow and underflow upon add/subtract instruction execution. it stores the shift-out value upon rotate instruction execution and functions as a bit accumulator during bit manipulation instruction execution. (3) stack pointer (sp) this is a 16-bit register to hold the start address of the memory stack area. only the internal high-speed ram area can be set as the stack area. the internal high-speed ram areas of each product are as follows. table 5-4. internal high-speed ram area part number internal high-speed ram area pd780021a, 780031a, 780021ay, 780031ay fd00h to feffh pd780022a, 780032a, 780022ay, 780032ay pd780023a, 780033a, 780023ay, 780033ay fb00h to feffh pd780024a, 780034a, 780024ay, 780034ay pd78f0034a, 78f0034b, 78f0034ay, 78f0034by
116 chapter 5 cpu architecture user s manual u14046ej3v0ud figure 5-13. stack pointer format 15 0 sp sp15 sp14 sp13 sp12 sp11 sp10 sp9 sp8 sp7 sp6 sp5 sp4 sp3 sp2 sp1 sp0 the sp is decremented ahead of write (save) to the stack memory and is incremented after read (restore) from the stack memory. each stack operation saves/restores data as shown in figures 5-14 and 5-15. caution since reset input makes the sp contents undefined, be sure to initialize the sp before using the stack. figure 5-14. data to be saved to stack memory (a) push rp instruction (when sp is fee0h) (b) call, callf, callt instructions (when sp is fee0h) (c) interrupt, brk instruction (when sp is fee0h) fee0h fee0h fedfh fedeh pc15 to pc8 pc7 to pc0 fedeh sp sp fee0h fee0h fedfh fedeh psw pc15 to pc8 feddh sp sp feddh pc7 to pc0 fee0h register pair higher register pair lower fedeh sp sp fee0h fedfh fedeh
117 chapter 5 cpu architecture user s manual u14046ej3v0ud figure 5-15. data to be restored from stack memory (a) pop rp instruction (when sp is fedeh) (b) ret instruction (when sp is fedeh) (c) reti, retb instructions (when sp is feddh) fee0h register pair higher register pair lower fedeh sp sp fee0h fedfh fedeh fee0h fee0h fedfh fedeh pc15 to pc8 pc7 to pc0 fedeh sp sp fee0h fee0h fedfh fedeh psw pc15 to pc8 feddh sp sp feddh pc7 to pc0
118 chapter 5 cpu architecture user s manual u14046ej3v0ud 5.2.2 general-purpose registers a general-purpose register is mapped at particular addresses (fee0h to feffh) of the data memory. it consists of 4 banks, each bank consisting of eight 8-bit registers (x, a, c, b, e, d, l, and h). each register can also be used as an 8-bit register. two 8-bit registers can be used in pairs as a 16-bit register (ax, bc, de, and hl). they can be described in terms of function names (x, a, c, b, e, d, l, h, ax, bc, de, and hl) and absolute names (r0 to r7 and rp0 to rp3). register banks to be used for instruction execution are set with the cpu control instruction (sel rbn). because of the 4-register bank configuration, an efficient program can be created by switching between a register for normal processing and a register for interrupts for each bank. figure 5-16. general-purpose register configuration (a) absolute name (b) function name bank0 bank1 bank2 bank3 feffh fef8h fee0h hl de bc ax h 15 0 7 0 l d e b c a x 16-bit processing 8-bit processing fef0h fee8h bank0 bank1 bank2 bank3 feffh fef8h fee0h rp3 rp2 rp1 rp0 r7 15 0 7 0 r6 r5 r4 r3 r2 r1 r0 16-bit processing 8-bit processing fef0h fee8h
119 chapter 5 cpu architecture user s manual u14046ej3v0ud 5.2.3 special function register (sfr) unlike a general-purpose register, each special function register has special functions. it is allocated in the ff00h to ffffh area. the special function register can be manipulated like the general-purpose register, with the operation, transfer and bit manipulation instructions. manipulatable bit units, 1, 8, and 16, depend on the special function register type. each manipulation bit unit can be specified as follows. 1-bit manipulation describe the symbol reserved with assembler for the 1-bit manipulation instruction operand (sfr.bit). this manipulation can also be specified with an address. 8-bit manipulation describe the symbol reserved with assembler for the 8-bit manipulation instruction operand (sfr). this manipulation can also be specified with an address. 16-bit manipulation describe the symbol reserved with assembler for the 16-bit manipulation instruction operand (sfrp). when addressing an address, describe an even address. table 5-5 gives a list of special function registers. the meaning of items in the table is as follows. symbol symbol indicating the address of a special function register. it is a reserved word in the ra78k0, and is defined via the header file sfrbit.h in the cc78k0. when using the ra78k0, id78k0-ns, id78k0, or sm78k0, symbols can be written as an instruction operand. r/w indicates whether the corresponding special function register can be read or written. r/w: read/write enable r: read only w: write only manipulatable bit units indicates the manipulatable bit unit (1, 8, or 16). indicates a bit unit for which manipulation is not possible. after reset indicates each register status upon reset input.
120 chapter 5 cpu architecture user s manual u14046ej3v0ud table 5-5. special function register list (1/3) address special function register (sfr) name symbol r/w manipulatable bit unit after reset 1 bit 8 bits 16 bits ff00h port 0 p0 r/w ?? 00h ff01h port 1 p1 r ?? ff02h port 2 p2 r/w ?? ff03h port 3 p3 ?? ff04h port 4 p4 ?? ff05h port 5 p5 ?? ff06h port 6 p6 ?? ff07h port 7 p7 ?? ff0ah 16-bit timer capture/compare register 00 cr00 ?? undefined ff0bh ff0ch 16-bit timer capture/compare register 01 cr01 ?? ff0dh ff0eh 16-bit timer counter 0 tm0 r ?? 0000h ff0fh ff10h 8-bit timer compare register 50 cr50 r/w ?? undefined ff11h 8-bit timer compare register 51 cr51 ?? ff12h 8-bit timer counter 50 tm5 tm50 r ?? 00h ff13h 8-bit timer counter 51 tm51 ? ff16h a/d conversion result register 0 adcr0 ?? note 2 ff17h ? note 1 ff18h transmit shift register 0 txs0 w ?? ffh receive buffer register 0 rxb0 r ?? ff1ah serial i/o shift register 30 sio30 r/w ?? undefined ff1bh serial i/o shift register 31 note 3 sio31 ?? ff1fh iic shift register 0 note 4 iic0 ?? 00h notes 1. pd780024a, 780024ay subseries only 2. pd780034a, 780034ay subseries only, 16-bit access possible 3. pd780024a, 780034a subseries only 4. pd780024ay, 780034ay subseries only
121 chapter 5 cpu architecture user s manual u14046ej3v0ud table 5-5. special function register list (2/3) address special function register (sfr) name symbol r/w manipulatable bit unit after reset 1 bit 8 bits 16 bits ff20h port mode register 0 pm0 r/w ?? ffh ff22h port mode register 2 pm2 ?? ff23h port mode register 3 pm3 ?? ff24h port mode register 4 pm4 ?? ff25h port mode register 5 pm5 ?? ff26h port mode register 6 pm6 ?? ff27h port mode register 7 pm7 ?? ff30h pull-up resistor option register 0 pu0 ?? 00h ff32h pull-up resistor option register 2 pu2 ?? ff33h pull-up resistor option register 3 pu3 ?? ff34h pull-up resistor option register 4 pu4 ?? ff35h pull-up resistor option register 5 pu5 ?? ff36h pull-up resistor option register 6 pu6 ?? ff37h pull-up resistor option register 7 pu7 ?? ff40h clock output select register cks ?? ff41h watch timer operation mode register wtm ?? ff42h watchdog timer clock select register wdcs ?? ff47h memory expansion mode register mem ?? ff48h external interrupt rising edge enable register egp ?? ff49h external interrupt falling edge enable register egn ?? ff60h 16-bit timer mode control register 0 tmc0 ?? ff61h prescaler mode register 0 prm0 ?? ff62h capture/compare control register 0 crc0 ?? ff63h 16-bit timer output control register 0 toc0 ?? ff70h 8-bit timer mode control register 50 tmc50 ?? ff71h timer clock select register 50 tcl50 ?? ff78h 8-bit timer mode control register 51 tmc51 ?? ff79h timer clock select register 51 tcl51 ?? ff80h a/d converter mode register 0 adm0 ?? ff81h analog input channel specification register 0 ads0 ?? ffa0h asynchronous serial interface mode register 0 asim0 ?? ffa1h asynchronous serial interface status register 0 asis0 r ?? ffa2h baud rate generator control register 0 brgc0 r/w ??
122 chapter 5 cpu architecture user s manual u14046ej3v0ud table 5-5. special function register list (3/3) address special function register (sfr) name symbol r/w manipulatable bit unit after reset 1 bit 8 bits 16 bits ffa8h iic control register 0 note 1 iicc0 r/w ?? 00h ffa9h iic status register 0 note 1 iics0 r ?? ffaah iic transfer clock select register 0 note 1 iiccl0 r/w ?? ffabh slave address register 0 note 1 sva0 ?? ffb0h serial operation mode register 30 csim30 ?? ffb8h serial operation mode register 31 note 2 csim31 ?? ffe0h interrupt request flag register 0l if0 if0l ?? ffe1h interrupt request flag register 0h if0h ? ffe2h interrupt request flag register 1l if1l ?? ffe4h interrupt mask flag register 0l mk0 mk0l ?? ffh ffe5h interrupt mask flag register 0h mk0h ? ffe6h interrupt mask flag register 1l mk1l ?? ffe8h priority level specification flag register 0l pr0 pr0l ?? ffe9h priority level specification flag register 0h pr0h ? ffeah priority level specification flag register 1l pr1l ?? fff0h memory size switching register ims ?? cfh note 3 fff8h memory expansion wait setting register mm ?? 10h fff9h watchdog timer mode register wdtm ?? 00h fffah oscillation stabilization time select register osts ?? 04h fffbh processor clock control register pcc ?? notes 1. pd780024ay, 780034ay subseries only 2. pd780024a, 780034a subseries only 3. the default is cfh, but set the value corresponding to each respective product as indicated below. pd780021a, 780031a, 780021ay, 780031ay: 42h pd780022a, 780032a, 780022ay, 780032ay: 44h pd780023a, 780033a, 780023ay, 780033ay: c6h pd780024a, 780034a, 780024ay, 780034ay: c8h pd78f0034a, 78f0034b, 78f0034ay, 78f0034by: value for mask rom version
123 chapter 5 cpu architecture user s manual u14046ej3v0ud 5.3 instruction address addressing an instruction address is determined by program counter (pc) contents and is normally incremented (+1 for each byte) automatically according to the number of bytes of an instruction to be fetched each time another instruction is executed. when a branch instruction is executed, the branch destination information is set to the pc and branched by the following addressing (for details of instructions, refer to 78k/0 series instructions user? manual (u12326e) ). 5.3.1 relative addressing [function] the value obtained by adding 8-bit immediate data (displacement value: jdisp8) of an instruction code to the start address of the following instruction is transferred to the program counter (pc) and branched. the displacement value is treated as signed two s complement data ( 128 to +127) and bit 7 becomes a sign bit. in other words, relative addressing consists in relative branching from the start address of the following instruction to the 128 to +127 range. this function is carried out when the br $addr16 instruction or a conditional branch instruction is executed. [illustration] 15 0 pc + 15 0 876 s 15 0 pc jdisp8 when s = 0, all bits of are 0. when s = 1, all bits of are 1. pc indicates the start address of the instruction after the br instruction. ...
124 chapter 5 cpu architecture user s manual u14046ej3v0ud 5.3.2 immediate addressing [function] immediate data in the instruction word is transferred to the program counter (pc) and branched. this function is carried out when the call !addr16 or br !addr16 or callf !addr11 instruction is executed. call !addr16 and br !addr16 instructions can be branched to the entire memory space. the callf !addr11 instruction is branched to the 0800h to 0fffh area. [illustration] in the case of call !addr16 and br !addr16 instructions in the case of callf !addr11 instruction 15 0 pc 87 70 fa 10 8 11 10 00001 643 callf fa 7 0 15 0 pc 87 70 call or br low addr. high addr.
125 chapter 5 cpu architecture user s manual u14046ej3v0ud 15 1 15 0 pc 70 low addr. high addr. memory (table) effective address+1 effective address 01 00000000 87 87 65 0 0 1 11 765 10 ta 4 0 operation code 5.3.3 table indirect addressing [function] table contents (branch destination address) of the particular location to be addressed by bits 1 to 5 of the immediate data of an operation code are transferred to the program counter (pc) and branched. this function is carried out when the callt [addr5] instruction is executed. this instruction references the address stored in the memory table from 40h to 7fh, and allows branching to the entire memory space. [illustration]
126 chapter 5 cpu architecture user s manual u14046ej3v0ud 5.3.4 register addressing [function] register pair (ax) contents to be specified with an instruction word are transferred to the program counter (pc) and branched. this function is carried out when the br ax instruction is executed. [illustration] 70 rp 07 ax 15 0 pc 87
127 chapter 5 cpu architecture user s manual u14046ej3v0ud 5.4 operand address addressing the following various methods are available to specify the register and memory (addressing) which undergo manipulation during instruction execution. 5.4.1 implied addressing [function] the register which functions as an accumulator (a and ax) in the general-purpose register is automatically (implicitly) addressed. of the pd780024a, 780034a, 780024ay, 780034ay subseries instruction words, the following instructions employ implied addressing. instruction register to be specified by implied addressing mulu a register for multiplicand and ax register for product storage divuw ax register for dividend and quotient storage adjba/adjbs a register for storage of numeric values which become decimal correction targets ror4/rol4 a register for storage of digit data which undergoes digit rotation [operand format] because implied addressing can be automatically employed with an instruction, no particular operand format is necessary. [description example] in the case of mulu x with an 8-bit 8-bit multiply instruction, the product of a register and x register is stored in ax. in this example, the a and ax registers are specified by implied addressing.
128 chapter 5 cpu architecture user s manual u14046ej3v0ud 5.4.2 register addressing [function] the general-purpose register to be specified is accessed as an operand with the register specify code (rn and rpn) of an instruction word in the registered bank specified with the register bank select flag (rbs0 and rbs1). register addressing is carried out when an instruction with the following operand format is executed. when an 8-bit register is specified, one of the eight registers is specified with 3 bits in the operation code. [operand format] identifier description r x, a, c, b, e, d, l, h rp ax, bc, de, hl r and rp can be described with absolute names (r0 to r7 and rp0 to rp3) as well as function names (x, a, c, b, e, d, l, h, ax, bc, de, and hl). [description example] mov a, c; when selecting c register as r operation code 01100010 register specify code incw de; when selecting de register pair as rp operation code 10000100 register specify code
129 chapter 5 cpu architecture user s manual u14046ej3v0ud 5.4.3 direct addressing [function] the memory to be manipulated is addressed with immediate data in an instruction word becoming an operand address. [operand format] identifier description addr16 label or 16-bit immediate data [description example] mov a, !0fe00h; when setting !addr16 to fe00h operation code 10001110 op code 00000000 00h 11111110 feh [illustration] memory 0 7 addr16 (lower) addr16 (upper) op code
130 chapter 5 cpu architecture user s manual u14046ej3v0ud 5.4.4 short direct addressing [function] the memory to be manipulated in the fixed space is directly addressed with 8-bit data in an instruction word. this addressing is applied to the 256-byte space fe20h to ff1fh. internal ram and special function registers (sfrs) are mapped at fe20h to feffh and ff00h to ff1fh, respectively. if the sfr area (ff00h to ff1fh) where short direct addressing is applied, ports which are frequently accessed in a program and compare and capture registers of the timer/event counter are mapped, and these sfrs can be manipulated with a small number of bytes and clocks. when 8-bit immediate data is at 20h to ffh, bit 8 of an effective address is cleared to 0. when it is at 00h to 1fh, bit 8 is set to 1. see the [illustration] below. [operand format] identifier description saddr label or immediate data indicating fe20h to ff1fh saddrp label or immediate data indicating fe20h to ff1fh (even address only) [description example] mov 0fe30h, a; when transferring the value in register a to saddr (fe30h) operation code 11110010 op code 00110000 30h (saddr-offset) [illustration] when 8-bit immediate data is 20h to ffh, = 0 when 8-bit immediate data is 00h to 1fh, = 1 15 0 short direct memory effective address 1 111111 87 0 7 op code saddr-offset
131 chapter 5 cpu architecture user s manual u14046ej3v0ud 15 0 sfr effective address 1 111111 87 0 7 op code sfr-offset 1 5.4.5 special function register (sfr) addressing [function] the memory-mapped special function register (sfr) is addressed with 8-bit immediate data in an instruction word. this addressing is applied to the 240-byte spaces ff00h to ffcfh and ffe0h to ffffh. however, the sfr mapped at ff00h to ff1fh can be accessed with short direct addressing. [operand format] identifier description sfr special function register name sfrp 16-bit manipulatable special function register name (even address only) [description example] mov pm0, a; when selecting pm0 (ff20h) as sfr operation code 11110110 op code 00100000 20h (sfr-offset) [illustration]
132 chapter 5 cpu architecture user s manual u14046ej3v0ud 5.4.6 register indirect addressing [function] register pair contents specified with a register pair specify code in an instruction word of the register bank specified with a register bank select flag (rbs0 and rbs1) serve as an operand address for addressing the memory to be manipulated. this addressing can be carried out for all the memory spaces. [operand format] identifier description ? [de], [hl] [description example] mov a, [de]; when selecting [de] as register pair operation code 10000101 [illustration] 16 0 8 d 7 e 0 7 7 0 a de the contents of the memory addressed are transferred. memory the memory address specified with the register pair de
133 chapter 5 cpu architecture user s manual u14046ej3v0ud 5.4.7 based addressing [function] 8-bit immediate data is added as offset data to the contents of the base register, that is, the hl register pair in an instruction word of the register bank specified by the register bank select flags (rbs0 and rbs1) and the sum is used to address the memory. addition is performed by expanding the offset data as a positive number to 16 bits. a carry from the 16th bit is ignored. this addressing can be carried out for all the memory spaces. [operand format] identifier description ? [hl + byte] [description example] mov a, [hl + 10h]; when setting byte to 10h operation code 10101110 00010000 [illustration] hl 16 0 8 7 hl a 70 70 memory the contents of the memory addressed are transferred. +10
134 chapter 5 cpu architecture user s manual u14046ej3v0ud 5.4.8 based indexed addressing [function] the b or c register contents specified in an instruction word are added to the contents of the base register, that is, the hl register pair in the register bank specified by the register bank select flags (rbs0 and rbs1) and the sum is used to address the memory. addition is performed by expanding the b or c register contents as a positive number to 16 bits. a carry from the 16th bit is ignored. this addressing can be carried out for all the memory spaces. [operand format] identifier description ? [hl + b], [hl + c] [description example] in the case of mov a, [hl + b] (selecting the b register) operation code 10101011 [illustration] hl 16 0 8 7 hl a 70 70 memory 70 + b ? ? ? ? ? the contents of the memory addressed are transferred.
135 chapter 5 cpu architecture user s manual u14046ej3v0ud 5.4.9 stack addressing [function] the stack area is indirectly addressed with the stack pointer (sp) contents. this addressing method is automatically employed when the push, pop, subroutine call and return instructions are executed or the register is saved/reset upon generation of an interrupt request. stack addressing can be used to address the internal high-speed ram area only. [description example] in the case of push de (saving the de register) operation code 10110101 [illustration] fee0h fee0h fedfh fedeh d e fedeh sp sp 7 0 memory
136 user? manual u14046ej3v0ud chapter 6 port functions 6.1 port functions the pd780024a, 780034a, 780024ay, and 780034ay subseries products incorporate eight input ports and 43 i/o ports. figure 6-1 shows the port configuration. every port is capable of 1-bit and 8-bit manipulations and can carry out considerably varied control operations. besides port functions, the ports can also serve as on-chip hardware i/o pins. figure 6-1. port types ? ? ? ? ? port 0 p00 ? ? ? ? ? ? ? ? ? port 1 p10 p17 ? ? ? ? ? ? ? port 2 p20 p25 ? ? ? ? ? ? ? port 3 p30 p36 ? ? ? ? ? ? ? ? ? ? ? ? ? ? port 6 port 5 p50 p57 p64 p67 ? ? ? ? ? ? ? port 7 p70 p75 ? ? ? ? ? ? ? ? ? port 4 p40 p47 p03
137 chapter 6 port functions user s manual u14046ej3v0ud function port 0 4-bit i/o port. input/output mode can be specified in 1-bit units. an on-chip pull-up resistor can be used by software settings. port 1 8-bit input-only port. port 2 6-bit i/o port. input/output mode can be specified in 1-bit units. an on-chip pull-up resistor can be used by software settings. port 3 n-ch open-drain i/o port. 7-bit i/o port. on-chip pull-up resistor can be specified by mask input/output mode can be specified option (mask rom version only). in 1-bit units. leds can be driven directly. an on-chip pull-up resistor can be specified by software settings. port 4 8-bit i/o port. input/output mode can be specified in 1-bit units. an on-chip pull-up resistor can be specified by software settings. interrupt request flag (krif) is set to 1 by falling edge detection. port 5 8-bit i/o port. leds can be driven directly. input/output mode can be specified in 1-bit units. an on-chip pull-up resistor can be used by software settings. port 6 4-bit i/o port. input/output mode can be specified in 1-bit units. an on-chip pull-up resistor can be used by software settings. port 7 6-bit i/o port. input/output mode can be specified in 1-bit units. an on-chip pull-up resistor can be used by software settings. table 6-1. port functions ( pd780024a, 780034a subseries) pin name p00 p01 p02 p03 p10 to p17 p20 p21 p22 p23 p24 p25 p30 p31 p32 p33 p34 p35 p36 p40 to p47 p50 to p57 p64 p65 p66 p67 p70 p71 p72 p73 p74 p75 alternate function intp0 intp1 intp2 intp3/adtrg ani0 to ani7 si30 so30 sck30 rxd0 txd0 asck0 ? si31 so31 sck31 ad0 to ad7 a8 to a15 rd wr wait astb ti00/to0 ti01 ti50/to50 ti51/to51 pcl buz
138 chapter 6 port functions user s manual u14046ej3v0ud table 6-2. port functions ( pd780024ay, 780034ay subseries) alternate function intp0 intp1 intp2 intp3/adtrg ani0 to ani7 si30 so30 sck30 rxd0 txd0 asck0 ? sda0 scl0 ? ad0 to ad7 a8 to a15 rd wr wait astb ti00/to0 ti01 ti50/to50 ti51/to51 pcl buz pin name p00 p01 p02 p03 p10 to p17 p20 p21 p22 p23 p24 p25 p30 p31 p32 p33 p34 p35 p36 p40 to p47 p50 to p57 p64 p65 p66 p67 p70 p71 p72 p73 p74 p75 function port 0 4-bit i/o port. input/output mode can be specified in 1-bit units. an on-chip pull-up resistor can be used by software settings. port 1 8-bit input-only port. port 2 6-bit i/o port input/output mode can be specified in 1-bit units. an on-chip pull-up resistor can be used by software settings. port 3 n-ch open-drain i/o port. 7-bit i/o port. on-chip pull-up resistor can be specified by mask input/output mode can be specified option (p30 and p31 are mask rom version only). in 1-bit units. leds can be driven directly. an on-chip pull-up resistor can be used by software settings. port 4 8-bit i/o port. input/output mode can be specified in 1-bit units. an on-chip pull-up resistor can be used by software settings. interrupt request flag (krif) is set to 1 by falling edge detection. port 5 8-bit i/o port. leds can be driven directly. input/output mode can be specified in 1-bit units. an on-chip pull-up resistor can be used by software settings. port 6 4-bit i/o port. input/output mode can be specified in 1-bit units. an on-chip pull-up resistor can be used by software settings. port 7 6-bit i/o port. input/output mode can be specified in 1-bit units. an on-chip pull-up resistor can be used by software settings.
139 chapter 6 port functions user s manual u14046ej3v0ud 6.2 port configuration a port consists of the following hardware. table 6-3. port configuration item configuration control register port mode register (pmm: m = 0, 2 to 7) pull-up resistor option register (pum: m = 0, 2 to 7) port total: 51 ports (8 inputs, 43 inputs/outputs) pull-up resistor mask rom version total: 43 (software control: 39, mask option: 4 note ) flash memory version total: 39 note two mask options for the pd780024ay and 780034ay subseries. 6.2.1 port 0 port 0 is a 4-bit i/o port with output latch. p00 to p03 pins can specify the input mode/output mode in 1-bit units with port mode register 0 (pm0). an on-chip pull-up resistor of p00 to p03 pins can be used for them in 1-bit units with pull-up resistor option register 0 (pu0). this port can also be used as an external interrupt request input and a/d converter external trigger input. reset input sets port 0 to input mode. figure 6-2 shows a block diagram of port 0. cautions 1. port 0 functions alternately as an external interrupt request input pin. if the output mode of the port function is specified and the output level of the port is changed while interrupts are not disabled by the external interrupt rising edge enable register (egp) and external interrupt falling edge enable register (egn), the interrupt request flag is set. thus, when the output mode is used, set the interrupt mask flag to 1. 2. when the external interrupt request function is switched to the port function, edge detection may be performed. therefore, clear bit n (egpn) of egp and bit n (egnn) of egn to 0 before selecting the port mode. 3. when using p03/intp3/adtrg as an a/d converter external trigger input, specify valid edges by setting bits 1 and 2 (ega00 and ega01) of a/d converter mode register 0 (adm0) and set the interrupt mask flag (pmk3) to 1. remark n = 0 to 3
140 chapter 6 port functions user s manual u14046ej3v0ud figure 6-2. block diagram of p00 to p03 pu: pull-up resistor option register pm: port mode register rd: port 0 read signal wr: port 0 write signal v dd0 p-ch p00/intp0 p02/intp2, p03/intp3/adtrg wr pu rd wr port wr pm pu00 to pu03 alternate function output latch (p00 to p03) pm00 to pm03 internal bus selector
141 chapter 6 port functions user s manual u14046ej3v0ud 6.2.2 port 1 port 1 is an 8-bit input-only port. this port can also be used as an a/d converter analog input. figure 6-3 shows a block diagram of port 1. figure 6-3. block diagram of p10 to p17 rd: port 1 read signal rd p10/ani0 to p17/ani7 a/d converter internal bus
142 chapter 6 port functions user s manual u14046ej3v0ud 6.2.3 port 2 port 2 is a 6-bit i/o port with output latch. p20 to p25 pins can specify the input mode/output mode in 1-bit units with port mode register 2 (pm2). an on-chip pull-up resistor of p20 to p25 pins can be used for them in 1-bit units with pull-up resistor option register 2 (pu2). this port has also alternate functions as serial interface data i/o and clock i/o. reset input sets port 2 to input mode. figures 6-4 to 6-6 show block diagrams of port 2. figure 6-4. block diagram of p20, p23, and p25 pu: pull-up resistor option register pm: port mode register rd: port 2 read signal wr: port 2 write signal v dd0 p-ch p20/si30, p23/rxd0, p25/asck0 wr pu rd wr port wr pm pu20, pu23, pu25 alternate function output latch (p20, p23, p25) pm20, pm23, pm25 internal bus selector
143 chapter 6 port functions user s manual u14046ej3v0ud figure 6-5. block diagram of p21 and p24 pu: pull-up resistor option register pm: port mode register rd: port 2 read signal wr: port 2 write signal p21/so30, p24/txd0 wr pu rd wr port wr pm pu21, pu24 output latch (p21, p24) pm21, pm24 alternate function v dd0 p-ch internal bus selector
144 chapter 6 port functions user s manual u14046ej3v0ud figure 6-6. block diagram of p22 pu: pull-up resistor option register pm: port mode register rd: port 2 read signal wr: port 2 write signal p22/sck30 wr pu rd wr port wr pm pu22 output latch (p22) pm22 alternate function alternate function v dd0 p-ch internal bus selector
145 chapter 6 port functions user s manual u14046ej3v0ud 6.2.4 port 3 ( pd780024a, 780034a subseries) port 3 is a 7-bit i/o port with output latch. p30 to p36 pins can specify the input mode/output mode in 1-bit units with port mode register 3 (pm3). this port has the following functions for pull-up resistors. these functions differ depending on the port s higher 3-bit/lower 4-bit, and whether the product is a mask rom version or a flash memory version. table 6-4. pull-up resistor of port 3 ( pd780024a, 780034a subseries) higher 3-bit (p34 to p36 pins) lower 4-bit (p30 to p33 pins) mask rom version an on-chip pull-up resistor can be an on-chip pull-up resistor can be specified connected in 1-bit units by pu3 in 1-bit units by mask option flash memory version on-chip pull-up resistor is not provided pu3: pull-up resistor option register 3 the p30 to p33 pins can drive leds directly. the p34 to p36 pins can also be used for serial interface data i/o and clock i/o. reset input sets port 3 to input mode. figures 6-7 to 6-11 show block diagrams of port 3. figure 6-7. block diagram of p30 and p31 ( pd780024a, 780034a subseries) pm: port mode register rd: port 3 read signal wr: port 3 write signal rd pm30, pm31 p30, p31 n-ch wr port output latch (p30, p31) wr pm v dd0 selector internal bus mask option resistor ? ? ? ? ? ? ? ? ? ? mask rom version only no pull-up resistor for flash memory version
146 chapter 6 port functions user s manual u14046ej3v0ud figure 6-8. block diagram of p32 and p33 ( pd780024a, 780034a subseries) pm: port mode register rd: port 3 read signal wr: port 3 write signal rd pm32, pm33 p32, p33 n-ch wr port wr pm v dd0 output latch (p32, p33) selector internal bus mask option resistor ? ? ? ? ? ? ? ? ? ? mask rom version only no pull-up resistor for flash memory version
147 chapter 6 port functions user s manual u14046ej3v0ud figure 6-9. block diagram of p34 ( pd780024a, 780034a subseries) pu: pull-up resistor option register pm: port mode register rd: port 3 read signal wr: port 3 write signal v dd0 p-ch p34/si31 wr pu rd wr port wr pm pu34 alternate function output latch (p34) pm34 selector internal bus
148 chapter 6 port functions user s manual u14046ej3v0ud figure 6-10. block diagram of p35 ( pd780024a, 780034a subseries) pu: pull-up resistor option register pm: port mode register rd: port 3 read signal wr: port 3 write signal p35/so31 wr pu rd wr port wr pm pu35 output latch (p35) pm35 alternate function v dd0 p-ch selector internal bus
149 chapter 6 port functions user s manual u14046ej3v0ud figure 6-11. block diagram of p36 ( pd780024a, 780034a subseries) pu: pull-up resistor option register pm: port mode register rd: port 3 read signal wr: port 3 write signal v dd0 p-ch p36/sck31 wr pu rd wr port wr pm pu36 alternate function output latch (p36) pm36 alternate function selector internal bus
150 chapter 6 port functions user s manual u14046ej3v0ud 6.2.5 port 3 ( pd780024ay, 780034ay subseries) port 3 is a 7-bit i/o port with output latch. p30 to p36 pins can specify the input mode/output mode in 1-bit units with port mode register 3 (pm3). this port has the following functions for pull-up resistors. these functions differ depending on port s bits location and mask rom version/flash memory version. table 6-5. pull-up resistor of port 3 ( pd780024ay, 780034ay subseries) p34 to p36 pins p30 and p31 pins mask rom version an on-chip pull-up resistor can an on-chip pull-up resistor can be specified be connected in 1-bit units by in 1-bit units by mask option flash memory version pu3 on-chip pull-up resistor is not provided pu3: pull-up resistor option register 3 caution p32 and p33 pins have no pull-up resistor. the p30 to p33 pins can drive leds directly. the p32 and p33 pins can also be used for serial interface data i/o and clock i/o. reset input sets port 3 to input mode. figures 6-12 to 6-15 show block diagrams of port 3.
151 chapter 6 port functions user s manual u14046ej3v0ud figure 6-12. block diagram of p30 and p31 ( pd780024ay, 780034ay subseries) pm: port mode register rd: port 3 read signal wr: port 3 write signal figure 6-13. block diagram of p32 and p33 ( pd780024ay, 780034ay subseries) pm: port mode register rd: port 3 read signal wr: port 3 write signal rd pm30, pm31 p30, p31 n-ch wr port wr pm v dd0 output latch (p30, p31) selector internal bus mask option resistor ? ? ? ? ? ? ? ? ? ? mask rom version only no pull-up resistor for flash memory version rd pm32, pm33 alternate function p32/sda0, p33/scl0 n-ch wr port output latch (p32, p33) wr pm internal bus selector
152 chapter 6 port functions user s manual u14046ej3v0ud figure 6-14. block diagram of p34 and p36 ( pd780024ay, 780034ay subseries) v dd0 p-ch p34, p36 wr pu rd wr port wr pm pu34, pu36 output latch ( p34, p36) pm34, pm36 selector internal bus pu: pull-up resistor option register pm: port mode register rd: port 3 read signal wr: port 3 write signal
153 chapter 6 port functions user? manual u14046ej3v0ud figure 6-15. block diagram of p35 ( pd780024ay, 780034ay subseries) pu: pull-up resistor option register pm: port mode register rd: port 3 read signal wr: port 3 write signal p35 wr pu rd wr port wr pm pu35 output latch (p35) pm35 v dd0 p-ch internal bus selector
154 chapter 6 port functions user s manual u14046ej3v0ud 6.2.6 port 4 port 4 is an 8-bit i/o port with output latch. the p40 to p47 pins can specify the input mode/output mode in 1- bit units with port mode register 4 (pm4). an on-chip pull-up resistor of p40 to p47 pins can be used for them in 1- bit units with pull-up resistor option register 4 (pu4). the interrupt request flag (krif) can be set to 1 by detecting falling edges. this port can also be used as an address/data bus in external memory expansion mode. reset input sets port 4 to input mode. figures 6-16 and 6-17 show a block diagram of port 4 and block diagram of the falling edge detector, respectively. cautions 1. the internal pull-up resistor is not disconnected even if the external memory expansion mode is set when pu4n = 1 (n = 0 to 7). 2. when using the falling edge detection interrupt (intkr), be sure to set the memory expansion mode register (mem) to 01h. figure 6-16. block diagram of p40 to p47 internal bus rd p40/ad0 to p47/ad7 p-ch wr pu wr port wr pm pu40 to pu47 output latch (p40 to p47) pm40 to pm47 alternate function alternate function selector selector memory expansion mode register (mem) v dd0 pu: pull-up resistor option register pm: port mode register rd: port 4 read signal wr: port 4 write signal
155 chapter 6 port functions user s manual u14046ej3v0ud figure 6-17. block diagram of falling edge detector p40 p41 p42 p43 p44 p45 p46 p47 intkr falling edge detector 1 when mem = 01h 6.2.7 port 5 port 5 is an 8-bit i/o port with output latch. the p50 to p57 pins can specify the input mode/output mode in 1- bit units with port mode register 5 (pm5). an on-chip pull-up resistor of p50 to p57 pins can be used for them in 1- bit units with pull-up resistor option register 5 (pu5). port 5 can drive leds directly. this port can also be used as an address bus in external memory expansion mode. reset input sets port 5 to input mode. figure 6-18 shows a block diagram of port 5. caution the internal pull-up resistor is not disconnected even if the external memory expansion mode is set when pu5n = 1 (n = 0 to 7). figure 6-18. block diagram of p50 to p57 pu: pull-up resistor option register pm: port mode register rd: port 5 read signal wr: port 5 write signal internal bus rd p50/a8 to p57/a15 p-ch wr pu wr port wr pm pu50 to pu57 pm50 to pm57 selector v dd0 output latch (p50 to p57) alternate function selector memory expansion mode register (mem)
156 chapter 6 port functions user s manual u14046ej3v0ud 6.2.8 port 6 port 6 is a 4-bit i/o port with output latch. the p64 to p67 pins can specify the input mode/output mode in 1-bit units with port mode register 6 (pm6). an on-chip pull-up resistor of p64 to p67 pins can be used for them in 1-bit units with pull-up resistor option register 6 (pu6). this port can also be used as a control signal output in external memory expansion mode. reset input sets port 6 to input mode. figures 6-19 and 6-20 show block diagrams of port 6. cautions 1. the internal pull-up resistor is not disconnected even if the external memory expansion mode is set when pu6n = 1 (n = 4 to 7). 2. when external wait is not used in external memory expansion mode, p66 can be used as an i/o port. figure 6-19. block diagram of p64, p65, and p67 pu: pull-up resistor option register pm: port mode register rd: port 6 read signal wr: port 6 write signal internal bus rd p64/rd, p65/wr, p67/astb p-ch wr pu wr port wr pm pu64, pu65, pu67 pm64, pm65, pm67 v dd0 output latch (p64, p65, p67) alternate function selector selector memory expansion mode register (mem)
157 chapter 6 port functions user s manual u14046ej3v0ud figure 6-20. block diagram of p66 pu: pull-up resistor option register pm: port mode register rd: port 6 read signal wr: port 6 write signal internal bus rd p66/wait p-ch wr pu wr port wr pm pu66 pm66 v dd0 output latch (p66) alternate function selector selector memory expansion mode register (mem)
158 chapter 6 port functions user s manual u14046ej3v0ud 6.2.9 port 7 port 7 is a 6-bit i/o port with output latch. the p70 to p75 pins can specify the input mode/output mode in 1-bit units with port mode register 7 (pm7). an on-chip pull-up resistor of p70 to p75 pins can be used for them in 1-bit units with pull-up resistor option register 7 (pu7). this port can also be used as a timer i/o, clock output, and buzzer output. reset input sets the input mode. figures 6-21 to 6-23 show block diagrams of port 7. figure 6-21. block diagram of p70, p72, and p73 pu: pull-up resistor option register pm: port mode register rd: port 7 read signal wr: port 7 write signal v dd0 p-ch p70/ti00/to0, p72/ti50/to50, p73/ti51/to51 wr pu rd wr port wr pm pu70, pu72, pu73 alternate function output latch ( p70, p72, p73) pm70, pm72, pm73 alternate function internal bus selector
159 chapter 6 port functions user s manual u14046ej3v0ud figure 6-22. block diagram of p71 pu: pull-up resistor option register pm: port mode register rd: port 7 read signal wr: port 7 write signal v dd0 p-ch p71/ti01 wr pu rd wr port wr pm pu71 pm71 output latch (p71) alternate function internal bus selector
160 chapter 6 port functions user s manual u14046ej3v0ud figure 6-23. block diagram of p74 and p75 pu: pull-up resistor option register pm: port mode register rd: port 7 read signal wr: port 7 write signal p74/pcl, p75/buz wr pu rd wr port wr pm pu74, pu75 output latch (p74, p75) pm74, pm75 alternate function v dd0 p-ch internal bus selector
161 chapter 6 port functions user s manual u14046ej3v0ud 6.3 port function control registers the following two types of registers control the ports. port mode registers (pm0, pm2 to pm7) pull-up resistor option registers (pu0, pu2 to pu7) (1) port mode registers (pm0, pm2 to pm7) these registers are used to set port input/output in 1-bit units. pm0 and pm2 to pm7 are independently set by a 1-bit or 8-bit memory manipulation instruction. reset input sets registers to ffh. when using a port pin as its alternate-function pin, set the port mode registers and output latches as shown in table 6-6. cautions 1. pins p10 to p17 are input-only pins. 2. port 0 functions alternately as an external interrupt request input pin. if the output mode of the port function is specified and the output level of the port is changed while interrupts are not disabled by the external interrupt rising edge enable register (egp) and external interrupt falling edge enable register (egn), the interrupt request flag is set. when the output mode is used, therefore, the interrupt mask flag should be set to 1 beforehand. 3. if a port has an alternate function pin and it is used as an alternate output function, clear the corresponding output latches (p0 and p2 to p7) to 0.
162 chapter 6 port functions user s manual u14046ej3v0ud figure 6-24. format of port mode register (pm0, pm2 to pm7) address: ff20h after reset: ffh r/w symbol 76543210 pm0 1111 pm03 pm02 pm01 pm00 address: ff22h after reset: ffh r/w symbol 76543210 pm2 1 1 pm25 pm24 pm23 pm22 pm21 pm20 address: ff23h after reset: ffh r/w symbol 76543210 pm3 1 pm36 pm35 pm34 pm33 pm32 pm31 pm30 address: ff24h after reset: ffh r/w symbol 76543210 pm4 pm47 pm46 pm45 pm44 pm43 pm42 pm41 pm40 address: ff25h after reset: ffh r/w symbol 76543210 pm5 pm57 pm56 pm55 pm54 pm53 pm52 pm51 pm50 address: ff26h after reset: ffh r/w symbol 76543210 pm6 pm67 pm66 pm65 pm64 1111 address: ff27h after reset: ffh r/w symbol 76543210 pm7 1 1 pm75 pm74 pm73 pm72 pm71 pm70 pmmn pmn pin i/o mode selection (m = 0, 2 to 7; n = 0 to 7) 0 output mode (output buffer on) 1 input mode (output buffer off)
163 chapter 6 port functions user s manual u14046ej3v0ud note 2 note 2 note 2 note 2 note 2 table 6-6. port mode registers and output latch settings when alternate function is used (1/2) pin name p00 to p02 p03 p10 to p17 p20 p21 p22 p23 p24 p25 p32 p33 p34 p35 p36 p40 to p47 p50 to p57 p64 p65 p66 p67 alternate function pm 1 1 1 1 (fix) 1 0 1 0 1 0 1 0 0 1 0 1 0 1 note 2 p 0 0 0 0 0 0 0 note 2 name intp0 to intp2 intp3 adtrg ani0 to ani7 si30 so30 sck30 rxd0 txd0 asck0 sda0 note 1 scl0 note 1 si31 so31 sck31 ad0 to ad7 a8 to a15 rd wr wait astb i/o input input input input input output input output input output input i/o i/o input output input output i/o output output output input output notes 1. pd780024ay, 780034ay subseries only 2. when using the p40 to p47, p50 to p57, and p64 to p67 pins as alternate-function pins, set the function using the memory expansion mode register (mem). remark : don t care pm : port mode register p : port output latch
164 chapter 6 port functions user s manual u14046ej3v0ud table 6-6. port mode registers and output latch settings when alternate function is used (2/2) pin name p70 p71 p72 p73 p74 p75 alternate function pm 1 0 1 1 0 1 0 0 0 p 0 0 0 0 0 name ti00 to0 ti01 ti50 to50 ti51 to51 pcl buz i/o input output input input output input output output output remark : don t care pm : port mode register p : port output latch
165 chapter 6 port functions user s manual u14046ej3v0ud (2) pull-up resistor option registers (pu0, pu2 to pu7) these registers are used to set whether to use an on-chip pull-up resistor at each port or not. by setting pu0 and pu2 to pu7, the on-chip pull-up resistors of the port pins corresponding to the bits in pu0 and pu2 to pu7 can be used. pu0 and pu2 to pu7 are independently set by a 1-bit or 8-bit memory manipulation instruction. reset input clears registers to 00h. cautions 1. the p10 to p17 pins do not incorporate a pull-up resistor. 2. pins p30 to p33 (in pd780024ay and 780034ay subseries, p30 and p31 pins) can be used with pull-up resistor by mask option only for mask rom version. 3. when pum is set to 1, the on-chip pull-up resistor is connected irrespective of the input/ output mode. when using in output mode, clear the bit of pum to 0 (m = 0, 2 to 7).
166 chapter 6 port functions user s manual u14046ej3v0ud figure 6-25. format of pull-up resistor option register (pu0, pu2 to pu7) address: ff30h after reset: 00h r/w symbol 76543210 pu0 0000 pu03 pu02 pu01 pu00 address: ff32h after reset: 00h r/w symbol 76543210 pu2 0 0 pu25 pu24 pu23 pu22 pu21 pu20 address: ff33h after reset: 00h r/w symbol 76543210 pu3 0 pu36 pu35 pu34 0000 address: ff34h after reset: 00h r/w symbol 76543210 pu4 pu47 pu46 pu45 pu44 pu43 pu42 pu41 pu40 address: ff35h after reset: 00h r/w symbol 76543210 pu5 pu57 pu56 pu55 pu54 pu53 pu52 pu51 pu50 address: ff36h after reset: 00h r/w symbol 76543210 pu6 pu67 pu66 pu65 pu64 0000 address: ff37h after reset: 00h r/w symbol 76543210 pu7 0 0 pu75 pu74 pu73 pu72 pu71 pu70 pumn pmn pin on-chip pull-up resistor selection (m = 0, 2 to 7; n = 0 to 7) 0 on-chip pull-up resistor not used 1 on-chip pull-up resistor used
167 chapter 6 port functions user s manual u14046ej3v0ud 6.4 port function operations port operations differ depending on whether the input or output mode is set, as shown below. caution in the case of 1-bit memory manipulation instruction, although a single bit is manipulated, the port is accessed as an 8-bit unit. therefore, on a port with a mixture of input and output pins, the output latch contents for pins specified as input are undefined, even for bits other than the manipulated bit. 6.4.1 writing to i/o port (1) output mode a value is written to the output latch by a transfer instruction, and the output latch contents are output from the pin. once data is written to the output latch, it is retained until data is written to the output latch again. the output latch data is cleared by reset. (2) input mode a value is written to the output latch by a transfer instruction, but since the output buffer is off, the pin status does not change. once data is written to the output latch, it is retained until data is written to the output latch again. 6.4.2 reading from i/o port (1) output mode the output latch contents are read by a transfer instruction. the output latch contents do not change. (2) input mode the pin status is read by a transfer instruction. the output latch contents do not change. 6.4.3 operations on i/o port (1) output mode an operation is performed on the output latch contents, and the result is written to the output latch. the output latch contents are output from the pins. once data is written to the output latch, it is retained until data is written to the output latch again. the output latch data is cleared by reset. (2) input mode the output latch contents are undefined, but since the output buffer is off, the pin status does not change.
168 chapter 6 port functions user s manual u14046ej3v0ud 6.5 selection of mask option the following mask option is provided in the mask rom version. the flash memory versions have no mask options. table 6-7. comparison between mask rom version and flash memory version pin name mask rom version flash memory version mask option for pins p30 to p33 note on-chip pull-up resistors can be specified in an on-chip pull-up resistor is not 1-bit units. provided. note for pd780024ay and 780034ay subseries products, only the p30 and p31 pins can incorporate a pull- up resistor.
169 user? manual u14046ej3v0ud chapter 7 clock generator 7.1 clock generator functions the clock generator generates the clock to be supplied to the cpu and peripheral hardware. the following two types of system clock oscillators are available. (1) main system clock oscillator this circuit oscillates a clock with the following frequencies. ? 1.0 to 8.38 mhz: conventional product of pd780021a, 780022a, 780023a, 780024a, 780031a, 780032a, 780033a, 780034a and pd780021ay, 780022ay, 780023ay, 780024ay, 780031ay, 780032ay, 780033ay, 780034ay, 78f0034a, 78f0034ay, 78f0034by ? 1.0 to 12 mhz: expanded-specification product of pd780021a, 780022a, 780023a, 780024a, 780031a, 780032a, 780033a, 780034a and pd78f0034b oscillation can be stopped by executing the stop instruction or setting the processor clock control register (pcc). (2) subsystem clock oscillator the circuit oscillates a clock with a frequency of 32.768 khz. oscillation cannot be stopped. if the subsystem clock oscillator is not used, the internal feedback resistor can be disabled by the processor clock control register (pcc). this enables to reduce the power consumption in the stop mode. 7.2 clock generator configuration the clock generator consists of the following hardware. table 7-1. clock generator configuration item configuration control registers processor clock control register (pcc) oscillation stabilization time select register (osts) oscillators main system clock oscillator subsystem clock oscillator controllers prescaler standby controller wait controller
170 chapter 7 clock generator user? manual u14046ej3v0ud figure 7-1. block diagram of clock generator xt1 xt2 frc subsystem clock oscillator f xt main system clock oscillator f x prescaler f x 2 f x 2 2 f x 2 3 f x 2 4 f xt 2 1/2 prescaler standby controller halt wait controller 3 3 stop mcc frc cls osts2 osts1 osts0 css pcc2 pcc1 pcc0 oscillation stabilization time select register (osts) x1 x2 watch timer, clock output function clock to peripheral hardware cpu clock (f cpu ) processor clock control register (pcc) internal bus internal bus selector
171 chapter 7 clock generator user s manual u14046ej3v0ud 7.3 clock generator control registers the clock generator is controlled by the following two registers. processor clock control register (pcc) oscillation stabilization time select register (osts) (1) processor clock control register (pcc) this register selects the cpu clock and the division ratio, sets main system clock oscillator operation/stop and sets whether to use the subsystem clock oscillator internal feedback resistor note . pcc is set by a 1-bit or 8-bit memory manipulation instruction. reset input sets the value of pcc to 04h. note the feedback resistor is required to control the bias point of the oscillation waveform so that the bias point is in the middle of the power supply voltage. when the subsystem clock is not used, the power consumption in the stop mode can be reduced by setting bit 6 (frc) of pcc to 1 (see figure 7-7 subsystem clock feedback resistor ).
172 chapter 7 clock generator user s manual u14046ej3v0ud figure 7-2. format of processor clock control register (pcc) address: fffbh after reset: 04h r/w note 1 symbol <7> <6> <5> <4> 3210 pcc mcc frc cls css 0 pcc2 pcc1 pcc0 mcc main system clock oscillation control note 2 0 oscillation possible 1 oscillation stopped frc subsystem clock feedback resistor selection 0 internal feedback resistor used 1 internal feedback resistor not used note 3 cls cpu clock status 0 main system clock 1 subsystem clock css pcc2 pcc1 pcc0 cpu clock (f cpu ) selection 0000f x 001f x /2 010f x /2 2 011f x /2 3 100f x /2 4 1000f xt /2 001 010 011 100 other than above setting prohibited notes 1. bit 5 is read-only. 2. when the cpu is operating on the subsystem clock, mcc should be used to stop the main system clock oscillation. the stop instruction should not be used. 3. this bit can be set to 1 only when the subsystem clock is not used. cautions 1. be sure to clear bit 3 to 0. 2. when the external clock is input, mcc should not be set. this is because the x2 pin is connected to v dd1 via a pull-up resistor. remarks 1. f x : main system clock oscillation frequency 2. f xt : subsystem clock oscillation frequency
173 chapter 7 clock generator user s manual u14046ej3v0ud the fastest instructions of the pd780024a, 780034a, 780024ay, and 780034ay subseries are carried out in two cpu clocks. the relationship between the cpu clock (f cpu ) and minimum instruction execution time is shown in table 7-2. table 7-2. relationship between cpu clock and minimum instruction execution time cpu clock (f cpu ) minimum instruction execution time: 2/f cpu f x = 8.38 mhz f x = 12 mhz note f xt = 32.768 khz f x 0.238 s 0.166 s ? f x /2 0.477 s 0.333 s ? f x /2 2 0.954 s 0.666 s ? f x /2 3 1.90 s 1.33 s ? f x /2 4 3.81 s 2.66 s ? f xt /2 ?? 122 s note expanded-specification products of pd780024a, 780034a subseries only remark f x : main system clock oscillation frequency f xt : subsystem clock oscillation frequency
174 chapter 7 clock generator user s manual u14046ej3v0ud (2) oscillation stabilization time select register (osts) this register is used to select the oscillation stabilization time from when reset is effected or stop mode is released to when oscillation is stabilized. osts is set by an 8-bit memory manipulation instruction. reset input sets osts to 04h. thus, when releasing the stop mode by reset input, the time required to release is 2 17 /f x . figure 7-3. format of oscillation stabilization time select register (osts) address: fffah after reset: 04h r/w symbol 76543210 osts 00000 osts2 osts1 osts0 osts2 osts1 osts0 selection of oscillation stabilization time f x = 8.38 mhz f x = 12 mhz note 0002 12 /f x 488 s 341 s 0012 14 /f x 1.95 ms 1.36 ms 0102 15 /f x 3.91 ms 2.73 ms 0112 16 /f x 7.82 ms 5.46 ms 1002 17 /f x 15.6 ms 10.9 ms other than the above setting prohibited note expanded-specification products of pd780024a, 780034a subseries only. caution the wait time when stop mode is released does not include the time (??in the figure below) from when stop mode is released until the clock starts oscillation. this also applies when reset is input and an interrupt request is generated. remark f x : main system clock oscillation frequency a stop mode is released voltage waveform of x1 pin
175 chapter 7 clock generator user s manual u14046ej3v0ud 7.4 system clock oscillator 7.4.1 main system clock oscillator the main system clock oscillator oscillates with a crystal resonator or a ceramic resonator (8.38 mhz typ.) connected to the x1 and x2 pins. external clocks can be input to the main system clock oscillator. in this case, input a clock signal to the x1 pin and an inverted-phase clock signal to the x2 pin. figure 7-4 shows an external circuit of the main system clock oscillator. figure 7-4. external circuit of main system clock oscillator (a) crystal and ceramic oscillation (b) external clock crystal resonator or ceramic resonator x2 v ss1 x1 x2 x1 external clock caution do not execute the stop instruction and do not set mcc (bit 7 of processor clock control register (pcc)) to 1 if an external clock is input. this is because when the stop instruction is executed or mcc is set to 1, the main system clock operation stops and the x2 pin is connected to v dd1 via a pull-up resistor.
176 chapter 7 clock generator user s manual u14046ej3v0ud 7.4.2 subsystem clock oscillator the subsystem clock oscillator oscillates with a crystal resonator (32.768 khz typ.) connected to the xt1 and xt2 pins. external clocks can be input to the subsystem clock oscillator. in this case, input a clock signal to the xt1 pin and an inverted-phase clock signal to the xt2 pin. figure 7-5 shows an external circuit of the subsystem clock oscillator. figure 7-5. external circuit of subsystem clock oscillator (a) crystal oscillation (b) external clock 32.768 khz xt2 xt1 external clock xt2 v ss1 xt1 cautions are listed on the next page.
177 chapter 7 clock generator user s manual u14046ej3v0ud caution 1. when using the main system clock oscillator and subsystem clock oscillator, wire as follows in the area enclosed by broken lines in figures 7-4 and 7-5 to avoid an adverse effect from wiring capacitance. keep the wiring length as short as possible. do not cross the wiring with other signal lines. do not route the wiring near a signal line through which a high fluctuating current flows. always make the ground point of the oscillator capacitor the same potential as v ss1 . do not ground the capacitor to a ground pattern through which a high current flows. do not fetch signals from the oscillator. note that the subsystem clock oscillator is designed as a low-amplitude circuit for reducing power consumption. figure 7-6 shows examples of incorrect oscillator connection. figure 7-6. examples of incorrect oscillator connection (1/2) (a) too long wiring (b) crossed signal line remark when using the subsystem clock, replace x1 and x2 with xt1 and xt2, respectively. also, insert resistors in series on the xt2 side. v ss1 v ss1 x2 x1 x2 x1 portn (n = 0 to 7)
178 chapter 7 clock generator user s manual u14046ej3v0ud figure 7-6. examples of incorrect oscillator connection (2/2) (c) wiring near high fluctuating current (d) current flowing through ground line of oscillator (potential at points a, b, and c fluctuates) (e) signals are fetched remark when using the subsystem clock, replace x1 and x2 with xt1 and xt2, respectively. also, insert resistors in series on the xt2 side. caution 2. when x2 and xt1 are wired in parallel, the crosstalk noise of x2 may increase with xt1, resulting in malfunction. to prevent that from occurring, it is recommended to wire x2 and xt1 so that they are not in parallel, and to connect the ic pin between x2 and xt1 directly to v ss1 . x2 v ss1 x1 high current x2 x1 v ss1 abc pnm v dd0 high current v ss1 x2 x1
179 chapter 7 clock generator user s manual u14046ej3v0ud 7.4.3 when subsystem clock is not used if it is not necessary to use the subsystem clock for low power consumption operations and watch operations, connect the xt1 and xt2 pins as follows. xt1: connect directly to v dd0 or v dd1 xt2: leave open in this state, however, some current may leak via the internal feedback resistor of the subsystem clock oscillator when the main system clock stops. to minimize leakage current, the above internal feedback resistor can be removed by setting bit 6 (frc) of the processor clock control register (pcc). in this case also, connect the xt1 and xt2 pins as described above. figure 7-7. subsystem clock feedback resistor frc p-ch feedback resistor xt1 xt2 remark the feedback resistor is required to control the bias point of the oscillation waveform so that the bias point is in the middle of the power supply voltage.
180 chapter 7 clock generator user s manual u14046ej3v0ud 7.5 clock generator operations the clock generator generates the following types of clocks and controls the cpu operating mode including the standby mode. main system clock f x subsystem clock f xt cpu clock f cpu clock to peripheral hardware the following clock generator functions and operations are determined by the processor clock control register (pcc). (a) upon generation of the reset signal, the lowest speed mode of the main system clock (3.81 s @ 8.38 mhz operation) is selected (pcc = 04h). main system clock oscillation stops while a low level is applied to the reset pin. (b) with the main system clock selected, one of the five levels of minimum instruction execution time (0.166 s, 0.333 s, 0.666 s, 1.33 s, 2.66 s: @ 12 mhz operation note , 0.238 s, 0.476 s, 0.954 s, 1.90 s, 3.81 s: @ 8.38 mhz operation) can be selected by setting pcc. (c) with the main system clock selected, two standby modes, the stop and halt modes, are available. to reduce power consumption in the stop mode, the subsystem clock feedback resistor can be disconnected to stop the subsystem clock. (d) pcc can be used to select the subsystem clock and to operate the system with low power consumption (122 s @ 32.768 khz operation). (e) with the subsystem clock selected, main system clock oscillation can be stopped via pcc. the halt mode can be used. however, the stop mode cannot be used. (subsystem clock oscillation cannot be stopped.) (f) the main system clock is divided and supplied to the peripheral hardware. the subsystem clock is supplied to the watch timer and clock output functions only. thus the watch function and the clock output function can also be continued in the standby state. however, since all other peripheral hardware operate with the main system clock, the peripheral hardware also stops if the main system clock is stopped (except external input clock operation). note expanded-specification products of pd780024a, 780034a subseries only
181 chapter 7 clock generator user s manual u14046ej3v0ud 7.5.1 main system clock operations when operating with the main system clock (with bit 5 (cls) of the processor clock control register (pcc) cleared to 0), the following operations are carried out by pcc setting. (a) because the operation-guaranteed instruction execution speed depends on the power supply voltage, the minimum instruction execution time can be changed by bits 0 to 2 (pcc0 to pcc2) of pcc. (b) when bit 4 (css) of pcc is set to 1 when operating with the main system clock, if bit 7 (mcc) of pcc is set to 1 after the operation has been switched to the subsystem clock (cls = 1), the main system clock oscillation stops (see figure 7-8 (1) ). (c) if bit 7 (mcc) of pcc is set to 1 when operating with the main system clock, the main system clock oscillation does not stop. when bit 4 (css) of pcc is set to 1 and the operation is switched to the subsystem clock (cls = 1) after that, the main system clock oscillation stops (see figure 7-8 (2) ). figure 7-8. main system clock stop function (1) operation when mcc is set after setting css with main system clock operation mcc css cls main system clock oscillation subsystem clock oscillation cpu clock (2) operation when css is set after setting mcc with main system clock operation main system clock oscillation subsystem clock oscillation cpu clock mcc css cls oscillation does not stop
182 chapter 7 clock generator user s manual u14046ej3v0ud 7.5.2 subsystem clock operations when operating with the subsystem clock (with bit 5 (cls) of the processor clock control register (pcc) set to 1), the following operations are carried out. (a) the minimum instruction execution time remains constant (122 s @ 32.768 khz operation) irrespective of bits 0 to 2 (pcc0 to pcc2) of pcc. (b) watchdog timer counting stops. caution do not execute the stop instruction while the subsystem clock is in operation. 7.6 changing system clock and cpu clock settings 7.6.1 time required for switchover between system clock and cpu clock the system clock and cpu clock can be switched over by means of bits 0 to 2 (pcc0 to pcc2) and bit 4 (css) of the processor clock control register (pcc). the actual switchover operation is not performed directly after writing to the pcc; operation continues on the pre- switchover clock for several instructions (see table 7-3 ). determination as to whether the system is operating on the main system clock or the subsystem clock is performed by bit 5 (cls) of the pcc register. table 7-3. maximum time required for cpu clock switchover remark one instruction is the minimum instruction execution time with the pre-switchover cpu clock. caution selection of the cpu clock cycle division ratio (pcc0 to pcc2) and switchover from the main system clock to the subsystem clock (changing css from 0 to 1) should not be set simultaneously. simultaneous setting is possible, however, for selection of the cpu clock cycle division ratio (pcc0 to pcc2) and switch over from the subsystem clock to the main system clock (changing css from 1 to 0). set value before set value after switchover switchover css pcc2 pcc1 pcc0 css pcc2 pcc1 pcc0 css pcc2 pcc1 pcc0 css pcc2 pcc1 pcc0 css pcc2 pcc1 pcc0 css pcc2 pcc1 pcc0 css pcc2 pcc1 pcc0 0000 00 01001000 1101001 0000 16 instructions 16 instructions 16 instructions 16 instructions f x /2f xt instruction 0 0 1 8 instructions 8 instructions 8 instructions 8 instructions f x /4f xt instruction 0 1 0 4 instructions 4 instructions 4 instructions 4 instructions f x /8f xt instruction 0 1 1 2 instructions 2 instructions 2 instructions 2 instructions f x /16f xt instruction 1 0 0 1 instruction 1 instruction 1 instruction 1 instruction f x /32f xt instruction 1 1 instruction 1 instruction 1 instruction 1 instruction 1 instruction
183 chapter 7 clock generator user s manual u14046ej3v0ud 7.6.2 system clock and cpu clock switching procedure this section describes procedure for switching between the system clock and cpu clock. figure 7-9. system clock and cpu clock switching <1> the cpu is reset by setting the reset signal to low level after power-on. after that, when reset is released by setting the reset signal to high level, the main system clock starts oscillation. at this time, the oscillation stabilization time (2 17 /f x ) is secured automatically. after that, the cpu starts executing instructions at the minimum speed of the main system clock (3.81 s @ 8.38 mhz operation). <2> after the lapse of sufficient time for the v dd voltage to increase to enable operation at maximum speeds, pcc is rewritten and maximum-speed operation is carried out. <3> upon detection of a decrease of the v dd voltage due to an interrupt request signal, the main system clock is switched to the subsystem clock (which must be in an oscillation stable state). <4> upon detection of v dd voltage reset due to an interrupt, 0 is set to the mcc and oscillation of the main system clock is started. after the lapse of the time required for stabilization of oscillation, pcc is rewritten and the maximum-speed operation is resumed. caution when the main system clock is stopped and the device is operating on the subsystem clock, wait until the oscillation stabilization time has been secured by the program before switching back to the main system clock. system clock cpu clock interrupt request signal reset v dd f x f x f xt f x lowest- speed operation highest- speed operation subsystem clock operation high-speed operation wait (15.6 ms: @8.38 mhz operation) internal reset operation
184 user? manual u14046ej3v0ud chapter 8 16-bit timer/event counter 0 8.1 functions of 16-bit timer/event counter 0 16-bit timer/event counter 0 has the following functions. (1) interval timer 16-bit timer/event counter 0 generates interrupt requests at the preset time interval. number of counts: 2 to 65536 (2) external event counter 16-bit timer/event counter 0 can measure the number of pulses with a high-/low-level width of a signal input externally. valid level pulse width: 16/f x or more (3) pulse width measurement 16-bit timer/event counter 0 can measure the pulse width of an externally input signal. valid level pulse width: 2/f x or more (4) square-wave output 16-bit timer/event counter 0 can output a square wave with any selected frequency. cycle: (2 2 to 65536 2) count clock cycle (5) ppg output 16-bit timer/event counter 0 can output a square wave that have arbitrary cycle and pulse width. 2 < pulse width < cycle (ffff + 1) h
185 chapter 8 16-bit timer/event counter 0 user? manual u14046ej3v0ud 8.2 configuration of 16-bit timer/event counter 0 16-bit timer/event counter 0 consists of the following hardware. table 8-1. configuration of 16-bit timer/event counter 0 item configuration timer counter 16-bit timer counter 0 (tm0) register 16-bit timer capture/compare registers: 00, 01 (cr00, cr01) timer input ti00, ti01 timer output to0 control registers 16-bit timer mode control register 0 (tmc0) capture/compare control register 0 (crc0) 16-bit timer output control register 0 (toc0) prescaler mode register 0 (prm0) port mode register 7 (pm7) port 7 (p7) figure 8-1 shows block diagram of this counter. figure 8-1. block diagram of 16-bit timer/event counter 0 note ti00 input and to0 output cannot be used at the same time. capture/compare control register 0 (crc0) prescaler mode register 0 (prm0) 16-bit timer output control register 0 (toc0) 16-bit timer mode control register 0 (tmc0) internal bus ti01/p71 f x f x /2 2 f x /2 6 f x /2 3 ti00/to0/p70 note 2 noise elimi- nator prm01 prm00 crc02 match match clear noise elimi- nator noise elimi- nator crc02 crc01 crc00 inttm00 to0/ti00/ p70 note inttm01 internal bus tmc03 tmc02 ovf0 toc04 lvs0 lvr0 toc01 toe0 output latch (p70) pm70 selector selector selector selector 16-bit timer capture/compare register 01 (cr01) 16-bit timer counter 0 (tm0) 16-bit timer capture/compare register 00 (cr00) output controller
186 chapter 8 16-bit timer/event counter 0 user s manual u14046ej3v0ud (1) 16-bit timer counter 0 (tm0) tm0 is a 16-bit read-only register that counts count pulses. the counter is incremented in synchronization with the rising edge of the count clock. if the count value is read during operation, input of the count clock is temporarily stopped, and the count value at that point is read. the count value is reset to 0000h in the following cases. <1> at reset input <2> if tmc03 and tmc02 are cleared <3> if the valid edge of ti00 is input in the clear & start mode entered by inputting the valid edge of ti00 <4> if tm0 and cr00 match in the clear & start mode entered on a match between tm0 and cr00 (2) 16-bit timer capture/compare register 00 (cr00) cr00 is a 16-bit register which has the functions of both a capture register and a compare register. whether it is used as a capture register or as a compare register is set by bit 0 (crc00) of capture/compare control register 0 (crc0). when cr00 is used as a compare register the value set in cr00 is constantly compared with the 16-bit timer counter 0 (tm0) count value, and an interrupt request (inttm00) is generated if they match. it can also be used as the register that holds the interval time then tm0 is set to interval timer operation. when cr00 is used as a capture register it is possible to select the valid edge of the ti00 pin or the ti01 pin as the capture trigger. setting of the ti00 or ti01 valid edge is performed by means of prescaler mode register 0 (prm0) (see table 8-2 ). table 8-2. cr00 capture trigger and valid edges of ti00 and ti01 pins (1) ti00 pin valid edge selected as capture trigger (crc01 = 1, crc00 = 1) cr00 capture trigger ti00 pin valid edge es01 es00 falling edge rising edge 0 1 rising edge falling edge 0 0 no capture operation both rising and falling edges 1 1 (2) ti01 pin valid edge selected as capture trigger (crc01 = 0, crc00 = 1) cr00 capture trigger ti01 pin valid edge es11 es10 falling edge falling edge 0 0 rising edge rising edge 0 1 both rising and falling edges both rising and falling edges 1 1 remarks 1. setting es01, es00 = 1, 0 and es11, es10 = 1, 0 is prohibited. 2. es01, es00: bits 5 and 4 of prescaler mode register 0 (prm0) es11, es10: bits 7 and 6 of prescaler mode register 0 (prm0) crc01, crc00: bits 1 and 0 of capture/compare control register 0 (crc0)
187 chapter 8 16-bit timer/event counter 0 user s manual u14046ej3v0ud cr00 is set by a 16-bit memory manipulation instruction. reset input makes cr00 undefined. cautions 1. set cr00 to a value other than 0000h in the clear & start mode entered on a match between tm0 and cr00. however, in the free-running mode and in the clear mode using the valid edge of ti00, if cr00 is cleared to 0000h, an interrupt request (inttm00) is generated when cr00 changes from 0000h to 0001h following overflow (ffffh). 2. if the new value of cr00 is less than the value of 16-bit timer counter 0 (tm0), tm0 continues counting, overflows, and then starts counting from 0 again. if the new value of cr00 is less than the old value, therefore, the timer must be reset to be restarted after the value of cr00 is changed. 3. when p70 is used as the input pin for the valid edge of ti00, it cannot be used as a timer output (to0). moreover, when p70 is used as to0, it cannot be used as the input pin for the valid edge of ti00. (3) 16-bit timer capture/compare register 01 (cr01) cr01 is a 16-bit register which has the functions of both a capture register and a compare register. whether it is used as a capture register or a compare register is set by bit 2 (crc02) of capture/compare control register 0 (crc0). when cr01 is used as a compare register the value set in cr01 is constantly compared with the 16-bit timer counter 0 (tm0) count value, and an interrupt request (inttm01) is generated if they match. when cr01 is used as a capture register it is possible to select the valid edge of the ti00 pin as the capture trigger. the ti00 valid edge is set by means of prescaler mode register 0 (prm0) (see table 8-3 ). table 8-3. cr01 capture trigger and valid edge of ti00 pin (crc02 = 1) cr01 capture trigger ti00 pin valid edge es01 es00 falling edge falling edge 0 0 rising edge rising edge 0 1 both rising and falling edges both rising and falling edges 1 1 remarks 1. setting es01, es00 = 1, 0 is prohibited. 2. es01, es00: bits 5 and 4 of prescaler mode register 0 (prm0) crc02: bit 2 of capture/compare control register 0 (crc0)
188 chapter 8 16-bit timer/event counter 0 user s manual u14046ej3v0ud cr01 is set by a 16-bit memory manipulation instruction. reset input makes cr01 undefined. caution set cr01 to other than 0000h in the clear & start mode entered on a match between tm0 and cr00. however, in the free-running mode and in the clear mode using the valid edge of ti00, if cr01 is cleared to 0000h, an interrupt request (inttm01) is generated when cr01 changes from 0000h to 0001h following overflow (ffffh). 8.3 registers to control 16-bit timer/event counter 0 the following six types of registers are used to control 16-bit timer/event counter 0. 16-bit timer mode control register 0 (tmc0) capture/compare control register 0 (crc0) 16-bit timer output control register 0 (toc0) prescaler mode register 0 (prm0) port mode register 7 (pm7) port 7 (p7) (1) 16-bit timer mode control register 0 (tmc0) this register sets the 16-bit timer operating mode, the 16-bit timer counter 0 (tm0) clear mode, and output timing, and detects an overflow. tmc0 is set by a 1-bit or 8-bit memory manipulation instruction. reset input clears tmc0 to 00h. caution 16-bit timer counter 0 (tm0) starts operation at the moment tmc02 and tmc03 (operation stop mode) are set to a value other than 0, 0, respectively. clear tmc02 and tmc03 to 0, 0 to stop the operation.
189 chapter 8 16-bit timer/event counter 0 user s manual u14046ej3v0ud figure 8-2. format of 16-bit timer mode control register 0 (tmc0) tmc03 tmc02 operating mode to0 output timing selection interrupt request generation and clear mode selection 0 0 operation stop no change not generated (tm0 cleared to 0) 0 1 free-running mode match between tm0 and cr00 or match between tm0 and cr01 1 0 clear & start on ti00 valid ? edge note 1 11 clear & start on match between match between tm0 and tm0 and cr00 note 2 cr00 or match between tm0 and cr01 ovf0 overflow detection of 16-bit timer counter 0 (tm0) 0 overflow not detected 1 overflow detected notes 1. set the valid edge of the ti00/to0/p70 pin with prescaler mode register 0 (prm0). 2. if the clear & start mode entered on a match between tm0 and cr00 is selected, when the set value of cr00 is ffffh and the tm0 value changes from ffffh to 0000h, the ovf0 flag is set to 1. cautions 1. to write different data to tmc0, stop the timer operation before writing. 2. the timer operation must be stopped before writing to bits other than the ovf0 flag. remarks 1. to0: 16-bit timer/event counter 0 output pin 2. ti00: 16-bit timer/event counter 0 input pin 3. tm0: 16-bit timer counter 0 4. cr00: 16-bit timer capture/compare register 00 5. cr01: 16-bit timer capture/compare register 01 generated on match between tm0 and cr00, or match between tm0 and cr01 7 0 6 0 5 0 4 0 <3> tmc03 <2> tmc02 1 0 <0> ovf0 symbol tmc0 address: ff60h after reset: 00h r/w
190 chapter 8 16-bit timer/event counter 0 user s manual u14046ej3v0ud (2) capture/compare control register 0 (crc0) this register controls the operation of the 16-bit timer capture/compare registers (cr00, cr01). crc0 is set by a 1-bit or 8-bit memory manipulation instruction. reset input clears crc0 to 00h. figure 8-3. format of capture/compare control register 0 (crc0) address: ff62h after reset: 00h r/w symbol 76543210 crc0 00000 crc02 crc01 crc00 crc02 cr01 operating mode selection 0 operate as compare register 1 operate as capture register crc01 cr00 capture trigger selection 0 capture on valid edge of ti01 1 capture on valid edge of ti00 by reverse phase note crc00 cr00 operating mode selection 0 operate as compare register 1 operate as capture register note if both the rising and falling edges have been selected as the valid edges of ti00, capture is not performed. cautions 1. the timer operation must be stopped before setting crc0. 2. when the clear & start mode entered on a match between tm0 and cr00 is selected by 16- bit timer mode control register 0 (tmc0), cr00 should not be specified as a capture register. 3. to ensure the reliability of the capture operation, the capture trigger requires a pulse longer than two cycles of the count clock selected by prescaler mode register 0 (prm0) (see figure 8-31).
191 chapter 8 16-bit timer/event counter 0 user s manual u14046ej3v0ud (3) 16-bit timer output control register 0 (toc0) this register controls the operation of the 16-bit timer/event counter output controller. it sets r-s type flip-flop (lv0) set/reset, output inversion enable/disable, and 16-bit timer/event counter timer output enable/disable. toc0 is set by a 1-bit or 8-bit memory manipulation instruction. reset input clears toc0 to 00h. figure 8-4. format of 16-bit timer output control register 0 (toc0) address: ff63h after reset: 00h r/w symbol 7654<3><2>1<0> toc0 0 0 0 toc04 lvs0 lvr0 toc01 toe0 toc04 timer output f/f control by match of cr01 and tm0 0 inversion operation disabled 1 inversion operation enabled lvs0 lvr0 16-bit timer/event counter 0 timer output f/f status setting 0 0 no change 0 1 timer output f/f reset (0) 1 0 timer output f/f set (1) 1 1 setting prohibited toc01 timer output f/f control by match of cr00 and tm0 0 inversion operation disabled 1 inversion operation enabled toe0 16-bit timer/event counter 0 output control 0 output disabled (output set to level 0) 1 output enabled cautions 1. the timer operation must be stopped before setting toc0. 2. if lvs0 and lvr0 are read after data is set, they will be 0. 3. be sure to clear bits 5 to 7 of toc0 to 0.
192 chapter 8 16-bit timer/event counter 0 user s manual u14046ej3v0ud (4) prescaler mode register 0 (prm0) this register is used to set the 16-bit timer counter 0 (tm0) count clock and ti00, ti01 input valid edges. prm0 is set by an 8-bit memory manipulation instruction. reset input clears prm0 to 00h. figure 8-5. format of prescaler mode register 0 (prm0) address: ff61h after reset: 00h r/w symbol 76543210 prm0 es11 es10 es01 es00 0 0 prm01 prm00 es11 es10 ti01 valid edge selection 0 0 falling edge 0 1 rising edge 1 0 setting prohibited 1 1 both falling and rising edges es01 es00 ti00 valid edge selection 0 0 falling edge 0 1 rising edge 1 0 setting prohibited 1 1 both falling and rising edges prm01 prm00 count clock selection f x = 8.38 mhz f x = 12 mhz note 1 00f x 8.38 mhz 12 mhz 01f x /2 2 2.09 mhz 3 mhz 10f x /2 6 130 khz 187 khz 1 1 ti00 valid edge notes 2, 3 notes 1. expanded-specification products of pd780024a, 780034a subseries only. 2. the external clock requires a pulse longer than two cycles of the internal count clock (f x /2 3 ). 3. when the valid edge of ti00 is selected, the main system clock is used as the sampling clock for noise elimination. the valid edge of ti00 can be used only when the main system clock is operating. cautions 1. always set data to prm0 after stopping the timer operation. 2. if the valid edge of ti00 is to be set as the count clock, do not set the clear & start mode and the capture trigger at the valid edge of ti00. moreover, do not use the p70/ti00/to0 pin as a timer output (to0). 3. if the ti00 or ti01 pin is high level immediately after system reset, the rising edge is immediately detected after the rising edge or both the rising and falling edges are set as the valid edge(s) of the ti00 pin or ti01 pin to enable the operation of 16-bit timer counter 0 (tm0). be careful when pulling up the ti00 pin or the ti01 pin. however, when re-enabling operation after the operation has been stopped once, the rising edge is not detected. remarks 1. f x : main system clock oscillation frequency 2. ti00, ti01: 16-bit timer/event counter 0 input pin
193 chapter 8 16-bit timer/event counter 0 user s manual u14046ej3v0ud (5) port mode register 7 (pm7) this register sets port 7 input/output in 1-bit units. when using the p70/to0/ti00 pin for timer output, clear pm70 and the output latch of p70 to 0. when using the p70/to0/ti00 pin for timer input, set pm70 to 1. at this time, the output latch of p70 can be either 0 or 1. pm7 is set by a 1-bit or 8-bit memory manipulation instruction. reset input sets pm7 to ffh. figure 8-6. format of port mode register 7 (pm7) 7 1 6 1 5 pm75 4 pm74 3 pm73 2 pm72 1 pm71 0 pm70 symbol pm7 address: ff27h after reset: ffh r/w pm7n 0 1 p7n pin i/o mode selection (n = 0 to 5) output mode (output buffer on) input mode (output buffer off)
194 chapter 8 16-bit timer/event counter 0 user s manual u14046ej3v0ud 8.4 operation of 16-bit timer/event counter 0 8.4.1 interval timer operation setting 16-bit timer mode control register 0 (tmc0) and capture/compare control register 0 (crc0) as shown in figure 8-7 allows operation as an interval timer. interrupt requests are generated repeatedly using the count value set in 16-bit timer capture/compare register 00 (cr00) beforehand as the interval. when the count value of 16-bit timer counter 0 (tm0) matches the value set to cr00, counting continues with the tm0 value cleared to 0 and the interrupt request signal (inttm00) is generated. the count clock of the 16-bit timer/event counter can be selected using bits 0 and 1 (prm00, prm01) of prescaler mode register 0 (prm0). figure 8-7. control register settings for interval timer operation (a) 16-bit timer mode control register 0 (tmc0) (b) capture/compare control register 0 (crc0) 0000 tmc03 1 tmc02 10 ovf0 0 tmc0 clears and starts on match between tm0 and cr00. 00000 crc02 0/1 crc01 0/1 crc00 0 crc0 cr00 used as compare register
195 chapter 8 16-bit timer/event counter 0 user s manual u14046ej3v0ud figure 8-8. interval timer configuration diagram 16-bit timer capture/compare register 00 16-bit timer counter 0 ovf0 note clear circuit inttm00 f x f x /2 2 f x /2 6 ti00/to0/p70 selector noise eliminator f x /2 3 note ovf0 is 1 only when 16-bit timer capture/compare register 00 is set to ffffh. figure 8-9. timing of interval timer operation count clock t tm0 count value cr00 inttm00 to0 0000h 0001h n 0000h 0001h n 0000h 0001h n n n n n count start clear clear interrupt acknowledged interrupt acknowledged interval time interval time remark interval time = (n + 1) t n = 0001h to ffffh
196 chapter 8 16-bit timer/event counter 0 user s manual u14046ej3v0ud when the compare register is changed during timer count operation, if the value after 16-bit timer capture/ compare register 00 (cr00) is changed is smaller than that of 16-bit timer counter 0 (tm0), tm0 continues counting, overflows and then restarts counting from 0. thus, if the value (m) after the cr00 change is smaller than that (n) before the change, it is necessary to restart the timer after changing cr00. figure 8-10. timing after change of compare register during timer count operation cr00 nm count clock tm0 count value x ? 1 x ffffh 0000h 0001h 0002h remark n > x > m
197 chapter 8 16-bit timer/event counter 0 user s manual u14046ej3v0ud 8.4.2 external event counter operation the external event counter counts the number of external clock pulses to be input to the ti00 pin with using 16- bit timer counter 0 (tm0). tm0 is incremented each time the valid edge specified by prescaler mode register 0 (prm0) is input. when the tm0 count value matches the 16-bit timer capture/compare register 00 (cr00) value, tm0 is cleared to 0 and the interrupt request signal (inttm00) is generated. input a value other than 0000h to cr00. (a count operation with a pulse cannot be carried out.) the rising edge, the falling edge, or both edges can be selected using bits 4 and 5 (es00 and es01) of prescaler mode register 0 (prm0). because an operation is carried out only when the valid edge of the ti00 pin is detected twice after sampling with the internal clock (f x /2 3 ), noise with a short pulse width can be removed. caution when used as an external event counter, the p70/ti00/to0 pin cannot be used as a timer output (to0). figure 8-11. control register settings in external event counter mode (a) 16-bit timer mode control register 0 (tmc0) 0000 tmc03 1 tmc02 10 ovf0 0 tmc0 clears and starts on match between tm0 and cr00. (b) capture/compare control register 0 (crc0) 00000 crc02 0/1 crc01 0/1 crc00 0 crc0 cr00 used as compare register
198 chapter 8 16-bit timer/event counter 0 user s manual u14046ej3v0ud figure 8-12. external event counter configuration diagram 16-bit timer capture/compare register 00 16-bit timer counter 0 (tm0) internal bus match clear ovf0 note inttm00 noise eliminator f x /2 3 valid edge of ti00 note ovf0 is 1 only when 16-bit timer capture/compare register 00 is set to ffffh. figure 8-13. external event counter operation timing (with rising edge specified) ti00 pin input tm0 count value cr00 inttm00 0000h 0001h 0002h 0003h 0004h 0005h n ? 1n 0000h 0001h 0002h 0003h n caution when reading the external event counter count value, tm0 should be read.
199 chapter 8 16-bit timer/event counter 0 user s manual u14046ej3v0ud 8.4.3 pulse width measurement operations it is possible to measure the pulse width of the signals input to the ti00 pin and ti01 pin using 16-bit timer counter 0 (tm0). there are two measurement methods: measuring with tm0 used in free-running mode, and measuring by restarting the timer in synchronization with the edge of the signal input to the ti00 pin. (1) pulse width measurement with free-running counter and one capture register when 16-bit timer counter 0 (tm0) is operated in free-running mode (see register settings in figure 8-14 ), and the edge specified by prescaler mode register 0 (prm0) is input to the ti00 pin, the value of tm0 is taken into 16-bit timer capture/compare register 01 (cr01) and an external interrupt request signal (inttm01) is set. any of three edges can be selected rising, falling, or both edges specified by bits 4 and 5 (es00 and es01) of prm0. sampling is performed with the count clock selected by prm0, and a capture operation is only performed when a valid level of the ti00 pin is detected twice, thus eliminating noise with a short pulse width. figure 8-14. control register settings for pulse width measurement with free-running counter and one capture register (a) 16-bit timer mode control register 0 (tmc0) 0000 tmc03 0 tmc02 10 ovf0 0 tmc0 free-running mode (b) capture/compare control register 0 (crc0) 00000 crc02 1 crc01 0/1 crc00 0 crc0 cr00 used as compare register cr01 used as capture register
200 chapter 8 16-bit timer/event counter 0 user s manual u14046ej3v0ud figure 8-15. configuration diagram for pulse width measurement with free-running counter f x f x /2 2 f x /2 6 ti00/to0/p70 16-bit timer counter 0 ovf0 16-bit timer capture/compare register 01 internal bus inttm01 selector figure 8-16. timing of pulse width measurement operation with free-running counter and one capture register (with both edges specified) t 0000h 0000h ffffh 0001h d0 d0 (d1 ? d0) t (d3 ? d2) t (10000h ? d1 + d2) t d1 d2 d3 d2 d3 d0 + 1 d1 d1 + 1 note count clock tm0 count value ti00 pin input cr01 capture value inttm01 ovf0 note ovf0 must be cleared by software.
201 chapter 8 16-bit timer/event counter 0 user s manual u14046ej3v0ud (2) measurement of two pulse widths with free-running counter when 16-bit timer counter 0 (tm0) is operated in free-running mode (see register settings in figure 8-17 ), it is possible to simultaneously measure the pulse widths of the two signals input to the ti00 pin and the ti01 pin. when the edge specified by bits 4 and 5 (es00 and es01) of prescaler mode register 0 (prm0) is input to the ti00 pin, the value of tm0 is taken into 16-bit timer capture/compare register 01 (cr01) and an interrupt request signal (inttm01) is set. also, when the edge specified by bits 6 and 7 (es10 and es11) of prm0 is input to the ti01 pin, the value of tm0 is taken into 16-bit timer capture/compare register 00 (cr00) and an interrupt request signal (inttm00) is set. any of three edges can be selected rising, falling, or both edges as the valid edges for the ti00 pin and the ti01 pin specified by bits 4 and 5 (es00 and es01) and bits 6 and 7 (es10 and es11) of prm0, respectively. sampling is performed at the interval selected by prescaler mode register 0 (prm0), and a capture operation is only performed when a valid level of the ti00 pin or ti01 pin is detected twice, thus eliminating noise with a short pulse width. figure 8-17. control register settings for measurement of two pulse widths with free-running counter (a) 16-bit timer mode control register 0 (tmc0) 0000 tmc03 0 tmc02 10 ovf0 0 tmc0 free-running mode (b) capture/compare control register 0 (crc0) 00000 crc02 1 crc01 0 crc00 1 crc0 cr00 used as capture register captures valid edge of ti01 pin to cr00 cr01 used as capture register
202 chapter 8 16-bit timer/event counter 0 user s manual u14046ej3v0ud figure 8-18. timing of pulse width measurement operation with free-running counter (with both edges specified) note ovf0 must be cleared by software. t 0000h 0000h ffffh 0001h d0 d0 (d1 ? d0) t (d3 ? d2) t (10000h ? d1 + d2) t (10000h ? d1 + (d2 + 1)) t d1 d2 + 1 d1 d2 d2 d3 d0 + 1 d1 d1 + 1 d2 + 1 d2 + 2 note ti01 pin input cr00 capture value inttm01 inttm00 ovf0 count clock tm0 count value ti00 pin input cr01 capture value
203 chapter 8 16-bit timer/event counter 0 user s manual u14046ej3v0ud (3) pulse width measurement with free-running counter and two capture registers when 16-bit timer counter 0 (tm0) is operated in free-running mode (see register settings in figure 8-19 ), it is possible to measure the pulse width of the signal input to the ti00 pin. when the edge specified by bits 4 and 5 (es00 and es01) of prescaler mode register 0 (prm0) is input to the ti00 pin, the value of tm0 is taken into 16-bit timer capture/compare register 01 (cr01) and an interrupt request signal (inttm01) is set. also, when the inverse edge to that of the capture operation to cr01 is input, the value of tm0 is taken into 16- bit timer capture/compare register 00 (cr00). either of two edges can be selected rising or falling as the valid edges for the ti00 pin specified by bits 4 and 5 (es00 and es01) of prescaler mode register 0 (prm0). sampling is performed at the interval selected by prescaler mode register 0 (prm0), and a capture operation is only performed when a valid level of the ti00 pin is detected twice, thus eliminating noise with a short pulse width. caution if the valid edge of ti00 is specified to be both the rising and falling edges, 16-bit timer capture/ compare register 00 (cr00) cannot perform the capture operation. figure 8-19. control register settings for pulse width measurement with free-running counter and two capture registers (a) 16-bit timer mode control register 0 (tmc0) 0000 tmc03 0 tmc02 10 ovf0 0 tmc0 free-running mode (b) capture/compare control register 0 (crc0) 00000 crc02 1 crc01 1 crc00 1 crc0 cr00 used as capture register captures to cr00 at edge reverse to valid edge of ti00. cr01 used as capture register
204 chapter 8 16-bit timer/event counter 0 user s manual u14046ej3v0ud figure 8-20. timing of pulse width measurement operation with free-running counter and two capture registers (with rising edge specified) t 0000h 0000h ffffh 0001h d0 d0 d2 d1 d3 d2 d3 d1 d0 + 1 d2 + 1 d1 + 1 inttm01 ovf0 cr00 capture value count clock tm0 count value ti00 pin input cr01 capture value (d1 ? d0) t (d3 ? d2) t (10000h ? d1 + d2) t note note ovf0 must be cleared by software. (4) pulse width measurement by means of restart when input of a valid edge to the ti00 pin is detected, the count value of 16-bit timer counter 0 (tm0) is taken into 16-bit timer capture/compare register 01 (cr01), and then the pulse width of the signal input to the ti00 pin is measured by clearing tm0 and restarting the count (see register settings in figure 8-22 ). the edge specification can be selected from two types, rising or falling edges, by bits 4 and 5 (es00 and es01) of prescaler mode register 0 (prm0). sampling is performed at the interval selected by prescaler mode register 0 (prm0) and a capture operation is only performed when a valid level of the ti00 pin is detected twice, thus eliminating noise with a short pulse width. caution if the valid edge of ti00 is specified to be both the rising and falling edges, 16-bit timer capture/ compare register 00 (cr00) cannot perform the capture operation.
205 chapter 8 16-bit timer/event counter 0 user s manual u14046ej3v0ud figure 8-21. control register settings for pulse width measurement by means of restart (a) 16-bit timer mode control register 0 (tmc0) 0000 tmc03 1 tmc02 00 ovf0 0 tmc0 clears and starts at valid edge of ti00 pin. (b) capture/compare control register 0 (crc0) 00000 crc02 1 crc01 1 crc00 1 crc0 cr00 used as capture register captures to cr00 at edge reverse to valid edge of ti00. cr01 used as capture register figure 8-22. timing of pulse width measurement operation by means of restart (with rising edge specified) t 0000h 0001h 0000h 0001h 0000h 0001h d0 d0 d2 d1 d2 d1 d1 t d2 t inttm01 cr00 capture value count clock tm0 count value ti00 pin input cr01 capture value
206 chapter 8 16-bit timer/event counter 0 user s manual u14046ej3v0ud 8.4.4 square-wave output operation a square wave with any selected frequency can be output at intervals determined by the count value preset to 16-bit timer capture/compare register 00 (cr00). the to0 pin output status is reversed at intervals determined by the count value preset to cr00 by setting bit 0 (toe0) and bit 1 (toc01) of 16-bit timer output control register 0 (toc0) to 1. this enables a square wave with any selected frequency to be output. figure 8-23. control register settings in square-wave output mode (a) 16-bit timer mode control register 0 (tmc0) 0000 tmc03 1 tmc02 10 ovf0 0 tmc0 clears and starts on match between tm0 and cr00. (b) capture/compare control register 0 (crc0) 00000 crc02 0/1 crc01 0/1 crc00 0 crc0 cr00 used as compare register (c) 16-bit timer output control register 0 (toc0) 000 toc04 0 lvs0 0/1 lvr0 0/1 toc01 1 toe0 1 toc0 enables to0 output. reverses output on match between tm0 and cr00. specifies initial value of to0 output f/f. does not reverse output on match between tm0 and cr01. figure 8-24. square-wave output operation timing count clock tm0 count value cr00 inttm00 to0 pin output 0000h 0001h 0002h n ? 1n 0000h 0001h 0002h n ? 1n 0000h n
207 chapter 8 16-bit timer/event counter 0 user s manual u14046ej3v0ud 8.4.5 ppg output operation setting 16-bit timer mode control register 0 (tmc0) and capture/compare control register 0 (crc0) as shown in figure 8-25 allows operation as ppg (programmable pulse generator) output. in the ppg output operation, square waves are output from the to0 pin with the pulse width and the cycle that correspond to the count values set beforehand in 16-bit timer capture/compare register 01 (cr01) and in 16-bit timer capture/compare register 00 (cr00), respectively. figure 8-25. control register settings for ppg output operation (a) 16-bit timer mode control register 0 (tmc0) 0000 tmc03 1 tmc02 10 ovf0 0 tmc0 clears and starts on match between tm0 and cr00. (b) capture/compare control register 0 (crc0) 00000 crc02 0 crc01 crc00 0 crc0 cr00 used as compare register cr01 used as compare register (c) 16-bit timer output control register 0 (toc0) 000 toc04 1 lvs0 0/1 lvr0 0/1 toc01 1 toe0 1 toc0 enables to0 output reverses output on match between tm0 and cr00 specifies initial value of to0 output f/f reverse output on match between tm0 and cr01 cautions 1. cr00 and cr01 values in the following range should be set to: 0000h < cr01 < cr00 ffffh 2. the cycle of the pulse generated via ppg output (cr00 setting value + 1) has a duty of (cr01 setting value + 1)/(cr00 setting value + 1). remark : don t care
208 chapter 8 16-bit timer/event counter 0 user s manual u14046ej3v0ud figure 8-26. ppg output configuration diagram figure 8-27. ppg output operation timing remark 0000h < m < n ffffh 16-bit timer capture/ compare register 00 16-bit timer counter 0 clear circuit f x f x /2 2 f x /2 6 16-bit timer capture/compare register 01 to0/ti00/p70 selector output controller t 0000h 0000h 0001h 0001h m ? 1 count clock tm0 count value to0 pulse width: (m + 1) t one cycle: (n + 1) t n cr00 cr01 m m n ? 1 n clear count start
209 chapter 8 16-bit timer/event counter 0 user s manual u14046ej3v0ud 8.5 program list caution the following sample program is shown as an example to describe the operation of semiconductor products and their applications. therefore, when applying the following information to your devices, design the devices after performing evaluation under your own responsibility.
210 chapter 8 16-bit timer/event counter 0 user s manual u14046ej3v0ud 8.5.1 interval timer /*******************************************************************************/ /* */ /* setting example of timer 0 interval timer mode */ /* cycle set to 130 as intervaltm0 (at 8.38 mhz for 1 ms) */ /* variable ppgdata prepared as rewrite data area */ /* : cycle (if 0000, no change) */ /* ppgdata to be checked at every inttm00, and changed if required. */ /* therefore, if change is required, set the change data in ppgdata. */ /* when changed, ppgdata cleared to 0000. */ /* */ /*******************************************************************************/ #pragma sfr #pragma ei #pragma di #define intervaltm0 130 /* cycle data to be set to cr00 */ #pragma interrupt inttm00 intervalint rb2 unsigned int ppgdata; /* data area to be set to timer 0 */ void main(void) { pcc = 0x0; /* set high-speed operation mode */ ppgdata = 0; /* set port */ /* set the following to output */ p7 = 0b11111110; /* clear p70 */ pm7.0 = 0; /* set p70 as output */ /* set interrupt */ tmmk00 = 0; /* cancel inttm00 interrupt mask */ /* set timer 0 */ prm0 = 0b00000010; /* count clock is fx/2^6 */ crc0 = 0b00000000; /* set cr00 and cr01 to compare register */ cr00 = intervaltm0; /* set cycle initial value to cr00 */ toc0 = 0b00000111; /* invert on match with cr00, initial value l */ tmc0 = 0b00001100; /* clear & start on match between tm0 and cr00 */ ei(); while(1); /* loop as dummy here */ } /* timer 0 interrupt function */ void intervalint() { unsigned int work; /***************************************************/ /* */ /* define variables required for interrupt here */ /* */ /***************************************************/ work = ppgdata; if (work != 0) { cr00 = work; ppgdata = 0; if (work == 0xffff) { tmc0 = 0b00000000; /* stop timer */ } } /***********************************************************/ /* */ /* describe processing required for interrupt below */ /* */ /***********************************************************/ }
211 chapter 8 16-bit timer/event counter 0 user s manual u14046ej3v0ud 8.5.2 pulse width measurement by free-running counter and one capture register /******************************************************************************/ /* */ /* timer 0 operation sample */ /* pulse width measurement example by free-running and cr01 */ /* measurement results to be up to 16 bits and not checked for errors */ /* data[0]: end flag */ /* data[1]: measurement results (pulse width) */ /* data[2]: previous read value */ /* */ /******************************************************************************/ #pragma sfr #pragma ei #pragma di #pragma interrupt inttm01 intervalint rb2 unsigned int data[3]; /* data area */ void main(void) { unsigned int length; pcc = 0x0; /* set high-speed operation mode */ data[0] = 0; data[1] = 0; data[2] = 0; /* set port */ pm7.0 = 1; /* set p70 as input */ /* set interrupt */ tmmk01 = 0; /* cancel inttm01 interrupt mask */ /* set timer 0 */ prm0 = 0b00110010; /* both rising and falling edges for ti00 */ /* count clock is fx/2^6 */ crc0 = 0b00000100; /* set cr01 to capture register */ tmc0 = 0b00000100; /* start in free-run mode */ ei(); while(1){ /* dummy loop */ while(data[0] == 0); /* wait for measurement completion */ di(); /* prohibit interrupt for exclusive operation */ length = data[1]; /* read measurement results */ data[0] = 0; /* clear end flag */ ei(); /* exclusive operation completed */ } } /* timer 0 interrupt function */ void intervalint() { unsigned int work; /*****************************************************/ /* */ /* define variables required for interrupt here */ /* */ /*****************************************************/ work = cr01; /* read capture value */ data[1] = work - data[2]; /* calculate and update interval */ data[2] = work; /* update read value */ data[0] = 0xffff; /* set measurement completion flag */ /***********************************************************/ /* */ /* describe processing required for interrupt below */ /* */ /***********************************************************/ }
212 chapter 8 16-bit timer/event counter 0 user s manual u14046ej3v0ud 8.5.3 two pulse widths measurement by free-running counter /******************************************************************************/ /* */ /* timer 0 operation sample */ /* two-pulse-width measurement sample by free-running */ /* measurement results to be up to 16 bits and not checked for errors */ /* result area at ti00 side */ /* data[0]: end flag */ /* data[1]: measurement results (pulse width) */ /* data[2]: previous read value */ /* result area at ti01 side */ /* data[3]: end flag */ /* data[4]: measurement results (pulse width) */ /* data[5]: previous read value */ /* */ /******************************************************************************/ #pragma sfr #pragma ei #pragma di #pragma interrupt inttm00 intervalint rb2 #pragma interrupt inttm01 intervalint2 rb2 unsigned int data[6]; /* data area */ void main(void) { unsigned int length,length2; pcc = 0x0; /* set high-speed operation mode */ data[0] = 0; /* clear data area */ data[1] = 0; data[2] = 0; data[3] = 0; data[4] = 0; data[5] = 0; /* set port */ pm7.0 = 1; /* set p70 as input */ pm7.1 = 1; /* set p71 as input */ /* set interrupt */ tmmk01 = 0; /* cancel inttm01 interrupt mask */ tmmk00 = 0; /* cancel inttm00 interrupt mask */ /* set timer 0 */ prm0 = 0b11110010; /* both rising and falling edges */ /* count clock is fx/2^6 */ crc0 = 0b00000101; /* set cr00 and cr01 to capture register */ tmc0 = 0b00000100; /* start in free-run mode */ ei(); while(1){ /* dummy loop */ if(data[0] != 0) /* ti00 measurement completion check */ { tmmk01 = 1; /* inttm01 interrupt prohibited for exclusive operation */ length = data[1]; /* read measurement results */ data[0] = 0; /* clear end flag */ tmmk01 = 0; /* exclusive operation completed */ } if(data[3] != 0) /* ti01 measurement completion check */ { tmmk00 = 1; /* inttm00 interrupt prohibited for exclusive operation */ length2 = data[4]; /* read measurement results */ data[3] = 0; /* clear end flag */ tmmk00 = 0; /* exclusive operation completed */ } } }
213 chapter 8 16-bit timer/event counter 0 user s manual u14046ej3v0ud /* inttm00 interrupt function */ void intervalint() { unsigned int work; /******************************************************/ /* */ /* define variables required for interrupt here */ /* */ /******************************************************/ work = cr00; /* read capture value */ data[4] = work - data[5]; /* calculate and update interval */ data[5] = work; /* update read value */ data[3] = 0xffff; /* set measurement completion flag */ /********************************************************/ /* */ /* describe processing required for interrupt below */ /* */ /********************************************************/ } /* inttm01 interrupt function */ void intervalint2() { unsigned int work; /******************************************************/ /* */ /* define variables required for interrupt here */ /* */ /******************************************************/ work = cr01; /* read capture value */ data[1] = work - data[2]; /* calculate and update interval */ data[2] = work; /* update read value */ data[0] = 0xffff; /* set measurement completion flag */ /********************************************************/ /* */ /* describe processing required for interrupt below */ /* */ /********************************************************/ }
214 chapter 8 16-bit timer/event counter 0 user s manual u14046ej3v0ud 8.5.4 pulse width measurement by restart /**************************************************************************/ /* */ /* timer 0 operation sample */ /* pulse width measurement example by restart */ /* measurement results up to 16 bits, not to be checked for errors */ /* data[0]: end flag */ /* data[1]: measurement results (pulse width) */ /* data[2]: previous read value */ /* */ /**************************************************************************/ #pragma sfr #pragma ei #pragma di #pragma interrupt inttm01 intervalint rb2 unsigned int data[3]; /* data area */ void main(void) { unsigned int length; pcc = 0x0; /* set high-speed operation mode */ data[0] = 0; data[1] = 0; data[2] = 0; /* set port */ pm7.0 = 1; /* set p70 as input */ /* set interrupt */ tmmk01 = 0; /* cancel inttm01 interrupt mask */ /* set timer 0 */ prm0 = 0b00110010; /* both rising and falling edges */ /* count clock is fx/2^6 */ crc0 = 0b00000100; /* set cr01 to capture register */ tmc0 = 0b00001000; /* clear & start at ti00 valid edge */ ei(); while(1){ /* dummy loop */ if(data[0] != 0) /* wait for ti00 measurement completion */ { tmmk01 = 1; /* prohibit inttm01 interrupt for exclusive operation */ length = data[1]+data[2]; /* cycle calculation based on measurement results */ data[0] = 0; /* clear end flag */ tmmk01 = 0; /* exclusive operation completed */ } } } /* timer 0 interrupt function */ void intervalint() { /******************************************************/ /* */ /* define variables required for interrupt here */ /* */ /******************************************************/ data[2] = data[1]; /* update old data */ data[1] = cr01; /* update read value */ data[0] = 0xffff; /* set measurement completion flag */ /********************************************************/ /* */ /* describe processing required for interrupt below */ /* */ /********************************************************/ }
215 chapter 8 16-bit timer/event counter 0 user s manual u14046ej3v0ud 8.5.5 ppg output /******************************************************************************/ /* */ /* timer 0 ppg mode setting example */ /* cycle set to 130 as intervaltm0 */ /* active period set to 65 as active_time */ /* array ppgdata prepared as data area for rewriting */ /* [0]: active period (0000: no change, 0xffff: stop) */ /* [1]: cycle (0000: no change) */ /* ppgdata to be checked at every inttm00, and changed if required. */ /* therefore, if change is required, set the change data in ppgdata. */ /* when changed, ppgdata cleared to 0000. */ /* */ /******************************************************************************/ #pragma sfr #pragma ei #pragma di #define intervaltm0 130 /* cycle data to be set to cr00 */ #define active_time 65 /* initial value data of cr01 */ #pragma interrupt inttm00 ppgint rb2 unsigned int ppgdata[2]; /* data area to be set to timer 0 */ void main(void) { pcc = 0x0; /* set high-speed operation mode */ ppgdata[0] = 0; ppgdata[1] = 0; /* set port */ p7 = 0b11111110; /* clear p70 */ pm7.0 = 0; /* set p70 to output */ /* set interrupt */ tmmk00 = 0; /* cancel inttm00 interrupt mask */ /* set timer 0 */ prm0 = 0b00000010; /* count clock is fx/2^6 */ crc0 = 0b00000000; /* set cr00 and cr01 to compare register */ cr00 = intervaltm0; /* set initial value of cycle */ cr01 = active_time; /* set initial value of active period */ toc0 = 0b00010111; /* inverted on match between cr00 and cr01, initial value l */ tmc0 = 0b00001100; /* clear & start on match between tm0 and cr00 */ ei(); while(1); } /* timer 0 interrupt function */ void ppgint() { unsigned int work; work = ppgdata[0]; if (work != 0) { cr01 = work; ppgdata[0] = 0; if (work == 0xffff) { tmc0 = 0b00000000; /* stop timer */ } } work = ppgdata[1]; if (work != 0) { cr00 = work; ppgdata[1]=0; } }
216 chapter 8 16-bit timer/event counter 0 user s manual u14046ej3v0ud 8.6 cautions related to 16-bit timer/event counter 0 (1) timer start errors an error of up to one clock may occur in the time required for a match signal to be generated after timer start. this is because 16-bit timer counter 0 (tm0) is started asynchronously to the count clock. figure 8-28. start timing of 16-bit timer counter 0 (tm0) tm0 count value 0000h 0001h 0002h 0004h count clock timer start 0003h (2) 16-bit timer capture/compare register setting (clear & start mode entered on match between tm0 and cr00) set 16-bit timer capture/compare registers 00, 01 (cr00, cr01) to other than 0000h. this means a 1-pulse count operation cannot be performed. (3) capture register data retention timing if the valid edge of the ti00 pin is input during 16-bit timer capture/compare register 01 (cr01) read, cr01 performs a capture operation but, the read value at this time is not guaranteed. the interrupt request signal (inttm01) is generated upon detection of the valid edge. figure 8-29. capture register data retention timing count clock tm0 count edge input inttm01 capture read signal cr01 capture value n n + 1 n + 2 m m + 1 m + 2 x n + 1 m + 1 read value not guaranteed though capture operation performed capture (4) valid edge setting set the valid edge of the ti00 pin after clearing bits 2 and 3 (tmc02 and tmc03) of 16-bit timer mode control register 0 (tmc0) to 0, 0, respectively, and then stopping the timer operation. the valid edge is set by bits 4 and 5 (es00 and es01) of prescaler mode register 0 (prm0).
217 chapter 8 16-bit timer/event counter 0 user s manual u14046ej3v0ud (5) operation of ovf0 flag <1> the ovf0 flag is also set to 1 in the following case. either of the clear & start mode entered on a match between tm0 and cr00, clear & start at the valid edge of ti00, or free-running mode is selected. cr00 is set to ffffh. when tm0 is counted up from ffffh to 0000h. figure 8-30. operation timing of ovf0 flag count clock cr00 tm0 ovf0 inttm00 ffffh fffeh ffffh 0000h 0001h <2> even if the ovf0 flag is cleared before the next count clock is counted (before tm0 becomes 0001h) after the occurrence of a tm0 overflow, the ovf0 flag is reset newly and clear is disabled. (6) conflicting operations when the 16-bit timer capture/compare register (cr00/cr01) is used as a compare register, if the write period and the match timing of 16-bit timer counter 0 (tm0) conflict, match determination is not successfully done. do not perform a write operation of cr00/cr01 near the match timing. (7) timer operation <1> even if 16-bit timer counter 0 (tm0) is read, the value is not captured by 16-bit timer capture/compare register 01 (cr01). <2> regardless of the cpu s operation mode, when the timer stops, the signals input to pins ti00/ti01 are not acknowledged.
218 chapter 8 16-bit timer/event counter 0 user s manual u14046ej3v0ud (8) capture operation <1> if ti00 is specified as the valid edge of the count clock, a capture operation by the capture register specified as the trigger for ti00 is not possible. <2> if both the rising and falling edges are selected as the valid edges of ti00, capture is not performed. <3> to ensure the reliability of the capture operation, the capture trigger requires a pulse longer than two cycles of the count clock selected by prescaler mode register 0 (prm0). figure 8-31. cr01 capture operation with rising edge specified count clock tm0 ti00 rising edge detection cr01 inttm01 n ? 3n ? 2n ? 1 n n + 1 n <4> the capture operation is performed at the fall of the count clock. an interrupt request input (inttm0n), however, occurs at the rise of the next count clock. (9) compare operation <1> when the 16-bit timer capture/compare register (cr00/cr01) is overwritten during timer operation, match interrupt may be generated or the clear operation may not be performed normally if that value is close to or large than the timer value. <2> the capture operation may not be performed for cr00/cr01 set in compare mode even if a capture trigger is input. (10) edge detection <1> if the ti00 pin or the ti01 pin is high level immediately after system reset and the rising edge or both the rising and falling edges are specified as the valid edge for the ti00 pin or ti01 pin to enable 16-bit timer counter 0 (tm0) operation, a rising edge is detected immediately. be careful when pulling up the ti00 pin or the ti01 pin. however, the rising edge is not detected at restart after the operation has been stopped once. <2> the sampling clock used to remove noise differs when a ti00 valid edge is used as the count clock and when it is used as a capture trigger. in the former case, the count clock is f x /2 3 , and in the latter case the count clock is selected by prescaler mode register 0 (prm0). the capture operation is not performed until the valid edge is sampled and the valid level is detected twice, thus eliminating noise with a short pulse width. (11) stop mode or main system clock stop mode setting except when ti00, ti01 input is selected, stop the timer operation before setting stop mode or main system clock stop mode; otherwise the timer may malfunction when the main system clock starts.
219 user? manual u14046ej3v0ud chapter 9 8-bit timer/event counters 50, 51 9.1 functions of 8-bit timer/event counters 50, 51 8-bit timer/event counters 50, 51 (tm50, tm51) have the following two modes. (1) mode using 8-bit timer/event counters 50, 51 alone (discrete mode) the timer operates as 8-bit timer/event counter 50 or 51. it has the following functions. <1> interval timer interrupt requests are generated at the preset interval. number of counts: 1 to 256 <2> external event counter the number of pulses with high/low level widths of the signal input externally can be measured. <3> square-wave output a square wave with an arbitrary frequency can be output. cycle: (1 2 to 256 2) cycles of count clock <4> pwm output a pulse with an arbitrary duty ratio can be output. cycle: count clock 256 duty ratio: set value of compare register/256 (2) mode using cascade connection (16-bit resolution: cascade connection mode) the timer operates as a 16-bit timer/event counter by combining two 8-bit timer/event counters. it has the following functions. interval timer with 16-bit resolution external event counter with 16-bit resolution square-wave output with 16-bit resolution figures 9-1 and 9-2 show block diagrams of 8-bit timer/event counters 50 and 51.
220 chapter 9 8-bit timer/event counters 50, 51 user? manual u14046ej3v0ud figure 9-1. block diagram of 8-bit timer/event counter 50 figure 9-2. block diagram of 8-bit timer/event counter 51 notes 1. the respective combinations, ti50 input and to50 output, and ti51 input and to51 output, cannot be used at the same time. 2. timer output f/f 3. pwm output f/f output latch (p72) pm72 to50/ti50/ p72 note 1 internal bus 8-bit timer compare register 50 (cr50) ti50/to50/p72 note 1 f x /2 4 f x /2 6 f x /2 8 f x /2 10 f x f x /2 2 match mask circuit ovf clear 3 selector tcl502 tcl501 tcl500 timer clock select register 50 (tcl50) internal bus tce50 tmc506 tmc504 lvs50 lvr50 tmc501 toe50 invert level 8-bit timer mode control register 50 (tmc50) s r s q r inv selector inttm50 note 2 note 3 selector 8-bit timer counter 50 (tm50) selector output latch (p73) pm73 to51/ti51/ p73 note 1 internal bus ti51/to51/p73 note 1 f x /2 3 f x /2 5 f x /2 7 f x /2 9 f x /2 match mask circuit ovf clear 3 tcl512 tcl511 tcl510 timer clock select register 51 (tcl51) internal bus tce51 tmc516 tmc514 lvs51 lvr51 tmc511 toe51 invert level 8-bit timer mode control register 51 (tmc51) s r q r inv selector inttm51 selector selector selector 8-bit timer compare register 51 (cr51) 8-bit timer counter 51 (tm51) s f x /2 11 note 2 note 3
221 chapter 9 8-bit timer/event counters 50, 51 user s manual u14046ej3v0ud 9.2 configuration of 8-bit timer/event counters 50, 51 8-bit timer/event counters 50, 51 consist of the following hardware. table 9-1. configuration of 8-bit timer/event counters 50, 51 item configuration timer counter 8-bit timer counter 5n (tm5n) register 8-bit timer compare register 5n (cr5n) timer input ti5n timer output to5n control registers timer clock select register 5n (tcl5n) 8-bit timer mode control register 5n (tmc5n) port mode register 7 (pm7) port 7 (p7) (1) 8-bit timer counter 5n (tm5n: n = 0, 1) tm5n is an 8-bit read-only register that counts the count pulses. the counter is incremented in synchronization with the rising edge of the count clock. when tm50 and tm51 can be connected in cascade and used as a 16-bit timer, they can be read by a 16-bit memory manipulation instruction. however, since they are connected by an internal 8-bit bus, tm50 and tm51 are read separately twice in that order. thus, take reading during the count change into consideration and compare them by reading twice. when the count value is read during operation, the count clock input is temporarily stopped note , and then the count value is read. in the following situations, count value is cleared to 00h. <1> reset input <2> when tce5n is cleared <3> when tm5n and cr5n match in the clear & start mode entered on a match between tm5n and cr5n. note an error may occur in the count. select a count clock with a high/low-level waveform longer than two cycles of the cpu clock. caution in cascade connection mode, the count value is reset to 0000h when tce50 of the lowest timer is cleared. (2) 8-bit timer compare register 5n (cr5n: n = 0, 1) when cr5n is used as a compare register in other than pwm mode, the value set in cr5n is constantly compared with the 8-bit timer counter 5n (tm5n) count value, and an interrupt request (inttm5n) is generated if they match. in pwm mode, the to5n pin goes to the active level by the overflow of tm5n. when the values of tm5n and cr5n match, the to5n pin goes to the inactive level. it is possible to rewrite the value of cr5n within 00h to ffh during a count operation. when tm50 and tm51 can be connected in cascade and used as a 16-bit timer, cr50 and cr51 operate as a 16-bit compare register. this register compares the count value with the register value, and if the values match, an interrupt request (inttm50) is generated. the inttm51 interrupt request is also generated at this time. thus, mask the inttm51 interrupt request. cr5n is set by an 8-bit memory manipulation instruction. reset input makes cr5n undefined. caution in cascade connection mode, stop the timer operation before setting data. remark n = 0, 1
222 chapter 9 8-bit timer/event counters 50, 51 user s manual u14046ej3v0ud 9.3 registers to control 8-bit timer/event counters 50, 51 the following four types of registers are used to control 8-bit timer/event counters 50, 51. timer clock select register 5n (tcl5n) 8-bit timer mode control register 5n (tmc5n) port mode register 7 (pm7) port 7 (p7) remark n = 0, 1 (1) timer clock select register 5n (tcl5n: n = 0, 1) this register sets the count clock of 8-bit timer/event counter 5n and the valid edge of ti50, ti51 input. tcl5n is set by an 8-bit memory manipulation instruction. reset input clears tcl5n to 00h. figure 9-3. format of timer clock select register 50 (tcl50) address: ff71h after reset: 00h r/w symbol 76543210 tcl50 00000 tcl502 tcl501 tcl500 tcl502 tcl501 tcl500 count clock selection f x = 8.38 mhz f x = 12 mhz note 0 0 0 ti50 falling edge ?? 0 0 1 ti50 rising edge ?? 010f x 8.38 mhz 12 mhz 011f x /2 2 2.09 mhz 3 mhz 100f x /2 4 523 khz 750 khz 101f x /2 6 131 khz 187 khz 110f x /2 8 32.7 khz 46.8 khz 111f x /2 10 8.18 khz 11.7 khz note expanded-specification products of pd780024a, 780034a subseries only. cautions 1. when rewriting tcl50 to other data, stop the timer operation beforehand. 2. be sure to clear bits 3 to 7 to 0. remarks 1. when cascade connection is used, only tcl50 is valid for count clock setting. 2. f x : main system clock oscillation frequency
223 chapter 9 8-bit timer/event counters 50, 51 user s manual u14046ej3v0ud figure 9-4. format of timer clock select register 51 (tcl51) address: ff79h after reset: 00h r/w symbol 76543210 tcl51 00000 tcl512 tcl511 tcl510 tcl512 tcl511 tcl510 count clock selection f x = 8.38 mhz f x = 12 mhz note 0 0 0 ti51 falling edge ?? 0 0 1 ti51 rising edge ?? 010f x /2 4.19 mhz 6 mhz 011f x /2 3 1.04 mhz 1.5 mhz 100f x /2 5 261 khz 375 khz 101f x /2 7 65.4 khz 93.7 khz 110f x /2 9 16.3 khz 23.4 khz 111f x /2 11 4.09 khz 5.85 khz note expanded-specification products of pd780024a, 780034a subseries only. cautions 1. when rewriting tcl51 to other data, stop the timer operation beforehand. 2. be sure to clear bits 3 to 7 to 0. remarks 1. when cascade connection is used, only tcl50 is valid for count clock setting. 2. f x : main system clock oscillation frequency (2) 8-bit timer mode control register 5n (tmc5n: n = 0, 1) tmc5n is a register that makes the following six settings. <1> 8-bit timer counter 5n (tm5n) count operation control <2> 8-bit timer counter 5n (tm5n) operating mode selection <3> discrete mode/cascade connection mode selection (tmc51 only) <4> timer output f/f (flip-flop) status setting <5> active level selection in timer f/f control or pwm (free-running) mode. <6> timer output control tmc5n is set by a 1-bit or 8-bit memory manipulation instruction. reset input clears tmc5n to 00h.
224 chapter 9 8-bit timer/event counters 50, 51 user s manual u14046ej3v0ud figure 9-5. format of 8-bit timer mode control register 50 (tmc50) address: ff70h after reset: 00h r/w symbol <7> 6 5 4 <3> <2> 1 <0> tmc50 tce50 tmc506 0 0 lvs50 lvr50 tmc501 toe50 tce50 tm50 count operation control 0 after clearing to 0, count operation disabled (prescaler disabled) 1 count operation start tmc506 tm50 operating mode selection 0 clear and start mode by match between tm50 and cr50 1 pwm (free-running) mode lvs50 lvr50 timer output f/f status setting 0 0 no change 0 1 timer output f/f reset (0) 1 0 timer output f/f set (1) 1 1 setting prohibited tmc501 in other modes (tmc506 = 0) in pwm mode (tmc506 = 1) timer f/f control active level selection 0 inversion operation disabled active high 1 inversion operation enabled active low toe50 timer output control 0 output disabled (port mode) 1 output enabled remarks 1. in pwm mode, pwm output will be inactive because tce50 = 0. 2. if lvs50 and lvr50 are read after data is set, 0 is read.
225 chapter 9 8-bit timer/event counters 50, 51 user s manual u14046ej3v0ud figure 9-6. format of 8-bit timer mode control register 51 (tmc51) address: ff78h after reset: 00h r/w symbol <7> 6 5 4 <3> <2> 1 <0> tmc51 tce51 tmc516 0 tmc514 lvs51 lvr51 tmc511 toe51 tce51 tm51 count operation control 0 after clearing to 0, count operation disabled (prescaler disabled) 1 count operation start tmc516 tm51 operating mode selection 0 clear and start mode by match between tm51 and cr51 1 pwm (free-running) mode tmc514 discrete mode/cascade connection mode selection 0 discrete mode 1 cascade connection mode (tm50: lower timer, tm51: higher timer) lvs51 lvr51 timer output f/f status setting 0 0 no change 0 1 timer output f/f reset (0) 1 0 timer output f/f set (1) 1 1 setting prohibited tmc511 in other modes (tmc516 = 0) in pwm mode (tmc516 = 1) timer f/f control active level selection 0 inversion operation disabled active high 1 inversion operation enabled active low toe51 timer output control 0 output disabled (port mode) 1 output enabled remarks 1. in pwm mode, pwm output will be inactive because tce51 = 0. 2. if lvs51 and lvr51 are read after data is set, 0 is read.
226 chapter 9 8-bit timer/event counters 50, 51 user s manual u14046ej3v0ud (3) port mode register 7 (pm7) this register sets port 7 input/output in 1-bit units. when using the p72/to50/ti50 and p73/ti51/to51 pins for timer output, clear pm72, pm73, and the output latches of p72 and p73 to 0. when using the p72/to50/ti50 and p73/ti51/to51 pins for timer input, set pm72 and pm73 to 1. at this time, the output latches of p72 and p73 can be either 0 or 1. pm7 is set by a 1-bit or 8-bit memory manipulation instruction. reset input sets pm7 to ffh. figure 9-7. format of port mode register 7 (pm7) address: ff27h after reset: ffh r/w symbol 7 6 5 4 3 2 1 0 pm7 1 1 pm75 pm74 pm73 pm72 pm71 pm70 pm7n p7n pin i/o mode selection (n = 0 to 5) 0 output mode (output buffer on) 1 input mode (output buffer off)
227 chapter 9 8-bit timer/event counters 50, 51 user s manual u14046ej3v0ud 9.4 operation of 8-bit timer/event counters 50, 51 9.4.1 8-bit interval timer operation the 8-bit timer/event counters operate as interval timers that generate interrupt requests repeatedly at intervals of the count value preset to 8-bit timer compare register 5n (cr5n). when the count value of 8-bit timer counter 5n (tm5n) matches the value set to cr5n, counting continues with the tm5n value cleared to 0 and an interrupt request signal (inttm5n) is generated. the count clock of tm5n can be selected with bits 0 to 2 (tcl5n0 to tcl5n2) of timer clock select register 5n (tcl5n). [setting] <1> set the registers. tcl5n: select count clock. cr5n: compare value tmc5n: count operation stop, clear & start mode on match between tm5n and cr5n. (tmc5n = 0000 0b = don t care) <2> after tce5n = 1 is set, count operation starts. <3> if the values of tm5n and cr5n match, inttm5n is generated (tm5n is cleared to 00h). <4> inttm5n is generated repeatedly at the same interval. clear tce5n to 0 to stop the count operation. remark n = 0, 1
228 chapter 9 8-bit timer/event counters 50, 51 user s manual u14046ej3v0ud figure 9-8. interval timer operation timing (1/3) (a) basic operation t count clock tm5n count value cr5n tce5n inttm5n to5n start count clear clear 00h 01h n 00h 01h n 00h 01h n n n n n interrupt acknowledged interrupt acknowledged interval time interval time remarks 1. interval time = (n + 1) t n = 00h to ffh 2. n = 0, 1
229 chapter 9 8-bit timer/event counters 50, 51 user s manual u14046ej3v0ud figure 9-8. interval timer operation timing (2/3) (b) when cr5n = 00h t count clock tm5n cr5n tce5n inttm5n to5n interval time 00h 00h 00h 00h 00h (c) when cr5n = ffh t count clock tm5n cr5n tce5n inttm5n to5n 01h feh ffh 00h feh ffh 00h ffh ffh ffh interval time interrupt acknowledged interrupt acknowledged remark n = 0, 1
230 chapter 9 8-bit timer/event counters 50, 51 user s manual u14046ej3v0ud figure 9-8. interval timer operation timing (3/3) (d) operated by cr5n transition (m < n) count clock tm5n cr5n tce5n inttm5n to5n 00h n n m n ffh 00h m 00h m cr5n transition tm5n overflows since m < n h (e) operated by cr5n transition (m > n) count clock tm5n cr5n tce5n inttm5n to5n n ? 1n n 00h 01h n m ? 1 m 00h 01h m cr5n transition h remark n = 0, 1
231 chapter 9 8-bit timer/event counters 50, 51 user s manual u14046ej3v0ud 9.4.2 external event counter operation the external event counter counts the number of external clock pulses to be input to ti5n using 8-bit timer counter 5n (tm5n). tm5n is incremented each time the valid edge specified by timer clock select register 5n (tcl5n) is input. either the rising or falling edge can be selected. when the tm5n count value matches the value of 8-bit timer compare register 5n (cr5n), tm5n is cleared to 0 and an interrupt request signal (inttm5n) is generated. whenever the tm5n count value matches the value of cr5n, inttm5n is generated. [setting] <1> set each register tcl5n: edge selection of ti5n input falling edge of ti5n tcl5n = 00h rising edge of ti5n tcl5n = 01h cr5n: compare value tmc5n: count operation stop, clear & start mode on match between tm5n and cr5n, timer f/f inverted operation disable, timer output disable (tmc5n = 0000 00b, = don t care) <2> when tce5n = 1 is set, the number of pulses input from ti5n is counted. <3> when the values of tm5n and cr5n match, inttm5n is generated (tm5n is cleared to 00h). <4> each time the values of tm5n and cr5n match, inttm5n is generated. figure 9-9. external event counter operation timing (with rising edge specified) ti5n tm5n count value cr5n inttm5n 00h 01h 02h 03h 04h 05h n ? 1 n 00h 01h 02h 03h n remarks 1. n = 00h to ffh 2. n = 0, 1
232 chapter 9 8-bit timer/event counters 50, 51 user s manual u14046ej3v0ud 9.4.3 square-wave output (8-bit resolution) operation a square wave with any selected frequency is output at intervals determined by the value preset to 8-bit timer compare register 5n (cr5n). the to5n pin output status is reversed at intervals determined by the count value preset to cr5n by setting bit 0 (toe5n) of 8-bit timer mode control register 5n (tmc5n) to 1. this enables a square wave with any selected frequency to be output (duty = 50%). [setting] <1> set each register clear port latches (p72, p73) note and port mode registers (pm72, pm73) note to 0. tcl5n: select count clock cr5n: compare value tmc5n: count operation stop, clear & start mode on match between tm5n and cr5n lvs5n lvr5n timer output f/f status setting 1 0 high-level output 0 1 low-level output timer output f/f reverse enable timer output enable toe5n = 1 (tmc5n = 00001011b or 00000111b) <2> after tce5n = 1 is set, the count operation starts. <3> timer output f/f is reversed by match between tm5n and cr5n. after inttm5n is generated, tm5n is cleared to 00h. <4> timer output f/f is reversed at the same interval and a square wave is output from to5n. the frequency is as follows. frequency = f cnt /2 (n + 1) (n = 00h to ffh, f cnt : count clock) note 8-bit timer/event counter 50: p72, pm72 8-bit timer/event counter 51: p73, pm73
233 chapter 9 8-bit timer/event counters 50, 51 user s manual u14046ej3v0ud figure 9-10. square-wave output operation timing count clock tm5n count value cr5n to5n note count start 00h 01h 02h n ? 1n 00h 01h 02h n ? 1n 00h n note the to5n output initial value can be set by bits 2 and 3 (lvr5n, lvs5n) of 8-bit timer mode control register 5n (tmc5n). remarks 1. n = 00h to ffh 2. n = 0, 1 9.4.4 8-bit pwm output operation the 8-bit timer/event counter operates as pwm output when bit 6 (tmc5n6) of 8-bit timer mode control register 5n (tmc5n) is set to 1. the duty ratio pulse is determined by the value set to 8-bit timer compare register 5n (cr5n). set the active level width of the pwm pulse to cr5n. the active level can be selected with bit 1 (tmc5n1) of tmc5n. the count clock can be selected with bits 0 to 2 (tcl5n0 to tcl5n2) of timer clock select register 5n (tcl5n). pwm output enable/disable can be selected with bit 0 (toe5n) of tmc5n. cycle = count clock 256 set value of compare register duty ratio = 256 caution cr5n can be rewritten in pwm mode only once per cycle. remark n = 0, 1
234 chapter 9 8-bit timer/event counters 50, 51 user s manual u14046ej3v0ud (1) pwm output basic operation [setting] <1> set each register. clear port latches (p72, p73) note and port mode registers (pm72, pm73) note to 0. tcl5n: count clock selection cr5n: compare value tmc5n: count operation stop, pwm mode selection, timer output f/f not changed tmc5n1 active level selection 0 active high 1 active low timer output enabled (tmc5n = 01000001b or 01000011b) <2> when tce5n = 1 is set, the count operation is started. to stop the count operation, clear tce5n to 0. note 8-bit timer/event counter 50: p72, pm72 8-bit timer/event counter 51: p73, pm73 [pwm output operation] <1> pwm output (output from to5n) outputs an inactive level after the count operation starts until an overflow occurs. <2> when an overflow occurs, the active level is output. the active level is output until cr5n matches the count value of 8-bit timer counter 5n (tm5n). <3> after cr5n matches the count value, pwm output outputs the inactive level again until an overflow occurs. <4> operations <2> and <3> are repeated until the count operation stops. <5> when the count operation is stopped by setting tce5n = 0, pwm output becomes the inactive level. remark n = 0, 1
235 chapter 9 8-bit timer/event counters 50, 51 user s manual u14046ej3v0ud figure 9-11. pwm output operation timing (a) basic operation (active level = h) count clock tm5n cr5n tce5n inttm5n to5n 00h 01h ffh 00h 01h 02h n n + 1 ffh 00h 01h 02h m 00h n active level active level inactive level (b) cr5n = 0 count clock tm5n cr5n tce5n inttm5n to5n l inactive level inactive level 01h 00h ffh 00h 01h 02h n n + 1 ffh 00h 01h 02h m 00h 00h n + 2 (c) cr5n = ffh tm5n count clock cr5n tce5n inttm5n to5n 01h 00h ffh 00h 01h 02h n n + 1 ffh 00h 01h 02h m 00h ffh n + 2 inactive level active level inactive level active level inactive level remark n = 0, 1
236 chapter 9 8-bit timer/event counters 50, 51 user s manual u14046ej3v0ud (2) operated by cr5n transition figure 9-12. timing of operation by change of cr5n (a) cr5n value is changed from n to m when tm5n > cr5n count clock tm5n cr5n tce5n inttm5n to5n cr5n transition (n m) n n + 1 n + 2 ffh 00h 01h m m + 1 m + 2 ffh 00h 01h 02h m m + 1 m + 2 n 02h m h (b) cr5n value is changed from n to m when tm5n < cr5n count clock tm5n cr5n tce5n inttm5n to5n n n + 1 n + 2 ffh 00h 01h n n + 1 n + 2 ffh 00h 01h 02h n 02h n h 03h m m m + 1 m + 2 cr5n transition (n m) remark n = 0, 1
237 chapter 9 8-bit timer/event counters 50, 51 user s manual u14046ej3v0ud 9.4.5 interval timer (16-bit) operations when bit 4 (tmc514) of 8-bit timer mode control register 51 (tmc51) is set to 1, the 16-bit resolution timer/counter mode is entered. the 8-bit timer/event counter operates as an interval timer that generates interrupt requests repeatedly at intervals of the count value preset to the 8-bit timer compare registers (cr50, cr51). [setting] <1> set each register tcl50: select count clock for tm50. cascade-connected tm51 need not be selected. cr50, cr51: compare value (each value can be set to 00h to ffh) tmc50, tmc51: select the clear & start mode entered on a match between tm50 and cr50 (tm51 and cr51). tm50 tmc50 = 0000 0b : don t care tm51 tmc51 = 0001 0b : don t care <2> when tmc51 is set to tce51 = 1 and then tmc50 is set to tce50 = 1, the count operation starts. <3> when the values of tm50 and cr50 of the cascade-connected timer match, inttm50 of tm50 is generated (tm50 and tm51 are cleared to 00h). <4> inttm50 is generated repeatedly at the same interval. cautions 1. stop the timer operation without fail before setting the compare registers (cr50, cr51). 2. inttm51 of tm51 is generated when the tm51 count value matches cr51, even if cascade connection is used. be sure to mask tm51 to disable interrupts. 3. set tce50 and tce51 in order of tm51 then tm50. 4. count restart/stop can only be controlled by setting tce50 of tm50 to 1/0. figure 9-13 shows an example of 16-bit resolution cascade connection mode timing. figure 9-13. 16-bit resolution cascade connection mode count clock tm50 tm51 cr50 cr51 tce50 tce51 inttm50 to50 operation enable count start interval time 00h 01h n n + 1 ffh 00h ffh 00h ffh 00h 01h n 00h 01h a 00h 00h 01h 02h m ? 1 m 00h b 00h n m interrupt request generation level reverse counter clear operation stop
238 chapter 9 8-bit timer/event counters 50, 51 user s manual u14046ej3v0ud 9.5 program list caution the following sample program is shown as an example to describe the operation of semiconductor products and their applications. therefore, when applying the following information to your devices, design the devices after performing evaluation under your own responsibility. 9.5.1 interval timer (8-bit) /*************************************************************************************/ /* */ /* timer 50 operation sample */ /* interval timer setting example (cycle change by interrupt servicing) */ /* data[0]: data set flag (value changed when other than 00) */ /* data[1]: set data */ /* */ /*************************************************************************************/ #pragma sfr #pragma ei #pragma di #pragma interrupt inttm50 intervalint rb2 unsigned char data[2]; /* data area */ void main(void) { pcc = 0x0; /* set high-speed operation mode */ data[0] = 0; /* clear data area */ data[1] = 0; /* set port */ p7 = 0b11111011; /* when using to50 */ pm7.2 = 0; /* set p72 to output */ /* set interrupt */ tmmk50 = 0; /* clear inttm50 interrupt mask */ /* set timer 50 */ tmc50 = 0b00000111; /* clear & start mode, initial value l */ tcl50 = 0b00000101; /* both rising and falling edges */ /* count clock is fx/2^6 */ cr50 = 131; /* set interval to 1 ms as initial value */ tce50 = 1; /* timer start */ ei(); while(1); /* dummy loop */ } /* inttm50 interrupt function */ void intervalint() { if(data[0] != 0) { cr50 = data[1]; /* set new set value */ data[0] = 0; /* clear request flag */ } }
239 chapter 9 8-bit timer/event counters 50, 51 user s manual u14046ej3v0ud 9.5.2 external event counter /***************************************************************/ /* */ /* timer 50 operation sample */ /* event counter setting example */ /* data: count up flag */ /* */ /***************************************************************/ #pragma sfr #pragma ei #pragma di #pragma interrupt inttm50 intervalint rb2 unsigned char data; /* data area */ void main(void) { pcc = 0x0; /* set high-speed operation mode */ data = 0; /* clear data area */ /* set port */ pm7.2 = 1; /* set p72 to input */ /* set interrupt */ tmmk50 = 0; /* clear inttm50 interrupt mask */ /* set timer 50 */ tmc50 = 0b00000000; /* clear & start mode */ tcl50 = 0b00000001; /* specify rising edge of ti50 */ cr50 = 0x10; /* set n = 16 as initial value */ tce50 = 1; /* timer start */ ei(); /*************************************************************/ /* */ /* describe the processing to be executed */ /* */ /*************************************************************/ while(data == 0); /* wait for count up */ /*************************************************************/ /* */ /* describe the processing after count up below */ /* */ /*************************************************************/ } /* inttm50 interrupt function */ void intervalint() { data = 0xff; /* set count up flag */ tce50 = 0; /* timer stop */ }
240 chapter 9 8-bit timer/event counters 50, 51 user s manual u14046ej3v0ud 9.5.3 interval timer (16-bit) /***************************************************************/ /* */ /* timer 5 operation sample */ /* cascade connection setting example */ /* */ /***************************************************************/ #pragma sfr #pragma ei #pragma di #define intervaltm5 130 /* cycle data to be set to cr */ #pragma interrupt inttm50 ppgint rb2 unsigned char ppgdata[2]; /* data area to be set to timer 5 */ void main(void) { int interval; interval = intervaltm5; pcc = 0x0; /* select high-speed operation mode */ ppgdata[0] = 0; /* clear cr50 data */ ppgdata[1] = 0; /* clear cr51 data */ /* set port */ p7 = 0b11111011; /* clear p72 */ pm7.2 = 0; /* set p72 to output */ /* set interrupt */ tmmk50 = 0; /* clear inttm50 interrupt mask */ tmmk51 = 1; /* set inttm51 interrupt mask */ /* set timer 5 */ tcl50 = 0b00000101; /* count clock is fx/2^6 */ cr50 = interval & 0xff; /* set lower compare register to cr50 */ cr51 = interval >> 8; /* set higher compare register to cr51 */ tmc50 = 0b00000111; /* inverted on match, initial value l */ tmc51 = 0b00010000; /* cascade mode */ tce51 = 1; tce50 = 1; /* timer starts */ ei(); while(1); } /* timer 5 interrupt function */ void ppgint() { unsigned int work; work = ppgdata[0]+ppgdata[1]*0x100; if (work != 0) { tce50 =0; cr51 = work >> 8; cr50 = work & 0xff; ppgdata[0] = 0; ppgdata[1] = 0; if (work != 0xffff) { tce50 = 1; /* timer resumes */ } } }
241 chapter 9 8-bit timer/event counters 50, 51 user s manual u14046ej3v0ud 9.6 cautions related to 8-bit timer/event counters 50, 51 (1) timer start errors an error of up to one clock may occur in the time required for a match signal to be generated after timer start. this is because 8-bit timer counter 5n (tm5n) is started asynchronously to the count pulse. figure 9-14. start timing of 8-bit timer counter 5n (tm5n) count pulse tm5n count 00h 01h 02h 03h 04h timer start (2) setting stop mode or main system clock stop mode except when ti5n input is selected, always set tce5n = 0 before setting the stop mode or main system clock stop mode. the timer may malfunction when the main system clock starts oscillating. (3) tm5n (n = 0, 1) reading during timer operation when reading tm5n during operation, the count clock stops temporarily, so select a count clock with a high/low- level waveform longer than two cycles of the cpu clock. for example, in the case where the cpu clock (f cpu ) is f x , when the selected count clock is f x /4 or below, it can be read. remark n = 0, 1
242 user? manual u14046ej3v0ud chapter 10 watch timer 10.1 watch timer functions the watch timer has the following functions. (1) watch timer when the main system clock or subsystem clock is used, interrupt requests (intwt) are generated at 2 14 /f w second intervals. (2) interval timer interrupt requests (intwti) are generated at the preset time interval. for the interval time, see table 10-2 . the watch timer and the interval timer can be used simultaneously. figure 10-1 shows the watch timer block diagram. figure 10-1. watch timer block diagram remark f w : watch timer clock frequency (f x /2 7 or f xt ) f x : main system clock oscillation frequency f xt : subsystem clock oscillation frequency f x /2 7 f xt f w f w 2 4 f w 2 5 f w 2 6 f w 2 7 f w 2 8 f w 2 9 clear 9-bit prescaler clear 5-bit counter intwt intwti wtm7 wtm6 wtm5 wtm4 wtm1 wtm0 watch timer operation mode register (wtm) internal bus selector selector
243 chapter 10 watch timer user s manual u14046ej3v0ud 10.2 watch timer configuration the watch timer consists of the following hardware. table 10-1. watch timer configuration item configuration counter 5 bits 1 prescaler 9 bits 1 control register watch timer operation mode register (wtm)
244 chapter 10 watch timer user s manual u14046ej3v0ud 10.3 register to control watch timer the watch timer is controlled by the watch timer operation mode register (wtm). watch timer operation mode register (wtm) this register sets the watch timer count clock, enables/disables operation, sets the prescaler interval time, and controls the 5-bit counter operation. wtm is set by a 1-bit or 8-bit memory manipulation instruction. reset input clears wtm to 00h. figure 10-2. format of watch timer operation mode register (wtm) address: ff41h after reset: 00h r/w symbol 765432<1><0> wtm wtm7 wtm6 wtm5 wtm4 0 0 wtm1 wtm0 wtm7 watch timer count clock selection 0f x /2 7 (65.4 khz: f x = 8.38 mhz, 93.7 khz: f x = 12 mhz note ) 1f xt (32.768 khz: f xt = 32.768 khz) wtm6 wtm5 wtm4 prescaler interval time selection 0002 4 /f w 0012 5 /f w 0102 6 /f w 0112 7 /f w 1002 8 /f w 1012 9 /f w other than above setting prohibited wtm1 5-bit counter operation control 0 clear after operation stop 1 start wtm0 watch timer operation enable 0 operation stopped (both prescaler and timer cleared) 1 operation enabled note expanded-specification products of pd780024a, 780034a subseries only. caution do not change the count clock and interval time (by using bits 4 to 7 (wtm4 to wtm7) of wtm) while the watch timer is operating. remarks 1. f w : watch timer clock frequency (f x /2 7 or f xt ) 2. f x : main system clock oscillation frequency 3. f xt : subsystem clock oscillation frequency
245 chapter 10 watch timer user s manual u14046ej3v0ud 10.4 watch timer operations 10.4.1 watch timer operation the watch timer generates an interrupt request (intwt) at specific time intervals (2 14 /f w seconds) by using the main system clock or subsystem clock. the interrupt request is generated at the following time intervals: if main system clock (8.38 mhz) is selected: 0.25 seconds if subsystem clock (32.768 khz) is selected: 0.5 seconds when bit 0 (wtm0) and bit 1 (wtm1) of the watch timer operation mode register (wtm) are set to 1, the count operation starts, and when these bits are cleared to 0, the 5-bit counter is cleared and the count operation stops. when the interval timer is simultaneously operated, a zero-second start can be achieved for the watch timer by setting wtm1 to 1 after clearing it to 0. in this case, however, the 9-bit prescaler is not cleared. therefore, an error up to 2 9 /f w seconds occurs in the first overflow (intwt) after the zero-second start. remark f w : watch timer clock frequency (f x /2 7 or f xt ) 10.4.2 interval timer operation the watch timer operates as interval timer that generates interrupt requests (intwti) repeatedly at an interval of the preset count value. the interval time can be selected with bits 4 to 6 (wtm4 to wtm6) of the watch timer operation mode register (wtm). table 10-2. interval timer interval time wtm6 wtm5 wtm4 interval when operated at when operated at when operated at when operated at time f x = 12 mhz note f x = 8.38 mhz f x = 4.19 mhz f xt = 32.768 khz 0002 4 /f w 170 s 244 s 488 s 488 s 0012 5 /f w 341 s 488 s 977 s 976 s 0102 6 /f w 682 s 977 s 1.95 ms 1.95 ms 0112 7 /f w 1.36 ms 1.95 ms 3.91 ms 3.90 ms 1002 8 /f w 2.73 ms 3.91 ms 7.82 ms 7.81 ms 1012 9 /f w 5.46 ms 7.82 ms 15.6 ms 15.6 ms other than above setting prohibited note expanded-specification products of pd780024a, 780034a subseries only. remark f w : watch timer clock frequency (f x /2 7 or f xt ) f x : main system clock oscillation frequency f xt : subsystem clock oscillation frequency
246 chapter 10 watch timer user s manual u14046ej3v0ud figure 10-3. operation timing of watch timer/interval timer caution if the watch timer and 5-bit counter are enabled by the watch timer mode control register (wtm) (by setting bits 0 (wtm0) and 1 (wtm1) of wtm to 1), the time from this setting to the occurrence of the first interrupt request (intwt) is not exactly the value set by bit 3 (wtm3) of wtm. this is because the 5-bit counter is late by one output cycle of the 9-bit prescaler in starting counting. the second intwt signal and those that follow are generated exactly at the set time. remark f w : watch timer clock frequency (f x /2 7 or f xt ) n: the number of interval timer operations figures in parentheses are for operation with f w = 32.768 khz. 0h start overflow overflow 5-bit counter count clock watch timer interrupt intwt interval timer interrupt intwti interrupt time of watch timer (0.5 s) interval time (t) t interrupt time of watch timer (0.5 s) n x t n x t
247 user? manual u14046ej3v0ud chapter 11 watchdog timer 11.1 watchdog timer functions the watchdog timer has the following functions. (1) watchdog timer the watchdog timer detects a program loop. upon detection of a program loop, a non-maskable interrupt request or reset can be generated. for the loop detection time, see table 11-2 . (2) interval timer interrupt requests are generated at the preset time intervals. for the interval time, see table 11-3 . caution select the watchdog timer mode or the interval timer mode using the watchdog timer mode register (wdtm). (the watchdog timer and the interval timer cannot be used simultaneously.) figure 11-1 shows a block diagram of the watchdog timer. figure 11-1. watchdog timer block diagram wdt mode signal watchdog timer clock select register (wdcs) watchdog timer mode register (wdtm) f x /2 8 f x run intwdt reset 3 wdcs2 wdcs1 wdcs0 run wdtm4 wdtm3 clock input controller divider circuit divided clock selector output controller division mode selector internal bus
248 chapter 11 watchdog timer user s manual u14046ej3v0ud 11.2 watchdog timer configuration the watchdog timer consists of the following hardware. table 11-1. watchdog timer configuration item configuration control registers watchdog timer clock select register (wdcs) watchdog timer mode register (wdtm) 11.3 registers to control watchdog timer the following two registers are used to control the watchdog timer. watchdog timer clock select register (wdcs) watchdog timer mode register (wdtm) (1) watchdog timer clock select register (wdcs) this register sets the overflow time of the watchdog timer and the interval timer. wdcs is set by an 8-bit memory manipulation instruction. reset input clears wdcs to 00h. figure 11-2. format of watchdog timer clock select register (wdcs) address: ff42h after reset: 00h r/w symbol 76543210 wdcs 00000 wdcs2 wdcs1 wdcs0 wdcs2 wdcs1 wdcs0 overflow time of watchdog timer/interval timer f x = 8.38 mhz f x = 12 mhz note 0002 12 /f x 488 s 341 s 0012 13 /f x 977 s 682 s 0102 14 /f x 1.95 ms 1.36 ms 0112 15 /f x 3.91 ms 2.73 ms 1002 16 /f x 7.82 ms 5.46 ms 1012 17 /f x 15.6 ms 10.9 ms 1102 18 /f x 31.2 ms 21.8 ms 1112 20 /f x 125 ms 87.3 ms note expanded-specification products of pd780024a, 780034a subseries only. remark f x : main system clock oscillation frequency
249 chapter 11 watchdog timer user s manual u14046ej3v0ud (2) watchdog timer mode register (wdtm) this register sets the watchdog timer operating mode and enables/disables counting. wdtm is set by a 1-bit or 8-bit memory manipulation instruction. reset input clears wdtm to 00h. figure 11-3. format of watchdog timer mode register (wdtm) address: fff9h after reset: 00h r/w symbol <7> 6543210 wdtm run 0 0 wdtm4 wdtm3 0 0 0 run watchdog timer operation mode selection note 1 0 count stop 1 counter is cleared and counting starts wdtm4 wdtm3 watchdog timer operation mode selection note 2 0 interval timer mode note 3 (maskable interrupt request occurs upon generation of overflow) 1 0 watchdog timer mode 1 (non-maskable interrupt request occurs upon generation of overflow) 1 1 watchdog timer mode 2 (reset operation is activated upon generation of overflow) notes 1. once set to 1, run cannot be cleared to 0 by software. thus, once counting starts, it can only be stopped by reset input. 2. once set to 1, wdtm3 and wdtm4 cannot be cleared to 0 by software. 3. the watchdog timer starts operation as an interval timer when run is set to 1. caution when run is set to 1 so that the watchdog timer is cleared, the actual overflow time is up to 2 8 /f x seconds shorter than the time set by the watchdog timer clock select register (wdcs). remark : don t care
250 chapter 11 watchdog timer user s manual u14046ej3v0ud 11.4 watchdog timer operations 11.4.1 watchdog timer operation when bit 4 (wdtm4) of the watchdog timer mode register (wdtm) is set to 1, the watchdog timer is operated to detect a program loop. the loop detection time interval is selected with bits 0 to 2 (wdcs0 to wdcs2) of the watchdog timer clock select register (wdcs). the watchdog timer starts by setting bit 7 (run) of wdtm to 1. after the watchdog timer is started, set run to 1 within the set loop time interval. the watchdog timer can be cleared and counting is started by setting run to 1. if run is not set to 1 and the loop detection time is exceeded, system reset or a non-maskable interrupt request is generated according to the value of wdtm bit 3 (wdtm3). the watchdog timer continues operating in the halt mode but it stops in the stop mode. thus, set run to 1 before the stop mode is set, clear the watchdog timer and then execute the stop instruction. cautions 1. the actual loop detection time may be shorter than the set time by up to 2 8 /f x seconds. 2. when the subsystem clock is selected for the cpu clock, the watchdog timer count operation is stopped. table 11-2. watchdog timer loop detection time loop detection time when operated at when operated at f x = 8.38 mhz f x = 12 mhz note 2 12 /f x 488 s 341 s 2 13 /f x 977 s 682 s 2 14 /f x 1.95 ms 1.36 ms 2 15 /f x 3.91 ms 2.73 ms 2 16 /f x 7.82 ms 5.46 ms 2 17 /f x 15.6 ms 10.9 ms 2 18 /f x 31.2 ms 21.8 ms 2 20 /f x 125 ms 87.3 ms note expanded-specification products of pd780024a, 780034a subseries only. remark f x : main system clock oscillation frequency
251 chapter 11 watchdog timer user s manual u14046ej3v0ud 11.4.2 interval timer operation the watchdog timer operates as an interval timer that generates interrupt requests repeatedly at an interval of the preset count value when bit 4 (wdtm4) of the watchdog timer mode register (wdtm) is cleared to 0. the interval time of the interval timer is selected with bits 0 to 2 (wdcs0 to wdcs2) of the watchdog timer clock select register (wdcs). when bit 7 (run) of wdtm is set to 1, the watchdog timer operates as an interval timer. when the watchdog timer operates as an interval timer, the interrupt mask flag (wdtmk) and priority specification flag (wdtpr) are validated and the maskable interrupt request (intwdt) can be generated. among the maskable interrupts, intwdt has the highest priority at default. the interval timer continues operating in the halt mode but it stops in stop mode. thus, set run to 1 before the stop mode is set, clear the interval timer and then execute the stop instruction. cautions 1. once bit 4 (wdtm4) of wdtm is set to 1 (this selects the watchdog timer mode), the interval timer mode is not set unless reset is input. 2. the interval time just after setting wdtm may be shorter than the set time by up to 2 8 /f x seconds. 3. when the subsystem clock is selected for the cpu clock, the watchdog timer count operation is stopped. table 11-3. interval timer interval time interval time when operated at when operated at f x = 8.38 mhz f x = 12 mhz note 2 12 /f x 488 s 341 s 2 13 /f x 977 s 682 s 2 14 /f x 1.95 ms 1.36 ms 2 15 /f x 3.91 ms 2.73 ms 2 16 /f x 7.82 ms 5.46 ms 2 17 /f x 15.6 ms 10.9 ms 2 18 /f x 31.2 ms 21.8 ms 2 20 /f x 125 ms 87.3 ms note expanded-specification products of pd780024a, 780034a subseries only. remark f x : main system clock oscillation frequency
252 user? manual u14046ej3v0ud chapter 12 clock output/buzzer output controller 12.1 clock output/buzzer output controller functions clock output is used for carrier output during remote controlled transmission and clock output for supply to peripheral ics. the clock selected by the clock output select register (cks) is output. in addition, buzzer output is used for square-wave output of the buzzer frequency selected by cks. figure 12-1 shows the block diagram of the clock output/buzzer output controller. figure 12-1. block diagram of clock output/buzzer output controller f x f x /2 10 to f x /2 13 f x to f x /2 7 f xt bzoe bcs1 bcs0 cloe cloe bzoe 84 pcl/p74 buz/p75 bcs0, bcs1 clock controller prescaler selector selector internal bus ccs3 clock output select register (cks) ccs2 ccs1 ccs0 output latch (p75) pm75 output latch (p74) pm74
253 chapter 12 clock output/buzzer output controller user s manual u14046ej3v0ud 12.2 configuration of clock output/buzzer output controller the clock output/buzzer output controller consists of the following hardware. table 12-1. configuration of clock output/buzzer output controller item configuration control registers clock output select register (cks) port mode register (pm7) port 7 (p7) 12.3 register to control clock output/buzzer output controller the following three registers are used to control the clock output/buzzer output controller. clock output select register (cks) port mode register (pm7) port 7 (p7) (1) clock output select register (cks) this register sets output enable/disable for clock output (pcl) and for the buzzer frequency output (buz), and sets the output clock. cks is set by a 1-bit or 8-bit memory manipulation instruction. reset input clears cks to 00h.
254 chapter 12 clock output/buzzer output controller user s manual u14046ej3v0ud figure 12-2. format of clock output select register (cks) address: ff40h after reset: 00h r/w symbol <7> 6 5 <4> 3210 cks bzoe bcs1 bcs0 cloe ccs3 ccs2 ccs1 ccs0 bzoe buz output enable/disable specification 0 stop clock divider operation. buz fixed to low level. 1 enable clock divider operation. buz output enabled. bcs1 bcs0 buz output clock selection f x = 8.38 mhz f x = 12 mhz note 00f x /2 10 8.18 khz 11.7 khz 01f x /2 11 4.09 khz 5.85 khz 10f x /2 12 2.04 khz 2.92 khz 11f x /2 13 1.02 khz 1.46 khz cloe pcl output enable/disable specification 0 stop clock divider operation. pcl fixed to low level. 1 enable clock divider operation. pcl output enabled. ccs3 ccs2 ccs1 ccs0 pcl output clock selection f x = 8.38 mhz f x = 12 mhz note 0000f x 8.38 mhz 12 mhz 0001f x /2 4.19 mhz 6 mhz 0010f x /2 2 2.09 mhz 3 mhz 0011f x /2 3 1.04 mhz 1.5 mhz 0100f x /2 4 523 khz 750 khz 0101f x /2 5 261 khz 375 khz 0110f x /2 6 130 khz 187 khz 0111f x /2 7 65.4 khz 93.7 khz 1000f xt (32.768 khz) other than above setting prohibited note expanded-specification products of pd780024a, 780034a subseries only. remarks 1. f x : main system clock oscillation frequency 2. f xt : subsystem clock oscillation frequency 3. figures in parentheses are for operation with f xt = 32.768 khz.
255 chapter 12 clock output/buzzer output controller user s manual u14046ej3v0ud (2) port mode register (pm7) this register sets port 7 input/output in 1-bit units. when using the p74/pcl pin for clock output and the p75/buz pin for buzzer output, clear pm74, pm75 and the output latches of p74 and p75 to 0. pm7 is set by a 1-bit or 8-bit memory manipulation instruction. reset input sets pm7 to ffh. figure 12-3. format of port mode register 7 (pm7) address: ff27h after reset: ffh r/w symbol 7 6 5 4 3 2 1 0 pm7 1 1 pm75 pm74 pm73 pm72 pm71 pm70 pm7n p7n pin i/o mode selection (n = 0 to 5) 0 output mode (output buffer on) 1 input mode (output buffer off)
256 chapter 12 clock output/buzzer output controller user s manual u14046ej3v0ud 12.4 operation of clock output/buzzer output controller 12.4.1 operation as clock output the clock pulse is output using the following procedure. <1> select the clock pulse output frequency using bits 0 to 3 (ccs0 to ccs3) of the clock output select register (cks) (clock pulse output in disabled state). <2> set bit 4 (cloe) of cks to 1, and enable clock output. remark the clock output controller is designed not to output pulses with a small width during output enable/ disable switching of the clock output. as shown in figure 12-4, be sure to start output from the low period of the clock (marked with * in the figure). when stopping output, do so after securing the high level of the clock. figure 12-4. remote control output application example cloe clock output ** 12.4.2 operation as buzzer output the buzzer frequency is output using the following procedure. <1> select the buzzer output frequency using bits 5 and 6 (bcs0, bcs1) of the clock output select register (cks) (buzzer output in disabled state). <2> set bit 7 (bzoe) of cks to 1 to enable buzzer output.
257 user? manual u14046ej3v0ud chapter 13 8-bit a/d converter ( pd780024a, 780024ay subseries) 13.1 a/d converter functions a/d converter is an 8-bit resolution converter that converts analog inputs into digital values. it can control up to 8 analog input channels (ani0 to ani7). (1) hardware start conversion is started by trigger input (adtrg: rising edge, falling edge, or both rising and falling edges can be specified). (2) software start conversion is started by setting a/d converter mode register 0 (adm0). select one channel for analog input from ani0 to ani7 to perform a/d conversion. in the case of hardware start, a/d conversion stops when an a/d conversion operation ends and an interrupt request (intad0) is generated. in the case of software start, a/d conversion is repeated. each time an a/d conversion operation ends, an interrupt request (intad0) is generated. caution although the pd78f0034a, 78f0034b, 78f0034ay, and 78f0034by incorporate a 10-bit a/d converter, this converter can be operated as an 8-bit a/d converter by using the device file df780024.
258 chapter 13 8-bit a/d converter ( pd780024a, 780024ay subseries) user? manual u14046ej3v0ud figure 13-1. 8-bit a/d converter block diagram note the valid edge of external interrupt is specified by bit 3 of the egp and egn registers (see figure 19-5 format of external interrupt rising edge enable register (egp), external interrupt falling edge enable register (egn) ). ani0/p10 ani1/p11 ani2/p12 ani3/p13 ani4/p14 ani5/p15 ani6/p16 ani7/p17 sample & hold circuit voltage comparator successive approximation register (sar) controller edge detector adtrg/intp3/p03 3 a/d conversion result register 0 (adcr0) av dd av ref av ss intad0 intp3 trigger enable a/d converter mode register 0 (adm0) analog input channel specification register 0 (ads0) internal bus ads02 ads01 ads00 adsc0 trg0 fr02 fr01 fr00 ega01 ega00 selector tap selector edge detector note series resistor string
259 chapter 13 8-bit a/d converter ( pd780024a, 780024ay subseries) user s manual u14046ej3v0ud 13.2 a/d converter configuration the a/d converter consists of the following hardware. table 13-1. a/d converter configuration item configuration analog input 8 channels (ani0 to ani7) hardware trigger input 1 (adtrg) registers successive approximation register (sar) a/d conversion result register 0 (adcr0) control registers a/d converter mode register 0 (adm0) analog input channel specification register 0 (ads0) (1) successive approximation register (sar) this register compares the analog input voltage value to the voltage tap (compare voltage) value applied from the series resistor string, and holds the result from the most significant bit (msb). when up to the least significant bit (lsb) is held (end of a/d conversion), the sar contents are transferred to a/d conversion result register 0 (adcr0). (2) a/d conversion result register 0 (adcr0) the adcr0 is an 8-bit register that stores the a/d conversion result. each time a/d conversion ends, the conversion result is loaded from the successive approximation register. adcr0 is read by an 8-bit memory manipulation instruction. reset input clears adcr0 to 00h. caution when writing is performed to a/d converter mode register 0 (adm0) and analog input channel specification register 0 (ads0), the contents of adcr0 may become undefined. read the conversion result following conversion completion before writing to adm0, ads0. using a timing other than the above may cause an incorrect conversion result to be read. (3) sample & hold circuit the sample & hold circuit samples the input signal of the analog input pin selected by the selector when a/d conversion is started and holds the sampled analog input voltage value during a/d conversion. (4) voltage comparator the voltage comparator compares the sampled analog input voltage to the series resistor string output voltage. (5) series resistor string the series resistor string is connected between av ref and av ss , and generates a voltage to be compared to the analog input.
260 chapter 13 8-bit a/d converter ( pd780024a, 780024ay subseries) user s manual u14046ej3v0ud (6) ani0 to ani7 pins these are eight analog input pins to input analog signals to undergo a/d conversion to the a/d converter. ani0 to ani7 are alternate-function pins that can also be used for digital input. cautions 1. use ani0 to ani7 input voltages within the specification range. if a voltage higher than av ref or lower than av ss is applied (even if within the absolute maximum rating range), the conversion value of that channel will be undefined and the conversion values of other channels may also be affected. 2. analog input (ani0 to ani7) pins are alternate function pins that can also be used as input port (p10 to p17) pins. when a/d conversion is performed by selecting any one of ani0 to ani7, do not access port 1 during conversion. it may cause the lower conversion resolution. 3. when a digital pulse is applied to a pin adjacent to the pin in the process of a/d conversion, a/d conversion values may not be obtained as expected due to coupling noise. thus, do not apply any pulse to a pin adjacent to the pin in the process of a/d conversion. (7) av ref pin this pin inputs the a/d converter reference voltage. it converts signals input to ani0 to ani7 into digital signals according to the voltage applied between av ref and av ss . caution a series resistor string of several 10 k ? is connected between the av ref pin and av ss pin. therefore, when the output impedance of the reference voltage is too high, it seems as if the av ref pin and the series resistor string are connected in series. this may cause a greater reference voltage error. (8) av ss pin this is the ground potential pin of the a/d converter. always keep it at the same potential as the v ss0 or v ss1 pin even when not using the a/d converter. (9) av dd pin this is the a/d converter analog power supply pin. always keep it at the same potential as the v dd0 or v dd1 pin even when not using the a/d converter. (10) adtrg pin this pin is a pin used to start the a/d converter by hardware.
261 chapter 13 8-bit a/d converter ( pd780024a, 780024ay subseries) user s manual u14046ej3v0ud 13.3 registers to control a/d converter the following 2 types of registers are used to control the a/d converter. a/d converter mode register 0 (adm0) analog input channel specification register 0 (ads0) (1) a/d converter mode register 0 (adm0) this register sets the conversion time for analog input to be a/d converted, conversion start/stop, and external trigger. adm0 is set by a 1-bit or 8-bit memory manipulation instruction. reset input clears adm0 to 00h.
262 chapter 13 8-bit a/d converter ( pd780024a, 780024ay subseries) user s manual u14046ej3v0ud figure 13-2. format of a/d converter mode register 0 (adm0) address: ff80h after reset: 00h r/w symbol <7> <6> 543210 adm0 adcs0 trg0 fr02 fr01 fr00 ega01 ega00 0 adcs0 a/d conversion operation control 0 stop conversion operation. 1 enable conversion operation. trg0 software start/hardware start selection 0 software start 1 hardware start fr02 fr01 fr00 conversion time selection note 1 f x = 8.38 mhz f x = 12 mhz note 2 0 0 0 144/f x 17.1 s 12.0 s 0 0 1 120/f x 14.3 s 10.0 s note 4 0 1 0 96/f x 11.4 s note 3 8.0 s note 4 1 0 0 72/f x 8.5 s note 3 6.0 s note 4 1 0 1 60/f x 7.1 s note 3 5.0 s note 4 1 1 0 48/f x 5.7 s note 3 4.0 s note 4 other than above setting prohibited ega01 ega00 external trigger signal, edge specification 0 0 no edge detection 0 1 falling edge detection 1 0 rising edge detection 1 1 both falling and rising edge detection notes 1. set the a/d conversion time as follows. when operated at f x = 12 mhz (v dd = 4.5 to 5.5 v): 12 s or more when operated at f x = 8.38 mhz (v dd = 4.0 to 5.5 v): 14 s or more 2. expanded-specification products of pd780024a subseries only. 3. setting is prohibited because the a/d conversion time is less than 14 s. 4. setting is prohibited because the a/d conversion time is less than 12 s. caution when rewriting fr00 to fr02 to other than the same data, stop a/d conversion operations once prior to performing rewrite. remark f x : main system clock oscillation frequency
263 chapter 13 8-bit a/d converter ( pd780024a, 780024ay subseries) user s manual u14046ej3v0ud (2) analog input channel specification register 0 (ads0) this register specifies the analog voltage input port for a/d conversion. ads0 is set by an 8-bit memory manipulation instruction. reset input clears ads0 to 00h. figure 13-3. format of analog input channel specification register 0 (ads0) address: ff81h after reset: 00h r/w symbol 76543210 ads0 00000 ads02 ads01 ads00 ads02 ads01 ads00 analog input channel specification 0 0 0 ani0 0 0 1 ani1 0 1 0 ani2 0 1 1 ani3 1 0 0 ani4 1 0 1 ani5 1 1 0 ani6 1 1 1 ani7
264 chapter 13 8-bit a/d converter ( pd780024a, 780024ay subseries) user s manual u14046ej3v0ud 13.4 a/d converter operations 13.4.1 basic operations of a/d converter <1> select one channel for a/d conversion with analog input channel specification register 0 (ads0). <2> the voltage input to the selected analog input channel is sampled by the sample & hold circuit. <3> when sampling has been done for a certain time, the sample & hold circuit is placed in the hold state and the input analog voltage is held until the a/d conversion operation is ended. <4> bit 7 of the successive approximation register (sar) is set. the series resistor string voltage tap is set to (1/2) av ref by the tap selector. <5> the voltage difference between the series resistor string voltage tap and analog input is compared by the voltage comparator. if the analog input is greater than (1/2) av ref , the msb of sar remains set. if the analog input is smaller than (1/2) av ref , the msb is reset. <6> next, bit 6 of sar is automatically set, and the operation proceeds to the next comparison. the series resistor string voltage tap is selected according to the preset value of bit 7, as described below. bit 7 = 1: (3/4) av ref bit 7 = 0: (1/4) av ref the voltage tap and analog input voltage are compared and bit 6 of sar is manipulated as follows. analog input voltage voltage tap: bit 6 = 1 analog input voltage < voltage tap: bit 6 = 0 <7> comparison is continued in this way up to bit 0 of sar. <8> upon completion of the comparison of 8 bits, an effective digital result value remains in sar, and the result value is transferred to and latched in a/d conversion result register 0 (adcr0). at the same time, the a/d conversion end interrupt request (intad0) can also be generated. cautions 1. the first a/d conversion value immediately after a/d conversion has been started may not satisfy the rated value. take measures such as polling the a/d conversion end interrupt request (intad0) and removing the first conversion results. 2. the a/d converter stops operation in standby mode.
265 chapter 13 8-bit a/d converter ( pd780024a, 780024ay subseries) user s manual u14046ej3v0ud figure 13-4. basic operation of 8-bit a/d converter sampling time setting adcs0 to 1, external trigger, or overwriting ads0 a/d conversion start delay time sampling a/d conversion undefined 80h c0h or 40h conversion result conversion result a/d converter operation sar adcr0 intad0 adcs0 conversion time a/d conversion operations are performed continuously until bit 7 (adcs0) of a/d converter mode register 0 (adm0) is reset (0) by software. reset input clears a/d conversion result register 0 (adcr0) to 00h. confirm the conversion results by referring to the a/d conversion end interrupt request flag (adif0). the sampling time of the a/d converter varies depending on the values set in a/d converter mode register 0 (adm0). there is a delay time from when the a/d converter is enabled for operation until sampling is actually performed. for the sets in which a strict a/d conversion time is required, note the contents described in table 13-2.
266 chapter 13 8-bit a/d converter ( pd780024a, 780024ay subseries) user s manual u14046ej3v0ud table 13-2. sampling time and a/d conversion start delay time of a/d converter fr02 fr01 fr00 conversion time note 1 sampling time a/d conversion start delay time min. max. 0 0 0 144/f x 20/f x 0.5/f cpu + 6/f x 0.5/f cpu + 8/f x 0 0 1 120/f x 16/f x 0 1 0 96/f x 12/f x 1 0 0 72/f x 10/f x 0.5/f cpu + 3/f x 0.5/f cpu + 4/f x 1 0 1 60/f x 8/f x 1 1 0 48/f x 6/f x other than above setting prohibited ??? notes 1. set the a/d conversion time as follows. when operated at f x = 12 mhz note 2 (v dd = 4.5 to 5.5 v): 12 s or more when operated at f x = 8.38 mhz (v dd = 4.0 to 5.5 v): 14 s or more 2. expanded-specification products of pd780024a subseries only. remark f x : main system clock oscillation frequency f cpu : cpu clock frequency
267 chapter 13 8-bit a/d converter ( pd780024a, 780024ay subseries) user s manual u14046ej3v0ud 13.4.2 input voltage and conversion results the relationship between the analog input voltage input to the analog input pins (ani0 to ani7) and the theoretical a/d conversion result (stored in a/d conversion result register 0 (adcr0)) is shown by the following expression. adcr0 = int ( v in 256 + 0.5) av ref or (adcr0 0.5) av ref v in < (adcr0 + 0.5) av ref 256 256 where, int( ): function which returns integer part of value in parentheses v in : analog input voltage av ref :av ref pin voltage adcr0: a/d conversion result register 0 (adcr0) value figure 13-5 shows the relationship between the analog input voltage and the a/d conversion result. figure 13-5. relationship between analog input voltage and a/d conversion result 255 254 253 3 2 1 0 a/d conversion result (adcr0) 1 512 1 256 3 512 2 256 5 512 3 256 507 512 254 256 509 512 255 256 511 512 1 input voltage/av ref
268 chapter 13 8-bit a/d converter ( pd780024a, 780024ay subseries) user s manual u14046ej3v0ud 13.4.3 a/d converter operation mode select one analog input channel from among ani0 to ani7 using analog input channel specification register 0 (ads0) to start a/d conversion. a/d conversion can be started in either of the following two ways. hardware start: conversion is started by trigger input (rising edge, falling edge, or both rising and falling edges enabled). software start: conversion is started by setting a/d converter mode register 0 (adm0). when a/d conversion is complete, the interrupt request signal (intad0) is generated. (1) a/d conversion by hardware start when bit 6 (trg0) and bit 7 (adcs0) of a/d converter mode register 0 (adm0) are set to 1, the a/d conversion standby state is set. when the external trigger signal (adtrg) is input, a/d conversion of the voltage applied to the analog input pin specified by analog input channel specification register 0 (ads0) starts. upon the end of a/d conversion, the conversion result is stored in a/d conversion result register 0 (adcr0), and the interrupt request signal (intad0) is generated. after one a/d conversion operation is started and finished, the next conversion operation is not started until a new external trigger signal is input. if ads0 is rewritten during a/d conversion, the converter suspends a/d conversion and waits for a new external trigger signal to be input. when the external trigger input signal is reinput, a/d conversion is carried out from the beginning. if ads0 is rewritten during a/d conversion standby, a/d conversion starts when the following external trigger input signal is input. if 1 is written to adcs0 again during a/d conversion, the a/d conversion in progress is discontinued and a new a/d conversion is started when the next external trigger input signal is input. if 0 is written to adcs0 during a/d conversion, the a/d conversion operation stops immediately. caution when p03/intp3/adtrg is used as the external trigger input (adtrg), specify the valid edge using bits 1, 2 (ega00, ega01) of a/d converter mode register 0 (adm0) and set the interrupt mask flag (pmk3) to 1.
269 chapter 13 8-bit a/d converter ( pd780024a, 780024ay subseries) user s manual u14046ej3v0ud figure 13-6. a/d conversion by hardware start (when falling edge is specified) remarks 1. n = 0, 1, ......, 7 2. m = 0, 1, ......, 7 a/d conversion adcr0 adtrg intad0 adm0 set adcs0 = 1, trg0 = 1 ads0 rewrite standby state anin anin standby state anin standby state anim anim anim anin anin undefined anin anim anim
270 chapter 13 8-bit a/d converter ( pd780024a, 780024ay subseries) user s manual u14046ej3v0ud (2) a/d conversion by software start when bit 6 (trg0) and bit 7 (adcs0) of a/d converter mode register 0 (adm0) are set to 0 and 1, respectively, a/d conversion of the voltage applied to the analog input pin specified by analog input channel specification register 0 (ads0) starts. upon the end of the a/d conversion, the conversion result is stored in a/d conversion result register 0 (adcr0), and the interrupt request signal (intad0) is generated. after one a/d conversion operation is started and ended, the next conversion operation is immediately started. a/d conversion operations are repeated until new data is written to ads0. if ads0 is rewritten during a/d conversion, the converter suspends a/d conversion and a/d conversion of the newly selected analog input channel is started. if 1 is written to adcs0 again during a/d conversion, the a/d conversion in progress is discontinued and a new a/d conversion is started. if 0 is written to adcs0 during a/d conversion, the a/d conversion operation stops immediately. figure 13-7. a/d conversion by software start remarks 1. n = 0, 1, ......, 7 2. m = 0, 1, ......, 7 adm0 set adcs0 = 1, trg0 = 0 ads0 rewrite adcs0 = 0 a/d conversion adcr0 intad0 anin anin anin anim anim stop anin undefined anin anim conversion suspended; conversion results are not stored
271 chapter 13 8-bit a/d converter ( pd780024a, 780024ay subseries) user s manual u14046ej3v0ud 13.5 how to read a/d converter characteristics table here we will explain the special terms unique to a/d converters. (1) resolution this is the minimum analog input voltage that can be identified. that is, the percentage of the analog input voltage per 1 bit of digital output is called 1lsb (least significant bit). the percentage of 1lsb with respect to the full scale is expressed by %fsr (full scale range). when the resolution is 8 bits, 1lsb = 1/2 8 = 1/256 = 0.4%fsr accuracy has no relation to resolution, but is determined by overall error. (2) overall error this shows the maximum error value between the actual measured value and the theoretical value. zero scale error, full scale error, integral linearity error, differential linearity error and errors which are combinations of these express overall error. furthermore, quantization error is not included in overall error in the characteristics table. (3) quantization error when analog values are converted to digital values, there naturally occurs a 1/2lsb error. in an a/d converter, an analog input voltage in a range of 1/2lsb are converted to the same digital code, so a quantization error cannot be avoided. furthermore, it is not included in the overall error, zero scale error, full scale error, integral linearity error, and differential linearity error in the characteristics table. figure 13-8. overall error figure 13-9. quantization error ideal line 0 0 1 1 digital output overall error analog input av ref 0 0 0 1 1 digital output quantization error 1/2lsb 1/2lsb analog input av ref 0
272 chapter 13 8-bit a/d converter ( pd780024a, 780024ay subseries) user s manual u14046ej3v0ud (4) zero scale error this shows the difference between the actual measured value of the analog input voltage and the theoretical value (1/2lsb) when the digital output changes from 0 000 to 0 001. if the actual measured value is greater than the theoretical value, it shows the difference between the actual measured value of the analog input voltage and the theoretical value (3/2lsb) when the digital output changes from 0 001 to 0 010. (5) full scale error this shows the difference between the actual measured value of the analog input voltage and the theoretical value (full scale 3/2lsb) when the digital output changes from 1 110 to 1 111. (6) integral linearity error this shows the degree to which the conversion characteristics deviate from the ideal linear relationship. it expresses the maximum value of the difference between the actual measured value and the ideal straight line when the zero scale error and full scale error are 0. (7) differential linearity error although the ideal output width for a given code is 1lsb, this value shows the difference between the actual measured value and the ideal value of the width when outputting a particular code. figure 13-10. zero scale error figure 13-11. full scale error figure 13-12. integral linearity error figure 13-13. differential linearity error 111 011 010 001 zero scale error ideal line 000 01 2 3 av ref digital output (lower 3 bits) analog input (lsb) 111 110 101 000 0 av ref av ref ? 1 av ref ? 2 av ref ? 3 digital output (lower 3 bits) analog input (lsb) ideal line full scale error 0 av ref digital output analog input integral linearity error ideal line 1 1 0 0 0 av ref digital output 1 ...... 1 0 ...... 0 ideal width of 1lsb differential linearity error analog input
273 chapter 13 8-bit a/d converter ( pd780024a, 780024ay subseries) user s manual u14046ej3v0ud (8) conversion time this expresses the time from when the sampling was started to the time when the digital output was obtained. sampling time is included in the conversion time in the characteristics table. (9) sampling time this is the time the analog switch is turned on for the analog voltage to be sampled by the sample & hold circuit. sampling time conversion time
274 chapter 13 8-bit a/d converter ( pd780024a, 780024ay subseries) user s manual u14046ej3v0ud 13.6 a/d converter cautions (1) power consumption in standby mode a/d converter stops operating in the standby mode. at this time, power consumption can be reduced by stopping the conversion operation (by clearing bit 7 (adcs0) of a/d converter mode register 0 (adm0) to 0). figure 13-14 shows the circuit configuration of a series resistor string. figure 13-14. circuit configuration of series resistor string av ref av ss p-ch series resistor string adcs0 (2) input range of ani0 to ani7 the input voltages of ani0 to ani7 should be within the specification range. in particular, if a voltage higher than av ref or lower than av ss is input (even if within the absolute maximum rating range), the conversion value of that channel will be undefined and the conversion values of other channels may also be affected. (3) contending operations <1> contention between a/d conversion result register 0 (adcr0) write and adcr0 read by instruction upon the end of conversion adcr0 read is given priority. after the read operation, the new conversion result is written to adcr0. <2> contention between adcr0 write and external trigger signal input upon the end of conversion the external trigger signal is not accepted during a/d conversion. therefore, the external trigger signal is not accepted during adcr0 write. <3> contention between adcr0 write and a/d converter mode register 0 (adm0) write or analog input channel specification register 0 (ads0) write upon the end of conversion adm0 or ads0 write is given priority. adcr0 write is not performed, nor is the conversion end interrupt request signal (intad0) generated. (4) ani0/p10 to ani7/p17 <1> the analog input pins (ani0 to ani7) also function as input port pins (p10 to p17). when a/d conversion is performed with any of pins ani0 to ani7 selected, do not access port 1 while conversion is in progress, as this may reduce the conversion resolution. <2> if digital pulses are applied to the pin adjacent to a pin in the process of a/d conversion, the expected a/d conversion value may not be obtainable due to coupling noise. therefore, avoid applying pulses to the pin adjacent to a pin undergoing a/d conversion.
275 chapter 13 8-bit a/d converter ( pd780024a, 780024ay subseries) user s manual u14046ej3v0ud (5) av ref pin input impedance a series resistor string is connected between the av ref pin and the av ss pin. therefore, when the output impedance of the reference voltage is too high, it seems as if the av ref pin and the series resistor string are connected in series. this may cause a greater reference voltage error. (6) interrupt request flag (adif0) the interrupt request flag (adif0) is not cleared even if analog input channel specification register 0 (ads0) is changed. therefore, if an analog input pin is changed during a/d conversion, the a/d conversion result and conversion end interrupt request flag for the pre-change analog input may be set just before the ads0 rewrite. caution is therefore required since, at this time, when adif0 is read immediately just after the ads0 rewrite, adif0 is set despite the fact that the a/d conversion for the post-change analog input has not finished. when a/d conversion is restarted after it is stopped, clear adif0 before restart. figure 13-15. a/d conversion end interrupt request generation timing remarks 1. n = 0, 1, ......, 7 2. m = 0, 1, ......, 7 (7) conversion results just after a/d conversion start the a/d conversion value immediately after a/d conversion has been started may not satisfy the rated value. take measures such as polling the a/d conversion end interrupt request (intad0) and removing the first conversion results. (8) a/d conversion result register 0 (adcr0) read operation when a/d converter mode register 0 (adm0) and analog input channel specification register 0 (ads0) are written, the contents of adcr0 may become undefined. read the conversion result following conversion completion before writing to adm0 and ads0. using a timing other than the above may cause an incorrect conversion result to be read. adm0 rewrite (start of anin conversion) ads0 rewrite (start of anim conversion) adif is set but anim conversion has not finished. a/d conversion adcr0 intad0 anin anin anim anim anin undefined anim anim
276 chapter 13 8-bit a/d converter ( pd780024a, 780024ay subseries) user s manual u14046ej3v0ud normal conversion result undefined value a/d conversion completes a/d conversion completes normal conversion result is read. a/d conversion is stopped. undefined value is read. adcr0 intad0 adcs0 (9) timing at which a/d conversion result is undefined the a/d conversion value may be undefined if the timing of completion of a/d conversion and the timing of stopping the a/d conversion conflict with each other. therefore, read the a/d conversion result before stopping the a/d conversion operation. figure 13-16 shows the timing of reading the conversion result. figure 13-16. timing of reading conversion result (when conversion result is undefined) (10) notes on board design locate analog circuits as far away from digital circuits as possible on the board because the analog circuits may be affected by the noise of the digital circuits. in particular, do not cross an analog signal line with a digital signal line, or wire an analog signal line in the vicinity of a digital signal line. otherwise, the a/d conversion characteristics may be affected by the noise of the digital line. connect av ss0 and v ss0 at one location on the board where the voltages are stable. (11) av dd pin the av dd pin is the analog circuit power supply pin. it supplies power to the input circuits of the ani0 to ani7 pins. therefore, be sure to apply the same potential as v dd0 to this pin even for applications designed to switch to a backup battery for power supply. figure 13-17. av dd pin connection main power supply capacitor for backup av ref v dd0 av ss av dd v ss0
277 chapter 13 8-bit a/d converter ( pd780024a, 780024ay subseries) user s manual u14046ej3v0ud (12) av ref pin connect a capacitor to the av ref pin to minimize conversion errors due to noise. if an a/d conversion operation has been stopped and then is started, the voltage applied to the av ref pin becomes unstable, causing the accuracy of the a/d conversion to drop. to prevent this, also connect a capacitor to the av ref pin. figure 13-18 shows an example of connecting a capacitor. figure 13-18. example of connecting capacitor to av ref pin remark c1: 4.7 f to 10 f (reference value) c2: 0.01 f to 0.1 f (reference value) connect c2 as close to the pin as possible. (13) internal equivalent circuit of ani0 to ani7 pins and permissible signal source impedance to complete sampling within the sampling time with sufficient a/d conversion accuracy, the impedance of the signal source such as a sensor must be sufficiently low. figure 13-19 shows the internal equivalent circuit of the ani0 to ani7 pins. if the impedance of the signal source is high, connect capacitors with a high capacitance to the pins ani0 to ani7. an example of this is shown in figure 13-20. in this case, however, the microcontroller cannot follow an analog signal with a high differential coefficient because a lowpass filter is created. to convert a high-speed analog signal or to convert an analog signal in the scan mode, insert a low-impedance buffer. figure 13-19. internal equivalent circuit of pins ani0 to ani7 remark n = 0 to 7 av ref av dd clamp using a diode with a low v f (0.3 v or lower). av ss c 2 c 1 c3 c2 r2 r1 c1 anin
278 chapter 13 8-bit a/d converter ( pd780024a, 780024ay subseries) user s manual u14046ej3v0ud table 13-3. resistances and capacitances of equivalent circuit (reference values) (typ.) av ref r1 r2 c1 c2 c3 2.7 v 12 k ? 8.0 k ? 3.0 pf 3.0 pf 2.0 pf 4.5 v 4 k ? 2.7 k ? 3.0 pf 1.4 pf 2.0 pf caution the resistances and capacitances in table 13-3 are not guaranteed values. figure 13-20. example of connection if signal source impedance is high remark n = 0 to 7 (14) input impedance of ani0 to ani7 pins this a/d converter executes sampling by charging the internal sampling capacitor for approximately 1/10 of the conversion time. therefore, only the leakage current flows during other than sampling, and the current for charging the capacitor flows during sampling. the input impedance therefore varies and has no meaning. to achieve sufficient sampling, it is recommended that the output impedance of the analog input source be 10 k ? or less, or attach a capacitor of around 100 pf to the ani0 to ani7 pins (see figure 13-20 ). c3 c2 r2 r1 if a noise of av ref or higher or av ss or lower may be generated, clamp using a diode with a low v f (0.3 v or lower). r0 anin av ref c1 c0 lowpass filter is created. output impedance of sensor c0 0.1 f reference voltage input
279 user? manual u14046ej3v0ud chapter 14 10-bit a/d converter ( pd780034a, 780034ay subseries) 14.1 a/d converter functions a/d converter is a 10-bit resolution converter that converts analog inputs into digital signals. it can control up to 8 analog input channels (ani0 to ani7). (1) hardware start conversion is started by trigger input (adtrg: rising edge, falling edge, or both rising and falling edges can be specified). (2) software start conversion is started by setting a/d converter mode register 0 (adm0). select one channel for analog input from ani0 to ani7 to start a/d conversion. in the case of hardware start, the a/d converter stops when a/d conversion is completed, and an interrupt request (intad0) is generated. in the case of software start, a/d conversion is repeated. each time as a/d conversion operation ends, an interrupt request (intad0) is generated. caution although the pd78f0034a, 78f0034b, 78f0034ay, and 78f0034by incorporate a 10-bit a/d converter, this converter can be operated as an 8-bit a/d converter by using the device file df780024.
280 chapter 14 10-bit a/d converter ( pd780034a, 780034ay subseries) user? manual u14046ej3v0ud figure 14-1. 10-bit a/d converter block diagram note the valid edge of external interrupt is specified by bit 3 of the egp and egn registers (see figure 19-5 format of external interrupt rising edge enable register (egp), external interrupt falling edge enable register (egn) ). ani0/p10 ani1/p11 ani2/p12 ani3/p13 ani4/p14 ani5/p15 ani6/p16 ani7/p17 sample & hold circuit series resistor string voltage comparator controller edge detector adtrg/intp3/p03 3 a/d conversion result register 0 (adcr0) av dd av ref av ss intad0 intp3 trigger enable a/d converter mode register 0 (adm0) analog input channel specification register 0 (ads0) internal bus ads02 ads01 ads00 adcs0 trg0 fr02 fr01 fr00 ega01 ega00 selector tap selector edge detector note successive approximation register (sar)
281 chapter 14 10-bit a/d converter ( pd780034a, 780034ay subseries) user s manual u14046ej3v0ud 14.2 a/d converter configuration the a/d converter consists of the following hardware. table 14-1. a/d converter configuration item configuration analog input 8 channels (ani0 to ani7) hardware trigger 1 (adtrg) input registers successive approximation register (sar) a/d conversion result register 0 (adcr0) control registers a/d converter mode register 0 (adm0) analog input channel specification register 0 (ads0) (1) successive approximation register (sar) this register compares the analog input voltage value to the voltage tap (compare voltage) value applied from the series resistor string, and holds the result from the most significant bit (msb). when up to the least significant bit (lsb) is held (end of a/d conversion), the sar contents are transferred to a/d conversion result register 0 (adcr0). (2) a/d conversion result register 0 (adcr0) this is a 16-bit register that stores the a/d conversion results. the lower 6 bits are fixed to 0. each time a/ d conversion ends, the conversion result is loaded from the successive approximation register (sar) and held by this register. the most significant bit (msb) is stored in adcr0 first. the higher 8 bits of the conversion results are stored in ff17h. the lower 2 bits of the conversion results are stored in ff16h. adcr0 is read by a 16-bit memory manipulation instruction. reset input clears adcr0 to 0000h. figure 14-2. format of a/d conversion result register 0 (adcr0) caution when a/d converter mode register 0 (adm0) and analog input channel specification register 0 (ads0) are written, the contents of adcr0 may become undefined. read the conversion result following conversion completion before writing to adm0 and ads0. using a timing other than the above may cause an incorrect conversion result to be read. (3) sample & hold circuit the sample & hold circuit samples the input signal of the analog input pin selected by the selector when a/d conversion is started and holds the sampled analog input voltage value during a/d conversion. 0 0 0 0 0 0 adcr0 symbol ff17h ff16h address: ff16h, ff17h after reset: 0000h r
282 chapter 14 10-bit a/d converter ( pd780034a, 780034ay subseries) user s manual u14046ej3v0ud (4) voltage comparator the voltage comparator compares the sampled analog input voltage to the series resistor string output voltage. (5) series resistor string the series resistor string is connected between av ref and av ss , and generates the voltage to be compared to the analog input. (6) ani0 to ani7 pins these are eight analog input pins used to input analog signals to undergo a/d conversion to the a/d converter. ani0 to ani7 are alternate-function pins that can also be used for digital input. cautions 1. use ani0 to ani7 input voltages within the specification range. if a voltage higher than or equal to av ref or lower than or equal to av ss is applied (even if within the absolute maximum rating range), the conversion value of that or equal to channel will be undefined and the conversion values of other channels may also be affected. 2. analog input (ani0 to ani7) pins are alternate-function pins that can also be used as input port pins (p10 to p17). when a/d conversion is performed by selecting any one of ani0 through ani7, do not access port 1 during conversion, as this may cause a lower conversion resolution. 3. when a digital pulse is applied to a pin adjacent to the pin in the process of a/d conversion, a/d conversion values may not be obtained as expected due to coupling noise. thus, do not apply a pulse to a pin adjacent to the pin in the process of a/d conversion. (7) av ref pin this is the a/d converter reference voltage pin and also the analog power supply pin. it converts signals input to ani0 to ani7 into digital signals according to the voltage applied between av ref and av ss . caution a series resistor string is connected between the av ref and av ss pins. therefore, when the output impedance of the reference voltage is too high, it seems as if the av ref pin and the series resistor string are connected in series. this may cause a greater reference voltage error. (8) av ss pin this is the ground potential pin of the a/d converter. always keep it at the same potential as the v ss0 or v ss1 pin even when not using the a/d converter. (9) av dd pin this is the a/d converter analog power supply pin. always keep it at the same potential as the v dd0 or v dd1 pin even when not using the a/d converter. (10) adtrg pin this pin is a pin used to start the a/d converter by hardware.
283 chapter 14 10-bit a/d converter ( pd780034a, 780034ay subseries) user s manual u14046ej3v0ud 14.3 registers to control a/d converter the following 2 types of registers are used to control the a/d converter. a/d converter mode register 0 (adm0) analog input channel specification register 0 (ads0) (1) a/d converter mode register 0 (adm0) this register sets the conversion time for analog input to be a/d converted, conversion start/stop, and external trigger. adm0 is set by a 1-bit or 8-bit memory manipulation instruction. reset input clears adm0 to 00h.
284 chapter 14 10-bit a/d converter ( pd780034a, 780034ay subseries) user s manual u14046ej3v0ud figure 14-3. format of a/d converter mode register 0 (adm0) address: ff80h after reset: 00h r/w symbol <7> <6> 543210 adm0 adcs0 trg0 fr02 fr01 fr00 ega01 ega00 0 adcs0 a/d conversion operation control 0 stop conversion operation. 1 enable conversion operation. trg0 software start/hardware start selection 0 software start 1 hardware start fr02 fr01 fr00 conversion time selection note 1 f x = 8.38 mhz f x = 12 mhz note 2 0 0 0 144/f x 17.1 s 12.0 s 0 0 1 120/f x 14.3 s 10.0 s note 4 0 1 0 96/f x 11.4 s note 3 8.0 s note 4 1 0 0 72/f x 8.5 s note 3 6.0 s note 4 1 0 1 60/f x 7.1 s note 3 5.0 s note 4 1 1 0 48/f x 5.7 s note 3 4.0 s note 4 other than above setting prohibited ega01 ega00 external trigger signal, edge specification 0 0 no edge detection 0 1 falling edge detection 1 0 rising edge detection 1 1 both falling and rising edge detection notes 1. set the a/d conversion time as follows. when operated at f x = 12 mhz (v dd = 4.5 to 5.5 v): 12 s or more when operated at f x = 8.38 mhz (v dd = 4.0 to 5.5 v): 14 s or more 2. expanded-specification products of pd780034a subseries only. 3. setting is prohibited because the a/d conversion time is less than 14 s. 4. setting is prohibited because the a/d conversion time is less than 12 s. caution when rewriting fr00 to fr02 to other than the same data, stop a/d conversion operations once prior to performing rewrite. remark f x : main system clock oscillation frequency
285 chapter 14 10-bit a/d converter ( pd780034a, 780034ay subseries) user s manual u14046ej3v0ud (2) analog input channel specification register 0 (ads0) this register specifies the analog voltage input port for a/d conversion. ads0 is set by an 8-bit memory manipulation instruction. reset input clears ads0 to 00h. figure 14-4. format of analog input channel specification register 0 (ads0) address: ff81h after reset: 00h r/w symbol 76543210 ads0 00000 ads02 ads01 ads00 ads02 ads01 ads00 analog input channel specification 0 0 0 ani0 0 0 1 ani1 0 1 0 ani2 0 1 1 ani3 1 0 0 ani4 1 0 1 ani5 1 1 0 ani6 1 1 1 ani7
286 chapter 14 10-bit a/d converter ( pd780034a, 780034ay subseries) user s manual u14046ej3v0ud 14.4 a/d converter operation 14.4.1 basic operations of a/d converter <1> select one channel for a/d conversion with analog input channel specification register 0 (ads0). <2> the voltage input to the selected analog input channel is sampled by the sample & hold circuit. <3> when sampling has been done for a certain time, the sample & hold circuit is placed in the hold state and the input analog voltage is held until the a/d conversion operation is ended. <4> bit 9 of the successive approximation register (sar) is set. the series resistor string voltage tap is set to (1/2) av ref by the tap selector. <5> the voltage difference between the series resistor string voltage tap and analog input is compared by the voltage comparator. if the analog input is greater than (1/2) av ref , the msb of sar remains set. if the analog input is smaller than (1/2) av ref , the msb is reset. <6> next, bit 8 of sar is automatically set, and the operation proceeds to the next comparison. the series resistor string voltage tap is selected according to the preset value of bit 9, as described below. bit 9 = 1: (3/4) av ref bit 9 = 0: (1/4) av ref the voltage tap and analog input voltage are compared and bit 8 of sar is manipulated as follows. analog input voltage voltage tap: bit 8 = 1 analog input voltage < voltage tap: bit 8 = 0 <7> comparison is continued in this way up to bit 0 of sar. <8> upon completion of the comparison of 10 bits, an effective digital result value remains in sar, and the result value is transferred to and latched in a/d conversion result register 0 (adcr0). at the same time, the a/d conversion end interrupt request (intad0) can also be generated. cautions 1. the first a/d conversion value immediately after a/d conversion has been started may not satisfy the rated value. take measures such as polling the a/d conversion end interrupt request (intad0) and removing the first conversion results. 2. the a/d converter stops operation in standby mode.
287 chapter 14 10-bit a/d converter ( pd780034a, 780034ay subseries) user s manual u14046ej3v0ud figure 14-5. basic operation of 10-bit a/d converter a/d conversion operations are performed continuously until bit 7 (adcs0) of a/d converter mode register 0 (adm0) is reset (0) by software. reset input clears a/d conversion result register 0 (adcr0) to 00h. confirm the conversion results by referring to the a/d conversion end interrupt request flag (adif0). the sampling time of the a/d converter varies depending on the values set in a/d converter mode register 0 (adm0). there is a delay time from when the a/d converter is enabled for operation until sampling is actually performed. for the sets in which a strict a/d conversion time is required, note the contents described in table 14-2. conversion time setting adcs0 to 1, external trigger, or overwriting ads0 a/d conversion start delay time sampling a/d conversion undefined conversion result conversion result a/d converter operation sar adcr0 intad0 adcs0 sampling time 200h 300h or 100h
288 chapter 14 10-bit a/d converter ( pd780034a, 780034ay subseries) user s manual u14046ej3v0ud table 14-2. sampling time and a/d conversion start delay time of a/d converter fr02 fr01 fr00 conversion time note 1 sampling time a/d conversion start delay time min. max. 0 0 0 144/f x 20/f x 0.5/f cpu + 6/f x 0.5/f cpu + 8/f x 0 0 1 120/f x 16/f x 0 1 0 96/f x 12/f x 1 0 0 72/f x 10/f x 0.5/f cpu + 3/f x 0.5/f cpu + 4/f x 1 0 1 60/f x 8/f x 1 1 0 48/f x 6/f x other than above setting prohibited ??? notes 1. set the a/d conversion time as follows. when operated at f x = 12 mhz note 2 (v dd = 4.5 to 5.5 v): 12 s or more when operated at f x = 8.38 mhz (v dd = 4.0 to 5.5 v): 14 s or more 2. expanded-specification products of pd780034a subseries only. remark f x : main system clock oscillation frequency f cpu : cpu clock frequency
289 chapter 14 10-bit a/d converter ( pd780034a, 780034ay subseries) user s manual u14046ej3v0ud 14.4.2 input voltage and conversion results the relationship between the analog input voltage input to the analog input pins (ani0 to ani7) and the theoretical a/d conversion result (stored in a/d conversion result register 0 (adcr0)) is shown by the following expression. adcr0 = int ( v in 1024 + 0.5) av ref or (adcr0 0.5) av ref v in < (adcr0 + 0.5) av ref 1024 1024 where, int( ): function which returns integer part of value in parentheses v in : analog input voltage av ref :av ref pin voltage adcr0: a/d conversion result register 0 (adcr0) value figure 14-6 shows the relationship between the analog input voltage and the a/d conversion result. figure 14-6. relationship between analog input voltage and a/d conversion result 1023 2 6 1022 2 6 1021 2 6 3 2 6 2 2 6 1 2 6 0 a/d conversion result (adcr0) 1 2048 1 1024 3 2048 2 1024 5 2048 3 1024 2043 2048 1022 1024 2045 2048 1023 1024 2047 2048 1 input voltage/av ref
290 chapter 14 10-bit a/d converter ( pd780034a, 780034ay subseries) user s manual u14046ej3v0ud 14.4.3 a/d converter operation mode select one analog input channel from among ani0 to ani7 using analog input channel specification register 0 (ads0) to start a/d conversion. a/d conversion can be started in either of the following two ways. hardware start: conversion is started by trigger input (rising edge, falling edge, or both rising and falling edges enabled). software start: conversion is started by setting a/d converter mode register 0 (adm0). when a/d conversion is complete, the interrupt request signal (intad0) is generated. (1) a/d conversion by hardware start when bit 6 (trg0) and bit 7 (adcs0) of a/d converter mode register 0 (adm0) are set to 1, the a/d conversion standby state is set. when the external trigger signal (adtrg) is input, a/d conversion of the voltage applied to the analog input pin specified by analog input channel specification register 0 (ads0) starts. upon the end of a/d conversion, the conversion result is stored in a/d conversion result register 0 (adcr0), and the interrupt request signal (intad0) is generated. after one a/d conversion operation is started and finished, the next conversion operation is not started until a new external trigger signal is input. if ads0 is rewritten during a/d conversion, the converter suspends a/d conversion and waits for a new external trigger signal to be input. when the external trigger input signal is reinput, a/d conversion is carried out from the beginning. if ads0 is rewritten during a/d conversion standby, a/d conversion starts when the following external trigger input signal is input. if 1 is written to adcs0 again during a/d conversion, the a/d conversion in progress is discontinued and a new a/d conversion is started when the next external trigger input signal is input. if 0 is written to adcs0 during a/d conversion, the a/d conversion operation stops immediately. caution when p03/intp3/adtrg is used as the external trigger input (adtrg), specify the valid edge using bits 1, 2 (ega00, ega01) of a/d converter mode register 0 (adm0) and set the interrupt mask flag (pmk3) to 1. figure 14-7. a/d conversion by hardware start (when falling edge is specified) remarks 1. n = 0, 1, ......, 7 2. m = 0, 1, ......, 7 a/d conversion adcr0 adtrg intad0 adm0 set adcs0 = 1, trg0 = 1 ads0 rewrite standby state anin anin standby state anin standby state anim anim anim anin anin undefined anin anim anim
291 chapter 14 10-bit a/d converter ( pd780034a, 780034ay subseries) user s manual u14046ej3v0ud (2) a/d conversion by software start when bit 6 (trg0) and bit 7 (adcs0) of a/d converter mode register 0 (adm0) are set to 0 and 1, respectively, a/d conversion of the voltage applied to the analog input pin specified by analog input channel specification register 0 (ads0) starts. upon the end of the a/d conversion, the conversion result is stored in a/d conversion result register 0 (adcr0), and the interrupt request signal (intad0) is generated. after one a/d conversion operation is started and ended, the next conversion operation is immediately started. a/d conversion operations are repeated until new data is written to ads0. if ads0 is rewritten during a/d conversion, the converter suspends a/d conversion and a/d conversion of the new selected analog input channel is started. if 1 is written to adcs0 again during a/d conversion, the a/d conversion in progress is discontinued and a new a/d conversion is started. if 0 is written to adcs0 during a/d conversion, the a/d conversion operation stops immediately. figure 14-8. a/d conversion by software start remarks 1. n = 0, 1, ......, 7 2. m = 0, 1, ......, 7 adm0 set adcs0 = 1, trg0 = 0 ads0 rewrite adcs0 = 0 a/d conversion adcr0 intad0 anin anin anin anim anim stop anin undefined anin anim conversion suspended; conversion results are not stored
292 chapter 14 10-bit a/d converter ( pd780034a, 780034ay subseries) user s manual u14046ej3v0ud 14.5 how to read a/d converter characteristics table here we will explain the special terms unique to a/d converters. (1) resolution this is the minimum analog input voltage that can be identified. that is, the percentage of the analog input voltage per 1 bit of digital output is called 1lsb (least significant bit). the percentage of 1lsb with respect to the full scale is expressed by %fsr (full scale range). when the resolution is 10 bits, 1lsb = 1/2 10 = 1/1024 = 0.098%fsr accuracy has no relation to resolution, but is determined by overall error. (2) overall error this shows the maximum error value between the actual measured value and the theoretical value. zero scale error, full scale error, integral linearity error, differential linearity error and errors which are combinations of these express overall error. furthermore, quantization error is not included in overall error in the characteristics table. (3) quantization error when analog values are converted to digital values, there naturally occurs a 1/2lsb error. in an a/d converter, an analog input voltage in a range of 1/2lsb are converted to the same digital code, so a quantization error cannot be avoided. furthermore, it is not included in the overall error, zero scale error, full scale error, integral linearity error, and differential linearity error in the characteristics table. figure 14-9. overall error figure 14-10. quantization error ideal line 0 0 1 1 digital output overall error analog input av ref 0 0 0 1 1 digital output quantization error 1/2lsb 1/2lsb analog input av ref 0
293 chapter 14 10-bit a/d converter ( pd780034a, 780034ay subseries) user s manual u14046ej3v0ud (4) zero scale error this shows the difference between the actual measured value of the analog input voltage and the theoretical value (1/2lsb) when the digital output changes from 0 000 to 0 001. if the actual measured value is greater than the theoretical value, it shows the difference between the actual measured value of the analog input voltage and the theoretical value (3/2lsb) when the digital output changes from 0 001 to 0 010. (5) full scale error this shows the difference between the actual measured value of the analog input voltage and the theoretical value (full scale 3/2lsb) when the digital output changes from 1 110 to 1 111. (6) integral linearity error this shows the degree to which the conversion characteristics deviate from the ideal linear relationship. it expresses the maximum value of the difference between the actual measured value and the ideal straight line when the zero scale error and full scale error are 0. (7) differential linearity error although the ideal output width for a given code is 1lsb, this value shows the difference between the actual measured value and the ideal value of the width when outputting a particular code. figure 14-11. zero scale error figure 14-12. full scale error figure 14-13. integral linearity error figure 14-14. differential linearity error 111 011 010 001 zero scale error ideal line 000 01 2 3 av ref digital output (lower 3 bits) analog input (lsb) 111 110 101 000 0 av ref av ref ? 1 av ref ? 2 av ref ? 3 digital output (lower 3 bits) analog input (lsb) ideal line full scale error 0 av ref digital output analog input integral linearity error ideal line 1 1 0 0 0 av ref digital output 1 ...... 1 0 ...... 0 ideal width of 1lsb differential linearity error analog input
294 chapter 14 10-bit a/d converter ( pd780034a, 780034ay subseries) user s manual u14046ej3v0ud (8) conversion time this expresses the time from when the sampling was started to the time when the digital output was obtained. sampling time is included in the conversion time in the characteristics table. (9) sampling time this is the time the analog switch is turned on for the analog voltage to be sampled by the sample & hold circuit. sampling time conversion time
295 chapter 14 10-bit a/d converter ( pd780034a, 780034ay subseries) user s manual u14046ej3v0ud 14.6 a/d converter cautions (1) power consumption in standby mode a/d converter stops operating in the standby mode. at this time, power consumption can be reduced by stopping the conversion operation (by clearing bit 7 (adcs0) of a/d converter mode register 0 (adm0) to 0). figure 14-15 shows the circuit configuration of a series resistor string. figure 14-15. circuit configuration of series resistor string av ref av ss p-ch series resistor string adcs0 (2) input range of ani0 to ani7 the input voltages of ani0 to ani7 should be within the specification range. in particular, if a voltage higher than av ref or lower than av ss is input (even if within the absolute maximum rating range), the conversion value of that channel will be undefined and the conversion values of other channels may also be affected. (3) contending operations <1> contention between a/d conversion result register 0 (adcr0) write and adcr0 read by instruction upon the end of conversion adcr0 read is given priority. after the read operation, the new conversion result is written to adcr0. <2> contention between adcr0 write and external trigger signal input upon the end of conversion the external trigger signal is not accepted during a/d conversion. therefore, the external trigger signal is not accepted during adcr0 write. <3> contention between adcr0 write and a/d converter mode register 0 (adm0) write or analog input channel specification register 0 (ads0) write upon the end of conversion adm0 or ads0 write is given priority. adcr0 write is not performed, nor is the conversion end interrupt request signal (intad0) generated. (4) ani0/p10 to ani7/p17 <1> the analog input pins (ani0 to ani7) also function as input port pins (p10 to p17). when a/d conversion is performed with any of pins ani0 to ani7 selected, do not access port 1 while conversion is in progress, as this may reduce the conversion resolution. <2> if digital pulses are applied to the pin adjacent to a pin in the process of a/d conversion, the expected a/d conversion value may not be obtainable due to coupling noise. therefore, avoid applying pulses to the pin adjacent to a pin undergoing a/d conversion.
296 chapter 14 10-bit a/d converter ( pd780034a, 780034ay subseries) user s manual u14046ej3v0ud (5) av ref pin input impedance a series resistor string is connected between the av ref pin and the av ss pin. therefore, when the output impedance of the reference voltage is too high, it seems as if the av ref pin and the series resistor string are connected in series. this may cause a greater reference voltage error. (6) interrupt request flag (adif0) the interrupt request flag (adif0) is not cleared even if analog input channel specification register 0 (ads0) is changed. therefore, if an analog input pin is changed during a/d conversion, the a/d conversion result and conversion end interrupt request flag for the pre-change analog input may be set just before the ads0 rewrite. caution is therefore required since, at this time, when adif0 is read immediately just after the ads0 rewrite, adif0 is set despite the fact that the a/d conversion for the post-change analog input has not finished. when a/d conversion is restarted after it is stopped, clear adif0 before restart. figure 14-16. a/d conversion end interrupt request generation timing remarks 1. n = 0, 1, ......, 7 2. m = 0, 1, ......, 7 (7) conversion results just after a/d conversion start the a/d conversion value immediately after a/d conversion has been started may not satisfy the rated value. take measures such as polling the a/d conversion end interrupt request (intad0) and removing the first conversion results. (8) a/d conversion result register 0 (adcr0) read operation when a/d converter mode register 0 (adm0) and analog input channel specification register 0 (ads0) are written, the contents of adcr0 may become undefined. read the conversion result following conversion completion before writing to adm0 and ads0. using a timing other than the above may cause an incorrect conversion result to be read. adm0 rewrite (start of anin conversion) ads0 rewrite (start of anim conversion) adif is set but anim conversion has not finished. a/d conversion adcr0 intad0 anin anin anim anim anin undefined anim anim
297 chapter 14 10-bit a/d converter ( pd780034a, 780034ay subseries) user s manual u14046ej3v0ud (9) timing at which a/d conversion result is undefined the a/d conversion value may be undefined if the timing of completion of a/d conversion and the timing of stopping the a/d conversion conflict with each other. therefore, read the a/d conversion result before stopping the a/d conversion operation. figure 14-17 shows the timing of reading the conversion result. figure 14-17. timing of reading conversion result (when conversion result is undefined) (10) notes on board design locate analog circuits as far away from digital circuits as possible on the board because the analog circuits may be affected by the noise of the digital circuits. in particular, do not cross an analog signal line with a digital signal line, or wire an analog signal line in the vicinity of a digital signal line. otherwise, the a/d conversion characteristics may be affected by the noise of the digital line. connect av ss0 and v ss0 at one location on the board where the voltages are stable. (11) av dd pin the av dd pin is the analog circuit power supply pin. it supplies power to the input circuits of the ani0 to ani7 pins. therefore, be sure to apply the same potential as v dd0 to this pin even for applications designed to switch to a backup battery for power supply. figure 14-18. av dd pin connection main power supply capacitor for backup av ref v dd0 av ss av dd v ss0 normal conversion result undefined value a/d conversion completes a/d conversion completes normal conversion result is read. a/d conversion is stopped. undefined value is read. adcr0 intad0 adcs0
298 chapter 14 10-bit a/d converter ( pd780034a, 780034ay subseries) user s manual u14046ej3v0ud (12) av ref pin connect a capacitor to the av ref pin to minimize conversion errors due to noise. if an a/d conversion operation has been stopped and then is started, the voltage applied to the av ref pin becomes unstable, causing the accuracy of the a/d conversion to drop. to prevent this, also connect a capacitor to the av ref pin. figure 14-19 shows an example of connecting a capacitor. figure 14-19. example of connecting capacitor to av ref pin remark c1: 4.7 f to 10 f (reference value) c2: 0.01 f to 0.1 f (reference value) connect c2 as close to the pin as possible. (13) internal equivalent circuit of ani0 to ani7 pins and permissible signal source impedance to complete sampling within the sampling time with sufficient a/d conversion accuracy, the impedance of the signal source such as a sensor must be sufficiently low. figure 14-20 shows the internal equivalent circuit of the ani0 to ani7 pins. if the impedance of the signal source is high, connect capacitors with a high capacitance to the pins ani0 to ani7. an example of this is shown in figure 14-21. in this case, however, the microcontroller cannot follow an analog signal with a high differential coefficient because a lowpass filter is created. to convert a high-speed analog signal or to convert an analog signal in the scan mode, insert a low-impedance buffer. figure 14-20. internal equivalent circuit of pins ani0 to ani7 av ref av dd clamp using a diode with a low v f (0.3 v or lower). av ss c 2 c 1 remark n = 0 to 7 c3 c2 r2 r1 c1 anin
299 chapter 14 10-bit a/d converter ( pd780034a, 780034ay subseries) user s manual u14046ej3v0ud table 14-3. resistances and capacitances of equivalent circuit (reference values) (typ.) av ref r1 r2 c1 c2 c3 2.7 v 12 k ? 8.0 k ? 3.0 pf 3.0 pf 2.0 pf 4.5 v 4 k ? 2.7 k ? 3.0 pf 1.4 pf 2.0 pf caution the resistances and capacitances in table 14-3 are not guaranteed values. figure 14-21. example of connection if signal source impedance is high remark n = 0 to 7 (14) input impedance of ani0 to ani7 pins this a/d converter executes sampling by charging the internal sampling capacitor for approximately 1/10 of the conversion time. therefore, only the leakage current flows during other than sampling, and the current for charging the capacitor flows during sampling. the input impedance therefore varies and has no meaning. to achieve sufficient sampling, it is recommended that the output impedance of the analog input source be 10 k ? or less, or attach a capacitor of around 100 pf to the ani0 to ani7 pins (see figure 14-21 ). c3 c2 r2 r1 if a noise of av ref or higher or av ss or lower may be generated, clamp using a diode with a low v f (0.3 v or lower). r0 anin av ref c1 c0 lowpass filter is created. output impedance of sensor c0 0.1 f reference voltage input
300 user? manual u14046ej3v0ud chapter 15 serial interface outline the pd780024a, 780034a subseries and the pd780024ay, 780034ay subseries have differences in their serial interfaces. these differences are listed in table 15-1. table 15-1. differences between pd780024a, 780034a subseries and pd780024ay, 780034ay subseries item pd780024a, 780034a pd780024ay, 780034ay relevant section uart0 ? chapter 16 sio3 sio30 ? chapter 17 sio31 ? iic0 ? chapter 18
301 user? manual u14046ej3v0ud chapter 16 serial interface uart0 16.1 functions of serial interface uart0 serial interface uart0 has the following three modes. (1) operation stop mode this mode is used when serial transfers are not performed to reduce power consumption. for details, see 16.4.1 operation stop mode . (2) asynchronous serial interface (uart) mode (fixed to lsb first) this mode enables full-duplex operation wherein one byte of data after the start bit is transmitted and received. the on-chip baud rate generator dedicated to uart enables communications using a wide range of selectable baud rates. the communication range is between 1.2 kbps and 131 kbps (when operated at f x = 8.38 mhz). in addition, a baud rate (39 kbps max. (when operated at f x = 1.25 mhz)) can also be defined by dividing the clock input to the asck0 pin. the uart baud rate generator can also be used to generate a midi-standard baud rate (31.25 kbps). for details, see 16.4.2 asynchronous serial interface (uart) mode . (3) infrared data transfer mode for details, see 16.4.3 infrared data transfer mode . figure 16-1 shows a block diagram of serial interface uart0.
302 chapter 16 serial interface uart0 user? manual u14046ej3v0ud figure 16-1. block diagram of serial interface uart0 note for the configuration of the baud rate generator, see figure 16-2 . figure 16-2. block diagram of baud rate generator remark txe0: bit 7 of asynchronous serial interface mode register 0 (asim0) rxe0: bit 6 of asynchronous serial interface mode register 0 (asim0) tps0 1 tps02 5-bit counter start bit sampling clock tps00 asck0/p25 f x /2 to f x /2 7 selector internal bus 34 mdl0 3 baud rate generator control register 0 (brgc0) mdl0 2 mdl0 1 mdl00 encoder transmit clock txe0 5-bit counter receive clock rxe0 start bit detection 1/2 match match 1/2 internal bus receive buffer register 0 (rxb0) rxd0/p23 txd0/p24 pm24 output latch (p24) pe0 fe0 ove0 asynchronous serial interface status register 0 ( asis0) intser0 intst0 baud rate generator note asck0/p25 f x /2 to f x /2 7 txe0 rxe0 ps01 ps00 cl0 sl0 isrm0 irdam0 asynchronous serial interface mode register 0 ( asim0) intsr0 receive controller (parity check) transmit shift register 0 (txs0) transmit controller (parity addition) receive shift register 0 (rx0)
303 chapter 16 serial interface uart0 user s manual u14046ej3v0ud 16.2 configuration of serial interface uart0 serial interface uart0 includes the following hardware. table 16-1. configuration of serial interface uart0 item configuration registers transmit shift register 0 (txs0) receive shift register 0 (rx0) receive buffer register 0 (rxb0) asynchronous serial interface status register 0 (asis0) control registers asynchronous serial interface mode register 0 (asim0) baud rate generator control register 0 (brgc0) port mode register 2 (pm2) port 2 (p2) (1) transmit shift register 0 (txs0) this is a register for setting transmit data. data written to txs0 is transmitted as serial data. when the data length is set as 7 bits, bits 0 to 6 of the data written to txs0 are transferred as transmit data. writing data to txs0 starts the transmit operation. txs0 can be written by an 8-bit memory manipulation instruction. it cannot be read. reset input sets txs0 to ffh. caution do not write to txs0 during a transmit operation. the same address is assigned to txs0 and receive buffer register 0 (rxb0), so a read operation reads values from rxb0. (2) receive shift register 0 (rx0) this register converts serial data input via the rxd0 pin to parallel data. when one byte of data is received at this register, the receive data is transferred to receive buffer register 0 (rxb0). rx0 cannot be manipulated directly by a program. (3) receive buffer register 0 (rxb0) this register is used to hold receive data. when one byte of data is received, one byte of new receive data is transferred from the receive shift register (rx0). when the data length is set as 7 bits, receive data is sent to bits 0 to 6 of rxb0. in this case, the msb of rxb0 is always 0. rxb0 can be read by an 8-bit memory manipulation instruction. it cannot be written. reset input sets rxb0 to ffh. caution the same address is assigned to rxb0 and transmit shift register 0 (txs0), so during a write operation, values are written to txs0.
304 chapter 16 serial interface uart0 user s manual u14046ej3v0ud (4) asynchronous serial interface status register 0 (asis0) when a receive error occurs in uart mode, this register indicates the type of error. asis0 can be read by an 8-bit memory manipulation instruction. reset input clears asis0 to 00h. figure 16-3. format of asynchronous serial interface status register 0 (asis0) address: ffa1h after reset: 00h r symbol 76543210 asis0 00000pe0fe0 ove0 pe0 parity error flag 0 no parity error 1 parity error (transmit data parity not matched) fe0 framing error flag 0 no framing error 1 framing error note 1 (stop bit not detected) ove0 overrun error flag 0 no overrun error 1 overrun error note 2 (next receive operation was completed before data was read from receive buffer register 0 (rxb0)) notes 1. even if the stop bit length is set to two bits by setting bit 2 (sl0) of asynchronous serial interface mode register 0 (asim0), stop bit detection during a receive operation only applies to a stop bit length of 1 bit. 2. when an overrun error has occurred, further overrun errors will continue to occur until the contents of receive buffer register 0 (rxb0) are read. (5) transmission controller the transmission controller controls transmit operations, such as adding a start bit, parity bit, and stop bit to data that is written to transmit shift register 0 (txs0), based on the values set to asynchronous serial interface mode register 0 (asim0). (6) reception controller the reception controller controls receive operations based on the values set to asynchronous serial interface mode register 0 (asim0). during a receive operation, it performs error checking, such as for parity errors, and sets various values to asynchronous serial interface status register 0 (asis0) according to the type of error that is detected.
305 chapter 16 serial interface uart0 user s manual u14046ej3v0ud 16.3 registers to control serial interface uart0 serial interface uart0 uses the following four registers for control functions. asynchronous serial interface mode register 0 (asim0) baud rate generator control register 0 (brgc0) port mode register 2 (pm2) port 2 (p2) (1) asynchronous serial interface mode register 0 (asim0) this is an 8-bit register that controls serial interface uart0 s serial transfer operations. asim0 is set by a 1-bit or 8-bit memory manipulation instruction. reset input clears asim0 to 00h. figure 16-4 shows the format of asim0.
306 chapter 16 serial interface uart0 user s manual u14046ej3v0ud figure 16-4. format of asynchronous serial interface mode register 0 (asim0) address: ffa0h after reset: 00h r/w symbol <7> <6> 543210 asim0 txe0 rxe0 ps01 ps00 cl0 sl0 isrm0 irdam0 txe0 rxe0 operation mode rxd0/p23 pin function txd0/p24 pin function 0 0 operation stop port function (p23) port function (p24) 0 1 uart mode serial function (rxd0) (receive only) 1 0 uart mode port function (p23) serial function (txd0) (transmit only) 1 1 uart mode serial function (rxd0) (transmit and receive) ps01 ps00 parity bit specification 0 0 no parity 0 1 zero parity always added during transmission no parity detection during reception (parity errors do not occur) 1 0 odd parity 1 1 even parity cl0 character length specification 0 7 bits 1 8 bits sl0 stop bit length specification for transmit data 0 1 bit 1 2 bits isrm0 receive completion interrupt control when error occurs 0 receive completion interrupt request is issued when an error occurs 1 receive completion interrupt request is not issued when an error occurs irdam0 operation specified for infrared data transfer mode note 1 0 uart (transmit/receive) mode 1 infrared data transfer (transmit/receive) mode note 2 notes 1. the uart/infrared data transfer mode specification is controlled by txe0 and rxe0. 2. when using infrared data transfer mode, be sure to set baud rate generator control register 0 (brgc0) to 10h . caution before writing different data to asim0, stop operation.
307 chapter 16 serial interface uart0 user s manual u14046ej3v0ud (2) baud rate generator control register 0 (brgc0) this register sets the serial clock for the serial interface. brgc0 is set by an 8-bit memory manipulation instruction. reset input clears brgc0 to 00h. figure 16-5 shows the format of brgc0.
308 chapter 16 serial interface uart0 user s manual u14046ej3v0ud figure 16-5. format of baud rate generator control register 0 (brgc0) address: ffa2h after reset: 00h r/w symbol 76543210 brgc0 0 tps02 tps01 tps00 mdl03 mdl02 mdl01 mdl00 (f x = 8.38 mhz) tps02 tps01 tps00 source clock selection for 5-bit counter n 0 0 0 external clock input to asck0 0 001f x /2 1 010f x /2 2 2 011f x /2 3 3 100f x /2 4 4 101f x /2 5 5 110f x /2 6 6 111f x /2 7 7 mdl03 mdl02 mdl01 mdl00 output clock selection for baud rate generator k 0000f sck0 /16 0 0001f sck0 /17 1 0010f sck0 /18 2 0011f sck0 /19 3 0100f sck0 /20 4 0101f sck0 /21 5 0110f sck0 /22 6 0111f sck0 /23 7 1000f sck0 /24 8 1001f sck0 /25 9 1010f sck0 /26 10 1011f sck0 /27 11 1100f sck0 /28 12 1101f sck0 /29 13 1110f sck0 /30 14 1111 setting prohibited ? cautions 1. writing to brgc0 during a communication operation may cause abnormal output from the baud rate generator and disable further communication operations. therefore, do not write to brgc0 during a communication operation. 2. set brgc0 to 10h when using in infrared data transfer mode. remarks 1. f x : main system clock oscillation frequency 2. f sck0 : source clock for 5-bit counter 3. n: value set via tps00 to tps02 (0 n 7) 4. k: value set via mdl00 to mdl03 (0 k 14) 5. the equation for the baud rate is as follows. [baud rate] = f x [hz] 2 n+1 (k + 16)
309 chapter 16 serial interface uart0 user s manual u14046ej3v0ud (3) port mode register 2 (pm2) port mode register 2 is used to set input/output of port 2 in 1-bit units. to use the p24/txd0 pin as a serial data output, clear pm24 and the output latch of p24 to 0. to use the p23/rxd0 pin as a serial data input, and the p25/asck0 pin as a clock input, set pm23 and pm25 to 1. at this time, the output latches of p23 and p25 can be either 0 or 1. pm2 is set by a 1-bit or 8-bit memory manipulation instruction. reset input sets pm2 to ffh. figure 16-6. format of port mode register 2 (pm2) address: ff22h after reset: ffh r/w symbol 76543210 pm2 1 1 pm25 pm24 pm23 pm22 pm21 pm20 pm2n i/o mode selection of p2n pin (n = 0 to 5) 0 output mode (output buffer on) 1 input mode (output buffer off)
310 chapter 16 serial interface uart0 user s manual u14046ej3v0ud 16.4 operation of serial interface uart0 this section explains the three modes of serial interface uart0. 16.4.1 operation stop mode because serial transfer is not performed in this mode, the power consumption can be reduced. in addition, pins can be used as ordinary ports. (1) register to be used operation stop mode is set by asynchronous serial interface mode register 0 (asim0). asim0 is set by a 1-bit or 8-bit memory manipulation instruction. reset input clears asim0 to 00h. address: ffa0h after reset: 00h r/w symbol <7> <6> 543210 asim0 txe0 rxe0 ps01 ps00 cl0 sl0 isrm0 irdam0 txe0 rxe0 operation mode rxd0/p23 pin function txd0/p24 pin function 0 0 operation stop port function (p23) port function (p24) 16.4.2 asynchronous serial interface (uart) mode this mode enables full-duplex operation wherein one byte of data after the start bit is transmitted or received. the on-chip baud rate generator dedicated to uart enables communications using a wide range of selectable baud rates. the communication range is between 1.2 kbps and 131 kbps (when operated at f x = 8.38 mhz). the baud rate (39 kbps max. (when operated of f x = 1.25 mhz)) can be defined by dividing the input clock to the asck0 pin. the uart baud rate generator can also be used to generate a midi-standard baud rate (31.25 kbps). (1) registers to be used asynchronous serial interface mode register 0 (asim0) asynchronous serial interface status register 0 (asis0) baud rate generator control register 0 (brgc0) port mode register 2 (pm2) port 2 (p2) (a) asynchronous serial interface mode register 0 (asim0) asim0 is set by a 1-bit or 8-bit memory manipulation instruction. reset input clears asim0 to 00h.
311 chapter 16 serial interface uart0 user s manual u14046ej3v0ud address: ffa0h after reset: 00h r/w symbol <7> <6> 543210 asim0 txe0 rxe0 ps01 ps00 cl0 sl0 isrm0 irdam0 txe0 rxe0 operation mode rxd0/p23 pin function txd0/p24 pin function 0 0 operation stop port function (p23) port function (p24) 0 1 uart mode serial function (rxd0) (receive only) 1 0 uart mode port function (p23) serial function (txd0) (transmit only) 1 1 uart mode serial function (rxd0) (transmit and receive) ps01 ps00 parity bit specification 0 0 no parity 0 1 zero parity always added during transmission no parity detection during reception (parity errors do not occur) 1 0 odd parity 1 1 even parity cl0 character length specification 0 7 bits 1 8 bits sl0 stop bit length specification for transmit data 0 1 bit 1 2 bits isrm0 receive completion interrupt control when error occurs 0 receive completion interrupt request is issued when an error occurs 1 receive completion interrupt request is not issued when an error occurs irdam0 operation specified for infrared data transfer mode note 1 0 uart (transmit/receive) mode 1 infrared data transfer (transmit/receive) mode note 2 notes 1. the uart/infrared data transfer mode specification is controlled by txe0 and rxe0. 2. when using infrared data transfer mode, be sure to set baud rate generator control register 0 (brgc0) to 10h. caution before writing different data to asim0, stop operation.
312 chapter 16 serial interface uart0 user s manual u14046ej3v0ud (b) asynchronous serial interface status register 0 (asis0) asis0 can be read by an 8-bit memory manipulation instruction. reset input clears asis0 to 00h. address: ffa1h after reset: 00h r symbol 76543210 asis0 00000pe0fe0 ove0 pe0 parity error flag 0 no parity error 1 parity error (transmit data parity not matched) fe0 framing error flag 0 no framing error 1 framing error note 1 (stop bit not detected) ove0 overrun error flag 0 no overrun error 1 overrun error note 2 (next receive operation was completed before data was read from receive buffer register 0 (rxb0)) notes 1. even if the stop bit length is set to two bits by setting bit 2 (sl0) of asynchronous serial interface mode register 0 (asim0), stop bit detection during a receive operation only applies to a stop bit length of 1 bit. 2. when an overrun error has occurred, further overrun errors will continue to occur until the contents of receive buffer register 0 (rxb0) are read.
313 chapter 16 serial interface uart0 user s manual u14046ej3v0ud (c) baud rate generator control register 0 (brgc0) brgc0 is set by an 8-bit memory manipulation instruction. reset input clears brgc0 to 00h. address: ffa2h after reset: 00h r/w symbol 76543210 brgc0 0 tps02 tps01 tps00 mdl03 mdl02 mdl01 mdl00 (f x = 8.38 mhz) tps02 tps01 tps00 source clock selection for 5-bit counter n 0 0 0 external clock input to asck0 0 001f x /2 1 010f x /2 2 2 011f x /2 3 3 100f x /2 4 4 101f x /2 5 5 110f x /2 6 6 111f x /2 7 7 mdl03 mdl02 mdl01 mdl00 output clock selection for baud rate generator k 0000f sck0 /16 0 0001f sck0 /17 1 0010f sck0 /18 2 0011f sck0 /19 3 0100f sck0 /20 4 0101f sck0 /21 5 0110f sck0 /22 6 0111f sck0 /23 7 1000f sck0 /24 8 1001f sck0 /25 9 1010f sck0 /26 10 1011f sck0 /27 11 1100f sck0 /28 12 1101f sck0 /29 13 1110f sck0 /30 14 1111 setting prohibited ? caution writing to brgc0 during a communication operation may cause abnormal output from the baud rate generator and disable further communication operations. therefore, do not write to brgc0 during a communication operation. remarks 1. f x : main system clock oscillation frequency 2. f sck0 : source clock for 5-bit counter 3. n: value set via tps00 to tps02 (0 n 7) 4. k: value set via mdl00 to mdl03 (0 k 14)
314 chapter 16 serial interface uart0 user s manual u14046ej3v0ud the transmit/receive clock that is used to generate the baud rate is obtained by dividing the main system clock. transmit/receive clock generation for baud rate by using main system clock the main system clock is divided to generate the transmit/receive clock. the baud rate generated from the main system clock is determined according to the following formula. [baud rate] = f x [hz] 2 n+1 (k + 16) f x : main system clock oscillation frequency when asck0 is selected as the source clock of the 5-bit counter, substitute the input clock frequency to the asck0 pin for f x in the above expression. n: value set via tps00 to tps02 (0 n 7) k: value set via mdl00 to mdl03 (0 k 14) table 16-2. relationship between main system clock and baud rate error baud rate f x = 8.3886 mhz f x = 8.000 mhz f x = 7.3728 mhz f x = 5.000 mhz f x = 4.1943 mhz (bps) brgc0 err (%) brgc0 err (%) brgc0 err (%) brgc0 err (%) brgc0 err (%) 600 ???????? 7bh 1.14 1200 7bh 1.10 7ah 0.16 78h 0 70h 1.73 6bh 1.14 2400 6bh 1.10 6ah 0.16 68h 0 60h 1.73 5bh 1.14 4800 5bh 1.10 5ah 0.16 58h 0 50h 1.73 4bh 1.14 9600 4bh 1.10 4ah 0.16 48h 0 40h 1.73 3bh 1.14 19200 3bh 1.10 3ah 0.16 38h 0 30h 1.73 2bh 1.14 31250 31h ? 1.3 30h 0 2dh 1.70 24h 0 21h ? 1.3 38400 2bh 1.10 2ah 0.16 28h 0 20h 1.73 1bh 1.14 76800 1bh 1.10 1ah 0.16 18h 0 10h 1.73 ?? 115200 12h 1.10 11h 2.12 10h 0 ???? remark f x : main system clock oscillation frequency error tolerance range for baud rate the error for the baud rate depends on the number of bits per frame and the 5-bit counter s division ratio [1/(16 + k)]. figure 16-7 shows an example of the baud rate error tolerance range.
315 chapter 16 serial interface uart0 user s manual u14046ej3v0ud figure 16-7. error tolerance (when k = 0), including sampling errors baud rate error tolerance (when k = 0) = 15.5 100 = 4.8438 (%) 320 caution the above error tolerance value is the value calculated based on the ideal sample point. in the actual design, allow margins that include errors of timing for detecting a start bit. remark t: 5-bit counter s source clock cycle (d) port mode register 2 (pm2) port mode register 2 is used to set input/output of port 2 in 1-bit units. to use the p24/txd0 pin as a serial data output, clear pm24 and the output latch of p24 to 0. to use the p23/rxd0 pin as a serial data input, and the p25/asck0 pin as a clock input, set pm23 and pm25 to 1. at this time, the output latches of p23 and p25 can be either 0 or 1. pm2 is set by a 1-bit or 8-bit memory manipulation instruction. reset input sets pm2 to ffh. address: ff22h after reset: ffh r/w symbol 76543210 pm2 1 1 pm25 pm24 pm23 pm22 pm21 pm20 pm2n i/o mode selection of p2n pin (n = 0 to 5) 0 output mode (output buffer on) 1 input mode (output buffer off) basic timing start d0 d7 p stop high-speed limit timing start d0 d7 p stop low-speed limit timing start d0 d7 p stop 32t 64t 256t 288t 320t 352t ideal sampling point 304t 336t 30.45t 60.9t 304.5t 15.5t 15.5t 0.5t sampling error 33.55t 67.1t 301.95t 335.5t
316 chapter 16 serial interface uart0 user s manual u14046ej3v0ud (2) communication operations (a) data format figure 16-8 shows the format of the transmit/receive data. figure 16-8. example of transmit/receive data format in asynchronous serial interface d0 d1 d2 d3 d4 d5 d6 d7 start bit parity bit stop bit 1 data frame character bits 1 data frame consists of the following bits. start bit ............. 1 bit character bits ... 7 bits or 8 bits (lsb first) parity bit ........... even parity, odd parity, zero parity, or no parity stop bit(s) ......... 1 bit or 2 bits asynchronous serial interface mode register 0 (asim0) is used to set the character bit length, parity selection, and stop bit length within each data frame. when 7 bits is selected as the number of character bits, only the lower 7 bits (bits 0 to 6) are valid, so that during a transmission the highest bit (bit 7) is ignored and during reception the highest bit (bit 7) must be cleared to 0. baud rate generator control register 0 (brgc0) is used to set the serial transfer rate. if a receive error occurs, information about the receive error can be ascertained by reading asynchronous serial interface status register 0 (asis0).
317 chapter 16 serial interface uart0 user s manual u14046ej3v0ud (b) parity types and operations the parity bit is used to detect bit errors in communication data. usually, the same type of parity bit is used by the transmitting and receiving sides. when odd parity or even parity is set, errors in the parity bit (the odd-number bit) can be detected. when zero parity or no parity is set, errors are not detected. (i) even parity during transmission the number of bits in transmit data that includes a parity bit is controlled so that there are an even number of character bits whose value is 1. the value of the parity bit is as follows. if the transmit data contains an odd number of character bits whose value is 1: the parity bit is 1 if the transmit data contains an even number of character bits whose value is 1: the parity bit is 0 during reception the number of character bits whose value is 1 is counted in the receive data that includes a parity bit, and a parity error occurs when the counted result is an odd number. (ii) odd parity during transmission the number of bits in transmit data that includes a parity bit is controlled so that there is an odd number of character bits whose value is 1. the value of the parity bit is as follows. if the transmit data contains an odd number of character bits whose value is 1: the parity bit is 0 if the transmit data contains an even number of character bits whose value is 1: the parity bit is 1 during reception the number of character bits whose value is 1 is counted in the receive data that includes a parity bit, and a parity error occurs when the counted result is an even number. (iii) zero parity during transmission, the parity bit is set to 0 regardless of the transmit data. during reception, the parity bit is not checked. therefore, no parity errors will occur regardless of whether the parity bit is a 0 or a 1 . (iv) no parity no parity bit is added to the transmit data. during reception, receive data is regarded as having no parity bit. since there is no parity bit, no parity errors will occur.
318 chapter 16 serial interface uart0 user s manual u14046ej3v0ud (c) transmission the transmit operation is enabled if bit 7 (txe0) of asynchronous serial interface mode register 0 (asim0) is set to 1, and the transmit operation is started when transmit data is written to transmit shift register 0 (txs0). a start bit, parity bit, and stop bit(s) are automatically added to the data. starting the transmit operation shifts out the data in txs0, thereby emptying txs0, after which a transmit completion interrupt request (intst0) is issued. the timing of the transmit completion interrupt request is shown in figure 16-9. figure 16-9. timing of asynchronous serial interface transmit completion interrupt request (i) stop bit length: 1 bit (ii) stop bit length: 2 bits caution do not rewrite asynchronous serial interface mode register 0 (asim0) during a transmit operation. rewriting the asim0 register during a transmit operation may disable further transmit operations (in such cases, enter a reset to restore normal operation). txd0 (output) d0 d1 d2 d6 d7 parity stop start intst0 txd0 (output) d0 d1 d2 d6 d7 parity start intst0 stop
319 chapter 16 serial interface uart0 user s manual u14046ej3v0ud (d) reception the receive operation performs level detection. the receive operation is enabled when 1 is set to bit 6 (rxe0) of asynchronous serial interface mode register 0 (asim0), and the input via the rxd0 pin is sampled. the serial clock specified by baud rate generator control register 0 (brgc0) is used to sample the rxd0 pin. when the rxd0 pin goes low, the 5-bit counter of the baud rate generator begins counting and the start timing signal for data sampling is output when half of the specified baud rate time has elapsed. if sampling the rxd0 pin input at this start timing signal yields a low-level result, a start bit is recognized, after which the 5-bit counter is initialized and starts counting and data sampling begins. after the start bit is recognized, the character data, parity bit, and one-bit stop bit are detected, at which point reception of one data frame is completed. once reception of one data frame is completed, the receive data in the shift register is transferred to receive buffer register 0 (rxb0) and intsr0 (receive completion interrupt request) occurs. if the rxe0 bit is reset (to 0) during a receive operation, the receive operation is stopped immediately. at this time, the contents of rxb0 and asis0 do not change, nor does intsr0 or intser0 (receive error interrupt request) occur. figure 16-10 shows the timing of the asynchronous serial interface receive completion interrupt request. figure 16-10. timing of asynchronous serial interface receive completion interrupt request caution if the receive operation is enabled with the rxd0 pin input at the low level, the receive operation is immediately started. make sure the rxd0 pin input is at the high level before enabling the receive operation. rxd0 (input) d0 d1 d2 d6 d7 parity stop start intsr0
320 chapter 16 serial interface uart0 user s manual u14046ej3v0ud (e) receive errors three types of errors can occur during a receive operation: a parity error, framing error, or overrun error. if, as the result of data reception, an error flag is set in asynchronous serial interface status register 0 (asis0), a receive error interrupt request (intser0) will occur. receive error interrupt requests are generated before the receive completion interrupt request (intsr0). table 16-3 lists the causes behind receive errors. as part of receive error interrupt request (intser0) servicing, the contents of asis0 can be read to determine which type of error occurred during the receive operation (see table 16-3 and figure 16-11 ). the contents of asis0 are reset (to 0) when receive buffer register 0 (rxb0) is read or when the next data is received (if the next data contains an error, its error flag will be set). table 16-3. causes of receive errors receive error cause asis0 value parity error parity specified does not match parity of receive data 04h framing error stop bit was not detected 02h overrun error reception of the next data was completed before data was read from 01h receive buffer register 0 (rxb0) figure 16-11. receive error timing rxd0 (input) d0 d1 d2 d6 d7 parity stop start intsr0 note intser0 (when framing/overrun error occurs) intser0 (when parity error occurs) note even if a receive error occurs when the isrm0 bit has been set (1), intsr0 does not occur. cautions 1. the contents of asynchronous serial interface status register 0 (asis0) are reset (to 0) when receive buffer register 0 (rxb0) is read or when the next data is received. to obtain information about the error, be sure to read the contents of asis0 before reading rxb0. 2. be sure to read the contents of receive buffer register 0 (rxb0) after the receive completion interrupt request has occurred even when a receive error has occurred. if rxb0 is not read after the receive completion interrupt request has occurred, overrun errors will occur during the next data receive operations and the receive error status will remain until the contents of rxb0 are read.
321 chapter 16 serial interface uart0 user s manual u14046ej3v0ud 16.4.3 infrared data transfer mode in infrared data transfer mode, pulses can be output and received in the data format shown in (2). (1) registers to be used asynchronous serial interface mode register 0 (asim0) asynchronous serial interface status register 0 (asis0) baud rate generator control register 0 (brgc0) port mode register 2 (pm2) port 2 (p2) (a) asynchronous serial interface mode register 0 (asim0) asim0 is set by a 1-bit or 8-bit memory manipulation instruction. reset input clears asim0 to 00h.
322 chapter 16 serial interface uart0 user s manual u14046ej3v0ud address: ffa0h after reset: 00h r/w symbol <7> <6> 543210 asim0 txe0 rxe0 ps01 ps00 cl0 sl0 isrm0 irdam0 txe0 rxe0 operation mode rxd0/p23 pin function txd0/p24 pin function 0 0 operation stop port function (p23) port function (p24) 0 1 uart mode serial function (rxd0) (receive only) 1 0 uart mode port function (p23) serial function (txd0) (transmit only) 1 1 uart mode serial function (rxd0) (transmit and receive) ps01 ps00 parity bit specification 0 0 no parity 0 1 zero parity always added during transmission no parity detection during reception (parity errors do not occur) 1 0 odd parity 1 1 even parity cl0 character length specification 0 7 bits 1 8 bits sl0 stop bit length specification for transmit data 0 1 bit 1 2 bits isrm0 receive completion interrupt control when error occurs 0 receive completion interrupt request is issued when an error occurs 1 receive completion interrupt request is not issued when an error occurs irdam0 operation specified for infrared data transfer mode note 1 0 uart (transmit/receive) mode 1 infrared data transfer (transmit/receive) mode note 2 notes 1. the uart/infrared data transfer mode specification is controlled by txe0 and rxe0. 2. when using infrared data transfer mode, be sure to set baud rate generator control register 0 (brgc0) to 10h . caution before writing different data to asim0, stop operation.
323 chapter 16 serial interface uart0 user s manual u14046ej3v0ud (b) asynchronous serial interface status register 0 (asis0) asis0 can be read by an 8-bit memory manipulation instruction. reset input clears asis0 to 00h. address: ffa1h after reset: 00h r symbol 76543210 asis0 00000pe0fe0 ove0 pe0 parity error flag 0 no parity error 1 parity error (transmit data parity not matched) fe0 framing error flag 0 no framing error 1 framing error note 1 (stop bit not detected) ove0 overrun error flag 0 no overrun error 1 overrun error note 2 (next receive operation was completed before data was read from receive buffer register 0 (rxb0)) notes 1. even if the stop bit length is set to two bits by setting bit 2 (sl0) of asynchronous serial interface mode register 0 (asim0), stop bit detection during a receive operation only applies to a stop bit length of 1 bit. 2. when an overrun error has occurred, further overrun errors will continue to occur until the contents of receive buffer register 0 (rxb0) are read.
324 chapter 16 serial interface uart0 user s manual u14046ej3v0ud (c) baud rate generator control register 0 (brgc0) brgc0 is set by an 8-bit memory manipulation instruction. reset input clears brgc0 to 00h. address: ffa2h after reset: 00h r/w symbol 76543210 brgc0 0 tps02 tps01 tps00 mdl03 mdl02 mdl01 mdl00 (f x = 8.38 mhz) tps02 tps01 tps00 source clock selection for 5-bit counter n 0 0 0 external clock input to asck0 0 001f x /2 1 010f x /2 2 2 011f x /2 3 3 100f x /2 4 4 101f x /2 5 5 110f x /2 6 6 111f x /2 7 7 mdl03 mdl02 mdl01 mdl00 output clock selection for baud rate generator k 0000f sck0 /16 0 0001f sck0 /17 1 0010f sck0 /18 2 0011f sck0 /19 3 0100f sck0 /20 4 0101f sck0 /21 5 0110f sck0 /22 6 0111f sck0 /23 7 1000f sck0 /24 8 1001f sck0 /25 9 1010f sck0 /26 10 1011f sck0 /27 11 1100f sck0 /28 12 1101f sck0 /29 13 1110f sck0 /30 14 1111 setting prohibited ? cautions 1. writing to brgc0 during a communication operation may cause abnormal output from the baud rate generator and disable further communication operations. therefore, do not write to brgc0 during a communication operation. 2. set brgc0 to 10h when using in infrared data transfer mode. remarks 1. f x : main system clock oscillation frequency 2. f sck0 : source clock for 5-bit counter 3. n: value set via tps00 to tps02 (0 n 7) 4. k: value set via mdl00 to mdl03 (0 k 14)
325 chapter 16 serial interface uart0 user s manual u14046ej3v0ud (d) port mode register 2 (pm2) port mode register 2 is used to set input/output of port 2 in 1-bit units. to use the p24/txd0 pin as a serial data output, clear pm24 and the output latch of p24 to 0. to use the p23/rxd0 pin as a serial data input, and the p25/asck0 pin as a clock input, set pm23 and pm25 to 1. at this time, the output latches of p23 and p25 can be either 0 or 1. pm2 is set by a 1-bit or 8-bit memory manipulation instruction. reset input sets pm2 to ffh. address: ff22h after reset: ffh r/w symbol 76543210 pm2 1 1 pm25 pm24 pm23 pm22 pm21 pm20 pm2n i/o mode selection of p2n pin (n = 0 to 5) 0 output mode (output buffer on) 1 input mode (output buffer off) (2) data format figure 16-12 compares the data format used in uart mode with that used in infrared data transfer mode. the ir (infrared) frame corresponds to the bit string of the uart frame, which consists of pulses that include a start bit, eight data bits, and a stop bit. the length of the electrical pulses that are used to transmit and receive in an ir frame is 3/16 the length of the cycle time for one bit (i.e., the bit time ). this pulse (whose width is 3/16 the length of one bit time) rises from the middle of the bit time (see the figure below). bit time pulse width = 3/16 bit time
326 chapter 16 serial interface uart0 user s manual u14046ej3v0ud figure 16-12. data format comparison between infrared data transfer mode and uart mode (3) relationship between main system clock and baud rate table 16-4 shows the relationship between the main system clock and the baud rate. table 16-4. relationship between main system clock and baud rate f x = 8.3886 mhz f x = 8.000 mhz f x = 7.3728 mhz f x = 5.000 mhz f x = 4.1943 mhz baud rate 131031 bps 125000 bps 115200 bps 78125 bps 65536 bps (4) bit rate and pulse width table 16-5 lists the bit rate, bit rate error tolerance, and pulse width values. table 16-5. bit rate and pulse width values bit rate bit rate error tolerance pulse width minimum value 3/16 pulse width maximum pulse width (kbps) (% of bit rate) ( s) note 2 ( s) ( s) 115.2 note 1 +/ ? 0.87 1.41 1.63 2.71 notes 1. operation with f x = 7.3728 mhz 2. when a digital noise eliminator is used in a microcontroller operating at 1.41 mhz or above. caution when using baud rate generator control register 0 (brgc0) in infrared data transfer mode, set it to 10h. remark f x : main system clock oscillation frequency 0 start bit 1 d0 0 d1 1 d2 0 d3 0 d4 1 d5 1 d6 0 d7 1 stop bit uart frame data bits start bit 10100110 stop bit ir frame data bits pulse width = 3/16 bit time bit time 0 1
327 chapter 16 serial interface uart0 user s manual u14046ej3v0ud (5) input data and internal signals transmit operation timing receive operation timing data reception is delayed for one-half of the specified baud rate. uart output data uart (inverted data) infrared data transfer enable signal txd0 pin output signal start bit stop bit uart transfer data rxd0 input edge detection sampling clock start bit stop bit receive rate conversion data sampling timing
328 chapter 16 serial interface uart0 user s manual u14046ej3v0ud table 16-6. register settings caution when using the infrared data transfer mode, set the brgc0 register to 10h. remark : don t care, asim0: asynchronous serial interface mode register 0 brgc0: baud rate generator control register 0, pm xx : port mode register, p xx : output latch of port asim0 txe0 0 rxe0 0 ps01 ps00 cl0 sl0 isrm0 irdam0 tps02 tps01 other than above tps00 mdl03 mdl02 mdl01 mdl00 p23/rxd0 p23 p24/txd0 p24 pm23 p23 pm24 p24 pin function operation mode stop brgc0 (1) operation stop mode asim0 txe0 0 1 1 rxe0 1 0 1 ps01 0/1 0/1 0/1 ps00 0/1 0/1 0/1 cl0 0/1 0/1 0/1 sl0 0/1 0/1 isrm0 0/1 0/1 irdam0 0 0 0 tps02 0/1 0/1 0/1 tps01 0/1 0/1 0/1 other than above tps00 0/1 0/1 0/1 mdl03 0/1 0/1 0/1 mdl02 0/1 0/1 0/1 mdl01 0/1 0/1 0/1 mdl00 0/1 0/1 0/1 p23/rxd0 rxd0 p23 rxd0 p24/txd0 p24 txd0 txd0 pm23 1 1 p23 pm24 0 0 p24 0 0 pin function operation mode receive transmit transmit /receive brgc0 (2) asynchronous serial interface (uart) mode setting prohibited asim0 txe0 0 1 1 rxe0 1 0 1 ps01 0/1 0/1 0/1 ps00 0/1 0/1 0/1 cl0 0/1 0/1 0/1 sl0 0/1 0/1 isrm0 0/1 0/1 irdam0 1 1 1 tps02 0 0 0 tps01 0 0 0 other than above tps00 1 1 1 mdl03 0 0 0 mdl02 0 0 0 mdl01 0 0 0 mdl00 0 0 0 p23/rxd0 rxd0 p23 rxd0 p24/txd0 p24 txd0 txd0 pm23 1 1 p23 pm24 0 0 p24 0 0 pin function operation mode receive transmit transmit /receive brgc0 (3) infrared data transfer mode setting prohibited setting prohibited
329 user? manual u14046ej3v0ud chapter 17 serial interfaces sio30 and sio31 the pd780024a, 780034a subseries products have two 3-wire serial i/o mode channels (sio30, sio31). the pd780024ay, 780034ay subseries products have one 3-wire serial i/o mode channel (sio30). 17.1 functions of serial interfaces sio30 and sio31 serial interface sio3n has the following two modes. (1) operation stop mode this mode is used when serial transfers are not performed. for details, see 17.4.1 operation stop mode . (2) 3-wire serial i/o mode (fixed as msb first) this is an 8-bit data transfer mode using three lines: a serial clock line (sck3n), serial output line (so3n), and serial input line (si3n). since simultaneous transmit and receive operations are enabled in 3-wire serial i/o mode, the processing time for data transfers is reduced. the first bit of the serial transferred 8-bit data is fixed as the msb. 3-wire serial i/o mode is useful for connection to a peripheral ic incorporating a clocked serial interface, a display controller, etc. for details, see 17.4.2 3-wire serial i/o mode . figure 17-1 shows a block diagram of serial interface sio3n. remark n = 0, 1: pd780024a, 780034a subseries n = 0: pd780024ay, 780034ay subseries figure 17-1. block diagram of serial interface sio3n note si30, so30, and sck30 pins are alternate with p20, p21, and p22 pins. si31, so31, and sck31 pins are alternate with p34, p35, and p36 pins. internal bus 8 serial clock controller serial clock counter interrupt request signal generator selector serial i/o shift register 3n (sio3n) si3n note so3n note sck3n note intcsi3n f x /2 3 f x /2 4 f x /2 5 output latch
330 chapter 17 serial interfaces sio30 and sio31 user s manual u14046ej3v0ud 17.2 configuration of serial interfaces sio30 and sio31 serial interface sio3n consists of the following hardware. table 17-1. configuration of serial interface sio3n item configuration register serial i/o shift register 3n (sio3n) control registers serial operation mode register 3n (csim3n) port mode registers 2, 3 (pm2, pm3) ports 2, 3 (p2, p3) (1) serial i/o shift register 3n (sio3n) this is an 8-bit register that performs parallel-serial conversion and serial transmit/receive (shift operations) synchronized with the serial clock. sio3n is set by an 8-bit memory manipulation instruction. when 1 is set to bit 7 (csie3n) of serial operation mode register 3n (csim3n), a serial operation can be started by writing data to or reading data from sio3n. when transmitting, data written to sio3n is output to the serial output (so3n). when receiving, data is read from the serial input (si3n) and written to sio3n. reset input makes sio3n undefined. caution do not access sio3n during a transfer operation unless the access is triggered by a transfer start (read operation is disabled when moden = 0 and write operation is disabled when moden = 1). remark n = 0, 1: pd780024a, 780034a subseries n = 0: pd780024ay, 780034ay subseries
331 chapter 17 serial interfaces sio30 and sio31 user s manual u14046ej3v0ud 17.3 registers to control serial interfaces sio30 and sio31 serial interface sio3n is controlled by the following three registers. ? serial operation mode register 3n (csim3n) ? port mode registers 2, 3 (pm2, pm3) ? ports 2, 3 (p2, p3) (1) serial operation mode register 3n (csim3n) this register is used to enable or disable sio3n s serial clock, operation modes, and specific operations. csim3n is set by a 1-bit or 8-bit memory manipulation instruction. reset input clears csim3n to 00h. remark n = 0, 1: pd780024a, 780034a subseries n = 0: pd780024ay, 780034ay subseries
332 chapter 17 serial interfaces sio30 and sio31 user s manual u14046ej3v0ud figure 17-2. format of serial operation mode register 30 (csim30) address: ffb0h after reset: 00h r/w symbol <7> 6543210 csim30 csie30 0000 mode0 scl301 scl300 csie30 enable/disable specification for sio30 shift register operation serial counter port 0 operation stopped clear port function note 1 1 operation enabled count operation enable serial function + port function note 2 mode0 transfer operation modes and flags operation mode transfer start trigger so30/p21 pin function 0 transmit/transmit and receive mode write to sio30 so30 1 receive-only mode read from sio30 p21 note 3 scl301 scl300 clock selection f x = 8.38 mhz f x = 12 mhz note 4 0 0 external clock input to sck30 ?? 01f x /2 3 1.04 mhz 1.50 mhz 10f x /2 4 523 khz 750 khz 11f x /2 5 261 khz 375 khz notes 1. when csie30 = 0 (sio30 operation stopped status), the si30, so30, and sck30 pins can be used as port functions. 2. when csie30 = 1 (sio30 operation enabled status), the si30 pin can be used as a port pin if only the transmit function is used, and the so30 pin can be used as a port pin if only the receive-only mode is used. 3. when mode0 = 1 (receive-only mode), the so30 pin can be used for port functions. 4. expanded-specification products of pd780024a, 780034a subseries only. caution do not rewrite the value of csim30 during transfer. however, csie30 can be rewritten using a 1-bit memory manipulation instruction. remark f x : main system clock oscillation frequency
333 chapter 17 serial interfaces sio30 and sio31 user s manual u14046ej3v0ud figure 17-3. format of serial operation mode register 31 (csim31) address: ffb8h after reset: 00h r/w symbol <7> 6543210 csim31 csie31 0000 mode1 scl311 scl310 csie31 enable/disable specification for sio31 shift register operation serial counter port 0 operation stopped clear port function note 1 1 operation enabled count operation enable serial function + port function note 2 mode1 transfer operation modes and flags operation mode transfer start trigger so31/p35 pin function 0 transmit/transmit and receive mode write to sio31 so31 1 receive-only mode read from sio31 p35 note 3 scl311 scl310 clock selection f x = 8.38 mhz f x = 12 mhz note 4 0 0 external clock input to sck31 01f x /2 3 1.04 mhz 1.50 mhz 10f x /2 4 523 khz 750 khz 11f x /2 5 261 khz 375 khz notes 1. when csie31 = 0 (sio31 operation stopped status), the si31, so31, and sck31 pins can be used as port functions. 2. when csie31 = 1 (sio31 operation enabled status), the si31 pin can be used as a port pin if only the transmit function is used, and the so31 pin can be used as a port pin if only the receive-only mode is used. 3. when mode1 = 1 (receive-only mode), the so31 pin can be used for port functions. 4. expanded-specification products of pd780024a, 780034a subseries only. caution do not rewrite the value of csim31 during transfer. however, csie31 can be rewritten using a 1-bit memory manipulation instruction. remark f x : main system clock oscillation frequency
334 chapter 17 serial interfaces sio30 and sio31 user s manual u14046ej3v0ud (2) port mode registers 2, 3 (pm2, pm3) these registers set the input/output of ports 2 and 3 in 1-bit units. to use the p21/so30 and p35/so31 pins as serial data output, and the p22/sck30 and p36/sck31 pins as clock output, clear pm21, pm35, pm22, pm36, and the output latches of p21, p35, p22, and p36 to 0. to use the p20/si30 and p34/si31 pins as serial data input, and the p22/sck30 and p36/sck31 pins as clock input, set pm20, pm34, pm22, and pm36 to 1. at this time, the output latches of p20, p34, p22, and p36 can be either 0 or 1. pm2 and pm3 are set by a 1-bit or 8-bit memory manipulation instruction. reset input sets pm2 and pm3 to ffh. figure 17-4. format of port mode register 2 (pm2) address: ff22h after reset: ffh r/w symbol 76543210 pm2 1 1 pm25 pm24 pm23 pm22 pm21 pm20 pm2n i/o mode selection of p2n pin (n = 0 to 5) 0 output mode (output buffer on) 1 input mode (output buffer off) figure 17-5. format of port mode register 3 (pm3) address: ff23h after reset: ffh r/w symbol 76543210 pm3 1 pm36 pm35 pm34 pm33 pm32 pm31 pm30 pm3n i/o mode selection of p3n pin (n = 0 to 6) 0 output mode (output buffer on) 1 input mode (output buffer off)
335 chapter 17 serial interfaces sio30 and sio31 user s manual u14046ej3v0ud 17.4 operations of serial interfaces sio30 and sio31 this section explains the two modes of serial interface sio3n. 17.4.1 operation stop mode because the serial transfer is not performed during this mode, the power consumption can be reduced. in addition, pins can be used as normal i/o ports. (1) register settings operation stop mode is set by serial operation mode register 3n (csim3n). csim3n is set by a 1-bit or 8-bit memory manipulation instruction. reset input clears csim3n to 00h. address: ffb0h (sio30), ffb8h (sio31) after reset: 00h r/w symbol <7> 6543210 csim3n csie3n 0000 moden scl3n1 scl3n0 csie3n enable/disable specification for sio3n shift register operation serial counter port 0 operation disabled clear port function note note when csie3n = 0 (sio3n operation stop status), the pins si3n, so3n, and sck3n can be used for port functions. remark n = 0, 1
336 chapter 17 serial interfaces sio30 and sio31 user s manual u14046ej3v0ud 17.4.2 3-wire serial i/o mode the 3-wire serial i/o mode can be used when connecting a peripheral ic incorporating a clocked serial interface, a display controller, etc. this mode executes data transfers via three lines: a serial clock line (sck3n), serial output line (so3n), and serial input line (si3n). (1) registers to be used serial operation mode register 3n (csim3n) port mode registers 2, 3 (pm2, pm3) ports 2, 3 (p2, p3) (a) serial operation mode register 3n (csim3n) csim3n is set by a 1-bit or 8-bit memory manipulation instruction. reset input clears csim3n to 00h. address: ffb0h (sio30), ffb8h (sio31) after reset: 00h r/w symbol <7> 6543210 csim3n csie3n 0000 moden scl3n1 scl3n0 csie3n enable/disable specification for sio3n shift register operation serial counter port 0 operation stopped clear port function note 1 1 operation enabled count operation enable serial function + port function note 2 moden transfer operation modes and flags operation mode transfer start trigger so3n pin function 0 transmit/transmit and receive mode write to sio3n so3n 1 receive-only mode read from sio3n port function note 3 scl3n1 scl3n0 clock selection f x = 8.38 mhz f x = 12 mhz note 4 0 0 external clock input to sck3n ?? 01f x /2 3 1.04 mhz 1.50 mhz 10f x /2 4 523 khz 750 khz 11f x /2 5 261 khz 375 khz notes 1. when csie3n = 0 (sio3n operation stopped status), the si3n, so3n, and sck3n pins can be used as port functions. 2. when csie3n = 1 (sio3n operation enabled status), the si3n pin can be used as a port pin if only the transmit function is used, and the so3n pin can be used as a port pin if only the receive-only mode is used. 3. when moden = 1 (receive-only mode), the so3n pin can be used for port functions. 4. expanded-specification products of pd780024a, 780034a subseries only.
337 chapter 17 serial interfaces sio30 and sio31 user s manual u14046ej3v0ud caution do not rewrite the value of csim3n during transfer. however, csie3n can be rewritten using a 1-bit memory manipulation instruction. remarks 1. f x : main system clock oscillation frequency 2. n = 0, 1: pd780024a, 780034a subseries n = 0: pd780024ay, 780034ay subseries (b) port mode registers 2, 3 (pm2, pm3) these registers set the input/output of ports 2 and 3 in 1-bit units. to use the p21/so30 and p35/so31 pins as serial data output, and the p22/sck30 and p36/sck31 pins as clock output, clear pm21, pm35, pm22, pm36, and the output latches of p21, p35, p22, and p36 to 0. to use the p20/si30 and p34/si31 pins as serial data input, and the p22/sck30 and p36/sck31 pins as clock input, set pm20, pm34, pm22, and pm36 to 1. at this time, the output latches of p20, p34, p22, and p36 can be either 0 or 1. pm2 and pm3 are set by a 1-bit or 8-bit memory manipulation instruction. reset input sets pm2 and pm3 to ffh. address: ff22h after reset: ffh r/w symbol 76543210 pm2 1 1 pm25 pm24 pm23 pm22 pm21 pm20 pm2n i/o mode selection of p2n pin (n = 0 to 5) 0 output mode (output buffer on) 1 input mode (output buffer off) address: ff23h after reset: ffh r/w symbol 76543210 pm3 1 pm36 pm35 pm34 pm33 pm32 pm31 pm30 pm3n i/o mode selection of p3n pin (n = 0 to 6) 0 output mode (output buffer on) 1 input mode (output buffer off) (2) transfer start a serial transfer starts when the following two conditions have been satisfied and transfer data has been set (or read) to serial i/o shift register 3n (sio3n). sio3n operation control bit (csie3n) = 1 after an 8-bit serial transfer, either the internal serial clock is stopped or sck3n is set to high level. transmit/transmit and receive mode (moden = 0) transfer starts when writing to sio3n. receive-only mode (moden = 1) transfer starts when reading from sio3n. caution after data has been written to sio3n, transfer will not start even if the csie3n bit value is set to 1.
338 chapter 17 serial interfaces sio30 and sio31 user s manual u14046ej3v0ud (3) communication operations in the 3-wire serial i/o mode, data is transmitted and received in 8-bit units. each bit of data is transmitted or received in synchronization with the serial clock. serial i/o shift register 3n (sio3n) is shifted in synchronization with the falling edge of the serial clock. transmit data is held in the so3n latch and is output from the so3n pin. data that is received via the si3n pin in synchronization with the rising edge of the serial clock is latched to sio3n. figure 17-6. timing of 3-wire serial i/o mode (4) transfer complete completion of an 8-bit transfer automatically stops the serial transfer operation and the interrupt request flag (csiif3n) is set. remark n = 0, 1: pd780024a, 780034a subseries n = 0: pd780024ay, 780034ay subseries si3n di7 di6 di5 di4 di3 di2 di1 di0 csiif3n sck3n 1 so3n do7 do6 do5 do4 do3 do2 do1 do0 2345678 transfer completion transfer starts in synchronization with the sck3n falling edge latched to sio3n at the sck3n rising edge
339 chapter 17 serial interfaces sio30 and sio31 user s manual u14046ej3v0ud table 17-2. register settings note when using for transmission only, it can be used as p20 or p34. remark : don t care, csim30, csim31: serial operation mode registers 30, 31, pm : port mode register, p : output latch of port csim30 pm20 p20 pm21 p21 pm22 p22 csie30 0 mode0 scl301 scl300 p20/si30 p20 p21/so30 p21 p22/sck30 p22 pin function operation stop other than above (1) operation stop mode ? serial interface sio30 ? serial interface sio31 setting prohibited csim31 pm34 p34 pm35 p35 pm36 p36 csie31 0 mode1 scl311 scl310 p34/si31 p34 p35/so31 p35 p36/sck31 p36 pin function operation stop other than above ? serial interface sio31 setting prohibited csim31 pm34 1 1 1 1 p34 pm35 0 0 p35 0 0 pm36 1 1 0 0 p36 0 0 csie31 1 1 1 1 mode1 1 0 1 0 scl311 0 0 scl310 0 0 p21/si31 si31 si31 note si31 si31 note p21/so31 p35 so31 p35 so31 p22/sck31 sck31 input sck31 input sck31 output sck31 output pin function other than above other than above setting prohibited operation slave receive slave transmit/transmit and receive master receive master transmit/transmit and receive (2) 3-wire serial i/o mode ? serial interface sio30 csim30 pm20 1 1 1 1 p20 pm21 0 0 p21 0 0 pm22 1 1 0 0 p22 0 0 csie30 1 1 1 1 mode0 1 0 1 0 scl301 0 0 scl300 0 0 p20/si30 si30 si30 note si30 si30 note p21/so30 p21 so30 p21 so30 p22/sck30 sck30 input sck30 input sck30 output sck30 output pin function other than above other than above setting prohibited operation slave receive slave transmit/transmit and receive master receive master transmit/transmit and receive
340 user? manual u14046ej3v0ud chapter 18 serial interface iic0 ( pd780024ay, 780034ay subseries only) 18.1 functions of serial interface iic0 serial interface iic0 has the following two modes. (1) operation stop mode this mode is used when serial transfers are not performed. it can therefore be used to reduce power consumption. (2) i 2 c bus mode (multimaster supported) this mode is used for 8-bit data transfers with several devices via two lines: a serial clock (scl0) line and a serial data bus (sda0) line. the transfer rate is as follows. 97.5 khz (standard mode) or 350 khz (high-speed mode): when operated at f x = 8.38 mhz this mode complies with the i 2 c bus format and can output ?tart condition? ?ata? and ?top condition?data segments when transmitting via the serial data bus. these data segments are automatically detected by hardware during reception. since scl0 and sda0 are open-drain outputs, the iic0 requires pull-up resistors for the serial clock line (scl0) and the serial data bus line (sda0). figure 18-1 shows a block diagram of serial interface iic0.
341 chapter 18 serial interface iic0 ( pd780024ay, 780034ay subseries only) user? manual u14046ej3v0ud figure 18-1. block diagram of serial interface iic0 internal bus slave address register 0 (sva0) noise eliminator sda0/p32 iic shift register 0 (iic0) ack detector pm32 output latch (p32) start condition detector stop condition detector serial clock counter serial clock controller noise eliminator scl0/p33 n-ch open- drain output prescaler n-ch open- drain output internal bus f x serial clock wait controller cld0 dad0 smc0 dfc0 cl00 interrupt request signal generator wake-up controller ack output circuit data hold time correction circuit cl00 dq so0 latch set clear match signal iice0 lrel0 wrel0 spie0 wtim0 acke0 stt0 spt0 msts0 ald0 exc0 coi0 trc0 adkd0 std0 spd0 iic transfer clock select register 0 (iiccl0) intiic0 iic status register 0 (iics0) iic control register 0 (iicc0) pm33 output latch (p33)
342 chapter 18 serial interface iic0 ( pd780024ay, 780034ay subseries only) user? manual u14046ej3v0ud figure 18-2 shows a serial bus configuration example. figure 18-2. serial bus configuration example using i 2 c bus sda0 scl0 sda0 +v dd0 +v dd0 scl0 sda0 scl0 slave cpu3 address 2 sda0 scl0 slave ic address 3 sda0 scl0 slave ic address n master cpu1 slave cpu1 address 0 serial data bus serial clock master cpu2 slave cpu2 address 1
343 chapter 18 serial interface iic0 ( pd780024ay, 780034ay subseries only) user s manual u14046ej3v0ud 18.2 configuration of serial interface iic0 serial interface iic0 includes the following hardware. table 18-1. configuration of serial interface iic0 item configuration registers iic shift register 0 (iic0) slave address register 0 (sva0) control registers iic control register 0 (iicc0) iic status register 0 (iics0) iic transfer clock select register 0 (iiccl0) port mode register 3 (pm3) port 3 (p3) (1) iic shift register 0 (iic0) iic0 is used to convert 8-bit serial data to 8-bit parallel data and vice versa in synchronization with the serial clock. iic0 can be used for both transmission and reception. write and read operations to iic0 are used to control the actual transmit and receive operations. iic0 is set by an 8-bit memory manipulation instruction. reset input clears iic0 to 00h. figure 18-3. format of iic shift register 0 (iic0) address: ff1fh after reset: 00h r/w symbol 76543210 iic0 caution do not write data to iic0 during data transfer. (2) slave address register 0 (sva0) this register sets local addresses when in slave mode. sva0 is set by an 8-bit memory manipulation instruction. reset input clears sva0 to 00h. figure 18-4. format of slave address register 0 (sva0) address: ffabh after reset: 00h r/w symbol 76543210 sva0 0 note note bit 0 is fixed to 0.
344 chapter 18 serial interface iic0 ( pd780024ay, 780034ay subseries only) user s manual u14046ej3v0ud (3) so0 latch the so0 latch is used to retain the sda0 pin s output level. (4) wake-up controller this circuit generates an interrupt request when the address received by this register matches the address value set to slave address register 0 (sva0) or when an extension code is received. (5) prescaler this selects the sampling clock to be used. (6) serial clock counter this counter counts the serial clocks that are output or input during transmit/receive operations and is used to verify that 8-bit data was transmitted or received. (7) interrupt request signal generator this circuit controls the generation of interrupt request signals (intiic0). an i 2 c interrupt request is generated following either of two triggers. falling of eighth or ninth clock of the serial clock (set by wtim0 bit note ) interrupt request generated when a stop condition is detected (set by spie0 bit note ) note wtim0 bit: bit 3 of iic control register 0 (iicc0) spie0 bit: bit 4 of iic control register 0 (iicc0) (8) serial clock controller in master mode, this circuit generates the clock output via the scl0 pin from a sampling clock. (9) serial clock wait controller this circuit controls the wait timing. (10) ack output circuit, stop condition detector, start condition detector, and ack detector these circuits are used to output and detect various control signals. (11) data hold time correction circuit this circuit generates the hold time for data corresponding to the falling edge of the serial clock.
345 chapter 18 serial interface iic0 ( pd780024ay, 780034ay subseries only) user s manual u14046ej3v0ud 18.3 registers to control serial interface iic0 serial interface iic0 is controlled by the following five registers. iic control register 0 (iicc0) iic status register 0 (iics0) iic transfer clock select register 0 (iiccl0) port mode register 3 (pm3) port 3 (p3) (1) iic control register 0 (iicc0) this register is used to enable/stop i 2 c operations, set wait timing, and set other i 2 c operations. iicc0 is set by a 1-bit or 8-bit memory manipulation instruction. reset input clears iicc0 to 00h.
346 chapter 18 serial interface iic0 ( pd780024ay, 780034ay subseries only) user s manual u14046ej3v0ud figure 18-5. format of iic control register 0 (iicc0) (1/4) address: ffa8h after reset: 00h r/w symbol <7> <6> <5> <4> <3> <2> <1> <0> iicc0 iice0 lrel0 wrel0 spie0 wtim0 acke0 stt0 spt0 iice0 i 2 c operation enable 0 stop operation. reset iic status register 0 (iics0). stop internal operation. 1 enable operation. condition for clearing (iice0 = 0) condition for setting (iice0 = 1) cleared by instruction set by instruction when reset is input lrel0 exit from communications 0 normal operation 1 this exits from the current communications operation and sets standby mode. this setting is automatically cleared after being executed. its uses include cases in which a locally irrelevant extension code has been received. the scl0 and sda0 lines go into the high impedance state. the following flags of iic status register 0 (iics0) and iic control register 0 (iicc0) are cleared. std0 ackd0 trc0 coi0 exc0 msts0 stt0 spt0 the standby mode following exit from communications remains in effect until the following communications entry conditions are met. after a stop condition is detected, restart is in master mode. an address match or extension code reception occurs after the start condition. condition for clearing (lrel0 = 0) note condition for setting (lrel0 = 1) automatically cleared after execution set by instruction when reset is input wrel0 cancel wait 0 do not cancel wait 1 cancel wait. this setting is automatically cleared after wait is canceled. when wrel0 is set (wait canceled) during the wait period at the ninth clock pulse in the transmission status (trc0 = 1), the sda0 line goes into the high impedance state (trc0 = 0). condition for clearing (wrel0 = 0) note condition for setting (wrel0 = 1) automatically cleared after execution set by instruction when reset is input spie0 enable/disable generation of interrupt request when stop condition is detected 0 disable 1 enable condition for clearing (spie0 = 0) note condition for setting (spie0 = 1) cleared by instruction set by instruction when reset is input note this flag s signal is invalid when iice0 = 0.
347 chapter 18 serial interface iic0 ( pd780024ay, 780034ay subseries only) user s manual u14046ej3v0ud figure 18-5. format of iic control register 0 (iicc0) (2/4) wtim0 control of wait and interrupt request generation 0 interrupt request is generated at the eighth clock s falling edge. master mode: after output of eight clocks, clock output is set to low level and wait is set. slave mode: after input of eight clocks, the clock is set to low level and wait is set for master device. 1 interrupt request is generated at the ninth clock s falling edge. master mode: after output of nine clocks, clock output is set to low level and wait is set. slave mode: after input of nine clocks, the clock is set to low level and wait is set for master device . this bit s setting is invalid during an address transfer and is valid after the transfer is completed. when in master mode, a wait is inserted at the falling edge of the ninth clock during address transfers. for a slave device that has received a local address, a wait is inserted at the falling edge of the ninth clock after an ack signal is issued. when the slave device has received an extension code, a wait is inserted at the falling edge of the eighth clock. condition for clearing (wtim0 = 0) note condition for setting (wtim0 = 1) cleared by instruction set by instruction when reset is input acke0 acknowledgment control 0 disable acknowledgment. 1 enable acknowledgment. during the ninth clock period, the sda0 line is set to low level. however, the ack is invalid during address transfers and is valid when exc0 = 1. condition for clearing (acke0 = 0) note condition for setting (acke0 = 1) cleared by instruction set by instruction when reset is input note this flag s signal is invalid when iice0 = 0.
348 chapter 18 serial interface iic0 ( pd780024ay, 780034ay subseries only) user s manual u14046ej3v0ud figure 18-5. format of iic control register 0 (iicc0) (3/4) stt0 start condition trigger 0 do not generate a start condition. 1 when bus is released (during stop mode): generate a start condition (for starting as master). the sda0 line is changed from high level to low level and then the start condition is generated. next, after the rated amount of time has elapsed, scl0 is changed to low level. when bus is not used: this trigger functions as a start condition reservation flag. when set, it releases the bus and then automatically generates a start condition. wait status (during master mode): generate a restart condition after wait is released. cautions concerning set timing for master reception: cannot be set during transfer. can be set only in the waiting period when acke0 has been set to 0 and slave has been notified of final reception. for master transmission: a start condition may not be generated normally during the ack period. therefore, set it during the waiting period. cannot be set at the same time as spt0 condition for clearing (stt0 = 0) condition for setting (stt0 = 1) cleared by loss in arbitration set by instruction cleared after start condition is generated by master device cleared by lrel0 = 1 (exit from communications) when iice0 = 0 (operation stop) when reset is input remark bit 1 (stt0) is 0 when read after data has been set.
349 chapter 18 serial interface iic0 ( pd780024ay, 780034ay subseries only) user s manual u14046ej3v0ud figure 18-5. format of iic control register 0 (iicc0) (4/4) spt0 stop condition trigger 0 stop condition is not generated. 1 stop condition is generated (termination of master device s transfer). after the sda0 line goes to low level, either set the scl0 line to high level or wait until it goes to high level. next, after the rated amount of time has elapsed, the sda0 line changes from low level to high level and a stop condition is generated. cautions concerning set timing for master reception: cannot be set during transfer. can be set only in the waiting period when acke0 has been set to 0 and slave has been notified of final reception. for master transmission: a stop condition cannot be generated normally during the ack0 period. therefore, set it during the waiting period. cannot be set at the same time as stt0. spt0 can be set only when in master mode. note when wtim0 has been set to 0, if spt0 is set during the wait period that follows output of eight clocks, note that a stop condition will be generated during the high level period of the ninth clock. when a ninth clock must be output, wtim0 should be changed from 0 to 1 during the wait period following output of eight clocks, and spt0 should be set during the wait period that follows output of the ninth clock. condition for clearing (spt0 = 0) condition for setting (spt0 = 1) cleared by loss in arbitration set by instruction automatically cleared after stop condition is detected cleared by lrel0 = 1 (exit from communications) when iice0 = 0 (operation stop) when reset is input note set spt0 only in master mode. however, spt0 must be set and a stop condition generated before the first stop condition is detected following the switch to the operation enabled status. for details, see 18.5.14 other cautions . caution when bit 3 (trc0) of iic status register 0 (iics0) is set to 1, wrel0 is set during the ninth clock and wait is canceled, after which trc0 is cleared and the sda0 line is set to high impedance. remark bit 0 (spt0) becomes 0 when it is read after data setting.
350 chapter 18 serial interface iic0 ( pd780024ay, 780034ay subseries only) user s manual u14046ej3v0ud (2) iic status register 0 (iics0) this register indicates the status of i 2 c. iics0 is read by a 1-bit or 8-bit memory manipulation instruction. reset input clears iics0 to 00h. figure 18-6. format of iic status register 0 (iics0) (1/3) address: ffa9h after reset: 00h r symbol <7> <6> <5> <4> <3> <2> <1> <0> iics0 msts0 ald0 exc0 coi0 trc0 ackd0 std0 spd0 msts0 master device status 0 slave device status or communication standby status 1 master device communication status condition for clearing (msts0 = 0) condition for setting (msts0 = 1) when a stop condition is detected when a start condition is generated when ald0 = 1 (arbitration loss) cleared by lrel0 = 1 (exit from communications) when iice0 changes from 1 to 0 (operation stop) when reset is input ald0 detection of arbitration loss 0 this status means either that there was no arbitration or that the arbitration result was a win . 1 this status indicates the arbitration result was a loss . msts0 is cleared. condition for clearing (ald0 = 0) condition for setting (ald0 = 1) automatically cleared after iics0 is read note when the arbitration result is a loss . when iice0 changes from 1 to 0 (operation stop) when reset is input exc0 detection of extension code reception 0 extension code was not received. 1 extension code was received. condition for clearing (exc0 = 0) condition for setting (exc0 = 1) when a start condition is detected when the higher 4 bits of the received when a stop condition is detected address data are either 0000 or 1111 cleared by lrel0 = 1 (exit from communications) (set at the rising edge of the eighth clock). when iice0 changes from 1 to 0 (operation stop) when reset is input note this register is also cleared when a bit manipulation instruction is executed for bits other than iics0. remark lrel0: bit 6 of iic control register 0 (iicc0) iice0: bit 7 of iic control register 0 (iicc0)
351 chapter 18 serial interface iic0 ( pd780024ay, 780034ay subseries only) user s manual u14046ej3v0ud figure 18-6. format of iic status register 0 (iics0) (2/3) coi0 detection of matching addresses 0 addresses do not match. 1 addresses match. condition for clearing (coi0 = 0) condition for setting (coi0 = 1) when a start condition is detected when the received address matches the local when a stop condition is detected address (slave address register 0 (sva0)) cleared by lrel0 = 1 (exit from communications) (set at the rising edge of the eighth clock). when iice0 changes from 1 to 0 (operation stop) when reset is input trc0 detection of transmit/receive status 0 receive status (other than transmit status). the sda0 line is set to high impedance. 1 transmit status. the value in the so0 latch is enabled for output to the sda0 line (valid starting at the falling edge of the first byte s ninth clock). condition for clearing (trc0 = 0) condition for setting (trc0 = 1) when a stop condition is detected when a start condition is generated cleared by lrel0 = 1 (exit from communications) when iice0 changes from 1 to 0 (operation stop) when 1 is input to the first byte s lsb cleared by wrel0 = 1 note (wait cancel) (transfer direction specification bit) when ald0 changes from 0 to 1 (arbitration loss) when reset is input when 1 is output to the first byte s lsb (transfer direction specification bit) when a start condition is detected when 0 is input to the first byte s lsb (transfer direction specification bit) note if the wait status is cleared by setting bit 5 (wrel0) of iic control register 0 (iicc0) to 1 at the ninth clock when bit 3 (trc0) of iic status register 0 (iics0) is 1, trc0 is cleared, and the sda0 line goes into a high-impedance state. remark lrel0: bit 6 of iic control register 0 (iicc0) iice0: bit 7 of iic control register 0 (iicc0)
352 chapter 18 serial interface iic0 ( pd780024ay, 780034ay subseries only) user s manual u14046ej3v0ud figure 18-6. format of iic status register 0 (iics0) (3/3) ackd0 detection of ack 0 ack was not detected. 1 ack was detected. condition for clearing (ackd0 = 0) condition for setting (ackd0 = 1) when a stop condition is detected after the sda0 line is set to low level at the at the rising edge of the next byte s first clock rising edge of the scl0 s ninth clock cleared by lrel0 = 1 (exit from communications) when iice0 changes from 1 to 0 (operation stop) when reset is input std0 detection of start condition 0 start condition was not detected. 1 start condition was detected. this indicates that the address transfer period is in effect. condition for clearing (std0 = 0) condition for setting (std0 = 1) when a stop condition is detected when a start condition is detected at the rising edge of the next byte s first clock following address transfer cleared by lrel0 = 1 (exit from communications) when iice0 changes from 1 to 0 (operation stop) when reset is input spd0 detection of stop condition 0 stop condition was not detected. 1 stop condition was detected. the master device s communication was terminated and the bus was released. condition for clearing (spd0 = 0) condition for setting (spd0 = 1) at the rising edge of the address transfer byte s when a stop condition is detected first clock following setting of this bit and detection of a start condition when iice0 changes from 1 to 0 (operation stop) when reset is input remark lrel0: bit 6 of iic control register 0 (iicc0) iice0: bit 7 of iic control register 0 (iicc0)
353 chapter 18 serial interface iic0 ( pd780024ay, 780034ay subseries only) user s manual u14046ej3v0ud (3) iic transfer clock select register 0 (iiccl0) this register is used to set the transfer clock for the i 2 c bus. iiccl0 is set by a 1-bit or 8-bit memory manipulation instruction. reset input clears iiccl0 to 00h. figure 18-7. format of iic transfer clock select register 0 (iiccl0) (1/2) address: ffaah after reset: 00h r/w note symbol 7 6 <5> <4> 3210 iiccl0 0 0 cld0 dad0 smc0 dfc0 0 cl00 cld0 detection of scl0 line level (valid only when iice0 = 1) 0 scl0 line was detected at low level. 1 scl0 line was detected at high level. condition for clearing (cld0 = 0) condition for setting (cld0 = 1) when the scl0 line is at low level when the scl0 line is at high level when iice0 = 0 (operation stop) when reset is input dad0 detection of sda0 line level (valid only when iice0 = 1) 0 sda0 line was detected at low level. 1 sda0 line was detected at high level. condition for clearing (dad0 = 0) condition for setting (dad0 = 1) when the sda0 line is at low level when the sda0 line is at high level when iice0 = 0 (operation stop) when reset is input smc0 operation mode switching 0 operation in standard mode 1 operation in high-speed mode condition for clearing (smc0 = 0) condition for setting (smc0 = 1) cleared by instruction set by instruction when reset is input note bits 4 and 5 are read-only bits. remark iice0: bit 7 of iic control register 0 (iicc0)
354 chapter 18 serial interface iic0 ( pd780024ay, 780034ay subseries only) user s manual u14046ej3v0ud figure 18-7. format of iic transfer clock select register 0 (iiccl0) (2/2) dfc0 control of digital filter operation note 1 0 digital filter off 1 digital filter on cl00 selection of transfer rate standard mode high-speed mode f x = 8.38 mhz f x = 8.38 mhz 0f x /44 190.4 khz note 2 f x /24 350 khz 1f x /86 97.5 khz notes 1. the digital filter can be used when in high-speed mode. the response time is slower when the digital filter is used. 2. the transfer rate in standard mode must not be set when f x is more than 100 khz. caution stop serial transfer once before rewriting cl00 to other than the same value. remarks 1. f x : main system clock oscillation frequency 2. the transfer clock does not change in the high-speed mode even if dfc0 is turned on and off. (4) port mode register 3 (pm3) pm3 is a register that sets the input/output of port 3 in 1-bit units. to use the p32/sda0 pin as serial data i/o and the p33/scl0 pin as clock i/o, clear pm32, pm33, and the output latches of p32 and p33 to 0. pm3 is set by a 1-bit or 8-bit memory manipulation instruction. reset input sets pm3 to ffh. figure 18-8. format of port mode register 3 (pm3) address: ff23fh after reset: ffh r/w symbol 76543210 pm3 1 pm36 pm35 pm34 pm33 pm32 pm31 pm30 pm3n i/o mode selection of p3n pin (n = 0 to 6) 0 output mode (output buffer on) 1 input mode (output buffer off)
355 chapter 18 serial interface iic0 ( pd780024ay, 780034ay subseries only) user s manual u14046ej3v0ud 18.4 i 2 c bus mode functions 18.4.1 pin configuration the serial clock pin (scl0) and serial data bus pin (sda0) are configured as follows. (1) scl0 this pin is used for serial clock input and output. this pin is an n-ch open-drain output for both master and slave devices. input is schmitt input. (2) sda0 this pin is used for serial data input and output. this pin is an n-ch open-drain output for both master and slave devices. input is schmitt input. since outputs from the serial clock line and the serial data bus line are n-ch open drain outputs, an external pull- up resistor is required. figure 18-9. pin configuration diagram v dd0 v ss0 v ss0 v ss0 v ss0 scl0 sda0 scl0 sda0 v dd0 clock output master device (clock input) data output data input (clock output) clock input data output data input slave device
356 chapter 18 serial interface iic0 ( pd780024ay, 780034ay subseries only) user s manual u14046ej3v0ud 18.5 i 2 c bus definitions and control methods the following section describes the i 2 c bus s serial data communication format and the signals used by the i 2 c bus. figure 18-10 shows the transfer timing for the start condition , data , and stop condition output via the i 2 c bus s serial data bus. figure 18-10. i 2 c bus serial data transfer timing the master device outputs the start condition, slave address, and stop condition. the acknowledge signal (ack) can be output by either the master or slave device (normally, it is output by the device that receives 8-bit data). the serial clock (scl0) is continuously output by the master device. however, in the slave device, the scl0 s low level period can be extended and a wait can be inserted. 18.5.1 start conditions a start condition is met when the scl0 pin is at high level and the sda0 pin changes from high level to low level. the start conditions for the scl0 pin and sda0 pin are signals that the master device outputs to the slave device when starting a serial transfer. when the device is used as a slave, start conditions can be detected. figure 18-11. start conditions a start condition is output when bit 1 (stt0) of iic control register 0 (iicc0) is set (to 1) after a stop condition has been detected (spd0: bit 0 = 1 in iic status register 0 (iics0)). when a start condition is detected, bit 1 (std0) of iics0 is set (to 1). 1-7 8 9 1-7 8 9 1-7 8 9 scl0 sda0 start condition address r/w ack data data stop condition ack ack h scl0 sda0
357 chapter 18 serial interface iic0 ( pd780024ay, 780034ay subseries only) user s manual u14046ej3v0ud 18.5.2 addresses the address is defined by the 7 bits of data that follow the start condition. an address is a 7-bit data segment that is output in order to select one of the slave devices that are connected to the master device via the bus lines. therefore, each slave device connected via the bus lines must have a unique address. the slave devices include hardware that detects the start condition and checks whether or not the 7-bit address data matches the data values stored in slave address register 0 (sva0). if the address data matches the sva0 values, the slave device is selected and communicates with the master device until the master device transmits a start condition or stop condition. figure 18-12. address note intiic0 is not issued if data other than a local address or extension code is received during slave device operation. the slave address and the eighth bit, which specifies the transfer direction as described in 18.5.3 transfer direction specification below, are together written to iic shift register 0 (iic0) and are then output. received addresses are written to iic0. the slave address is assigned to the higher 7 bits of iic0. 18.5.3 transfer direction specification in addition to the 7-bit address data, the master device sends 1 bit that specifies the transfer direction. when this transfer direction specification bit has a value of 0 , it indicates that the master device is transmitting data to a slave device. when the transfer direction specification bit has a value of 1 , it indicates that the master device is receiving data from a slave device. figure 18-13. transfer direction specification note intiic0 is not issued if data other than a local address or extension code is received during slave device operation. address scl0 1 sda0 intiic0 note 23456789 a6 a5 a4 a3 a2 a1 a0 r/w scl0 1 sda0 intiic0 23456789 a6 a5 a4 a3 a2 a1 a0 r/w transfer direction specification note
358 chapter 18 serial interface iic0 ( pd780024ay, 780034ay subseries only) user s manual u14046ej3v0ud 18.5.4 acknowledge (ack) signal the acknowledge (ack) signal is used by the transmitting and receiving devices to confirm serial data reception. the receiving device returns one ack signal for each 8 bits of data it receives. the transmitting device normally receives an ack signal after transmitting 8 bits of data. however, when the master device is the receiving device, it does not output an ack signal after receiving the final data to be transmitted. the transmitting device detects whether or not an ack signal is returned after it transmits 8 bits of data. when an ack signal is returned, the reception is judged as normal and processing continues. if the slave device does not return an ack signal, the master device outputs either a stop condition or a restart condition and then stops the current transmission. failure to return an ack signal may be caused by the following two factors. (a) reception was not performed normally. (b) the final data was received. when the receiving device sets the sda0 line to low level during the ninth clock, the ack signal becomes active (normal receive response). when bit 2 (acke0) of iic control register 0 (iicc0) is set to 1, automatic ack signal generation is enabled. transmission of the eighth bit following the 7 address data bits causes bit 3 (trc0) of iic status register 0 (iics0) to be set. when this trc0 bit s value is 0 , it indicates receive mode. therefore, acke0 should be set to 1. when the slave device is receiving (when trc0 = 0), if the slave device does not need to receive any more data after receiving several bytes, setting acke0 to 0 will prevent the master device from starting transmission of the subsequent data. similarly, when the master device is receiving (when trc0 = 0) and the subsequent data is not needed and when either a restart condition or a stop condition should therefore be output, setting acke0 to 0 will prevent the ack signal from being returned. this prevents the msb data from being output via the sda0 line (i.e., stops transmission) during transmission from the slave device. figure 18-14. ack signal when the local address is received, an ack signal is automatically output in sync with the falling edge of the scl0 s eighth clock regardless of the acke0 value. no ack signal is output if the received address is not a local address. the ack signal output method during data reception is based on the wait timing setting, as described below. when 8-clock wait is selected: ack signal is output when acke0 is set to 1 before wait cancellation. (wtim0 = 0) when 9-clock wait is selected: ack signal is automatically output at the falling edge of the scl0 s eighth clock (wtim0 = 1) if acke0 has already been set to 1. scl0 1 sda0 23456789 a6 a5 a4 a3 a2 a1 a0 r/w ack
359 chapter 18 serial interface iic0 ( pd780024ay, 780034ay subseries only) user s manual u14046ej3v0ud 18.5.5 stop condition when the scl0 pin is at high level, changing the sda0 pin from low level to high level generates a stop condition. a stop condition is a signal that the master device outputs to the slave device when serial transfer has been completed. when the device is used as a slave, stop conditions can be detected. figure 18-15. stop condition a stop condition is generated when bit 0 (spt0) of iic control register 0 (iicc0) is set (to 1). when the stop condition is detected, bit 0 (spd0) of iic status register 0 (iics0) is set (to 1) and intiic0 is generated when bit 4 (spie0) of iicc0 is set (to 1). h scl0 sda0
360 chapter 18 serial interface iic0 ( pd780024ay, 780034ay subseries only) user s manual u14046ej3v0ud 18.5.6 wait signal (wait) the wait signal (wait) is used to notify the communication partner that a device (master or slave) is preparing to transmit or receive data (i.e., is in a wait state). setting the scl0 pin to low level notifies the communication partner of the wait status. when wait status has been canceled for both the master and slave devices, the next data transfer can begin. figure 18-16. wait signal (1/2) (1) when master device has a nine-clock wait and slave device has an eight-clock wait (master transmits, slave receives, and acke0 = 1) iic0 scl0 iic0 scl0 acke0 scl0 sda0 6789 123 master returns to high impedance but slave is in wait state (low level). wait after output of ninth clock iic0 data write (cancel wait) wait after output of eighth clock wait signal from slave wait signal from master ffh is written to iic0 or wrel0 is set to 1 678 9 123 d2 d1 d0 d7 d6 d5 ack h master slave transfer lines
361 chapter 18 serial interface iic0 ( pd780024ay, 780034ay subseries only) user s manual u14046ej3v0ud figure 18-16. wait signal (2/2) (2) when master and slave devices both have a nine-clock wait (master transmits, slave receives, and acke0 = 1) remark acke0: bit 2 of iic control register 0 (iicc0) wrel0: bit 5 of iic control register 0 (iicc0) a wait may be automatically generated depending on the setting of bit 3 (wtim0) of iic control register 0 (iicc0). normally, the receiving side cancels the wait status when bit 5 (wrel0) is set to 1 or when ffh is written to iic shift register 0 (iic0), and the transmitting side cancels the wait status when data is written to iic0. the master device can also cancel the wait status via either of the following methods. by setting bit 1 (stt0) of iicc0 to 1 by setting bit 0 (spt0) of iicc0 to 1 iic0 scl0 iic0 scl0 acke0 scl0 sda0 h 6789 1 23 master and slave both wait after output of ninth clock wait signal from master and slave wait signal from slave iic0 data write (cancel wait) ffh is written to iic0 or wrel0 is set to 1 6789 123 d2 d1 d0 ack d7 d6 d5 output according to previously set acke0 value master slave transfer lines
362 chapter 18 serial interface iic0 ( pd780024ay, 780034ay subseries only) user s manual u14046ej3v0ud 18.5.7 interrupt request (intiic0) generation timing and wait control the setting of bit 3 (wtim0) of iic control register 0 (iicc0) determines the timing by which intiic0 is generated and the corresponding wait control, as shown in table 18-2. table 18-2. intiic0 timing and wait control wtim0 during slave device operation during master device operation address data reception data transmission address data reception data transmission 09 notes 1, 2 8 note 2 8 note 2 988 19 notes 1, 2 9 note 2 9 note 2 999 notes 1. the slave device s intiic0 signal and wait period occurs at the falling edge of the ninth clock only when there is a match with the address set to slave address register 0 (sva0). at this point, ack is output regardless of the value set to iicc0 s bit 2 (acke0). for a slave device that has received an extension code, intiic0 occurs at the falling edge of the eighth clock. however, if the address does not match after restart, intiic0 is generated at the falling of the 9th clock, but wait does not occur. 2. if the received address does not match the contents of slave address register 0 (sva0) and extension code is not received, neither intiic0 nor a wait occurs. remark the numbers in the table indicate the number of the serial clock s clock signals. interrupt requests and wait control are both synchronized with the falling edge of these clock signals. (1) during address transmission/reception slave device operation: interrupt and wait timing are determined depending on the conditions described in notes 1 and 2 above, regardless of the wtim0 bit. master device operation: interrupt and wait timing occur at the falling edge of the ninth clock regardless of the wtim0 bit. (2) during data reception master/slave device operation: interrupt and wait timing are determined according to the wtim0 bit. (3) during data transmission master/slave device operation: interrupt and wait timing are determined according to the wtim0 bit. (4) wait cancellation method the four wait cancellation methods are as follows. by setting bit 5 (wrel0) of iic control register 0 (iicc0) to 1 by writing to the iic shift register 0 (iic0) by setting a start condition (setting bit 1 (stt0) of iicc0 to 1) note by setting a stop condition (setting bit 0 (spt0) of iicc0 to 1) note note master only. when an 8-clock wait has been selected (wtim0 = 0), the output level of ack must be determined prior to wait cancellation.
363 chapter 18 serial interface iic0 ( pd780024ay, 780034ay subseries only) user s manual u14046ej3v0ud (5) stop condition detection intiic0 is generated when a stop condition is detected. 18.5.8 address match detection method in i 2 c bus mode, the master device can select a particular slave device by transmitting the corresponding slave address. address match can be detected automatically by hardware. an interrupt request (intiic0) occurs when a local address has been set to slave address register 0 (sva0) and when the address set to sva0 matches the slave address sent by the master device, or when an extension code has been received. 18.5.9 error detection in i 2 c bus mode, the status of the serial data bus (sda0) during data transmission is captured by iic shift register 0 (iic0) of the transmitting device, so the iic0 data prior to transmission can be compared with the transmitted iic0 data to enable detection of transmission errors. a transmission error is judged as having occurred when the compared data values do not match. 18.5.10 extension code (1) when the higher 4 bits of the receive address are either 0000 or 1111 , the extension code flag (exc0) is set for extension code reception and an interrupt request (intiic0) is issued at the falling edge of the eighth clock. the local address stored in slave address register 0 (sva0) is not affected. (2) if 111110 is set to sva0 by a 10-bit address transfer and 111110 is transferred from the master device, the results are as follows. note that intiic0 occurs at the falling edge of the eighth clock. higher four bits of data match: exc0 = 1 note seven bits of data match: coi0 = 1 note note exc0: bit 5 of iic status register 0 (iics0) coi0: bit 4 of iic status register 0 (iics0) (3) since the processing after the interrupt request occurs differs according to the data that follows the extension code, such processing is performed by software. for example, after the extension code is received, if you do not wish to operate the target device as a slave device, you can set bit 6 (lrel0) of iic control register 0 (iicc0) to 1 to set the standby mode for the next communication operation. table 18-3. extension code bit definitions slave address r/w bit description 0000 000 0 general call address 0000 000 1 start byte 0000 001 cbus address 0000 010 address that is reserved for different bus format 1111 0 10-bit slave address specification
364 chapter 18 serial interface iic0 ( pd780024ay, 780034ay subseries only) user s manual u14046ej3v0ud 18.5.11 arbitration when several master devices simultaneously output a start condition (when stt0 is set to 1 before std0 is set to 1 note ), communication among the master devices is performed as the number of clocks are adjusted until the data differs. this kind of operation is called arbitration. when one of the master devices loses in arbitration, an arbitration loss flag (ald0) in iic status register 0 (iics0) is set (1) via the timing by which the arbitration loss occurred, and the scl0 and sda0 lines are both set to high impedance, which releases the bus. the arbitration loss is detected based on the timing of the next interrupt request (the eighth or ninth clock, when a stop condition is detected, etc.) and the ald0 = 1 setting that has been made by software. for details of interrupt request timing, see 18.5.16 timing of i 2 c interrupt request (intiic0) occurrence . note std0: bit 1 of iic status register 0 (iics0) stt0: bit 1 of iic control register 0 (iicc0) figure 18-17. arbitration timing example master 1 master 2 transfer lines scl0 sda0 scl0 sda0 scl0 sda0 master 1 loses arbitration hi-z hi-z
365 chapter 18 serial interface iic0 ( pd780024ay, 780034ay subseries only) user s manual u14046ej3v0ud table 18-4. status during arbitration and interrupt request generation timing status during arbitration interrupt request generation timing during address transmission at falling edge of eighth or ninth clock following byte transfer note 1 read/write data after address transmission during extension code transmission read/write data after extension code transmission during data transmission during ack signal transfer period after data transmission when restart condition is detected during data transfer when stop condition is detected during data transfer when stop condition is output (when spie0 = 1) note 2 when data is at low level while attempting to output a at falling edge of eighth or ninth clock following byte transfer note 1 restart condition when stop condition is detected while attempting to when stop condition is output (when spie0 = 1) note 2 output a restart condition when data is at low level while attempting to output a at falling edge of eighth or ninth clock following byte transfer note 1 stop condition when scl0 is at low level while attempting to output a restart condition notes 1. when wtim0 (bit 3 of iic control register 0 (iicc0)) = 1, an interrupt request occurs at the falling edge of the ninth clock. when wtim0 = 0 and the extension code s slave address is received, an interrupt request occurs at the falling edge of the eighth clock. 2. when there is a chance that arbitration will occur, set spie0 = 1 for master device operation. remark spie0: bit 4 of iic control register 0 (iicc0) 18.5.12 wake-up function the i 2 c bus slave function is a function that generates an interrupt request (intiic0) when a local address and extension code have been received. this function makes processing more efficient by preventing unnecessary interrupt requests from occurring when addresses do not match. when a start condition is detected, wake-up standby mode is set. this wake-up standby mode is in effect while addresses are transmitted due to the possibility that an arbitration loss may change the master device (which has output a start condition) to a slave device. however, when a stop condition is detected, bit 4 (spie0) of iic control register 0 (iicc0) is set regardless of the wake-up function, and this determines whether interrupt requests are enabled or disabled.
366 chapter 18 serial interface iic0 ( pd780024ay, 780034ay subseries only) user s manual u14046ej3v0ud 18.5.13 communication reservation to start master device communications when not currently using a bus, a communication reservation can be made to enable transmission of a start condition when the bus is released. there are two modes under which the bus is not used. when arbitration results in neither master nor slave operation when an extension code is received and slave operation is disabled (ack is not returned and the bus was released when bit 6 (lrel0) of iic control register 0 (iicc0) was set to 1). if bit 1 (stt0) of iicc0 is set (1) while the bus is not used (after a stop condition is detected), a start condition is automatically generated and wait status is set. when the bus release is detected (when a stop condition is detected), writing to iic shift register 0 (iic0) causes the master address transfer to start. at this point, bit 4 (spie0) of iicc0 should be set (1). when stt0 has been set (1), the operation mode (as start condition or as communication reservation) is determined according to the bus status. if the bus has been released ........................................... a start condition is generated if the bus has not been released (standby mode) .......... communication reservation check whether the communication reservation operates or not by using msts0 (bit 7 of iic status register 0 (iics0)) after sst0 is set and the wait time elapses. the wait periods, which should be set via software, are listed in table 18-5. these wait periods can be set via the settings for bits 3 and 0 (smc0 and cl00) in iic transfer clock select register 0 (iiccl0). table 18-5. wait periods smc0 cl00 wait period 0 0 26 clocks 0 1 46 clocks 1 0 16 clocks 11 figure 18-18 shows the communication reservation timing.
367 chapter 18 serial interface iic0 ( pd780024ay, 780034ay subseries only) user s manual u14046ej3v0ud figure 18-18. communication reservation timing remark iic0: iic shift register 0 stt0: bit 1 of iic control register 0 (iicc0) std0: bit 1 of iic status register 0 (iics0) spd0: bit 0 of iic status register 0 (iics0) communication reservations are accepted via the following timing. after bit 1 (std0) of iic status register 0 (iics0) is set to 1, a communication reservation can be made by setting bit 1 (stt0) of iic control register 0 (iicc0) to 1 before a stop condition is detected. figure 18-19. timing for accepting communication reservations figure 18-20 shows the communication reservation protocol. 2 1 3456 2 1 3456 789 scl0 sda0 program processing hardware processing write to iic0 set spd0 and intiic0 stt0 = 1 communication reservation set std0 output by master with bus mastership scl0 sda0 std0 spd0 standby mode
368 chapter 18 serial interface iic0 ( pd780024ay, 780034ay subseries only) user s manual u14046ej3v0ud figure 18-20. communication reservation protocol note the communication reservation operation executes a write to iic shift register 0 (iic0) when a stop condition interrupt request occurs. remark stt0: bit 1 of iic control register 0 (iicc0) msts0: bit 7 of iic status register 0 (iics0) iic0: iic shift register 0 18.5.14 other cautions after a reset, when changing from a mode in which no stop condition has been detected (the bus has not been released) to a master device communication mode, first generate a stop condition to release the bus, then perform master device communication. when using multiple masters, it is not possible to perform master device communication when the bus has not been released (when a stop condition has not been detected). use the following sequence for generating a stop condition. (a) set iic transfer clock select register 0 (iiccl0). (b) set (1) bit 7 (iice0) of iic control register 0 (iicc0). (c) set (1) bit 0 (spt0) of iicc0. di set1 stt0 define communication reservation wait cancel communication reservation no yes mov iic0, # h ei msts0 = 0? (communication reservation) note (generate start condition) sets stt0 flag (communication reservation) secures wait period set by software (see table 18-5 ) confirmation of communication reservation clear user flag iic0 write operation defines that communication reservation is in effect (defines and sets user flag to any part of ram)
369 chapter 18 serial interface iic0 ( pd780024ay, 780034ay subseries only) user s manual u14046ej3v0ud 18.5.15 communication operations (1) master operations the procedure of controlling slave eeprom tm using the pd780024ay and 780034ay subseries as the master of the i 2 c bus is as follows. figure 18-21. master operation flowchart (1/5) issue start condition. stt0 = 1 set transfer clock. iiccl0 h set port (mode and data). pm32, pm33 1, p32, p33 0 set port. pm32, pm33 0 set iic control register 0. iice0 = wtim0 = 1 issue stop condition. spt0 = 1 set interrupt. iicif0, iicmk0 0 spd0 = 1? a start no yes first perform initialization to use i 2 c. set the port that functions alternately as the pins to be used. first set the port in the input mode, and clear the output latch to 0. specify the operation mode, turn on/off the digital filter, and specify the transfer rate. set a 9-clock wait and enable operation. set the port in the output mode to enable output of i 2 c. clear the interrupt request of i 2 c. clear the mask to enable the interrupt when using the interrupt. issue the stop condition before starting operation, and release the bus. wait until the bus is released. if the stop condition is detected, the bus is released and can be used. declare use of the bus by issuing the start condition. if the stop condition cannot be detected, the chances are the connected pin is driving the bus low. in this case, refer to remark .
370 chapter 18 serial interface iic0 ( pd780024ay, 780034ay subseries only) user s manual u14046ej3v0ud figure 18-21. master operation flowchart (2/5) ackd0 = 1? transmit eeprom higher address. iic0 eeprom higher address transmit eeprom lower address. iic0 eeprom lower address transfer slave address. iic0 address, r/w (0) intiic0 = 1? clear intiic0. clear intiic0. b ackd0 = 1? end (no slave) no no no end (no acknowledgment) a std0 = 1? no yes yes yes yes yes intiic0 = 1? no wait until the start condition is detected and the bus is ready. specify writing and transfer the address of the slave (eeprom). wait until transfer is completed. clear intiic0 to poll intiic0 without using an interrupt. if ack is not sent, it means that the specified slave does not exist. end processing. if a slave does exist, divide the address of eeprom (2 bytes) into two, and start transmitting the address from the higher byte. each time transmission is completed, check ack. transmit the lower address.
371 chapter 18 serial interface iic0 ( pd780024ay, 780034ay subseries only) user s manual u14046ej3v0ud figure 18-21. master operation flowchart (3/5) ackd0 = 1? transmission? trc0 = 1? transmit write data. iic0 data prepare write data. intiic0 = 1? clear intiic0. clear intiic0. b reception c ackd0 = 1? transfer end? end end (no acknowledgment) set error flag. no no no no no intiic0 = 1? yes yes yes yes yes yes when writing data to eeprom, continue writing data. when reading data from eeprom, start reception processing. prepare data to be written to eeprom, and transmit it to eeprom. each time data has been transmitted, the slave returns ack. if any error occurs before transmission of the necessary data is completed, ack may not be returned. in this case, end transfer. in the case of an error, set the error flag as shown on the left, and release the bus.
372 chapter 18 serial interface iic0 ( pd780024ay, 780034ay subseries only) user s manual u14046ej3v0ud figure 18-21. master operation flowchart (4/5) transfer slave address. iic0 address, r/w (1) issue stop condition. spt0 = 1 intiic0 = 1? clear intiic0. d reception ackd0 = 1? end no issue start condition. stt0 = 1 std0 = 1? no no end (no acknowledgment) when transmission is completed, issue the stop condition to notify the slave of completion of transmission. for reception, the data transfer direction must be changed. issue the start condition again and redo (restart) communication. because the master receives data this time, set the r/w bit to 1 and transmit an address. c spd0 = 1? no yes yes yes yes
373 chapter 18 serial interface iic0 ( pd780024ay, 780034ay subseries only) user s manual u14046ej3v0ud figure 18-21. master operation flowchart (5/5) re-set iic control register 0. acke0 = 1, wtim0 = 0 issue stop condition. spt0 = 1 re-set iic control register 0. acke0 = 0, wrel0 = wtim0 = 1 spd0 = 1? d end no remaining data? yes start data reception. iic0 0ffh intiic0 = 1? no no set so that ack is automatically returned after an 8-clock wait (set acke0 so that ack is returned except when the last data is received. specify an 8-clock wait so that automatic returning of ack can be cleared when the last data is received). write dummy data to iic0 and start reception (reception can also be started when wrel0 = 1). reception is completed when intiic0 occurs. save the received data to a buffer. when reception of data is completed, disable automatic returning of ack, set a 9- clock wait, cancel wait in the ack cycle, and stop at the 9th clock. as a result, ack is not returned to the slave. this indicates the completion of reception. issue the stop condition and end communication. save receive data. clear intiic0. yes yes remark while the slave is outputting a low level to the data line, the master cannot issue the stop condition. this happens if eeprom is not reset, even though the microcontroller is reset, because of supply voltage fluctuation during communication (reading from eeprom). in this case, the eeprom continues sending data, and may output a low level to the data line. because the structure of i 2 c does not allow the master to forcibly make the data line high, the master cannot issue the stop condition. to avoid this phenomenon, it is possible to use a clock line as a port, output a dummy clock from the port, continue reading data from eeprom by inputting the dummy clock, and complete reading with some eeproms (because the data line goes high when reading is completed, the master can issue the stop condition. after that, the status of eeprom can be controlled). at this time, the port corresponding to the data line must always be in the high-impedance state (high-level output).
374 chapter 18 serial interface iic0 ( pd780024ay, 780034ay subseries only) user s manual u14046ej3v0ud (2) slave operation the processing procedure of the slave operation is as follows. basically, the slave operation is event-driven. therefore, processing by the intiic0 interrupt (processing that must substantially change the operation status such as detection of a stop condition during communication) is necessary. in the following explanation, it is assumed that the extension code is not supported for data communication. it is also assumed that the intiic0 interrupt servicing only performs status transition processing, and that actual data communication is performed by the main processing. therefore, data communication processing is performed by preparing the following three flags and passing them to the main processing instead of intiic0. <1> communication mode flag this flag indicates the following two communication statuses. ? clear mode: status in which data communication is not performed ? communication mode: status in which data communication is performed (from valid address detection to stop condition detection, no detection of ack from master, address mismatch) <2> ready flag this flag indicates that data communication is enabled. its function is the same as the intiic0 interrupt for ordinary data communication. this flag is set by interrupt servicing and cleared by the main processing. clear this flag by interrupt servicing when communication is started. however, the ready flag is not set by interrupt servicing when the first data is transmitted. therefore, the first data is transmitted without the flag being cleared (an address match is interpreted as a request for the next data). <3> communication direction flag this flag indicates the direction of communication. its value is the same as trc0. iic0 interrupt servicing main processing intiic0 flag setting data setting
375 chapter 18 serial interface iic0 ( pd780024ay, 780034ay subseries only) user s manual u14046ej3v0ud the main processing of the slave operation is explained next. start serial interface iic0 and wait until communication is enabled. when communication is enabled, execute communication by using the communication mode flag and ready flag (processing of the stop condition and start condition is performed by an interrupt. here, check the status by using the flags). the transmission operation is repeated until the master no longer returns ack. if ack is not returned from the master, communication is completed. for reception, the necessary amount of data is received. when communication is completed, ack is not returned as the next data. after that, the master issues a stop condition or restart condition. exit from the communication status occurs in this way. figure 18-22. slave operation flowchart (1/2) communication direction flag = 1? iic0 data iicc0 h iice0 = 1 data processing clear ready flag. wrel0 = 1 clear communication mode flag. wtim0 = 1 communication mode? ready? ackd0 = 1? no no no no communication mode? yes yes yes yes yes start no no no ready? data processing wrel0 = 1 acke0 = wtim0 = 1 clear ready flag. acke0 = 0 wrel0 = 1 read data. communication ends? communication mode? yes yes yes no
376 chapter 18 serial interface iic0 ( pd780024ay, 780034ay subseries only) user s manual u14046ej3v0ud an example of the processing procedure of the slave with the intiic0 interrupt is explained below (processing is performed assuming that no extension code is used). the intiic0 interrupt checks the status, and the following operations are performed. <1> communication is stopped if the stop condition is issued. <2> if the start condition is issued, the address is checked and communication is completed if the address does not match. if the address matches, the communication mode is set, wait is cancelled, and processing returns from the interrupt (the ready flag is cleared). <3> for data transmit/receive, only the ready flag is set. processing returns from the interrupt with the iic0 bus remaining in the wait status. remark <1> to <3> above correspond to <1> to <3> in figure 18-22 slave operation flowchart (2/2) . figure 18-22. slave operation flowchart (2/2) std0 = 1 clear communication mode flag. lrel0 = 1 end processing yes yes yes <2> <3> <1> spd0 = 1 no no generate intiic0 complete interrupt servicing. set ready flag complete interrupt servicing. coi0 = 1? communication direction flag trc0 set communication mode flag and clear ready flag. complete interrupt servicing. no
chapter 18 serial interface iic0 ( pd780024ay, 780034ay subseries only) 377 user? manual u14046ej3v0ud spt0 = 1 spt0 = 1 18.5.16 timing of i 2 c interrupt request (intiic0) occurrence the intiic0 interrupt request timing and iic status register 0 (iics0) settings corresponding to that timing are described below. (1) master device operation (a) start ~ address ~ data ~ data ~ stop (normal transmission/reception) (i) when wtim0 = 0 st ad6 to ad0 rw ak d7 to d0 ak d7 to d0 ak sp 1 2 3 4 5 1: iics0 = 1000 110b 2: iics0 = 1000 000b 3: iics0 = 1000 000b (sets wtim0) 4: iics0 = 1000 00b (sets spt0) 5: iics0 = 00000001b remark : always generated : generated only when spie0 = 1 : don? care (ii) when wtim0 = 1 st ad6 to ad0 rw ak d7 to d0 ak d7 to d0 ak sp 1 2 3 4 1: iics0 = 1000 110b 2: iics0 = 1000 100b 3: iics0 = 1000 00b (sets spt0) 4: iics0 = 00000001b remark : always generated : generated only when spie0 = 1 : don? care
chapter 18 serial interface iic0 ( pd780024ay, 780034ay subseries only) 378 user? manual u14046ej3v0ud stt0 = 1 spt0 = 1 stt0 = 1 spt0 = 1 (b) start ~ address ~ data ~ start ~ address ~ data ~ stop (restart) (i) when wtim0 = 0 st ad6 to ad0 rw ak d7 to d0 ak st ad6 to ad0 rw ak d7 to d0 ak sp 1 2 3 4 5 6 7 1: iics0 = 1000 110b 2: iics0 = 1000 000b (sets wtim0) 3: iics0 = 1000 00b (clears wtim0, sets stt0) 4: iics0 = 1000 110b 5: iics0 = 1000 000b (sets wtim0) 6: iics0 = 1000 00b (sets spt0) 7: iics0 = 00000001b remark : always generated : generated only when spie0 = 1 : don? care (ii) when wtim0 = 1 st ad6 to ad0 rw ak d7 to d0 ak st ad6 to ad0 rw ak d7 to d0 ak sp 1 2 3 4 5 1: iics0 = 1000 110b 2: iics0 = 1000 00b (sets stt0) 3: iics0 = 1000 110b 4: iics0 = 1000 00b (sets spt0) 5: iics0 = 00000001b remark : always generated : generated only when spie0 = 1 : don? care
chapter 18 serial interface iic0 ( pd780024ay, 780034ay subseries only) 379 user? manual u14046ej3v0ud spt0 = 1 spt0 = 1 (c) start ~ code ~ data ~ data ~ stop (extension code transmission) (i) when wtim0 = 0 st ad6 to ad0 rw ak d7 to d0 ak d7 to d0 ak sp 1 2 3 4 5 1: iics0 = 1010 110b 2: iics0 = 1010 000b 3: iics0 = 1010 000b (sets wtim0) 4: iics0 = 1010 00b (sets spt0) 5: iics0 = 00000001b remark : always generated : generated only when spie0 = 1 : don? care (ii) when wtim0 = 1 st ad6 to ad0 rw ak d7 to d0 ak d7 to d0 ak sp 1 2 3 4 1: iics0 = 1010 110b 2: iics0 = 1010 100b 3: iics0 = 1010 00b (sets spt0) 4: iics0 = 00001001b remark : always generated : generated only when spie0 = 1 : don? care
chapter 18 serial interface iic0 ( pd780024ay, 780034ay subseries only) 380 user? manual u14046ej3v0ud (2) slave device operation (slave address data reception time (matches with sva0)) (a) start ~ address ~ data ~ data ~ stop (i) when wtim0 = 0 st ad6 to ad0 rw ak d7 to d0 ak d7 to d0 ak sp 1 2 3 4 1: iics0 = 0001 110b 2: iics0 = 0001 000b 3: iics0 = 0001 000b 4: iics0 = 00000001b remark : always generated : generated only when spie0 = 1 : don? care (ii) when wtim0 = 1 st ad6 to ad0 rw ak d7 to d0 ak d7 to d0 ak sp 1 2 3 4 1: iics0 = 0001 110b 2: iics0 = 0001 100b 3: iics0 = 0001 00b 4: iics0 = 00000001b remark : always generated : generated only when spie0 = 1 : don? care
chapter 18 serial interface iic0 ( pd780024ay, 780034ay subseries only) 381 user? manual u14046ej3v0ud (b) start ~ address ~ data ~ start ~ address ~ data ~ stop (i) when wtim0 = 0 (after restart, matches with sva0) st ad6 to ad0 rw ak d7 to d0 ak st ad6 to ad0 rw ak d7 to d0 ak sp 1 2 3 4 5 1: iics0 = 0001 110b 2: iics0 = 0001 000b 3: iics0 = 0001 110b 4: iics0 = 0001 000b 5: iics0 = 00000001b remark : always generated : generated only when spie0 = 1 : don? care (ii) when wtim0 = 1 (after restart, matches with sva0) st ad6 to ad0 rw ak d7 to d0 ak st ad6 to ad0 rw ak d7 to d0 ak sp 1 2 3 4 5 1: iics0 = 0001 110b 2: iics0 = 0001 00b 3: iics0 = 0001 110b 4: iics0 = 0001 00b 5: iics0 = 00000001b remark : always generated : generated only when spie0 = 1 : don? care
chapter 18 serial interface iic0 ( pd780024ay, 780034ay subseries only) 382 user? manual u14046ej3v0ud (c) start ~ address ~ data ~ start ~ code ~ data ~ stop (i) when wtim0 = 0 (after restart, extension code reception) st ad6 to ad0 rw ak d7 to d0 ak st ad6 to ad0 rw ak d7 to d0 ak sp 1 2 3 4 5 1: iics0 = 0001 110b 2: iics0 = 0001 000b 3: iics0 = 0010 010b 4: iics0 = 0010 000b 5: iics0 = 00000001b remark : always generated : generated only when spie0 = 1 : don? care (ii) when wtim0 = 1 (after restart, extension code reception) st ad6 to ad0 rw ak d7 to d0 ak st ad6 to ad0 rw ak d7 to d0 ak sp 1 2 3 4 5 6 1: iics0 = 0001 110b 2: iics0 = 0001 00b 3: iics0 = 0010 010b 4: iics0 = 0010 110b 5: iics0 = 0010 00b 6: iics0 = 00000001b remark : always generated : generated only when spie0 = 1 : don? care
chapter 18 serial interface iic0 ( pd780024ay, 780034ay subseries only) 383 user? manual u14046ej3v0ud (d) start ~ address ~ data ~ start ~ address ~ data ~ stop (i) when wtim0 = 0 (after restart, does not match with address (= not extension code)) st ad6 to ad0 rw ak d7 to d0 ak st ad6 to ad0 rw ak d7 to d0 ak sp 1 2 3 4 1: iics0 = 0001 110b 2: iics0 = 0001 000b 3: iics0 = 00000 10b 4: iics0 = 00000001b remark : always generated : generated only when spie0 = 1 : don? care (ii) when wtim0 = 1 (after restart, does not match with address (= not extension code)) st ad6 to ad0 rw ak d7 to d0 ak st ad6 to ad0 rw ak d7 to d0 ak sp 1 2 3 4 1: iics0 = 0001 110b 2: iics0 = 0001 00b 3: iics0 = 00000 10b 4: iics0 = 00000001b remark : always generated : generated only when spie0 = 1 : don? care
chapter 18 serial interface iic0 ( pd780024ay, 780034ay subseries only) 384 user? manual u14046ej3v0ud (3) slave device operation (when receiving extension code) (a) start ~ code ~ data ~ data ~ stop (i) when wtim0 = 0 st ad6 to ad0 rw ak d7 to d0 ak d7 to d0 ak sp 1 2 3 4 1: iics0 = 0010 010b 2: iics0 = 0010 000b 3: iics0 = 0010 000b 4: iics0 = 00000001b remark : always generated : generated only when spie0 = 1 : don? care (ii) when wtim0 = 1 st ad6 to ad0 rw ak d7 to d0 ak d7 to d0 ak sp 1 2 3 4 5 1: iics0 = 0010 010b 2: iics0 = 0010 110b 3: iics0 = 0010 100b 4: iics0 = 0010 00b 5: iics0 = 00000001b remark : always generated : generated only when spie0 = 1 : don? care
chapter 18 serial interface iic0 ( pd780024ay, 780034ay subseries only) 385 user? manual u14046ej3v0ud (b) start ~ code ~ data ~ start ~ address ~ data ~ stop (i) when wtim0 = 0 (after restart, matches with sva0) st ad6 to ad0 rw ak d7 to d0 ak st ad6 to ad0 rw ak d7 to d0 ak sp 1 2 3 4 5 1: iics0 = 0010 010b 2: iics0 = 0010 000b 3: iics0 = 0001 110b 4: iics0 = 0001 000b 5: iics0 = 00000001b remark : always generated : generated only when spie0 = 1 : don? care (ii) when wtim0 = 1 (after restart, matches with sva0) st ad6 to ad0 rw ak d7 to d0 ak st ad6 to ad0 rw ak d7 to d0 ak sp 1 2 3 4 5 6 1: iics0 = 0010 010b 2: iics0 = 0010 110b 3: iics0 = 0010 00b 4: iics0 = 0001 110b 5: iics0 = 0001 00b 6: iics0 = 00000001b remark : always generated : generated only when spie0 = 1 : don? care
chapter 18 serial interface iic0 ( pd780024ay, 780034ay subseries only) 386 user? manual u14046ej3v0ud (c) start ~ code ~ data ~ start ~ code ~ data ~ stop (i) when wtim0 = 0 (after restart, extension code reception) st ad6 to ad0 rw ak d7 to d0 ak st ad6 to ad0 rw ak d7 to d0 ak sp 1 2 3 4 5 1: iics0 = 0010 010b 2: iics0 = 0010 000b 3: iics0 = 0010 010b 4: iics0 = 0010 000b 5: iics0 = 00000001b remark : always generated : generated only when spie0 = 1 : don? care (ii) when wtim0 = 1 (after restart, extension code reception) st ad6 to ad0 rw ak d7 to d0 ak st ad6 to ad0 rw ak d7 to d0 ak sp 1 2 3 4 5 6 7 1: iics0 = 0010 010b 2: iics0 = 0010 110b 3: iics0 = 0010 00b 4: iics0 = 0010 010b 5: iics0 = 0010 110b 6: iics0 = 0010 00b 7: iics0 = 00000001b remark : always generated : generated only when spie0 = 1 : don? care
chapter 18 serial interface iic0 ( pd780024ay, 780034ay subseries only) 387 user? manual u14046ej3v0ud (d) start ~ code ~ data ~ start ~ address ~ data ~ stop (i) when wtim0 = 0 (after restart, does not match with address (= not extension code)) st ad6 to ad0 rw ak d7 to d0 ak st ad6 to ad0 rw ak d7 to d0 ak sp 1 2 3 4 1: iics0 = 0010 010b 2: iics0 = 0010 000b 3: iics0 = 00000 10b 4: iics0 = 00000001b remark : always generated : generated only when spie0 = 1 : don? care (ii) when wtim0 = 1 (after restart, does not match with address (= not extension code)) st ad6 to ad0 rw ak d7 to d0 ak st ad6 to ad0 rw ak d7 to d0 ak sp 1 2 3 4 5 1: iics0 = 0010 010b 2: iics0 = 0010 110b 3: iics0 = 0010 00b 4: iics0 = 00000 10b 5: iics0 = 00000001b remark : always generated : generated only when spie0 = 1 : don? care (4) operation without communication (a) start ~ code ~ data ~ data ~ stop st ad6 to ad0 rw ak d7 to d0 ak d7 to d0 ak sp 1 1: iics0 = 00000001b remark : generated only when spie0 = 1
chapter 18 serial interface iic0 ( pd780024ay, 780034ay subseries only) 388 user? manual u14046ej3v0ud (5) arbitration loss operation (operation as slave after arbitration loss) (a) when arbitration loss occurs during transmission of slave address data (i) when wtim0 = 0 st ad6 to ad0 rw ak d7 to d0 ak d7 to d0 ak sp 1 2 3 4 1: iics0 = 0101 110b ( example when ald0 is read during interrupt servicing) 2: iics0 = 0001 000b 3: iics0 = 0001 000b 4: iics0 = 00000001b remark : always generated : generated only when spie0 = 1 : don? care (ii) when wtim0 = 1 st ad6 to ad0 rw ak d7 to d0 ak d7 to d0 ak sp 1 2 3 4 1: iics0 = 0101 110b ( example when ald0 is read during interrupt servicing) 2: iics0 = 0001 100b 3: iics0 = 0001 00b 4: iics0 = 00000001b remark : always generated : generated only when spie0 = 1 : don? care
chapter 18 serial interface iic0 ( pd780024ay, 780034ay subseries only) 389 user? manual u14046ej3v0ud (b) when arbitration loss occurs during transmission of extension code (i) when wtim0 = 0 st ad6 to ad0 rw ak d7 to d0 ak d7 to d0 ak sp 1 2 3 4 1: iics0 = 0110 010b ( example when ald0 is read during interrupt servicing) 2: iics0 = 0010 000b 3: iics0 = 0010 000b 4: iics0 = 00000001b remark : always generated : generated only when spie0 = 1 : don? care (ii) when wtim0 = 1 st ad6 to ad0 rw ak d7 to d0 ak d7 to d0 ak sp 1 2 3 4 5 1: iics0 = 0110 010b ( example when ald0 is read during interrupt servicing) 2: iics0 = 0010 110b 3: iics0 = 0010 100b 4: iics0 = 0010 00b 5: iics0 = 00000001b remark : always generated : generated only when spie0 = 1 : don? care
chapter 18 serial interface iic0 ( pd780024ay, 780034ay subseries only) 390 user? manual u14046ej3v0ud (6) operation when arbitration loss occurs (no communication after arbitration loss) (a) when arbitration loss occurs during transmission of slave address data (when wtim0 = 1) st ad6 to ad0 rw ak d7 to d0 ak d7 to d0 ak sp 1 2 1: iics0 = 01000110b ( example when ald0 is read during interrupt servicing) 2: iics0 = 00000001b remark : always generated : generated only when spie0 = 1 (b) when arbitration loss occurs during transmission of extension code st ad6 to ad0 rw ak d7 to d0 ak d7 to d0 ak sp 1 2 1: iics0 = 0110 010b ( example when ald0 is read during interrupt servicing) lrel0 is set to ??by software 2: iics0 = 00000001b remark : always generated : generated only when spie0 = 1 : don? care
chapter 18 serial interface iic0 ( pd780024ay, 780034ay subseries only) 391 user? manual u14046ej3v0ud (c) when arbitration loss occurs during transmission of data (i) when wtim0 = 0 st ad6 to ad0 rw ak d7 to d0 ak d7 to d0 ak sp 1 2 3 1: iics0 = 10001110b 2: iics0 = 01000000b ( example when ald0 is read during interrupt servicing) 3: iics0 = 00000001b remark : always generated : generated only when spie0 = 1 (ii) when wtim0 = 1 st ad6 to ad0 rw ak d7 to d0 ak d7 to d0 ak sp 1 2 3 1: iics0 = 10001110b 2: iics0 = 01000100b ( example when ald0 is read during interrupt servicing) 3: iics0 = 00000001b remark : always generated : generated only when spie0 = 1
chapter 18 serial interface iic0 ( pd780024ay, 780034ay subseries only) 392 user? manual u14046ej3v0ud (d) when loss occurs due to restart condition during data transfer (i) not extension code (example: unmatches with sva0, wtim0 = 1) st ad6 to ad0 rw ak d7 to dn st ad6 to ad0 rw ak d7 to d0 ak sp 1 2 3 1: iics0 = 1000 110b 2: iics0 = 01000110b ( example when ald0 is read during interrupt servicing) 3: iics0 = 00000001b remark : always generated : generated only when spie0 = 1 : don? care n = 6 to 0 (ii) extension code st ad6 to ad0 rw ak d7 to dn st ad6 to ad0 rw ak d7 to d0 ak sp 1 2 3 1: iics0 = 1000 110b 2: iics0 = 0110 010b ( example when ald0 is read during interrupt servicing) sets lrel0 = 1 by software 3: iics0 = 00000001b remark : always generated : generated only when spie0 = 1 : don? care n = 6 to 0
chapter 18 serial interface iic0 ( pd780024ay, 780034ay subseries only) 393 user? manual u14046ej3v0ud (e) when loss occurs due to stop condition during data transfer st ad6 to ad0 rw ak d7 to dn sp 1 2 1: iics0 = 1000 110b 2: iics0 = 01000001b remark : always generated : generated only when spie0 = 1 : don? care n = 6 to 0 (f) when arbitration loss occurs due to low-level data when attempting to generate a restart condition (i) when wtim0 = 1 st ad6 to ad0 rw ak d7 to d0 ak d7 to d0 ak d7 to d0 ak sp 1 2 3 4 1: iics0 = 1000 110b 2: iics0 = 1000 100b (sets stt0) 3: iics0 = 01000100b ( example when ald0 is read during interrupt servicing) 4: iics0 = 00000001b remark : always generated : generated only when spie0 = 1 : don? care (g) when arbitration loss occurs due to a stop condition when attempting to generate a restart condition (i) when wtim0 = 1 st ad6 to ad0 rw ak d7 to d0 ak sp 1 2 3 1: iics0 = 1000 110b 2: iics0 = 1000 00b (sets stt0) 3: iics0 = 01000001b remark : always generated : generated only when spie0 = 1 : don? care stt0 = 1 stt0 = 1
chapter 18 serial interface iic0 ( pd780024ay, 780034ay subseries only) 394 user? manual u14046ej3v0ud (h) when arbitration loss occurs due to low-level data when attempting to generate a stop condition (i) when wtim0 = 1 st ad6 to ad0 rw ak d7 to d0 ak d7 to d0 ak d7 to d0 ak sp 1 2 3 4 1: iics0 = 1000 110b 2: iics0 = 1000 00b (sets spt0) 3: iics0 = 01000000b ( example when ald0 is read during interrupt servicing) 4: iics0 = 00000001b remark : always generated : generated only when spie0 = 1 : don? care spt0 = 1
chapter 18 serial interface iic0 ( pd780024ay, 780034ay subseries only) 395 user? manual u14046ej3v0ud 18.6 timing charts when using the i 2 c bus mode, the master device outputs an address via the serial bus to select one of several slave devices as its communication partner. after outputting the slave address, the master device transmits the trc0 bit (bit 3 of iic status register 0 (iics0)), which specifies the data transfer direction, and then starts serial communication with the slave device. figures 18-23 and 18-24 show timing charts of the data communication. iic shift register 0 (iic0)? shift operation is synchronized with the falling edge of the serial clock (scl0). the transmit data is transferred to the so0 latch and is output (msb first) via the sda0 pin. data input via the sda0 pin is captured into iic0 at the rising edge of scl0.
chapter 18 serial interface iic0 ( pd780024ay, 780034ay subseries only) 396 user? manual u14046ej3v0ud figure 18-23. example of master to slave communication (when 9-clock wait is selected for both master and slave) (1/3) (1) start condition ~ address note to cancel slave wait, write ?fh?to iic0 or set wrel0. iic0 ackd0 std0 spd0 wtim0 acke0 msts0 stt0 spt0 wrel0 intiic0 trc0 scl0 sda0 iic0 ackd0 std0 spd0 wtim0 acke0 msts0 stt0 spt0 wrel0 intiic0 trc0 iic0 address iic0 data h transmit h h l l a6 a5 a4 a3 a2 a1 a0 w ack d7 d6 d5 d4 4 3 2 1 9 8 7 6 5 4 3 2 1 h h l l l l receive (when exc0 = 1) note iic0 ffh note start condition processing by master device transfer lines processing by slave device
chapter 18 serial interface iic0 ( pd780024ay, 780034ay subseries only) 397 user s manual u14046ej3v0ud figure 18-23. example of master to slave communication (when 9-clock wait is selected for both master and slave) (2/3) (2) data note to cancel slave wait, write ffh to iic0 or set wrel0. iic0 ackd0 std0 spd0 wtim0 acke0 msts0 stt0 spt0 wrel0 intiic0 trc0 scl0 sda0 iic0 ackd0 std0 spd0 wtim0 acke0 msts0 stt0 spt0 wrel0 intiic0 trc0 l l l l h h l l receive note note iic0 ffh note iic0 ffh note 89 123456789 123 d0 d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 h transmit l l l h h h l l iic0 data iic0 data processing by master device transfer lines processing by slave device
chapter 18 serial interface iic0 ( pd780024ay, 780034ay subseries only) 398 user s manual u14046ej3v0ud figure 18-23. example of master to slave communication (when 9-clock wait is selected for both master and slave) (3/3) (3) stop condition note to cancel slave wait, write ffh to iic0 or set wrel0. iic0 ackd0 std0 spd0 wtim0 h h l l l l h h h l acke0 msts0 stt0 spt0 wrel0 intiic0 trc0 iic0 ackd0 std0 spd0 wtim0 acke0 msts0 stt0 spt0 wrel0 intiic0 trc0 scl0 sda0 processing by master device transfer lines processing by slave device 123456789 2 1 d7 d6 d5 d4 d3 d2 d1 d0 a5 a6 iic0 data iic0 address iic0 ffh note iic0 ffh note stop condition start condition transmit note note (when spie0 = 1) receive (when spie0 = 1)
chapter 18 serial interface iic0 ( pd780024ay, 780034ay subseries only) 399 user s manual u14046ej3v0ud figure 18-24. example of slave to master communication (when 9-clock wait is selected for both master and slave) (1/3) (1) start condition ~ address note to cancel master wait, write ffh to iic0 or set wrel0. iic0 ackd0 std0 spd0 wtim0 acke0 msts0 stt0 spt0 wrel0 intiic0 trc0 scl0 sda0 iic0 ackd0 std0 spd0 wtim0 acke0 msts0 stt0 spt0 wrel0 intiic0 trc0 iic0 address iic0 ffh note h h l note 123456789 123456 a6 a5 a4 a3 a2 a1 a0 r d7 d6 d5 d4 d3 d2 iic0 data h h l l l l start condition processing by master device transfer lines processing by slave device
chapter 18 serial interface iic0 ( pd780024ay, 780034ay subseries only) 400 user? manual u14046ej3v0ud figure 18-24. example of slave to master communication (when 9-clock wait is selected for both master and slave) (2/3) (2) data note to cancel master wait, write ?fh?to iic0 or set wrel0. iic0 ackd0 std0 spd0 wtim0 h h h l l l l l l h h h l l l l l acke0 msts0 stt0 spt0 wrel0 intiic0 trc0 iic0 ackd0 std0 spd0 wtim0 acke0 msts0 stt0 spt0 wrel0 intiic0 trc0 scl0 sda0 processing by master device transfer lines processing by slave device 1 89 23456789 3 2 1 d7 d0 ack d6 d5 d4 d3 d2 d1 d0 ack d5 d6 d7 note note receive transmit iic0 data iic0 data iic0 ffh note iic0 ffh note
chapter 18 serial interface iic0 ( pd780024ay, 780034ay subseries only) 401 user s manual u14046ej3v0ud figure 18-24. example of slave to master communication (when 9-clock wait is selected for both master and slave) (3/3) (3) stop condition note to cancel master wait, write ffh to iic0 or set wrel0. iic0 ackd0 std0 spd0 wtim0 h h l l l h acke0 msts0 stt0 spt0 wrel0 intiic0 trc0 iic0 ackd0 std0 spd0 wtim0 acke0 msts0 stt0 spt0 wrel0 intiic0 trc0 scl0 sda0 processing by master device transfer lines processing by slave device 123456789 2 1 d7 d6 d5 d4 d3 d2 d1 d0 a5 a6 iic0 address iic0 ffh note note iic0 data stop condition start condition (when spie0 = 1) n ? ack (when spie0 = 1)
402 user? manual u14046ej3v0ud chapter 19 interrupt functions 19.1 interrupt function types the following three types of interrupt functions are used. (1) non-maskable interrupt this interrupt is acknowledged even in an interrupt disabled state. it does not undergo priority control and is given top priority over all other interrupt requests. the other interrupt requests are held pending while the non- maskable interrupt is serviced. the non-maskable interrupt generates a standby release signal and releases the halt mode during main system clock operation. the non-maskable interrupt has only interrupt request from the watchdog timer. (2) maskable interrupts these interrupts undergo mask control. maskable interrupts can be divided into a high interrupt priority group and a low interrupt priority group by setting the priority specification flag registers (pr0l, pr0h, pr1l). multiple high priority interrupts can be applied to low priority interrupts. if two or more interrupts with the same priority are simultaneously generated, each interrupt has a predetermined priority (see table 19-1 ). the maskable interrupt generates a standby release signal and releases the stop and halt modes. five external interrupt requests and 13 internal interrupt requests are incorporated as maskable interrupts. (3) software interrupt this is a vectored interrupt to be generated by executing the brk instruction. it is acknowledged even in an interrupt disabled state. the software interrupt does not undergo interrupt priority control. 19.2 interrupt sources and configuration a total of 20 interrupt sources exist among non-maskable, maskable, and software interrupts (see table 19-1 ). remark a non-maskable interrupt or a maskable interrupt (internal) can be selected as the watchdog timer interrupt (intwdt).
403 chapter 19 interrupt functions user? manual u14046ej3v0ud table 19-1. interrupt source list interrupt default interrupt source internal/ vector basic type priority note 1 external table configuration name trigger address type note 2 non- ? intwdt watchdog timer overflow internal 0004h (a) maskable (with watchdog timer mode 1 selected) maskable 0 intwdt watchdog timer overflow (b) (with interval timer mode selected) 1 intp0 pin input edge detection external 0006h (c) 2 intp1 0008h 3 intp2 000ah 4 intp3 000ch 5 intser0 serial interface uart0 reception error internal 000eh (b) generation 6 intsr0 end of serial interface uart0 reception 0010h 7 intst0 end of serial interface uart0 transmission 0012h 8 intcsi30 end of serial interface sio30 transfer 0014h 9 intcsi31 end of serial interface sio31 transfer 0016h [only for pd780024a, 780034a subseries] 10 intiic0 end of serial interface iic0 transfer 0018h [only for pd780024ay, 780034ay subseries] 11 intwti reference time interval signal from watch timer 001ah 12 inttm00 match between tm0 and cr00 001ch (when cr00 is specified as compare register) detection of ti01 valid edge (when cr00 is specified as capture register) 13 inttm01 match between tm0 and cr01 001eh (when cr01 is specified as compare register) detection of ti00 valid edge (when cr01 is specified as capture register) 14 inttm50 match between tm50 and cr50 0020h 15 inttm51 match between tm51 and cr51 0022h 16 intad0 end of a/d converter conversion 0024h 17 intwt watch timer overflow 0026h 18 intkr port 4 falling edge detection external 0028h (d) software ? brk brk instruction execution ? 003eh (e) notes 1. the default priority is the priority applicable when two or more maskable interrupts are generated simultaneously. 0 is the highest priority, and 18 is the lowest. 2. basic configuration types (a) to (e) correspond to (a) to (e) in figure 19-1.
404 chapter 19 interrupt functions user? manual u14046ej3v0ud figure 19-1. basic configuration of interrupt function (1/2) (a) internal non-maskable interrupt (b) internal maskable interrupt (c) external maskable interrupt (intp0 to intp3) internal bus interrupt request if mk ie pr isp priority controller vector table address generator standby release signal external interrupt edge enable register (egp, egn) edge detector internal bus interrupt request priority controller vector table address generator standby release signal internal bus interrupt request if mk ie pr isp priority controller vector table address generator standby release signal
405 chapter 19 interrupt functions user s manual u14046ej3v0ud figure 19-1. basic configuration of interrupt function (2/2) (d) external maskable interrupt (intkr) (e) software interrupt if: interrupt request flag ie: interrupt enable flag isp: in-service priority flag mk: interrupt mask flag pr: priority specification flag mem: memory expansion mode register if mk ie pr isp internal bus interrupt request priority controller vector table address generator standby release signal falling edge detector 1 when mem = 01h internal bus interrupt request vector table address generator
406 chapter 19 interrupt functions user s manual u14046ej3v0ud 19.3 interrupt function control registers the following 6 types of registers are used to control the interrupt functions. interrupt request flag registers (if0l, if0h, if1l) interrupt mask flag registers (mk0l, mk0h, mk1l) priority specification flag registers (pr0l, pr0h, pr1l) external interrupt rising edge enable register (egp) external interrupt falling edge enable register (egn) program status word (psw) table 19-2 gives a list of interrupt request flags, interrupt mask flags, and priority specification flags corresponding to interrupt request sources. table 19-2. flags corresponding to interrupt request sources interrupt source interrupt request flag interrupt mask flag priority specification flag register register register intwdt wdtif note 1 if0l wdtmk mk0l wdtpr pr0l intp0 pif0 pmk0 ppr0 intp1 pif1 pmk1 ppr1 intp2 pif2 pmk2 ppr2 intp3 pif3 pmk3 ppr3 intser0 serif0 sermk0 serpr0 intsr0 srif0 srmk0 srpr0 intst0 stif0 stmk0 stpr0 intcsi30 csiif30 if0h csimk30 mk0h csipr30 pr0h intcsi31 note 2 csiif31 note 2 csimk31 note 2 csipr31 note 2 intiic0 note 3 iicif0 note 3 iicmk0 note 3 iicpr0 note 3 intwti wtiif wtimk wtipr inttm00 tmif00 tmmk00 tmpr00 inttm01 tmif01 tmmk01 tmpr01 inttm50 tmif50 tmmk50 tmpr50 inttm51 tmif51 tmmk51 tmpr51 intad0 adif0 if1l admk0 mk1l adpr0 pr1l intwt wtif wtmk wtpr intkr krif krmk krpr notes 1. interrupt control flag when watchdog timer is used as interval timer 2. pd780024a, 780034a subseries only 3. pd780024ay, 780034ay subseries only
407 chapter 19 interrupt functions user s manual u14046ej3v0ud (1) interrupt request flag registers (if0l, if0h, if1l) the interrupt request flags are set to 1 when the corresponding interrupt request is generated or an instruction is executed. they are cleared to 0 when an instruction is executed upon acknowledgment of an interrupt request or upon application of reset input. if0l, if0h, and if1l are set by a 1-bit or 8-bit memory manipulation instruction. when if0l and if0h are combined to form 16-bit register if0, they are set by a 16-bit memory manipulation instruction. reset input clears these registers to 00h. figure 19-2. format of interrupt request flag registers (if0l, if0h, if1l) address: ffe0h after reset: 00h r/w symbol <7> <6> <5> <4> <3> <2> <1> <0> if0l stif0 srif0 serif0 pif3 pif2 pif1 pif0 wdtif address: ffe1h after reset: 00h r/w symbol <7> <6> <5> <4> <3> <2> <1> <0> if0h tmif51 tmif50 tmif01 tmif00 wtiif iicif0 note 1 csiif31 note 2 csiif30 address: ffe2h after reset: 00h r/w symbol 76543<2><1><0> if1l 00000 krif wtif adif0 xxifx interrupt request flag 0 no interrupt request signal is generated 1 interrupt request signal is generated, interrupt request status notes 1. incorporated only in the pd780024ay, 780034ay subseries. be sure to clear 0 for the pd780024a, 780034a subseries. 2. incorporated only in the pd780024a, 780034a subseries. be sure to clear 0 for the pd780024ay, 780034ay subseries. cautions 1. the wdtif flag is r/w enabled only when the watchdog timer is used as the interval timer. if watchdog timer mode 1 is used, set the wdtif flag to 0. 2. be sure to clear bits 3 to 7 of if1l to 0. 3. when operating a timer, serial interface, or a/d converter after standby release, run it once after clearing an interrupt request flag. an interrupt request flag may be set by noise. 4. when an interrupt is acknowledged, the interrupt request flag is automatically cleared, and then processing of the interrupt routine is started. 5. when the interrupt request flag register is being manipulated (including 1-bit memory manipulation), if an interrupt request corresponding to other flags in the same register is generated, the flag corresponding to the interrupt request may not be set (1).
408 chapter 19 interrupt functions user s manual u14046ej3v0ud (2) interrupt mask flag registers (mk0l, mk0h, mk1l) the interrupt mask flags are used to enable/disable the corresponding maskable interrupt service. mk0l, mk0h, and mk1l are set by a 1-bit or 8-bit memory manipulation instruction. when mk0l and mk0h are combined to form a 16-bit register mk0, they are set by a 16-bit memory manipulation instruction. reset input sets these registers to ffh. figure 19-3. format of interrupt mask flag registers (mk0l, mk0h, mk1l) address: ffe4h after reset: ffh r/w symbol <7> <6> <5> <4> <3> <2> <1> <0> mk0l stmk0 srmk0 sermk0 pmk3 pmk2 pmk1 pmk0 wdtmk address: ffe5h after reset: ffh r/w symbol <7> <6> <5> <4> <3> <2> <1> <0> mk0h tmmk51 tmmk50 tmmk01 tmmk00 wtimk iicmk0 note 1 csimk31 note 2 csimk30 address: ffe6h after reset: ffh r/w symbol 76543<2><1><0> mk1l 11111 krmk wtmk admk0 xxmkx interrupt servicing control 0 interrupt servicing enabled 1 interrupt servicing disabled notes 1. incorporated only in the pd780024ay, 780034ay subseries. be sure to set 1 for the pd780024a, 780034a subseries. 2. incorporated only in the pd780024a, 780034a subseries. be sure to set 1 for the pd780024ay, 780034ay subseries. cautions 1. if the watchdog timer is used in watchdog timer mode 1, the contents of the wdtmk flag become undefined when read. 2. because port 0 pins have an alternate function as external interrupt request input, when the output level is changed by specifying the output mode of the port function, an interrupt request flag is set. therefore, 1 should be set in the interrupt mask flag before using the output mode. 3. be sure to set bits 3 to 7 of mk1l to 1.
409 chapter 19 interrupt functions user s manual u14046ej3v0ud (3) priority specification flag registers (pr0l, pr0h, pr1l) the priority specification flags are used to set the corresponding maskable interrupt priority orders. pr0l, pr0h, and pr1l are set by a 1-bit or 8-bit memory manipulation instruction. if pr0l and pr0h are combined to form 16-bit register pr0, they are set by a 16-bit memory manipulation instruction. reset input sets these registers to ffh. figure 19-4. format of priority specification flag registers (pr0l, pr0h, pr1l) address: ffe8h after reset: ffh r/w symbol <7> <6> <5> <4> <3> <2> <1> <0> pr0l stpr0 srpr0 serpr0 ppr3 ppr2 ppr1 ppr0 wdtpr address: ffe9h after reset: ffh r/w symbol <7> <6> <5> <4> <3> <2> <1> <0> pr0h tmpr51 tmpr50 tmpr01 tmpr00 wtipr iicpr0 note 1 csipr31 note 2 csipr30 address: ffeah after reset: ffh r/w symbol 76543<2><1><0> pr1l 11111 krpr wtpr adpr0 xxprx priority level selection 0 high priority level 1 low priority level notes 1. incorporated only in the pd780024ay, 780034ay subseries. be sure to set 1 for the pd780024a, 780034a subseries. 2. incorporated only in the pd780024a, 780034a subseries. be sure to set 1 for the pd780024ay, 780034ay subseries. cautions 1. if the watchdog timer is used in watchdog timer mode 1, set the wdtpr flag to 1. 2. be sure to set bits 3 to 7 of pr1l to 1.
410 chapter 19 interrupt functions user s manual u14046ej3v0ud (4) external interrupt rising edge enable register (egp), external interrupt falling edge enable register (egn) these registers specify the valid edge for intp0 to intp3. egp and egn are set by a 1-bit or 8-bit memory manipulation instruction. reset input clears these registers to 00h. figure 19-5. format of external interrupt rising edge enable register (egp), external interrupt falling edge enable register (egn) address: ff48h after reset: 00h r/w symbol 76543210 egp 0000 egp3 egp2 egp1 egp0 address: ff49h after reset: 00h r/w symbol 76543210 egn 0000 egn3 egn2 egn1 egn0 egpn egnn intpn pin valid edge selection (n = 0 to 3) 0 0 interrupt disable 0 1 falling edge 1 0 rising edge 1 1 both rising and falling edges caution when the function is switched from external interrupt request to port, edge detection may be performed. therefore, clear egpn and egnn to 0 before switching to the port mode.
411 chapter 19 interrupt functions user s manual u14046ej3v0ud (5) program status word (psw) the program status word is a register to hold the instruction execution result and the current status for an interrupt request. the ie flag to set maskable interrupt enable/disable and the isp flag to control nesting processing are mapped. besides 8-bit read/write, this register can carry out operations with a bit manipulation instruction and dedicated instructions (ei and di). when a vectored interrupt request is acknowledged, if the brk instruction is executed, the contents of psw are automatically saved into a stack and the ie flag is reset to 0. if a maskable interrupt request is acknowledged, the contents of the priority specification flag of the acknowledged interrupt are transferred to the isp flag. the psw contents are also saved into the stack with the push psw instruction. they are restored from the stack with the reti, retb, and pop psw instructions. reset input sets psw to 02h. figure 19-6. program status word format 7 ie 6 z 5 rbs1 4 ac 3 rbs0 2 0 1 isp 0 cy psw after reset 02h isp high-priority interrupt servicing (low-priority interrupt disable) ie 0 1 disable priority of interrupt currently being serviced interrupt request acknowledge enable/disable used when normal instruction is executed enable interrupt request not acknowledged, or low- priority interrupt servicing (all maskable interrupts enable) 0 1
412 chapter 19 interrupt functions user s manual u14046ej3v0ud 19.4 interrupt servicing operations 19.4.1 non-maskable interrupt request acknowledgment operation a non-maskable interrupt request is unconditionally acknowledged even in an interrupt acknowledgment disabled state. it does not undergo interrupt priority control and has the highest priority of all interrupts. if a non-maskable interrupt request is acknowledged, the contents are saved into the stacks in the order of psw, then pc, the ie flag and isp flag are reset (0), and the contents of the vector table are loaded into the pc and branched. at this time, the nmis flag is set (1) to disable acknowledgment of multiple interrupts. a new non-maskable interrupt request generated during execution of a non-maskable interrupt servicing program is acknowledged after the current non-maskable interrupt servicing program is terminated (following reti instruction execution) and one main routine instruction has been executed. however, if a new non-maskable interrupt request is generated twice or more during non-maskable interrupt servicing program execution, only one non-maskable interrupt request is acknowledged after termination of the non-maskable interrupt servicing program. figures 19-7, 19-8, and 19-9 show the flowchart of non-maskable interrupt request generation through acknowledgment, the acknowledgment timing of a non-maskable interrupt request, and the acknowledgment operation when multiple non- maskable interrupt requests are generated, respectively. remark when a non-maskable interrupt is acknowledged, the nmis flag is set (1). it is cleared (0) by the ret or reti instruction. when a non-maskable interrupt is generated, execute the reti instruction to restore processing from the interrupt.
413 chapter 19 interrupt functions user s manual u14046ej3v0ud figure 19-7. non-maskable interrupt request generation to acknowledge flowchart figure 19-8. non-maskable interrupt request acknowledge timing start wdtm4 = 1 (with watchdog timer mode selected)? overflow in wdt? wdt interrupt servicing? interrupt control register not accessed? interval timer no reset processing no interrupt request generation start of interrupt servicing interrupt request held pending no no no yes yes yes yes yes wdtm: watchdog timer mode register wdt: watchdog timer wdtm3 = 0 (with non-maskable interrupt selected)? instruction instruction psw and pc save, jump to interrupt servicing interrupt service program cpu processing wdtif interrupt request generated during this interval is acknowledged at . wdtif: watchdog timer interrupt request flag
414 chapter 19 interrupt functions user s manual u14046ej3v0ud figure 19-9. non-maskable interrupt request acknowledge operation (a) if a non-maskable interrupt request is generated during non-maskable interrupt servicing program execution main routine nmi request <1> execution of 1 instruction nmi request <2> execution of nmi request <1> nmi request <2> held pending servicing of nmi request <2> that was pended (b) if two non-maskable interrupt requests are generated during non-maskable interrupt servicing program execution main routine nmi request <1> execution of 1 instruction execution of nmi request <1> nmi request <2> held pending nmi request <3> held pending servicing of nmi request <2> that was pended nmi request <3> not acknowledged (although two or more nmi requests have been generated, only one request is acknowledged.) nmi request <2> nmi request <3>
415 chapter 19 interrupt functions user s manual u14046ej3v0ud 19.4.2 maskable interrupt request acknowledgment operation a maskable interrupt request becomes acknowledgeable when an interrupt request flag is set to 1 and the mask (mk) flag corresponding to that interrupt request is cleared to 0. a vectored interrupt request is acknowledged if interrupts are enabled (when the ie flag is set to 1). however, a low-priority interrupt request is not acknowledged during servicing of a higher priority interrupt request (when the isp flag is reset to 0). moreover, even if the ei instruction is executed during execution of a non-maskable interrupt servicing program (nmis = 1), neither non-maskable interrupt requests nor maskable interrupt requests are acknowledged. the times from generation of a maskable interrupt request until interrupt servicing is performed are listed in table 19-3 below. for the interrupt request acknowledgment timing, see figures 19-11 and 19-12 . table 19-3. times from generation of maskable interrupt until servicing minimum time maximum time note when pr = 0 7 clocks 32 clocks when pr = 1 8 clocks 33 clocks note if an interrupt request is generated just before a divide instruction, the wait time becomes longer. remark 1 clock: 1/f cpu (f cpu : cpu clock) if two or more interrupt requests are generated simultaneously, the request with a higher priority level specified by the priority specification flag is acknowledged first. if two or more interrupt requests have the same priority level, the request with the highest default priority is acknowledged first. an interrupt request that is held pending is acknowledged when it becomes acknowledgeable. figure 19-10 shows the interrupt request acknowledgment algorithm. if a maskable interrupt request is acknowledged, the contents are saved into the stacks in the order of psw, then pc, the ie flag is reset (0), and the contents of the priority specification flag corresponding to the acknowledged interrupt are transferred to the isp flag. further, the vector table data determined for each interrupt request is loaded into the pc and branched. return from an interrupt is possible using the reti instruction.
416 chapter 19 interrupt functions user s manual u14046ej3v0ud figure 19-10. interrupt request acknowledge processing algorithm start if = 1? mk = 0? pr = 0? ie = 1? isp = 1? interrupt request held pending yes yes no no yes (interrupt request generation) yes no (low priority) no no yes yes no ie = 1? no any high-priority interrupt request among those simultaneously generated with pr = 0? yes (high priority) no yes yes no vectored interrupt servicing interrupt request held pending interrupt request held pending interrupt request held pending interrupt request held pending interrupt request held pending interrupt request held pending vectored interrupt servicing any high-priority interrupt request among those simultaneously generated? any high-priority interrupt request among those simultaneously generated with pr = 0? if: interrupt request flag mk: interrupt mask flag pr: priority specification flag ie: flag that controls acknowledge of maskable interrupt request (1 = enable, 0 = disable) isp: flag that indicates the priority level of the interrupt currently being serviced (0 = high-priority interrupt servicing, 1 = no interrupt request acknowledged, or low-priority interrupt servicing)
417 chapter 19 interrupt functions user s manual u14046ej3v0ud 33 clocks 32 clocks instruction divide instruction psw and pc save, jump to interrupt servicing interrupt servicing program cpu processing if ( pr = 1) if ( pr = 0) 6 clocks 25 clocks 8 clocks 7 clocks instruction instruction psw and pc save, jump to interrupt servicing interrupt servicing program cpu processing if ( pr = 1) if ( pr = 0) 6 clocks figure 19-11. interrupt request acknowledge timing (minimum time) remark 1 clock: 1/f cpu (f cpu : cpu clock) figure 19-12. interrupt request acknowledge timing (maximum time) remark 1 clock: 1/f cpu (f cpu : cpu clock) 19.4.3 software interrupt request acknowledgment operation a software interrupt request is acknowledged by brk instruction execution. software interrupts cannot be disabled. if a software interrupt request is acknowledged, the contents are saved into the stacks in the order of the program status word (psw), then program counter (pc), the ie flag is reset (0), and the contents of the vector table (003eh, 003fh) are loaded into pc and branched. return from a software interrupt is possible with the retb instruction. caution do not use the reti instruction for returning from the software interrupt.
418 chapter 19 interrupt functions user s manual u14046ej3v0ud 19.4.4 nesting interrupt servicing nesting occurs when another interrupt request is acknowledged during execution of an interrupt. nesting does not occur unless the interrupt request acknowledge enable state is selected (ie = 1) (except non- maskable interrupts). also, when an interrupt request is acknowledged, interrupt request acknowledge becomes disabled (ie = 0). therefore, to enable nesting, it is necessary to set (1) the ie flag with the ei instruction during interru pt servicing to enable interrupt acknowledge. moreover, even if interrupts are enabled, nesting may not be enabled, this being subject to interrupt priority control. two types of priority control are available: default priority control and programmable priority control. programmable priority control is used for nesting. in the interrupt enable state, if an interrupt request with a priority equal to or higher than that of the interrupt currently being serviced is generated, it is acknowledged for nesting. if an interrupt with a priority lower than that of the interrupt currently being serviced is generated during interrupt servicing, it is not acknowledged for nesting. interrupt requests that are not enabled because of the interrupt disable state or they have a lower priority are held pending. when servicing of the current interrupt ends, the pended interrupt request is acknowledged following execution of at least one main processing instruction execution. nesting is not possible during non-maskable interrupt servicing. table 19-4 shows interrupt requests enabled for nesting and figure 19-13 shows nesting examples. table 19-4. interrupt requests enabled for nesting during interrupt servicing nesting request non-maskable maskable interrupt request software interrupt request pr = 0 pr = 1 interrupt interrupt being serviced ie = 1 ie = 0 ie = 1 ie = 0 request non-maskable interrupt maskable interrupt isp = 0 isp = 1 software interrupt remarks 1. : nesting enabled 2. : nesting disabled 3. isp and ie are flags contained in the psw. isp = 0: an interrupt with higher priority is being serviced. isp = 1: no interrupt request has been acknowledged, or an interrupt with a lower priority is being serviced. ie = 0: interrupt request acknowledgment is disabled. ie = 1: interrupt request acknowledgment is enabled. 4. pr is a flag contained in pr0l, pr0h, and pr1l. pr = 0: higher priority level pr = 1: lower priority level
419 chapter 19 interrupt functions user s manual u14046ej3v0ud figure 19-13. nesting examples (1/2) example 1. nesting occurs twice main processing intxx servicing intyy servicing intzz servicing ei ei ei reti reti reti intxx (pr = 1) intyy (pr = 0) intzz (pr = 0) ie = 0 ie = 1 ie = 1 ie = 1 ie = 0 ie = 0 during servicing of interrupt intxx, two interrupt requests, intyy and intzz, are acknowledged, and nesting takes place. before each interrupt request is acknowledged, the ei instruction must always be issued to enable interrupt request acknowledgment. example 2. nesting does not occur due to priority control main processing intxx servicing intyy servicing intxx (pr = 0) intyy (pr = 1) ei reti ie = 0 ie = 0 ie = 1 ie = 1 ei reti 1 instruction execution interrupt request intyy issued during servicing of interrupt intxx is not acknowledged because its priority is lower than that of intxx, and nesting does not take place. the intyy interrupt request is held pending, and is acknowledged following execution of one main processing instruction. pr = 0: higher priority level pr = 1: lower priority level ie = 0: interrupt request acknowledgment disabled
420 chapter 19 interrupt functions user s manual u14046ej3v0ud figure 19-13. nesting examples (2/2) example 3. nesting does not occur because interrupts are not enabled main processing intxx servicing intyy servicing ei reti reti intxx (pr = 0) intyy (pr = 0) ie = 0 ie = 1 ie = 0 ie = 1 1 instruction execution interrupts are not enabled during servicing of interrupt intxx (ei instruction is not issued), so interrupt request intyy is not acknowledged and nesting does not take place. the intyy interrupt request is held pending, and is acknowledged following execution of one main processing instruction. pr = 0: higher priority level ie = 0: interrupt request acknowledgment disabled
421 chapter 19 interrupt functions user s manual u14046ej3v0ud 19.4.5 interrupt request hold there are instructions where, even if an interrupt request is issued for them while another instruction is executed, request acknowledge is held pending until the end of execution of the next instruction. these instructions (interrupt request hold instructions) are listed below. mov psw, #byte mov a, psw mov psw, a mov1 psw.bit, cy mov1 cy, psw.bit and1 cy, psw.bit or1 cy, psw.bit xor1 cy, psw.bit set1 psw.bit clr1 psw.bit retb reti push psw pop psw bt psw.bit, $addr16 bf psw.bit, $addr16 btclr psw.bit, $addr16 ei di manipulate instructions for the if0l, if0h, if1l, mk0l, mk0h, mk1l, pr0l, pr0h, and pr1l registers caution the brk instruction is not one of the above-listed interrupt request hold instructions. however, the software interrupt activated by executing the brk instruction causes the ie flag to be cleared to 0. therefore, even if a maskable interrupt request is generated during execution of the brk instruction, the interrupt request is not acknowledged. however, a non-maskable interrupt request is acknowledged. figure 19-14 shows the timing with which interrupt requests are held pending. figure 19-14. interrupt request hold instruction n instruction m save psw and pc, jump to interrupt servicing interrupt servicing program cpu processing if remarks 1. instruction n: interrupt request hold instruction 2. instruction m: instruction other than interrupt request hold instruction 3. the pr (priority level) values do not affect the operation of if (interrupt request).
422 user? manual u14046ej3v0ud chapter 20 external device expansion function use the expanded-specification products of the pd780024a and 780034a subseries, under the conventional- specification conditions (f x = 8.38 mhz: v dd = 4.0 to 5.5 v, f x = 5 mhz: v dd = 2.7 to 5.5 v, f x = 1.25 mhz: v dd = 1.8 to 5.5 v). the external device expansion function cannot be used under the expanded-specification conditions (high-speed operation). 20.1 external device expansion function the external device expansion function connects external devices to areas other than the internal rom, ram, and sfr. connection of external devices uses ports 4 to 6. ports 4 to 6 control address/data, read/write strobe, wait, address strobe, etc. table 20-1. pin functions in external memory expansion mode pin function when external device is connected alternate function name function ad0 to ad7 multiplexed address/data bus p40 to p47 a8 to a15 address bus p50 to p57 rd read strobe signal p64 wr write strobe signal p65 wait wait signal p66 astb address strobe signal p67 table 20-2. state of port 4 to 6 pins in external memory expansion mode caution when the external wait function is not used, the wait pin can be used as a port in all modes. port port 4 port 5 port 6 external expansion mode 0 to 7 0 1 2 3 4 5 6 74567 single-chip mode port port port 256-byte expansion mode address/data port rd, wr, wait, astb 4 kb expansion mode address/data address port rd, wr, wait, astb 16 kb expansion mode address/data address port rd, wr, wait, astb full-address mode address/data address rd, wr, wait, astb
423 chapter 20 external device expansion function user? manual u14046ej3v0ud the memory maps when the external device expansion function is used are as follows. figure 20-1. memory map when using external device expansion function (1/2) (a) memory map of pd780021a, 780031a, 780021ay, 780031ay and of pd78f0034a, 78f0034ay when internal rom (flash memory) size is 8 kb (b) memory map of pd780022a, 780032a, 780022ay, 780032ay and of pd78f0034a, 78f0034ay when internal rom (flash memory) size is 16 kb sfr internal high-speed ram reserved full-address mode (when mm2 to mm0 = 111) 16 kb expansion mode (when mm2 to mm0 = 101) 4 kb expansion mode (when mm2 to mm0 = 100) 256-byte expansion mode (when mm2 to mm0 = 011) single-chip mode ffffh ff00h feffh fd00h fcffh f800h f7ffh 6000h 5fffh 3000h 2fffh 2100h 20ffh 2000h 1fffh 0000h ffffh ff00h feffh fd00h fcffh f800h f7ffh 8000h 7fffh 5000h 4fffh 4100h 40ffh 4000h 3fffh 0000h sfr internal high-speed ram reserved full-address mode (when mm2 to mm0 = 111) 16 kb expansion mode (when mm2 to mm0 = 101) 4 kb expansion mode (when mm2 to mm0 = 100) 256-byte expansion mode (when mm2 to mm0 = 011) single-chip mode
424 chapter 20 external device expansion function user s manual u14046ej3v0ud figure 20-1. memory map when using external device expansion function (2/2) (c) memory map of pd780023a, 780033a, 780023ay, 780033ay and of pd78f0034a, 78f0034ay when internal rom (flash memory) size is 24 kb (d) memory map of pd780024a, 780034a, 780024ay, 780034ay and of pd78f0034a, 78f0034ay when internal rom (flash memory) size is 32 kb sfr internal high-speed ram reserved full-address mode (when mm2 to mm0 = 111) 16 kb expansion mode (when mm2 to mm0 = 101) 256-byte expansion mode (when mm2 to mm0 = 011) single-chip mode ffffh ff00h feffh fb00h faffh f800h f7ffh a000h 9fffh 6100h 60ffh 0000h 7000h 6fffh 6000h 5fffh 4 kb expansion mode (when mm2 to mm0 = 100) ffffh ff00h feffh fb00h faffh f800h f7ffh c000h bfffh 8100h 80ffh 0000h 9000h 8fffh 8000h 7fffh sfr internal high-speed ram reserved full-address mode (when mm2 to mm0 = 111) 16 kb expansion mode (when mm2 to mm0 = 101) 256-byte expansion mode (when mm2 to mm0 = 011) single-chip mode 4 kb expansion mode (when mm2 to mm0 = 100)
425 chapter 20 external device expansion function user s manual u14046ej3v0ud 20.2 external device expansion function control registers the external device expansion function is controlled by the following two registers. memory expansion mode register (mem) memory expansion wait setting register (mm) (1) memory expansion mode register (mem) mem sets the external expansion area. mem is set by a 1-bit or 8-bit memory manipulation instruction. reset input clears mem to 00h. figure 20-2. format of memory expansion mode register (mem) address: ff47h after reset: 00h r/w symbol 76543210 mem 00000mm2mm1mm0 mm2 mm1 mm0 single-chip/memory p40 to p47, p50 to p57, p64 to p67 pin state expansion mode selection p40 to p47 p50 to p53 p54, p55 p56, p57 p64 to p67 0 0 0 single-chip mode port mode 0 0 1 port 4 falling edge detection mode 0 1 1 memory 256-byte ad0 to ad7 port mode p64 = rd expansion mode p65 = wr 100 mode note 1 4 kb a8 to a11 port mode p66 =wait mode p67 = astb 1 0 1 16 kb a12, a13 port mode mode 111 full-address a14, a15 mode note 2 other than above setting prohibited notes 1. when the memory expansion mode is set, if an area other than the external expansion area is accessed, the read value is undefined. 2. the full-address mode allows external expansion to the entire 64 kb address space except for the internal rom, ram, and sfr areas, and the reserved areas. caution when using the falling edge detection function of port 4, be sure to set mem to 01h.
426 chapter 20 external device expansion function user s manual u14046ej3v0ud (2) memory expansion wait setting register (mm) mm sets the number of waits. mm is set by a 1-bit or 8-bit memory manipulation instruction. reset input sets mm to 10h. figure 20-3. format of memory expansion wait setting register (mm) address: fff8h after reset: 10h r/w symbol 76543210 mm 00pw1pw00000 pw1 pw0 wait control 0 0 no wait 0 1 wait (one wait state inserted) 1 0 setting prohibited 1 1 wait control by external wait pin cautions 1. when wait is controlled by the external wait pin, be sure to set the wait/p66 pin to input mode (set bit 6 (pm66) of port mode register 6 (pm6) to 1). 2. when wait is not controlled by the external wait pin, the wait/p66 pin can be used as an i/o port pin.
427 chapter 20 external device expansion function user s manual u14046ej3v0ud 20.3 external device expansion function timing timing control signal output pins in the external memory expansion mode are as follows. (1) rd pin (alternate function: p64) read strobe signal output pin. the read strobe signal is output in data read and instruction fetch from external memory. during internal memory read, the read strobe signal is not output (maintains high level). (2) wr pin (alternate function: p65) write strobe signal output pin. the write strobe signal is output in data write to external memory. during internal memory write, the write strobe signal is not output (maintains high level). (3) wait pin (alternate function: p66) external wait signal input pin. when the external wait is not used, the wait pin can be used as an i/o port. during internal memory access, the external wait signal is ignored. (4) astb pin (alternate function: p67) address strobe signal output pin. the address strobe signal is output regardless of data access and instruction fetch from external memory. during internal memory access, the address strobe signal is output. (5) ad0 to ad7, a8 to a15 pins (alternate function: p40 to p47, p50 to p57) address/data signal output pins. valid signal is output or input during data accesses and instruction fetches from external memory. these signals change even during internal memory access (output values are undefined). the timing charts are shown in figures 20-4 to 20-7.
428 chapter 20 external device expansion function user s manual u14046ej3v0ud figure 20-4. instruction fetch from external memory (a) no wait (pw1, pw0 = 0, 0) setting (b) wait (pw1, pw0 = 0, 1) setting (c) external wait (pw1, pw0 = 1, 1) setting rd astb ad0 to ad7 a8 to a15 lower address instruction code higher address rd astb ad0 to ad7 a8 to a15 internal wait signal ( 1-clock wait ) lower address instruction code higher address rd astb ad0 to ad7 a8 to a15 wait lower address instruction code higher address
429 chapter 20 external device expansion function user s manual u14046ej3v0ud figure 20-5. external memory read timing (a) no wait (pw1, pw0 = 0, 0) setting (b) wait (pw1, pw0 = 0, 1) setting (c) external wait (pw1, pw0 = 1, 1) setting rd astb ad0 to ad7 a8 to a15 lower address read data higher address rd astb ad0 to ad7 a8 to a15 internal wait signal (1-clock wait) lower address read data higher address rd astb ad0 to ad7 a8 to a15 wait lower address read data higher address
430 chapter 20 external device expansion function user s manual u14046ej3v0ud figure 20-6. external memory write timing (a) no wait (pw1, pw0 = 0, 0) setting wr astb ad0 to ad7 a8 to a15 lower address write data higher address hi-z (b) wait (pw1, pw0 = 0, 1) setting wr astb ad0 to ad7 a8 to a15 internal wait signal (1-clock wait) lower address write data higher address hi-z (c) external wait (pw1, pw0 = 1, 1) setting wr astb ad0 to ad7 a8 to a15 wait lower address write data higher address hi-z
431 chapter 20 external device expansion function user s manual u14046ej3v0ud figure 20-7. external memory read modify write timing (a) no wait (pw1, pw0 = 0, 0) setting (b) wait (pw1, pw0 = 0, 1) setting (c) external wait (pw1, pw0 = 1, 1) setting read data write data higher address hi-z lower address rd astb ad0 to ad7 a8 to a15 wr rd astb ad0 to ad7 a8 to a15 hi-z wr write data higher address internal wait signal (1-clock wait) read data lower address wait hi-z rd astb ad0 to ad7 a8 to a15 wr write data higher address read data lower address remark the read-modify-write timing is that of an operation when a bit manipulation instruction is executed.
432 chapter 20 external device expansion function user s manual u14046ej3v0ud rd wr a8 to a14 astb ad0 to ad7 v dd0 74hc573 le d0 to d7 oe q0 to q7 pd43256b cs oe we i/o1 to i/o8 a0 to a14 data bus pd780024a address bus 20.4 example of connection with memory this section provide an example of connecting the pd780024a with external memory (in this example, sram) in figure 20-8. in addition, the external device expansion function is used in the full-address mode, and the addresses from 0000h to 7fffh (32 kb) are allocated for internal rom, and the addresses after 8000h for sram. figure 20-8. connection example of pd780024a and memory
433 user? manual u14046ej3v0ud chapter 21 standby function 21.1 standby function and configuration 21.1.1 standby function the standby function is designed to decrease power consumption of the system. the following two modes are available. (1) halt mode halt instruction execution sets the halt mode. the halt mode stops the cpu operation clock. the system clock oscillator continues oscillating. in this mode, power consumption is not decreased as much as in the stop mode. however, the halt mode is effective to restart operation immediately upon an interrupt request and to carry out intermittent operations. (2) stop mode stop instruction execution sets the stop mode. in the stop mode, the main system clock oscillator stops, stopping the whole system, thereby considerably reducing the cpu power consumption. data memory low-voltage hold (down to v dd = 1.6 v) is possible. thus, the stop mode is effective to hold data memory contents with ultra-low power consumption. because this mode can be released upon an interrupt request, it enables intermittent operations to be carried out. however, because a wait time is required to stabilize oscillation after the stop mode is released, select the halt mode if it is necessary to start processing immediately upon an interrupt request. in either of these two modes, all the contents of registers, flags and data memory just before the standby mode is set are held. the i/o port output latches and output buffer statuses are also held. cautions 1. the stop mode can be used only when the system operates with the main system clock (subsystem clock oscillation cannot be stopped). the halt mode can be used with either the main system clock or the subsystem clock. 2. when operation is transferred to the stop mode, be sure to stop operation of the peripheral hardware operating with the main system clock before executing the stop instruction. 3. the following sequence is recommended for reducing the power consumption of the a/d converter when the standby function is used: first clear bit 7 (adcs0) of a/d converter mode register 0 (adm0) to 0 to stop the a/d conversion operation, and then execute the halt or stop instruction.
434 chapter 21 standby function user? manual u14046ej3v0ud 21.1.2 standby function control register the wait time after the stop mode is released upon an interrupt request is controlled by the oscillation stabilization time select register (osts). osts is set by an 8-bit memory manipulation instruction. reset input sets osts to 04h. therefore, when the stop mode is released by inputting reset, it takes 2 17 / f x until release. figure 21-1. format of oscillation stabilization time select register (osts) address: fffah after reset: 04h r/w symbol 76543210 osts 00000 osts2 osts1 osts0 osts2 osts1 osts0 selection of oscillation stabilization time f x = 8.38 mhz f x = 12 mhz note 0002 12 /f x 488 s 341 s 0012 14 /f x 1.95 ms 1.36 ms 0102 15 /f x 3.91 ms 2.73 ms 0112 16 /f x 7.82 ms 5.46 ms 1002 17 /f x 15.6 ms 10.9 ms other than above setting prohibited note expanded-specification products of pd780024a, 780034a subseries only. caution the wait time after the stop mode is released does not include the time (see ??in the illustration below) from stop mode release to clock oscillation start. this applies regardless of whether stop mode is released by reset input or by interrupt request generation. stop mode release x1 pin voltage waveform a remark f x : main system clock oscillation frequency
435 chapter 21 standby function user s manual u14046ej3v0ud 21.2 standby function operations 21.2.1 halt mode (1) halt mode setting and operating statuses the halt mode is set by executing the halt instruction. it can be set with the main system clock or the subsystem clock. the operating statuses in the halt mode are described below. table 21-1. halt mode operating statuses halt mode halt instruction execution when halt instruction execution when setting using main system clock using subsystem clock without subsystem with subsystem with main system with main system clock note 1 clock note 2 clock oscillation clock oscillation item stopped clock generator both main system clock and subsystem clock can be oscillated. clock supply to cpu stops. cpu operation stops. ports (output latches) status before halt mode setting is held. 16-bit timer/event operable stop counter 0 8-bit timer/event operable operable when ti50, counters 50, 51 ti51 are selected as count clock. watch timer operable when f x /2 7 is operable operable when f xt is selected as count clock. selected as count clock. watchdog timer operable operation stops. clock output operable when f x to f x /2 7 operable operable when f xt is is selected as output clock. selected as output clock. buzzer output operable buz is at low level. a/d converter stop serial interface operable operable during external clock input. external interrupt operable bus line ad0 to ad7 high impedance during a8 to a15 status before halt mode setting is held. external astb low level expansion wr, rd high level wait high impedance notes 1. including case when external clock is not supplied. 2. including case when external clock is supplied.
436 chapter 21 standby function user s manual u14046ej3v0ud (2) halt mode release the halt mode can be released with the following three types of sources. (a) release by unmasked interrupt request when an unmasked interrupt request is generated, the halt mode is released. if interrupt acknowledge is enabled, vectored interrupt service is carried out. if interrupt acknowledge is disabled, the next address instruction is executed. figure 21-2. halt mode release by interrupt request generation halt instruction wait wait operating mode halt mode operating mode oscillation clock standby release signal interrupt request remarks 1. the broken line indicates the case when the interrupt request which has released the standby mode is acknowledged. 2. wait times are as follows: when vectored interrupt service is carried out: 8 or 9 clocks when vectored interrupt service is not carried out: 2 or 3 clocks (b) release by non-maskable interrupt request when a non-maskable interrupt request is generated, the halt mode is released and vectored interrupt service is carried out whether interrupt acknowledge is enabled or disabled. however, a non-maskable interrupt request is not generated during subsystem clock operation.
437 chapter 21 standby function user s manual u14046ej3v0ud (c) release by reset input when reset signal is input, halt mode is released. and, as in the case with normal reset operation, a program is executed after branch to the reset vector address. figure 21-3. halt mode release by reset input halt instruction wait (2 17 /f x : 15.6 ms) oscillation stabilization wait status operating mode halt mode operating mode oscillation stop clock reset signal oscillation oscillation reset period remarks 1. f x : main system clock oscillation frequency 2. values in parentheses are for operation with f x = 8.38 mhz. table 21-2. operation after halt mode release release source mk pr ie isp operation maskable interrupt request 0 0 0 next address instruction execution 001 interrupt service execution 0101 next address instruction execution 01 0 0111 interrupt service execution 1 halt mode hold non-maskable interrupt request ?? interrupt service execution reset input ?? reset processing : don t care
438 chapter 21 standby function user? manual u14046ej3v0ud 21.2.2 stop mode (1) stop mode setting and operating statuses the stop mode is set by executing the stop instruction. it can be set only with the main system clock. cautions 1. when the stop mode is set, the x2 pin is internally connected to v dd1 via a pull-up resistor to minimize the leakage current at the crystal oscillator. thus, do not use the stop mode in a system where an external clock is used for the main system clock. 2. because the interrupt request signal is used to clear the standby mode, if there is an interrupt source with the interrupt request flag set and the interrupt mask flag reset, the standby mode is immediately cleared if set. thus, the stop mode is reset to the halt mode immediately after execution of the stop instruction. the operating mode is set after the wait set using the oscillation stabilization time select register (osts). the operating statuses in the stop mode are described below. table 21-3. stop mode operating statuses stop mode setting with subsystem clock without subsystem clock item clock generator only main system clock oscillation is stopped. cpu operation stops. ports (output latches) status before stop mode setting is held. 16-bit timer/event counter 0 operation stops. 8-bit timer/event counters 50, 51 operable only when ti50, ti51 are selected as count clock. watch timer operable only when f xt is selected as operation stops. count clock. watchdog timer operation stops. clock output operable when f xt is selected as pcl is at low level. output clock. buzzer output buz is at low level. a/d converter operation stops. serial interface other than uart0 operable only when externally supplied clock is specified as the serial clock. uart0 operation stops. (transmit shift register 0 (txs0), receive shift register 0 (rx0), and receive buffer register 0 (rxb0) hold the value just before the clock stopped.) external interrupt operable bus line during ad0 to ad7 high impedance external expansion a8 to a15 status before stop mode setting is held. astb low level wr, rd high level wait high impedance
439 chapter 21 standby function user s manual u14046ej3v0ud (2) stop mode release the stop mode can be released by the following two types of sources. (a) release by unmasked interrupt request when an unmasked interrupt request is generated, the stop mode is released. if interrupt acknowledge is enabled after the lapse of oscillation stabilization time, vectored interrupt service is carried out. if interrupt acknowledge is disabled, the next address instruction is executed. figure 21-4. stop mode release by interrupt request generation stop instruction wait (time set by osts) oscillation stabilization wait status operating mode stop mode operating mode oscillation clock standby release signal oscillation stop oscillation interrupt request remark the broken line indicates the case when the interrupt request which has released the standby mode is acknowledged.
440 chapter 21 standby function user s manual u14046ej3v0ud (b) release by reset input the stop mode is released when reset signal is input, and after the lapse of oscillation stabilization time, reset operation is carried out. figure 21-5. stop mode release by reset input stop instruction wait (2 17 /f x : 15.6 ms) oscillation stabilization wait status operating mode stop mode operating mode oscillation stop clock reset signal oscillation oscillation reset period remarks 1. f x : main system clock oscillation frequency 2. values in parentheses are for operation with f x = 8.38 mhz. table 21-4. operation after stop mode release release source mk pr ie isp operation maskable interrupt request 0 0 0 next address instruction execution 001 interrupt service execution 0101 next address instruction execution 01 0 0111 interrupt service execution 1 stop mode hold reset input ?? reset processing : don t care
441 user? manual u14046ej3v0ud chapter 22 reset function the following two operations are available to generate the reset signal. (1) external reset input via reset pin (2) internal reset by watchdog timer program loop time detection external reset and internal reset have no functional differences. in both cases, program execution starts at the address at 0000h and 0001h by reset input. when a low level is input to the reset pin or the watchdog timer overflows, a reset is applied and each hardware is set to the status shown in table 22-1. each pin has high impedance during reset input or during oscillation stabilization time just after reset release. when a high level is input to the reset pin, the reset is released and program execution starts after the lapse of oscillation stabilization time (2 17 /f x ). the reset applied by watchdog timer overflow is automatically released after a reset and program execution starts after the lapse of oscillation stabilization time (2 17 /f x ) (see figures 22-2 to 22-4 ). cautions 1. for an external reset, input a low level for 10 s or more to the reset pin. 2. during reset input, main system clock oscillation remains stopped but subsystem clock oscillation continues. 3. when the stop mode is released by reset, the stop mode contents are held during reset input. however, the port pin becomes high impedance. figure 22-1. reset function block diagram reset count clock reset controller watchdog timer stop overflow reset signal interrupt function
442 chapter 22 reset function user s manual u14046ej3v0ud figure 22-2. timing of reset by reset input delay delay hi-z normal operation reset period (oscillation stop) oscillation stabilization time wait normal operation (reset processing) x1 reset internal reset signal port pin figure 22-3. timing of reset due to watchdog timer overflow hi-z normal operation reset period (oscillation stop) oscillation stabilization time wait normal operation (reset processing) x1 watchdog timer overflow internal reset signal port pin figure 22-4. timing of reset in stop mode by reset input delay delay hi-z normal operation oscillation stabilization time wait normal operation (reset processing) x1 reset internal reset signal port pin stop status (oscillation stop) stop instruction execution reset period (oscillation stop)
443 chapter 22 reset function user s manual u14046ej3v0ud table 22-1. hardware statuses after reset (1/2) hardware status after reset program counter (pc) note 1 contents of reset vector table (0000h, 0001h) are set. stack pointer (sp) undefined program status word (psw) 02h ram data memory undefined note 2 general-purpose register undefined note 2 port (output latch) 00h port mode registers 0, 2 to 7 (pm0, pm2 to pm7) ffh pull-up resistor option registers 0, 2 to 7 (pu0, pu2 to pu7) 00h processor clock control register (pcc) 04h memory size switching register (ims) cfh note 3 memory expansion mode register (mem) 00h memory expansion wait setting register (mm) 10h oscillation stabilization time select register (osts) 04h 16-bit timer/event counter 0 timer counter 0 (tm0) 0000h capture/compare registers 00, 01 (cr00, cr01) undefined prescaler mode register 0 (prm0) 00h capture/compare control register 0 (crc0) 00h mode control register 0 (tmc0) 00h output control register 0 (toc0) 00h 8-bit timer/event counters 50, 51 timer counters 50, 51 (tm50, tm51) 00h compare registers 50, 51 (cr50, cr51) undefined clock select registers 50, 51 (tcl50, tcl51) 00h mode control registers 50, 51 (tmc50, tmc51) 00h watch timer operation mode register (wtm) 00h watchdog timer clock select register (wdcs) 00h mode register (wdtm) 00h notes 1. during reset input or oscillation stabilization time wait, only the pc contents among the hardware statuses become undefined. all other hardware statuses remain unchanged after reset. 2. when a reset is executed in the standby mode, the pre-reset status is held even after reset. 3. although the initial value is cfh, use the following value to be set for each version. pd780021a, 780021ay, 780031a, 780031ay: 42h pd780022a, 780022ay, 780032a, 780032ay: 44h pd780023a, 780023ay, 780033a, 780033ay: c6h pd780024a, 780024ay, 780034a, 780034ay: c8h pd78f0034a, 78f0034b, 78f0034ay, 78f0034by: value for mask rom versions
444 chapter 22 reset function user s manual u14046ej3v0ud table 22-1. hardware statuses after reset (2/2) hardware status after reset clock output/buzzer output controller clock output select register (cks) 00h a/d converter conversion result register 0 (adcr0) 00h mode register 0 (adm0) 00h analog input channel specification register 0 (ads0) 00h serial interface uart0 asynchronous serial interface mode register 0 (asim0) 00h asynchronous serial interface status register 0 (asis0) 00h baud rate generator control register 0 (brgc0) 00h transmit shift register 0 (txs0) ffh receive buffer register 0 (rxb0) serial interfaces sio30, sio31 note 1 shift registers 30, 31 (sio30, sio31) undefined operation mode registers 30, 31 (csim30, csim31) 00h serial interface iic0 note 2 transfer clock select register 0 (iiccl0) 00h shift register 0 (iic0) 00h control register 0 (iicc0) 00h status register 0 (iics0) 00h slave address register 0 (sva0) 00h interrupt request flag registers 0l, 0h, 1l (if0l, if0h, if1l) 00h mask flag registers 0l, 0h, 1l (mk0l, mk0h, mk1l) ffh priority specification flag registers 0l, 0h, 1l (pr0l, ffh pr0h, pr1l) external interrupt rising edge enable register (egp) 00h external interrupt falling edge enable register (egn) 00h notes 1. serial interface sio31 is provided only in the pd780024a, 780034a subseries. 2. serial interface iic0 is provided only in the pd780024ay, 780034ay subseries.
445 user? manual u14046ej3v0ud chapter 23 pd78f0034a, 78f0034b, 78f0034ay, 78f0034by the pd78f0034a, 78f0034b, 78f0034ay, and 78f0034by are provided as the flash memory versions of the pd780024a, 780034a, 780024ay, 780034ay subseries. the pd78f0034a, 78f0034b, 78f0034ay, and 78f0034by are products that incorporate flash memory in which the program can be written, erased, and rewritten while it is mounted on the board. writing to flash memory can be performed with the memory mounted on the target system (on board). a dedicated flash programmer is connected to the target system to perform writing. the following can be considered as the development environment and the applications using flash memory. software can be altered after the pd78f0034a, 78f0034b, 78f0034ay, and 78f0034by are solder- mounted on the target system. small scale production of various models is made easier by differentiating software. data adjustment in starting mass production is made easier. table 23-1 shows the correspondence between pd78f0034a, 78f0034b, 78f0034ay, 78f0034by and the mask rom versions. table 23-1. correspondence between pd78f0034a, 78f0034b, 78f0034ay, 78f0034by, and mask rom versions mask rom version pd780021a/22a/ pd780021a(a)/ pd780021ay/ pd780021ay(a)/ 23a/24a/31a/32a/ 22a(a)/23a(a)/24a(a)/ 22ay/23ay/24ay/ 22ay(a)/23ay(a)/ 33a/34a 31a(a)/32a(a)/33a(a)/ 31ay/32ay/33ay/ 24ay(a)/31ay(a)/ 34a(a) 34ay 32ay(a)/33ay(a)/ conventional expanded- conventional expanded- 34ay(a) flash memory products specification products specification version products products pd78f0034a ??? ? ? pd78f0034b ??? ? ? pd78f0034b(a) ?? note ? ? pd78f0034ay ???? ? pd78f0034by ???? ? pd78f0034by(a) ???? ? note the pd78f0034b(a) and the conventional products of the pd780021a(a), 780022a(a), 780023a(a), 780024a(a), 780031a(a), 780032a(a), 780033a(a), and 780034a(a) differ in the operating frequency. when replacing a flash memory version with a mask rom version, note the supply voltage and operating frequency. remarks 1. : supported, ? : not supported 2. expanded-specification products and conventional products of the pd780024a and 780034a subseries differ in operating frequency ratings. for details, refer to the description of electrical specifications. 3. expanded-specification products of the pd780024ay, 780034ay subseries are not available. only conventional products are available. 4. a special grade product of the pd78f0034a, 78f0034ay is not available. only a standard grade product is available.
chapter 23 pd78f0034a, 78f0034b, 78f0034ay, 78f0034by 446 user? manual u14046ej3v0ud 23.1 differences between pd78f0034a, 78f0034ay and pd78f0034b, 78f0034by table 23-2 shows the differences between the pd78f0034a and pd78f0034b, and table 23-3 shows differences between the pd78f0034ay and pd78f0034by. table 23-2. differences between pd78f0034a and pd78f0034b item pd78f0034a pd78f0034b guaranteed operating speed 4.5 to 5.5 v 8.38 mhz (0.238 s) 12 mhz (0.166 s) (operating frequency) 4.0 to 5.5 v 8.38 mhz (0.238 s) 8.38 mhz (0.238 s) 3.0 to 5.5 v 5 mhz (0.4 s) 8.38 mhz (0.238 s) 2.7 to 5.5 v 5 mhz (0.4 s) 5 mhz (0.4 s) 1.8 to 5.5 v 1.25 mhz (1.6 s) 1.25 mhz (1.6 s) minimum instruction execution time minimum instruction execution time variable function incorporated when main system clock is selected 0.238 s/0.477 s/0.954 s/1.90 s/3.81 s 0.166 s/0.333 s/0.666 s/1.33 s/2.66 s (@ 8.38 mhz operation, v dd = 4.0 to 5.5 v) (@ 12 mhz operation, v dd = 4.5 to 5.5 v) when subsystem clock is selected 122 s (32.768 khz) clock output ? 65.5 khz, 131 khz, 262 khz, 524 khz, ? 93.7 khz, 187 khz, 375 khz, 750 khz, 1.05 mhz, 2.10 mhz, 4.19 mhz, 8.38 1.5 mhz, 3 mhz, 6 mhz, 12 mhz (@ 12 mhz (@ 8.38 mhz operation with main mhz operation with main system clock) system clock) 32.768 khz (@ 32.768 khz operation ? 32.768 khz (@ 32.768 khz operation with subsystem clock) with subsystem clock) buzzer output 1.02 khz, 2.05 khz, 4.10 khz, 8.19 khz 1.46 khz, 2.92 khz, 5.85 khz, 11.7 khz (@ 8.38 mhz operation with main system (@ 12 mhz operation with main system clock) clock) communication mode of flash memory ? 3-wire serial i/o: 2 channels note ? 3-wire serial i/o: 2 channels note programming ? uart: 1 channel ? uart: 1 channel ? pseudo 3-wire serial i/o: 1 channel ? pseudo 3-wire serial i/o: 1 channel electrical specifications, recommended refer to the description of electrical specifications and recommended soldering conditions soldering conditions. note the pd78f0034a cannot use a handshake mode. the pd78f0034b can use one channel (serial interface sio30) as a handshake mode. remark the operating frequency ratings of the pd78f0034a and the conventional products of the mask rom versions of the pd780024a, 780034a subseries are the same. the operating frequency ratings of the pd78f0034b and the expanded-specification products of the mask rom versions of the pd780024a, 780034a subseries are the same.
chapter 23 pd78f0034a, 78f0034b, 78f0034ay, 78f0034by 447 user? manual u14046ej3v0ud table 23-3. differences between pd78f0034ay and pd78f0034by item pd78f0034ay pd78f0034by guaranteed operating speed 4.5 to 5.5 v 8.38 mhz (0.238 s) (operating frequency) 4.0 to 5.5 v 8.38 mhz (0.238 s) 3.0 to 5.5 v 5 mhz (0.4 s) 2.7 to 5.5 v 5 mhz (0.4 s) 1.8 to 5.5 v 1.25 mhz (1.6 s) minimum instruction execution time minimum instruction execution time variable function incorporated when main system clock is selected 0.238 s/0.477 s/0.954 s/1.90 s/3.81 s (@ 8.38 mhz operation, v dd = 4.0 to 5.5 v) when subsystem clock is selected 122 s (32.768 khz) clock output 65.5 khz, 131 khz, 262 khz, 524 khz, 1.05 mhz, 2.10 mhz, 4.19 mhz, 8.38 mhz (@ 8.38 mhz operation with main system clock) ? 32.768 khz (@ 32.768 khz operation with subsystem clock) buzzer output 1.02 khz, 2.05 khz, 4.10 khz, 8.19 khz (@ 8.38 mhz operation with main system clock) communication mode of flash memory ? 3-wire serial i/o: 2 channels note ? 3-wire serial i/o: 2 channels note programming ? uart: 1 channel ? uart: 1 channel ? pseudo 3-wire serial i/o: 1 channel ? pseudo 3-wire serial i/o: 1 channel electrical specifications, recommended refer to the description of electrical specifications and recommended soldering conditions soldering conditions. note the pd78f0034ay cannot use a handshake mode. the pd78f0034by can use one channel (serial interface sio30) as a handshake mode. remark the operating frequency ratings of the pd78f0034ay, 78f0034by and the mask rom versions of the pd780024ay, 780034ay subseries are the same. 23.2 differences between pd78f0034b, 78f0034by and pd78f0034b(a), 78f0034by(a) the pd78f0034b(a) and 78f0034by(a) are products to which a quality assurance program more stringent than that used for the pd78f0034b and 78f0034by (standard products) is applied (nec electronics classifies these products as ?pecial?quality grade products). the pd78f0034b, 78f0034by and pd78f0034b(a), 78f0034by(a) only differ in the quality grade; there are no differences in functions and electrical specifications. table 23-4. differences between pd78f0034b, 78f0034by and pd78f0034b(a), 78f0034by(a) item pd78f0034b, 78f0034by pd78f0034b(a), 78f0034by(a) quality grade standard special functions and electrical specifications no differences. this chapter explains the pd78f0034b as the representative product of the pd78f0034b and 78f0034b(a), and the pd78f0034by as the representative product of the pd78f0034by and 78f0034by(a).
chapter 23 pd78f0034a, 78f0034b, 78f0034ay, 78f0034by 448 user? manual u14046ej3v0ud 23.3 differences between pd78f0034a, 78f0034b, 78f0034ay, 78f0034by and mask rom versions tables 23-5 and 23-6 show the differences between the pd78f0034a, 78f0034b, 78f0034ay, 78f0034by and the mask rom versions. table 23-5. differences between pd78f0034a, 78f0034b and mask rom versions item pd78f0034a, 78f0034b mask rom versions pd780034a subseries pd780024a subseries note internal rom structure flash memory mask rom internal rom capacity 32 kb pd780031a: 8 kb pd780021a: 8 kb pd780032a: 16 kb pd780022a: 16 kb pd780033a: 24 kb pd780023a: 24 kb pd780034a: 32 kb pd780024a: 32 kb internal high-speed ram capacity 1,024 bytes pd780031a: 512 bytes pd780021a: 512 bytes pd780032a: 512 bytes pd780022a: 512 bytes pd780033a: 1,024 bytes pd780023a: 1,024 bytes pd780034a: 1,024 bytes pd780024a: 1,024 bytes minimum instruction execution time minimum instruction execution time variable function incorporated when main system clock is selected 0.166 s/0.333 s/0.666 s/1.33 s/2.66 s (@ 12 mhz operation, pd78f0034b and expanded-specification products of the mask rom versions only ) ?0.238 s/0.477 s/0.954 s/1.90 s/3.81 s (@ 8.38 mhz operation) when subsystem clock is selected 122 s (@32.768 khz operation) clock output ?93.7 khz, 187 khz, 375 khz, 750 khz, 1.5 mhz, 3 mhz, 6 mhz, 12 mhz (@ 12 mhz operation with main system clock, pd78f0034b and expanded- specification products of the mask rom versions only) ?65.5 khz, 131 khz, 262 khz, 524 khz, 1.05 mhz, 2.10 mhz, 4.19 mhz, 8.38 mhz (@ 8.38 mhz operation with main system clock) ?32.768 khz (@ 32.768 khz operation with subsystem clock) buzzer output ?1.46 khz, 2.92 khz, 5.85 khz, 11.7 khz (@ 12 mhz operation with main system clock, pd78f0034b and expanded-specification products of the mask rom versions only) ? 1.02 khz, 2.05 khz, 4.10 khz, 8.19 khz (@ 8.38 mhz operation with main system clock) a/d converter resolution 10 bits 8 bits mask option specification of on-chip not available available pull-up resistor for pins p30 to p33 ic pin not provided provided v pp pin provided not provided electrical specifications, refer to the description of electrical specifications and recommended soldering recommended soldering conditions conditions. note the pd78f0034a and 78f0034b can be used as the flash memory version of the pd780024a subseries. caution there are differences in noise immunity and noise radiation between the flash memory and mask rom versions. when pre-producing an application set with the flash memory version and then mass producing it with the mask rom version, be sure to conduct sufficient evaluations on the commercial samples (cs) (not engineering samples (es)) of the mask rom versions.
chapter 23 pd78f0034a, 78f0034b, 78f0034ay, 78f0034by 449 user? manual u14046ej3v0ud table 23-6. differences between pd78f0034ay, 78f0034by and mask rom versions item pd78f0034ay, mask rom versions 78f0034by pd780034ay subseries pd780024ay subseries note internal rom structure flash memory mask rom internal rom capacity 32 kb pd780031ay: 8 kb pd780021ay: 8 kb pd780032ay: 16 kb pd780022ay: 16 kb pd780033ay: 24 kb pd780023ay: 24 kb pd780034ay: 32 kb pd780024ay: 32 kb internal high-speed ram capacity 1,024 bytes pd780031ay: 512 bytes pd780021ay: 512 bytes pd780032ay: 512 bytes pd780022ay: 512 bytes pd780033ay: 1,024 bytes pd780023ay: 1,024 bytes pd780034ay: 1,024 bytes pd780024ay: 1,024 bytes minimum instruction execution time minimum instruction execution time variable function incorporated when main system clock is selected 0.238 s/0.477 s/0.954 s/1.90 s/3.81 s (@8.38 mhz operation) when subsystem clock is selected 122 s (@32.768 khz operation) clock output 65.5 khz, 131 khz, 262 khz, 524 khz, 1.05 mhz, 2.10 mhz, 4.19 mhz, 8.38 mhz (@ 8.38 mhz operation with main system clock) 32.768 khz (@ 32.768 khz operation with subsystem clock) buzzer output 1.02 khz, 2.05 khz, 4.10 khz, 8.19 khz (@ 8.38 mhz operation with main system clock) a/d converter resolution 10 bits 8 bits mask option specification of on-chip not available available pull-up resistor for pins p30 and p31 ic pin not provided provided v pp pin provided not provided electrical specifications, refer to the description of electrical specifications and recommended soldering recommended soldering conditions conditions. note the pd78f0034ay and 78f0034by can be used as the flash memory version of the pd780024ay subseries. caution there are differences in noise immunity and noise radiation between the flash memory and mask rom versions. when pre-producing an application set with the flash memory version and then mass producing it with the mask rom version, be sure to conduct sufficient evaluations on the commercial samples (cs) (not engineering samples (es)) of the mask rom versions.
chapter 23 pd78f0034a, 78f0034b, 78f0034ay, 78f0034by 450 user? manual u14046ej3v0ud 23.4 memory size switching register the pd78f0034a, 78f0034b, 78f0034ay, and 78f0034by allow users to select the internal memory capacity using the memory size switching register (ims) so that the same memory map as that of the mask rom versions with a different size of internal memory capacity can be achieved. ims is set by an 8-bit memory manipulation instruction. reset input sets ims to cfh. caution be sure to set the value of the target mask rom version to ims as an initialization setting of the program. ims is set to cfh by reset, so be sure to set the value of the target mask rom version after reset. figure 23-1. format of memory size switching register (ims) address: fff0h after reset: cfh r/w symbol 76543210 ims ram2 ram1 ram0 0 rom3 rom2 rom1 rom0 ram2 ram1 ram0 internal high-speed ram capacity selection 0 1 0 512 bytes 1 1 0 1024 bytes other than above setting prohibited rom3 rom2 rom1 rom0 internal rom capacity selection 00108 kb 010016 kb 011024 kb 100032 kb 111160 kb (setting prohibited) other than above setting prohibited the ims settings to obtain the same memory map as mask rom versions are shown in table 23-7. table 23-7. memory size switching register settings target mask rom versions ims setting pd780021a, 780031a, 780021ay, 780031ay 42h pd780022a, 780032a, 780022ay, 780032ay 44h pd780023a, 780033a, 780023ay, 780033ay c6h pd780024a, 780034a, 780024ay, 780034ay c8h caution when using the mask rom versions, be sure to set the value indicated in table 23-7 to ims.
chapter 23 pd78f0034a, 78f0034b, 78f0034ay, 78f0034by 451 user? manual u14046ej3v0ud 23.5 flash memory characteristics flash memory programming is performed by connecting a dedicated flash programmer (flashpro iii (part no. fl- pr3, pg-fp3)/flashpro iv (part no. fl-pr4, pg-fp4)) to the target system with the flash memory mounted on the target system (on-board). a flash memory writing adapter (program adapter), which is a target board used exclusively for programming, is also provided. remark fl-pr3, fl-pr4, and the program adapter are products made by naito densei machida mfg. co., ltd. (tel +81-45-475-4191). programming using flash memory has the following advantages. software can be modified after the microcontroller is solder-mounted on the target system. distinguishing software facilities low-quantity, varied model production easy data adjustment when starting mass production 23.5.1 programming environment the following shows the environment required for pd78f0034a, 78f0034b, 78f0034ay, and 78f0034by flash memory programming. when flashpro iii or flashpro iv is used as a dedicated flash programmer, a host machine is required to control the dedicated flash programmer. communication between the host machine and flash programmer is performed via rs-232c/usb (rev. 1.1). for details, refer to the manuals of flashpro iii/flashpro iv. remark usb is supported by flashpro iv only. figure 23-2. environment for writing program to flash memory note iic is supported by the pd78f0034ay, 78f0034by only. rs-232c usb dedicated flash programmer pd78f0034a, pd78f0034b, pd78f0034ay, pd78f0034by v pp v dd v ss reset sio/uart/pseudo 3-wire/iic note host machine pg-fp4 (flash pro4) cxxxxxx bxxxxx axxxx xxx yyy xxxxx xxxxxx xxxx xxxx yyyy statve
chapter 23 pd78f0034a, 78f0034b, 78f0034ay, 78f0034by 452 user s manual u14046ej3v0ud 23.5.2 communication mode use the communication mode shown in table 23-8 to perform communication between the dedicated flash programmer and the pd78f0034a, 78f0034b, 78f0034ay, and 78f0034by. table 23-8. communication mode list (1/2) (1) pd78f0034a, 78f0034b communication standard (type) setting note 1 pins used number mode port speed on target frequency multiply of (comm port) (sio clock) (cpu (flashpro rate v pp clock) clock) (multiple rate) pulses 3-wire serial i/o sio-ch0 2.4 khz to 625 khz note 2 optional 1 to 10 mhz note 2 1.0 si30/p20 0 (sio30) (sio ch-0) (100 hz to 1.25 mhz) note 2 so30/p21 sck30/p22 3-wire serial i/o sio-ch1 si31/p34 1 (sio31) (sio ch-1) so31/p35 sck31/p36 3-wire serial i/o sio-h/s si30/p20 3 (sio30) (sio ch-3 + so30/p21 with handshake handshake) sck30/p22 note 3 hs/p25 uart uart-ch0 4800 to 76800 baud notes 2, 4 r x d0/p23 8 (uart0) (uart ch-0) (4800 to 76800 bps) notes 2, 4 t x d0/p24 pseudo 3-wire port-ch0 100 hz to 1500 hz note 2 p70/ti00/to0 12 serial i/o (port a) (100 hz to 1.25 mhz) note 2 (serial data input) p71/ti01 (serial data output) p72/ti50/to50 (serial clock input) notes 1. selection items for standard settings on flashpro iv (type settings on flashpro iii). 2. the possible setting range differs depending on the voltage. for details, refer to the description of electrical specifications. 3. pd78f0034b only 4. because factors other than the baud rate error, such as the signal waveform slew, also affect uart communication, thoroughly evaluate the slew as well as the baud rate error. remark items enclosed in parentheses in the setting item column are the set value and set item of flashpro iii when they differ from those of flashpro iv.
chapter 23 pd78f0034a, 78f0034b, 78f0034ay, 78f0034by 453 user s manual u14046ej3v0ud table 23-8. communication mode list (2/2) (2) pd78f0034ay, 78f0034by communication standard (type) setting note 1 pins used number mode port speed on target frequency multiply of (comm port) (sio clock) (cpu (flashpro rate v pp clock) clock) (multiple rate) pulses 3-wire serial i/o sio-ch0 2.4 khz to 625 khz note 2 optional 1 to 10 mhz note 2 1.0 si30/p20 0 (sio30) (sio ch-0) (100 hz to 1.25 mhz) note 2 so30/p21 sck30/p22 3-wire serial i/o sio-h/s si30/p20 3 (sio30) (sio ch-3 + so30/p21 with handshake handshake) sck30/p22 note 3 hs/p25 i 2 c bus iic-ch0 10 k to 100 k band note 2 sda0/p32 4 (iic0) (i 2 c ch-0) (50 khz) note 2 scl0/p33 uart uart-ch0 4800 to 76800 baud notes 2, 4 r x d0/p23 8 (uart0) (uart ch-0) (4800 to 76800 bps) notes 2, 4 t x d0/p24 pseudo 3-wire port-ch0 100 hz to 1500 hz note 2 p70/ti00/to0 12 serial i/o (port a) (100 hz to 1.25 mhz) note 2 (serial data input) p71/ti01 (serial data output) p72/ti50/to50 (serial clock input) notes 1. selection items for standard settings on flashpro iv (type settings on flashpro iii). 2. the possible setting range differs depending on the voltage. for details, refer to the description of electrical specifications. 3. pd78f0034by only 4. because factors other than the baud rate error, such as the signal waveform slew, also affect uart communication, thoroughly evaluate the slew as well as the baud rate error. remark items enclosed in parentheses in the setting item column are the set value and set item of flashpro iii when they differ from those of flashpro iv. figure 23-3. communication mode selection format 10 v v pp v pp pulse flash memory write mode reset v dd v ss v dd v ss
chapter 23 pd78f0034a, 78f0034b, 78f0034ay, 78f0034by 454 user s manual u14046ej3v0ud figure 23-4. example of connection with dedicated flash programmer (1/2) (a) 3-wire serial i/o (sio3n note 1 ) dedicated flash programmer v pp v dd /reset sck so/txd si/rxd clk gnd v pp v dd0 , v dd1 , av dd note 4 reset sck3n si3n so3n x1 note 4 v ss0 , v ss1 , av ss , av ref flash memory version (b) 3-wire serial i/o (sio30) with handshake note 2 v pp v dd /reset sck so/txd si/rxd h/s gnd v pp v dd0 , v dd1 , av dd note 4 reset sck30 si3 so3 p25 (hs) clk x1 note 4 v ss0 , v ss1 , av ss , av ref flash memory version dedicated flash programmer (c) i 2 c bus (iic0) note 3 v pp v dd /reset sck si/rxd clk gnd v pp v dd0 , v dd1 , av dd note 4 reset scl0 sda0 x1 note 4 v ss0 , v ss1 , av ss , av ref flash memory version dedicated flash programmer notes 1. n = 0, 1: pd78f0034a, 78f0034b n = 0: pd78f0034ay, 78f0034by 2. pd78f0034b, 78f0034by only 3. pd78f0034ay, 78f0034by only 4. the v dd0 , v dd1 , av dd , and x1 pins can be supplied on board. in this case, these pins do not need to be connected to the dedicated flash programmer, but v dd voltage must be supplied to these pins (except the x1 pin) before programming is started.
chapter 23 pd78f0034a, 78f0034b, 78f0034ay, 78f0034by 455 user s manual u14046ej3v0ud figure 23-4. example of connection with dedicated flash programmer (2/2) (d) uart (uart0) v pp v dd /reset so/t x d si/r x d clk gnd v pp v dd0 , v dd1 , av dd note reset r x d0 t x d0 x1 note v ss0 , v ss1 , av ss , av ref flash memory version dedicated flash programmer (e) pseudo 3-wire serial i/o dedicated flash programmer v pp v dd /reset sck so/txd si/rxd clk gnd v pp v dd0 , v dd1 , av dd note reset p72 p70 p71 x1 note v ss0 , v ss1 , av ss , av ref flash memory version note the v dd0 , v dd1 , av dd , and x1 pins can be supplied on board. in this case, these pins do not need to be connected to the dedicated flash programmer, but v dd voltage must be supplied to these pins (except the x1 pin) before programming is started. if flashpro iii/flashpro iv is used as the dedicated flash programmer, the following signals are generated for the pd78f0034a, 78f0034b, 78f0034ay, and 78f0034by. for details, refer to the manual of flashpro iii/flashpro iv.
chapter 23 pd78f0034a, 78f0034b, 78f0034ay, 78f0034by 456 user s manual u14046ej3v0ud table 23-9. pin connection list signal name i/o pin function pin name sio30 sio31 sio30 uart0 iic0 pseudo note 1 (hs) note 3 3-wire note 2 v pp output write voltage v pp v dd i/o v dd voltage generation/voltage v dd0 , v dd1 , av dd note 4 note 4 note 4 note 4 note 4 note 4 monitoring gnd ? ground v ss0 , v ss1 , av ss , av ref clk output clock output x1 /reset output reset signal reset si/r x d input reception signal so30/so31 note 1 txd0/sda0 note 3 /p71 so/t x d output transmission signal si30/si31 note 1 /rxd0/ p70 sck output transfer clock sck30/sck31 note 1 / scl0 note 3 /p72 h/s input handshake signal p25 (hs) note 2 notes 1. pd78f0034a, 78f0034b only 2. pd78f0034b, 78f0034by only 3. pd78f0034ay, 78f0034by only 4. v dd voltage must be supplied before programming is started. remark : pin must be connected. : if the signal is supplied on the target board, pin does not need to be connected. : pin does not need to be connected.
chapter 23 pd78f0034a, 78f0034b, 78f0034ay, 78f0034by 457 user s manual u14046ej3v0ud 23.5.3 on-board pin processing when performing programming on the target system, provide a connector on the target system to connect the dedicated flash programmer. an on-board function that allows switching between normal operation mode and flash memory programming mode may be required in some cases. in normal operation mode, input 0 v to the v pp pin. in flash memory programming mode, a write voltage of 10.0 v (typ.) is supplied to the v pp pin, so perform the following. (1) connect a pull-down resistor (rv pp = 10 k ? ) to the v pp pin. (2) use the jumper on the board to switch the v pp pin input to either the programmer or directly to gnd. a v pp pin connection example is shown below. figure 23-5. v pp pin connection example the following shows the pins used by the serial interface. notes 1. pd78f0034a, 78f0034b only 2. pd78f0034b, 78f0034by only 3. pd78f0034ay, 78f0034by only when connecting the dedicated flash programmer to a serial interface pin that is connected to another device on-board, signal conflict or abnormal operation of the other device may occur. care must therefore be taken with such connections. serial interface pins used 3-wire serial i/o (sio30) si30/p20, so30/p21, sck30/p22 3-wire serial i/o (sio31) note 1 si31/p34, so31/p35, sck31/p36 3-wire serial i/o (sio30) si30/p20, so30/p21, sck30/p22, hs/p25 with handshake note 2 i 2 c bus (iic0) note 3 sda0/p32, scl0/p33 uart (uart0) r x d0/p23, t x d0/p24 pseudo 3-wire serial i/o p70/ti00/to0 (serial data input), p71/ti01 (serial data output), p72/ti50/to50 (serial clock input) pd78f0034a, 78f0034b, 78f0034ay, 78f0034by v pp connection pin of dedicated flash programmer pull-down resistor ( rv pp )
chapter 23 pd78f0034a, 78f0034b, 78f0034ay, 78f0034by 458 user s manual u14046ej3v0ud (1) signal conflict if the dedicated flash programmer (output) is connected to a serial interface pin (input) that is connected to another device (output), a signal conflict occurs. to prevent this, isolate the connection with the other device or set the other device to the output high impedance status. figure 23-6. signal conflict (input pin of serial interface) (2) abnormal operation of other device if the dedicated flash programmer (output or input) is connected to a serial interface pin (input or output) that is connected to another device (input), a signal is output to the device, which may cause an abnormal operation. to prevent this abnormal operation, isolate the connection with the other device or set so that the input signals to the other device are ignored. figure 23-7. abnormal operation of other device input pin signal conflict connection pin of dedicated flash programmer other device output pin in the flash memory programming mode, the signal output by another device and the signal sent by the dedicated flash programmer conflict, therefore, isolate the signal of the other device. flash memory version if the signal output by the pd78f0034a, 78f0034b, 78f0034ay, 78f0034by affects another device in the flash memory programming mode, isolate the signals of the other device. if the signal output by the dedicated flash programmer affects another device in the flash memory programming mode, isolate the signals of the other device. flash memory version flash memory version pin connection pin of dedicated flash programmer other device input pin pin connection pin of dedicated flash programmer other device input pin
chapter 23 pd78f0034a, 78f0034b, 78f0034ay, 78f0034by 459 user s manual u14046ej3v0ud if the reset signal of the dedicated flash programmer is connected to the reset pin connected to the reset signal generator on-board, a signal conflict occurs. to prevent this, isolate the connection with the reset signal generator. if the reset signal is input from the user system in the flash memory programming mode, a normal programming operation cannot be performed. therefore, do not input reset signals from other than the dedicated flash programmer. figure 23-8. signal conflict (reset pin) when the pd78f0034a, 78f0034b, 78f0034ay, and 78f0034by enter the flash memory programming mode, all the pins other than those that communicate in flash memory programming are in the same status as immediately after reset. if the external device does not recognize initial statuses such as the output high impedance status, therefore, connect the external device to v dd0 or v ss0 via a resistor. when using the on-board clock, connect x1, x2, xt1, and xt2 as required in the normal operation mode. when using the clock output of the flash programmer, connect it directly to x1, disconnecting the main oscillator on-board, and leave the x2 pin open. the subsystem clock conforms to the normal operation mode. to use the power output from the flash programmer, connect the v dd0 and v dd1 pins to v dd of the flash programmer, and the v ss0 and v ss1 pins to gnd of the flash programmer. to use the on-board power supply, make connections that accord with the normal operation mode. however, because the voltage is monitored by the flash programmer, be sure to connect v dd of the flash programmer. supply the same power as in the normal operation mode to the other power supply pins (av dd , av ref , and av ss ). reset connection pin of dedicated flash programmer reset signal generator signal conflict output pin the signal output by the reset signal generator and the signal output from the dedicated flash programmer conflict in the flash memory programming mode, so isolate the signal of the reset signal generator. flash memory version
chapter 23 pd78f0034a, 78f0034b, 78f0034ay, 78f0034by 460 user s manual u14046ej3v0ud 23.5.4 connection on adapter for flash memory writing examples of the recommended connection when using the adapter for flash memory writing are shown below. figure 23-9. example of wiring adapter for flash memory writing in 3-wire serial i/o (sio30) mode (1/2) (1) 64-pin plastic sdip (19.05 mm (750)) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 lvdd (vpp2) vdd gnd si so sck clkout reset pp writer interface reserve/hs vdd (2.7 to 5.5 v) gnd
chapter 23 pd78f0034a, 78f0034b, 78f0034ay, 78f0034by 461 user s manual u14046ej3v0ud figure 23-9. example of wiring adapter for flash memory writing in 3-wire serial i/o (sio30) mode (2/2) (2) 64-pin plastic qfp (14 14), 64-pin plastic lqfp (14 14), 64-pin plastic tqfp (12 12), 64-pin plastic lqfp (10 10) gnd vdd lvdd (vpp2) si so sck clkout reset vpp reserve/hs writer interface vdd (2.7 to 5.5 v) gnd 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
chapter 23 pd78f0034a, 78f0034b, 78f0034ay, 78f0034by 462 user s manual u14046ej3v0ud figure 23-10. example of wiring adapter for flash memory writing in 3-wire serial i/o (sio31) mode ( pd78f0034a, 78f0034b only) (1/2) (1) 64-pin plastic sdip (19.05 mm (750)) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 lvdd (vpp) vdd gnd si so sck clkout reset vpp writer interface reserve/hs vdd (2.7 to 5.5 v) gnd
chapter 23 pd78f0034a, 78f0034b, 78f0034ay, 78f0034by 463 user s manual u14046ej3v0ud figure 23-10. example of wiring adapter for flash memory writing in 3-wire serial i/o (sio31) mode ( pd78f0034a, 78f0034b only) (2/2) (2) 64-pin plastic qfp (14 14), 64-pin plastic lqfp (14 14), 64-pin plastic tqfp (12 12), 64-pin plastic lqfp (10 10) gnd vdd lvdd (vpp2) si so sck clkout reset vpp reserve/hs writer interface vdd (2.7 to 5.5 v) gnd 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
chapter 23 pd78f0034a, 78f0034b, 78f0034ay, 78f0034by 464 user s manual u14046ej3v0ud figure 23-11. example of wiring adapter for flash memory writing in 3-wire serial i/o (sio30 + hs) mode ( pd78f0034b, 78f0034by only) (1/2) (1) 64-pin plastic sdip (19.05 mm (750)) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 lvdd (vpp2) vdd gnd si so sck clkout reset vpp writer interface reserve/hs vdd (2.7 to 5.5 v) gnd
chapter 23 pd78f0034a, 78f0034b, 78f0034ay, 78f0034by 465 user s manual u14046ej3v0ud figure 23-11. example of wiring adapter for flash memory writing in 3-wire serial i/o (sio30 + hs) mode ( pd78f0034b, 78f0034by only) (2/2) (2) 64-pin plastic qfp (14 14), 64-pin plastic lqfp (14 14), 64-pin plastic tqfp (12 12), 64-pin plastic lqfp (10 10) gnd vdd lvdd (vpp2) si so sck clkout reset vpp reserve/hs writer interface vdd (2.7 to 5.5 v) gnd 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
chapter 23 pd78f0034a, 78f0034b, 78f0034ay, 78f0034by 466 user s manual u14046ej3v0ud figure 23-12. example of wiring adapter for flash memory writing in i 2 c bus (iic0) mode ( pd78f0034ay, 78f0034by only) (1/2) (1) 64-pin plastic sdip (19.05 mm (750)) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 lvdd (vpp2) vdd gnd si so sck clkout reset vpp writer interface reserve/hs vdd (2.7 to 5.5 v) gnd
chapter 23 pd78f0034a, 78f0034b, 78f0034ay, 78f0034by 467 user s manual u14046ej3v0ud figure 23-12. example of wiring adapter for flash memory writing in i 2 c bus (iic0) mode ( pd78f0034ay, 78f0034by only) (2/2) (2) 64-pin plastic qfp (14 14), 64-pin plastic lqfp (14 14), 64-pin plastic tqfp (12 12), 64-pin plastic lqfp (10 10) gnd vdd lvdd (vpp2) si so sck clkout reset vpp reserve/hs writer interface vdd (2.7 to 5.5 v) gnd 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
chapter 23 pd78f0034a, 78f0034b, 78f0034ay, 78f0034by 468 user s manual u14046ej3v0ud figure 23-13. example of wiring adapter for flash memory writing in uart (uart0) mode (1/2) (1) 64-pin plastic sdip (19.05 mm (750)) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 lvdd (vpp2) vdd gnd si so sck clkout reset vpp writer interface reserve/hs vdd (2.7 to 5.5 v) gnd
chapter 23 pd78f0034a, 78f0034b, 78f0034ay, 78f0034by 469 user s manual u14046ej3v0ud figure 23-13. example of wiring adapter for flash memory writing in uart (uart0) mode (2/2) (2) 64-pin plastic qfp (14 14), 64-pin plastic lqfp (14 14), 64-pin plastic tqfp (12 12), 64-pin plastic lqfp (10 10) gnd vdd lvdd (vpp2) si so sck clkout reset vpp reserve/hs writer interface vdd (2.7 to 5.5 v) gnd 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
chapter 23 pd78f0034a, 78f0034b, 78f0034ay, 78f0034by 470 user s manual u14046ej3v0ud figure 23-14. example of wiring adapter for flash memory writing in pseudo 3-wire serial i/o mode (1/2) (1) 64-pin plastic sdip (19.05 mm (750)) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 lvdd (vpp2) vdd gnd si so sck clkout reset vpp writer interface reserve/hs vdd (2.7 to 5.5 v) gnd
chapter 23 pd78f0034a, 78f0034b, 78f0034ay, 78f0034by 471 user s manual u14046ej3v0ud figure 23-14. example of wiring adapter for flash memory writing in pseudo 3-wire serial i/o mode (2/2) (2) 64-pin plastic qfp (14 14), 64-pin plastic lqfp (14 14), 64-pin plastic tqfp (12 12), 64-pin plastic lqfp (10 10) gnd vdd lvdd (vpp2) si so sck clkout reset vpp reserve/hs writer interface vdd (2.7 to 5.5 v) gnd 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
472 user? manual u14046ej3v0ud chapter 24 instruction set this chapter lists each instruction set of the pd780024a, 780034a, 780024ay, 780034ay subseries in table form. for details of its operation and operation code, refer to the separate document 78k/0 series instructions user? manual (u12326e) .
473 chapter 24 instruction set user? manual u14046ej3v0ud 24.1 conventions 24.1.1 operand identifiers and specification methods operands are written in ?perand?column of each instruction in accordance with the specification method of the instruction operand identifier (refer to the assembler specifications for detail). when there are two or more methods, select one of them. alphabetic letters in capitals and symbols, #, !, $, and [ ] are key words and must be written as they are. each symbol has the following meaning. #: immediate data specification !: absolute address specification $: relative address specification [ ]: indirect address specification in the case of immediate data, describe an appropriate numeric value or a label. when using a label, be sure to write the #, !, $, and [ ] symbols. for operand register identifiers, r and rp, either function names (x, a, c, etc.) or absolute names (names in parentheses in the table below, r0, r1, r2, etc.) can be used for specification. table 24-1. operand identifiers and specification methods identifier specification method r x (r0), a (r1), c (r2), b (r3), e (r4), d (r5), l (r6), h (r7) rp ax (rp0), bc (rp1), de (rp2), hl (rp3) sfr special function register symbol note sfrp special function register symbol (16-bit manipulatable register even addresses only) note saddr fe20h to ff1fh immediate data or labels saddrp fe20h to ff1fh immediate data or labels (even address only) addr16 0000h to ffffh immediate data or labels (only even addresses for 16-bit data transfer instructions) addr11 0800h to 0fffh immediate data or labels addr5 0040h to 007fh immediate data or labels (even address only) word 16-bit immediate data or label byte 8-bit immediate data or label bit 3-bit immediate data or label rbn rb0 to rb3 note addresses from ffd0h to ffdfh cannot be accessed with these operands. remark for special function register symbols, see table 5-5 special function register list .
474 chapter 24 instruction set user? manual u14046ej3v0ud 24.1.2 description of ?peration?column a: a register; 8-bit accumulator x: x register b: b register c: c register d: d register e: e register h: h register l: l register ax: ax register pair; 16-bit accumulator bc: bc register pair de: de register pair hl: hl register pair pc: program counter sp: stack pointer psw: program status word cy: carry flag ac: auxiliary carry flag z: zero flag rbs: register bank select flag ie: interrupt request enable flag nmis: non-maskable interrupt servicing flag ( ): memory contents indicated by address or register contents in parentheses x h , x l : higher 8 bits and lower 8 bits of 16-bit register : logical product (and) : logical sum (or) : exclusive logical sum (exclusive or) : inverted data addr16: 16-bit immediate data or label jdisp8: signed 8-bit data (displacement value) 24.1.3 description of ?lag operation?column (blank): not affected 0: cleared to 0 1: set to 1 : set/cleared according to the result r: previously saved value is restored
475 chapter 24 instruction set user? manual u14046ej3v0ud 24.2 operation list instruction mnemonic operands byte clock operation flag group note 1 note 2 zaccy mov r, #byte 2 4 r byte saddr, #byte 3 6 7 (saddr) byte sfr, #byte 3 7 sfr byte a, r note 3 12 a r r, a note 3 12 r a a, saddr 2 4 5 a (saddr) saddr, a 2 4 5 (saddr) a a, sfr 2 5 a sfr sfr, a 2 5 sfr a a, !addr16 3 8 9 + n a (addr16) !addr16, a 3 8 9 + m (addr16) a psw, #byte 3 7 psw byte a, psw 2 5 a psw psw, a 2 5 psw a a, [de] 1 4 5 + n a (de) [de], a 1 4 5 + m (de) a a, [hl] 1 4 5 + n a (hl) [hl], a 1 4 5 + m (hl) a a, [hl + byte] 2 8 9 + n a (hl + byte) [hl + byte], a 2 8 9 + m (hl + byte) a a, [hl + b] 1 6 7 + n a (hl + b) [hl + b], a 1 6 7 + m (hl + b) a a, [hl + c] 1 6 7 + n a (hl + c) [hl + c], a 1 6 7 + m (hl + c) a xch a, r note 3 12 a ? r a, saddr 2 4 6 a ? (saddr) a, sfr 2 6 a ? (sfr) a, !addr16 3 8 10 + n + m a ? (addr16) a, [de] 1 4 6 + n + m a ? (de) a, [hl] 1 4 6 + n + m a ? (hl) a, [hl + byte] 2 8 10 + n + m a ? (hl + byte) a, [hl + b] 2 8 10 + n + m a ? (hl + b) a, [hl + c] 2 8 10 + n + m a ? (hl + c) notes 1. when the internal high-speed ram area is accessed or instruction with no data access 2. when an area except the internal high-speed ram area is accessed 3. except r = a remarks 1. one instruction clock cycle is one cycle of the cpu clock (f cpu ) selected by the processor clock control register (pcc). 2. this clock cycle applies to internal rom program. 3. n is the number of waits when external memory expansion area is read from. 4. m is the number of waits when external memory expansion area is written to. 8-bit data transfer
476 chapter 24 instruction set user? manual u14046ej3v0ud instruction mnemonic operands byte clock operation flag group note 1 note 2 zaccy movw rp, #word 3 6 rp word saddrp, #word 4 8 10 (saddrp) word sfrp, #word 4 10 sfrp word ax, saddrp 2 6 8 ax (saddrp) saddrp, ax 2 6 8 (saddrp) ax ax, sfrp 2 8 ax sfrp sfrp, ax 2 8 sfrp ax ax, rp note 3 1 4 ax rp rp, ax note 3 1 4 rp ax ax, !addr16 3 10 12 + 2n ax (addr16) !addr16, ax 3 10 12 + 2m (addr16) ax xchw ax, rp note 3 1 4 ax ? rp add a, #byte 2 4 a, cy a + byte saddr, #byte 3 6 8 (saddr), cy (saddr) + byte a, r note 4 2 4 a, cy a + r r, a 2 4 r, cy r + a a, saddr 2 4 5 a, cy a + (saddr) a, !addr16 3 8 9 + n a, cy a + (addr16) a, [hl] 1 4 5 + n a, cy a + (hl) a, [hl + byte] 2 8 9 + n a, cy a + (hl + byte) a, [hl + b] 2 8 9 + n a, cy a + (hl + b) a, [hl + c] 2 8 9 + n a, cy a + (hl + c) addc a, #byte 2 4 a, cy a + byte + cy saddr, #byte 3 6 8 (saddr), cy (saddr) + byte + cy a, r note 4 2 4 a, cy a + r + cy r, a 2 4 r, cy r + a + cy a, saddr 2 4 5 a, cy a + (saddr) + cy a, !addr16 3 8 9 + n a, cy a + (addr16) + cy a, [hl] 1 4 5 + n a, cy a + (hl) + cy a, [hl + byte] 2 8 9 + n a, cy a + (hl + byte) + cy a, [hl + b] 2 8 9 + n a, cy a + (hl + b) + cy a, [hl + c] 2 8 9 + n a, cy a + (hl + c) + cy notes 1. when the internal high-speed ram area is accessed or instruction with no data access 2. when an area except the internal high-speed ram area is accessed 3. only when rp = bc, de or hl 4. except r = a remarks 1. one instruction clock cycle is one cycle of the cpu clock (f cpu ) selected by the processor clock control register (pcc). 2. this clock cycle applies to internal rom program. 3. n is the number of waits when external memory expansion area is read from. 4. m is the number of waits when external memory expansion area is written to. 16-bit data transfer 8-bit operation
477 chapter 24 instruction set user? manual u14046ej3v0ud instruction mnemonic operands byte clock operation flag group note 1 note 2 zaccy sub a, #byte 2 4 a, cy a ?byte saddr, #byte 3 6 8 (saddr), cy (saddr) ?byte a, r note 3 2 4 a, cy a ?r r, a 2 4 r, cy r ?a a, saddr 2 4 5 a, cy a ?(saddr) a, !addr16 3 8 9 + n a, cy a ?(addr16) a, [hl] 1 4 5 + n a, cy a ?(hl) a, [hl + byte] 2 8 9 + n a, cy a ?(hl + byte) a, [hl + b] 2 8 9 + n a, cy a ?(hl + b) a, [hl + c] 2 8 9 + n a, cy a ?(hl + c) subc a, #byte 2 4 a, cy a ?byte ?cy saddr, #byte 3 6 8 (saddr), cy (saddr) ?byte ?cy a, r note 3 2 4 a, cy a ?r ?cy r, a 2 4 r, cy r ?a ?cy a, saddr 2 4 5 a, cy a ?(saddr) ?cy a, !addr16 3 8 9 + n a, cy a ?(addr16) ?cy a, [hl] 1 4 5 + n a, cy a ?(hl) ?cy a, [hl + byte] 2 8 9 + n a, cy a ?(hl + byte) ?cy a, [hl + b] 2 8 9 + n a, cy a ?(hl + b) ?cy a, [hl + c] 2 8 9 + n a, cy a ?(hl + c) ?cy and a, #byte 2 4 a a byte saddr, #byte 3 6 8 (saddr) (saddr) byte a, r note 3 24 a a r r, a 2 4 r r a a, saddr 2 4 5 a a (saddr) a, !addr16 3 8 9 + n a a (addr16) a, [hl] 1 4 5 + n a a (hl) a, [hl + byte] 2 8 9 + n a a (hl + byte) a, [hl + b] 2 8 9 + n a a (hl + b) a, [hl + c] 2 8 9 + n a a (hl + c) notes 1. when the internal high-speed ram area is accessed or instruction with no data access 2. when an area except the internal high-speed ram area is accessed 3. except r = a remarks 1. one instruction clock cycle is one cycle of the cpu clock (f cpu ) selected by the processor clock control register (pcc). 2. this clock cycle applies to internal rom program. 3. n is the number of waits when external memory expansion area is read from. 8-bit operation
478 chapter 24 instruction set user? manual u14046ej3v0ud instruction mnemonic operands byte clock operation flag group note 1 note 2 zaccy or a, #byte 2 4 a a byte saddr, #byte 3 6 8 (saddr) (saddr) byte a, r note 3 24 a a r r, a 2 4 r r a a, saddr 2 4 5 a a (saddr) a, !addr16 3 8 9 + n a a (addr16) a, [hl] 1 4 5 + n a a (hl) a, [hl + byte] 2 8 9 + n a a (hl + byte) a, [hl + b] 2 8 9 + n a a (hl + b) a, [hl + c] 2 8 9 + n a a (hl + c) xor a, #byte 2 4 a a byte saddr, #byte 3 6 8 (saddr) (saddr) byte a, r note 3 24 a a r r, a 2 4 r r a a, saddr 2 4 5 a a (saddr) a, !addr16 3 8 9 + n a a (addr16) a, [hl] 1 4 5 + n a a (hl) a, [hl + byte] 2 8 9 + n a a (hl + byte) a, [hl + b] 2 8 9 + n a a (hl + b) a, [hl + c] 2 8 9 + n a a (hl + c) cmp a, #byte 2 4 a ?byte saddr, #byte 3 6 8 (saddr) ?byte a, r note 3 24 a r r, a 2 4 r ?a a, saddr 2 4 5 a ?(saddr) a, !addr16 3 8 9 + n a ?(addr16) a, [hl] 1 4 5 + n a ?(hl) a, [hl + byte] 2 8 9 + n a ?(hl + byte) a, [hl + b] 2 8 9 + n a ?(hl + b) a, [hl + c] 2 8 9 + n a ?(hl + c) notes 1. when the internal high-speed ram area is accessed or instruction with no data access 2. when an area except the internal high-speed ram area is accessed 3. except r = a remarks 1. one instruction clock cycle is one cycle of the cpu clock (f cpu ) selected by the processor clock control register (pcc). 2. this clock cycle applies to internal rom program. 3. n is the number of waits when external memory expansion area is read from. 8-bit operation
479 chapter 24 instruction set user? manual u14046ej3v0ud instruction mnemonic operands byte clock operation flag group note 1 note 2 zaccy addw ax, #word 3 6 ax, cy ax + word subw ax, #word 3 6 ax, cy ax ?word cmpw ax, #word 3 6 ax ?word mulu x 2 16 ax a x divuw c 2 25 ax (quotient), c (remainder) ax c inc r12r r + 1 saddr 2 4 6 (saddr) (saddr) + 1 dec r12r r ?1 saddr 2 4 6 (saddr) (saddr) ?1 incw rp 1 4 rp rp + 1 decw rp 1 4 rp rp ?1 ror a, 1 1 2 (cy, a 7 a 0 , a m ?1 a m ) 1 time rol a, 1 1 2 (cy, a 0 a 7 , a m + 1 a m ) 1 time rorc a, 1 1 2 (cy a 0 , a 7 cy, a m ?1 a m ) 1 time rolc a, 1 1 2 (cy a 7 , a 0 cy, a m + 1 a m ) 1 time ror4 [hl] 2 10 12 + n + m a 3 ?0 (hl) 3 ?0 , (hl) 7 ?4 a 3 ?0 , (hl) 3 ?0 (hl) 7 ?4 rol4 [hl] 2 10 12 + n + m a 3 ?0 (hl) 7 ?4 , (hl) 3 ?0 a 3 ?0 , (hl) 7 ?4 (hl) 3 ?0 adjba 2 4 decimal adjust accumulator after addition adjbs 2 4 decimal adjust accumulator after subtract mov1 cy, saddr.bit 3 6 7 cy (saddr.bit) cy, sfr.bit 3 7 cy sfr.bit cy, a.bit 2 4 cy a.bit cy, psw.bit 3 7 cy psw.bit cy, [hl].bit 2 6 7 + n cy (hl).bit saddr.bit, cy 3 6 8 (saddr.bit) cy sfr.bit, cy 3 8 sfr.bit cy a.bit, cy 2 4 a.bit cy psw.bit, cy 3 8 psw.bit cy [hl].bit, cy 2 6 8 + n + m (hl).bit cy notes 1. when the internal high-speed ram area is accessed or instruction with no data access 2. when an area except the internal high-speed ram area is accessed remarks 1. one instruction clock cycle is one cycle of the cpu clock (f cpu ) selected by the processor clock control register (pcc). 2. this clock cycle applies to internal rom program. 3. n is the number of waits when external memory expansion area is read from. 4. m is the number of waits when external memory expansion area is written to. 16-bit operation increment/ decrement bcd adjust bit manipu- late multiply/ divide rotate
480 chapter 24 instruction set user? manual u14046ej3v0ud instruction mnemonic operands byte clock operation flag group note 1 note 2 zaccy and1 cy, saddr.bit 3 6 7 cy cy (saddr.bit) cy, sfr.bit 3 7 cy cy sfr.bit cy, a.bit 2 4 cy cy a.bit cy, psw.bit 3 7 cy cy psw.bit cy, [hl].bit 2 6 7 + n cy cy (hl).bit or1 cy, saddr.bit 3 6 7 cy cy (saddr.bit) cy, sfr.bit 3 7 cy cy sfr.bit cy, a.bit 2 4 cy cy a.bit cy, psw.bit 3 7 cy cy psw.bit cy, [hl].bit 2 6 7 + n cy cy (hl).bit xor1 cy, saddr.bit 3 6 7 cy cy (saddr.bit) cy, sfr.bit 3 7 cy cy sfr.bit cy, a.bit 2 4 cy cy a.bit cy, psw.bit 3 7 cy cy psw.bit cy, [hl].bit 2 6 7 + n cy cy (hl).bit set1 saddr.bit 2 4 6 (saddr.bit) 1 sfr.bit 3 8 sfr.bit 1 a.bit 2 4 a.bit 1 psw.bit 2 6 psw.bit 1 [hl].bit 2 6 8 + n + m (hl).bit 1 clr1 saddr.bit 2 4 6 (saddr.bit) 0 sfr.bit 3 8 sfr.bit 0 a.bit 2 4 a.bit 0 psw.bit 2 6 psw.bit 0 [hl].bit 2 6 8 + n + m (hl).bit 0 set1 cy 1 2 cy 11 clr1 cy 1 2 cy 00 not1 cy 1 2 cy cy notes 1. when the internal high-speed ram area is accessed or instruction with no data access 2. when an area except the internal high-speed ram area is accessed remarks 1. one instruction clock cycle is one cycle of the cpu clock (f cpu ) selected by the processor clock control register (pcc). 2. this clock cycle applies to internal rom program. 3. n is the number of waits when external memory expansion area is read from. 4. m is the number of waits when external memory expansion area is written to. bit manipu- late
481 chapter 24 instruction set user? manual u14046ej3v0ud uncondi- tional branch stack manipu- late conditional branch call/return instruction mnemonic operands byte clock operation flag group note 1 note 2 zaccy call !addr16 3 7 (sp ?1) (pc + 3) h , (sp ?2) (pc + 3) l , pc addr16, sp sp ?2 callf !addr11 2 5 (sp ?1) (pc + 2) h , (sp ?2) (pc + 2) l , pc 15 ?11 00001, pc 10 ?0 addr11, sp sp ?2 callt [addr5] 1 6 (sp ?1) (pc + 1) h , (sp ?2) (pc + 1) l , pc h (00000000, addr5 + 1), pc l (00000000, addr5), sp sp ?2 brk 1 6 (sp ?1) psw, (sp ?2) (pc + 1) h , (sp ?3) (pc + 1) l , pc h (003fh), pc l (003eh), sp sp ?3, ie 0 ret 16 pc h (sp + 1), pc l (sp), sp sp + 2 reti 16 pc h (sp + 1), pc l (sp), r r r psw (sp + 2), sp sp + 3, nmis 0 retb 16 pc h (sp + 1), pc l (sp), r r r psw (sp + 2), sp sp + 3 push psw 1 2 (sp ?1) psw, sp sp ?1 rp 1 4 (sp ?1) rp h , (sp ?2) rp l , sp sp ?2 pop psw 1 2 psw (sp), sp sp + 1 r r r rp 1 4 rp h (sp + 1), rp l (sp), sp sp + 2 movw sp, #word 4 10 sp word sp, ax 2 8 sp ax ax, sp 2 8 ax sp br !addr16 3 6 pc addr16 $addr16 2 6 pc pc + 2 + jdisp8 ax 2 8 pc h a, pc l x bc $addr16 2 6 pc pc + 2 + jdisp8 if cy = 1 bnc $addr16 2 6 pc pc + 2 + jdisp8 if cy = 0 bz $addr16 2 6 pc pc + 2 + jdisp8 if z = 1 bnz $addr16 2 6 pc pc + 2 + jdisp8 if z = 0 notes 1. when the internal high-speed ram area is accessed or instruction with no data access 2. when an area except the internal high-speed ram area is accessed remarks 1. one instruction clock cycle is one cycle of the cpu clock (f cpu ) selected by the processor clock control register (pcc). 2. this clock cycle applies to internal rom program.
482 chapter 24 instruction set user? manual u14046ej3v0ud instruction mnemonic operands byte clock operation flag group note 1 note 2 zaccy bt saddr.bit, $addr16 3 8 9 pc pc + 3 + jdisp8 if (saddr.bit) = 1 sfr.bit, $addr16 4 11 pc pc + 4 + jdisp8 if sfr.bit = 1 a.bit, $addr16 3 8 pc pc + 3 + jdisp8 if a.bit = 1 psw.bit, $addr16 3 9 pc pc + 3 + jdisp8 if psw.bit = 1 [hl].bit, $addr16 3 10 11 + n pc pc + 3 + jdisp8 if (hl).bit = 1 bf saddr.bit, $addr16 4 10 11 pc pc + 4 + jdisp8 if (saddr.bit) = 0 sfr.bit, $addr16 4 11 pc pc + 4 + jdisp8 if sfr.bit = 0 a.bit, $addr16 3 8 pc pc + 3 + jdisp8 if a.bit = 0 psw.bit, $addr16 4 11 pc pc + 4 + jdisp8 if psw.bit = 0 [hl].bit, $addr16 3 10 11 + n pc pc + 3 + jdisp8 if (hl).bit = 0 btclr saddr.bit, $addr16 4 10 12 pc pc + 4 + jdisp8 if (saddr.bit) = 1 then reset (saddr.bit) sfr.bit, $addr16 4 12 pc pc + 4 + jdisp8 if sfr.bit = 1 then reset sfr.bit a.bit, $addr16 3 8 pc pc + 3 + jdisp8 if a.bit = 1 then reset a.bit psw.bit, $addr16 4 12 pc pc + 4 + jdisp8 if psw.bit = 1 then reset psw.bit [hl].bit, $addr16 3 10 12 + n + m pc pc + 3 + jdisp8 if (hl).bit = 1 then reset (hl).bit dbnz b, $addr16 2 6 b b ?1, then pc pc + 2 + jdisp8 if b 0 c, $addr16 2 6 c c ?, then pc pc + 2 + jdisp8 if c 0 saddr, $addr16 3 8 10 (saddr) (saddr) ?1, then pc pc + 3 + jdisp8 if(saddr) 0 sel rbn 2 4 rbs1, 0 n nop 1 2 no operation ei 2 6 ie 1 (enable interrupt) di 2 6 ie 0 (disable interrupt) halt 2 6 set halt mode stop 2 6 set stop mode notes 1. when the internal high-speed ram area is accessed or instruction with no data access 2. when an area except the internal high-speed ram area is accessed remarks 1. one instruction clock cycle is one cycle of the cpu clock (f cpu ) selected by the processor clock control register (pcc). 2. this clock cycle applies to internal rom program. 3. n is the number of waits when external memory expansion area is read from. 4. m is the number of waits when external memory expansion area is written to. cpu control condi- tional branch
483 chapter 24 instruction set user? manual u14046ej3v0ud 24.3 instructions listed by addressing type (1) 8-bit instructions mov, xch, add, addc, sub, subc, and, or, xor, cmp, mulu, divuw, inc, dec, ror, rol, rorc, rolc, ror4, rol4, push, pop, dbnz
484 chapter 24 instruction set user? manual u14046ej3v0ud second operand #byte a r note sfr saddr !addr16 psw [de] [hl] [hl + byte] $addr16 1 none [hl + b] first operand [hl + c] a add mov mov mov mov mov mov mov mov ror addc xch xch xch xch xch xch xch rol sub add add add add add rorc subc addc addc addc addc addc rolc and sub sub sub sub sub or subc subc subc subc subc xor and and and and and cmp or or or or or xor xor xor xor xor cmp cmp cmp cmp cmp r mov mov inc add dec addc sub subc and or xor cmp b, c dbnz sfr mov mov saddr mov mov dbnz inc add dec addc sub subc and or xor cmp !addr16 mov psw mov mov push pop [de] mov [hl] mov ror4 rol4 [hl + byte] mov [hl + b] [hl + c] x mulu c divuw note except r = a
485 chapter 24 instruction set user? manual u14046ej3v0ud (2) 16-bit instructions movw, xchw, addw, subw, cmpw, push, pop, incw, decw second operand #word ax rp note sfrp saddrp !addr16 sp none first operand ax addw movw movw movw movw movw subw xchw cmpw rp movw movw note incw decw push pop sfrp movw movw saddrp movw movw !addr16 movw sp movw movw note only when rp = bc, de, hl (3) bit manipulation instructions mov1, and1, or1, xor1, set1, clr1, not1, bt, bf, btclr second operand a.bit sfr.bit saddr.bit psw.bit [hl].bit cy $addr16 none first operand a.bit mov1 bt set1 bf clr1 btclr sfr.bit mov1 bt set1 bf clr1 btclr saddr.bit mov1 bt set1 bf clr1 btclr psw.bit mov1 bt set1 bf clr1 btclr [hl].bit mov1 bt set1 bf clr1 btclr cy mov1 mov1 mov1 mov1 mov1 set1 and1 and1 and1 and1 and1 clr1 or1 or1 or1 or1 or1 not1 xor1 xor1 xor1 xor1 xor1
486 chapter 24 instruction set user? manual u14046ej3v0ud (4) call instructions/branch instructions call, callf, callt, br, bc, bnc, bz, bnz, bt, bf, btclr, dbnz second operand ax !addr16 !addr11 [addr5] $addr16 first operand basic instruction br call callf callt br br bc bnc bz bnz compound bt instruction bf btclr dbnz (5) other instructions adjba, adjbs, brk, ret, reti, retb, sel, nop, ei, di, halt, stop
487 user? manual u14046ej3v0ud chapter 25 electrical specifications (expanded-specification products: f x = 1.0 to 12 mhz) target products ? pd780021a, 780022a, 780023a, 780024a, 780031a, 780032a, 780033a, 780034a, 780021a(a), 780022a(a), 780023a(a), 780024a(a), 780031a(a), 780032a(a), 780033a(a), 780034a(a) for which orders were received after december 1, 2001 (products with a rank note other than k, e, p, x) ? pd78f0034b, 78f0034b(a) note the rank is indicated by the 5th digit from the left in the lot number marked on the package. lot number year code rank week code
488 chapter 25 electrical specifications (expanded-specification products: f x = 1.0 to 12 mhz) user s manual u14046ej3v0ud absolute maximum ratings (t a = 25 c) parameter symbol conditions ratings unit supply voltage v dd ? 0.3 to +6.5 v v pp flash memory version only, note 2 ? 0.3 to +10.5 v av dd ? 0.3 to v dd + 0.3 note 1 v av ref ? 0.3 to v dd + 0.3 note 1 v av ss ? 0.3 to +0.3 v input voltage v i1 p00 to p03, p10 to p17, p20 to p25, p34 to p36, ? 0.3 to v dd + 0.3 note 1 v p40 to p47, p50 to p57, p64 to p67, p70 to p75, x1, x2, xt1, xt2, reset v i2 p30 to p33 n-ch open drain ? 0.3 to +6.5 v on-chip pull-up resistor ? 0.3 to v dd + 0.3 note 1 v output voltage v o ? 0.3 to v dd + 0.3 note 1 v analog input voltage v an p10 to p17 analog input pin av ss ? 0.3 to av ref + 0.3 note 1 v and ? 0.3 to v dd + 0.3 note 1 output current, high i oh per pin ? 10 ma total for p00 to p03, p40 to p47, p50 to p57, ? 15 ma p64 to p67, p70 to p75 total for p20 to p25, p30 to p36 ? 15 ma output current, low i ol per pin for p00 to p03, p20 to p25, p34 to p36, 20 ma p40 to p47, p64 to p67, p70 to p75 per pin for p30 to p33, p50 to p57 30 ma total for p00 to p03, p40 to p47, p64 to p67, 50 ma p70 to p75 total for p20 to p25 20 ma total for p30 to p36 100 ma total for p50 to p57 100 ma operating ambient t a during normal operation ? 40 to +85 c temperature during flash memory programming +10 to +80 c storage t stg mask rom version ? 65 to +150 c temperature flash memory version ? 40 to +125 c notes 1. 6.5 v or below ( note 2 is explained on the following page.) caution product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. that is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. remark unless otherwise specified, the characteristics of alternate-function pins are the same as those of port pins.
489 chapter 25 electrical specifications (expanded-specification products: f x = 1.0 to 12 mhz) user s manual u14046ej3v0ud notes 2. make sure that the following conditions of the v pp voltage application timing are satisfied when the flash memory is written. ? when supply voltage rises v pp must exceed v dd 10 s or more after v dd has reached the lower-limit value (1.8 v) of the operating voltage range (see a in the figure below). ? when supply voltage drops v dd must be lowered 10 s or more after v pp falls below the lower-limit value (1.8 v) of the operating voltage range of v dd (see b in the figure below). capacitance (t a = 25 c, v dd = v ss = 0 v) parameter symbol conditions min. typ. max. unit input c in f = 1 mhz 15 pf capacitance unmeasured pins returned to 0 v. i/o c io f = 1 mhz p00 to p03, p20 to p25, 15 pf capacitance unmeasured pins p34 to p36, p40 to p47, returned to 0 v. p50 to p57, p64 to p67, p70 to p75 p30 to p33 20 pf remark unless otherwise specified, the characteristics of alternate-function pins are the same as those of port pins. 1.8 v v dd 0 v 0 v v pp 1.8 v a b
490 chapter 25 electrical specifications (expanded-specification products: f x = 1.0 to 12 mhz) user s manual u14046ej3v0ud main system clock oscillator characteristics (t a = ? 40 to +85 c, v dd = 1.8 to 5.5 v) resonator recommended parameter conditions min. typ. max. unit circuit ceramic oscillation 4.5 v v dd 5.5 v 1.0 12.0 mhz resonator frequency (f x ) note 1 3.0 v v dd < 4.5 v 1.0 8.38 1.8 v v dd < 3.0 v 1.0 5.0 oscillation after v dd reaches 4 ms stabilization time note 2 oscillation voltage range min. crystal oscillation 4.5 v v dd 5.5 v 1.0 12.0 mhz resonator frequency (f x ) note 1 3.0 v v dd < 4.5 v 1.0 8.38 1.8 v v dd < 3.0 v 1.0 5.0 oscillation 4.0 v v dd 5.5 v 10 ms stabilization time note 2 1.8 v v dd < 4.0 v 30 external x1 input 4.5 v v dd 5.5 v 1.0 12.0 mhz clock frequency (f x ) note 1 3.0 v v dd < 4.5 v 1.0 8.38 1.8 v v dd < 3.0 v 1.0 5.0 x1 input 4.5 v v dd 5.5 v 38 500 ns high-/low-level width 3.0 v v dd < 4.5 v 50 500 (t xh , t xl ) 1.8 v v dd < 3.0 v 85 500 notes 1. indicates only oscillator characteristics. refer to ac characteristics for instruction execution time. 2. time required to stabilize oscillation after reset or stop mode release. cautions 1. when using the main system clock oscillator, wire as follows in the area enclosed by the broken lines in the above figures to avoid an adverse effect from wiring capacitance. keep the wiring length as short as possible. do not cross the wiring with the other signal lines. do not route the wiring near a signal line through which a high fluctuating current flows. always make the ground point of the oscillator capacitor the same potential as v ss1 . do not ground the capacitor to a ground pattern through which a high current flows. do not fetch signals from the oscillator. 2. when the main system clock is stopped and the system is operating on the subsystem clock, wait until the oscillation stabilization time has been secured by the program before switching back to the main system clock. c2 r1 c1 x1 v ss1 x2 c2 r1 c1 x1 v ss1 x2 x2 x1
491 chapter 25 electrical specifications (expanded-specification products: f x = 1.0 to 12 mhz) user? manual u14046ej3v0ud subsystem clock oscillator characteristics (t a = ? 40 to +85 c, v dd = 1.8 to 5.5 v) notes 1. indicates only oscillator characteristics. refer to ac characteristics for instruction execution time. 2. time required to stabilize oscillation after v dd reaches oscillation voltage range min. cautions 1. when using the subsystem clock oscillator, wire as follows in the area enclosed by the broken lines in the above figure to avoid an adverse effect from wiring capacitance. keep the wiring length as short as possible. do not cross the wiring with the other signal lines. do not route the wiring near a signal line through which a high fluctuating current flows. always make the ground point of the oscillator capacitor the same potential as v ss1 . do not ground the capacitor to a ground pattern through which a high current flows. do not fetch signals from the oscillator. 2. the subsystem clock oscillator is designed as a low-amplitude circuit for reducing power consumption, and is more prone to malfunction due to noise than the main system clock oscillator. particular care is therefore required with the wiring method when the subsystem clock is used. remark for the resonator selection and oscillator constant of the subsystem clock, customers are required to either evaluate the oscillation themselves or apply to the resonator manufacturer for evaluation. min. 32 32 resonator crystal resonator external clock parameter oscillation frequency (f xt ) note 1 oscillation stabilization time note 2 xt1 input frequency (f xt ) note 1 xt1 input high-/low-level width (t xth , t xtl ) conditions 4.0 v v dd 5.5 v 1.8 v v dd < 4.0 v typ. 32.768 1.2 max. 35 2 10 38.5 unit khz s khz recommended circuit 12 15 s xt1 xt2 c3 xt2 xt1 v ss1 r c4
492 chapter 25 electrical specifications (expanded-specification products: f x = 1.0 to 12 mhz) user s manual u14046ej3v0ud recommended oscillator constant to use the pd78f0034b or 78f0034b(a), for the resonator selection and oscillator constant, customers are required to either evaluate the oscillation themselves or apply to the resonator manufacturer for evaluation. ? mask rom versions of pd780024a, 780034a subseries (expanded-specification product) main system clock: ceramic resonator (t a = ? 40 to +85 c) manufacturer part number frequency recommended circuit constant oscillation voltage range (mhz) c1 (pf) c2 (pf) r1 (k ? ) min. (v) max. (v) murata mfg. csbfb1m00j58 1.00 100 100 2.2 1.8 5.5 co., ltd. csbla1m00j58 1.00 100 100 2.2 1.8 5.5 cstcc2m00g56 2.00 on-chip on-chip 0 1.8 5.5 cstls2m00g56 2.00 on-chip on-chip 0 1.8 5.5 cstcc3m58g53 3.58 on-chip on-chip 0 1.8 5.5 cstls3m58g53 3.58 on-chip on-chip 0 1.8 5.5 cstcr4m00g53 4.00 on-chip on-chip 0 1.8 5.5 cstls4m00g53 4.00 on-chip on-chip 0 1.8 5.5 cstcr4m19g53 4.19 on-chip on-chip 0 1.8 5.5 cstls4m19g53 4.19 on-chip on-chip 0 1.8 5.5 cstcr4m91g53 4.91 on-chip on-chip 0 1.8 5.5 cstls4m91g53 4.91 on-chip on-chip 0 1.8 5.5 cstcr5m00g53 5.00 on-chip on-chip 0 1.8 5.5 cstls5m00g53 5.00 on-chip on-chip 0 1.8 5.5 cstce8m00g52 8.00 on-chip on-chip 0 2.7 5.5 cstls8m00g53 8.00 on-chip on-chip 0 2.7 5.5 cstce8m38g52 8.38 on-chip on-chip 0 3.0 5.5 cstls8m38g53 8.38 on-chip on-chip 0 3.0 5.5 cstce10m0g52 10.00 on-chip on-chip 0 3.0 5.5 cstls10m0g53 10.00 on-chip on-chip 0 3.0 5.5 cstce12m0g52 12.00 on-chip on-chip 0 4.5 5.5 cstla12m0t55 12.00 on-chip on-chip 0 4.5 5.5 tdk ccr3.58mc3 3.58 on-chip on-chip 0 1.8 5.5 ccr4.19mc3 4.19 on-chip on-chip 0 1.8 5.5 ccr5.0mc3 5.00 on-chip on-chip 0 1.8 5.5 ccr8.0mc5 8.00 on-chip on-chip 0 2.7 5.5 ccr8.38mc5 8.38 on-chip on-chip 0 3.0 5.5 caution the oscillator constant is a reference value based on evaluation in specific environments by the resonator manufacturer. if the oscillator characteristics need to be optimized in the actual application, request the resonator manufacturer for evaluation on the implementation circuit. note that the oscillation voltage and oscillation frequency merely indicate the characteristics of the oscillator. use the internal operation conditions of the pd780024a, 780034a subseries within the specifications of the dc and ac characteristics.
493 chapter 25 electrical specifications (expanded-specification products: f x = 1.0 to 12 mhz) user s manual u14046ej3v0ud dc characteristics (t a = ? 40 to +85 c, v dd = 1.8 to 5.5 v) (1/4) parameter symbol conditions min. typ. max. unit output current, i oh per pin 1ma high all pins 15 ma output current, i ol per pin for p00 to p03, p20 to p25, p34 to p36, 10 ma low p40 to p47, p64 to p67, p70 to p75 per pin for p30 to p33, p50 to p57 15 ma total for p00 to p03, p40 to p47, p64 to p67, p70 to p75 20 ma total for p20 to p25 10 ma total for p30 to p36 70 ma total for p50 to p57 70 ma input voltage, v ih1 p10 to p17, p21, p24, p35, 2.7 v v dd 5.5 v 0.7v dd v dd v high p40 to p47, p50 to p57, 1.8 v v dd < 2.7 v 0.8v dd v dd v p64 to p67, p74, p75 v ih2 p00 to p03, p20, p22, p23, p25, 2.7 v v dd 5.5 v 0.8v dd v dd v p34, p36, p70 to p73, reset 1.8 v v dd < 2.7 v 0.85v dd v dd v v ih3 p30 to p33 2.7 v v dd 5.5 v 0.7v dd 5.5 v (n-ch open-drain) 1.8 v v dd < 2.7 v 0.8v dd 5.5 v v ih4 x1, x2 2.7 v v dd 5.5 v v dd 0.5 v dd v 1.8 v v dd < 2.7 v v dd 0.2 v dd v v ih5 xt1, xt2 4.0 v v dd 5.5 v 0.8v dd v dd v 1.8 v v dd < 4.0 v 0.9v dd v dd v input voltage, v il1 p10 to p17, p21, p24, p35, 2.7 v v dd 5.5 v 0 0.3v dd v low p40 to p47, p50 to p57, 1.8 v v dd < 2.7 v 0 0.2v dd v p64 to p67, p74, p75 v il2 p00 to p03, p20, p22, p23, p25, 2.7 v v dd 5.5 v 0 0.2v dd v p34, p36, p70 to p73, reset 1.8 v v dd < 2.7 v 0 0.15v dd v v il3 p30 to p33 4.0 v v dd 5.5 v 0 0.3v dd v 2.7 v v dd < 4.0 v 0 0.2v dd v 1.8 v v dd < 2.7 v 0 0.1v dd v v il4 x1, x2 2.7 v v dd 5.5 v 0 0.4 v 1.8 v v dd < 2.7 v 0 0.2 v v il5 xt1, xt2 4.0 v v dd 5.5 v 0 0.2v dd v 1.8 v v dd < 4.0 v 0 0.1v dd v output voltage, v oh1 4.0 v v dd 5.5 v, i oh = 1 ma v dd 1.0 v dd v high 1.8 v v dd < 4.0 v, i oh = 100 a v dd 0.5 v dd v output voltage, v ol1 p30 to p33 4.0 v v dd 5.5 v, 2.0 v low v ol2 p50 to p57 i ol = 15 ma 0.4 2.0 v v ol3 p00 to p03, p20 to p25, p34 to p36, 4.0 v v dd 5.5 v, 0.4 v p40 to p47, p64 to p67, p70 to p75 i ol = 1.6 ma v ol4 i ol = 400 a 0.5 v remark unless otherwise specified, the characteristics of alternate-function pins are the same as those of port pins.
494 chapter 25 electrical specifications (expanded-specification products: f x = 1.0 to 12 mhz) user s manual u14046ej3v0ud dc characteristics (t a = ? 40 to +85 c, v dd = 1.8 to 5.5 v) (2/4) parameter symbol conditions min. typ. max. unit input leakage i lih1 v in = v dd p00 to p03, p10 to p17, p20 to p25, 3 a current, high p34 to p36, p40 to p47, p50 to p57, p64 to p67, p70 to p75, reset i lih2 x1, x2, xt1, xt2 20 a i lih3 v in = 5.5 v p30 to p33 3 a input leakage i lil1 v in = 0 v p00 to p03, p10 to p17, p20 to p25, 3 a current, low p34 to p36, p40 to p47, p50 to p57, p64 to p67, p70 to p75, reset i lil2 x1, x2, xt1, xt2 20 a i lil3 p30 to p33 3 a output leakage i loh v out = v dd 3 a current, high output leakage i lol v out = 0 v 3 a current, low mask option pull- r 1 v in = 0 v, 15 30 90 k ? up resistance p30, p31, p32, p33 (mask rom version only) software pull- r 2 v in = 0 v, 15 30 90 k ? up resistance p00 to p03, p20 to p25, p34 to p36, p40 to p47, p50 to p57, p64 to p67, p70 to p75 remark unless otherwise specified, the characteristics of alternate-function pins are the same as those of port pins.
495 chapter 25 electrical specifications (expanded-specification products: f x = 1.0 to 12 mhz) user s manual u14046ej3v0ud dc characteristics (t a = ? 40 to +85 c, v dd = 1.8 to 5.5 v) (3/4) (1) mask rom versions of pd780024a, 780034a subseries (expanded-specification product) parameter symbol conditions min. typ. max. unit power supply i dd1 note 2 12.0 mhz v dd = 5.0 v 10% note 3 when a/d converter is 8.5 17 ma current note 1 crystal oscillation stopped operating mode when a/d converter is 9.5 19 ma operating note 7 8.38 mhz v dd = 5.0 v 10% note 3 when a/d converter is 5.5 11 ma crystal oscillation stopped operating mode when a/d converter is 6.5 13 ma operating note 7 v dd = 3.0 v + 10% notes 3, 6 when a/d converter is 3 6 ma stopped when a/d converter is 4 8 ma operating note 7 5.00 mhz v dd = 3.0 v 10% note 3 when a/d converter is 2 4 ma crystal oscillation stopped operating mode when a/d converter is 3 6 ma operating note 7 v dd = 2.0 v 10% note 4 when a/d converter is 0.4 1.5 ma stopped when a/d converter is 1.4 4.2 ma operating note 7 i dd2 12.0 mhz v dd = 5.0 v 10% note 3 when peripheral functions 24ma crystal oscillation are stopped halt mode when peripheral functions 10 ma are operating 8.38 mhz v dd = 5.0 v 10% note 3 when peripheral functions 1.1 2.2 ma crystal oscillation are stopped halt mode when peripheral functions 4.7 ma are operating v dd = 3.0 v + 10% notes 3, 6 when peripheral functions 0.5 1 ma are stopped when peripheral functions 4ma are operating 5.00 mhz v dd = 3.0 v 10% note 3 when peripheral functions 0.35 0.7 ma crystal oscillation are stopped halt mode when peripheral functions 1.7 ma are operating v dd = 2.0 v 10% note 4 when peripheral functions 0.15 0.4 ma are stopped when peripheral functions 1.1 ma are operating i dd3 32.768 khz crystal oscillation v dd = 5.0 v 10% 40 80 a operating mode note 5 v dd = 3.0 v 10% 20 40 a v dd = 2.0 v 10% 10 20 a i dd4 32.768 khz crystal oscillation v dd = 5.0 v 10% 30 60 a halt mode note 5 v dd = 3.0 v 10% 6 18 a v dd = 2.0 v 10% 2 10 a i dd5 xt1 = v dd , stop mode v dd = 5.0 v 10% 0.1 30 a when feedback resistor is not used v dd = 3.0 v 10% 0.05 10 a v dd = 2.0 v 10% 0.05 10 a
496 chapter 25 electrical specifications (expanded-specification products: f x = 1.0 to 12 mhz) user s manual u14046ej3v0ud notes 1. total current through the internal power supply (v dd0 , v dd1 ) (except the current through pull-up resistors of ports). 2. i dd1 includes the peripheral operation current. 3. when the processor clock control register (pcc) is cleared to 00h. 4. when pcc is set to 02h. 5. when main system clock operation is stopped. 6. the values show the specifications when v dd = 3.0 to 3.3 v. the value in the typ. column show the specifications when v dd = 3.0 v. 7. includes the current through the av dd pin.
497 chapter 25 electrical specifications (expanded-specification products: f x = 1.0 to 12 mhz) user s manual u14046ej3v0ud dc characteristics (t a = ? 40 to +85 c, v dd = 1.8 to 5.5 v) (4/4) (2) pd78f0034b, 78f0034b(a) parameter symbol conditions min. typ. max. unit power supply i dd1 note 2 12.0 mhz v dd = 5.0 v 10% note 3 when a/d converter is 16 32 ma current note 1 crystal oscillation stopped operating mode when a/d converter is 17 34 ma operating note 7 8.38 mhz v dd = 5.0 v 10% note 3 when a/d converter is 10.5 21 ma crystal oscillation stopped operating mode when a/d converter is 11.5 23 ma operating note 7 v dd = 3.0 v + 10% notes 3, 6 when a/d converter is 7 14 ma stopped when a/d converter is 8 16 ma operating note 7 5.00 mhz v dd = 3.0 v 10% note 3 when a/d converter is 4.5 9 ma crystal oscillation stopped operating mode when a/d converter is 5.5 11 ma operating note 7 v dd = 2.0 v 10% note 4 when a/d converter is 1 2 ma stopped when a/d converter is 2 6 ma operating note 7 i dd2 12.0 mhz v dd = 5.0 v 10% note 3 when peripheral functions 24ma crystal oscillation are stopped halt mode when peripheral functions 8ma are operating 8.38 mhz v dd = 5.0 v 10% note 3 when peripheral functions 1.2 2.4 ma crystal oscillation are stopped halt mode when peripheral functions 5ma are operating v dd = 3.0 v + 10% notes 3, 6 when peripheral functions 0.6 1.2 ma are stopped when peripheral functions 2.4 ma are operating 5.00 mhz v dd = 3.0 v 10% note 3 when peripheral functions 0.4 0.8 ma crystal oscillation are stopped halt mode when peripheral functions 1.7 ma are operating v dd = 2.0 v 10% note 4 when peripheral functions 0.2 0.4 ma are stopped when peripheral functions 1.1 ma are operating i dd3 32.768 khz crystal oscillation v dd = 5.0 v 10% 115 230 a operating mode note 5 v dd = 3.0 v 10% 95 190 a v dd = 2.0 v 10% 75 150 a i dd4 32.768 khz crystal oscillation v dd = 5.0 v 10% 30 60 a halt mode note 5 v dd = 3.0 v 10% 6 18 a v dd = 2.0 v 10% 2 10 a i dd5 xt1 = v dd , stop mode v dd = 5.0 v 10% 0.1 30 a when feedback resistor is not used v dd = 3.0 v 10% 0.05 10 a v dd = 2.0 v 10% 0.05 10 a
498 chapter 25 electrical specifications (expanded-specification products: f x = 1.0 to 12 mhz) user s manual u14046ej3v0ud notes 1. total current through the internal power supply (v dd0 , v dd1 ) (except the current through pull-up resistors of ports). 2. i dd1 includes the peripheral operation current. 3. when the processor clock control register (pcc) is cleared to 00h. 4. when pcc is set to 02h. 5. when main system clock operation is stopped. 6. the values show the specifications when v dd = 3.0 to 3.3 v. the value in the typ. column show the specifications when v dd = 3.0 v. 7. includes the current through the av dd pin.
499 chapter 25 electrical specifications (expanded-specification products: f x = 1.0 to 12 mhz) user s manual u14046ej3v0ud ac characteristics (1) basic operation (t a = ? 40 to +85 c, v dd = 1.8 to 5.5 v) parameter symbol conditions min. typ. max. unit cycle time t cy operating with 4.5 v v dd 5.5 v 0.166 16 s (min. instruction main system clock 3.0 v v dd < 4.5 v 0.238 16 s execution time) 2.7 v v dd < 3.0 v 0.4 16 s 1.8 v v dd < 2.7 v 1.6 16 s operating with subsystem clock 103.9 note 1 122 125 s ti00, ti01 input t tih0 , t til0 3.0 v v dd 5.5 v 2/f sam + 0.1 note 2 s high-/low-level 2.7 v v dd < 3.0 v 2/f sam + 0.2 note 2 s width 1.8 v v dd < 2.7 v 2/f sam + 0.5 note 2 s ti50, ti51 input f ti5 2.7 v v dd 5.5 v 0 4 mhz frequency 1.8 v v dd < 2.7 v 0 275 khz ti50, ti51 input t tih5 , t til5 2.7 v v dd 5.5 v 100 ns high-/low-level 1.8 v v dd < 2.7 v 1.8 s width interrupt request t inth , t intl intp0 to intp3, 2.7 v v dd 5.5 v 1 s input high-/low- p40 to p47 1.8 v v dd < 2.7 v 2 s level width reset t rsl 2.7 v v dd 5.5 v 10 s low-level width 1.8 v v dd < 2.7 v 20 s notes 1. value when the external clock is used. when a crystal resonator is used, it is 114 s (min.). 2. selection of f sam = f x , f x /4, f x /64 is possible using bits 0 and 1 (prm00, prm01) of prescaler mode register 0 (prm0). however, if the ti00 valid edge is selected as the count clock, the value becomes f sam = f x /8.
500 chapter 25 electrical specifications (expanded-specification products: f x = 1.0 to 12 mhz) user s manual u14046ej3v0ud t cy vs. v dd (main system clock operation) 5.0 1.0 2.0 1.6 0.4 0.238 0.166 0.1 supply voltage v dd [v] cycle time t cy [ s] 0 10.0 1.0 2.0 3.0 4.0 5.0 6.0 1.8 5.5 2.7 4.5 operation guaranteed range 16.0
501 chapter 25 electrical specifications (expanded-specification products: f x = 1.0 to 12 mhz) user s manual u14046ej3v0ud (2) read/write operation (t a = ? 40 to +85 c, v dd = 4.0 to 5.5 v) (1/3) parameter symbol conditions min. max. unit astb high-level width t asth 0.3t cy ns address setup time t ads 20 ns address hold time t adh 6ns data input time from address t add1 (2 + 2n)t cy 54 ns t add2 (3 + 2n)t cy 60 ns address output time from rd t rdad 0 100 ns data input time from rd t rdd1 (2 + 2n)t cy 87 ns t rdd2 (3 + 2n)t cy 93 ns read data hold time t rdh 0ns rd low-level width t rdl1 (1.5 + 2n)t cy 33 ns t rdl2 (2.5 + 2n)t cy 33 ns input time from rd to wait t rdwt1 t cy 43 ns t rdwt2 t cy 43 ns input time from wr to wait t wrwt t cy 25 ns wait low-level width t wtl (0.5 + 2n)t cy + 10 (2 + 2n)t cy ns write data setup time t wds 60 ns write data hold time t wdh 6ns wr low-level width t wrl1 (1.5 + 2n)t cy 15 ns delay time from astb to rd t astrd 6ns delay time from astb to wr t astwr 2t cy 15 ns delay time from t rdast 0.8t cy 15 1.2t cy ns rd to astb at external fetch address hold time from t rdadh 0.8t cy 15 1.2t cy + 30 ns rd at external fetch write data output time from rd t rdwd 40 ns write data output time from wr t wrwd 10 60 ns address hold time from wr t wradh 0.8t cy 15 1.2t cy + 30 ns delay time from wait to rd t wtrd 0.8t cy 2.5t cy + 25 ns delay time from wait to wr t wtwr 0.8t cy 2.5t cy + 25 ns caution t cy can only be used when the min. value is 0.238 s. remarks 1. t cy = t cy /4 2. n indicates the number of waits. 3 .c l = 100 pf (c l indicates the load capacitance of the ad0 to ad7, a8 to a15, rd, wr, wait, and astb pins.)
502 chapter 25 electrical specifications (expanded-specification products: f x = 1.0 to 12 mhz) user s manual u14046ej3v0ud (2) read/write operation (t a = ? 40 to +85 c, v dd = 2.7 to 4.0 v) (2/3) parameter symbol conditions min. max. unit astb high-level width t asth 0.3t cy ns address setup time t ads 30 ns address hold time t adh 10 ns input time from address to data t add1 (2 + 2n)t cy 108 ns t add2 (3 + 2n)t cy 120 ns output time from rd to address t rdad 0 200 ns input time from rd to data t rdd1 (2 + 2n)t cy 148 ns t rdd2 (3 + 2n)t cy 162 ns read data hold time t rdh 0ns rd low-level width t rdl1 (1.5 + 2n)t cy 40 ns t rdl2 (2.5 + 2n)t cy 40 ns input time from rd to wait t rdwt1 t cy 75 ns t rdwt2 t cy 60 ns input time from wr to wait t wrwt t cy 50 ns wait low-level width t wtl (0.5 + 2n)t cy + 10 (2 + 2n)t cy ns write data setup time t wds 60 ns write data hold time t wdh 10 ns wr low-level width t wrl1 (1.5 + 2n)t cy 30 ns delay time from astb to rd t astrd 10 ns delay time from astb to wr t astwr 2t cy 30 ns delay time from t rdast 0.8t cy 30 1.2t cy ns rd to astb at external fetch hold time from t rdadh 0.8t cy 30 1.2t cy + 60 ns rd to address at external fetch write data output time from rd t rdwd 40 ns write data output time from wr t wrwd 20 120 ns hold time from wr to address t wradh 0.8t cy 30 1.2t cy + 60 ns delay time from wait to rd t wtrd 0.5t cy 2.5t cy + 50 ns delay time from wait to wr t wtwr 0.5t cy 2.5t cy + 50 ns caution t cy can only be used when the min. value is 0.4 s. remarks 1. t cy = t cy /4 2. n indicates the number of waits. 3. c l = 100 pf (c l indicates the load capacitance of the ad0 to ad7, a8 to a15, rd, wr, wait, and astb pins.)
503 chapter 25 electrical specifications (expanded-specification products: f x = 1.0 to 12 mhz) user s manual u14046ej3v0ud (2) read/write operation (t a = ? 40 to +85 c, v dd = 1.8 to 2.7 v) (3/3) parameter symbol conditions min. max. unit astb high-level width t asth 0.3t cy ns address setup time t ads 120 ns address hold time t adh 20 ns input time from address to data t add1 (2 + 2n)t cy 233 ns t add2 (3 + 2n)t cy 240 ns output time from rd to address t rdad 0 400 ns input time from rd to data t rdd1 (2 + 2n)t cy 325 ns t rdd2 (3 + 2n)t cy 332 ns read data hold time t rdh 0ns rd low-level width t rdl1 (1.5 + 2n)t cy 92 ns t rdl2 (2.5 + 2n)t cy 92 ns input time from rd to wait t rdwt1 t cy 350 ns t rdwt2 t cy 132 ns input time from wr to wait t wrwt t cy 100 ns wait low-level width t wtl (0.5 + 2n)t cy + 10 (2 + 2n)t cy ns write data setup time t wds 60 ns write data hold time t wdh 20 ns wr low-level width t wrl1 (1.5 + 2n)t cy 60 ns delay time from astb to rd t astrd 20 ns delay time from astb to wr t astwr 2t cy 60 ns delay time from t rdast 0.8t cy 60 1.2t cy ns rd to astb at external fetch hold time from t rdadh 0.8t cy 60 1.2t cy + 120 ns rd to address at external fetch write data output time from rd t rdwd 40 ns write data output time from wr t wrwd 40 240 ns hold time from wr to address t wradh 0.8t cy 60 1.2t cy + 120 ns delay time from wait to rd t wtrd 0.5t cy 2.5t cy + 100 ns delay time from wait to wr t wtwr 0.5t cy 2.5t cy + 100 ns caution t cy can only be used when the min. value is 1.6 s. remarks 1. t cy = t cy /4 2. n indicates the number of waits. 3. c l = 100 pf (c l indicates the load capacitance of the ad0 to ad7, a8 to a15, rd, wr, wait, and astb pins.)
504 chapter 25 electrical specifications (expanded-specification products: f x = 1.0 to 12 mhz) user s manual u14046ej3v0ud (3) serial interface (t a = ? 40 to +85 c, v dd = 1.8 to 5.5 v) (1/2) (a) 3-wire serial i/o mode (sck3n... internal clock output) parameter symbol conditions min. typ. max. unit sck3n t kcy1 4.5 v v dd 5.5 v 666 ns cycle time 3.0 v v dd < 4.5 v 954 ns 2.7 v v dd < 3.0 v 1600 ns 1.8 v v dd < 2.7 v 3200 ns sck3n high-/ t kh1 , t kl1 3.0 v v dd 5.5 v t kcy1 /2 50 ns low-level width 1.8 v v dd < 3.0 v t kcy1 /2 100 ns si3n setup time t sik1 3.0 v v dd 5.5 v 100 ns (to sck3n ) 2.7 v v dd < 3.0 v 150 ns 1.8 v v dd < 2.7 v 300 ns si3n hold time t ksi1 4.5 v v dd 5.5 v 300 ns (from sck3n ) 1.8 v v dd < 4.5 v 400 ns delay time from t kso1 c = 100 pf note 4.5 v v dd 5.5 v 200 ns sck3n to so3n 1.8 v v dd < 4.5 v 300 ns output note c is the load capacitance of the sck3n and so3n output lines. (b) 3-wire serial i/o mode (sck3n... external clock input) parameter symbol conditions min. typ. max. unit sck3n t kcy2 4.5 v v dd 5.5 v 666 ns cycle time 3.0 v v dd < 4.5 v 800 ns 2.7 v v dd < 3.0 v 1600 ns 1.8 v v dd < 2.7 v 3200 ns sck3n high-/ t kh2 , t kl2 4.5 v v dd 5.5 v 333 ns low-level width 3.0 v v dd < 4.5 v 400 ns 2.7 v v dd < 3.0 v 800 ns 1.8 v v dd < 2.7 v 1600 ns si3n setup time t sik2 100 ns (to sck3n ) si3n hold time t ksi2 4.5 v v dd 5.5 v 300 ns (from sck3n ) 1.8 v v dd < 4.5 v 400 ns delay time from t kso2 c = 100 pf note 4.5 v v dd 5.5 v 200 ns sck3n to so3n 1.8 v v dd < 4.5 v 300 ns output note c is the load capacitance of the so3n output line. remark n = 0, 1
505 chapter 25 electrical specifications (expanded-specification products: f x = 1.0 to 12 mhz) user s manual u14046ej3v0ud (3) serial interface (t a = ? 40 to +85 c, v dd = 1.8 to 5.5 v) (2/2) (c) uart mode (dedicated baud-rate generator output) parameter symbol conditions min. typ. max. unit transfer rate 4.5 v v dd 5.5 v 187500 bps 3.0 v v dd < 4.5 v 131031 bps 2.7 v v dd < 3.0 v 78125 bps 1.8 v v dd < 2.7 v 39063 bps (d) uart mode (external clock input) parameter symbol conditions min. typ. max. unit asck0 cycle time t kcy3 4.0 v v dd 5.5 v 800 ns 2.7 v v dd < 4.0 v 1600 ns 1.8 v v dd < 2.7 v 3200 ns asck0 high-/low-level width t kh3 , 4.0 v v dd 5.5 v 400 ns t kl3 2.7 v v dd < 4.0 v 800 ns 1.8 v v dd < 2.7 v 1600 ns transfer rate 4.0 v v dd 5.5 v 39063 bps 2.7 v v dd < 4.0 v 19531 bps 1.8 v v dd < 2.7 v 9766 bps (e) uart mode (infrared data transfer mode) parameter symbol conditions min. max. unit transfer rate 4.0 v v dd 5.5 v 131031 bps allowable bit rate error 4.0 v v dd 5.5 v 0.87 % output pulse width 4.0 v v dd 5.5 v 1.2 0.24/fbr note s input pulse width 4.0 v v dd 5.5 v 4/f x s note fbr: specified baud rate
506 chapter 25 electrical specifications (expanded-specification products: f x = 1.0 to 12 mhz) user s manual u14046ej3v0ud a/d converter characteristics (t a = ? 40 to +85 c, v dd = av dd = 1.8 to 5.5 v, av ss = v ss = 0 v) (1/2) (1) 8-bit a/d converter: pd780024a subseries parameter symbol conditions min. typ. max. unit resolution 888bit overall error note 4.0 v av ref 5.5 v 0.4 %fsr 2.7 v av ref < 4.0 v 0.6 %fsr 1.8 v av ref < 2.7 v 1.2 %fsr conversion time t conv 4.5 v av dd 5.5 v 12 96 s 4.0 v av dd < 4.5 v 14 96 s 2.7 v av dd < 4.0 v 17 96 s 1.8 v av dd < 2.7 v 28 96 s analog input voltage v ain 0av ref v reference voltage av ref 1.8 av dd v resistance between av ref and av ss r ref during a/d converter operation 20 40 k ? note excludes quantization error ( 1/2 lsb). this value is indicated as a ratio (%fsr) to the full-scale value. remark the impedance of the analog input pins is shown below. [equivalent circuit] [parameter value] (typ.) av dd r1 r2 c1 c2 c3 2.7 v 12 k ? 8.0 k ? 3.0 pf 3.0 pf 2.0 pf 4.5 v 4 k ? 2.7 k ? 3.0 pf 1.4 pf 2.0 pf c3 c2 r2 r1 c1 anin (n = 0 to 3)
507 chapter 25 electrical specifications (expanded-specification products: f x = 1.0 to 12 mhz) user s manual u14046ej3v0ud a/d converter characteristics (t a = ? 40 to +85 c, v dd = av dd = 1.8 to 5.5 v, av ss = v ss = 0 v) (2/2) (2) 10-bit a/d converter: pd780034a subseries parameter symbol conditions min. typ. max. unit resolution 10 10 10 bit overall error notes 1, 2 4.0 v av ref 5.5 v 0.2 0.4 %fsr 2.7 v av ref < 4.0 v 0.3 0.6 %fsr 1.8 v av ref < 2.7 v 0.6 1.2 %fsr conversion time t conv 4.5 v av dd 5.5 v 12 96 s 4.0 v av dd < 4.5 v 14 96 s 2.7 v av dd < 4.0 v 17 96 s 1.8 v av dd < 2.7 v 28 96 s zero-scale error notes 1, 2 4.0 v av ref 5.5 v 0.4 %fsr 2.7 v av ref < 4.0 v 0.6 %fsr 1.8 v av ref < 2.7 v 1.2 %fsr full-scale error notes 1, 2 4.0 v av ref 5.5 v 0.4 %fsr 2.7 v av ref < 4.0 v 0.6 %fsr 1.8 v av ref < 2.7 v 1.2 %fsr integral linearity error note 1 4.0 v av ref 5.5 v 2.5 lsb 2.7 v av ref < 4.0 v 4.5 lsb 1.8 v av ref < 2.7 v 8.5 lsb differential linearity error 4.0 v av ref 5.5 v 1.5 lsb 2.7 v av ref < 4.0 v 2.0 lsb 1.8 v av ref < 2.7 v 3.5 lsb analog input voltage v ain 0av ref v reference voltage av ref 1.8 av dd v resistance between av ref and av ss r ref during a/d converter operation 20 40 k ? notes 1. excludes quantization error ( 1/2 lsb). 2. this value is indicated as a ratio to the full-scale value. remark the impedance of the analog input pins is shown below. [equivalent circuit] [parameter value] (typ.) av dd r1 r2 c1 c2 c3 2.7 v 12 k ? 8.0 k ? 3.0 pf 3.0 pf 2.0 pf 4.5 v 4 k ? 2.7 k ? 3.0 pf 1.4 pf 2.0 pf c3 c2 r2 r1 c1 anin (n = 0 to 3)
508 chapter 25 electrical specifications (expanded-specification products: f x = 1.0 to 12 mhz) user s manual u14046ej3v0ud data memory stop mode low supply voltage data retention characteristics (t a = 40 to +85 c) parameter symbol conditions min. typ. max. unit data retention power v dddr 1.6 5.5 v supply voltage data retention power i dddr v dddr = 1.6 v 0.1 30 a supply current (subsystem clock unused (xt1 = v dd ) and feedback resistor disconnected) release signal set time t srel 0 s oscillation stabilization t wait release by reset 2 17 /f x s wait time release by interrupt request note s note selection of 2 12 /f x and 2 14 /f x to 2 17 /f x is possible using bits 0 to 2 (osts0 to osts2) of the oscillation stabilization time select register (osts).
509 chapter 25 electrical specifications (expanded-specification products: f x = 1.0 to 12 mhz) user s manual u14046ej3v0ud flash memory programming characteristics (1/2) (t a = +10 to +40 c, v dd = av dd = 1.8 to 5.5 v, v ss = av ss = 0 v) ? pd78f0034b, 78f0034b(a) (a) write erase characteristics parameter symbol conditions min. typ. max. unit operating frequency f x 4.5 v v dd 5.5 v 1.0 10.0 mhz 3.0 v v dd < 4.5 v 1.0 8.38 mhz 2.7 v v dd < 3.0 v 1.0 5.00 mhz 1.8 v v dd < 2.7 v 1.0 1.25 mhz v pp supply voltage v pp2 during flash memory programming 9.7 10.0 10.3 v v dd supply current note 1 i dd when 10 mhz crystal v dd = 5.0 v 10% 30 ma v pp = v pp2 oscillation operating mode 8.38 mhz crystal v dd = 5.0 v 10% 24 ma oscillation v dd = 3.0 v 10% 17 ma operating mode v pp supply current i pp when v pp = v pp2 100 ma step erase time note 2 t er 0.199 0.2 0.201 s overall erase time note 3 t era when step erase time = 0.2 s 20 s/chip writeback time note 4 t wb 49.4 50 50.6 ms number of writebacks per c wb when writeback time = 50 ms 60 times writeback command note 5 number of erases/writebacks c erwb 16 times step write time note 6 t wr 48 50 52 s overall write time per word note 7 t wrw when step write time = 50 s (1 word = 1 byte) 48 520 s number of rewrites per chip note 8 c erwr 1 erase + 1 write after erase = 1 rewrite 20 times/area notes 1. av dd current and port current (current that flows through the internal pull-up resistor) are not included. 2. the recommended setting value of the step erase time is 0.2 s. 3. the prewrite time before erasure and the erase verify time (writeback time) are not included. 4. the recommended setting value of the writeback time is 50 ms. 5. writeback is executed once by the issuance of the writeback command. therefore, the number of retries must be the maximum value minus the number of commands issued. 6. the recommended setting value of the step write time is 50 s. 7. the actual write time per word is 100 s longer. the internal verify time during or after a write is not included. 8. when a product is first written after shipment, erase write and write only are both taken as one rewrite. example: p: write, e: erase shipped product p e p e p: 3 rewrites shipped product e p e p e p: 3 rewrites
510 chapter 25 electrical specifications (expanded-specification products: f x = 1.0 to 12 mhz) user s manual u14046ej3v0ud flash memory programming characteristics (2/2) (t a = +10 to +40 c, v dd = av dd = 1.8 to 5.5 v, v ss = av ss = 0 v) ? pd78f0034b, 78f0034b(a) (b) serial write operation characteristics parameter symbol conditions min. typ. max. unit set time from v dd to v pp t dp 10 s release time from v pp to reset t pr 1.0 s v pp pulse input start time from t rp 1.0 s reset v pp pulse high-/low-level width t pw 8.0 s v pp pulse input end time from t rpe 20 ms reset v pp pulse low-level input voltage v ppl 0.8v dd 1.2v dd v v pp pulse high-level input voltage v pph 9.7 10.0 10.3 v
511 chapter 25 electrical specifications (expanded-specification products: f x = 1.0 to 12 mhz) user s manual u14046ej3v0ud timing charts ac timing test points (excluding x1, xt1 input) clock timing ti timing 0.8v dd 0.2v dd test points 0.8v dd 0.2v dd t xl t xh 1/f x v ih4 (min.) v il4 (max.) t xtl t xth 1/f xt v ih5 (min.) v il5 (max.) x1 input xt1 input t til0 t tih0 ti00, ti01 1/f ti5 t tih5 t til5 ti50, ti51
512 chapter 25 electrical specifications (expanded-specification products: f x = 1.0 to 12 mhz) user s manual u14046ej3v0ud interrupt request input timing reset input timing intp0 to intp3 t intl t inth t rsl reset
513 chapter 25 electrical specifications (expanded-specification products: f x = 1.0 to 12 mhz) user s manual u14046ej3v0ud read/write operation external fetch (no wait): external fetch (wait insertion): a8 to a15 ad0 to ad7 astb rd higher 8-bit address lower 8-bit address t add1 hi-z t ads t asth t adh t rdd1 t rdad instruction code t rdadh t rdast t astrd t rdl1 t rdh a8 to a15 ad0 to ad7 astb rd higher 8-bit address lower 8-bit address t add1 hi-z t ads t asth t adh t rdad t rdd1 instruction code t rdadh t rdast t astrd t rdl1 t rdh wait t rdwt1 t wtl t wtrd
514 chapter 25 electrical specifications (expanded-specification products: f x = 1.0 to 12 mhz) user s manual u14046ej3v0ud external data access (no wait): external data access (wait insertion): a8 to a15 ad0 to ad7 astb rd higher 8-bit address lower 8-bit address t add2 hi-z t ads t asth t adh t rdd2 t rdad read data t astrd t rdwd wr t astwr write data hi-z t wdh t wradh t wds t wrwd t wrl1 t rdh t rdl2 a8 to a15 ad0 to ad7 astb rd higher 8-bit address lower 8-bit address t add2 t ads t asth t adh t rdad t rdd2 read data t astrd wr t astwr write data hi-z t wdh t wradh t wds t wrwd t wrl1 t rdh t rdl2 t rdwt2 t wtl t wrwt t wtl t wtwr t wtrd wait t rdwd hi-z
515 chapter 25 electrical specifications (expanded-specification products: f x = 1.0 to 12 mhz) user s manual u14046ej3v0ud serial transfer timing 3-wire serial i/o mode: remarks 1. m = 1, 2 2. n = 0, 1 uart mode (external clock input): t kcym t klm t khm sck3n si3n so3n t sikm t ksim t ksom input data output data t kcy3 t kh3 t kl3 asck0
516 chapter 25 electrical specifications (expanded-specification products: f x = 1.0 to 12 mhz) user s manual u14046ej3v0ud data retention timing (stop mode release by reset) data retention timing (standby release signal: stop mode release by interrupt request signal) t srel t wait v dd reset stop instruction execution stop mode data retention mode internal reset operation halt mode operating mode v dddr t srel t wait v dd stop instruction execution stop mode data retention mode halt mode operating mode standby release signal (interrupt request) v dddr
517 chapter 25 electrical specifications (expanded-specification products: f x = 1.0 to 12 mhz) user s manual u14046ej3v0ud flash memory write mode set timing v dd v dd 0 v 0 v v dd reset (input) 0 v v pph v pp v ppl t rp t pr t dp t pw t pw t rpe
518 user? manual u14046ej3v0ud chapter 26 electrical specifications (conventional products: f x = 1.0 to 8.38 mhz) target products ? pd780021a, 780022a, 780023a, 780024a, 780031a, 780032a, 780033a, 780034a, 780021a(a), 780022a(a), 780023a(a), 780024a(a), 780031a(a), 780032a(a), 780033a(a), 780034a(a) for which orders were received before november 30, 2001 (products with rank note k, e, p, x) ? pd780021ay, 780022ay, 780023ay, 780024ay, 780031ay, 780032ay, 780033ay, 780034ay, 780021ay(a), 780022ay(a), 780023ay(a), 780024ay(a), 780031ay(a), 780032ay(a), 780033ay(a), 780034ay(a) ? pd78f0034a, 78f0034ay, 78f0034by, 78f0034by(a) note the rank is indicated by the 5th digit from the left in the lot number marked on the package. caution the pd780021ay(a), 780023ay(a), 780024ay(a), 780031ay(a), 780032ay(a), 780033ay(a), and 780034ay(a) are under development. the electrical specifications of the above products are target values (reference values only); mass-produced products do not necessarily satisfy these ratings. lot number year code rank week code
519 chapter 26 electrical specifications (conventional products: f x = 1.0 to 8.38 mhz) user s manual u14046ej3v0ud absolute maximum ratings (t a = 25 c) (1/2) parameter symbol conditions ratings unit supply voltage v dd ? 0.3 to +6.5 v v pp flash memory version only, note 2 ? 0.3 to +10.5 v av dd ? 0.3 to v dd + 0.3 note 1 v av ref ? 0.3 to v dd + 0.3 note 1 v av ss ? 0.3 to +0.3 v input voltage v i1 p00 to p03, p10 to p17, p20 to p25, p34 to p36, ? 0.3 to v dd + 0.3 note 1 v p40 to p47, p50 to p57, p64 to p67, p70 to p75, x1, x2, xt1, xt2, reset v i2 p30 to p33 n-ch open drain ? 0.3 to +6.5 v on-chip pull-up resistor ? 0.3 to v dd + 0.3 note 1 v output voltage v o ? 0.3 to v dd + 0.3 note 1 v analog input voltage v an p10 to p17 analog input pin av ss ? 0.3 to av ref + 0.3 note 1 v and ? 0.3 to v dd + 0.3 note 1 notes 1. 6.5 v or below 2. make sure that the following conditions of the v pp voltage application timing are satisfied when the flash memory is written. ? when supply voltage rises v pp must exceed v dd 10 s or more after v dd has reached the lower-limit value (1.8 v) of the operating voltage range (see a in the figure below). ? when supply voltage drops v dd must be lowered 10 s or more after v pp falls below the lower-limit value (1.8 v) of the operating voltage range of v dd (see b in the figure below). 1.8 v v dd 0 v 0 v v pp 1.8 v a b caution product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. that is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. remark unless otherwise specified, the characteristics of alternate-function pins are the same as those of port pins.
520 chapter 26 electrical specifications (conventional products: f x = 1.0 to 8.38 mhz) user s manual u14046ej3v0ud absolute maximum ratings (t a = 25 c) (2/2) parameter symbol conditions ratings unit output current, high i oh per pin ? 10 ma total for p00 to p03, p40 to p47, p50 to p57, ? 15 ma p64 to p67, p70 to p75 total for p20 to p25, p30 to p36 ? 15 ma output current, low i ol per pin for p00 to p03, p20 to p25, p34 to p36, 20 ma p40 to p47, p64 to p67, p70 to p75 per pin for p30 to p33, p50 to p57 30 ma total for p00 to p03, p40 to p47, p64 to p67, 50 ma p70 to p75 total for p20 to p25 20 ma total for p30 to p36 100 ma total for p50 to p57 100 ma operating ambient t a during normal operation ? 40 to +85 c temperature during flash memory programming ? 10 to +80 c storage t stg mask rom version ? 65 to +150 c temperature flash memory version ? 40 to +125 c caution product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. that is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. remark unless otherwise specified, the characteristics of alternate-function pins are the same as those of port pins.
521 chapter 26 electrical specifications (conventional products: f x = 1.0 to 8.38 mhz) user s manual u14046ej3v0ud capacitance (t a = 25 c, v dd = v ss = 0 v) parameter symbol conditions min. typ. max. unit input c in f = 1 mhz 15 pf capacitance unmeasured pins returned to 0 v. i/o c io f = 1 mhz p00 to p03, p20 to p25, 15 pf capacitance unmeasured pins p34 to p36, p40 to p47, returned to 0 v. p50 to p57, p64 to p67, p70 to p75 p30 to p33 20 pf remark unless otherwise specified, the characteristics of alternate-function pins are the same as those of port pins. main system clock oscillator characteristics (t a = ? 40 to +85 c, v dd = 1.8 to 5.5 v) resonator recommended parameter conditions min. typ. max. unit circuit ceramic oscillation 4.0 v v dd 5.5 v 1.0 8.38 mhz resonator frequency (f x ) note 1 1.8 v v dd < 4.0 v 1.0 5.0 oscillation after v dd reaches 4 ms stabilization time note 2 oscillation voltage range min. crystal oscillation 4.0 v v dd 5.5 v 1.0 8.38 mhz resonator frequency (f x ) note 1 1.8 v v dd < 4.0 v 1.0 5.0 oscillation 4.0 v v dd 5.5 v 10 ms stabilization time note 2 1.8 v v dd < 4.0 v 30 external x1 input 4.0 v v dd 5.5 v 1.0 8.38 mhz clock frequency (f x ) note 1 1.8 v v dd < 4.0 v 1.0 5.0 x1 input 4.0 v v dd 5.5 v 50 500 ns high-/low-level width 1.8 v v dd < 4.0 v 85 500 (t xh , t xl ) notes 1. indicates only oscillator characteristics. refer to ac characteristics for instruction execution time. 2. time required to stabilize oscillation after reset or stop mode release. cautions 1. when using the main system clock oscillator, wire as follows in the area enclosed by the broken lines in the above figures to avoid an adverse effect from wiring capacitance. keep the wiring length as short as possible. do not cross the wiring with the other signal lines. do not route the wiring near a signal line through which a high fluctuating current flows. always make the ground point of the oscillator capacitor the same potential as v ss1 . do not ground the capacitor to a ground pattern through which a high current flows. do not fetch signals from the oscillator. 2. when the main system clock is stopped and the system is operating on the subsystem clock, wait until the oscillation stabilization time has been secured by the program before switching back to the main system clock. c2 r1 c1 x1 v ss1 x2 c2 r1 c1 x1 v ss1 x2 x2 x1
522 chapter 26 electrical specifications (conventional products: f x = 1.0 to 8.38 mhz) user s manual u14046ej3v0ud subsystem clock oscillator characteristics (t a = ? 40 to +85 c, v dd = 1.8 to 5.5 v) notes 1. indicates only oscillator characteristics. refer to ac characteristics for instruction execution time. 2. time required to stabilize oscillation after v dd reaches oscillation voltage range min. cautions 1. when using the subsystem clock oscillator, wire as follows in the area enclosed by the broken lines in the above figure to avoid an adverse effect from wiring capacitance. keep the wiring length as short as possible. do not cross the wiring with the other signal lines. do not route the wiring near a signal line through which a high fluctuating current flows. always make the ground point of the oscillator capacitor the same potential as v ss1 . do not ground the capacitor to a ground pattern through which a high current flows. do not fetch signals from the oscillator. 2. the subsystem clock oscillator is designed as a low-amplitude circuit for reducing power consumption, and is more prone to malfunction due to noise than the main system clock oscillator. particular care is therefore required with the wiring method when the subsystem clock is used. remark for the resonator selection and oscillator constant of the subsystem clock, customers are required to either evaluate the oscillation themselves or apply to the resonator manufacturer for evaluation. min. 32 32 resonator crystal resonator external clock parameter oscillation frequency (f xt ) note 1 oscillation stabilization time note 2 xt1 input frequency (f xt ) note 1 xt1 input high-/low-level width (t xth , t xtl ) conditions 4.0 v v dd 5.5 v 1.8 v v dd < 4.0 v typ. 32.768 1.2 max. 35 2 10 38.5 unit khz s khz recommended circuit 12 15 s c3 xt2 xt1 v ss1 r c4 xt1 xt2
523 chapter 26 electrical specifications (conventional products: f x = 1.0 to 8.38 mhz) user s manual u14046ej3v0ud recommended oscillator constant (1/2) to use the pd78f0034by or 78f0034by(a), for the resonator selection and oscillator constant, customers are required to either evaluate the oscillation themselves or apply to the resonator manufacturer for evaluation. (1) mask rom versions of pd780024a, 780034a subseries (conventional product) and pd780024ay, 780034ay subseries main system clock: ceramic resonator (t a = ? 40 to +85 c) manufacturer part number frequency recommended circuit constant oscillation voltage range (mhz) c1 (pf) c2 (pf) r1 (k ? ) min. (v) max. (v) murata mfg. csbfb1m00j58 1.00 100 100 2.2 1.8 5.5 co., ltd. csbla1m00j58 1.00 100 100 2.2 1.8 5.5 cstcc2m00g56 2.00 on-chip on-chip 0 1.8 5.5 cstls2m00g56 2.00 on-chip on-chip 0 1.8 5.5 cstcc3m58g53 3.58 on-chip on-chip 0 1.8 5.5 cstls3m58g53 3.58 on-chip on-chip 0 1.8 5.5 cstcr4m00g53 4.00 on-chip on-chip 0 1.8 5.5 cstls4m00g53 4.00 on-chip on-chip 0 1.8 5.5 cstcr4m19g53 4.19 on-chip on-chip 0 1.8 5.5 cstls4m19g53 4.19 on-chip on-chip 0 1.8 5.5 cstcr4m91g53 4.91 on-chip on-chip 0 1.8 5.5 cstls4m91g53 4.91 on-chip on-chip 0 1.8 5.5 cstcr5m00g53 5.00 on-chip on-chip 0 1.8 5.5 cstls5m00g53 5.00 on-chip on-chip 0 1.8 5.5 cstce8m00g52 8.00 on-chip on-chip 0 2.7 5.5 cstls8m00g53 8.00 on-chip on-chip 0 2.7 5.5 cstce8m38g52 8.38 on-chip on-chip 0 4.0 5.5 cstls8m38g53 8.38 on-chip on-chip 0 4.0 5.5 tdk ccr3.58mc3 3.58 on-chip on-chip 0 1.8 5.5 ccr4.19mc3 4.19 on-chip on-chip 0 1.8 5.5 ccr5.0mc3 5.00 on-chip on-chip 0 1.8 5.5 ccr8.0mc5 8.00 on-chip on-chip 0 2.7 5.5 ccr8.38mc5 8.38 on-chip on-chip 0 4.0 5.5 caution the oscillator constant is a reference value based on evaluation in specific environments by the resonator manufacturer. if the oscillator characteristics need to be optimized in the actual application, request the resonator manufacturer for evaluation on the implementation circuit. note that the oscillation voltage and oscillation frequency merely indicate the characteristics of the oscillator. use the internal operation conditions of the pd780024a, 780024ay, 780034a, 780034ay subseries within the specifications of the dc and ac characteristics.
524 chapter 26 electrical specifications (conventional products: f x = 1.0 to 8.38 mhz) user s manual u14046ej3v0ud recommended oscillator constant (2/2) (2) pd78f0034a, 78f0034ay main system clock: ceramic resonator (t a = ? 40 to +85 c) manufacturer part number frequency recommended circuit constant oscillation voltage range (mhz) c1 (pf) c2 (pf) r1 (k ? ) min. (v) max. (v) murata mfg. csbfb1m00j58 1.00 100 100 2.2 1.9 5.5 co., ltd. csbla1m00j58 1.00 100 100 2.2 1.9 5.5 cstcc2m00g56 2.00 on-chip on-chip 0 1.8 5.5 cstls2m00g56 2.00 on-chip on-chip 0 1.8 5.5 cstcc3m58g53 3.58 on-chip on-chip 0 1.8 5.5 cstls3m58g53 3.58 on-chip on-chip 0 1.8 5.5 cstcr4m00g53 4.00 on-chip on-chip 0 1.8 5.5 cstls4m00g53 4.00 on-chip on-chip 0 1.8 5.5 cstcr4m19g53 4.19 on-chip on-chip 0 1.8 5.5 cstls4m19g53 4.19 on-chip on-chip 0 1.8 5.5 cstcr4m91g53 4.91 on-chip on-chip 0 1.8 5.5 cstls4m91g53 4.91 on-chip on-chip 0 1.8 5.5 cstcr5m00g53 5.00 on-chip on-chip 0 1.8 5.5 cstls5m00g53 5.00 on-chip on-chip 0 1.8 5.5 cstce8m00g52 8.00 on-chip on-chip 0 2.7 5.5 cstls8m00g53 8.00 on-chip on-chip 0 2.7 5.5 cstls8m00g53093 8.00 on-chip on-chip 0 2.7 5.5 cstce8m38g52 8.38 on-chip on-chip 0 4.0 5.5 cstls8m38g53 8.38 on-chip on-chip 0 4.0 5.5 cstls8m38g53093 8.38 on-chip on-chip 0 4.0 5.5 tdk ccr3.58mc3 3.58 on-chip on-chip 0 1.8 5.5 ccr4.19mc3 4.19 on-chip on-chip 0 1.8 5.5 ccr5.0mc3 5.00 on-chip on-chip 0 1.8 5.5 ccr8.0mc5 8.00 on-chip on-chip 0 2.7 5.5 ccr8.38mc5 8.38 on-chip on-chip 0 4.0 5.5 caution the oscillator constant is a reference value based on evaluation in specific environments by the resonator manufacturer. if the oscillator characteristics need to be optimized in the actual application, request the resonator manufacturer for evaluation on the implementation circuit. note that the oscillation voltage and oscillation frequency merely indicate the characteristics of the oscillator. use the internal operation conditions of the pd780024a, 780024ay, 780034a, 780034ay subseries within the specifications of the dc and ac characteristics.
525 chapter 26 electrical specifications (conventional products: f x = 1.0 to 8.38 mhz) user? manual u14046ej3v0ud dc characteristics (t a = ? 40 to +85 c, v dd = 1.8 to 5.5 v) (1/4) parameter symbol conditions min. typ. max. unit output current, i oh per pin ? ma high all pins ?5 ma output current, i ol per pin for p00 to p03, p20 to p25, p34 to p36, 10 ma low p40 to p47, p64 to p67, p70 to p75 per pin for p30 to p33, p50 to p57 15 ma total for p00 to p03, p40 to p47, p64 to p67, p70 to p75 20 ma total for p20 to p25 10 ma total for p30 to p36 70 ma total for p50 to p57 70 ma input voltage, v ih1 p10 to p17, p21, p24, p35, 2.7 v v dd 5.5 v 0.7v dd v dd v high p40 to p47, p50 to p57, 1.8 v v dd < 2.7 v 0.8v dd v dd v p64 to p67, p74, p75 v ih2 p00 to p03, p20, p22, p23, p25, 2.7 v v dd 5.5 v 0.8v dd v dd v p34, p36, p70 to p73, reset 1.8 v v dd < 2.7 v 0.85v dd v dd v v ih3 p30 to p33 2.7 v v dd 5.5 v 0.7v dd 5.5 v (n-ch open-drain) 1.8 v v dd < 2.7 v 0.8v dd 5.5 v v ih4 x1, x2 2.7 v v dd 5.5 v v dd 0.5 v dd v 1.8 v v dd < 2.7 v v dd 0.2 v dd v v ih5 xt1, xt2 4.0 v v dd 5.5 v 0.8v dd v dd v 1.8 v v dd < 4.0 v 0.9v dd v dd v input voltage, v il1 p10 to p17, p21, p24, p35, 2.7 v v dd 5.5 v 0 0.3v dd v low p40 to p47, p50 to p57, 1.8 v v dd < 2.7 v 0 0.2v dd v p64 to p67, p74, p75 v il2 p00 to p03, p20, p22, p23, p25, 2.7 v v dd 5.5 v 0 0.2v dd v p34, p36, p70 to p73, reset 1.8 v v dd < 2.7 v 0 0.15v dd v v il3 p30 to p33 4.0 v v dd 5.5 v 0 0.3v dd v 2.7 v v dd < 4.0 v 0 0.2v dd v 1.8 v v dd < 2.7 v 0 0.1v dd v v il4 x1, x2 2.7 v v dd 5.5 v 0 0.4 v 1.8 v v dd < 2.7 v 0 0.2 v v il5 xt1, xt2 4.0 v v dd 5.5 v 0 0.2v dd v 1.8 v v dd < 4.0 v 0 0.1v dd v output voltage, v oh1 4.0 v v dd 5.5 v, i oh = ? ma v dd 1.0 v dd v high 1.8 v v dd < 4.0 v, i oh = ?00 a v dd 0.5 v dd v output voltage, v ol1 p30 to p33 4.0 v v dd 5.5 v, 2.0 v low v ol2 p50 to p57 i ol = 15 ma 0.4 2.0 v v ol3 p00 to p03, p20 to p25, p34 to p36, 4.0 v v dd 5.5 v, 0.4 v p40 to p47, p64 to p67, p70 to p75 i ol = 1.6 ma v ol4 i ol = 400 a 0.5 v remark unless otherwise specified, the characteristics of alternate-function pins are the same as those of port pins.
526 chapter 26 electrical specifications (conventional products: f x = 1.0 to 8.38 mhz) user s manual u14046ej3v0ud dc characteristics (t a = ? 40 to +85 c, v dd = 1.8 to 5.5 v) (2/4) parameter symbol conditions min. typ. max. unit input leakage i lih1 v in = v dd p00 to p03, p10 to p17, p20 to p25, 3 a current, high p34 to p36, p40 to p47, p50 to p57, p64 to p67, p70 to p75, reset i lih2 x1, x2, xt1, xt2 20 a i lih3 v in = 5.5 v p30 to p33 3 a input leakage i lil1 v in = 0 v p00 to p03, p10 to p17, p20 to p25, 3 a current, low p34 to p36, p40 to p47, p50 to p57, p64 to p67, p70 to p75, reset i lil2 x1, x2, xt1, xt2 20 a i lil3 p30 to p33 3 a output leakage i loh v out = v dd 3 a current, high output leakage i lol v out = 0 v 3 a current, low mask option pull- r 1 v in = 0 v, 15 30 90 k ? up resistance p30, p31, p32 note , p33 note (mask rom version only) software pull- r 2 v in = 0 v, 15 30 90 k ? up resistance p00 to p03, p20 to p25, p34 to p36, p40 to p47, p50 to p57, p64 to p67, p70 to p75 note pd780024a, 780034a subseries only remark unless otherwise specified, the characteristics of alternate-function pins are the same as those of port pins.
527 chapter 26 electrical specifications (conventional products: f x = 1.0 to 8.38 mhz) user s manual u14046ej3v0ud dc characteristics (t a = ? 40 to +85 c, v dd = 1.8 to 5.5 v) (3/4) (1) mask rom versions of pd780024a, 780034a subseries (conventional product) and pd780024ay, 780034ay subseries parameter symbol conditions min. typ. max. unit power supply i dd1 note 2 8.38 mhz v dd = 5.0 v 10% note 3 when a/d converter is 5.5 11 ma current note 1 crystal oscillation stopped operating mode when a/d converter is 6.5 13 ma operating note 6 5.00 mhz v dd = 3.0 v 10% note 3 when a/d converter is 2 4 ma crystal oscillation stopped operating mode when a/d converter is 3 6 ma operating note 6 v dd = 2.0 v 10% note 4 when a/d converter is 0.4 1.5 ma stopped when a/d converter is 1.4 4.2 ma operating note 6 i dd2 8.38 mhz v dd = 5.0 v 10% note 3 when peripheral functions 1.1 2.2 ma crystal oscillation are stopped halt mode when peripheral functions 4.7 ma are operating 5.00 mhz v dd = 3.0 v 10% note 3 when peripheral functions 0.35 0.7 ma crystal oscillation are stopped halt mode when peripheral functions 1.7 ma are operating v dd = 2.0 v 10% note 4 when peripheral functions 0.15 0.4 ma are stopped when peripheral functions 1.1 ma are operating i dd3 32.768 khz crystal oscillation v dd = 5.0 v 10% 40 80 a operating mode note 5 v dd = 3.0 v 10% 20 40 a v dd = 2.0 v 10% 10 20 a i dd4 32.768 khz crystal oscillation v dd = 5.0 v 10% 30 60 a halt mode note 5 v dd = 3.0 v 10% 6 18 a v dd = 2.0 v 10% 2 10 a i dd5 xt1 = v dd , stop mode v dd = 5.0 v 10% 0.1 30 a when feedback resistor is not used v dd = 3.0 v 10% 0.05 10 a v dd = 2.0 v 10% 0.05 10 a notes 1. total current through the internal power supply (v dd0 , v dd1 ) (except the current through pull-up resistors of ports). 2. i dd1 includes the peripheral operation current. 3. when the processor clock control register (pcc) is cleared to 00h. 4. when pcc is set to 02h. 5. when main system clock operation is stopped. 6. includes the current through the av dd pin.
528 chapter 26 electrical specifications (conventional products: f x = 1.0 to 8.38 mhz) user s manual u14046ej3v0ud dc characteristics (t a = ? 40 to +85 c, v dd = 1.8 to 5.5 v) (4/4) (2) pd78f0034a, 78f0034ay, 78f0034by, 78f0034by(a) parameter symbol conditions min. typ. max. unit power supply i dd1 note 2 8.38 mhz v dd = 5.0 v 10% note 3 when a/d converter is 10.5 21 ma current note 1 crystal oscillation stopped operating mode when a/d converter is 11.5 23 ma operating note 6 5.00 mhz v dd = 3.0 v 10% note 3 when a/d converter is 4.5 9 ma crystal oscillation stopped operating mode when a/d converter is 5.5 11 ma operating note 6 v dd = 2.0 v 10% note 4 when a/d converter is 1 2 ma stopped when a/d converter is 2 6 ma operating note 6 i dd2 8.38 mhz v dd = 5.0 v 10% note 3 when peripheral functions 1.2 2.4 ma crystal oscillation are stopped halt mode when peripheral functions 5ma are operating 5.00 mhz v dd = 3.0 v 10% note 3 when peripheral functions 0.4 0.8 ma crystal oscillation are stopped halt mode when peripheral functions 1.7 ma are operating v dd = 2.0 v 10% note 4 when peripheral functions 0.2 0.4 ma are stopped when peripheral functions 1.1 ma are operating i dd3 32.768 khz crystal oscillation v dd = 5.0 v 10% note 2 115 230 a operating mode note 5 v dd = 3.0 v 10% note 2 95 190 a v dd = 2.0 v 10% note 3 75 150 a i dd4 32.768 khz crystal oscillation v dd = 5.0 v 10% note 2 30 60 a halt mode note 5 v dd = 3.0 v 10% note 2 618 a v dd = 2.0 v 10% note 3 210 a i dd5 xt1 = v dd , stop mode v dd = 5.0 v 10% note 2 0.1 30 a when feedback resistor is not used v dd = 3.0 v 10% note 2 0.05 10 a v dd = 2.0 v 10% note 3 0.05 10 a notes 1. total current through the internal power supply (v dd0 , v dd1 ) (except the current through pull-up resistors of ports). 2. i dd1 includes the peripheral operation current. 3. when the processor clock control register (pcc) is cleared to 00h. 4. when pcc is set to 02h. 5. when main system clock operation is stopped. 6. includes the current through the av dd pin.
529 chapter 26 electrical specifications (conventional products: f x = 1.0 to 8.38 mhz) user s manual u14046ej3v0ud ac characteristics (1) basic operation (t a = ? 40 to +85 c, v dd = 1.8 to 5.5 v) parameter symbol conditions min. typ. max. unit cycle time t cy operating with 4.0 v v dd 5.5 v 0.238 16 s (min. instruction main system clock 2.7 v v dd < 4.0 v 0.4 16 s execution time) 1.8 v v dd < 2.7 v 1.6 16 s operating with subsystem clock 103.9 note 1 122 125 s ti00, ti01 input t tih0 , t til0 4.0 v v dd 5.5 v 2/f sam + 0.1 note 2 s high-/low-level 2.7 v v dd < 4.0 v 2/f sam + 0.2 note 2 s width 1.8 v v dd < 2.7 v 2/f sam + 0.5 note 2 s ti50, ti51 input f ti5 2.7 v v dd 5.5 v 0 4 mhz frequency 1.8 v v dd < 2.7 v 0 275 khz ti50, ti51 input t tih5 , t til5 2.7 v v dd 5.5 v 100 ns high-/low-level 1.8 v v dd < 2.7 v 1.8 s width interrupt request t inth , t intl intp0 to intp3, 2.7 v v dd 5.5 v 1 s input high-/low- p40 to p47 1.8 v v dd < 2.7 v 2 s level width reset t rsl 2.7 v v dd 5.5 v 10 s low-level width 1.8 v v dd < 2.7 v 20 s notes 1. value when the external clock is used. when a crystal resonator is used, it is 114 s (min.). 2. selection of f sam = f x , f x /4, f x /64 is possible using bits 0 and 1 (prm00, prm01) of prescaler mode register 0 (prm0). however, if the ti00 valid edge is selected as the count clock, the value becomes f sam = f x /8.
530 chapter 26 electrical specifications (conventional products: f x = 1.0 to 8.38 mhz) user s manual u14046ej3v0ud t cy vs. v dd (main system clock operation) 5.0 1.0 2.0 1.6 0.4 0.238 0.1 0 10.0 1.0 2.0 3.0 4.0 5.0 6.0 1.8 5.5 2.7 operation guaranteed range 16.0 cycle time t cy [ s] supply voltage v dd [v]
531 chapter 26 electrical specifications (conventional products: f x = 1.0 to 8.38 mhz) user s manual u14046ej3v0ud (2) read/write operation (t a = ? 40 to +85 c, v dd = 4.0 to 5.5 v) (1/3) parameter symbol conditions min. max. unit astb high-level width t asth 0.3t cy ns address setup time t ads 20 ns address hold time t adh 6ns data input time from address t add1 (2 + 2n)t cy 54 ns t add2 (3 + 2n)t cy 60 ns address output time from rd t rdad 0 100 ns data input time from rd t rdd1 (2 + 2n)t cy 87 ns t rdd2 (3 + 2n)t cy 93 ns read data hold time t rdh 0ns rd low-level width t rdl1 (1.5 + 2n)t cy 33 ns t rdl2 (2.5 + 2n)t cy 33 ns input time from rd to wait t rdwt1 t cy 43 ns t rdwt2 t cy 43 ns input time from wr to wait t wrwt t cy 25 ns wait low-level width t wtl (0.5 + 2n)t cy + 10 (2 + 2n)t cy ns write data setup time t wds 60 ns write data hold time t wdh 6ns wr low-level width t wrl1 (1.5 + 2n)t cy 15 ns delay time from astb to rd t astrd 6ns delay time from astb to wr t astwr 2t cy 15 ns delay time from t rdast 0.8t cy 15 1.2t cy ns rd to astb at external fetch address hold time from t rdadh 0.8t cy 15 1.2t cy + 30 ns rd at external fetch write data output time from rd t rdwd 40 ns write data output time from wr t wrwd 10 60 ns address hold time from wr t wradh 0.8t cy 15 1.2t cy + 30 ns delay time from wait to rd t wtrd 0.8t cy 2.5t cy + 25 ns delay time from wait to wr t wtwr 0.8t cy 2.5t cy + 25 ns remarks 1. t cy = t cy /4 2. n indicates the number of waits. 3 .c l = 100 pf (c l indicates the load capacitance of the ad0 to ad7, a8 to a15, rd, wr, wait, and astb pins.)
532 chapter 26 electrical specifications (conventional products: f x = 1.0 to 8.38 mhz) user s manual u14046ej3v0ud (2) read/write operation (t a = ? 40 to +85 c, v dd = 2.7 to 4.0 v) (2/3) parameter symbol conditions min. max. unit astb high-level width t asth 0.3t cy ns address setup time t ads 30 ns address hold time t adh 10 ns input time from address to data t add1 (2 + 2n)t cy 108 ns t add2 (3 + 2n)t cy 120 ns output time from rd to address t rdad 0 200 ns input time from rd to data t rdd1 (2 + 2n)t cy 148 ns t rdd2 (3 + 2n)t cy 162 ns read data hold time t rdh 0ns rd low-level width t rdl1 (1.5 + 2n)t cy 40 ns t rdl2 (2.5 + 2n)t cy 40 ns input time from rd to wait t rdwt1 t cy 75 ns t rdwt2 t cy 60 ns input time from wr to wait t wrwt t cy 50 ns wait low-level width t wtl (0.5 + 2n)t cy + 10 (2 + 2n)t cy ns write data setup time t wds 60 ns write data hold time t wdh 10 ns wr low-level width t wrl1 (1.5 + 2n)t cy 30 ns delay time from astb to rd t astrd 10 ns delay time from astb to wr t astwr 2t cy 30 ns delay time from t rdast 0.8t cy 30 1.2t cy ns rd to astb at external fetch hold time from t rdadh 0.8t cy 30 1.2t cy + 60 ns rd to address at external fetch write data output time from rd t rdwd 40 ns write data output time from wr t wrwd 20 120 ns hold time from wr to address t wradh 0.8t cy 30 1.2t cy + 60 ns delay time from wait to rd t wtrd 0.5t cy 2.5t cy + 50 ns delay time from wait to wr t wtwr 0.5t cy 2.5t cy + 50 ns remarks 1. t cy = t cy /4 2. n indicates the number of waits. 3. c l = 100 pf (c l indicates the load capacitance of the ad0 to ad7, a8 to a15, rd, wr, wait, and astb pins.)
533 chapter 26 electrical specifications (conventional products: f x = 1.0 to 8.38 mhz) user s manual u14046ej3v0ud (2) read/write operation (t a = ? 40 to +85 c, v dd = 1.8 to 2.7 v) (3/3) parameter symbol conditions min. max. unit astb high-level width t asth 0.3t cy ns address setup time t ads 120 ns address hold time t adh 20 ns input time from address to data t add1 (2 + 2n)t cy 233 ns t add2 (3 + 2n)t cy 240 ns output time from rd to address t rdad 0 400 ns input time from rd to data t rdd1 (2 + 2n)t cy 325 ns t rdd2 (3 + 2n)t cy 332 ns read data hold time t rdh 0ns rd low-level width t rdl1 (1.5 + 2n)t cy 92 ns t rdl2 (2.5 + 2n)t cy 92 ns input time from rd to wait t rdwt1 t cy 350 ns t rdwt2 t cy 132 ns input time from wr to wait t wrwt t cy 100 ns wait low-level width t wtl (0.5 + 2n)t cy + 10 (2 + 2n)t cy ns write data setup time t wds 60 ns write data hold time t wdh 20 ns wr low-level width t wrl1 (1.5 + 2n)t cy 60 ns delay time from astb to rd t astrd 20 ns delay time from astb to wr t astwr 2t cy 60 ns delay time from t rdast 0.8t cy 60 1.2t cy ns rd to astb at external fetch hold time from t rdadh 0.8t cy 60 1.2t cy + 120 ns rd to address at external fetch write data output time from rd t rdwd 40 ns write data output time from wr t wrwd 40 240 ns hold time from wr to address t wradh 0.8t cy 60 1.2t cy + 120 ns delay time from wait to rd t wtrd 0.5t cy 2.5t cy + 100 ns delay time from wait to wr t wtwr 0.5t cy 2.5t cy + 100 ns remarks 1. t cy = t cy /4 2. n indicates the number of waits. 3. c l = 100 pf (c l indicates the load capacitance of the ad0 to ad7, a8 to a15, rd, wr, wait, and astb pins.)
534 chapter 26 electrical specifications (conventional products: f x = 1.0 to 8.38 mhz) user s manual u14046ej3v0ud (3) serial interface (t a = ? 40 to +85 c, v dd = 1.8 to 5.5 v) (1/3) (a) 3-wire serial i/o mode (sck3n... internal clock output) parameter symbol conditions min. typ. max. unit sck3n t kcy1 4.0 v v dd 5.5 v 954 ns cycle time 2.7 v v dd < 4.0 v 1600 ns 1.8 v v dd < 2.7 v 3200 ns sck3n high-/ t kh1 , t kl1 4.0 v v dd 5.5 v t kcy1 /2 50 ns low-level width 1.8 v v dd < 4.0 v t kcy1 /2 100 ns si3n setup time t sik1 4.0 v v dd 5.5 v 100 ns (to sck3n ) 2.7 v v dd < 4.0 v 150 ns 1.8 v v dd < 2.7 v 300 ns si3n hold time t ksi1 400 ns (from sck3n ) delay time from t kso1 c = 100 pf note 300 ns sck3n to so3n output note c is the load capacitance of the sck3n and so3n output lines. (b) 3-wire serial i/o mode (sck3n... external clock input) parameter symbol conditions min. typ. max. unit sck3n t kcy2 4.0 v v dd 5.5 v 800 ns cycle time 2.7 v v dd < 4.0 v 1600 ns 1.8 v v dd < 2.7 v 3200 ns sck3n high-/ t kh2 , t kl2 4.0 v v dd 5.5 v 400 ns low-level width 2.7 v v dd < 4.0 v 800 ns 1.8 v v dd < 2.7 v 1600 ns si3n setup time t sik2 100 ns (to sck3n ) si3n hold time t ksi2 400 ns (from sck3n ) delay time from t kso2 c = 100 pf note 300 ns sck3n to so3n output note c is the load capacitance of the so3n output line. remark pd780024a, 780034a subseries: n = 0, 1 pd780024ay, 780034ay subseries: n = 0
535 chapter 26 electrical specifications (conventional products: f x = 1.0 to 8.38 mhz) user s manual u14046ej3v0ud (3) serial interface (t a = ? 40 to +85 c, v dd = 1.8 to 5.5 v) (2/3) (c) uart mode (dedicated baud-rate generator output) parameter symbol conditions min. typ. max. unit transfer rate 4.0 v v dd 5.5 v 131031 bps 2.7 v v dd < 4.0 v 78125 bps 1.8 v v dd < 2.7 v 39063 bps (d) uart mode (external clock input) parameter symbol conditions min. typ. max. unit asck0 cycle time t kcy3 4.0 v v dd 5.5 v 800 ns 2.7 v v dd < 4.0 v 1600 ns 1.8 v v dd < 2.7 v 3200 ns asck0 high-/low-level width t kh3 , 4.0 v v dd 5.5 v 400 ns t kl3 2.7 v v dd < 4.0 v 800 ns 1.8 v v dd < 2.7 v 1600 ns transfer rate 4.0 v v dd 5.5 v 39063 bps 2.7 v v dd < 4.0 v 19531 bps 1.8 v v dd < 2.7 v 9766 bps (e) uart mode (infrared data transfer mode) parameter symbol conditions min. max. unit transfer rate 4.0 v v dd 5.5 v 131031 bps allowable bit rate error 4.0 v v dd 5.5 v 0.87 % output pulse width 4.0 v v dd 5.5 v 1.2 0.24/fbr note s input pulse width 4.0 v v dd 5.5 v 4/f x s note fbr: specified baud rate
536 chapter 26 electrical specifications (conventional products: f x = 1.0 to 8.38 mhz) user s manual u14046ej3v0ud (3) serial interface (t a = ? 40 to +85 c, v dd = 1.8 to 5.5 v) (3/3) (f) i 2 c bus mode ( pd780024ay, 780034ay subseries only) parameter symbol standard mode high-speed mode unit min. max. min. max. scl0 clock frequency f clk 0 100 0 400 kh z bus free time t buf 4.7 ? 1.3 ? s (between stop and start conditions) hold time note 1 t hd:sta 4.0 ? 0.6 ? s scl0 clock low-level width t low 4.7 ? 1.3 ? s scl0 clock high-level width t high 4.0 ? 0.6 ? s start/restart condition setup time t su:sta 4.7 ? 0.6 ? s data hold time cbus-compatible master t hd:dat 5.0 ??? s i 2 c bus 0 note 2 ? 0 note 2 0.9 note 3 s data setup time t su:dat 250 ? 100 note 4 ? ns sda0 and scl0 signal rise time t r ? 1000 20 + 0.1cb note 5 300 ns sda0 and scl0 signal fall time t f ? 300 20 + 0.1cb note 5 300 ns stop condition setup time t su:sto 4.0 ? 0.6 ? s spike pulse width controlled by input filter t sp ?? 0 50 ns capacitive load per bus line cb ? 400 ? 400 pf notes 1. in the start condition, the first clock pulse is generated after this hold time. 2. to fill in the undefined area of the scl0 falling edge, it is necessary for the device to internally provide at least 300 ns of hold time for the sda0 signal (which is v ihmin . of the scl0 signal). 3. if the device does not extend the scl0 signal low hold time (t low ), only the maximum data hold time t hd:dat needs to be fulfilled. 4. the high-speed mode i 2 c bus is available in a standard mode i 2 c bus system. at this time, the conditions described below must be satisfied. if the device does not extend the scl0 signal low state hold time t su:dat 250 ns if the device extends the scl0 signal low state hold time be sure to transmit the next data bit to the sda0 line before the scl0 line is released (t rmax . + t su:dat = 1000 + 250 = 1250 ns by standard mode i 2 c bus specification). 5. cb: total capacitance per bus line (unit: pf)
537 chapter 26 electrical specifications (conventional products: f x = 1.0 to 8.38 mhz) user s manual u14046ej3v0ud a/d converter characteristics (t a = ? 40 to +85 c, v dd = av dd = 1.8 to 5.5 v, av ss = v ss = 0 v) (1/2) (1) 8-bit a/d converter: pd780024a, 780024ay subseries parameter symbol conditions min. typ. max. unit resolution 888bit overall error note 4.0 v av ref 5.5 v 0.4 %fsr 2.7 v av ref < 4.0 v 0.6 %fsr 1.8 v av ref < 2.7 v 1.2 %fsr conversion time t conv 4.0 v av dd 5.5 v 14 96 s 2.7 v av dd < 4.0 v 19 96 s 1.8 v av dd < 2.7 v 28 96 s analog input voltage v ain 0av ref v reference voltage av ref 1.8 av dd v resistance between av ref and av ss r ref during a/d converter operation 20 40 k ? note excludes quantization error ( 1/2 lsb). this value is indicated as a ratio (%fsr) to the full-scale value. remark the impedance of the analog input pins is shown below. [equivalent circuit] [parameter value] (typ.) av dd r1 r2 c1 c2 c3 2.7 v 12 k ? 8.0 k ? 3.0 pf 3.0 pf 2.0 pf 4.5 v 4 k ? 2.7 k ? 3.0 pf 1.4 pf 2.0 pf c3 c2 r2 r1 c1 anin (n = 0 to 3)
538 chapter 26 electrical specifications (conventional products: f x = 1.0 to 8.38 mhz) user s manual u14046ej3v0ud a/d converter characteristics (t a = ? 40 to +85 c, v dd = av dd = 1.8 to 5.5 v, av ss = v ss = 0 v) (2/2) (2) 10-bit a/d converter: pd780034a, 780034ay subseries parameter symbol conditions min. typ. max. unit resolution 10 10 10 bit overall error notes 1, 2 4.0 v av ref 5.5 v 0.2 0.4 %fsr 2.7 v av ref < 4.0 v 0.3 0.6 %fsr 1.8 v av ref < 2.7 v 0.6 1.2 %fsr conversion time t conv 4.0 v av dd 5.5 v 14 96 s 2.7 v av dd < 4.0 v 19 96 s 1.8 v av dd < 2.7 v 28 96 s zero-scale error notes 1, 2 4.0 v av ref 5.5 v 0.4 %fsr 2.7 v av ref < 4.0 v 0.6 %fsr 1.8 v av ref < 2.7 v 1.2 %fsr full-scale error notes 1, 2 4.0 v av ref 5.5 v 0.4 %fsr 2.7 v av ref < 4.0 v 0.6 %fsr 1.8 v av ref < 2.7 v 1.2 %fsr integral linearity error note 1 4.0 v av ref 5.5 v 2.5 lsb 2.7 v av ref < 4.0 v 4.5 lsb 1.8 v av ref < 2.7 v 8.5 lsb differential linearity error 4.0 v av ref 5.5 v 1.5 lsb 2.7 v av ref < 4.0 v 2.0 lsb 1.8 v av ref < 2.7 v 3.5 lsb analog input voltage v ain 0av ref v reference voltage av ref 1.8 av dd v resistance between av ref and av ss r ref during a/d converter operation 20 40 k ? notes 1. excludes quantization error ( 1/2 lsb). 2. this value is indicated as a ratio to the full-scale value. remark the impedance of the analog input pins is shown below. [equivalent circuit] [parameter value] (typ.) av dd r1 r2 c1 c2 c3 2.7 v 12 k ? 8.0 k ? 3.0 pf 3.0 pf 2.0 pf 4.5 v 4 k ? 2.7 k ? 3.0 pf 1.4 pf 2.0 pf c3 c2 r2 r1 c1 anin (n = 0 to 3)
539 chapter 26 electrical specifications (conventional products: f x = 1.0 to 8.38 mhz) user s manual u14046ej3v0ud data memory stop mode low supply voltage data retention characteristics (t a = 40 to +85 c) parameter symbol conditions min. typ. max. unit data retention power v dddr 1.6 5.5 v supply voltage data retention power i dddr v dddr = 1.6 v 0.1 30 a supply current (subsystem clock unused (xt1 = v dd ) and feedback resistor disconnected) release signal set time t srel 0 s oscillation stabilization t wait release by reset 2 17 /f x s wait time release by interrupt request note s note selection of 2 12 /f x and 2 14 /f x to 2 17 /f x is possible using bits 0 to 2 (osts0 to osts2) of the oscillation stabilization time select register (osts).
540 chapter 26 electrical specifications (conventional products: f x = 1.0 to 8.38 mhz) user s manual u14046ej3v0ud flash memory programming characteristics (1/3) (t a = +10 to +40 c, v dd = av dd = 2.7 to 5.5 v, v ss = av ss = 0 v) (1) pd78f0034a, 78f0034ay (a) write erase characteristics parameter symbol conditions min. typ. max. unit operating frequency f x 4.0 v v dd 5.5 v 1.0 8.38 mhz 2.7 v v dd < 4.0 v 1.0 5.0 mhz v pp supply voltage v pp2 during flash memory 9.7 10.0 10.3 v programming note 1 v dd supply current note 2 i dd when 8.38 mhz crystal v dd = 5.0 v 10% 24 ma v pp = v pp2 oscillation operating mode 5.0 mhz crystal v dd = 3.0 v 10% 12 ma oscillation operating mode v pp supply current i pp when v pp = v pp2 100 ma step erase time note 3 t er 0.99 1.0 1.01 s overall erase time note 4 t era when step erase time = 1 s 20 s/chip step write time note 5 t wr 50 100 s overall write time per word note 6 t wrw when step write time = 100 s (1 word = 1 byte) 1000 s number of rewrites per chip note 7 c erwr 1 erase + 1 write after erase = 1 rewrite 20 note 8 times/area notes 1. product rank k, e, p indicates 10.2 v (min.), 10.3 v (typ.), and 10.4 v (max.). 2. av dd current and port current (current that flows through the internal pull-up resistor) are not included. 3. the recommended setting value of the step erase time is 1 s. 4. the prewrite time before erasure and the erase verify time are not included. 5. the recommended setting value of the step write time is 50 s. 6. the actual write time per word is 100 s longer. the internal verify time during or after a write is not included. 7. when a product is first written after shipment, erase write and write only are both taken as one rewrite. example: p: write, e: erase shipped product p e p e p: 3 rewrites shipped product e p e p e p: 3 rewrites 8. product rank k, e indicates one time (max.). (b) serial write operation characteristics parameter symbol conditions min. typ. max. unit set time from v dd to v pp t dp 10 s release time from v pp to reset t pr 1.0 s v pp pulse input start time from t rp 1.0 s reset v pp pulse high-/low-level width t pw 8.0 s v pp pulse input end time from t rpe 20 ms reset v pp pulse low-level input voltage v ppl 0.8v dd v dd 1.2v dd v v pp pulse high-level input voltage v pph 9.7 10.0 10.3 v
541 chapter 26 electrical specifications (conventional products: f x = 1.0 to 8.38 mhz) user s manual u14046ej3v0ud flash memory programming characteristics (2/3) (t a = +10 to +40 c, v dd = av dd = 1.8 to 5.5 v, v ss = av ss = 0 v) (2) pd78f0034by, 78f0034by(a) (a) write erase characteristics parameter symbol conditions min. typ. max. unit operating frequency f x 4.0 v v dd 5.5 v 1.0 8.38 mhz 2.7 v v dd < 4.0 v 1.0 5.0 mhz 1.8 v v dd < 2.7 v 1.0 1.25 mhz v pp supply voltage v pp2 during flash memory programming 9.7 10.0 10.3 v v dd supply current note 1 i dd when 8.38 mhz crystal v dd = 5.0 v 10% 24 ma v pp = v pp2 oscillation v dd = 3.0 v 10% 17 ma operating mode v pp supply current i pp when v pp = v pp2 100 ma step erase time note 2 t er 0.199 0.2 0.201 s overall erase time note 3 t era when step erase time = 0.2 s 20 s/chip writeback time note 4 t wb 49.4 50 50.6 ms number of writebacks per c wb when writeback time = 50 ms 60 times writeback command note 5 number of erases/writebacks c erwb 16 times step write time note 6 t wr 48 50 52 s overall write time per word note 7 t wrw when step write time = 50 s (1 word = 1 byte) 48 520 s number of rewrites per chip note 8 c erwr 1 erase + 1 write after erase = 1 rewrite 20 times/area notes 1. av dd current and port current (current that flows through the internal pull-up resistor) are not included. 2. the recommended setting value of the step erase time is 0.2 s. 3. the prewrite time before erasure and the erase verify time (writeback time) are not included. 4. the recommended setting value of the writeback time is 50 ms. 5. writeback is executed once by the issuance of the writeback command. therefore, the number of retries must be the maximum value minus the number of commands issued. 6. the recommended setting value of the step write time is 50 s. 7. the actual write time per word is 100 s longer. the internal verify time during or after a write is not included. 8. when a product is first written after shipment, erase write and write only are both taken as one rewrite. example: p: write, e: erase shipped product p e p e p: 3 rewrites shipped product e p e p e p: 3 rewrites
542 chapter 26 electrical specifications (conventional products: f x = 1.0 to 8.38 mhz) user s manual u14046ej3v0ud flash memory programming characteristics (3/3) (t a = +10 to +40 c, v dd = av dd = 1.8 to 5.5 v, v ss = av ss = 0 v) (b) serial write operation characteristics parameter symbol conditions min. typ. max. unit set time from v dd to v pp t dp 10 s release time from v pp to reset t pr 1.0 s v pp pulse input start time from t rp 1.0 s reset v pp pulse high-/low-level width t pw 8.0 s v pp pulse input end time from t rpe 20 ms reset v pp pulse low-level input voltage v ppl 0.8v dd 1.2v dd v v pp pulse high-level input voltage v pph 9.7 10.0 10.3 v
543 chapter 26 electrical specifications (conventional products: f x = 1.0 to 8.38 mhz) user s manual u14046ej3v0ud timing charts ac timing test points (excluding x1, xt1 input) clock timing ti timing 0.8v dd 0.2v dd test points 0.8v dd 0.2v dd t xl t xh 1/f x v ih4 (min.) v il4 (max.) t xtl t xth 1/f xt v ih5 (min.) v il5 (max.) x1 input xt1 input t til0 t tih0 ti00, ti01 1/f ti5 t tih5 t til5 ti50, ti51
544 chapter 26 electrical specifications (conventional products: f x = 1.0 to 8.38 mhz) user s manual u14046ej3v0ud interrupt request input timing reset input timing t rsl reset intp0 to intp3 t intl t inth
545 chapter 26 electrical specifications (conventional products: f x = 1.0 to 8.38 mhz) user s manual u14046ej3v0ud read/write operation external fetch (no wait): external fetch (wait insertion): a8 to a15 ad0 to ad7 astb rd higher 8-bit address lower 8-bit address t add1 hi-z t ads t asth t adh t rdd1 t rdad instruction code t rdadh t rdast t astrd t rdl1 t rdh a8 to a15 ad0 to ad7 astb rd higher 8-bit address lower 8-bit address t add1 hi-z t ads t asth t adh t rdad t rdd1 instruction code t rdadh t rdast t astrd t rdl1 t rdh wait t rdwt1 t wtl t wtrd
546 chapter 26 electrical specifications (conventional products: f x = 1.0 to 8.38 mhz) user s manual u14046ej3v0ud external data access (no wait): external data access (wait insertion): a8 to a15 ad0 to ad7 astb rd higher 8-bit address lower 8-bit address t add2 t ads t asth t adh t rdad t rdd2 read data t astrd wr t astwr write data hi-z t wdh t wradh t wds t wrwd t wrl1 t rdh t rdl2 t rdwt2 t wtl t wrwt t wtl t wtwr t wtrd wait t rdwd hi-z a8 to a15 ad0 to ad7 astb rd higher 8-bit address lower 8-bit address t add2 hi-z t ads t asth t adh t rdd2 t rdad read data t astrd t rdwd wr t astwr write data hi-z t wdh t wradh t wds t wrwd t wrl1 t rdh t rdl2
547 chapter 26 electrical specifications (conventional products: f x = 1.0 to 8.38 mhz) user s manual u14046ej3v0ud serial transfer timing 3-wire serial i/o mode: remarks 1. m = 1, 2 2. pd780024a, 780034a subseries: n = 0, 1 pd780024ay, 780034ay subseries: n = 0 uart mode (external clock input): t kcy3 t kh3 t kl3 asck0 i 2 c bus mode ( pd780024ay, 780034ay subseries only): scl0 sda0 t hd:sta t buf t hd:dat t high t f t su:dat t su:sta t hd:sta t sp t su : sto t r t low stop condition start condition stop condition restart condition t kcym t klm t khm sck3n si3n so3n t sikm t ksim t ksom input data output data
548 chapter 26 electrical specifications (conventional products: f x = 1.0 to 8.38 mhz) user s manual u14046ej3v0ud data retention timing (stop mode release by reset) data retention timing (standby release signal: stop mode release by interrupt request signal) t srel t wait v dd reset stop instruction execution stop mode data retention mode internal reset operation halt mode operating mode v dddr t srel t wait v dd stop instruction execution stop mode data retention mode halt mode operating mode standby release signal (interrupt request) v dddr
549 chapter 26 electrical specifications (conventional products: f x = 1.0 to 8.38 mhz) user s manual u14046ej3v0ud flash memory write mode set timing v dd v dd 0 v 0 v v dd reset (input) 0 v v pph v pp v ppl t rp t pr t dp t pw t pw t rpe
550 user? manual u14046ej3v0ud chapter 27 package drawings remark the external dimensions and materials of the es version are the same as those of the mass-produced version. i j g h f d n m cb m r 64 33 32 1 l notes p64c-70-750a,c-4 item millimeters b c d f g h j k 1.778 (t.p.) 3.2 0.3 0.51 min. 1.78 max. l m 0.17 0.25 19.05 (t.p.) 5.08 max. 17.0 0.2 n 0 ~ 15 0.50 0.10 0.9 min. r +0.10 -0.05 1. each lead centerline is located within 0.17 mm of its true position (t.p.) at maximum material condition. 2. item "k" to center of leads when formed parallel. a 58.0 +0.68 -0.20 i 4.05 +0.26 -0.20 64-pin plastic sdip (19.05mm(750)) a k
551 chapter 27 package drawings user s manual u14046ej3v0ud remark the external dimensions and materials of the es version are the same as those of the mass-produced version. 48 49 32 64 1 17 16 33 64-pin plastic qfp (14x14) note each lead centerline is located within 0.15 mm of its true position (t.p.) at maximum material condition. item millimeters a b d g 17.6 0.4 14.0 0.2 0.8 (t.p.) 1.0 j 17.6 0.4 k p64gc-80-ab8-5 c 14.0 0.2 i 0.15 1.8 0.2 l 0.8 0.2 f 1.0 n p q 0.10 2.55 0.1 0.1 0.1 r s 5 5 2.85 max. h 0.37 +0.08 -0.07 m 0.17 +0.08 -0.07 s s n j detail of lead end c d a b r k m l p i s q g f m h
552 chapter 27 package drawings user s manual u14046ej3v0ud remark the external dimensions and materials of the es version are the same as those of the mass-produced version. 64-pin plastic lqfp (14x14) note each lead centerline is located within 0.20 mm of its true position (t.p.) at maximum material condition. item millimeters a b d g 17.2 0.2 14.0 0.2 0.8 (t.p.) 1.0 j 17.2 0.2 k c 14.0 0.2 i 0.20 1.6 0.2 l 0.8 f 1.0 n p q 0.10 1.4 0.1 0.127 0.075 u 0.886 0.15 r s 3 1.7 max. t 0.25 p64gc-80-8bs h 0.37 + 0.08 ? 0.07 m 0.17 + 0.03 ? 0.06 s n j t detail of lead end c d a b k m i s p r l u q g f m h + 4 ? 3 1 64 49 17 32 16 48 33 s
553 chapter 27 package drawings user s manual u14046ej3v0ud remark the external dimensions and materials of the es version are the same as those of the mass-produced version. 48 32 33 64 1 17 16 49 s s 64-pin plastic tqfp (12x12) item millimeters g 1.125 a 14.0 0.2 c 12.0 0.2 d f 1.125 14.0 0.2 b 12.0 0.2 n 0.10 p q 0.1 0.05 1.0 s r 3 + 4 ? 3 r h k j q g i s p detail of lead end note each lead centerline is located within 0.13 mm of its true position (t.p.) at maximum material condition. m h 0.32 + 0.06 ? 0.10 i 0.13 j k 1.0 0.2 0.65 (t.p.) l 0.5 m 0.17 + 0.03 ? 0.07 p64gk-65-9et-3 t u 0.6 0.15 0.25 f m a b cd n t l u 1.1 0.1
554 chapter 27 package drawings user s manual u14046ej3v0ud remark the external dimensions and materials of the es version are the same as those of the mass-produced version. m 48 32 33 64 1 17 16 49 s n s j detail of lead end r k m i s l t p q g f h 64-pin plastic lqfp (10x10) item millimeters a b d g 12.0 0.2 10.0 0.2 1.25 12.0 0.2 h 0.22 0.05 c 10.0 0.2 f 1.25 i j k 0.08 0.5 (t.p.) 1.0 0.2 l 0.5 p 1.4 q 0.1 0.05 t 0.25 s 1.5 0.10 u 0.6 0.15 s64gb-50-8eu-1 r3 + 4 ? 3 n 0.08 m 0.17 + 0.03 ? 0.07 a b cd u
555 chapter 27 package drawings user s manual u14046ej3v0ud remark the external dimensions and materials of the es version are the same as those of the mass-produced version. b s a a b c d e f g h j s wb y1 s s wa s y s e x ba a1 a2 a b m ? e ze zd 9 8 7 6 5 4 3 2 1 index mark d item dimensions d e w a a1 a2 e 9.00 0.10 9.00 0.10 0.80 0.08 0.10 0.20 1.30 1.30 0.20 0.35 0.06 1.28 0.10 0.93 p73f1-80-cn3 0.50 +0.05 0.10 (unit:mm) x y y1 zd ze b 73-pin plastic fbga (9x9)
556 user? manual u14046ej3v0ud chapter 28 recommended soldering conditions this product should be soldered and mounted under the following recommended conditions. for soldering methods and conditions other than those recommended below, contact an nec electronics sales representative. for technical information, see the following website. semiconductor device mount manual (http://www.necel.com/pkg/en/mount/index.html) caution evaluation of the soldering conditions for the following products is incomplete because these products are under development. ? 64-pin plastic lqfp (gb-8eu type) of pd780021a(a), 780022a(a), 780023a(a), 780024a(a), 780031a(a), 780032a(a), 780033a(a), 780034a(a) ? pd780021ay(a), 780022ay(a) (except 64-pin plastic qfp (gc-ab8 type)), 780023ay(a), 780024ay(a), 780031ay(a), 780032ay(a), 780033ay(a), 780034ay(a) table 28-1. surface mounting type soldering conditions (1/5) (1) 64-pin plastic qfp (14 14) pd780021agc- -ab8, 780022agc- -ab8, 780023agc- -ab8, pd780024agc- -ab8, 780021aygc- -ab8, 780022aygc- -ab8, pd780023aygc- -ab8, 780024aygc- -ab8, 780031agc- -ab8, pd780032agc- -ab8, 780033agc- -ab8, 780034agc- -ab8, pd780031aygc- -ab8, 780032aygc- -ab8, 780033aygc- -ab8, pd780034aygc- -ab8, 780021agc(a)- -ab8, 780022agc(a)- -ab8, pd780023agc(a)- -ab8, 780024agc(a)- -ab8, 780022aygc(a)- -ab8, pd780031agc(a)- -ab8, 780032agc(a)- -ab8, 780033agc(a)- -ab8, pd780034agc(a)- -ab8 soldering method soldering conditions recommended condition symbol infrared reflow package peak temperature: 235 c, time: 30 seconds max. ir35-00-3 (at 210 c or higher), count: three times or less vps package peak temperature: 215 c, time: 40 seconds max. vp15-00-3 (at 200 c or higher), count: three times or less wave soldering solder bath temperature: 260 c max., time: 10 seconds max., ws60-00-1 count: once, preheating temperature: 120 c max. (package surface temperature) partial heating pin temperature: 300 c max., time: 3 seconds max. (per pin row) ? caution do not use different soldering methods together (except for partial heating).
557 chapter 28 recommended soldering conditions user? manual u14046ej3v0ud table 28-1. surface mounting type soldering conditions (2/5) (2) 64-pin plastic lqfp (14 14) pd780021agc- -8bs, 780022agc- -8bs, 780023agc- -8bs, pd780024agc- -8bs, 780021aygc- -8bs, 780022aygc- -8bs, pd780023aygc- -8bs, 780024aygc- -8bs, 780031agc- -8bs, pd780032agc- -8bs, 780033agc- -8bs, 780034agc- -8bs, pd780031aygc- -8bs, 780032aygc- -8bs, 780033aygc- -8bs, pd780034aygc- -8bs, 780021agc(a)- -8bs, 780022agc(a)- -8bs, pd780023agc(a)- -8bs, 780024agc(a)- -8bs, 780031agc(a)- -8bs, pd780032agc(a)- -8bs, 780033agc(a)- -8bs, 780034agc(a)- -8bs, pd78f0034agc-8bs, 78f0034aygc-8bs, 78f0034bgc-8bs, pd78f0034bygc-8bs, 78f0034bgc(a)-8bs, 78f0034bygc(a)-8bs 64-pin plastic qfp (14 14) pd78f0034agc-ab8 note , 78f0034aygc-ab8 soldering method soldering conditions recommended condition symbol infrared reflow package peak temperature: 235 c, time: 30 seconds max. ir35-00-2 (at 210 c or higher), count: two times or less vps package peak temperature: 215 c, time: 40 seconds max. vp15-00-2 (at 200 c or higher), count: two times or less wave soldering solder bath temperature: 260 c max., time: 10 seconds max., ws60-00-1 count: once, preheating temperature: 120 c max. (package surface temperature) partial heating pin temperature: 300 c max., time: 3 seconds max. (per pin row) ? note maintenance product caution do not use different soldering methods together (except for partial heating).
558 chapter 28 recommended soldering conditions user? manual u14046ej3v0ud table 28-1. surface mounting type soldering conditions (3/5) (3) 64-pin plastic tqfp (12 12) pd780021agk- -9et, 780022agk- -9et, 780023agk- -9et, pd780024agk- -9et, 780021aygk- -9et, 780022aygk- -9et, pd780023aygk- -9et, 780024aygk- -9et, 780031agk- -9et, pd780032agk- -9et, 780033agk- -9et, 780034agk- -9et, pd780031aygk- -9et, 780032aygk- -9et, 780033aygk- -9et, pd780034aygk- -9et, 780021agk(a)- -9et, 780022agk(a)- -9et, pd780023agk(a)- -9et, 780024agk(a)- -9et, 780031agk(a)- -9et, pd780032agk(a)- -9et, 780033agk(a)- -9et, 780034agk(a)- -9et, pd78f0034agk-9et, 78f0034aygk-9et, 78f0034bgk-9et, 78f0034bygk-9et, pd78f0034bgk(a)-9et, 78f0034bygk(a)-9et soldering method soldering conditions recommended condition symbol infrared reflow package peak temperature: 235 c, time: 30 seconds max. ir35-107-2 (at 210 c or higher), count: two times or less, exposure limit: 7 days note (after that, prebake at 125 c for 10 hours) vps package peak temperature: 215 c, time: 40 seconds max. vp15-107-2 (at 200 c or higher), count: two times or less, exposure limit: 7 days note (after that, prebake at 125 c for 10 hours) wave soldering solder bath temperature: 260 c max., time: 10 seconds max., ws60-107-1 count: once, preheating temperature: 120 c max. (package surface temperature), exposure limit: 7 days note (after that, prebake at 125 c for 10 hours) partial heating pin temperature: 300 c max., time: 3 seconds max. (per pin row) ? note after opening the dry pack, store it at 25 c or less and 65% rh or less for the allowable storage period. caution do not use different soldering methods together (except for partial heating).
559 chapter 28 recommended soldering conditions user? manual u14046ej3v0ud table 28-1. surface mounting type soldering conditions (4/5) (4) 64-pin plastic lqfp (10 10) pd780021agb- -8eu, 780022agb- -8eu, 780023agb- -8eu, pd780024agb- -8eu, 780021aygb- -8eu, 780022aygb- -8eu, pd780023aygb- -8eu, 780024aygb- -8eu, 780031agb- -8eu, pd780032agb- -8eu, 780033agb- -8eu, 780034agb- -8eu, pd780031aygb- -8eu, 780032aygb- -8eu, 780033aygb- -8eu, pd780034aygb- -8eu soldering method soldering conditions recommended condition symbol infrared reflow package peak temperature: 235 c, time: 30 seconds max. ir35-00-2 (at 210 c or higher), count: two times or less vps package peak temperature: 215 c, time: 40 seconds max. vp15-00-2 (at 200 c or higher), count: two times or less partial heating pin temperature: 300 c max., time: 3 seconds max. (per pin row) ? caution do not use different soldering methods together (except for partial heating). (5) 64-pin plastic lqfp (10 10) pd78f0034agb-8eu, 78f0034aygb-8eu, 78f0034bgb-8eu, 78f0034bygb-8eu, pd78f0034bgb(a)-8eu, 78f0034bygb(a)-8eu soldering method soldering conditions recommended condition symbol infrared reflow package peak temperature: 235 c, time: 30 seconds max. ir35-107-2 (at 210 c or higher), count: two times or less, exposure limit: 7 days note (after that prebake at 125 c for 10 hours) vps package peak temperature: 215 c, time: 40 seconds max. vp15-107-2 (at 200 c or higher), count: two times or less, exposure limit: 7 days note (after that, prebake at 125 c for 10 hours) partial heating pin temperature: 300 c max., time: 3 seconds max. (per pin row) ? note after opening the dry pack, store it at 25 c or less and 65% rh or less for the allowable storage period. caution do not use different soldering methods together (except for partial heating).
560 chapter 28 recommended soldering conditions user? manual u14046ej3v0ud table 28-1. surface mounting type soldering conditions (5/5) (6) 73-pin plastic fbga (9 9) pd780021af1- -cn3, 780022af1- -cn3, 780023af1- -cn3, pd780024af1- -cn3, 780021ayf1- -cn3, 780022ayf1- -cn3, pd780023ayf1- -cn3, 780024ayf1- -cn3, 780031af1- -cn3, pd780032af1- -cn3, 780033af1- -cn3, 780034af1- -cn3, pd780031ayf1- -cn3, 780032ayf1- -cn3, 780033ayf1- -cn3, pd780034af1- -cn3, 78f0034bf1-cn3, 78f0034byf1-cn3 soldering method soldering conditions recommended condition symbol infrared reflow package peak temperature: 260 c, time: 60 seconds max. ir60-203-3 (at 220 c or higher), count: three times or less, exposure limit: 3 days note (after that, prebake at 125 c for 20 hours) vps package peak temperature: 215 c, time: 40 seconds max. vp15-203-3 (at 200 c or higher), count: three times or less, exposure limit: 3 days note (after that, prebake at 125 c for 20 hours) note after opening the dry pack, store it at 25 c or less and 65% rh or less for the allowable storage period. caution do not use different soldering methods together. table 28-2. insertion type soldering conditions 64-pin plastic sdip (19.05 mm (750)) pd780021acw- , 780022acw- , 780023acw- , 780024acw- , pd780021aycw- , 780022aycw- , 780023aycw- , 780024aycw- , pd780031acw- , 780032acw- , 780033acw- , 780034acw- , pd780031aycw- , 780032aycw- , 780033aycw- , 780034aycw- , pd780021acw(a)- , 780022acw(a)- , 780023acw(a)- , 780024acw(a)- , pd780031acw(a)- , 780032acw(a)- , 780033acw(a)- , 780034acw(a)- , pd78f0034acw, 78f0034aycw soldering method soldering conditions wave soldering solder bath temperature: 260 c max., time: 10 seconds max. (only for pins) partial heating pin temperature: 300 c max., time: 3 seconds max. (per pin row) caution apply wave soldering only to the pins and be careful not to bring solder into direct contact with the package.
561 user? manual u14046ej3v0ud appendix a differences between pd78018f, 780024a, 780034a, and 780078 subseries tables a-1 and a-2 show the major differences between the pd78018f, 780024a, 780034a, and 780078 subseries. table a-1. major differences between pd78018f, 780024a, 780034a, and 780078 subseries (hardware) note maintenance product name item emi noise reduction internal i 2 c bus version (y subseries) flash memory version rom internal high-speed ram internal expansion ram minimum instruction execution time number of i/o ports timer a/d converter serial interface timer output package device file emulation board electrical specifications recommended soldering conditions pd78018f subseries note pd780024a, 780034a pd780078 subseries subseries not provided provided provided provided (multi-task supported) pd78f018f pd78f0034a, 78f0034b pd78f0078 8 kb to 60 kb 8 kb to 32 kb 48 kb, 60 kb 512, 1024 bytes 512, 1024 bytes 1024 bytes 512, 1024 bytes not provided 1024 bytes 0.4 s (10 mhz) 0.24 s (8.38 mhz), 0.16 s (12 mhz, expanded-specification products only) 53 51 52 16 bits: 1, 8 bits: 2, 16 bits: 1, 8 bits: 2, 16 bits: 2, 8 bits: 2, watch timer: 1, watch timer: 1, watch timer: 1, watchdog timer: 1 watchdog timer: 1 watchdog timer: 1 8 bits 8 8 bits 8 10 bits 8 ( pd780024a subseries) ?10 bits 8 ( pd780034a subseries) 3-wire/2-wire/sbi: 1, 3-wire: 2, uart: 1 3-wire: 1, uart: 1, 3-wire (automatic 3-wire/uart: 1 transmission/reception): 1 3-wire/2-wire/i 2 c: 1, 3-wire: 2, uart: 1, 3-wire: 1, uart: 1, 3-wire (automatic multi-master i 2 c: 1 3-wire/uart: 1, transmission/reception): 1 multi-master i 2 c: 1 3 (14-bit pwm output possible: 2) 3 (8-bit pwm output possible: 2) 4 (8-bit pwm output possible: 2) ? 64-pin sdip (19.05 mm (750)) ? 64-pin sdip (19.05 mm (750)) ?64-pin qfp (14 14) ?64-pin qfp (14 14) ?64-pin qfp (14 14) ?64-pin tqfp (12 12) ?64-pin lqfp (12 12) ?64-pin tqfp (12 12) ?64-pin lqfp (14 14) ?64-pin lqfp (14 14) ?64-pin lqfp (10 10) ?73-pin fbga (9 9) df78014 df780034 df780078 ie-78014-r-em-a, ie-780034-ns-em1 ie-780078-ns-em1 ie-78018-ns-em1 refer to the data sheet or user? manual (with electrical specifications) of each product. subseries without suffix y subseries with suffix y
562 appendix a differences between pd78018f, 780024a, 780034a, and 780078 subseries user? manual u14046ej3v0ud table a-2. major differences between pd78018f, 780024a, 780034a, and 780078 subseries (software) (1/2) notes 1. maintenance product 2. tcl0: timer clock select register 0 name item a/d converter 16-bit timer/event counter interval timer pwm output ppg output pulse width measurement external event counter square wave output count clock control register output control register compare/capture register prescaler mode register capture/compare control register interrupt pd78018f subseries note 1 pd780024a, 780034a pd780078 subseries subseries ? take the appropriate measures for the first a/d conversion result immediately after the a/d conversion operation is started (adcs0 is set to 1), such as discarding it, because it may not satisfy the rating. however, if a wait time of 14 s (min.) has been secured after adce0 was set to 1 before starting operation (adcs0 is set to 1), the first data can be used. 1 ch 1 ch 2 ch tm0 tm0 tm00 tm01 ?? ?? ?? ?? ?? ?? f x /2, f x /2 2 , f x /2 3 , ti0 f x , f x /2 2 , f x /2 6 , ti00 f x , f x /2 2 ,f x /2, f x /2 3 f x /2 6 , ti000 f x /2 9 , ti001 tmc0 tmc0 tmc00 tmc01 toc0 toc0 toc00 toc01 cr00, cr01 (capture only) cr00, cr01 cr000, cr010 cr001, cr011 tcl0 note 2 prm0 prm00 prm01 ? crc0 crc00 crc01 inttm0 inttm00, inttm01 inttm000, inttm001, inttm010 inttm011
563 appendix a differences between pd78018f, 780024a, 780034a, and 780078 subseries user? manual u14046ej3v0ud table a-2. major differences between pd78018f, 780024a, 780034a, and 780078 subseries (software) (2/2) note maintenance product name item 8-bit timer/event counter unit mode interval timer external event counter square wave output pwm output cascade connection mode interval timer external event counter square wave output count clock control register output control register clock select register interrupt pd78018f subseries note pd780024a, 780034a pd780078 subseries subseries 2 ch 2 ch tm1 tm2 tm50 tm51 ?? ?? ?? ?? ?? ?? ?? tmc1 tmc50 tmc51 toc1 tmc50 tmc51 tcl1 tcl50 tcl51 inttm1 inttm2 inttm50 inttm51 f x /2 2 , f x /2 3 , f x /2 4 , f x /2 5 , f x /2 6 , f x /2 7 , f x /2 8 , f x /2 9 , f x /2 10 ,f x 2 12 , ti1 f x /2 2 , f x /2 3 , f x /2 4 , f x /2 5 , f x /2 6 , f x /2 7 , f x /2 8 , f x /2 9 , f x /2 10 , f x /2 12 , ti2 f x , f x /2 2 , f x /2 4 , f x /2 6 , f x /2 8 , f x /2 10 , ti50 f x /2, f x /2 3 , f x /2 5 , f x /2 7 , f x /2 9 , f x /2 11 , ti51
564 user? manual u14046ej3v0ud appendix b development tools the following development tools are available for the development of systems that employ the pd780024a, 780034a, 780024ay, and 780034ay subseries. figure b-1 shows the development tool configuration. support for pc98-nx series unless otherwise specified, products compatible with ibm pc/at tm computers are compatible with pc98-nx series computers. when using pc98-nx series computers, refer to the explanation for ibm pc/at computers. windows unless otherwise specified, ?indows?means the following oss. windows 3.1 windows 95 windows 98 windows 2000 windows nt tm ver 4.0
565 appendix b development tools user? manual u14046ej3v0ud figure b-1. development tool configuration (1/2) (1) when using the in-circuit emulator ie-78k0-ns, ie-78k0-ns-a notes 1. the c library source file is not included in the software package. 2. the project manager is included in the assembler package. the project manager is only used for windows. language processing software ? assembler package ? c compiler package ? device file ? c library source file note 1 debugging software ? integrated debugger ? system simulator host machine (pc or ews) interface adapter, pc card interface, etc. in-circuit emulator emulation board emulation probe conversion socket or conversion adapter target system flash programmer flash memory write adapter flash memory ? software package ? project manager (windows only) note 2 software package flash memory write environment control software embedded software ? real-time os i/o board performance board power supply unit
566 appendix b development tools user s manual u14046ej3v0ud figure b-1. development tool configuration (2/2) (2) when using the in-circuit emulator ie-78001-r-a notes 1. the c library source file is not included in the software package. 2. the project manager is included in the assembler package. the project manager is only used for windows. language processing software ? assembler package ? c compiler package ? device file ? c library source file note 1 debugging software ? integrated debugger ? system simulator host machine (pc or ews) interface adapter, pc card interface, etc. in-circuit emulator emulation board emulation probe conversion socket or conversion adapter target system flash programmer flash memory write adapter flash memory ? software package ? project manager (windows only) note 2 software package flash memory write environment control software embedded software ? real-time os i/o board emulation probe conversion board performance board
567 appendix b development tools user s manual u14046ej3v0ud b.1 software package sp78k0 this package contains various software tools for 78k/0 series development. software package the following tools are included. ra78k0, cc78k0, id78k0-ns, sm78k0, and various device files part number: s sp78k0 remark in the part number differs depending on the os used. s sp78k0 host machine os supply medium ab17 pc-9800 series, windows (japanese version) cd-rom bb17 ibm pc/at compatibles windows (english version) b.2 language processing software ra78k0 assembler package cc78k0 c compiler package df780024 note 1 df780034 note 1 device file cc78k0-l note 2 c library source file this assembler converts programs written in mnemonics into object codes executable with a microcontroller. further, this assembler is provided with functions capable of automatically creating symbol tables and branch instruction optimization. this assembler should be used in combination with device file (df780024 or df780034) (sold separately). this assembler package is a dos-based application. it can also be used in windows, however, by using the project manager (included in the assembler package) on windows. part number: s ra78k0 this compiler converts programs written in c language into object codes executable with a microcontroller. this compiler should be used in combination with an assembler package and device file (both sold separately). this c compiler package is a dos-based application. it can also be used in windows, however, by using the project manager (included in the assembler package) on windows. part number: s cc78k0 this file contains information peculiar to the device. this device file should be used in combination with tool (ra78k0, cc78k0, sm78k0, id78k0-ns, and rx78k0) (all sold separately). the corresponding os and host machine differ depending on the tool used. ? df780024: pd780024a, 780024ay, 780024as subseries ? df780034: pd780034a, 780034ay, 780034as subseries part number: s df780024, s df780034 this is a source file of functions configuring the object library included in the c compiler package. this file is required to match the object library included in c compiler package to the user s specifications. it does not depend on the operating environment because it is a source file. part number: s cc78k0-l
568 appendix b development tools user s manual u14046ej3v0ud notes 1. the df780024 and df780034 can be used in common with the ra78k0, cc78k0, sm78k0, id78k0- ns, and rx78k0. 2. cc78k0-l is not included in the software package (sp78k0). remark in the part number differs depending on the host machine and os used. s ra78k0 s cc78k0 host machine os supply medium ab13 pc-9800 series, windows (japanese version) 3.5-inch 2hd fd bb13 ibm pc/at compatibles windows (english version) ab17 windows (japanese version) cd-rom bb17 windows (english version) 3p17 hp9000 series 700 tm hp-ux tm (rel. 10.10) 3k17 sparcstation tm sunos tm (rel. 4.1.4), solaris tm (rel. 2.5.1) s df780024 s df780034 s cc78k0-l host machine os supply medium ab13 pc-9800 series, windows (japanese version) 3.5-inch 2hd fd bb13 ibm pc/at compatibles windows (english version) 3p16 hp9000 series 700 hp-ux (rel. 10.10) dat 3k13 sparcstation sunos (rel. 4.1.4), 3.5-inch 2hd fd 3k15 solaris (rel. 2.5.1) 1/4-inch cgmt b.3 control software project manager this is control software designed to enable efficient user program development in the windows environment. all operations used in development of a user program, such as starting the editor, building, and starting the debugger, can be performed from the project manager. the project manager is included in the assembler package (ra78k0). it can only be used in windows.
569 appendix b development tools user s manual u14046ej3v0ud b.4 flash memory writing tools flashpro iii (part number: fl-pr3, pg-fp3) flashpro iv (part number: fl-pr4, pg-fp4) flash programmer fa-64cw fa-64gc-8bs-a fa-64gc fa-64gk-9et fa-64gb-8eu-a fa-73f1-cn3-a flash memory writing adapter remark fl-pr3, fl-pr4, fa-64cw, fa-64gc-8bs-a, fa-64gc, fa-64gk-9et, fa-64gb-8eu-a, and fa- 73f1-cn3-a are products of naito densei machida mfg. co., ltd. contact: +81-45-475-4191 naito densei machida mfg. co., ltd. b.5 debugging tools (hardware) b.5.1 when using the in-circuit emulator ie-78k0-ns, ie-78k0-ns-a (1/2) ie-78k0-ns in-circuit emulator ie-78k0-ns-pa performance board ie-78k0-ns-a in-circuit emulator ie-70000-mc-ps-b power supply unit ie-70000-98-if-c interface adapter ie-70000-cd-if-a pc card interface ie-70000-pc-if-c interface adapter ie-70000-pci-if-a interface adapter ie-780034-ns-em1 emulation board np-64cw np-h64cw emulation probe flash programmer dedicated to microcontrollers with on-chip flash memory. flash memory writing adapter used connected to the flashpro iii and flashpro iv. fa-64cw: 64-pin plastic sdip (cw type) fa-64gc-8bs-a: 64-pin plastic lqfp (gc-8bs type) fa-64gc: 64-pin plastic qfp (gc-ab8 type) fa-64gk-9et: 64-pin plastic tqfp (gk-9et type) fa-64gb-8eu-a: 64-pin plastic lqfp (gb-8eu type) fa-73f1-cn3-a: 73-pin plastic fbga (f1-cn3 type) the in-circuit emulator serves to debug hardware and software when developing application systems using a 78k/0 series product. it corresponds to the integrated debugger (id78k0-ns). this emulator should be used in combination with a power supply unit, emulation probe, and interface adapter which is required to connect this emulator to the host machine. this board is connected to the ie-78k0-ns to expand its functions. adding this board adds a coverage function and enhances debugging functions such as tracer and timer functions. a combination of the ie-78k0-ns and ie-78k0-ns-pa. this adapter is used for supplying power from a receptacle of 100 v to 240 v ac. this adapter is required when using a pc-9800 series computer (except notebook type) as the host machine (c bus compatible). this is pc card and interface cable required when using a notebook-type computer as the host machine (pcmcia socket compatible). this adapter is required when using an ibm pc/at compatible computer as the host machine (isa bus compatible). this adapter is required when using a computer with a pci bus as the host machine. this board emulates the operations of the peripheral hardware peculiar to a device. it should be used in combination with an in-circuit emulator. this probe is used to connect the in-circuit emulator to a target system and is designed for use with a 64-pin plastic sdip (cw type).
570 appendix b development tools user s manual u14046ej3v0ud (2/2) np-64gc emulation probe ev-9200gc-64 conversion socket (see figures b-2 and b-3 ) np-64gc-tq np-h64gc-tq emulation probe tgc-064sap conversion adapter (see figure b-4 ) np-64gk np-h64gk-tq emulation probe tgk-064sbw conversion adapter (see figure b-5 ) np-h64gb-tq emulation probe tgb-064sdp conversion adapter (see figure b-6 ) np-73f1-cn3 emulation probe csice73a0909n01, lspack73a0909n01, cssocket73a0909n01 conversion socket remarks 1. np-64cw, np-h64cw, np-64gc, np-64gc-tq, np-h64gc-tq, np-64gk, np-h64gk-tq, np- h64gb-tq, and np-73f1-cn3 are products of naito densei machida mfg. co., ltd. contact: +81-45-475-4191 naito densei machida mfg. co., ltd. 2. tgc-064sap, tgk-064sbw, tgb-064sdp, csice73a0909n01, lspack73a0909n01, and cssocket73a0909n01 are products of tokyo eletech corporation. contact: daimaru kogyo, ltd. phone: tokyo +81-3-3820-7112 electronics dept. osaka +81-6-6244-6672 electronics 2nd dept. 3. ev-9200gc-64 is sold in five-unit sets. 4. tgk-064sbw and tgc-064sap are sold in single units. 5. the emulation probe (np-73f1-cn3) is supplied with a conversion socket (csice73a0909n01, lspack73a0909n01, cssocket73a0909n01). this probe is used to connect the in-circuit emulator to a target system and is designed for use with a 64-pin plastic qfp (gc-ab8 type) and 64-pin plastic lqfp (gc-8bs type). this conversion socket connects the np-64gc to a target system board designed for a 64-pin plastic qfp (gc-ab8 type) and 64-pin plastic lqfp (gc-8bs type). this probe is used to connect the in-circuit emulator to a target system and is designed for use with a 64-pin plastic qfp (gc-ab8 type) and 64-pin plastic lqfp (gc-8bs type). this conversion adapter connects the np-64gc-tq or np-h64gc-tq to a target system board designed for a 64-pin plastic qfp (gc-ab8 type) and 64-pin plastic lqfp (gc-8bs type). this probe is used to connect the in-circuit emulator to a target system and is designed for use with a 64-pin plastic tqfp (gk-9et type). this conversion adapter connects the np-64gk or np-h64gk-tq to a target system board designed for a 64-pin plastic tqfp (gk-9et type). this probe is used to connect the in-circuit emulator to a target system and is designed for use with a 64-pin plastic lqfp (gb-8eu type). this conversion adapter connects the np-h64gb-tq to a target system board designed for a 64-pin plastic lqfp (gb-8eu type). this probe is used to connect the in-circuit emulator to a target system and is designed for use with a 73-pin plastic fbga (f1-cn3 type). this conversion socket connects the np-73f1-cn3 to a target system board designed for a 73-pin plastic fbga (f1-cn3 type). ? csice73a0909n01: yqsocket/lspack conversion adapter ? lspack73a0909n01: socket for target connection ? cssocket73a0909n01: socket for emulator connection
571 appendix b development tools user s manual u14046ej3v0ud b.5.2 when using the in-circuit emulator ie-78001-r-a ie-78001-r-a in-circuit emulator ie-70000-98-if-c interface adapter ie-70000-pc-if-c interface adapter ie-70000-pci-if-a interface adapter ie-780034-ns-em1 emulation board ie-78k0-r-ex1 emulation probe conversion board ep-78240cw-r note emulation probe ep-78240gc-r note emulation probe ev-9200gc-64 conversion socket (see figures b-2 and b-3 ) ep-78012gk-r emulation probe tgk-064sbw conversion adapter (see figure b-5 ) note maintenance product caution the ie-78001-r-a is not supported for the 64-pin plastic lqfp (gb-8eu type) and 73-pin plastic fbga (f1-cn3 type). remarks 1. tgk-064sbw is a product of tokyo eletech corporation. contact: daimaru kogyo, ltd. phone: tokyo +81-3-3820-7112 electronics dept. osaka +81-6-6244-6672 electronics 2nd dept. 2. ev-9200gc-64 is sold in five-unit sets. 3. tgk-064sbw is sold in single units. the in-circuit emulator serves to debug hardware and software when developing application systems using a 78k/0 series product. it corresponds to the integrated debugger (id78k0). this emulator should be used in combination with an emulation probe and interface adapter, which is required to connect this emulator to the host machine. this adapter is required when using a pc-9800 series computer (except notebook type) as the host machine (c bus compatible). this adapter is required when using an ibm pc/at compatible computer as the host machine (isa bus compatible). this adapter is required when using a computer with a pci bus as the host machine. this board emulates the operations of the peripheral hardware peculiar to a device. it should be used in combination with an in-circuit emulator and emulation probe conversion board. this board is required when using the ie-780034-ns-em1 on the ie-78001-r-a. this probe is used to connect the in-circuit emulator to a target system and is designed for use with a 64-pin plastic sdip (cw type). this probe is used to connect the in-circuit emulator to a target system and is designed for use with a 64-pin plastic qfp (gc-ab8 type) and 64-pin plastic lqfp (gc-8bs type). this conversion socket connects the ep-78240gc-r to a target system board designed for a 64-pin plastic qfp (gc-ab8 type) and 64-pin plastic lqfp (gc-8bs type). this probe is used to connect the in-circuit emulator to a target system and is designed for use with a 64-pin plastic tqfp (gk-9et type). this conversion adapter connects the ep-78012gk-r to a target system board designed for a 64-pin plastic tqfp (gk-9et type).
572 appendix b development tools user s manual u14046ej3v0ud b.6 debugging tools (software) sm78k0 this is a system simulator for the 78k/0 series. the sm78k0 is windows-based system simulator software. it is used to perform debugging at the c source level or assembler level while simulating the operation of the target system on a host machine. use of the sm78k0 allows the execution of application logical testing and performance testing on an independent basis from hardware development, thereby providing higher development efficiency and software quality. the sm78k0 should be used in combination with the device file (df780024 or df780034) (sold separately). part number: s sm78k0 id78k0-ns this debugger supports the in-circuit emulators for the 78k/0 series. the integrated debugger id78k0-ns is windows-based software. (supporting in-circuit emulators it has improved c-compatible debugging functions and can display the results of ie-78k0-ns and ie-78k0-ns-a) tracing with the source program using an integrating window function that associates id78k0 the source program, disassemble display, and memory display with the trace result. integrated debugger it should be used in combination with the device file (sold separately). (supporting in-circuit emulator ie-78001-r-a) part number: s id78k0-ns, s id78k0 remark in the part number differs depending on the host machine and os used. s sm78k0 s id78k0-ns s id78k0 host machine os supply medium ab13 ibm pc/at compatibles windows (japanese version) 3.5-inch 2hd fd bb13 windows (english version) ab17 windows (japanese version) cd-rom bb17 windows (english version)
573 appendix b development tools user s manual u14046ej3v0ud b.7 embedded software rx78k0 rx78k0 is a real-time os conforming to the itron specifications. real-time os a tool (configurator) for generating the nucleus of rx78k0 and multiple information tables is supplied. it is used in combination with an assembler package (ra78k0) and device file (df780024 or df780034) (both sold separately). the real-time os is a dos-based application. it should be used from the dos prompt when using in windows. part number: s rx78013- ???? caution when purchasing the rx78k0, fill in the purchase application form in advance and sign the user agreement. remark and ???? in the part number differ depending on the host machine and os used. s rx78013- ???? ???? product outline maximum number for use in mass production 001 evaluation object do not use for mass-produced product. 100k mass-production object 0.1 million units 001m 1 million units 010m 10 million units s01 source program source program for mass-produced object host machine os supply medium aa13 pc-9800 series windows (japanese version) 3.5-inch 2hd fd ab13 ibm pc/at compatibles windows (japanese version) bb13 windows (english version)
574 appendix b development tools user s manual u14046ej3v0ud b.8 system upgrade from former in-circuit emulator for 78k/0 series to ie-78001-r-a if you already have a former in-circuit emulator for 78k/0 series microcontrollers (ie-78000-r or ie-78000-r-a), that in-circuit emulator can operate as an equivalent to the ie-78001-r-a by replacing its internal break board with the ie-78001-r-bk. table b-1. system upgrade method from former in-circuit emulator for 78k/0 series to ie-78001-r-a in-circuit emulator owned in-circuit emulator cabinet upgrade note board to be purchased ie-78000-r required ie-78001-r-bk ie-78000-r-a not required note for upgrading of a cabinet, send your in-circuit emulator to nec electronics.
575 appendix b development tools user s manual u14046ej3v0ud b.9 package drawings of conversion socket and conversion adapter figure b-2. ev-9200gc-64 package drawing (for reference only) a f 1 e ev-9200gc-64 b d c m n l k r q i h p o s t j g no.1 pin index ev-9200gc-64-g0 item millimeters inches a b c d e f g h i j k l m n o p q r s t 18.8 14.1 14.1 18.8 4-c 3.0 0.8 6.0 15.8 18.5 6.0 15.8 18.5 8.0 7.8 2.5 2.0 1.35 0.35 0.1 2.3 1.5 0.74 0.555 0.555 0.74 4-c 0.118 0.031 0.236 0.622 0.728 0.236 0.622 0.728 0.315 0.307 0.098 0.079 0.053 0.014 0.091 0.059 +0.004 0.005
576 appendix b development tools user s manual u14046ej3v0ud figure b-3. ev-9200gc-64 recommended board mounting pattern (for reference only) f e d g h i j k l c b a 0.031 0.591=0.472 0.031 0.591=0.472 ev-9200gc-64-p1e item millimeters inches a b c d e f g h i j k l 19.5 14.8 14.8 19.5 6.00 0.08 6.00 0.08 0.5 0.02 2.36 0.03 2.2 0.1 1.57 0.03 0.768 0.583 0.583 0.768 0.236 0.236 0.197 0.093 0.087 0.062 0.8 0.02 15=12.0 0.05 0.8 0.02 15=12.0 0.05 +0.002 0.001 +0.003 0.002 +0.002 0.001 +0.003 0.002 +0.004 0.003 +0.004 0.003 +0.001 0.002 +0.001 0.002 +0.004 0.005 +0.001 0.002 dimensions of mount pad for ev-9200 and that for target device (qfp) may be different in some parts. for the recommended mount pad dimensions for qfp, refer to "semiconductor device mount manual" website (http://www.necel.com/pkg/en/mount/index.html). caution
577 appendix b development tools user s manual u14046ej3v0ud figure b-4. tgc-064sap package drawing (for reference only) item millimeters inches b 3.5 0.138 c 2.0 0.079 a 1.85 0.073 d 6.0 0.236 e 0.25 0.010 f 13.6 g 1.2 0.047 0.535 item millimeters inches b 0.8x15=12.0 0.031x0.591=0.472 c 0.8 0.031 a 14.12 0.556 d h 17.2 0.677 i c 2.0 c 0.079 j 9.05 0.356 e 10.0 0.394 f 12.4 0.488 k 5.0 0.197 l 13.35 0.526 m q 12.5 0.492 r 17.5 0.689 s n 1.325 0.052 o 16.0 p 20.65 0.813 4- 1.3 4- 0.051 0.630 w x (19.65) (0.667) y 7.35 0.289 t u v z 1.2 0.047 20.65 1.325 0.813 0.052 g 14.8 0.583 v c i j i a eg h f b c w note : product by tokyo eletech corporation. z mn ? 1.8 0.071 3.55 0.140 ? 0.9 0.035 ? 0.3 0.012 ? h 1.2 0.047 i 2.4 j 2.7 0.106 0.094 tgc-064sap-g0e protrusion height a b u g h q r f e d l o k t s j p x y d
578 appendix b development tools user s manual u14046ej3v0ud figure b-5. tgk-064sbw package drawing (for reference only) item millimeters inches b 1.85 0.073 c 3.5 0.138 a 0.3 0.012 d 2.0 0.079 h 5.9 0.232 i 0.8 0.031 j 2.4 0.094 e 3.9 0.154 f 1.325 g 1.325 0.052 0.052 item millimeters inches b 0.65x15=9.75 0.026x0.591=0.384 c 0.65 0.026 a 18.4 0.724 d h 0.65x15=9.75 0.026x0.591=0.384 i 11.85 0.467 j 18.4 0.724 e 10.15 0.400 f 12.55 0.494 k c 2.0 c 0.079 l 12.45 0.490 m q 11.1 0.437 r 1.45 0.057 s 1.45 0.057 n 7.7 0.303 o 10.02 p 14.92 0.587 0.394 w 5.3 0.209 x 4-c 1.0 4-c 0.039 y 3.55 0.140 t 4- 1.3 4- 0.051 u 1.8 v 5.0 0.197 0.071 z 0.9 0.035 7.75 10.25 0.305 0.404 g 14.95 0.589 k 2.7 0.106 tgk-064sbw-g1e ? h a h a g z c l q n b c i j k g f e d m x r s w o p protrusion height u t v k j i y e d b f note : product by tokyo eletech corporation.
579 appendix b development tools user s manual u14046ej3v0ud figure b-6. tgb-064sdp package drawing (for reference only) (1/2) tgb-064sdp-g1e-1 item millimeters inches a b c e f g h i 14.0 0.5 15=7.5 8.04 10.44 12.84 9.24 10.1 9.77 m 8.0 5.64 n 0.551 0.364 0.222 0.317 0.411 0.506 0.385 0.398 0.315 0.020 0.591=0.295 8.99 o 12.0 p 0.354 0.472 1.505 q 0.059 1.505 r 6.75 s 0.059 0.266 12.9 t 5.0 u 0.508 0.197 1.8 v 0.25 w 0.071 0.010 1.85 x 0.073 3.5 y 2.0 z 0.138 0.079 d 0.5 0.020 j k l c 1.0 4.3 4- 0.7 c 0.039 0.169 4- 0.028 item millimeters inches a 2.6 0.102 ? b 0.25 0.010 c 9.24 0.364 d 1.38 0.054 e 1.38 0.054 a b c j k e f g h i w l b d c e z y x a m n u s t protrusion height v o p qr note : product by tokyo eletech corporation d
580 appendix b development tools user s manual u14046ej3v0ud figure b-6. tgb-064sdp package drawing (for reference only) (2/2) tgb-064sdp-g1e-2 item millimeters inches a b c e f g h i 16.0 0.5 10.44 12.84 9.77 0.5 15=7.5 0.8 c 2.0 m 3.5 8.04 n 0.630 0.020 0.591=0.295 0.317 0.411 0.506 0.385 c 0.079 0.031 0.138 0.020 0.3 o 0.9 p 0.012 0.035 13.6 q 0.535 6.0 r 1.0 s 0.236 0.039 4.2 t 0.2 u 0.165 0.008 4.0 v 0.7 w 0.157 0.028 1.03 x 0.041 1.1 y 0.7 z 0.043 0.028 d 5.64 0.222 j k l 5.9 2.7 2.4 0.232 0.106 0.094 item millimeters inches a 1.4 0.055 ? ? m a b c i d e f g h j k l o x w n v p r q s t u yza note : product by tokyo eletech corporation
581 user? manual u14046ej3v0ud appendix c notes on target system design the following shows a diagram of the connection conditions between the emulation probe and conversion adapter. design your system making allowances for conditions such as the shape of parts mounted on the target system, as shown below. of the products described in this chapter, all the emulation probes are products of naito densei machida mfg. co., ltd., and all the conversion adapters are products of tokyo eletech corporation. table c-1. distance between ie system and conversion adapter emulation probe conversion adapter distance between ie system and conversion adapter np-64cw ? 170 mm np-h64cw 370 mm np-64gc-tq tgc-064sap 155 mm np-h64gc-tq 355 mm np-64gk tgk-064sbw 155 mm np-h64gk-tq 355 mm np-64gb-tq tgb-064sdp 155 mm np-h64gb-tq 355 mm np-73f1-cn3 csice73a0909n01, lspack73a0909n01, cssocket73a0909n01 213 mm
582 appendix c notes on target system design user? manual u14046ej3v0ud figure c-1. distance between in-circuit emulator and conversion adapter (when using 64cw) 170 mm note in-circuit emulator ie-78k0-ns or ie-78k0-ns-a emulation board ie-780034-ns-em1 target system cn5 ic socket emulation probe np-64cw, np-h64cw note distance when using np-64cw. this is 370 mm when using np-h64cw. figure c-2. connection conditions of target system (when using np-64cw) 20 mm 14 mm 8 mm 24 mm 8 mm 13 mm target system 13 mm 34 mm emulation probe np-64cw emulation board ie-780034-ns-em1
583 appendix c notes on target system design user s manual u14046ej3v0ud figure c-3. connection conditions of target system (when using np-h64cw) emulation probe np-h64cw 42 mm 19 mm 60 mm 23 mm 45 mm emulation board ie-780034-ns-em1 target system
584 appendix c notes on target system design user s manual u14046ej3v0ud figure c-4. distance between in-circuit emulator and conversion adapter (when using 64gc) 155 mm note in-circuit emulator ie-78k0-ns or ie-78k0-ns-a emulation board ie-780034-ns-em1 conversion adapter: tgc-064sap target system emulation probe np-64gc-tq, np-h64gc-tq cn6 note distance when using np-64gc-tq. this is 355 mm when using np-h64gc-tq. figure c-5. connection conditions of target system (when using np-64gc-tq) emulation probe np-64gc-tq emulation board ie-780034-ns-em1 23 mm 25 mm 40 mm 34 mm target system conversion adapter tgc-064sap 20.65 mm pin 1 11 mm 20.65 mm
585 appendix c notes on target system design user s manual u14046ej3v0ud figure c-6. connection conditions of target system (when using np-h64gc-tq) emulation probe np-h64gc-tq emulation board ie-780034-ns-em1 23 mm 23 mm 42 mm 45 mm target system conversion adapter: tgc-064sap 20.65 mm pin 1 11 mm 20.65 mm
586 appendix c notes on target system design user s manual u14046ej3v0ud figure c-7. distance between in-circuit emulator and conversion adapter (when using 64gk) 155 mm note in-circuit emulator ie-78k0-ns or ie-78k0-ns-a emulation board ie-780034-ns-em1 conversion adapter: tgk-064sbw target system emulation probe np-64gk, np-h64gk-tq cn6 note distance when using np-64gk. this is 355 mm when using np-h64gk-tq. figure c-8. connection conditions of target system (when using np-64gk) emulation probe np-64gk emulation board ie-780034-ns-em1 21.95 mm 40 mm 34 mm target system conversion adapter tgk-064sbw 18.4 mm pin 1 11 mm 25 mm 18.4 mm
587 appendix c notes on target system design user s manual u14046ej3v0ud figure c-9. connection conditions of target system (when using np-h64gk-tq) emulation probe np-h64gk-tq emulation board ie-780034-ns-em1 42 mm 45 mm 18.4 mm 11 mm target system conversion adapter tgk-064sbw 18.4 mm pin 1 21.95 mm 23 mm
588 appendix c notes on target system design user s manual u14046ej3v0ud figure c-10. distance between in-circuit emulator and conversion adapter (when using 64gb) 155 mm note in-circuit emulator ie-78k0-ns or ie-78k0-ns-a emulation board ie-780034-ns-em1 conversion adapter: tgb-064sdp target system emulation probe np-64gb-tq, np-h64gb-tq cn6 note distance when using np-64gb-tq. this is 355 mm when using np-h64gb-tq. figure c-11. connection conditions of target system (when using np-64gb-tq) emulation probe np-64gb-tq emulation board ie-780034-ns-em1 22 mm 40 mm 34 mm target system conversion adapter tgb-064sdp 16 mm pin 1 11 mm 16 mm
589 appendix c notes on target system design user s manual u14046ej3v0ud figure c-12. connection conditions of target system (when using np-h64gb-tq) emulation probe np-h64gb-tq emulation board ie-780034-ns-em1 21.4 mm 42.6 mm 45 mm 16 mm target system conversion adapter tgb-064sdp 16 mm pin 1 11 mm
590 appendix c notes on target system design user s manual u14046ej3v0ud figure c-13. distance between in-circuit emulator and conversion socket (when using np-73f1-cn3) figure c-14. connection conditions of target system (when using np-73f1-cn3) 213 mm in-circuit emulator ie-78k0-ns or ie-78k0-ns-a emulation board ie-780034-ns-em1 conversion socket: csice73a0909n01, lspack73a0909n01, cssocket73a0909n01 target system cn6 emulation probe np-73f1-cn3 emulation probe np-73f1-cn3 21 mm 27 mm 23 mm 23 mm 33 mm 20 mm emulation board ie-780034-ns-em1 conversion socket csice73a0909n01, lspack73a0909n01, cssocket73a0909n01 target system
591 user? manual u14046ej3v0ud appendix d register index d.1 register name index [a] a/d conversion result register 0 (adcr0) ...................................................................................................... 259, 281 a/d converter mode register 0 (adm0) .......................................................................................................... 261, 283 analog input channel specification register 0 (ads0) ................................................................................... 263, 285 asynchronous serial interface mode register 0 (asim0) ........................................................................................ 305 asynchronous serial interface status register 0 (asis0) ........................................................................................ 304 [b] baud rate generator control register 0 (brgc0) .................................................................................................... 307 [c] capture/compare control register 0 (crc0) ............................................................................................................ 190 clock output select register (cks) ........................................................................................................................... 253 [e] 8-bit timer compare register 50 (cr50) ................................................................................................................... 221 8-bit timer compare register 51 (cr51) ................................................................................................................... 221 8-bit timer counter 50 (tm50) ............................................................................................................................... ... 221 8-bit timer counter 51 (tm51) ............................................................................................................................... ... 221 8-bit timer mode control register 50 (tmc50) ......................................................................................................... 223 8-bit timer mode control register 51 (tmc51) ......................................................................................................... 223 external interrupt falling edge enable register (egn) ............................................................................................. 410 external interrupt rising edge enable register (egp) .............................................................................................. 410 [i] iic control register 0 (iicc0) ............................................................................................................................... ..... 345 iic shift register 0 (iic0) ............................................................................................................................... ............ 343 iic status register 0 (iics0) ............................................................................................................................... ...... 350 iic transfer clock select register 0 (iiccl0) ............................................................................................................ 353 interrupt mask flag register 0h (mk0h) ................................................................................................................... 408 interrupt mask flag register 0l (mk0l) .................................................................................................................... 408 interrupt mask flag register 1l (mk1l) .................................................................................................................... 408 interrupt request flag register 0h (if0h) ................................................................................................................. 407 interrupt request flag register 0l (if0l) ................................................................................................................... 407 interrupt request flag register 1l (if1l) ................................................................................................................... 407 [m] memory expansion mode register (mem) ................................................................................................................ 425 memory expansion wait setting register (mm) ........................................................................................................ 426 memory size switching register (ims) ...................................................................................................................... 450 [o] oscillation stabilization time select register (osts) ...................................................................................... 174, 434
592 appendix d register index user? manual u14046ej3v0ud [p] port 0 (p0) ............................................................................................................................... .................................. 139 port 1 (p1) ............................................................................................................................... .................................. 141 port 2 (p2) ............................................................................................................................... .................................. 142 port 3 (p3) ............................................................................................................................... ......................... 145, 150 port 4 (p4) ............................................................................................................................... .................................. 154 port 5 (p5) ............................................................................................................................... .................................. 155 port 6 (p6) ............................................................................................................................... .................................. 156 port 7 (p7) ............................................................................................................................... .................................. 158 port mode register 0 (pm0) ............................................................................................................................... ....... 161 port mode register 2 (pm2) .................................................................................................................... 161, 309, 334 port mode register 3 (pm3) .................................................................................................................... 161, 334, 354 port mode register 4 (pm4) ............................................................................................................................... ....... 161 port mode register 5 (pm5) ............................................................................................................................... ....... 161 port mode register 6 (pm6) ............................................................................................................................... ....... 161 port mode register 7 (pm7) ............................................................................................................ 161, 193, 226, 255 prescaler mode register 0 (prm0) .......................................................................................................................... 192 priority specification flag register 0h (pr0h) .......................................................................................................... 409 priority specification flag register 0l (pr0l) ........................................................................................................... 409 priority specification flag register 1l (pr1l) ........................................................................................................... 409 processor clock control register (pcc) ................................................................................................................... 171 program status word (psw) ............................................................................................................................ 114 , 411 pull-up resistor option register 0 (pu0) ................................................................................................................... 165 pull-up resistor option register 2 (pu2) ................................................................................................................... 165 pull-up resistor option register 3 (pu3) ................................................................................................................... 165 pull-up resistor option register 4 (pu4) ................................................................................................................... 165 pull-up resistor option register 5 (pu5) ................................................................................................................... 165 pull-up resistor option register 6 (pu6) ................................................................................................................... 165 pull-up resistor option register 7 (pu7) ................................................................................................................... 165 [r] receive buffer register 0 (rxb0) ............................................................................................................................. 30 3 receive shift register 0 (rx0) ............................................................................................................................... ... 303 [s] serial i/o shift register 30 (sio30) .......................................................................................................................... 330 serial i/o shift register 31 (sio31) .......................................................................................................................... 330 serial operation mode register 30 (csim30) ........................................................................................................... 331 serial operation mode register 31 (csim31) ........................................................................................................... 331 16-bit timer capture/compare register 00 (cr00) ................................................................................................... 186 16-bit timer capture/compare register 01 (cr01) ................................................................................................... 187 16-bit timer counter 0 (tm0) ............................................................................................................................... ...... 186 16-bit timer mode control register 0 (tmc0) ........................................................................................................... 188 16-bit timer output control register 0 (toc0) .......................................................................................................... 191 slave address register 0 (sva0) .............................................................................................................................. 3 43
593 appendix d register index user? manual u14046ej3v0ud [t] timer clock select register 50 (tcl50) ................................................................................................................... 222 timer clock select register 51 (tcl51) ................................................................................................................... 222 transmit shift register 0 (txs0) ............................................................................................................................... 303 [w] watch timer operation mode register (wtm) .......................................................................................................... 243 watchdog timer clock select register (wdcs) ........................................................................................................ 248 watchdog timer mode register (wdtm) .................................................................................................................. 249
594 appendix d register index user? manual u14046ej3v0ud d.2 register symbol index [a] adcr0: a/d conversion result register 0 ................................................................................................ 259, 281 adm0: a/d converter mode register 0 .................................................................................................. 261, 283 ads0: analog input channel specification register 0 ........................................................................... 263, 285 asim0: asynchronous serial interface mode register 0 ................................................................................. 305 asis0: asynchronous serial interface status register 0 ................................................................................. 304 [b] brgc0: baud rate generator control register 0 ............................................................................................... 307 [c] cks: clock output select register ................................................................................................................ 253 cr00: 16-bit timer capture/compare register 00 ........................................................................................... 186 cr01: 16-bit timer capture/compare register 01 ........................................................................................... 187 cr50: 8-bit timer compare register 50 .......................................................................................................... 221 cr51: 8-bit timer compare register 51 .......................................................................................................... 221 crc0: capture/compare control register 0 .................................................................................................... 190 csim30: serial operation mode register 30 ...................................................................................................... 331 csim31: serial operation mode register 31 ...................................................................................................... 331 [e] egn: external interrupt falling edge enable register ................................................................................... 410 egp: external interrupt rising edge enable register .................................................................................... 410 [i] if0h: interrupt request flag register 0h ....................................................................................................... 407 if0l: interrupt request flag register 0l ........................................................................................................ 407 if1l: interrupt request flag register 1l ........................................................................................................ 407 iic0: iic shift register 0 ............................................................................................................................... . 343 iicc0: iic control register 0 ............................................................................................................................ 345 iiccl0: iic transfer clock select register 0 ...................................................................................................... 353 iics0: iic status register 0 ............................................................................................................................. 35 0 ims: memory size switching register .......................................................................................................... 450 [m] mem: memory expansion mode register ...................................................................................................... 425 mk0h: interrupt mask flag register 0h ........................................................................................................... 408 mk0l: interrupt mask flag register 0l ............................................................................................................ 408 mk1l: interrupt mask flag register 1l ............................................................................................................ 408 mm: memory expansion wait setting register ............................................................................................. 426 [o] osts: oscillation stabilization time select register .............................................................................. 174, 434
595 appendix d register index user? manual u14046ej3v0ud [p] p0: port 0 ............................................................................................................................... ..................... 139 p1: port 1 ............................................................................................................................... ..................... 141 p2: port 2 ............................................................................................................................... ..................... 142 p3: port 3 ............................................................................................................................... ............ 145, 150 p4: port 4 ............................................................................................................................... ..................... 154 p5: port 5 ............................................................................................................................... ..................... 155 p6: port 6 ............................................................................................................................... ..................... 156 p7: port 7 ............................................................................................................................... ..................... 158 pcc: processor clock control register ......................................................................................................... 171 pm0: port mode register 0 ........................................................................................................................... 161 pm2: port mode register 2 ......................................................................................................... 161, 309, 334 pm3: port mode register 3 ......................................................................................................... 161, 334, 354 pm4: port mode register 4 ........................................................................................................................... 161 pm5: port mode register 5 ........................................................................................................................... 161 pm6: port mode register 6 ........................................................................................................................... 161 pm7: port mode register 7 ................................................................................................. 161, 193, 226, 255 pr0h: priority specification flag register 0h .................................................................................................. 409 pr0l: priority specification flag register 0l .................................................................................................. 409 pr1l: priority specification flag register 1l .................................................................................................. 409 prm0: prescaler mode register 0 ................................................................................................................... 192 psw: program status word .................................................................................................................. 114, 411 pu0: pull-up resistor option register 0 ........................................................................................................ 165 pu2: pull-up resistor option register 2 ........................................................................................................ 165 pu3: pull-up resistor option register 3 ........................................................................................................ 165 pu4: pull-up resistor option register 4 ........................................................................................................ 165 pu5: pull-up resistor option register 5 ........................................................................................................ 165 pu6: pull-up resistor option register 6 ........................................................................................................ 165 pu7: pull-up resistor option register 7 ........................................................................................................ 165 [r] rx0: receive shift register 0 ....................................................................................................................... 303 rxb0: receive buffer register 0 ..................................................................................................................... 303 [s] sio30: serial i/o shift register 30 ................................................................................................................... 330 sio31: serial i/o shift register 31 ................................................................................................................... 330 sva0: slave address register 0 ..................................................................................................................... 343 [t] tcl50: timer clock select register 50 ............................................................................................................. 222 tcl51: timer clock select register 51 ............................................................................................................. 222 tm0: 16-bit timer counter 0 .......................................................................................................................... 186 tm50: 8-bit timer counter 50 .......................................................................................................................... 221 tm51: 8-bit timer counter 51 .......................................................................................................................... 221 tmc0: 16-bit timer mode control register 0 ................................................................................................... 188 tmc50: 8-bit timer mode control register 50 ................................................................................................... 223 tmc51: 8-bit timer mode control register 51 ................................................................................................... 223
596 appendix d register index user? manual u14046ej3v0ud toc0: 16-bit timer output control register 0 .................................................................................................. 191 txs0: transmit shift register 0 ...................................................................................................................... 303 [w] wdcs: watchdog timer clock select register ................................................................................................. 248 wdtm: watchdog timer mode register ........................................................................................................... 249 wtm: watch timer operation mode register ................................................................................................. 243
597 user? manual u14046ej3v0ud appendix e revision history the revision history for this manual is detailed below. ?hapter?indicates the chapter of each edition. (1/5) edition revision from previous edition chapter second deletion of the following products throughout edition ? pd780021ay(a), 780022ay(a), 780023ay(a), 780024ay(a), 780031ay(a), 780032ay(a), 780033ay(a), 780034ay(a) deletion of the following package ?64-pin plastic lqfp (gk-8a8 type) addition of the following packages ?64-pin plastic tqfp (gk-9et type) ?64-pin plastic lqfp (gb-8eu type) modification of recommended connection of unused pins in chapter 3 pin function table 3-1 pin i/o circuit types ( pd780024a, 780034a subseries) modification of recommended connection of unused pins in chapter 4 pin function table 4-1 pin i/o circuit types ( pd780024ay, 780034ay subseries) modification of figure 6-2 p00 to p03 block diagram chapter 6 port functions modification of figure 6-4 p20, p22, p23, p25 block diagram modification of figure 6-7 p34 and p36 block diagram ( pd780024a, 780034a subseries) modification of figure 6-8 p35 block diagram ( pd780024a, 780034a subseries) modification of figure 6-10 p32 and p33 block diagram ( pd780024ay, 780034ay subseries) modification of figure 6-12 p40 to p47 block diagram modification of figure 6-14 p50 to p57 block diagram modification of figure 6-15 p64 to p67 block diagram modification of figure 6-16 p70 to p73 block diagram modification of figure 6-17 p74 and p75 block diagram addition of note for feedback resistor in figure 7-3 processor chapter 7 clock generator clock control register (pcc) format deletion of one-shot pulse output function chapter 8 16-bit timer/event counter 0 addition of caution for intwt in figure 10-3 operation timing of chapter 10 watch timer watch timer/interval timer addition of 13.5 how to read a/d converter characteristics table chapter 13 8-bit a/d converter 13.6 a/d converter cautions ( pd780024a, 780024ay subseries) addition of (10) timing at which a/d conversion result is undefined addition of (11) notes on board design addition of (13) av ref pin addition of (14) internal equivalent circuit of ani0 to ani7 pins and permissible signal source impedance addition of 14.5 how to read a/d converter characteristics table chapter 14 10-bit a/d converter 14.6 a/d converter cautions ( pd780034a, 780034ay subseries) addition of (10) timing at which a/d conversion result is undefined addition of (11) notes on board design addition of (13) av ref pin addition of (14) internal equivalent circuit of ani0 to ani7 pins and permissible signal source impedance
598 appendix e revision history user? manual u14046ej3v0ud (2/5) edition revision from previous edition chapter second modification of figure 18-3 iic control register 0 (iicc0) format chapter 18 serial interface edition (iic0) ( pd780024ay, 780034ay subseries only) deletion of flashpro ii chapter 23 pd78f0034a, 78f0034ay revision of development tools appendix b development tools third addition of the following products throughout edition pd780021ay(a), 780022ay(a), 780023ay(a), 780024ay(a), pd780031ay(a), 780032ay(a), 780033ay(a), 780034ay(a), pd78f0034b, 78f0034b(a), 78f0034by, 78f0034by(a) addition of the following packages ? 64-pin plastic lqfp (gc-8bs type) ? 73-pin plastic fbga (f1-cn3 type) addition of expanded-specification products to pd780024a, 780034a subseries addition of 1.1 expanded-specification products and chapter 1 outline ( pd780024a, conventional products 780034a subseries) addition of 1.10 correspondence between mask rom versions and flash memory versions modification of 1.11 differences between standard grade products and special grade products addition of 1.12 correspondence between products and packages addition of 2.9 correspondence between mask rom versions chapter 2 outline ( pd780024ay, and flash memory versions 780034ay subseries) modification of 2.10 differences between standard grade products and special grade products addition of 2.11 correspondence between products and packages addition of description of pin processing in 3.2.18 v pp (flash chapter 3 pin function memory versions only) ( pd780024a, 780034a subseries) modification of table 3-1 pin i/o circuit types addition of description of pin processing in 4.2.18 v pp (flash chapter 4 pin function memory versions only) ( pd780024ay, 780034ay subseries) modification of table 4-1 pin i/o circuit types addition of description of program area in 5.1.2 internal data chapter 5 cpu architecture memory space modification of figure 5-14 data to be saved to stack memory and figure 5-15 data to be restored from stack memory modification of [description example] in 5.4.4 short direct addressing addition of [illustration] in 5.4.7 based addressing , 5.4.8 based indexed addressing , and 5.4.9 stack addressing modification of port block diagram ( figures 6-2 block diagram of chapter 6 port functions p00 to p03 to 6-23 block diagram of p74 and p75 ) addition of table 6-6 port mode registers and output latch settings when alternate function is used
599 appendix e revision history user? manual u14046ej3v0ud (3/5) edition revision from previous edition chapter third addition of description of internal feedback resistor and oscillation chapter 7 clock generator edition stabilization time select register (osts) in 7.3 clock generator control registers modification of figure 8-1 block diagram of 16-bit timer/event chapter 8 16-bit timer/event counter 0 counter 0 modification of tables 8-2 ti00/to0/p70 pin valid edge and cr00, cr01 capture trigger and 8-3 ti01/p71 pin valid edge and cr00 capture trigger in 2nd edition to table 8-2 cr00 capture trigger and valid edges of ti00 and ti01 pins and table 8-3 cr01 capture trigger and valid edge of ti00 pin (crc02 = 1) modification of description procedure of each function in 8.4 operation of 16-bit timer/event counter 0 addition of figure 8-26 ppg output configuration diagram and figure 8-27 ppg output operation timing addition of 8.5 program list modification of 8.6 (3) capture register data retention timing and addition of (11) stop mode or main system clock stop mode setting modification of figures 9-1 block diagram of 8-bit timer/event chapter 9 8-bit timer/event counter 50 and 9-2 block diagram of 8-bit timer/event counter counters 50, 51 51 deletion of caution in figures 9-5 format of 8-bit timer mode control register 50 (tmc50) and 9-6 format of 8-bit timer mode control register 51 (tmc51) addition of [setting] in 9.4.2 external event counter operation addition of description of frequency to [setting] in 9.4.3 square- wave output (8-bit resolution) operation addition of description of cycle and duty ratio to [setting] in 9.4.4 8-bit pwm output operation addition of 9.5 program list deletion of 9.5 (2) operation after compare register change during timer count operation in 2nd edition deletion of oscillation stabilization time select register (osts) from chapter 11 watchdog timer 11.3 registers to control watchdog timer in 2nd edition modification of figure 12-1 block diagram of clock output/buzzer chapter 12 clock output/ output controller buzzer output controller modification of description in 13.2 (3) sample & hold circuit , (4) chapter 13 8-bit a/d converter voltage comparator , and addition of (10) adtrg pin ( pd780024a, 780024ay subseries) addition of table 13-2 sampling time and a/d conversion start delay time of a/d converter deletion of 13.6 (4) noise countermeasures (contents of deletion are added to figure 13-18 example of connecting capacitor to av ref pin and figure 13-20 example of connection if signal source impedance is high ), and addition of (14) input impedance of ani0 to ani7 pins modification of table 13-3 resistances and capacitances of equivalent circuit (reference values)
600 appendix e revision history user? manual u14046ej3v0ud (4/5) edition revision from previous edition chapter third addition of figure 14-2 format of a/d conversion result chapter 14 10-bit a/d converter edition register 0 (adcr0) ( pd780034a, 780034ay subseries) modification of description in 14.2 (3) sample & hold circuit , (4) voltage comparator , and addition of (10) adtrg pin addition of table 14-2 sampling time and a/d conversion start delay time of a/d converter deletion of 14.6 (4) noise countermeasures (contents of deletion are added to figure 14-19 example of connecting capacitor to av ref pin and figure 14-21 example of connection if signal source impedance is high ), and addition of (14) input impedance of ani0 to ani7 pins modification of table 14-3 resistances and capacitances of equivalent circuit (reference values) modification of figure 16-1 block diagram of serial interface chapter 16 serial interface uart0 uart0 move of description of asynchronous serial interface status register 0 (asis0) in 16.3 registers to control serial interface uart0 to 16.2 configuration of serial interface uart0 addition of caution in figure 16-7 error tolerance (when k = 0 ), including sampling errors modification of caution in figure 16-10 timing of asynchronous serial interface receive completion interrupt request addition of (1) registers to be used and (3) relationship between main system clock and baud rate in 16.4.3 infrared data transfer mode addition of table 16-6 register settings modification of figure 17-1 block diagram of serial interface chapter 17 serial interfaces sio3n sio30 and sio31 addition of note 3 and caution in figures 17-2 format of serial operation mode register 30 (csim30) and 17-3 format of serial operation mode register 31 (csim31) addition of table 17-2 register settings modification of figure 18-1 block diagram of serial interface iic0 chapter 18 serial interface iic0 unification of 18.2 (1) iic shift register 0 (iic0) and (4) iic shift ( pd780024ay, 780034ay subseries register 0 (iic0) in 2nd edition, and (2) slave address register 0 only) (sva0) and (3) slave address register 0 (sva0) in 2nd edition addition of description to ?ransfer lines?in figure 18-16 wait signal addition of description to notes 1 and 2 in table 18-2 intiic0 timing and wait control modification of figure 18-21 master operation flowchart modification of 18.5.15 (2) slave operation modification of (1) start condition ~ address and (2) data in figure 18-23 example of master to slave communication (when 9-clock wait is selected for both master and slave) modification of figure 18-24 example of slave to master communication (when 9-clock wait is selected for both master and slave)
601 appendix e revision history user? manual u14046ej3v0ud (5/5) edition revision from previous edition chapter third modification of (e) software interrupt in figure 19-1 basic chapter 19 interrupt functions edition configuration of interrupt function addition of caution 5 in figure 19-2 format of interrupt request flag registers (if0l, if0h, if1l) addition of caution in figure 19-5 format of external interrupt rising edge enable register (egp), external interrupt falling edge enable register (egn) addition of description and remark in 19.4.1 non-maskable interrupt request acknowledgment operation addition of description in 19.4.2 maskable interrupt request acknowledgment operation addition of an item in table 19-4 interrupt requests enabled for nesting during interrupt servicing addition of description of using expanded-specification products chapter 20 external device expansion function addition of clock output and buzzer output in table 21-1 halt chapter 21 standby function mode operating statuses modification of clock output in table 21-3 stop mode operating statuses revision of description chapter 23 pd78f0034a, 78f0034b, 78f0034ay, 78f0034by addition of description chapter 25 electrical specifications (expanded- specification products: f x = 1.0 to 12 mhz) chapter 26 electrical specifications (conventional products: f x = 1.0 to 8.38 mhz) chapter 27 package drawings chapter 28 recommended soldering conditions revision of description appendix a differences between pd78018f, 780024a, 780034a, and 780078 subseries revision of description appendix b development tools addition of description appendix c notes on target system design

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