 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| 1 of 50 ddr3 sdram rev. 1.23 july 2009 unbuffered dimm ddr3 sdram specification 240pin unbuffered dimm based on 1gb d-die 64/72-bit non-ecc/ecc 82/100fbga with lead-free (rohs compliant) * samsung electronics reserves the right to chan ge products or specification without notice. information in this document is provided in relation to samsung products, and is subject to change without notice. nothing in this document shall be construed as granting any license, express or implied, by estoppel or other- wise, to any intellectual property rights in samsung products or technol- ogy. all information in this document is provided on as "as is" basis without guarantee or warranty of any kind. 1. for updates or additional information about sa msung products, contact your nearest samsung office. 2. samsung products are not intended for use in life support, critical care, me dical, safety equipment, or similar applications where product failure could result in loss of life or personal or physical harm, or any military or defense application, or any governmen tal procurement to which special terms or provisions may apply.
2 of 50 ddr3 sdram rev. 1.23 july 2009 unbuffered dimm 1.0 ddr3 registered dimm ordering in formation ........... ................ ................. ................ ......... ......5 2.0 key features ......... ................ ................ .............. .............. .............. ............... ............ ........... ........5 3.0 address configuration .... ................. ................ ................ ................. ................ ............... ............5 4.0 x64 dimm pin configurati ons (front side/back side) .. ............... ................. ................ .............6 5.0 x72 dimm pin configurati ons (front side/back side) .. ............... ................. ................ .............7 6.0 pin description ............ ................ ................ ................. ................ ................. ............. .......... ........8 7.0 spd and thermal sensor for ecc udi mms ................. ................ ................. ................ .............8 8.0 input/output functional description ................ .............. .............. ............... .............. .............. ...9 8.1 address mirroring feature ................. ................ ................ ................. ................ .............. ...........10 8.1.1 dram pin wi ring mirroring ................ ................ .............. .............. .............. .............. ...........10 9.0 function block diag ram: .............. .............. .............. .............. ............... .............. .............. ........11 9.1 512mb, 64mx64 modu le (populated as 1 rank of x16 ddr3 sdrams) .............. .............. ............ ........11 9.2 1gb, 128mx64 module (populated as 1 rank of x8 ddr3 sdrams) ............... .............. .............. ........12 9.3 1gb, 128mx72 ecc module (populated as 1 rank of x8 ddr3 sdrams) ................. ................ ...........13 9.4 2gb, 256mx64 module (populated as 2 ranks of x8 ddr3 sdrams) ................. ............ ............ ........14 9.5 2gb, 256mx72 ecc module (populated as 2 ranks of x8 ddr3 sdrams) ............... ................ ...........15 10.0 absolute maximum ratings ............... ................. ................ ................. ................ ................ ....16 10.1 absolute maximum dc ratings ................... ................. ................ ................. ................ .............16 10.2 dram component operating temperature range ................. ................ .............. .............. ...........16 11.0 ac & dc operating conditions ..... ................ ................ .............. ............... .............. ............. ..16 11.1 recommended dc operating conditions (sstl - 15) ................. ............... .............. .............. ........16 12.0 ac & dc input measuremen t levels ............... ................. ................ .............. .............. ...........17 12.1 ac & dc logic input levels for single-ended signals .............. .............. .............. .............. ...........17 12.2 v ref tolerances ................... ................. ................ .............. .............. .............. .............. ...........18 12.3 ac & dc logic input levels for differential signals ................. .............. .............. .............. ...........19 12.3.1 differential signals definition ............... ................. ................ ................. ................ .............19 12.3.2 differential swing requirement for clock (ck - ck ) and strobe (dqs - dqs ) ............... .............19 12.3.3 single-ended requirements for differential signals ................... ................. ................ ...........20 12.3.4 differential in put cross point voltage ................ .............. .............. .............. .............. ...........21 12.4 slew rate definition for single-ended input signals ................. .............. .............. .............. ...........21 12.5 slew rate definition for differential input signals ............. ................ ................. ................ ...........21 13.0 ac & dc output measurement levels ................. .............. .............. .............. .............. ...........22 13.1 single-ended ac & dc output levels ................ ................ ................. ................ .............. ...........22 13.2 differential ac & dc output levels ................. ................ ................ ................. ................ ...........22 13.3 single-ended output slew rate ................... ................. ................ ................. ................ .............22 13.4 differential output slew rate ................. ................ .............. .............. .............. .............. ...........23 table contents 3 of 50 ddr3 sdram rev. 1.23 july 2009 unbuffered dimm 14.0 idd specification defini tion ............... ................. ................ ................. .............. .............. ........24 14.1 idd spec table ................ ................ ................ ................. ................ .............. .............. ...........26 15.0 input/output capacitance ................ ................ ................. ................ ................. ............... .......29 15.1 non ecc udimm ................ ................ ................. ................ .............. .............. .............. ...........29 15.2 ecc udimm ................ ................ ................. ................ ................ ................. ................ ...........29 16.0 electrical characteristics and ac timing .......... ................ .............. .............. .............. ...........30 16.1 refresh parameters by device density ................ ................. ................ .............. .............. ...........30 16.2 speed bins and cl, trcd, trp, trc and tras for corresponding bin ................ ................ .............30 16.3 speed bins and cl, trcd, trp, trc and tras for corresponding bin ................. ................ .............30 16.3.1 speed bin table notes ............... ................ ................. ................ .............. .............. ...........31 17.0 timing parameters by speed grade . ................. ................ .............. .............. .............. ...........32 17.1 jitter notes ................. ................ ................. ................ ................ ................. .............. .............3 5 17.2 timing parameter notes ............... ................. ................ ................ ................. ................ ...........36 17.3 address / command setup, hold and derating ................... ................. ................ .............. ...........37 17.4 data setup, hold and slew rate derating: ................ .............. .............. .............. .............. ...........43 18.0 physical dimensions ..... ................. ................ ................ ................. ................ ............... ..........48 18.1 64mbx16 based 64mx64 module (1 rank) ................ ................ .............. .............. .............. ...........48 18.2 128mbx8 based 128mx64/x72 module (1 rank) ................... ................. ................ .............. ...........49 18.3 128mbx8 based 256mx64/x72 module (2 ranks) ................ ................ ................. ................ ...........50 4 of 50 ddr3 sdram rev. 1.23 july 2009 unbuffered dimm revision history revision month year history 1.0 april 2008 - first release 1.1 august 2008 - change current spec. - corrected typo. 1.2 october 2008 - changed ac parameters to support binning down backward compatibility (1333 mbps 9-9-9 to 1066mbps 7-7-7) 1.21 january 2009 - corrected module physical dimensions. 1.22 february 2009 - added tolerances to physical dimensions 1.23 july 2009 - corrected typo. 5 of 50 ddr3 sdram rev. 1.23 july 2009 unbuffered dimm 1.0 ddr3 registered di mm ordering information note : - "##" - f8/h9 - f8 - 1066mbps 7-7-7 & h9 - 1333mbps 9-9-9 2.0 key features ? jedec standard 1.5v 0.075v power supply ?v ddq = 1.5v 0.075v ? 533mhz f ck for 1066mb/sec/pin, 667mhz f ck for 1333mb/sec/pin ? 8 independent internal bank ? programmable cas latency: 6,7,8,9,10 ? programmable additive latency(posted cas ) : 0, cl - 2, or cl - 1 clock ? programmable cas write latency(cwl) = 6(ddr3-1066) and 7(ddr3-1333) ? 8-bit pre-fetch ? burst length: 8 (interleave without any limit, sequential with st arting address ?000? only), 4 with tccd = 4 which does not al low seamless read or write [either on the fly using a12 or mrs] ? bi-directional differential data strobe ? internal(self) calibration : internal self ca libration through zq pin (rzq : 240 ohm 1%) ? on die termination using odt pin ? average refresh period 7.8us at lower then t case 85 c, 3.9us at 85 c < t case 95 c ? asynchronous reset 3.0 address configuration part number density organization component composition number of rank height m378b6474dz1-cf8/h9 512mb 64mx64 64mx16(k4b1g1646d-hc##)*4 1 30mm m378b2873dz1-cf8/h9 1gb 128mx64 128mx8(k4b1g0846d-hc##)*8 1 30mm m391b2873dz1-cf8/h9 1gb 128mx72 128mx8(k4b1g0846d-hc##)*9 1 30mm m378b5673dz1-cf8/h9 2gb 256mx64 128mx8(k4b1g0846d-hc##)*16 2 30mm m391b5673dz1-cf8/h9 2gb 256mx72 128mx8(k4b1g0846d-hc##)*18 2 30mm speed ddr3-1066 ddr3-1333 unit 7-7-7 9-9-9 tck(min) 1.875 1.5 ns cas latency 79tck trcd(min) 13.125 13.5 ns trp(min) 13.125 13.5 ns tras(min) 37.5 36 ns trc(min) 50.625 49.5 ns organization row address column address bank address auto precharge 128x8(1gb) based module a0-a13 a0-a9 ba0-ba2 a10/ap 64x16(1gb) based module a0-a12 a0-a9 ba0-ba2 a10/ap 6 of 50 ddr3 sdram rev. 1.23 july 2009 unbuffered dimm 4.0 x64 dimm pin configurati ons (front side/back side) nc = no connect; nf = no function; nu = not usable; rfu = reserved future use 1. s1 , odt1, cke1: used for dual-rank udimms; nc on single-rank udimms 2. ck1,nc 2 and ck1 ,nc 2 : used for dual-rank udimms; not used on single-rank udimms, but terminated 3. test (pin 167) used by memory bus analysis tools (unused on memory dimms) samsung electronics co., ltd. reserves the right to change products and specifications without notice. pin front pin back pin front pin back pin front pin back 1 v refdq 121 v ss 42 nc 162 nc 82 dq33 202 v ss 2 v ss 122 dq4 43 nc 163 v ss 83 v ss 203 dm4 3 dq0 123 dq5 44 v ss 164 nc 84 dqs 4 204 nc 4 dq1 124 v ss 45 nc 165 nc 85 dqs4 205 v ss 5 v ss 125 dm0 46 nc 166 v ss 86 v ss 206 dq38 6dqs 0 126 nc 47 v ss 167 nc (test) 3 87 dq34 207 dq39 7 dqs0 127 v ss 48 nc 168 reset 88 dq35 208 v ss 8 v ss 128 dq6 key 89 v ss 209 dq44 9 dq2 129 dq7 49 nc 169 cke1,nc 1 90 dq40 210 dq45 10 dq3 130 v ss 50 cke0 170 v dd 91 dq41 211 v ss 11 v ss 131 dq12 51 v dd 171 nc 92 v ss 212 dm5 12 dq8 132 dq13 52 ba2 172 nc 93 dqs 5 213 nc 13 dq9 133 v ss 53 nc 173 v dd 94 dqs5 214 v ss 14 v ss 134 dm1 54 v dd 174 a12/bc 95 v ss 215 dq46 15 dqs 1 135 nc 55 a11 175 a9 96 dq42 216 dq47 16 dqs1 136 v ss 56 a7 176 v dd 97 dq43 217 v ss 17 v ss 137 dq14 57 v dd 177 a8 98 v ss 218 dq52 18 dq10 138 dq15 58 a5 178 a6 99 dq48 219 dq53 19 dq11 139 v ss 59 a4 179 v dd 100 dq49 220 v ss 20 v ss 140 dq20 60 v dd 180 a3 101 v ss 221 dm6 21 dq16 141 dq21 61 a2 181 a1 102 dqs 6 222 nc 22 dq17 142 v ss 62 v dd 182 v dd 103 dqs6 223 v ss 23 v ss 143 dm2 63 ck1,nc 2 183 v dd 104 v ss 224 dq54 24 dqs 2 144 nc 64 ck 1,nc 2 184 ck0 105 dq50 225 dq55 25 dqs2 145 v ss 65 v dd 185 ck 0 106 dq51 226 v ss 26 v ss 146 dq22 66 v dd 186 v dd 107 v ss 227 dq60 27 dq18 147 dq23 67 v ref ca 187 nc 108 dq56 228 dq61 28 dq19 148 v ss 68 nc 188 a0 109 dq57 229 v ss 29 v ss 149 dq28 69 v dd 189 v dd 110 v ss 230 dm7 30 dq24 150 dq29 70 a10/ap 190 ba1 111 dqs 7 231 nc 31 dq25 151 v ss 71 ba0 191 v dd 112 dqs7 232 v ss 32 v ss 152 dm3 72 v dd 192 ras 113 v ss 233 dq62 33 dqs 3 153 nc 73 we 193 s 0 114 dq58 234 dq63 34 dqs3 154 v ss 74 cas 194 v dd 115 dq59 235 v ss 35 v ss 155 dq30 75 v dd 195 odt0 116 v ss 236 v ddspd 36 dq26 156 dq31 76 s 1, nc 1 196 a13 117 sa0 237 sa1 37 dq27 157 v ss 77 odt1, nc 1 197 v dd 118 scl 238 sda 38 v ss 158 nc 78 v dd 198 nc 119 sa2 239 v ss 39 nc 159 nc 79 nc 199 v ss 120 v tt 240 v tt 40 nc 160 v ss 80 v ss 200 dq36 41 v ss 161 nc 81 dq32 201 dq37 7 of 50 ddr3 sdram rev. 1.23 july 2009 unbuffered dimm 5.0 x72 dimm pin configurati ons (front side/back side) nc = no connect; nf = no function; nu = not usable; rfu = reserved future use 1. s1 , odt1, cke1: used for dual-rank udimms; nc on single-rank udimms 2. ck1,nc 2 and ck1 ,nc 2 : used for dual-rank udimms; not used on single-rank udimms, but terminated 3. test (pin 167) used by memory bus analysis tools (unused on memory dimms) samsung electronics co., ltd. reserves the right to change products and specifications without notice. pin front pin back pin front pin back pin front pin back 1 v refdq 121 v ss 42 nc 162 nc 82 dq33 202 v ss 2 v ss 122 dq4 43 nc 163 v ss 83 v ss 203 dm4 3 dq0 123 dq5 44 v ss 164 cb6 84 dqs 4 204 nc 4 dq1 124 v ss 45 cb2 165 cb7 85 dqs4 205 v ss 5 v ss 125 dm0 46 cb3 166 v ss 86 v ss 206 dq38 6dqs 0 126 nc 47 v ss 167 nc (test) 3 87 dq34 207 dq39 7 dqs0 127 v ss 48 nc 168 reset 88 dq35 208 v ss 8 v ss 128 dq6 key 89 v ss 209 dq44 9 dq2 129 dq7 49 nc 169 cke1,nc 1 90 dq40 210 dq45 10 dq3 130 v ss 50 cke0 170 v dd 91 dq41 211 v ss 11 v ss 131 dq12 51 v dd 171 nc 92 v ss 212 dm5 12 dq8 132 dq13 52 ba2 172 nc 93 dqs 5 213 nc 13 dq9 133 v ss 53 nc 173 v dd 94 dqs5 214 v ss 14 v ss 134 dm1 54 v dd 174 a12/bc 95 v ss 215 dq46 15 dqs 1 135 nc 55 a11 175 a9 96 dq42 216 dq47 16 dqs1 136 v ss 56 a7 176 v dd 97 dq43 217 v ss 17 v ss 137 dq14 57 v dd 177 a8 98 v ss 218 dq52 18 dq10 138 dq15 58 a5 178 a6 99 dq48 219 dq53 19 dq11 139 v ss 59 a4 179 v dd 100 dq49 220 v ss 20 v ss 140 dq20 60 v dd 180a3101 v ss 221 dm6 21 dq16 141 dq21 61 a2 181 a1 102 dqs 6 222 nc 22 dq17 142 v ss 62 v dd 182 v dd 103 dqs6 223 v ss 23 v ss 143 dm2 63 ck1,nc 2 183 v dd 104 v ss 224 dq54 24 dqs 2 144 nc 64 ck 1,nc 2 184 ck0 105 dq50 225 dq55 25 dqs2 145 v ss 65 v dd 185 ck 0 106 dq51 226 v ss 26 v ss 146 dq22 66 v dd 186 v dd 107 v ss 227 dq60 27 dq18 147 dq23 67 v ref ca 187 event 108 dq56 228 dq61 28 dq19 148 v ss 68 nc 188 a0 109 dq57 229 v ss 29 v ss 149 dq28 69 v dd 189 v dd 110 v ss 230 dm7 30 dq24 150 dq29 70 a10/ap 190 ba1 111 dqs 7 231 nc 31 dq25 151 v ss 71 ba0 191 v dd 112 dqs7 232 v ss 32 v ss 152 dm3 72 v dd 192 ras 113 v ss 233 dq62 33 dqs 3 153 nc 73 we 193 s 0 114 dq58 234 dq63 34 dqs3 154 v ss 74 cas 194 v dd 115 dq59 235 v ss 35 v ss 155 dq30 75 v dd 195 odt0 116 v ss 236 v ddspd 36 dq26 156 dq31 76 s 1, nc 1 196 a13 117 sa0 237 sa1 37 dq27 157 v ss 77 odt1, nc 1 197 v dd 118 scl 238 sda 38 v ss 158 cb4 78 v dd 198 nc 119 sa2 239 v ss 39 cb0 159 cb5 79 nc 199 v ss 120 v tt 240 v tt 40 cb1 160 v ss 80 v ss 200 dq36 41 v ss 161 dm8 81 dq32 201 dq37 8 of 50 ddr3 sdram rev. 1.23 july 2009 unbuffered dimm 6.0 pin description *the v dd and v ddq pins are tied common to a single power-plane on these designs. 7.0 spd and thermal sensor for ecc udimms on dimm thermal sensor will provide dram temperat ure readout through a integrated thermal sensor. note : 1. raw cards d (1rx8 ecc) and e (2rx8 ecc) support a thermal sensor. 2. when the spd and the thermal sensor are placed on the module, r1 is placed but r2 is not. when only the spd is placed on the module, r2 is placed but r1 is not. temperature sensor characteristics pin name description pin name description a0-a13 sdram address bus scl i 2 c serial bus clock for eeprom ba0-ba2 sdram bank select sda i 2 c serial bus data line for eeprom ras sdram row address strobe sa0-sa2 i 2 c serial address select for eeprom cas sdram column address strobe v dd * sdram core power supply we sdram write enable v ddq * sdram i/o driver power supply s 0, s 1 dimm rank select lines v refdq sdram i/o reference supply cke0,cke1 sdram clock enable lines v refca sdram command/address reference supply odt0, odt1 on-die termination control lines v ss power supply return (ground) dq0 - dq63 dimm memory data bus v ddspd serial eeprom positive power supply cb0 - cb7 dimm ecc check bits nc spare pins(no connect) dqs0 - dqs8 sdram data strobes (positive line of differential pair) test used by memory bus analysis tools (unused on memory dimms) dqs 0-dqs 8 sdram differential data strobes (negative line of differential pair) reset set drams known state dm0-dm8 sdram data masks/high data strobes (x8-based x72 dimms) event reserved for optional temperature-sensing hardware ck0, ck1 sdram clocks (positive line of differential pair) v tt sdram i/o termination supply ck 0, ck 1 sdram clocks (negative line of differential pair) rfu reserved for future use grade range temperature sensor accuracy units notes min. typ. max. b 75 < ta < 95 - +/- 0.5 +/- 1.0 c - 40 < ta < 125 - +/- 1.0 +/- 2.0 - -20 < ta < 125 - +/- 2.0 +/- 3.0 - resolution 0.25 c /lsb - scl sda wp/event sa0 sa1 sa2 sa0 sa1 sa2 event r1 0 ? r2 0 ? 9 of 50 ddr3 sdram rev. 1.23 july 2009 unbuffered dimm 8.0 input/output functional description symbol type function ck0-ck1 ck 0-ck 1 sstl ck and ck are differential clock inputs. all the ddr3 sdram addr/cntl inputs are sampled on the crossing of positive edge of ck and negative edge of ck . output (read) data is reference to the crossing of ck and ck (both directions of crossing) cke0-cke1 sstl activates the sdram ck signal when hi gh and deactivates the ck signal when low. by deactivating the clocks, cke low initiates the power down mode, or the self-refresh mode s 0-s 1sstl enables the associated sdram command decoder when low and disables the command decoder when high. when the command decoder is disabled, new command are ignored but prev ious operations continue. this signal provides for external rank selection on systems with multiple ranks. ras , cas , we sstl ras , cas , and we ( along with s ) define the command being entered. odt0-odt1 sstl when high, termination resistance is enabled for all dq, dqs, dqs and dm pins, assuming the function is enabled in the extended mode register set (emrs). v refdq supply reference voltage for sstl 15 i/o inputs. v refca supply reference voltage for sstl 15 command/address inputs. v ddq supply power supply for the ddr3 sdram output buffers to provi de improved noise immunity. for all current ddr3 unbuffered dimm designs, v ddq shares the same power plane as v dd pins. ba0-ba2 sstl selects which sdram bank of eight is activated. a0-a13 sstl during a bank activate command cycle, addre ss input defines the row address (ra0-ra13) during a read or write command cycle, address input defines the column address, in addition to the column address, ap is used to invoke autoprecharge operation at the end of t he burst read or write cycle. if ap is high, autoprecharge is selected and ba0, ba1, ba2 defines the bank to be precharged . if ap is low, autoprecharge is disabled. during a pre- charge command cycle, ap is used in conjunction with ba0, ba1, ba2 to control which bank(s) to precharge. if ap is high, all banks will be precharged regardless of the state of ba0, ba1 or ba2. if ap is low, ba0, ba1 and ba2 are used to define which bank to precharge. a12(bc ) is sampled during read and write commands to determine if burst chop (on-the-fly) will be performed (high, no burst chop; low, burst chopped). dq0-dq63 cb0-cb7 sstl data and check bit input/output pins. dm0-dm8 sstl dm is an input mask signal for write data. input data is mask ed when dm is sampled high coincident with that input data during a write access. dm is sampled on both edges of dqs. although dm pins are input only, the dm loading matches the dq and dqs loading. v dd ,v ss supply power and ground for ddr3 sdram input buffers, and core logic. v dd and v ddq pins are tied to v dd /v ddq planes on these modules. dqs0-dqs8 dqs 0-dqs 8 sstl data strobe for input and output data. for raw cards usin g x16 organized drams, pins dq 0-7 are associated with the ldqs and ldqs pins and pins dq8-15 are associated with udqs and udqs pins. sa0-sa2 - these signals and tied at the system planar to either v ss or v ddspd to configure the serial spd eerpom address range. sda - this bidirectional pin is used to transfer data into or out of the spd eeprom. an external resistor may be connected from the sda bus line to v ddspd to act as a pull-up on the system board. scl - this signal is used to clock data into and out of the spd eeprom. an external resistor may be connected from the scl bus time to v ddspd to act as a pull-up on the system board. v ddspd supply power supply for spd eeprom. this supply is separate from the v dd /v ddq power plane. eeprom supply is operable from 3.0v to 3.6v. reset - the reset pin is connected to the reset pin on each dram. when low, all drams are set to a know state. event output this signal indicates that a thermal event has been detec ted in the thermal sensing device. the system should guaran- tee the electrical level requirement is met for the event pin on ts/spd part 10 of 50 ddr3 sdram rev. 1.23 july 2009 unbuffered dimm 8.1 address mirroring feature there is a via grid located under the drams for wiring the ca signals (address, bank address, command, and control lines) to th e dram pins. the length of the traces from the vias to the drams places limitations on the bandwidth of the module. the shorter these traces, the highe r the bandwidth. to extend the bandwidth of the ca bus for ddr3 modules, a scheme was defined to reduce the length of these traces. the pins on the dram are defined in a manner that allows for th ese short trace lengths. the ca bus pins in columns 2 and 8, ign oring the mechanical support pins, do not have any special function s (secondary functions). this allows the most flexibility with these pins. these are address pins a3, a4, a5, a6, a7, a8 and bank address pins ba0 and ba1. refer to table . rank 0 dram pins are wired straight, with no mismatch between th e connector pin assignment and the dram pin assignment. some of the rank 1 dram pins are cross wired as defined in the table. pins not listed i n the table are wired straight. 8.1.1 dram pin wiring mirroring figure 1 illustrates the wiring in both the mirrored and non-mirrored case. the lengths of the trac es to the dram pins, is obvi ously shorter. the via grid is smaller as well. figure 1 - wiring differences for mirrored and non-mirrored addresses since the cross-wired pins have no secondary functions, there is no problem in normal operation. any data written is read the s ame way. there are limi- tations however. when writing to the internal registers with a "load mode" operation, the specific address is required. this re quires the controller to know if the rank is mirrored or not. this requires a few rules. mirroring is done on 2 rank modules and can only be done on the seco nd rank. there is not a requirement that the second rank be mirrored. there is a bit as signment in the spd that indicates whether the module has been d esigned with the mir- rored feature or not. see the ddr3 udimm spd specification for these details. the controller must read the spd and have the cap ability of de-mirroring the address when accessing the second rank. connector pin dram pin rank 0 rank 1 a3 a3 a4 a4 a4 a3 a5 a5 a6 a6 a6 a5 a7 a7 a8 a8 a8 a7 ba0 ba0 ba1 ba1 ba1 ba0 11 of 50 ddr3 sdram rev. 1.23 july 2009 unbuffered dimm 9.0 function block diagram: 9.1 512mb, 64mx64 module (populated as 1 rank of x16 ddr3 sdrams) s 0 dqs 0 dqs0 dm0 cs dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 d0 note : 1. dq-to-i/o wiring is shown as recommended but may be changed. 2. dq/dqs/dqs /odt/dm/cke/s relationships must be maintained as shown. 3. dq, dm, dqs/dqs resistors: refer to associated topology diagram. 4. refer to the appropriate clock wiring topology under the dimm wiring details section of this document. 5. the pair ck1 and ck 1 is terminated in 7.5 ? but is not used on the module. 6. a15 is not routed on the module. 7. for each dram, a unique zq resistor is connected to ground. the zq resistor is 240 ? 1% 8. one spd exists per module. a0 serial pd a1 a2 sa0 sa1 sa2 scl sda v ss d0 - d3 v dd /v ddq d0 - d3 d0 - d3 v refdq v ddspd spd a0 - a14 a0-a14 : sdrams d0 - d3 ras ras : sdrams d0 - d3 cas cas : sdrams d0 - d3 we we : sdrams d0 - d3 cke0 cke : sdrams d0 - d3 ba0 - ba2 ba0-ba2 : sdrams d0 - d3 odt0 odt : sdrams d0 - d3 v refca d0 - d3 ck0 ck : sdrams d0 - d3 zq ldqs ldqs ldm dqs 1 dqs1 dm1 dq8 dq9 dq10 dq11 dq12 dq13 dq14 dq15 i/o 8 i/o 9 i/o 10 i/o 11 i/o 12 i/o 13 i/o 14 i/o 15 udqs udqs udm dqs 2 dqs2 dm2 cs dq16 dq17 dq18 dq19 dq20 dq21 dq22 dq23 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 d1 zq ldqs ldqs ldm dqs 3 dqs3 dm3 dq24 dq25 dq26 dq27 dq28 dq29 dq30 dq31 i/o 8 i/o 9 i/o 10 i/o 11 i/o 12 i/o 13 i/o 14 i/o 15 udqs udqs udm dqs 4 dqs4 dm4 cs dq32 dq33 dq34 dq35 dq36 dq37 dq38 dq39 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 d0 zq ldqs ldqs ldm dqs 5 dqs5 dm5 dq40 dq41 dq42 dq43 dq44 dq45 dq46 dq47 i/o 8 i/o 9 i/o 10 i/o 11 i/o 12 i/o 13 i/o 14 i/o 15 udqs udqs udm dqs 6 dqs6 dm6 cs dq48 dq49 dq50 dq51 dq52 dq53 dq54 dq55 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 d1 zq ldqs ldqs ldm dqs 3 dqs3 dm3 dq56 dq57 dq58 dq59 dq60 dq61 dq62 dq63 i/o 8 i/o 9 i/o 10 i/o 11 i/o 12 i/o 13 i/o 14 i/o 15 udqs udqs udm ck 0ck : sdrams d0 - d3 reset reset : sdrams d0 - d3 wp 12 of 50 ddr3 sdram rev. 1.23 july 2009 unbuffered dimm 9.2 1gb, 128mx64 module (populated as 1 rank of x8 ddr3 sdrams) s 0 dqs 0 dqs0 dm0 dm cs dqs dqs dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 d0 dqs 1 dqs1 dm1 dm cs dqs dqs dq8 dq9 dq10 dq11 dq12 dq13 dq14 dq15 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 d1 dqs 2 dqs 2 dm2 dm cs dqs dqs dq16 dq17 dq18 dq19 dq20 dq21 dq22 dq23 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 d2 dqs 3 dqs3 dm3 dm nu/ cs dqs dqs dq24 dq25 dq26 dq27 dq28 dq29 dq30 dq31 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 d3 dqs 4 dqs4 dm4 dm cs dqs dqs dq32 dq33 dq34 dq35 dq36 dq37 dq38 dq39 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 d4 dqs 5 dqs5 dm5 dm cs dqs dqs dq40 dq41 dq42 dq43 dq44 dq45 dq46 dq47 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 d5 dqs 6 dqs6 dm6 dm cs dqs dqs dq48 dq49 dq50 dq51 dq52 dq53 dq54 dq55 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 d6 dqs 7 dqs7 dm7 dm cs dqs dqs dq56 dq57 dq58 dq59 dq60 dq61 dq62 dq63 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 d7 note : 1. dq-to-i/o wiring is shown as recommended but may be changed. 2. dq/dqs/dqs /odt/dm/cke/s relationships must be maintained as shown. 3. dq, dm, dqs/dqs resistors: refer to associated topology diagram. 4. refer to the appropriate clock wiring topology under the dimm wiring details section of this document. 5. refer to section 7.1 of this document for details on address mirroring. 6. for each dram, a unique zq resistor is connected to ground. the zq resistor is 240 ohm +/- 1% 7. one spd exists per module. v ss d0 - d7 v dd /v ddq d0 - d7 d0 - d7 v refdq v ddspd spd a0 - a13 a0-a13 : sdrams d0 - d7 ras ras : sdrams d0 - d7 cas cas : sdrams d0 - d7 we we : sdrams d0 - d7 cke0 cke : sdrams d0 - d7 ba0 - ba2 ba0-ba2 : sdrams d0 - d7 odt0 odt : sdrams d0 - d7 v refca d0 - d7 ck0 ck : sdrams d0 - d7 zq zq zq zq zq zq zq zq a0 serial pd a1 a2 sa0 sa1 sa2 scl sda wp 13 of 50 ddr3 sdram rev. 1.23 july 2009 unbuffered dimm 9.3 1gb, 128mx72 ecc module (populated as 1 rank of x8 ddr3 sdrams) s 0 dqs 0 dqs0 dm0 dm cs dqs dqs dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 d0 dqs 1 dqs1 dm1 dm cs dqs dqs dq8 dq9 dq10 dq11 dq12 dq13 dq14 dq15 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 d1 dqs 2 dqs 2 dm2 dm cs dqs dqs dq16 dq17 dq18 dq19 dq20 dq21 dq22 dq23 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 d2 dqs 3 dqs3 dm3 dm cs dqs dqs dq24 dq25 dq26 dq27 dq28 dq29 dq30 dq31 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 d3 dqs 4 dqs4 dm4 dm cs dqs dqs dq32 dq33 dq34 dq35 dq36 dq37 dq38 dq39 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 d4 dqs 5 dqs5 dm5 dm cs dqs dqs dq40 dq41 dq42 dq43 dq44 dq45 dq46 dq47 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 d5 dqs 6 dqs6 dm6 dm cs dqs dqs dq48 dq49 dq50 dq51 dq52 dq53 dq54 dq55 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 d6 dqs 7 dqs7 dm7 dm cs dqs dqs dq56 dq57 dq58 dq59 dq60 dq61 dq62 dq63 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 d7 dqs 8 dqs8 dm8 dm cs dqs dqs cb0 cb1 cb2 cb3 cb4 cb5 cb6 cb7 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 d8 v ss d0 - d8 v dd /v ddq d0 - d8 d0 - d8 v refdq v ddspd spd v refca d0 - d8 note : 1. dq-to-i/o wiring is shown as recommended but may be changed. 2. dq/dqs/dqs /odt/dm/cke/s relationships must be maintained as shown. 3. dq, cb, dm, dqs/dqs resistors: refe r to associated topology diagram. 4. refer to the appropriate clock wiring topology under the dimm wiring details section of this document. 5. for each dram, a unique zq resistor is connected to ground. the zq resistor is 240 ohm +/- 1% 6 . refer to "spd and thermal sensor for ecc udimms" for spd detail. a0 - a15 a0-a15 : sdrams d0 - d8 ras ras : sdrams d0 - d8 cas cas : sdrams d0 - d8 we we : sdrams d0 - d8 cke0 cke : sdrams d0 - d8 ba0 - ba2 ba0-ba2 : sdrams d0 - d8 odt0 odt : sdrams d0 - d8 ck0 ck : sdrams d0 - d8 zq zq zq zq zq zq zq zq zq a0 serial pd a1 a2 sa0 sa1 sa2 scl sda event event 14 of 50 ddr3 sdram rev. 1.23 july 2009 unbuffered dimm 9.4 2gb, 256mx64 module (populated as 2 ranks of x8 ddr3 sdrams) s 0 dqs 0 dqs0 dm0 dm cs dqs dqs dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 d0 dqs 1 dqs1 dm1 dm cs dqs dqs dq8 dq9 dq10 dq11 dq12 dq13 dq14 dq15 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 d1 dqs 2 dqs 2 dm2 dm cs dqs dqs dq16 dq17 dq18 dq19 dq20 dq21 dq22 dq23 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 d2 dqs 3 dqs3 dm3 dm cs dqs dqs dq24 dq25 dq26 dq27 dq28 dq29 dq30 dq31 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 d3 dqs 4 dqs4 dm4 dm cs dqs dqs dq32 dq33 dq34 dq35 dq36 dq37 dq38 dq39 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 d4 dqs 5 dqs5 dm5 dm cs dqs dqs dq40 dq41 dq42 dq43 dq44 dq45 dq46 dq47 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 d5 dqs 6 dqs6 dm6 dm cs dqs dqs dq48 dq49 dq50 dq51 dq52 dq53 dq54 dq55 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 d6 dqs 7 dqs7 dm7 dm cs dqs dqs dq56 dq57 dq58 dq59 dq60 dq61 dq62 dq63 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 d7 dqs 8 dqs8 dm8 dm cs dqs dqs cb0 cb1 cb2 cb3 cb4 cb5 cb6 cb7 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 d8 v ss d0 - d8 v dd /v ddq d0 - d8 d0 - d8 v refdq v ddspd spd v refca d0 - d8 note : 1. dq-to-i/o wiring is shown as recommended but may be changed. 2. dq/dqs/dqs /odt/dm/cke/s relationships must be maintained as shown. 3. dq, cb, dm, dqs/dqs resistors: refe r to associated topology diagram. 4. refer to the appropriate clock wiring topology under the dimm wiring details section of this document. 5. for each dram, a unique zq resistor is connected to ground. the zq resistor is 240 ohm +/- 1% 6 . refer to "spd and thermal sensor for ecc udimms" for spd detail. a0 - a15 a0-a15 : sdrams d0 - d8 ras ras : sdrams d0 - d8 cas cas : sdrams d0 - d8 we we : sdrams d0 - d8 cke0 cke : sdrams d0 - d8 ba0 - ba2 ba0-ba2 : sdrams d0 - d8 odt0 odt : sdrams d0 - d8 ck0 ck : sdrams d0 - d8 zq zq zq zq zq zq zq zq zq a0 serial pd a1 a2 sa0 sa1 sa2 scl sda event event 15 of 50 ddr3 sdram rev. 1.23 july 2009 unbuffered dimm 9.5 2gb, 256mx72 ecc module (populated as 2 ranks of x8 ddr3 sdrams) s 0 dqs 0 dqs0 dm0 dm cs dqs dqs dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 d0 dqs 1 dqs1 dm1 dm cs dqs dqs dq8 dq9 dq10 dq11 dq12 dq13 dq14 dq15 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 d1 dqs 2 dqs 2 dm2 dm cs dqs dqs dq16 dq17 dq18 dq19 dq20 dq21 dq22 dq23 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 d2 dqs 3 dqs3 dm3 dm cs dqs dqs dq24 dq25 dq26 dq27 dq28 dq29 dq30 dq31 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 d3 dqs 4 dqs4 dm4 dm cs dqs dqs dq32 dq33 dq34 dq35 dq36 dq37 dq38 dq39 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 d4 dqs 5 dqs5 dm5 dm cs dqs dqs dq40 dq41 dq42 dq43 dq44 dq45 dq46 dq47 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 d5 dqs 6 dqs6 dm6 dm cs dqs dqs dq48 dq49 dq50 dq51 dq52 dq53 dq54 dq55 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 d6 dqs 7 dqs7 dm7 dm cs dqs dqs dq56 dq57 dq58 dq59 dq60 dq61 dq62 dq63 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 d7 dm cs dqs dqs i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 d9 dm cs dqs dqs i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 d10 dm cs dqs dqs i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 d11 dm cs dqs dqs i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 d12 dm cs dqs dqs i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 d13 dm cs dqs dqs i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 d14 dm cs dqs dqs i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 d15 dm cs dqs dqs i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 d16 s 1 dqs 8 dqs8 dm8 dm cs dqs dqs i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 d8 dm cs dqs dqs i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 d17 cb0 cb1 cb2 cb3 cb4 cb5 cb6 cb7 v ss d0 - d17 v dd /v ddq d0 - d17 d0 - d17 v refdq v ddspd spd v refca d0 - d17 note : 1. dq-to-i/o wiring is shown as recommended but may be changed. 2. dq/dqs/dqs /odt/dm/cke/s relationships must be maintained as shown. 3. dq, cb, dm, dqs, dqs resistors: refer to associated topology diagram. 4. refer to section 7.1 of this document for details on address mirroring. 5. for each dram, a unique zq resistor is connected to ground. the zq resistor is 240 ohm +/- 1% 6 . refer to "spd and thermal sensor for ecc udimms" for spd detail. a0 - a15 a0-a15 : sdrams d0 - d17 ras ras : sdrams d0 - d17 cas cas : sdrams d0 - d17 we we : sdrams d0 - d17 cke0 cke : sdrams d0 - d8 ba0 - ba2 ba0-ba2 : sdrams d0 - d17 odt0 odt : sdrams d0 - d8 odt1 odt : sdrams d9 - d17 ck0 ck : sdrams d0 - d8 ck1 ck : sdrams d9 - d17 cke1 cke : sdrams d9 - d17 zq zq zq zq zq zq zq zq zq zq zq zq zq zq zq zq zq zq a0 serial pd a1 a2 sa0 sa1 sa2 scl sda event event 16 of 50 ddr3 sdram rev. 1.23 july 2009 unbuffered dimm 10.0 absolute maximum ratings 10.1 absolute maximum dc ratings note : 1. stresses greater than those listed under ?absolute maximum ra tings? may cause permanent damage to the device. this is a stre ss rating only and functional operation of the device at these or any other conditions above t hose indicated in the operat ional sections of this s pecification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. storage temperature is the case surface temperature on the c enter/top side of the dram. for the measurement conditions, plea se refer to jesd51-2 standard. 3. v dd and v ddq must be within 300mv of each other at all times;and v ref must be not greater than 0.6 x v ddq , when v dd and v ddq are less than 500mv; v ref may be equal to or less than 300mv. 10.2 dram component operating temperature range note : 1. operating temperature t oper is the case surface temperature on the center/top side of the dram. for measurement conditions, please refer to the jedec document jesd51-2. 2. the normal temperature range specifies the temperatures wher e all dram specifications will be supported. during operation, t he dram case tem- perature must be maintained between 0-85 c under all operating conditions 3. some applications require operation of the extended temperature range between 85 c and 95 c case temperature. full specifications are guaran- teed in this range, but the fo llowing additional conditions apply: a) refresh commands must be doubled in frequency, therefore r educing the refresh interval trefi to 3.9us. it is also possibl e to specify a component with 1x refresh (trefi to 7.8us) in the extended temperature range. b) if self-refresh operation is required in the extended temp erature range, then it is mandatory to either use the manual sel f-refresh mode with extended temperature range capability (mr2 a6 = 0b and mr2 a7 = 1b) or enable the optional auto self-refresh mode (mr2 a6 = 1b and mr2 a7 = 0b) 11.0 ac & dc operating conditions 11.1 recommended dc operating conditions (sstl - 15) note : 1. under all conditions v ddq must be less than or equal to v dd . 2. v ddq tracks with v dd . ac parameters are measured with v dd and v ddq tied together. symbol parameter rating units notes v dd voltage on v dd pin relative to v ss -0.4 v ~ 1.975 v v 1,3 v ddq voltage on v ddq pin relative to v ss -0.4 v ~ 1.975 v v 1,3 v in, v out voltage on any pin relative to v ss -0.4 v ~ 1.975 v v 1 t stg storage temperature -55 to +100 c 1, 2 symbol parameter rating unit notes t oper operating temperature range 0 to 95 c 1, 2, 3 symbol parameter rating units notes min. typ. max. v dd supply voltage 1.425 1.5 1.575 v 1,2 v ddq supply voltage for output 1.425 1.5 1.575 v 1,2 17 of 50 ddr3 sdram rev. 1.23 july 2009 unbuffered dimm 12.0 ac & dc input measurement levels 12.1 ac & dc logic input levels for single-ended signals single ended ac and dc input levels for command and address note : 1. for input only pins except reset , v ref = v refca (dc) 2. see "overshoot and undershoot specifications" section. 3. the ac peak noise on v ref may not allow v ref to deviate from v ref (dc) by more than 1% v dd (for reference : approx. 15mv) 4. for reference : approx. v dd /2 15mv single ended ac and dc input levels for dq and dm note : 1. for input only pins except reset , v ref = v refdq (dc) 2. see 9.6 "overshoot and under shoot specifications" section. 3. the ac peak noise on v ref may not allow v ref to deviate from v ref (dc) by more than 1% v dd (for reference : approx. 15mv) 4. for reference : approx. v dd /2 15mv 5. single ended swing requirement for dqs - dqs is 350mv (peak to peak). differential swing for dqs - dqs is 700mv (peak to peak). symbol parameter ddr3-1066 ddr3-1333 unit notes min. max. min. max. v ih.ca (dc) dc input logic high v ref + 100 v dd v ref + 100 v dd mv 1 v il.ca (dc) dc input logic low v ss v ref - 100 v ss v ref - 100 mv 1 v ih.ca (ac) ac input logic high v ref + 175 - v ref + 175 -mv1,2 v il.ca (ac) ac input logic low - v ref - 175 - v ref - 175 mv 1,2 v ih.ca (ac150) ac input logic high - - v ref +150 -mv1,2 v il.ca (ac150) ac input logic low - - - v ref -150 mv 1,2 v refca (dc) reference voltage for add, cmd inputs 0.49*v dd 0.51*v dd 0.49*v dd 0.51*v dd v3,4 symbol parameter ddr3-1066 ddr3-1333 unit notes min. max. min. max. v ih.dq (dc) dc input logic high v ref + 100 v dd v ref + 100 v dd mv 1 v il.dq (dc) dc input logic low v ss v ref - 100 v ss v ref - 100 mv 1 v ih.dq (ac) ac input logic high v ref + 175 - v ref + 150 - mv 1,2,5 v il.dq (ac) ac input logic low - v ref - 175 - v ref - 150 mv 1,2,5 v ref dq (dc) i/o reference voltage(dq) 0.49*v dd 0.51*v dd 0.49*v dd 0.51*v dd v3,4 18 of 50 ddr3 sdram rev. 1.23 july 2009 unbuffered dimm 12.2 v ref tolerances the dc-tolerance limits and ac-noise limits for the reference voltages v refca and v refdq are illustrate in figure 2. it shows a valid reference voltage v ref (t) as a function of time. (v ref stands for v refca and v refdq likewise). v ref (dc) is the linear average of v ref (t) over a very long period of time (e.g. 1 sec). th is average has to meet the min/max requirements of v ref . fur- thermore v ref (t) may temporarily deviate from v ref (dc) by no more than 1% v dd . the voltage levels for setup and hold time measurements v ih (ac), v ih (dc), v il (ac) and v il (dc) are dependent on v ref . "v ref " shall be understood as v ref (dc), as defined in figure 2. this clarifies, that dc-variations of v ref affect the absolute voltage a signal has to reach to ac hieve a valid high or low level and therefore the time to which setup and hold is measured. system timi ng and voltage budgets need to account for v ref (dc) deviations from the optimum position within the data-eye of the input signals. this also clarifies that the dram setup/hold specification and derating values need to include time and voltage associated wit h v ref ac-noise. timing and voltage effects due to ac-noise on v ref up to the specified limit (+/-1% of v dd ) are included in dram timings and their associated deratings. voltage v dd v ss time figure 2. illustration of v ref (dc) tolerance and v ref ac-noise limits 19 of 50 ddr3 sdram rev. 1.23 july 2009 unbuffered dimm 12.3 ac & dc logic input levels for differential signals 12.3.1 differential signals definition 12.3.2 differential swing requirement for clock (ck - ck ) and strobe (dqs - dqs ) notes: 1. used to define a differential signal slew-rate. 2. for ck - ck use v ih /v il (ac) of add/cmd and v refca ; for dqs - dqs , dqsl - dqsl , dqsu - dqsu use v ih /v il (ac) of dqs and v refdq ; if a reduced ac-high or ac-low level is used for a si gnal group, then the reduced level applies also here. 3. these values are not defined, however they single-ended signals ck, ck , dqs, dqs , dqsl, dqsl , dqsu, dqsu need to be within the respective limits (v ih (dc) max, v il (dc)min) for single-ended signals as well as the limitations for overshoot and undersh oot. refer to "overshoot and undersheet specification " on page20. allowed time before ringback (tdvac) for clk - clk and dqs - dqs . symbol parameter ddr3-1066/1333 unit note min max v ihdiff differential input high +0.2 note 3 v 1 v ildiff differential input low note 3 -0.2 v 1 v ihdiff (ac) differential input high ac 2 x (v ih (ac)-v ref ) note 3 v 2 v ildiff (ac) differential input low ac note 3 2 x (v ref - v il (ac)) v2 slew rate [v/ns] tdvac [ps] @ |v ih/ldiff (ac)| = 350mv tdvac [ps] @ |v ih/ldiff (ac)| = 300mv min max min max > 4.0 75 - 175 - 4.0 57 - 170 - 3.0 50 - 167 - 2.0 38 - 163 - 1.8 34 - 162 - 1.6 29 - 161 - 1.4 22 - 159 - 1.2 13 - 155 - 1.0 0 - 150 - < 1.0 0 - 150 - figure 3 : definition of differential ac -swing and "time above ac level" tdvac 0.0 tdvac v ih .diff.min half cycle differential input voltage (i.e. dqs-dqs , ck-ck ) time tdvac v ih .diff.ac.min v il .diff.max v il .diff.ac.max 20 of 50 ddr3 sdram rev. 1.23 july 2009 unbuffered dimm 12.3.3 single-ended requirements for differential signals each individual component of a differen tial signal (ck, dqs, dqsl, dqsu, ck , dqs , dqsl , or dqsu ) has also to comply with certain requirements for single-ended signals. ck and ck have to approximately reach v seh min / v sel max (approximately equal to the ac-levels ( v ih (ac) / v il (ac) ) for add/cmd signals) in every half-cycle. dqs, dqsl, dqsu, dqs , dqsl have to reach v seh min / v sel max (approximately the ac-levels ( v ih (ac) / v il (ac) ) for dq signals) in every half-cycle proceeding and following a valid transition. note that the applicable ac-levels for add/cmd and dq ?s might be different per speed-bin etc. e.g. if v ih 150(ac)/v il 150(ac) is used for add/cmd sig- nals, then these ac-levels apply also for the single-ended signals ck and ck . note that while add/cmd and dq signal requirements are with respect to v ref , the single-ended components of differential signals have a requirement with respect to v dd /2; this is nominally the same. the trans ition of single-ended signals through the ac-lev els is used to measure setup time. for single- ended components of differential signals the requirement to reach v sel max, v seh min has no bearing on timing, but adds a restriction on the common mode characteristic s of these signals. single ended levels for ck, dqs, dqsl, dqsu, ck , dqs , dqsl or dqsu notes: 1. for ck, ck use v ih /v il (ac) of add/cmd; for strobes (dqs, dqs , dqsl, dqsl , dqsu, dqsu ) use v ih /v il (ac) of dqs. 2. v ih (ac)/v il (ac) for dqs is based on v refdq ; v ih (ac)/v il (ac) for add/cmd is based on v refca ; if a reduced ac-high or ac-low level is used for a signal group, then the redu ced level applies also here 3. these values are not defined, however they single-ended signals ck, ck , dqs, dqs , dqsl, dqsl , dqsu, dqsu need to be within the respective limits (v ih (dc) max, v il (dc)min) for single-ended signals as well as the limitations for overshoot and unders hoot. refer to "overshoot and undershoot specification" symbol parameter ddr3-1066/1333 unit notes min max v seh single-ended high-level for strobes (v dd /2)+0.175 note3 v 1, 2 single-ended high-level for ck, ck (v dd /2)+0.175 note3 v 1, 2 v sel single-ended low-level for strobes note3 (v dd /2)-0.175 v1, 2 single-ended low-level for ck, ck note3 (v dd /2)-0.175 v1, 2 v dd or v ddq v seh min v dd /2 or v ddq /2 v sel max v seh v ss or v ssq v sel ck or dqs time figure 4 : single-ended requirement for differential signals. 21 of 50 ddr3 sdram rev. 1.23 july 2009 unbuffered dimm 12.3.4 differential input cross point voltage to guarantee tight setup and hold times as well as output skew parameters with respect to cl ock and strobe, each cross point vo ltage of differential input signals (ck, ck and dqs, dqs ) must meet the requirements in below table. the differential input cross point voltage v ix is measured from the actual cross point of true and complement signal to the mid level between of v dd and v ss . cross point voltage for differential input signals (ck, dqs) note : 1. extended range for v ix is only allowed for clock and if si ngle-ended clock input signals ck and ck are monotonic, have a single-ended swing v sel / v seh of at least v dd /2 =/-250 mv, and the differential slew rate of ck-ck is larger than 3 v/ ns. refer to table 11 on page 17 for v sel and v seh standard values. 12.4 slew rate definition for single-ended input signals see "address / command setup, hold and derating" on page 36 fo r single-ended slew rate definit ions for address and command sig nals. see "data setup, hold and slew rate derating" on page 42 for si ngle-ended slew rate definitions for data signals.tdh nominal s lew rate for a falling sig- nal is defined as the slew rate between the last crossing of v ih (dc)min and the first crossing of v ref 12.5 slew rate definition for differential input signals input slew rate for differential signals (ck, ck and dqs, dqs ) are defined and measured as shown in below. differential input slew rate definition symbol parameter ddr3-1066/1333 unit notes min max v ix differential input cross point voltage relative to v dd /2 for ck,ck -150 150 mv -175 175 mv 1 v ix differential input cross point voltage relative to v dd /2 for dqs,dqs -150 150 mv description measured defined by from to differential input slew rate for rising edge (ck-ck and dqs-dqs ) v ildiffmax v ihdiffmin v ihdiffmin - v ildiffmax delta trdiff differential input slew rate for falling edge (ck-ck and dqs-dqs ) v ihdiffmin v ildiffmax v ihdiffmin - v ildiffmax delta tfdiff v dd ck , dqs v dd /2 ck, dqs v ss v ix v ix v ix figure 5. v ix definition figure 6. differential input slew rate definition for dqs, dqs and ck, ck v ihdiffmin 0 v ildiffmax delta trdiff delta tfdiff 22 of 50 ddr3 sdram rev. 1.23 july 2009 unbuffered dimm 13.0 ac & dc output measurement levels 13.1 single-ended ac & dc output levels single ended ac and dc output levels note : 1. the swing of +/-0.1 x v ddq is based on approximately 50% of the static single ended output high or low sw ing with a driver impedance of 40 ? and an effective test load of 25 ? to v tt =v ddq /2. 13.2 differential ac & dc output levels differential ac and dc output levels note : 1. the swing of +/-0.2xv ddq is based on approximately 50% of the static single ended out put high or low swing with a driver impedance of 40 ? and an effective test load of 25 ? to v tt =v ddq /2 at each of the differential outputs. 13.3 single-ended output slew rate with the reference load for timing measur ements, output slew rate for falling and rising edges is defined and measured between v ol (ac) and v oh (ac) for single ended signals as shown in below. single ended output slew rate definition note : output slew rate is verified by design and char acterization, and may not be subject to production test. single ended output slew rate description : sr : slew rate q : query output (like in dq, whic h stands for data-in, query-output se : singe-ended signals for ron = rzq/7 setting symbol parameter ddr3-1066/1333 units notes v oh (dc) dc output high measurement level (for iv curve linearity) 0.8 x v ddq v v om (dc) dc output mid measurement level (for iv curve linearity) 0.5 x v ddq v v ol (dc) dc output low measurement level (for iv curve linearity) 0.2 x v ddq v v oh (ac) ac output high measurement level (for output sr) v tt + 0.1 x v ddq v1 v ol (ac) ac output low measurement level (for output sr) v tt - 0.1 x v ddq v1 symbol parameter ddr3-1066/1333 units notes v ohdiff (ac) ac differential output high measurement level (for output sr) +0.2 x v ddq v1 v oldiff (dc) ac differential output low measurement level (for output sr) -0.2 x v ddq v1 description measured defined by from to single ended output slew rate for rising edge v ol (ac) v oh (ac) v oh (ac)-v ol (ac) delta trse single ended output slew rate for falling edge v oh (ac) v ol (ac) v oh (ac)-v ol (ac) delta tfse parameter symbol ddr3-1066 ddr3-1333 units min max min max single ended output slew rate srqse 2.5 5 2.5 5 v/ns v oh(ac) v ol(ac) delta trse delta tfse figure 7. single ended output slew rate definition v tt 23 of 50 ddr3 sdram rev. 1.23 july 2009 unbuffered dimm 13.4 differential output slew rate with the reference load for timing measurements, output slew rate for falling and rising edges is defined and measured between v oldiff (ac) and v ohdiff (ac) for differential signals as shown in below. differential output slew rate definition note : output slew rate is verified by design and char acterization, and may not be subject to production test. differential output slew rate description : sr : slew rate q : query output (like in dq, whic h stands for data-in, query-output diff : singe-ended signals description measured defined by from to differential output slew rate for rising edge v oldiff (ac) v ohdiff (ac) v ohdiff (ac)-v oldiff (ac) delta trdiff differential output slew rate for falling edge v ohdiff (ac) v oldiff (ac) v ohdiff (ac)-v oldiff (ac) delta tfdiff parameter symbol ddr3-1066 ddr3-1333 units min max min max differential output slew rate srqse 5 10 5 10 v/ns v ohdiff (ac) v oldiff (ac) delta trdiff delta tfdiff figure 8. differential outp ut slew rate definition v tt 24 of 50 ddr3 sdram rev. 1.23 july 2009 unbuffered dimm 14.0 idd specificat ion definition symbol description idd0 operating one bank active-precharge current cke: high; external clock: on; tck, nrc, nras, cl: ac timing table ; bl : 8 a) ; al : 0; cs : high between act and pre; command, address, bank address inputs: partially toggling ; data io: floating; dm: stable at 0; bank activity: cycling with one bank active at a time: 0,0,1,1,2,2,... ; output buffer and rtt: enabled in mode registers b) ; odt signal: stable at 0 idd1 operating one bank active-read-precharge current cke: high; external clock: on; tck, nrc, nras, nrcd, cl: ac timing table ; bl : 8 a) ; al : 0; cs : high between act, rd and pre; command, address, bank address inputs, data io: partially toggling ; dm: stable at 0; bank activity: cycling with one bank active at a time: 0,0,1,1,2,2,... ; output buffer and rtt: enabled in mode registers b) ; odt signal: stable at 0; idd2n precharge standby current cke: high; external clock: on; tck, cl: ac timing table ; bl: 8 a) ; al: 0; cs : stable at 1; command, address, bank address inputs: partially toggling ; data io: floating; dm: stable at 0; bank activity: all banks closed; output buffer and rtt: enabled in mode registers b) ; odt signal: stable at 0 dd2nt precharge standby odt current cke: high; external clock: on; tck, cl : ac timing table ; bl: 8 a) ; al: 0; cs : stable at 1; command, address, bank address inputs: partially toggling ; data io: floating; dm: stable at 0; bank activity: all banks closed; output buffer and rtt: enabled in mode registers b) ; odt signal: toggling ddq2nt (optional) precharge standby odt iddq current same definition like for idd2nt, however measuring iddq current instead of idd current idd2p0 precharge power-down current slow exit cke: low; external clock: on; tck, cl: ac timing table ; bl: 8 a) ; al: 0; cs : stable at 1; command, address, bank address inputs: stable at 0; data io: floating; dm: stable at 0; bank activity: all banks closed; output buffer and rtt: enabled in mode registers b) ; odt signal: stable at 0; precharge power down mode: slow exit c) idd2p1 precharge power-down current fast exit cke: low; external clock: on; tck, cl: ac timing table ; bl: 8 a) ; al: 0; cs : stable at 1; command, address, bank address inputs: stable at 0; data io: floating; dm: stable at 0; bank activity: all banks closed; output buffer and rtt: enabled in mode registers b) ; odt signal: stable at 0; pecharge power down mode: fast exit c) idd2q precharge quiet standby current cke: high; external clock: on; tck, cl: ac timing table ; bl: 8 a) ; al: 0; cs : stable at 1; command, address, bank address inputs: stable at 0; data io: floating; dm: stable at 0; bank activity: all banks closed; output buffer and rtt: enabled in mode registers b) ; odt signal: stable at 0 idd3n active standby current cke: high; external clock: on; tck, cl: ac timing table ; bl: 8 a) ; al: 0; cs : stable at 1; command, address, bank address inputs: partially toggling according to table 34 ; data io: floating; dm: stable at 0; bank activity: all banks open; output buffer and rtt: enabled in mode registers b) ; odt sig- nal: stable at 0 idd3p active power-down current cke: low; external clock: on; tck, cl: ac timing table ; bl: 8 a) ; al: 0; cs : stable at 1; command, address, bank address inputs: stable at 0; data io: floating; dm :stable at 0; bank activity: all banks open; output buffer and rtt: enabled in mode registers b) ; odt signal: stable at 0 idd4r operating burst read current cke: high; external clock: on; tck, cl: ac timing table ; bl: 8 a) ; al: 0; cs : high between rd; command, address, bank address inputs: partially tog- gling ; data io: seamless read data burst with different data between one burst and the next one according to table 36 ; dm: stable at 0; bank activity: all banks open, rd commands cycling through banks: 0,0,1,1,2,2,... (see table 7 on page 10); output buffer and rtt: enabled in mode registers b) ; odt signal: stable at 0 iddq4r (optional) operating burst read iddq current same definition like for idd4r, however measuring iddq current instead of idd current idd4w operating burst write current cke: high; external clock: on; tck, cl: ac timing table ; bl: 8 a) ; al: 0; cs : high between wr; command, address, bank address inputs: partially tog- gling ; data io: seamless write data burst with different data between one burst and the next one ; dm: stable at 0; bank activity: all banks open, wr com- mands cycling through banks: 0,0,1,1,2,2,... ; output buffer and rtt: enabled in mode registers b) ; odt signal: stable at high idd5b burst refresh current cke: high; external clock: on; tck, cl, nrfc: ac timing table ; bl: 8 a) ; al: 0; cs : high between ref; command, address, bank address inputs: par- tially toggling according to table 38 ; data io: floating; dm: stable at 0; bank activity: ref command every nrfc (see table 38); output buffer and rtt: enabled in mode registers b) ; odt signal: stable at 0 idd6 self refresh current: normal temperature range tcase: 0 - 85c; auto self-refresh (asr): disabled d) ; self-refresh temperature range (srt): n ormal e) ; cke: low; external clock: off; ck and ck : low; cl: ac timing table ; bl: 8 a) ; al: 0; cs , command, address, bank address, data io: floating; dm: stable at 0; bank activity: self-refresh opera- tion; output buffer and rtt: enabled in mode registers b) ; odt signal: floating 25 of 50 ddr3 sdram rev. 1.23 july 2009 unbuffered dimm a) burst length: bl8 fixed by mrs: set mr0 a[1,0]=00b b) output buffer enable: set mr1 a[12] = 0b; set mr1 a[5,1] = 01b; rtt_nom enable: set mr1 a[9,6,2] = 011b; rtt_wr enable: set mr2 a[10,9] = 10b c) precharge power down mode: set mr0 a12=0b for slow exit or mr0 a12=1b for fast exit d) auto self-refresh (asr): set mr2 a6 = 0b to disable or 1b to enable feature e) self-refresh temperature range (srt): set mr2 a7=0b for normal or 1b for extended temperature range f) refer to dram supplier data sheet and/or dimm spd to determine if optional features or requirements are supported by ddr3 sd ram device g) idd current measure method and detail patterns are described on ddr3 component datasheet symbol description idd6et self-refresh current: extended temperature range (optional) f) tcase: 0 - 95c; auto self-refresh (asr): disabled d) ; self-refresh temperature range (srt): extended e) ; cke: low; external clock: off; ck and ck : low; cl: ac timing table ; bl: 8 a) ; al: 0; cs , command, address, bank address, data io: floating; dm: stable at 0; bank activity: extended tempera- ture self-refresh operation; output buffer and rtt: enabled in mode registers b) ; odt signal: floating idd6tc auto self-refresh current (optional) f) tcase: 0 - 95c; auto self-refresh (asr): enabled d) ; self-refresh temperature range (srt): normal e) ; cke: low; external clock: off; ck and ck : low; cl: ac timing table ; bl: 8 a) ; al: 0; cs , command, address, bank address, data io: floating; dm: stable at 0; bank activity: auto self-refresh operation; output buffer and rtt: enabled in mode registers b) ; odt signal: floating idd7 operating bank interleave read current cke: high; external clock: on; tck, nrc, nras, nrcd, nrrd, nfaw, cl: ac timing table; bl: 8 a) ; al: cl-1; cs : high between act and rda; com- mand, address, bank address inputs: partially toggling ; data io: read data bursts with different data between one burst and the next one ; dm: stable at 0; bank activity: two times interleaved cycling through banks (0, 1, ...7) with different addressing, see table 39 ; output buffer and rtt: enabled in mode reg- isters b) ; odt signal: stable at 0 26 of 50 ddr3 sdram rev. 1.23 july 2009 unbuffered dimm 14.1 idd spec table m378b6474dz1 : 512mb(64mx64) module m378b2873dz1 : 1gb(128mx64) module symbol f8 (ddr3-1066@cl=7) h9 (ddr3-1333@cl=9) unit notes idd0 360 400 ma idd1 500 540 ma idd2p0(slow exit) 44 48 ma idd2p1(fast exit) 180 200 ma idd2n 220 240 ma idd2q 220 240 ma idd3p(fast exit) 180 200 ma idd3n 240 260 ma idd4r 920 1160 ma idd4w 940 1160 ma idd5b 840 880 ma idd6 40 40 ma idd7 1240 1480 ma symbol f8 (ddr3-1066@cl=7) h9 (ddr3-1333@cl=9) unit notes idd0 680 720 ma idd1 840 880 ma idd2p0(slow exit) 88 96 ma idd2p1(fast exit) 360 400 ma idd2n 440 480 ma idd2q 440 480 ma idd3p(fast exit) 360 400 ma idd3n 480 520 ma idd4r 1360 1640 ma idd4w 1520 1840 ma idd5b 1680 1760 ma idd6 80 80 ma idd7 2200 2920 ma 27 of 50 ddr3 sdram rev. 1.23 july 2009 unbuffered dimm m378b5673dz1: 2gb(256mx64) module m391b2873dz1: 1gb(128mx72) module symbol f8 (ddr3-1066@cl=7) h9 (ddr3-1333@cl=9) unit notes idd0 1120 1200 ma idd1 1280 1360 ma idd2p0(slow exit) 176 192 ma idd2p1(fast exit) 720 800 ma idd2n 880 960 ma idd2q 880 960 ma idd3p(fast exit) 720 800 ma idd3n 920 1000 ma idd4r 1800 2120 ma idd4w 1960 2320 ma idd5b 2120 2240 ma idd6 160 160 ma idd7 2640 3400 ma symbol f8 (ddr3-1066@cl=7) h9 (ddr3-1333@cl=9) unit notes idd0 765 810 ma idd1 945 990 ma idd2p0(slow exit) 100 108 ma idd2p1(fast exit) 405 450 ma idd2n 495 540 ma idd2q 495 540 ma idd3p(fast exit) 405 450 ma idd3n 540 585 ma idd4r 1530 1845 ma idd4w 1710 2070 ma idd5b 1890 1980 ma idd6 90 90 ma idd7 2475 3285 ma 28 of 50 ddr3 sdram rev. 1.23 july 2009 unbuffered dimm m391b5673dz1 : 2gb(256mx72) module symbol f8 (ddr3-1066@cl=7) h9 (ddr3-1333@cl=9) unit notes idd0 1260 1350 ma idd1 1440 1530 ma idd2p0(slow exit) 200 220 ma idd2p1(fast exit) 810 900 ma idd2n 990 1080 ma idd2q 990 1080 ma idd3p(fast exit) 810 900 ma idd3n 1035 1125 ma idd4r 2025 2385 ma idd4w 2205 2610 ma idd5b 2385 2520 ma idd6 180 180 ma idd7 2970 3825 ma 29 of 50 ddr3 sdram rev. 1.23 july 2009 unbuffered dimm 15.0 input/output capacitance 15.1 non ecc udimm 15.2 ecc udimm m378b6474dz1 parameter symbol ddr3-1066 ddr3-1333 units notes min max min max input/output capacitance (dq, dm, dqs, dqs , tdqs, tdqs ) cio - tbd - tbd pf input capacitance (ck and ck) cck - tbd - tbd pf input capacitance (all other input-only pins) ci - tbd - tbd pf input/output capacitance of zq pin czq - tbd - tbd pf m378b2873dz1 parameter symbol ddr3-1066 ddr3-1333 units notes min max min max input/output capacitance (dq, dm, dqs, dqs , tdqs, tdqs ) cio - tbd - tbd pf input capacitance (ck and ck) cck - tbd - tbd pf input capacitance (all other input-only pins) ci - tbd - tbd pf input/output capacitance of zq pin czq - tbd - tbd pf m378b5673dz1 parameter symbol ddr3-1066 ddr3-1333 units notes min max min max input/output capacitance (dq, dm, dqs, dqs , tdqs, tdqs ) cio - tbd - tbd pf input capacitance (ck and ck) cck - tbd - tbd pf input capacitance (all other input-only pins) ci - tbd - tbd pf input/output capacitance of zq pin czq - tbd - tbd pf m391b2873dz1 parameter symbol ddr3-1066 ddr3-1333 units notes min max min max input/output capacitance (dq, dm, dqs, dqs , tdqs, tdqs ) cio - tbd - tbd pf input capacitance (ck and ck) cck - tbd - tbd pf input capacitance (all other input-only pins) ci - tbd - tbd pf input/output capacitance of zq pin czq - tbd - tbd pf m391b5673dz1 parameter symbol ddr3-1066 ddr3-1333 units notes min max min max input/output capacitance (dq, dm, dqs, dqs , tdqs, tdqs ) cio - tbd - tbd pf input capacitance (ck and ck) cck - tbd - tbd pf input capacitance (all other input-only pins) ci - tbd - tbd pf input/output capacitance of zq pin czq - tbd - tbd pf 30 of 50 ddr3 sdram rev. 1.23 july 2009 unbuffered dimm 16.0 electrical character istics and ac timing (0 c 32 of 50 ddr3 sdram rev. 1.23 july 2009 unbuffered dimm 17.0 timing parameters by speed grade speed ddr3-1066 ddr3-1333 units note parameter symbol min max min max clock timing minimum clock cycle time (dll off mode) tck(dll_of f) 8 - 8 - ns 6 average clock period tck(avg) see speed bins table ps clock period tck(abs) tck(avg)min + tjit(per)min tck(avg)max + tjit(per)max tck(avg)min + tjit(per)min tck(avg)max + tjit(per)max ps average high pulse width tch(avg) 0.47 0.53 0.47 0.53 tck(avg) average low pulse width tcl(avg) 0.47 0.53 0.47 0.53 tck(avg) clock period jitter tjit(per) -90 90 -80 80 ps clock period jitter during dll locking period tjit(per, lck) -80 80 -70 70 ps cycle to cycle period jitter tjit(cc) 180 160 ps cycle to cycle period jitter during dll locking period tjit(cc, lck) 160 140 ps cumulative error across 2 cycles terr(2per) - 132 132 - 118 118 ps cumulative error across 3 cycles terr(3per) - 157 157 - 140 140 ps cumulative error across 4 cycles terr(4per) - 175 175 - 155 155 ps cumulative error across 5 cycles terr(5per) - 188 188 - 168 168 ps cumulative error across 6 cycles terr(6per) - 200 200 - 177 177 ps cumulative error across 7 cycles terr(7per) - 209 209 - 186 186 ps cumulative error across 8 cycles terr(8per) - 217 217 - 193 193 ps cumulative error across 9 cycles terr(9per) - 224 224 - 200 200 ps cumulative erro r across 10 cycles terr(10per) - 231 231 - 205 205 ps cumulative erro r across 11 cycles terr(11per) - 237 237 - 210 210 ps cumulative erro r across 12 cycles terr(12per) - 242 242 - 215 215 ps cumulative error across n = 13, 14 ... 49, 50 cycles terr(nper) terr(nper)min = (1 + 0.68ln(n))*tjit(per)min terr(nper)max = (1 = 0.68ln(n))*tjit(per)max ps 24 absolute clock high pulse width tch(abs) 0.43 - 0.43 - tck(avg) 25 absolute clock low pulse width tcl(abs) 0.43 - 0.43 - tck(avg) 26 data timing dqs,dqs to dq skew, per group, per access tdqsq - 150 - 125 ps 13 dq output hold time from dqs, dqs tqh 0.38 - 0.38 - tck(avg) 13, g dq low-impedance time from ck, ck tlz(dq) -600 300 -500 250 ps 13,14, f dq high-impedance time from ck, ck thz(dq) - 300 - 250 ps 13,14, f data setup time to dqs, dqs referenced to v ih (ac)v il (ac) levels tds(base) 25 - 30 - ps d, 17 data hold time to dqs, dqs referenced to v ih (ac)v il (ac) levels tdh(base) 100 - 65 - ps d, 17 dq and dm input pulse width for each input tdipw 490 - 400 - ps 28 data strobe timing dqs, dqs read preamble trpre 0.9 note 19 0.9 note 19 tck 13, 19, g dqs, dqs differential read postamble trpst 0.3 note 11 0.3 note 11 tck 11, 13, b dqs, dqs output high time tqsh 0.38 - 0.4 - tck(avg) 13, g dqs, dqs output low time tqsl 0.38 - 0.4 - tck(avg) 13, g dqs, dqs write preamble twpre 0.9 - 0.9 - tck dqs, dqs write postamble twpst 0.3 - 0.3 - tck dqs, dqs rising edge output access time from rising ck, ck tdqsck -300 300 -255 255 ps 13,f dqs, dqs low-impedance time (referenced from rl-1) tlz(dqs) -600 300 -500 250 ps 13,14,f dqs, dqs high-impedance time (referenced from rl+bl/2) thz(dqs) - 300 - 250 ps 12,13,14 dqs, dqs differential input low pulse width tdqsl 0.45 0.55 0.45 0.55 tck 29, 31 dqs, dqs differential input high pulse width tdqsh 0.45 0.55 0.45 0.55 tck 30, 31 dqs, dqs rising edge to ck, ck rising edge tdqss -0.25 0.25 -0.25 0.25 tck(avg) c dqs,dqs falling edge setup time to ck, ck rising edge tdss 0.2 - 0.2 - tck(avg) c, 32 dqs,dqs falling edge hold time to ck, ck rising edge tdsh 0.2 - 0.2 - tck(avg) c, 32 33 of 50 ddr3 sdram rev. 1.23 july 2009 unbuffered dimm speed ddr3-1066 ddr3-1333 units note parameter symbol min max min max command and address timing dll locking time tdllk 512 - 512 - nck internal read command to precharge command delay trtp max (4nck,7.5ns) - max (4nck,7.5ns) - e delay from start of internal write transaction to internal read command twtr max (4nck,7.5ns) - max (4nck,7.5ns) - e,18 write recovery time twr 15 - 15 - ns e mode register set command cycle time tmrd 4 - 4 - nck mode register set command update delay tmod max (12nck,15ns) - max (12nck,15ns) - cas# to cas# command delay tccd 4 - 4 - nck auto precharge write recovery + precharge time tdal(min) wr + roundup (trp / tck(avg)) nck multi-purpose register recovery time tmprr 1 - 1 - nck 22 active to precharge command period tras see " speed bins and cl, trcd, trp, trc and tras for corresponding bin" ns e active to active command period for 1kb page size trrd max (4nck,7.5ns) - max (4nck,6ns) - e active to active command period for 2kb page size trrd max (4nck,10ns) - max (4nck,7.5ns) - e four activate window for 1kb page size tfaw 37.5 - 30 - ns e four activate window for 2kb page size tfaw 50 - 45 - ns e command and address setup time to ck, ck referenced to v ih (ac) / v il (ac) levels tis(base) 125 - 65 - ps b,16 command and address hold time from ck, ck referenced to v ih (ac) / v il (ac) lev- els tih(base) 200 - 140 - ps b,16 command and address setup time to ck, ck referenced to v ih (ac) / v il (ac) levels tis(base) ac150 125 + 150 - 65+125 - ps b,16,27 control & address input pulse width for each input tipw 780 - 620 - ps 28 calibration timing power-up and reset calibration time tzqiniti 512 - 512 - nck normal operation full calibration time tzqoper 256 - 256 - nck normal operation short calibration time tzqcs 64 - 64 - nck 23 reset timing exit reset from cke high to a valid command txpr max(5nck, trfc + 10ns) - max(5nck, trfc + 10ns) - self refresh timing exit self refresh to commands not requiring a locked dll txs max(5nck,trfc + 10ns) - max(5nck,trfc + 10ns) - exit self refresh to commands requiring a locked dll txsdll tdllk(min) - tdllk(min) - nck minimum cke low width for self refresh entry to exit timing tckesr tcke(min) + 1tck - tcke(min) + 1tck - valid clock requirement after self refresh entry (sre) or power-down entry (pde) tcksre max(5nck, 10ns) - max(5nck, 10ns) - valid clock requirement before self refresh exit (srx) or power-down exit (pdx) or reset exit tcksrx max(5nck, 10ns) - max(5nck, 10ns) - 34 of 50 ddr3 sdram rev. 1.23 july 2009 unbuffered dimm speed ddr3-1066 ddr3-1333 units note parameter symbol min max min max power down timing exit power down with dll on to any valid command;exit precharge power down with dll frozen to commands not requiring a locked dll txp max (3nck, 7.5ns) - max (3nck,6ns) - exit precharge power down with dll frozen to commands requiring a locked dll txpdll max (10nck, 24ns) - max (10nck, 24ns) - 2 cke minimum pulse width tcke max (3nck, 5.625ns) - max (3nck, 5.625ns) - command pass disable delay tcpded 1 - 1 - nck power down entry to exit timing tpd tcke(min) 9*trefi tcke(min) 9*trefi tck 15 timing of act command to power down entry tactpden 1 - 1 - nck 20 timing of pre command to power down entry tprpden 1 - 1 - nck 20 timing of rd/rda command to power down entry trdpden rl + 4 +1 - rl + 4 +1 - timing of wr command to power down entry (bl8otf, bl8mrs, bl4otf) twrpden wl + 4 +(twr/ tck(avg)) - wl + 4 +(twr/ tck(avg)) - nck 9 timing of wra command to power down entry (bl8otf, bl8mrs, bl4otf) twrapden wl + 4 +wr +1 - wl + 4 +wr +1 - nck 10 timing of wr command to power down entry (bl4mrs) twrpden wl + 2 +(twr/ tck(avg)) - wl + 2 +(twr/ tck(avg)) - nck 9 timing of wra command to power down entry (bl4mrs) twrapden wl +2 +wr +1 - wl +2 +wr +1 - nck 10 timing of ref command to power down entry trefpden 1 - 1 - 20,21 timing of mrs command to power down entry tmrspden tmod(min) - tmod(min) - odt timing odt high time without write command or with write command and bc4 odth4 4 - 4 - nck odt high time with write command and bl8 odth8 6 - 6 - nck asynchronous rtt turn-on delay (power-down with dll frozen) taonpd 2 8.5 2 8.5 ns asynchronous rtt turn-off delay (power-down with dll frozen) taofpd 2 8.5 2 8.5 ns odt turn-on taon -300 300 -250 250 ps 7,f rtt_nom and rtt_wr turn-off time from odtloff reference taof 0.3 0.7 0.3 0.7 tck(avg) 8,f rtt dynamic change skew tadc 0.3 0.7 0.3 0.7 tck(avg) f write leveling timing first dqs pulse rising edge after tdqss margining mode is programmed twlmrd 40 - 40 - tck 3 dqs/dqs delay after tdqs margining mode is programmed twldqsen 25 - 25 - tck 3 setup time for tdqss latch twls 245 - 195 - ps write leveling hold time from rising dqs, dqs crossing to rising ck, ck cross- ing twlh 245 - 195 - ps write leveling output delay twlo 0 9 0 9 ns write leveling output error twloe 0 2 0 2 ns 35 of 50 ddr3 sdram rev. 1.23 july 2009 unbuffered dimm 17.1 jitter notes specific note a unit ?tck(avg)? represents the actual tck(avg) of the input clock under operation. unit ?nck? represents one clock cycle of th e input clock, counting the actual clock edges.ex) tmrd = 4 [nck] means; if one mode register set command is registered at tm, another mode register set command may be registered at tm+4, even if (tm+4 - tm) is 4 x tck(avg) + terr(4per),min. specific note b these parameters are measured from a command/address signal (cke, cs , ras , cas , we , odt, ba0, a0, a1, etc.) transition edge to its respective clock signal (ck/ck ) crossing. the spec values are not affected by the amount of clock jitter applied (i.e. tjit(per), tjit(cc), etc.), as the setup and hold are relative to the clo ck signal crossing that latches the command/address. that is, the se param- eters should be met whether clock jitter is present or not. specific note c these parameters are measured from a data strobe signal (dqs(l/u), dqs (l/u)) crossing to its res pective clock signal (ck, ck ) cross- ing. the spec values are not affected by the amount of clock jitter applied (i.e. tjit(per), tj it(cc), etc.), as these are rela tive to the clock signal crossing. that is, t hese parameters should be met whet her clock jitter is present or not. specific note d these parameters are measured from a data signal (dm(l/u), dq(l/u)0, dq(l/u)1, etc.) transition edge to its respective data strobe signal (dqs(l/u), dqs (l/u)) crossing. specific note e for these parame ters, the ddr3 sdram device supports tnparam [nck] = ru{ tparam [ns] / tck(avg) [ns] }, which is in clock cycles, assuming all input clo ck jitter specifications are satisfied. for example, the device will support tnrp = ru{trp / tck(avg) }, which is in clock cycles , if all input clock jitter specifications are met. this means: for ddr3-800 6-6-6, of which trp = 15ns, the device will support tnrp = ru{trp / tck(avg)} = 6, as long as the input clock jitter s pecifi- cations are met, i.e. precharge command at tm and active command at tm+6 is valid even if (tm+6 - tm) is less than 15ns due to input clock jitter. specific note f when the device is operated with input clock jitter, this parameter needs to be derated by the actual terr(mper),act of the input clock, where 2 <= m <= 12. (output deratings are relative to the sdram input clock.) for example, if the measured jitter into a ddr3-800 sdram has terr(mper),act,min = - 172 ps and terr(mper),act,max = + 193 ps, then tdqsck,min(derated) = tdqsck,min - terr(mper),act,max = - 400 ps - 193 ps = - 593 ps and tdqsck,max(derated) = tdqsck,max - terr(mper),act,min = 400 ps + 172 ps = + 572 ps. simi larly, tlz(dq) for ddr3-800 derat es to tlz(dq),min(derated) = - 800 ps - 193 ps = - 993 ps and tlz(dq),max(derated) = 400 ps + 172 ps = + 572 ps. (caution on the min/max usage!) note that terr(mper),act,min is the minimu m measured value of terr(nper) where 2 <= n <= 12, and terr(mper),act,max is the maximum measured value of terr(nper) where 2 <= n <= 12. specific note g when the device is operated with input cl ock jitter, this parameter needs to be derat ed by the actual tjit(per),act of the in put clock. (out- put deratings are relative to the sdram input clock.) for example, if the measured ji tter into a ddr3-800 sdram has tck(avg),ac t = 2500 ps, tjit(per),act,min = - 72 ps and tjit(per),act,max = + 93 ps, then trpre,min(derated) = trpre,min + tjit(per),act,min = 0.9 x tck(avg),act + tjit(per),act,min = 0.9 x 2500 ps - 72 ps = + 2178 ps. similarly, tqh,min(derated) = tqh,min + tjit(per),act,m in = 0.38 x tck(avg),act + tjit(per),act,min = 0.38 x 2500 ps - 72 ps = + 878 ps. (caution on the min/max usage!) 36 of 50 ddr3 sdram rev. 1.23 july 2009 unbuffered dimm 17.2 timing parameter notes 1. actual value dependant upon measurement level definitions which are tbd. 2. commands requiring a locked dll are: read (and rap) and synchronous odt commands. 3. the max values are system dependent. 4. wr as programmed in mode register 5. value must be rounded-up to next higher integer value 6. there is no maximum cycle time limit besides the need to satisfy the refresh interval, trefi. 7. for definition of rtt turn-on time taon see "device operation" 8. for definition of rtt turn-off time taof see "device operation". 9. twr is defined in ns, for calculation of twrpden it is necessary to round up twr / tck to the next integer. 10. wr in clock cycles as programmed in mr0 11. the maximum read postamble is bound by tdqsck(min) plus tqsh(min) on the left side and thz(dqs)max on the right side. see d evice operation datasheet 12. output timing deratings are relative to the sdram input clock. when the device is operated with input clock jitter, this pa rameter needs to be derated by tbd 13. value is valid for ron34 14. single ended signal parameter. 15. trefi depends on t oper 16. tis(base) and tih(base) values are for 1v/ns cmd/add single-ended slew rate and 2v/ns ck, ck differential slew rate, note for dq and dm signals, v ref (dc) = v ref dq(dc). for input only pins except reset, v ref (dc)=v ref ca(dc). see "address/ command setup, hold and derating" 17. tds(base) and tdh(base) values are for 1v/ns dq single-ended slew rate and 2v/ns dqs, dqs differential slew rate. note for dq and dm signals, v ref (dc)= v ref dq(dc). for input only pins except reset , v ref (dc)=v ref ca(dc). see "data setup, hold and slew rate derating". 18. start of internal write transaction is defined as follows ; for bl8 (fixed by mrs and on-the-fly) : rising clock edge 4 clock cycles after wl. for bc4 (on-the-fly) : rising clock edge 4 clock cycles after wl for bc4 (fixed by mrs) : rising clock edge 2 clock cycles after wl 19. the maximum read preamble is bound by tlzdqs(min) on the left side and tdqsck(max) on the right side. see "device operation " 20. cke is allowed to be registered low while operations such as row activation, precharge, autoprecharge or refresh are in pro gress, but power-down idd spec will not be applied until finishing those operations. 21. although cke is allowed to be registered low after a refresh command once trefpden(min) is satisfied, there are cases where additional time such as txpdll(min) is also required. see "device operation". 22. defined between end of mpr read burst and mrs which reloads mpr or disables mpr function. 23. one zqcs command can effectively correct a minimum of 0.5 % (zqcorrection) of ron and rtt impedance error within 64 nck for all speed bins assuming the maximum sensitivities specified in the ?output driver voltage and temperature sensitivity? and ?odt voltage and temperature sensitivity? tables. the appropriate interval between zqcs commands can be determined from these tables and other application specific parameters. one method for calculating the interval between zqcs commands, given the temperature (tdriftrate) and voltage (vdriftrate) drift rates that the sdram is sub- ject to in the application, is illustrated. the interval could be defined by the following formula: where tsens = max(drttdt, drondtm) and vsens = max(drttdv, drondvm) define the sdram temperature and voltage sensitivities. for example, if tsens = 1.5% / c, vsens = 0.15% / mv, tdriftrate = 1 c / sec and vdriftrate = 15 mv / sec, then the interval between zqcs commands is calcu- lated as: 24. n = from 13 cycles to 50 cycles. this row defines 38 parameters. 25. tch(abs) is the absolute instantaneous clock high pulse width, as measured from one rising edge to the following falling ed ge. 26. tcl(abs) is the absolute instantaneous clock low pulse width, as measured from one falling edge to the following rising edg e. 27. the tis(base) ac150 specifications are adjusted from the tis(base) specification by adding an additional 100 ps of derating to accommodate for the lower alter- nate threshold of 150 mv and another 25 ps to account for the earlier reference point [(175 mv - 150 mv) / 1 v/ns]. 28. pulse width of a input signal is defined as the width between the first crossing of v ref (dc) and the consecutive crossing of v ref (dc) 29. tdqsl describes the instantaneous differential input low pulse width on dqs-dqs , as measured from one falling edge to the next consecutive rising edge. 30. tdqsh describes the instantaneous differential input high pulse width on dqs-dqs , as measured from one rising edge to the next consecutive falling edge. 31. tdqsh, act + tdqsl, act = 1 tck, act ; with txyz, act being the actual measured value of the respective timing parameter in the application. 32. tdsh, act + tdss, act = 1 tck, act ; with txyz, act being the actual measured value of the respective timing parameter in t he application. zqcorrection (tsens x tdriftrate) + (vsens x vdriftrate) 0.5 (1.5 x 1) + (0.15 x 15) = 0.133 ~ ~ 128ms 37 of 50 ddr3 sdram rev. 1.23 july 2009 unbuffered dimm 17.3 address / command setup, hold and derating for all input signals the total tis (setup time) and tih (hold ti me) required is calculated by adding the data sheet tis(base) and tih(base) value to the ? tis and ? tih derating value respectively. example: tis (total setup time) = tis(base) + ? tis setup (tis) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of v ref (dc) and the first crossing of v ih (ac)min. setup (tis) nominal slew rate for a falling signal is defined as the slew rate between the last crossing of v ref (dc) and the first crossing of v il (ac)max. if the actual signal is alwa ys earlier than the nominal slew rate line between shaded ?v ref (dc) to ac region?, use nominal slew rate for derating value. if the ac tual signal is later than t he nominal slew rate line any - where between shaded ?v ref (dc) to ac region?, the slew rate of a tangent line to the act ual signal from the ac level to dc level is used for derating val ue. hold (tih) nominal slew rate for a rising signal is def ined as the slew rate between the last crossing of v il (dc)max and the first crossing of v ref (dc). hold (tih) nominal slew rate for a falling signal is defined as the slew rate between the last crossing of v ih (dc)min and the first crossing of v ref (dc). if the actual signal is always later than the nominal slew rate line between shaded ?dc to v ref (dc) region?, use nominal slew rate for derating value (see figure 9). if the actual signal is earlier than the nom inal slew rate line anywhere between shaded ?dc to v ref (dc) region?, the slew rate of a tangent line to the actual signal from the dc level to v ref (dc) level is used for derating value. for a valid transition the input si gnal has to remain above/below v ih/il (ac) for some time tvac. although for slow slew rates the total setup time might be negative (i.e. a valid inpu t signal will not have reached v ih/il (ac) at the time of the rising clock transition) a valid input signal is still requi red to complete the transition and reach v ih/il (ac). for slew rates in between the values listed in table below , the derating values may obtained by linear interpolation. these values are typically not subj ect to production test. they are ve rified by design and characterization. add/cmd setup and hold base-values for 1v/ns note : ac/dc referenced for 1v/ns dq-s lew rate and 2v/ns dqs slew rate note : the tis(base)-ac150 specifications are further adjusted to add an additional 100p s of derating to accommodate for the lo wer alternate thresh-old of 150mv and another 25ps to account for the earlier reference point [(175mv-150mv)/1 v/ns]. derating values ddr3-1066/1333 tis/tih-ac/dc based [ps] ddr3-1066 ddr3-1333 reference tis(base) 125 65 v ih/l (ac) tih(base) 200 140 v ih/l (dc) tis(base)-ac150 125 + 150 65+125 v ih/l (ac) ? tis, ? tih derating [ps] ac/dc based ac175 threshold -> v ih (ac) = v ref (dc) + 175mv, v il (ac) = v ref (dc) - 175mv clk,clk differential slew rate 4.0 v/ns 3.0 v/ns 2.0 v/ns 1.8 v/ns 1.6 v/ns 1.4v/ns 1.2v/ns 1.0v/ns ? tis ? tih ? tis ? tih ? tis ? tih ? tis ? tih ? tis ? tih ? tis ? tih ? tis ? tih ? tis ? tih cmd/ add slew rate v/ns 2.0 88 50 88 50 88 50 96 58 104 66 112 74 120 84 128 100 1.559345934593467427550835891689984 1.0000000881616242432344050 0.9-2 -4 -2 -4 -2 -4 6 4 1412202030303846 0.8-6-10-6-10-6-10 2 -2 10 6 131426243440 0.7 -11 -16 -11 -16 -11 -16 -3 -8 5 0 13 8 21 18 29 34 0.6 -17 -26 -17 -26 -17 -26 -9 -18 -1 -10 7 -2 15 8 23 24 0.5 -35 -40 -35 -40 -35 -40 -27 -32 -19 -24 -11 -16 -2 -6 5 10 0.4 -62 -60 -62 -60 -62 -60 -54 -52 -46 -44 -38 -36 -30 -26 -22 -10 38 of 50 ddr3 sdram rev. 1.23 july 2009 unbuffered dimm derating values ddr3-1333/1600 tis/tih-ac/dc based - alternate ac150 threshold required time t vac above v ih (ac) {blow v il (ac)} for valid transition ? tis, ? tih derating [ps] ac/dc based alternate ac150 threshold -> v ih (ac) = v ref (dc) + 150mv, v il (ac) = v ref (dc) - 150mv clk,clk differential slew rate 4.0 v/ns 3.0 v/ns 2.0 v/ns 1.8 v/ns 1.6 v/ns 1.4v/ns 1.2v/ns 1.0v/ns ? tis ? tih ? tis ? tih ? tis ? tih ? tis ? tih ? tis ? tih ? tis ? tih ? tis ? tih ? tis ? tih cmd/ add slew rate v/ns 2.075507550755083589166997410784115100 1.550345034503458426650745882689084 1.0000000881616242432344050 0.9 0 -4 0 -4 0 -4 8 4 1612242032304046 0.8 0 -10 0 -10 0 -10 8 -2 16 6 241432244040 0.70-160-160-168 -816 0 24 8 32184034 0.6 -1 -26 -1 -26 -1 -26 7 -18 15 -10 23 -2 31 8 39 24 0.5 -10 -40 -10 -40 -10 -40 -2 -32 6 -24 14 -16 22 -6 30 10 0.4 -25 -60 -25 -60 -25 -60 -17 -52 -9 -44 -1 -36 7 -26 15 -10 slew rate[v/ns] t vac @175mv [ps] t vac @150mv [ps] min max min max >2.0 75 - 175 - 2.0 57 -170 - 1.5 50 - 167 - 1.0 38 -163 - 0.9 34 - 162 - 0.8 29 -161 - 0.7 22 - 159 - 0.6 13 -155 - 0.5 0 - 150 - < 0.5 0 -150 - 39 of 50 ddr3 sdram rev. 1.23 july 2009 unbuffered dimm v ss ck ck tds tdh setup slew rate setup slew rate rising signal falling signal delta tf delta tr v ref (dc) - v il (ac)max delta tf = v ih (ac)min - v ref (dc) delta tr = v ddq v ih (ac) min v ih (dc) min v ref (dc) v il (dc) max v il (ac) max nominal slew rate nominal slew rate v ref to ac region v ref to ac region figure 9 - illustration of nominal slew rate and tvac fo r setup time tds (for dq with respect to strobe) and tis (for add/cmd with respect to clock). tis tih tds tdh tis tih tvac tvac note :clock and strobe are drawn on a different time scale. dqs dqs 40 of 50 ddr3 sdram rev. 1.23 july 2009 unbuffered dimm v ss ck ck hold slew rate hold slew rate falling signal rising signal delta tr delta tf v ref (dc) - v il (dc)max delta tr = v ih (dc)min - v ref (dc) delta tf = v ddq v ih (ac) min v ih (dc) min v ref (dc) v il (dc) max v il (ac) max nominal slew rate nominal slew rate dc to v ref region dc to v ref region figure 10 - illustration of nominal slew rate for hold time tdh (for dq with respect to strobe) and tih (for add/cmd with respect to clock). tis tih tis tih dc to v ref region note :clock and strobe are drawn on a different time scale. tds tdh tds tdh dqs dqs 41 of 50 ddr3 sdram rev. 1.23 july 2009 unbuffered dimm v ss setup slew rate setup slew rate rising signal falling signal delta tf delta tr tangent line[v ref (dc) - v il (ac)max] delta tf = tangent line[v ih (ac)min - v ref (dc)] delta tr = v ddq v ih (ac) min v ih (dc) min v ref (dc) v il (dc) max v il (ac) max tangent tangent v ref to ac region v ref to ac region line line nominal line nominal line figure 11. illustration of tangent line for setup time tds (for dq with re spect to strobe) and tis (for add/cmd with respect to clock) ck ck tis tih tis tih tvac note :clock and strobe are drawn on a different time scale. tds tdh tds tdh dqs dqs 42 of 50 ddr3 sdram rev. 1.23 july 2009 unbuffered dimm v ss hold slew rate delta tf delta tr tangent line [ v ih (dc)min - v ref (dc) ] delta tf = v ddq v ih (ac) min v ih (dc) min v ref (dc) v il (dc) max v il (ac) max tangent tangent dc to v ref region dc to v ref region line line nominal line nominal line falling signal hold slew rate tangent line [ v ref (dc) - v il (dc)max ] delta tr = rising signal figure 12 - illustration of tangent line for hold time tdh (for dq with re spect to strobe) and tih (for add/cmd with respect to clock) ck ck tis tih tis tih note :clock and strobe are drawn on a different time scale. tds tdh tds tdh dqs dqs 43 of 50 ddr3 sdram rev. 1.23 july 2009 unbuffered dimm 17.4 data setup, hold and slew rate derating: for all input signals the total tds (setup time) and tdh (hold time) required is calculated by adding the data sheet tds(base) and tdh(base) value to the ? tds and ? tdh derating value respectively. example: tds (total setup time) = tds(base) + ? tds. setup (tds) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of v ref (dc) and the first crossing of v ih (ac)min. setup (tds) nominal slew rate for a falling signal is defined as the slew rate between the last crossing of v ref (dc) and the first crossing of v il (ac)max. if the actual signal is always earlier than t he nominal slew rate line between shaded ?v ref (dc) to ac region?, use nominal sl ew rate for derating value. if the actual signal is later than the nominal slew rate line anywhere between shaded ?v ref (dc) to ac region?, the slew rate of a tangent line to the act ual signal from the ac level to dc level is used for derating val ue. hold (tdh) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of v il (dc)max and the first crossing of v ref (dc). hold (tdh) nominal slew rate for a falling signal is def ined as the slew rate between the last crossing of v ih (dc)min and the first crossing of v ref (dc). if the actual signal is always later than the nomi nal slew rate line between shaded ?dc level to v ref (dc) region?, use nominal slew rate for derating value. if the actual signal is earlier than the nominal slew rate line anywhere between shaded ?dc to v ref (dc) region?, the slew rate of a tangent line to the actual signal from the dc level to v ref (dc) level is used for derating value. for a valid transition the input si gnal has to remain above/below v ih/il (ac) for some time tvac. although for slow slew rates the total setup time might be negative (i.e. a valid inpu t signal will not have reached v ih/il (ac) at the time of the rising clock transition) a valid input signal is still requi red to complete the transition and reach v ih/il (ac). for slew rates in between the values listed in the tables the derating values may obtained by linear interpolation. these values are typically not subj ect to production test. they are ve rified by design and characterization data setup and hold base-value note : ac/dc referenced for 1v/ns dq-slew rate and 2 v/ns dqs slew rate) derating values ddr3-1066/1333 tis/tih-ac/dc based note : a. cell contents shaded in red are defined as ?not supported?. required time t vac above v ih (ac) {blow v il (ac)} for valid transition [ps] ddr3-1066 ddr3-1333 reference tds(base) 25 30 v ih/l (ac) tdh(base) 100 65 v ih/l (dc) ? tds, ? tdh derating [ps] ac/dc based a dqs,dqs differential slew rate 4.0 v/ns 3.0 v/ns 2.0 v/ns 1.8 v/ns 1.6 v/ns 1.4v/ns 1.2v/ns 1.0v/ns ? tds ? tdh ? tds ? tdh ? tds ? tdh ? tds ? tdh ? tds ? tdh ? tds ? tdh ? tds ? tdh ? tds ? tdh ddr3 - 800/ 1066 dq slew rate v/ns 2.0885088508850---------- 1.55934593459346742 - - - - - - - - 1.0000000881616- - - - - - 0.9- - -2-4-2-4 6 414122220 - - - - 0.8 - - - - -6 -10 2 -2 10 6 18 14 26 24 - - 0.7 - - - - - - -3 -8 5 0 13 8 21 18 29 34 0.6 - - - - - - - - -1 -10 7 -2 15 8 23 24 0.5-----------11-16-2-6610 0.4-------------30-26-22-10 ddr3 - 1333/ 1600 dq slew rate v/ns 2.0755075507550---------- 1.55034503450345842 - - - - - - - - 1.0000000881616- - - - - - 0.9- - 0 -4 0 -4 8 4 16122420 - - - - 0.8 - - - - 0 -10 8 -2 16 6 24 14 32 24 - - 0.7 - - - - - - 8 -8 16 0 24 8 32 18 40 34 0.6 - - - - - - - - 15 -10 23 -2 31 8 39 24 0.5 - - - - - - - - - - 14 -16 22 -6 30 10 0.4------------7-2615-10 slew rate[v/ns] t vac [ps] ddr3-1066 t vac [ps] ddr3-1333 min max min max >2.0 75 - 175 - 2.0 57 - 170 - 1.5 50 - 167 - 1.0 38 - 163 - 0.9 34 - 162 - 0.8 29 - 161 - 0.7 22 - 159 - 0.6 13 - 155 - 0.5 0 - 155 - <0.5 0 - 150 - 44 of 50 ddr3 sdram rev. 1.23 july 2009 unbuffered dimm v ss ck ck tds tdh setup slew rate setup slew rate rising signal falling signal delta tf delta tr v ref (dc) - v il (ac)max delta tf = v ih (ac)min - v ref (dc) delta tr = v ddq v ih (ac) min v ih (dc) min v ref (dc) v il (dc) max v il (ac) max nominal slew rate nominal slew rate v ref to ac region v ref to ac region figure 13 - illustration of nominal slew rate and tvac for setup time tds (fo r dq with respect to strobe) and tis (for add/cmd with respect to clock). tis tih tds tdh tis tih tvac tvac note :clock and strobe are drawn on a different time scale. dqs dqs 45 of 50 ddr3 sdram rev. 1.23 july 2009 unbuffered dimm v ss ck ck hold slew rate hold slew rate falling signal rising signal delta tr delta tf v ref (dc) - v il (dc)max delta tr = v ih (dc)min - v ref (dc) delta tf = v ddq v ih (ac) min v ih (dc) min v ref (dc) v il (dc) max v il (ac) max nominal slew rate nominal slew rate dc to v ref region dc to v ref region figure 14 - illustration of nominal slew rate for hold time tdh (for dq with respect to strobe) and tih (for add/cmd with respect to clock). tis tih tis tih dc to v ref region note :clock and strobe are drawn on a different time scale. tds tdh tds tdh dqs dqs 46 of 50 ddr3 sdram rev. 1.23 july 2009 unbuffered dimm v ss setup slew rate setup slew rate rising signal falling signal delta tf delta tr tangent line[v ref (dc) - v il (ac)max] delta tf = tangent line[v ih (ac)min - v ref (dc)] delta tr = v ddq v ih (ac) min v ih (dc) min v ref (dc) v il (dc) max v il (ac) max tangent tangent v ref to ac region v ref to ac region line line nominal line nominal line figure 15 - illustration of tangent line for setup time tds (for dq with re spect to strobe) and tis (for add/cmd with respect to clock) ck ck tis tih tis tih tvac note :clock and strobe are drawn on a different time scale. tds tdh tds tdh dqs dqs 47 of 50 ddr3 sdram rev. 1.23 july 2009 unbuffered dimm v ss hold slew rate delta tf delta tr tangent line [ v ih (dc)min - v ref (dc) ] delta tf = v ddq v ih (ac) min v ih (dc) min v ref (dc) v il (dc) max v il (ac) max tangent tangent dc to v ref region dc to v ref region line line nominal line nominal line falling signal hold slew rate tangent line [ v ref (dc) - v il (dc)max ] delta tr = rising signal figure 16 - illustration of tangent line for hold time tdh (for dq with re spect to strobe) and tih (for add/cmd with respect to clock) ck ck tis tih tis tih note :clock and strobe are drawn on a different time scale. tds tdh tds tdh dqs dqs 48 of 50 ddr3 sdram rev. 1.23 july 2009 unbuffered dimm 18.0 physical dimensions 18.1 64mbx16 based 64mx64 module (1 rank) * note : tolerances on all dimensions 0.15 unless otherwise specified. units : millimeters 133.35 0.15 9.50 1.270 0.10 max 4.00 spd 128.95 (2) (4x)3.00 0.1 30.00 0.15 2.30 17.30 the used device is 64m x16 ddr3 sdram, fbga. ddr3 sdram part no : k4b1g1646d-hc ?? a b 47.00 71.00 2.50 1.00 0.2 0.15 2.50 0.20 detail b 5.00 detail a 1.500.10 0.80 0.05 3.80 2x 2.10 0.15 2.50 54.675 49 of 50 ddr3 sdram rev. 1.23 july 2009 unbuffered dimm 133.35 0.15 54.675 18.2 128mbx8 based 128mx64/x72 module (1 rank) * note : tolerances on all dimensions 0.15 unless otherwise specified. units : millimeters 9.50 1.270 0.10 128.95 (2) (4x)3.00 0.1 30.00 0.15 2.30 17.30 the used device is 128m x8 ddr3 sdram, fbga. ddr3 sdram part no : k4b1g0846d-hc ?? a b 47.00 71.00 2.50 1.00 0.2 0.15 2.50 0.20 detail b 5.00 detail a 1.500.10 0.80 0.05 3.80 2x 2.10 0.15 2.50 spd n/a (for x72) (for x64) ecc max 4.00 50 of 50 ddr3 sdram rev. 1.23 july 2009 unbuffered dimm 133.35 0.15 54.675 18.3 128mbx8 based 256mx64/x72 module (2 ranks) * note : tolerances on all dimensions 0.15 unless otherwise specified. units : millimeters 9.50 128.95 (2) (4x)3.00 0.1 30.00 0.15 2.30 17.30 the used device is 128m x8 ddr3 sdram, fbga. ddr3 sdram part no : k4b1g0846d-hc ?? a b 47.00 71.00 2.50 1.00 0.2 0.15 2.50 0.20 detail b 5.00 detail a 1.500.10 0.80 0.05 3.80 2x 2.10 0.15 2.50 spd n/a (for x72) (for x64) ecc 1.270 0.10 n/a (for x64) (for x72) ecc max 4.00 |
Price & Availability of M378B5673DZ1-CH9
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |